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- This comparison shows the changes necessary to convert path
/or1k/tags/nog_patch_68/or1ksim/cache
- from Rev 1462 to Rev 1765
- ↔ Reverse comparison
Rev 1462 → Rev 1765
/dcache_model.c
0,0 → 1,410
/* dcache_model.c -- data cache simulation |
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
|
/* Cache functions. |
At the moment this functions only simulate functionality of data |
caches and do not influence on fetche/decode/execute stages and timings. |
They are here only to verify performance of various cache configurations. |
*/ |
|
#include <stdio.h> |
#include <string.h> |
#include <errno.h> |
#include <stdarg.h> |
|
#include "config.h" |
|
#ifdef HAVE_INTTYPES_H |
#include <inttypes.h> |
#endif |
|
#include "port.h" |
#include "arch.h" |
#include "dcache_model.h" |
#include "abstract.h" |
#include "except.h" |
#include "opcode/or32.h" |
#include "spr_defs.h" |
#include "execute.h" |
#include "stats.h" |
#include "sprs.h" |
#include "sim-config.h" |
|
/* Data cache */ |
|
struct dc_set { |
struct { |
uint32_t line[MAX_DC_BLOCK_SIZE]; |
oraddr_t tagaddr; /* tag address */ |
int lru; /* least recently used */ |
} way[MAX_DC_WAYS]; |
} dc[MAX_DC_SETS]; |
|
void dc_info() |
{ |
if (!testsprbits(SPR_UPR, SPR_UPR_DCP)) { |
PRINTF("DCache not implemented. Set UPR[DCP].\n"); |
return; |
} |
|
PRINTF("Data cache %dKB: ", config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024); |
PRINTF("%d ways, %d sets, block size %d bytes\n", config.dc.nways, config.dc.nsets, config.dc.blocksize); |
} |
|
/* First check if data is already in the cache and if it is: |
- increment DC read hit stats, |
- set 'lru' at this way to config.dc.ustates - 1 and |
decrement 'lru' of other ways unless they have reached 0, |
and if not: |
- increment DC read miss stats |
- find lru way and entry and replace old tag with tag of the 'dataaddr' |
- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other |
ways unless they have reached 0 |
- refill cache line |
*/ |
|
uint32_t dc_simulate_read(oraddr_t dataaddr, int width) |
{ |
int set, way = -1; |
int i; |
oraddr_t tagaddr; |
uint32_t tmp; |
|
if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || |
(!testsprbits(SPR_SR, SPR_SR_DCE)) || |
data_ci) { |
if (width == 4) |
tmp = evalsim_mem32(dataaddr); |
else if (width == 2) |
tmp = evalsim_mem16(dataaddr); |
else if (width == 1) |
tmp = evalsim_mem8(dataaddr); |
|
if(!cur_area) { |
if (width == 4) |
printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n", |
dataaddr); |
else if (width == 2) |
printf("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n", |
dataaddr); |
else if (width == 1) |
printf("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n", |
dataaddr); |
except_handle(EXCEPT_BUSERR, cur_vadd); |
return 0; |
} else if (cur_area->log) |
fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", dataaddr, |
tmp); |
|
return tmp; |
} |
|
/* Which set to check out? */ |
set = (dataaddr / config.dc.blocksize) % config.dc.nsets; |
tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets; |
|
/* Scan all ways and try to find a matching way. */ |
for (i = 0; i < config.dc.nways; i++) |
if (dc[set].way[i].tagaddr == tagaddr) |
way = i; |
|
/* Did we find our cached data? */ |
if (way >= 0) { /* Yes, we did. */ |
dc_stats.readhit++; |
|
for (i = 0; i < config.dc.nways; i++) |
if (dc[set].way[i].lru > dc[set].way[way].lru) |
dc[set].way[i].lru--; |
dc[set].way[way].lru = config.dc.ustates - 1; |
runtime.sim.mem_cycles += config.dc.load_hitdelay; |
|
tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2]; |
if (width == 4) |
return tmp; |
else if (width == 2) { |
tmp = ((tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff); |
return tmp; |
} |
else if (width == 1) { |
tmp = ((tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff); |
return tmp; |
} |
} else { /* No, we didn't. */ |
int minlru = config.dc.ustates - 1; |
int minway = 0; |
|
dc_stats.readmiss++; |
|
for (i = 0; i < config.dc.nways; i++) { |
if (dc[set].way[i].lru < minlru) { |
minway = i; |
minlru = dc[set].way[i].lru; |
} |
} |
|
for (i = 0; i < (config.dc.blocksize); i += 4) { |
dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] = |
evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1))); |
if(!cur_area) { |
dc[set].way[minway].tagaddr = -1; |
dc[set].way[minway].lru = 0; |
printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n", |
dataaddr); |
except_handle(EXCEPT_BUSERR, cur_vadd); |
return 0; |
} else if (cur_area->log) |
fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", dataaddr, |
tmp); |
} |
|
dc[set].way[minway].tagaddr = tagaddr; |
for (i = 0; i < config.dc.nways; i++) |
if (dc[set].way[i].lru) |
dc[set].way[i].lru--; |
dc[set].way[minway].lru = config.dc.ustates - 1; |
runtime.sim.mem_cycles += config.dc.load_missdelay; |
|
tmp = dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2]; |
if (width == 4) |
return tmp; |
else if (width == 2) { |
tmp = (tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff; |
return tmp; |
} |
else if (width == 1) { |
tmp = (tmp >> (8 * (3 - (dataaddr & 3)))) & 0xff; |
return tmp; |
} |
} |
} |
|
/* First check if data is already in the cache and if it is: |
- increment DC write hit stats, |
- set 'lru' at this way to config.dc.ustates - 1 and |
decrement 'lru' of other ways unless they have reached 0, |
and if not: |
- increment DC write miss stats |
- find lru way and entry and replace old tag with tag of the 'dataaddr' |
- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other |
ways unless they have reached 0 |
*/ |
|
void dc_simulate_write(oraddr_t dataaddr, uint32_t data, int width) |
{ |
int set, way = -1; |
int i; |
oraddr_t tagaddr; |
uint32_t tmp; |
|
if (width == 4) |
setsim_mem32(dataaddr, data); |
else if (width == 2) |
setsim_mem16(dataaddr, data); |
else if (width == 1) |
setsim_mem8(dataaddr, data); |
|
if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || |
(!testsprbits(SPR_SR, SPR_SR_DCE)) || |
data_ci || |
(!cur_area)) |
return; |
|
/* Which set to check out? */ |
set = (dataaddr / config.dc.blocksize) % config.dc.nsets; |
tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets; |
|
/* Scan all ways and try to find a matching way. */ |
for (i = 0; i < config.dc.nways; i++) |
if (dc[set].way[i].tagaddr == tagaddr) |
way = i; |
|
/* Did we find our cached data? */ |
if (way >= 0) { /* Yes, we did. */ |
dc_stats.writehit++; |
|
for (i = 0; i < config.dc.nways; i++) |
if (dc[set].way[i].lru > dc[set].way[way].lru) |
dc[set].way[i].lru--; |
dc[set].way[way].lru = config.dc.ustates - 1; |
runtime.sim.mem_cycles += config.dc.store_hitdelay; |
|
tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2]; |
if (width == 4) |
tmp = data; |
else if (width == 2) { |
tmp &= 0xffff << ((dataaddr & 2) ? 16 : 0); |
tmp |= (data & 0xffff) << ((dataaddr & 2) ? 0 : 16); |
} |
else if (width == 1) { |
tmp &= ~(0xff << (8 * (3 - (dataaddr & 3)))); |
tmp |= (data & 0xff) << (8 * (3 - (dataaddr & 3))); |
} |
dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2] = tmp; |
} |
else { /* No, we didn't. */ |
int minlru = config.dc.ustates - 1; |
int minway = 0; |
|
dc_stats.writemiss++; |
|
for (i = 0; i < config.dc.nways; i++) |
if (dc[set].way[i].lru < minlru) |
minway = i; |
|
for (i = 0; i < (config.dc.blocksize); i += 4) { |
dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] = |
evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1))); |
if(!cur_area) { |
dc[set].way[minway].tagaddr = -1; |
dc[set].way[minway].lru = 0; |
return; |
} |
} |
|
dc[set].way[minway].tagaddr = tagaddr; |
for (i = 0; i < config.dc.nways; i++) |
if (dc[set].way[i].lru) |
dc[set].way[i].lru--; |
dc[set].way[minway].lru = config.dc.ustates - 1; |
runtime.sim.mem_cycles += config.dc.store_missdelay; |
} |
} |
|
/* First check if data is already in the cache and if it is: |
- invalidate block if way isn't locked |
otherwise don't do anything. |
*/ |
|
void dc_inv(oraddr_t dataaddr) |
{ |
int set, way = -1; |
int i; |
oraddr_t tagaddr; |
|
if (!testsprbits(SPR_UPR, SPR_UPR_DCP)) |
return; |
|
/* Which set to check out? */ |
set = (dataaddr / config.dc.blocksize) % config.dc.nsets; |
tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets; |
|
if (!testsprbits(SPR_SR, SPR_SR_DCE)) { |
for (i = 0; i < config.dc.nways; i++) { |
dc[set].way[i].tagaddr = -1; |
dc[set].way[i].lru = 0; |
} |
return; |
} |
/* Scan all ways and try to find a matching way. */ |
for (i = 0; i < config.dc.nways; i++) |
if (dc[set].way[i].tagaddr == tagaddr) |
way = i; |
|
/* Did we find our cached data? */ |
if (way >= 0) { /* Yes, we did. */ |
dc[set].way[way].tagaddr = -1; |
dc[set].way[way].lru = 0; |
} |
} |
|
/*-----------------------------------------------------[ DC configuration ]---*/ |
void dc_enabled(union param_val val, void *dat) |
{ |
config.dc.enabled = val.int_val; |
setsprbits (SPR_UPR, SPR_UPR_DCP, val.int_val ? 1 : 0); |
} |
|
void dc_nsets(union param_val val, void *dat) |
{ |
if (is_power2(val.int_val) && val.int_val <= MAX_DC_SETS){ |
config.dc.nsets = val.int_val; |
setsprbits (SPR_DCCFGR, SPR_DCCFGR_NCS, log2(val.int_val)); |
} |
else { |
char tmp[200]; |
sprintf (tmp, "value of power of two and lower or equal than %i expected.", MAX_DC_SETS); |
CONFIG_ERROR(tmp); |
} |
} |
|
void dc_nways(union param_val val, void *dat) |
{ |
if (is_power2(val.int_val) && val.int_val <= MAX_DC_WAYS){ |
config.dc.nways = val.int_val; |
setsprbits (SPR_DCCFGR, SPR_DCCFGR_NCW, log2(val.int_val)); |
} |
else{ |
char tmp[200]; |
sprintf (tmp, "value of power of two and lower or equal than %i expected.", |
MAX_DC_WAYS); |
CONFIG_ERROR(tmp); |
} |
} |
|
void dc_blocksize(union param_val val, void *dat) |
{ |
if (is_power2(val.int_val)) { |
config.dc.blocksize = val.int_val; |
setsprbits (SPR_DCCFGR, SPR_DCCFGR_CBS,log2(val.int_val)); |
} else |
CONFIG_ERROR("value of power of two expected."); |
} |
|
void dc_ustates(union param_val val, void *dat) |
{ |
if (val.int_val >= 2 && val.int_val <= 4) |
config.dc.ustates = val.int_val; |
else |
CONFIG_ERROR("invalid USTATE."); |
} |
|
void dc_load_missdelay(union param_val val, void *dat) |
{ |
config.dc.load_missdelay = val.int_val; |
} |
|
void dc_load_hitdelay(union param_val val, void *dat) |
{ |
config.dc.load_hitdelay = val.int_val; |
} |
|
void dc_store_missdelay(union param_val val, void *dat) |
{ |
config.dc.store_missdelay = val.int_val; |
} |
|
void dc_store_hitdelay(union param_val val, void *dat) |
{ |
config.dc.store_hitdelay = val.int_val; |
} |
|
void reg_dc_sec(void) |
{ |
struct config_section *sec = reg_config_sec("dc", NULL, NULL); |
|
reg_config_param(sec, "enabled", paramt_int, dc_enabled); |
reg_config_param(sec, "nsets", paramt_int, dc_nsets); |
reg_config_param(sec, "nways", paramt_int, dc_nways); |
reg_config_param(sec, "blocksize", paramt_int, dc_blocksize); |
reg_config_param(sec, "ustates", paramt_int, dc_ustates); |
reg_config_param(sec, "load_missdelay", paramt_int, dc_load_missdelay); |
reg_config_param(sec, "load_hitdelay", paramt_int, dc_load_hitdelay); |
reg_config_param(sec, "store_missdelay", paramt_int, dc_store_missdelay); |
reg_config_param(sec, "store_hitdelay", paramt_int, dc_store_hitdelay); |
} |
/icache_model.c
0,0 → 1,272
/* icache_model.c -- instruction cache simulation |
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
|
/* Cache functions. |
At the moment this functions only simulate functionality of instruction |
caches and do not influence on fetche/decode/execute stages and timings. |
They are here only to verify performance of various cache configurations. |
*/ |
|
#include <stdio.h> |
#include <string.h> |
#include <errno.h> |
#include <stdarg.h> |
|
#include "config.h" |
|
#ifdef HAVE_INTTYPES_H |
#include <inttypes.h> |
#endif |
|
#include "port.h" |
#include "arch.h" |
#include "abstract.h" |
#include "icache_model.h" |
#include "except.h" |
#include "opcode/or32.h" |
#include "spr_defs.h" |
#include "execute.h" |
#include "stats.h" |
#include "sim-config.h" |
#include "sprs.h" |
#include "sim-config.h" |
|
extern struct dev_memarea *cur_area; |
struct ic_set { |
struct { |
uint32_t line[MAX_IC_BLOCK_SIZE]; |
oraddr_t tagaddr; /* tag address */ |
int lru; /* least recently used */ |
} way[MAX_IC_WAYS]; |
} ic[MAX_IC_SETS]; |
|
void ic_info() |
{ |
if (!testsprbits(SPR_UPR, SPR_UPR_ICP)) { |
PRINTF("ICache not implemented. Set UPR[ICP].\n"); |
return; |
} |
|
PRINTF("Instruction cache %dKB: ", config.ic.nsets * config.ic.blocksize * config.ic.nways / 1024); |
PRINTF("%d ways, %d sets, block size %d bytes\n", config.ic.nways, config.ic.nsets, config.ic.blocksize); |
} |
|
/* First check if instruction is already in the cache and if it is: |
- increment IC read hit stats, |
- set 'lru' at this way to config.ic.ustates - 1 and |
decrement 'lru' of other ways unless they have reached 0, |
- read insn from the cache line |
and if not: |
- increment IC read miss stats |
- find lru way and entry and replace old tag with tag of the 'fetchaddr' |
- set 'lru' with config.ic.ustates - 1 and decrement 'lru' of other |
ways unless they have reached 0 |
- refill cache line |
*/ |
|
uint32_t ic_simulate_fetch(oraddr_t fetchaddr) |
{ |
int set, way = -1; |
int i; |
oraddr_t tagaddr; |
uint32_t tmp; |
|
/* ICache simulation enabled/disabled. */ |
if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)) || insn_ci) { |
tmp = evalsim_mem32(fetchaddr); |
if(!cur_area) { |
printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n", |
fetchaddr); |
except_handle(EXCEPT_BUSERR, cur_vadd); |
return 0; |
} else if (cur_area->log) |
fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", fetchaddr, |
tmp); |
return tmp; |
} |
|
/* Which set to check out? */ |
set = (fetchaddr / config.ic.blocksize) % config.ic.nsets; |
tagaddr = (fetchaddr / config.ic.blocksize) / config.ic.nsets; |
|
/* Scan all ways and try to find a matching way. */ |
for (i = 0; i < config.ic.nways; i++) |
if (ic[set].way[i].tagaddr == tagaddr) |
way = i; |
|
/* Did we find our cached instruction? */ |
if (way >= 0) { /* Yes, we did. */ |
ic_stats.readhit++; |
|
for (i = 0; i < config.ic.nways; i++) |
if (ic[set].way[i].lru > ic[set].way[way].lru) |
ic[set].way[i].lru--; |
ic[set].way[way].lru = config.ic.ustates - 1; |
runtime.sim.mem_cycles += config.ic.hitdelay; |
return (ic[set].way[way].line[(fetchaddr & (config.ic.blocksize - 1)) >> 2]); |
} |
else { /* No, we didn't. */ |
int minlru = config.ic.ustates - 1; |
int minway = 0; |
|
ic_stats.readmiss++; |
|
for (i = 0; i < config.ic.nways; i++) { |
if (ic[set].way[i].lru < minlru) { |
minway = i; |
minlru = ic[set].way[i].lru; |
} |
} |
|
for (i = 0; i < (config.ic.blocksize); i += 4) { |
tmp = ic[set].way[minway].line[((fetchaddr + i) & (config.ic.blocksize - 1)) >> 2] = |
evalsim_mem32((fetchaddr & ~(config.ic.blocksize - 1)) + ((fetchaddr + i) & (config.ic.blocksize - 1))); |
if(!cur_area) { |
ic[set].way[minway].tagaddr = -1; |
ic[set].way[minway].lru = 0; |
printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n", |
fetchaddr); |
except_handle(EXCEPT_BUSERR, cur_vadd); |
return 0; |
} else if (cur_area->log) |
fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", |
fetchaddr, tmp); |
} |
|
ic[set].way[minway].tagaddr = tagaddr; |
for (i = 0; i < config.ic.nways; i++) |
if (ic[set].way[i].lru) |
ic[set].way[i].lru--; |
ic[set].way[minway].lru = config.ic.ustates - 1; |
runtime.sim.mem_cycles += config.ic.missdelay; |
return (ic[set].way[minway].line[(fetchaddr & (config.ic.blocksize - 1)) >> 2]); |
} |
} |
|
/* First check if data is already in the cache and if it is: |
- invalidate block if way isn't locked |
otherwise don't do anything. |
*/ |
|
void ic_inv(oraddr_t dataaddr) |
{ |
int set, way = -1; |
int i; |
oraddr_t tagaddr; |
|
if (!testsprbits(SPR_UPR, SPR_UPR_ICP)) |
return; |
|
/* Which set to check out? */ |
set = (dataaddr / config.ic.blocksize) % config.ic.nsets; |
tagaddr = (dataaddr / config.ic.blocksize) / config.ic.nsets; |
|
if (!testsprbits(SPR_SR, SPR_SR_ICE)) { |
for (i = 0; i < config.ic.nways; i++) { |
ic[set].way[i].tagaddr = -1; |
ic[set].way[i].lru = 0; |
} |
return; |
} |
|
/* Scan all ways and try to find a matching way. */ |
for (i = 0; i < config.ic.nways; i++) |
if (ic[set].way[i].tagaddr == tagaddr) |
way = i; |
|
/* Did we find our cached data? */ |
if (way >= 0) { /* Yes, we did. */ |
ic[set].way[way].tagaddr = -1; |
ic[set].way[way].lru = 0; |
} |
} |
|
/*-----------------------------------------------------[ IC configuration ]---*/ |
void ic_enabled(union param_val val, void *dat) |
{ |
config.ic.enabled = val.int_val; |
setsprbits (SPR_UPR, SPR_UPR_ICP, val.int_val ? 1 : 0); |
} |
|
void ic_nsets(union param_val val, void *dat) |
{ |
if (is_power2(val.int_val) && val.int_val <= MAX_IC_SETS){ |
config.ic.nsets = val.int_val; |
setsprbits (SPR_ICCFGR, SPR_ICCFGR_NCS,log2(val.int_val)); |
} |
else { |
char tmp[200]; |
sprintf (tmp, "value of power of two and lower or equal than %i expected.", MAX_IC_SETS); |
CONFIG_ERROR(tmp); |
} |
} |
|
void ic_nways(union param_val val, void *dat) |
{ |
if (is_power2(val.int_val) && val.int_val <= MAX_IC_WAYS) { |
config.ic.nways = val.int_val; |
setsprbits (SPR_ICCFGR, SPR_ICCFGR_NCW, log2(val.int_val)); |
} |
else { |
char tmp[200]; |
sprintf (tmp, "value of power of two and lower or equal than %i expected.", |
MAX_IC_WAYS); |
CONFIG_ERROR(tmp); |
} |
} |
|
void ic_blocksize(union param_val val, void *dat) |
{ |
if (is_power2(val.int_val)){ |
config.ic.blocksize = val.int_val; |
setsprbits (SPR_ICCFGR, SPR_ICCFGR_CBS,log2(val.int_val)); |
} else |
CONFIG_ERROR("value of power of two expected."); |
} |
|
void ic_ustates(union param_val val, void *dat) |
{ |
if (val.int_val >= 2 && val.int_val <= 4) |
config.ic.ustates = val.int_val; |
else |
CONFIG_ERROR("invalid USTATE."); |
} |
|
void ic_missdelay(union param_val val, void *dat) |
{ |
config.ic.missdelay = val.int_val; |
} |
|
void ic_hitdelay(union param_val val, void *dat) |
{ |
config.ic.hitdelay = val.int_val; |
} |
|
void reg_ic_sec(void) |
{ |
struct config_section *sec = reg_config_sec("ic", NULL, NULL); |
|
reg_config_param(sec, "enabled", paramt_int, ic_enabled); |
reg_config_param(sec, "nsets", paramt_int, ic_nsets); |
reg_config_param(sec, "nways", paramt_int, ic_nways); |
reg_config_param(sec, "blocksize", paramt_int, ic_blocksize); |
reg_config_param(sec, "ustates", paramt_int, ic_ustates); |
reg_config_param(sec, "missdelay", paramt_int, ic_missdelay); |
reg_config_param(sec, "hitdelay", paramt_int, ic_hitdelay); |
} |
/icache_model.h
0,0 → 1,26
/* icache_model.h -- instruction cache header file |
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
|
#define MAX_IC_SETS 1024 |
#define MAX_IC_WAYS 32 |
#define MAX_IC_BLOCK_SIZE 4 /* In words */ |
|
uint32_t ic_simulate_fetch(oraddr_t fetchaddr); |
void ic_inv(oraddr_t dataaddr); |
void ic_info(); |
/dcache_model.h
0,0 → 1,27
/* dcache_model.h -- data cache header file |
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
|
#define MAX_DC_SETS 1024 |
#define MAX_DC_WAYS 32 |
#define MAX_DC_BLOCK_SIZE 4 /* In words */ |
|
uint32_t dc_simulate_read(oraddr_t dataaddr, int width); |
void dc_simulate_write(oraddr_t dataaddr, uint32_t data, int width); |
void dc_info(); |
void dc_inv(oraddr_t dataaddr); |
/Makefile.in
0,0 → 1,333
# Makefile.in generated by automake 1.6.3 from Makefile.am. |
# @configure_input@ |
|
# Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
# Free Software Foundation, Inc. |
# This Makefile.in is free software; the Free Software Foundation |
# gives unlimited permission to copy and/or distribute it, |
# with or without modifications, as long as this notice is preserved. |
|
# This program is distributed in the hope that it will be useful, |
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without |
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A |
# PARTICULAR PURPOSE. |
|
@SET_MAKE@ |
|
# Makefile -- Makefile for cpu architecture independent simulation |
# Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
# |
# This file is part of OpenRISC 1000 Architectural Simulator. |
# |
# This program is free software; you can redistribute it and/or modify |
# it under the terms of the GNU General Public License as published by |
# the Free Software Foundation; either version 2 of the License, or |
# (at your option) any later version. |
# |
# This program is distributed in the hope that it will be useful, |
# but WITHOUT ANY WARRANTY; without even the implied warranty of |
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
# GNU General Public License for more details. |
# |
# You should have received a copy of the GNU General Public License |
# along with this program; if not, write to the Free Software |
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
# |
SHELL = @SHELL@ |
|
srcdir = @srcdir@ |
top_srcdir = @top_srcdir@ |
VPATH = @srcdir@ |
prefix = @prefix@ |
exec_prefix = @exec_prefix@ |
|
bindir = @bindir@ |
sbindir = @sbindir@ |
libexecdir = @libexecdir@ |
datadir = @datadir@ |
sysconfdir = @sysconfdir@ |
sharedstatedir = @sharedstatedir@ |
localstatedir = @localstatedir@ |
libdir = @libdir@ |
infodir = @infodir@ |
mandir = @mandir@ |
includedir = @includedir@ |
oldincludedir = /usr/include |
pkgdatadir = $(datadir)/@PACKAGE@ |
pkglibdir = $(libdir)/@PACKAGE@ |
pkgincludedir = $(includedir)/@PACKAGE@ |
top_builddir = .. |
|
ACLOCAL = @ACLOCAL@ |
AUTOCONF = @AUTOCONF@ |
AUTOMAKE = @AUTOMAKE@ |
AUTOHEADER = @AUTOHEADER@ |
|
am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd |
INSTALL = @INSTALL@ |
INSTALL_PROGRAM = @INSTALL_PROGRAM@ |
INSTALL_DATA = @INSTALL_DATA@ |
install_sh_DATA = $(install_sh) -c -m 644 |
install_sh_PROGRAM = $(install_sh) -c |
install_sh_SCRIPT = $(install_sh) -c |
INSTALL_SCRIPT = @INSTALL_SCRIPT@ |
INSTALL_HEADER = $(INSTALL_DATA) |
transform = @program_transform_name@ |
NORMAL_INSTALL = : |
PRE_INSTALL = : |
POST_INSTALL = : |
NORMAL_UNINSTALL = : |
PRE_UNINSTALL = : |
POST_UNINSTALL = : |
build_alias = @build_alias@ |
build_triplet = @build@ |
host_alias = @host_alias@ |
host_triplet = @host@ |
target_alias = @target_alias@ |
target_triplet = @target@ |
|
EXEEXT = @EXEEXT@ |
OBJEXT = @OBJEXT@ |
PATH_SEPARATOR = @PATH_SEPARATOR@ |
AMTAR = @AMTAR@ |
AR = @AR@ |
ARFLAGS = @ARFLAGS@ |
AWK = @AWK@ |
BUILD_DIR = @BUILD_DIR@ |
CC = @CC@ |
CFLAGS = @CFLAGS@ |
CPU_ARCH = @CPU_ARCH@ |
DEPDIR = @DEPDIR@ |
INCLUDES = @INCLUDES@ |
INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ |
LOCAL_CFLAGS = @LOCAL_CFLAGS@ |
LOCAL_DEFS = @LOCAL_DEFS@ |
MAKE_SHELL = @MAKE_SHELL@ |
PACKAGE = @PACKAGE@ |
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STRIP = @STRIP@ |
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VERSION = @VERSION@ |
am__include = @am__include@ |
am__quote = @am__quote@ |
host = @host@ |
host_cpu = @host_cpu@ |
host_os = @host_os@ |
install_sh = @install_sh@ |
|
noinst_LIBRARIES = libcache.a |
libcache_a_SOURCES = dcache_model.c icache_model.c |
subdir = cache |
mkinstalldirs = $(SHELL) $(top_srcdir)/mkinstalldirs |
CONFIG_HEADER = $(top_builddir)/config.h |
CONFIG_CLEAN_FILES = |
LIBRARIES = $(noinst_LIBRARIES) |
|
libcache_a_AR = $(AR) cru |
libcache_a_LIBADD = |
am_libcache_a_OBJECTS = dcache_model.$(OBJEXT) icache_model.$(OBJEXT) |
libcache_a_OBJECTS = $(am_libcache_a_OBJECTS) |
|
DEFS = @DEFS@ |
DEFAULT_INCLUDES = -I. -I$(srcdir) -I$(top_builddir) |
CPPFLAGS = @CPPFLAGS@ |
LDFLAGS = @LDFLAGS@ |
LIBS = @LIBS@ |
depcomp = $(SHELL) $(top_srcdir)/depcomp |
am__depfiles_maybe = depfiles |
@AMDEP_TRUE@DEP_FILES = ./$(DEPDIR)/dcache_model.Po \ |
@AMDEP_TRUE@ ./$(DEPDIR)/icache_model.Po |
COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ |
$(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) |
CCLD = $(CC) |
LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@ |
DIST_SOURCES = $(libcache_a_SOURCES) |
DIST_COMMON = Makefile.am Makefile.in |
SOURCES = $(libcache_a_SOURCES) |
|
all: all-am |
|
.SUFFIXES: |
.SUFFIXES: .c .o .obj |
$(srcdir)/Makefile.in: Makefile.am $(top_srcdir)/configure.in $(ACLOCAL_M4) |
cd $(top_srcdir) && \ |
$(AUTOMAKE) --gnu cache/Makefile |
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status |
cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe) |
|
clean-noinstLIBRARIES: |
-test -z "$(noinst_LIBRARIES)" || rm -f $(noinst_LIBRARIES) |
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-rm -f libcache.a |
$(libcache_a_AR) libcache.a $(libcache_a_OBJECTS) $(libcache_a_LIBADD) |
$(RANLIB) libcache.a |
|
mostlyclean-compile: |
-rm -f *.$(OBJEXT) core *.core |
|
distclean-compile: |
-rm -f *.tab.c |
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dcache_model.Po@am__quote@ |
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/icache_model.Po@am__quote@ |
|
distclean-depend: |
-rm -rf ./$(DEPDIR) |
|
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@AMDEP_TRUE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ |
@AMDEP_TRUE@ depfile='$(DEPDIR)/$*.Po' tmpdepfile='$(DEPDIR)/$*.TPo' @AMDEPBACKSLASH@ |
@AMDEP_TRUE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ |
$(COMPILE) -c `test -f '$<' || echo '$(srcdir)/'`$< |
|
.c.obj: |
@AMDEP_TRUE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ |
@AMDEP_TRUE@ depfile='$(DEPDIR)/$*.Po' tmpdepfile='$(DEPDIR)/$*.TPo' @AMDEPBACKSLASH@ |
@AMDEP_TRUE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ |
$(COMPILE) -c `cygpath -w $<` |
CCDEPMODE = @CCDEPMODE@ |
uninstall-info-am: |
|
ETAGS = etags |
ETAGSFLAGS = |
|
tags: TAGS |
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ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES) |
list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ |
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if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ |
done | \ |
$(AWK) ' { files[$$0] = 1; } \ |
END { for (i in files) print i; }'`; \ |
mkid -fID $$unique |
|
TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \ |
$(TAGS_FILES) $(LISP) |
tags=; \ |
here=`pwd`; \ |
list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ |
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$$tags $$unique |
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&& gtags -i $(GTAGS_ARGS) $$here |
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-rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH |
DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) |
|
top_distdir = .. |
distdir = $(top_distdir)/$(PACKAGE)-$(VERSION) |
|
distdir: $(DISTFILES) |
@list='$(DISTFILES)'; for file in $$list; do \ |
if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ |
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if test "$$dir" != "$$file" && test "$$dir" != "."; then \ |
dir="/$$dir"; \ |
$(mkinstalldirs) "$(distdir)$$dir"; \ |
else \ |
dir=''; \ |
fi; \ |
if test -d $$d/$$file; then \ |
if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ |
cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \ |
fi; \ |
cp -pR $$d/$$file $(distdir)$$dir || exit 1; \ |
else \ |
test -f $(distdir)/$$file \ |
|| cp -p $$d/$$file $(distdir)/$$file \ |
|| exit 1; \ |
fi; \ |
done |
check-am: all-am |
check: check-am |
all-am: Makefile $(LIBRARIES) |
|
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|
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|
# Tell versions [3.59,3.63) of GNU make to not export all variables. |
# Otherwise a system limit (for SysV at least) may be exceeded. |
.NOEXPORT: |
/Makefile.am
0,0 → 1,23
# Makefile -- Makefile for cpu architecture independent simulation |
# Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
# |
# This file is part of OpenRISC 1000 Architectural Simulator. |
# |
# This program is free software; you can redistribute it and/or modify |
# it under the terms of the GNU General Public License as published by |
# the Free Software Foundation; either version 2 of the License, or |
# (at your option) any later version. |
# |
# This program is distributed in the hope that it will be useful, |
# but WITHOUT ANY WARRANTY; without even the implied warranty of |
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
# GNU General Public License for more details. |
# |
# You should have received a copy of the GNU General Public License |
# along with this program; if not, write to the Free Software |
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
# |
|
noinst_LIBRARIES = libcache.a |
libcache_a_SOURCES = dcache_model.c icache_model.c |
|
.
Property changes :
Added: svn:ignore
## -0,0 +1,2 ##
+Makefile
+.deps