URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

Compare Revisions

This comparison shows the changes necessary to convert path
```
/or1k/tags/rel-0-3-0-rc1/or1ksim/cpu/or32
```
from Rev 1749 to Rev 1765
↔ Reverse comparison
Compare Path: Rev

With Path: Rev

Rev 1749 → Rev 1765

/Makefile.in

0,0 → 1,799

/rec-i386.h

0,0 → 1,28

/op-2t.h

0,0 → 1,62

/op-mftspr-op.h

0,0 → 1,82

/op-i386.h

0,0 → 1,46

/sched-i386.h

0,0 → 1,40

/dyn32-defs.h

0,0 → 1,123

/or32.c

0,0 → 1,1305

/op-support.c

0,0 → 1,114

/op-lwhb-op.h

0,0 → 1,38

/op-comp-op.h

0,0 → 1,50

/op-support.h

0,0 → 1,28

/op-swhb-op.h

0,0 → 1,62

/dyn-rec.c

0,0 → 1,2448

/execute.c

0,0 → 1,1169

/op-arith-op.h

0,0 → 1,33

/op-1t.h

0,0 → 1,38

/dyn-rec.h

0,0 → 1,61

/op-3t.h

0,0 → 1,135

/op-ff1-op.h

0,0 → 1,35

/op-t-reg-mov-op.h

0,0 → 1,330

/dyngen-i386.c

0,0 → 1,75

/simpl32-defs.h

0,0 → 1,95

/op-1t-op.h

0,0 → 1,75

/op-2t-op.h

0,0 → 1,44

/insnset.c

0,0 → 1,614

insnset.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: op-3t-op.h =================================================================== --- op-3t-op.h (nonexistent) +++ op-3t-op.h (revision 1765) @@ -0,0 +1,25 @@ +/* op-3t-op.h -- Micro operations useing three temporaries + Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +__or_dynop void glue(op_cmov, T)(void) +{ + T0 = env->sprs[SPR_SR] & SPR_SR_F ? T1 : T2; +} + Index: op-extend-op.h =================================================================== --- op-extend-op.h (nonexistent) +++ op-extend-op.h (revision 1765) @@ -0,0 +1,27 @@ +/* op-extend-op.h -- Micro operations template for sign extention operations + Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +void glue(glue(op_, EXT_NAME), T)(void) +{ + register EXT_TYPE x; + x = T1; + T0 = EXT_CAST x; +} + Index: common-i386.h =================================================================== --- common-i386.h (nonexistent) +++ common-i386.h (revision 1765) @@ -0,0 +1,63 @@ +/* common-i386.h -- Assembler routines used in rec_i386.h and op_i386.h + Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* This is needed because we can't move an mmx register to a general purpose + * register. */ +static union { + struct { + uint32_t low32; + uint32_t high32; + } val3232; + uint64_t val64; +} useless_x86; + +/* Sets the PC with a specified value */ +static void set_pc(oraddr_t pc) +{ + /* I could just use pc as a memory argument, but if I do that then gcc may put + * the value of pc onto the stack, in which case gcc would also shift the + * stack twice, which would result in two add 4, %esp instructions and a + * mov %eax, *%esp, which would not only be slow but it would take up more + * space. */ + asm("movq %%mm0, %0\n" + "\tmovl %2, %1\n" + "\tmovq %3, %%mm0" + : "=m" (useless_x86.val64), + "=m" (useless_x86.val3232.high32) + : "r" (pc), + "m" (useless_x86.val64)); +} + +/* Returns the current value of the pc */ +static oraddr_t get_pc(void) +{ + asm("movq %%mm0, %0" : "=m" (useless_x86.val64)); + return useless_x86.val3232.high32; +} + +/* Updates the runtime.sim.cycles counter */ +static void upd_sim_cycles(void) +{ + asm volatile ("movq %%mm0, %0\n" : "=m" (useless_x86.val64)); + runtime.sim.cycles += scheduler.job_queue->time - useless_x86.val3232.low32; + scheduler.job_queue->time = useless_x86.val3232.low32; + cpu_state.pc = useless_x86.val3232.high32; +} + Index: Makefile.am =================================================================== --- Makefile.am (nonexistent) +++ Makefile.am (revision 1765) @@ -0,0 +1,201 @@ +# Makefile -- Makefile for OR32 dependent simulation +# +# Copyright (C) 1999 Damjan Lampret, lampret@opencores.org +# Copyright (C) 2008 Embecosm Limited +# +# Contributor Jeremy Bennett +# +# This file is part of OpenRISC 1000 Architectural Simulator. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along +# with this program. If not, see . + + +if DYNAMIC_EXECUTION + +noinst_LTLIBRARIES = libarch.la libop.la + +noinst_PROGRAMS = dyngen + +dyngen_SOURCES = dyngen.c \ + dyngen-i386.c \ + dyngen-elf.c \ + common-i386.h \ + dyn32-defs.h \ + dyngen.h \ + dyn-rec.h \ + i386-regs.h \ + op-arith-op.h \ + op-comp-op.h \ + op-extend-op.h \ + op-ff1-op.h \ + op-i386.h \ + op-lwhb-op.h \ + op-mac-op.h \ + op-mftspr-op.h \ + op-support.h \ + op-swhb-op.h \ + op-t-reg-mov-op.h \ + rec-i386.h \ + sched-i386.h \ + simpl32-defs.h +dyngen_CFLAGS = $(AM_CFLAGS) + +libarch_la_SOURCES = execute.c \ + or32.c \ + op.c \ + dyn-rec.c \ + op-support.c \ + common-i386.h \ + dyn32-defs.h \ + dyngen.h \ + dyn-rec.h \ + i386-regs.h \ + op-arith-op.h \ + op-comp-op.h \ + op-extend-op.h \ + op-ff1-op.h \ + op-i386.h \ + op-lwhb-op.h \ + op-mac-op.h \ + op-mftspr-op.h \ + op-support.h \ + op-swhb-op.h \ + op-t-reg-mov-op.h \ + rec-i386.h \ + sched-i386.h \ + simpl32-defs.h + +nodist_libarch_la_SOURCES = gen-ops.h \ + gen-ops.c \ + gen-ops-gen.c \ + gen-ops-rel.c + +BUILT_SOURCES = gen-ops.h \ + gen-ops.c \ + gen-ops-gen.c \ + gen-ops-rel.c + +libop_la_SOURCES = op.c \ + op-t-reg-mov-op.h \ + op-i386.h op-arith-op.h \ + op-comp-op.h \ + op-extend-op.h \ + op-mac-op.h \ + op-mftspr-op.h \ + op-lwhb-op.h \ + op-swhb-op.h + +libop_la_CFLAGS = -Wall -fomit-frame-pointer -fno-reorder-blocks -O2 + +gen-ops.h gen-ops.c gen-ops-gen.c gen-ops-rel.c: dyngen$(EXEEXT) op.lo + ./dyngen$(EXEEXT) op.lo gen-ops.c gen-ops-gen.c gen-ops-rel.c gen-ops.h + +else + +noinst_LTLIBRARIES = libarch.la + +if GENERATE_NEEDED + +EXTRA_DIST = insnset.c + +libarch_la_SOURCES = execute.c \ + or32.c \ + common-i386.h \ + dyn32-defs.h \ + dyngen.h \ + dyn-rec.h \ + i386-regs.h \ + op-arith-op.h \ + op-comp-op.h \ + op-extend-op.h \ + op-ff1-op.h \ + op-i386.h \ + op-lwhb-op.h \ + op-mac-op.h \ + op-mftspr-op.h \ + op-support.h \ + op-swhb-op.h \ + op-t-reg-mov-op.h \ + rec-i386.h \ + sched-i386.h \ + simpl32-defs.h + +BUILT_SOURCES = execgen.c + +noinst_PROGRAMS = generate$(EXEEXT) + +generate_SOURCES = or32.c \ + generate.c \ + common-i386.h \ + dyn32-defs.h \ + dyngen.h \ + dyn-rec.h \ + i386-regs.h \ + op-arith-op.h \ + op-comp-op.h \ + op-extend-op.h \ + op-ff1-op.h \ + op-i386.h \ + op-lwhb-op.h \ + op-mac-op.h \ + op-mftspr-op.h \ + op-support.h \ + op-swhb-op.h \ + op-t-reg-mov-op.h \ + rec-i386.h \ + sched-i386.h \ + simpl32-defs.h + +generate_CFLAGS = $(AM_CFLAGS) + +execgen.c: generate$(EXEEXT) insnset.c + ./generate$(EXEEXT) $(srcdir)/insnset.c execgen.c + +else + +libarch_la_SOURCES = execute.c \ + insnset.c \ + or32.c \ + common-i386.h \ + dyn32-defs.h \ + dyngen.h \ + dyn-rec.h \ + i386-regs.h \ + op-arith-op.h \ + op-comp-op.h \ + op-extend-op.h \ + op-ff1-op.h \ + op-i386.h \ + op-lwhb-op.h \ + op-mac-op.h \ + op-mftspr-op.h \ + op-support.h \ + op-swhb-op.h \ + op-t-reg-mov-op.h \ + rec-i386.h \ + sched-i386.h \ + simpl32-defs.h + +endif +endif + +# If the simulator was first built without --enable-simple and then with it, +# then also remove these two files + +CLEANFILES = execgen.c \ + generate \ + gen-ops.c \ + gen-ops.h \ + gen-ops-rel.c \ + gen-ops-gen.c Index: dyngen-elf.c =================================================================== --- dyngen-elf.c (nonexistent) +++ dyngen-elf.c (revision 1765) @@ -0,0 +1,359 @@ +/* dyngen-elf.c -- Elf parser for dyngen + Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include +#include +#include +#include + +#include + +#include "dyngen.h" + +struct elf_obj { + Elf32_Ehdr e_hdr; + Elf32_Shdr *e_shdrs; + void **e_sections; + Elf32_Sym *e_syms; /* The symbol table in the elf file */ + unsigned int e_sym_num; /* The number of symbols */ + unsigned int e_sym_str_tab; /* The string-table associated with symbols */ + Elf32_Rel *e_rels; + unsigned int e_rel_num; /* The number of relocations (in e_rel) */ + unsigned int e_rel_sym; + unsigned int e_rel_sec; /* The section to modify */ + Elf32_Rela *e_relas; + unsigned int e_rela_num; /* The number of relocations (in e_rela) */ + unsigned int e_rela_sym; + unsigned int e_rela_sec; /* The section to modify */ +}; + +void *elf_open_obj(const char *file) +{ + struct elf_obj *obj; + FILE *f; + int i; + + if(!(obj = malloc(sizeof(struct elf_obj)))) { + fprintf(stderr, "OOM\n"); + return NULL; + } + + if(!(f = fopen(file, "r"))) { + free(obj); + return NULL; + } + + fread(&obj->e_hdr, sizeof(Elf32_Ehdr), 1, f); + + /* Do some sanity checks */ + if((obj->e_hdr.e_ident[EI_MAG0] != ELFMAG0) || + (obj->e_hdr.e_ident[EI_MAG1] != ELFMAG1) || + (obj->e_hdr.e_ident[EI_MAG2] != ELFMAG2) || + (obj->e_hdr.e_ident[EI_MAG3] != ELFMAG3)) { + fprintf(stderr, "%s is not an elf file!\n", file); + goto error_load; + } + + if(obj->e_hdr.e_ident[EI_CLASS] == ELFCLASSNONE) { + fprintf(stderr, "Invalid class in ELF header\n"); + goto error_load; + } + + if(obj->e_hdr.e_ident[EI_DATA] == ELFDATANONE) { + fprintf(stderr, "Invalid data format in ELF header\n"); + goto error_load; + } + + /* FIXME: Swap data as necessary */ + + if((obj->e_hdr.e_ident[EI_VERSION] != 1) || + (obj->e_hdr.e_version != 1)) { + fprintf(stderr, "Unexpected elf version found: %i (%li)\n", + obj->e_hdr.e_ident[EI_VERSION], obj->e_hdr.e_version); + goto error_load; + } + + if(obj->e_hdr.e_type != ET_REL) { + fprintf(stderr, "Appears that we did not receive a object file\n"); + goto error_load; + } + + if(obj->e_hdr.e_phoff) { + fprintf(stderr, "What am I supposed to do with a program header??\n"); + goto error_load; + } + + if(obj->e_hdr.e_ehsize != sizeof(Elf32_Ehdr)) { + fprintf(stderr, "Unknown size of elf header\n"); + goto error_load; + } + + if(!obj->e_hdr.e_shoff || !obj->e_hdr.e_shnum) { + fprintf(stderr, "The elf file contains no sections!\n"); + goto error_load; + } + + if(obj->e_hdr.e_shentsize != sizeof(Elf32_Shdr)) { + fprintf(stderr, "Unknown section header size %i\n", obj->e_hdr.e_shentsize); + goto error_load; + } + + /* Load the section headers */ + if(!(obj->e_shdrs = malloc(obj->e_hdr.e_shentsize * obj->e_hdr.e_shnum))){ + fprintf(stderr, "OOM\n"); + goto error_load; + } + + fseek(f, obj->e_hdr.e_shoff, SEEK_SET); + fread(obj->e_shdrs, obj->e_hdr.e_shentsize, obj->e_hdr.e_shnum, f); + + /* FIXME: swap data */ + + /* Load the sections */ + if(!(obj->e_sections = calloc(obj->e_hdr.e_shnum, sizeof(void *)))) { + fprintf(stderr, "OOM\n"); + free(obj->e_shdrs); + goto error_load; + } + + for(i = 0; i < obj->e_hdr.e_shnum; i++) { + if(obj->e_shdrs[i].sh_type == SHT_NOBITS) + continue; + if(!(obj->e_sections[i] = malloc(obj->e_shdrs[i].sh_size))) { + fprintf(stderr, "OOM\n"); + goto post_sec_error_load; + } + fseek(f, obj->e_shdrs[i].sh_offset, SEEK_SET); + fread(obj->e_sections[i], obj->e_shdrs[i].sh_size, 1, f); + } + + obj->e_rels = NULL; + obj->e_syms = NULL; + obj->e_relas = NULL; + + /* Find the symbol table and relocation table(s) */ + for(i = 0; i < obj->e_hdr.e_shnum; i++) { + switch(obj->e_shdrs[i].sh_type) { + case SHT_SYMTAB: + if(obj->e_syms) { + fprintf(stderr, "ELF file has more than one symbol table\n"); + goto post_sec_error_load; + } + if(obj->e_shdrs[i].sh_entsize != sizeof(Elf32_Sym)) { + fprintf(stderr, "ELF symbol table entry size is unknown\n"); + goto post_sec_error_load; + } + if((obj->e_shdrs[i].sh_size % obj->e_shdrs[i].sh_entsize)) { + fprintf(stderr, "Symbol table's length is not a multiple of sizeof(Elf32_Sym\n"); + goto post_sec_error_load; + } + obj->e_syms = obj->e_sections[i]; + obj->e_sym_num = obj->e_shdrs[i].sh_size / obj->e_shdrs[i].sh_entsize; + obj->e_sym_str_tab = obj->e_shdrs[i].sh_link; + break; + case SHT_REL: + if(obj->e_rels) { + fprintf(stderr, "ELF file has more than one relocation table\n"); + goto post_sec_error_load; + } + if(obj->e_shdrs[i].sh_entsize != sizeof(Elf32_Rel)) { + fprintf(stderr, "ELF relocation table entry size is unknown\n"); + goto post_sec_error_load; + } + if((obj->e_shdrs[i].sh_size % obj->e_shdrs[i].sh_entsize)) { + fprintf(stderr, "Relocation table's length is not a multiple of sizeof(Elf32_Rel\n"); + goto post_sec_error_load; + } + obj->e_rels = obj->e_sections[i]; + obj->e_rel_sec = obj->e_shdrs[i].sh_info; + obj->e_rel_sym = obj->e_shdrs[i].sh_link; + obj->e_rel_num = obj->e_shdrs[i].sh_size / obj->e_shdrs[i].sh_entsize; + break; + case SHT_RELA: + if(obj->e_relas) { + fprintf(stderr, "ELF file has more than one a-relocation table\n"); + goto post_sec_error_load; + } + if(obj->e_shdrs[i].sh_entsize != sizeof(Elf32_Rela)) { + fprintf(stderr, "ELF a-relocation table entry size is unknown\n"); + goto post_sec_error_load; + } + if((obj->e_shdrs[i].sh_size % obj->e_shdrs[i].sh_entsize)) { + fprintf(stderr, "Relocation table's length is not a multiple of sizeof(Elf32_Rela)\n"); + goto post_sec_error_load; + } + obj->e_relas = obj->e_sections[i]; + obj->e_rela_sec = obj->e_shdrs[i].sh_info; + obj->e_rela_sym = obj->e_shdrs[i].sh_link; + obj->e_rela_num = obj->e_shdrs[i].sh_size / obj->e_shdrs[i].sh_entsize; + break; + } + } + + fclose(f); + return obj; + +post_sec_error_load: + for(i = 0; i < obj->e_hdr.e_shnum; i++) { + if(obj->e_sections[i]) + free(obj->e_sections[i]); + } + free(obj->e_sections); + free(obj->e_shdrs); +error_load: + free(obj); + fclose(f); + return NULL; +} + +void elf_close_obj(void *e_obj) +{ + struct elf_obj *obj = e_obj; + int i; + + for(i = 0; i < obj->e_hdr.e_shnum; i++) { + if(obj->e_sections[i]) + free(obj->e_sections[i]); + } + free(obj->e_sections); + free(obj->e_shdrs); + free(obj); +} + +static Elf32_Sym *elf_find_func(struct elf_obj *obj, unsigned int func) +{ + int i, j; + Elf32_Sym *cur; + + for(i = 0, j = 0, cur = obj->e_syms; i < obj->e_sym_num; i++, cur++) { + if(ELF32_ST_BIND(cur->st_info) != STB_GLOBAL) + continue; + if(ELF32_ST_TYPE(cur->st_info) != STT_FUNC) + continue; + if(j == func) + return cur; + j++; + } + return NULL; +} + +char *elf_get_func_name(void *e_obj, unsigned int func) +{ + struct elf_obj *obj = e_obj; + Elf32_Sym *func_sym = elf_find_func(obj, func); + + if(func_sym) + return obj->e_sections[obj->e_sym_str_tab] + func_sym->st_name; + + return NULL; +} + +unsigned int elf_get_func_len(void *e_obj, unsigned int func) +{ + struct elf_obj *obj = e_obj; + Elf32_Sym *func_sym = elf_find_func(obj, func); + + if(func_sym) + return func_sym->st_size; + return 0; +} + +void *elf_get_func_start(void *e_obj, unsigned int func) +{ + struct elf_obj *obj = e_obj; + Elf32_Sym *func_sym = elf_find_func(obj, func); + + if(!func_sym) + return NULL; + + if(func_sym->st_shndx == SHN_COMMON) { + fprintf(stderr, "Don't know how to handle SHN_COMMON section header\n"); + return NULL; + } + + return obj->e_sections[func_sym->st_shndx] + func_sym->st_value; +} + +static char *elf_get_sym_name(struct elf_obj *obj, unsigned int sym) +{ + char *name; + + name = obj->e_sections[obj->e_sym_str_tab]; + name += obj->e_syms[sym].st_name; + + return name; +} + +int elf_get_func_reloc(void *e_obj, unsigned int func, unsigned int relocn, + struct reloc *reloc) +{ + struct elf_obj *obj = e_obj; + Elf32_Sym *func_sym = elf_find_func(obj, func); + Elf32_Rel *cur; + Elf32_Rela *cura; + int i, j; + +/* + if(obj->e_rel_sec != func_sym->st_shndx) { + fprintf(stderr, "Don't know what to do: Function does not have a relocation table\n"); + return 0; + } +*/ + + for(i = 0, j = 0, cur = obj->e_rels; i < obj->e_rel_num; i++, cur++) { + if((cur->r_offset - func_sym->st_value) > func_sym->st_size) + continue; + if(relocn == j) { + reloc->name = elf_get_sym_name(obj, ELF32_R_SYM(cur->r_info)); + reloc->func_offset = cur->r_offset - func_sym->st_value; + reloc->type = ELF32_R_TYPE(cur->r_info); + /* FIXME: Byte-swap */ + reloc->addend = *(uint32_t *)(obj->e_sections[obj->e_rel_sec] + cur->r_offset); + return 1; + } + j++; + } + + if(!obj->e_relas) + return 0; + + for(i = 0, cura = obj->e_relas; i < obj->e_rela_num; i++, cura++) { + if((cura->r_offset - func_sym->st_value) > func_sym->st_size) + continue; + if(relocn == j) { + reloc->name = elf_get_sym_name(obj, ELF32_R_SYM(cur->r_info)); + reloc->func_offset = cura->r_offset - func_sym->st_value; + reloc->type = ELF32_R_TYPE(cur->r_info); + reloc->addend = cura->r_addend; + return 1; + } + j++; + } + + return 0; +} + +const struct bff bffs = { + elf_open_obj, + elf_close_obj, + elf_get_func_name, + elf_get_func_start, + elf_get_func_len, + elf_get_func_reloc }; Index: generate.c =================================================================== --- generate.c (nonexistent) +++ generate.c (revision 1765) @@ -0,0 +1,412 @@ +/* generate.c -- generates file execgen.c from instruction set + + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org + Copyright (C) 2008 Embecosm Limited + + Contributor Jeremy Bennett + + This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along + with this program. If not, see . */ + +/* This program is commented throughout in a fashion suitable for processing + with Doxygen. */ + + +/* Autoconf and/or portability configuration */ +#include "config.h" +#include "port.h" + +/* System includes */ +#include +#include +#include + +/* Package includes */ +#include "opcode/or32.h" + +static char *in_file; +static char *out_file; + +/* Whether this instruction stores something in register */ +static int write_to_reg; + +static int out_lines = 0; + +static int shift_fprintf(int level, FILE *f, const char *fmt, ...) +{ + va_list ap; + int i; + + va_start(ap, fmt); + for(i = 0; i < level; i++) + fprintf(f, " "); + + i = vfprintf(f, fmt, ap); + va_end(ap); + + out_lines++; + return i + (level * 2); +} + +/* Generates a execute sequence for one instruction */ +int output_function (FILE *fo, const char *func_name, int level) +{ + FILE *fi; + int olevel; + int line_num = 0; + + if ((fi = fopen (in_file, "rt")) == NULL) { + printf("could not open file\n"); + return 1; + } + + while (!feof (fi)) { + char line[10000], *str = line; + fgets (str, sizeof (line), fi); + line[sizeof (line) - 1] = 0; + line_num++; + if (strncmp (str, "INSTRUCTION (", 13) == 0) { + char *s; + str += 13; + while (isspace (*str)) str++; + s = str; + while (*s && *s != ')') s++; + *s = 0; + while (isspace(*(s - 1))) s--; + *s = 0; + if (strcmp (str, func_name) == 0) { + olevel = 1; + str += strlen (str) + 1; + while (isspace (*str)) str++; + s = str; + while (*s && *s != '\n' && *s != '\r') s++; + *s = 0; + while (isspace(*(s - 1))) s--; + *s = 0; + /*shift_fprintf (level, fo, "#line %i \"%s\"\n", line_num, in_file);*/ + shift_fprintf (level, fo, "%s", str); + shift_fprintf (level, fo, " /* \"%s\" */\n", func_name); + do { + fgets (line, sizeof (line), fi); + line[sizeof(line) - 1] = 0; + for (str = line; *str; str++) { + if (*str == '{') olevel++; + else if (*str == '}') olevel--; + } + shift_fprintf (level, fo, "%s", line); + } while (olevel); + fclose(fi); + /*shift_fprintf (level, fo, "#line %i \"%s\"\n", out_lines, out_file);*/ + return 0; + } + } + } + shift_fprintf (level, fo, "%s ();\n", func_name); + + fclose(fi); + return 0; +} + +/* Parses operands. */ + +static int +gen_eval_operands (FILE *fo, int insn_index, int level) +{ + struct insn_op_struct *opd = op_start[insn_index]; + int i; + int num_ops; + int nbits = 0; + int set_param = 0; + int dis = 0; + int sbit; + int dis_op = -1; + + write_to_reg = 0; + + shift_fprintf (level, fo, "uorreg_t "); + + /* Count number of operands */ + for (i = 0, num_ops = 0;; i++) { + if (!(opd[i].type & OPTYPE_OP)) + continue; + if (opd[i].type & OPTYPE_DIS) + continue; + if (num_ops) + fprintf(fo, ", "); + fprintf(fo, "%c", 'a' + num_ops); + num_ops++; + if (opd[i].type & OPTYPE_LAST) + break; + } + + fprintf (fo, ";\n"); + + shift_fprintf (level, fo, "/* Number of operands: %i */\n", num_ops); + + i = 0; + num_ops = 0; + do { +/* + printf("opd[%i].type = %c\n", i, opd->type & OPTYPE_LAST ? '1' : '0'); printf("opd[%i].type = %c\n", i, opd->type & OPTYPE_OP ? '1' : '0'); + printf("opd[%i].type = %c\n", i, opd->type & OPTYPE_REG ? '1' : '0'); + printf("opd[%i].type = %c\n", i, opd->type & OPTYPE_SIG ? '1' : '0'); + printf("opd[%i].type = %c\n", i, opd->type & OPTYPE_DIS ? '1' : '0'); + printf("opd[%i].type = %i\n", i, opd->type & OPTYPE_SHR); + printf("opd[%i].type = %i\n", i, (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR); + printf("opd[%i].data = %i\n", i, opd->data); +*/ + + if (!nbits) + shift_fprintf (level, fo, "%c = (insn >> %i) & 0x%x;\n", 'a' + num_ops, + opd->type & OPTYPE_SHR, (1 << opd->data) - 1); + else + shift_fprintf (level, fo, "%c |= ((insn >> %i) & 0x%x) << %i;\n", + 'a' + num_ops, opd->type & OPTYPE_SHR, + (1 << opd->data) - 1, nbits); + + nbits += opd->data; + + if ((opd->type & OPTYPE_DIS) && (opd->type & OPTYPE_OP)) { + sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR; + if (opd->type & OPTYPE_SIG) + shift_fprintf (level, fo, "if(%c & 0x%08x) %c |= 0x%x;\n", + 'a' + num_ops, 1 << sbit, 'a' + num_ops, + 0xffffffff << sbit); + opd++; + shift_fprintf (level, fo, "*(orreg_t *)&%c += (orreg_t)cpu_state.reg[(insn >> %i) & 0x%x];\n", + 'a' + num_ops, opd->type & OPTYPE_SHR, + (1 << opd->data) - 1); + dis = 1; + dis_op = num_ops; + } + + if (opd->type & OPTYPE_OP) { + sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR; + if (opd->type & OPTYPE_SIG) + shift_fprintf (level, fo, "if(%c & 0x%08x) %c |= 0x%x;\n", + 'a' + num_ops, 1 << sbit, 'a' + num_ops, + 0xffffffff << sbit); + if ((opd->type & OPTYPE_REG) && !dis) { + if(!i) { + shift_fprintf (level, fo, "#define SET_PARAM0(val) cpu_state.reg[a] = val\n"); + set_param = 1; + } + shift_fprintf (level, fo, "#define PARAM%i cpu_state.reg[%c]\n", num_ops, + 'a' + num_ops); + if(opd->type & OPTYPE_DST) + write_to_reg = 1; + } else { + shift_fprintf (level, fo, "#define PARAM%i %c\n", num_ops, + 'a' + num_ops); + } + num_ops++; + nbits = 0; + dis = 0; + } + + if ((opd->type & OPTYPE_LAST)) + break; + opd++; + i++; + } while (1); + + output_function (fo, or32_opcodes[insn_index].function_name, level); + + if (set_param) + shift_fprintf (level, fo, "#undef SET_PARAM\n"); + + for (i = 0; i < num_ops; i++) + shift_fprintf (level, fo, "#undef PARAM%i\n", i); + + return dis_op; +} + +/* Generates decode and execute for one instruction instance */ +static int output_call (FILE *fo, int index, int level) +{ + int dis_op = -1; + + /*printf ("%i:%s\n", index, insn_name (index));*/ + + shift_fprintf (level++, fo, "{\n"); + + if (index >= 0) + dis_op = gen_eval_operands (fo, index, level); + + if (index < 0) output_function (fo, "l_invalid", level); + + fprintf (fo, "\n"); + + shift_fprintf (level++, fo, "if (do_stats) {\n"); + + if (dis_op >= 0) + shift_fprintf (level, fo, "cpu_state.insn_ea = %c;\n", 'a' + dis_op); + + shift_fprintf (level, fo, "current->insn_index = %i; /* \"%s\" */\n", index, + insn_name (index)); + + shift_fprintf (level, fo, "analysis(current);\n"); + shift_fprintf (--level, fo, "}\n"); + + if (write_to_reg) + shift_fprintf (level, fo, "cpu_state.reg[0] = 0; /* Repair in case we changed it */\n"); + shift_fprintf (--level, fo, "}\n"); + return 0; +} + +/* Generates .c file header */ +static int generate_header (FILE *fo) +{ + fprintf (fo, "/* execgen.c -- Automatically generated decoder\n"); + fprintf (fo, "\n"); + fprintf (fo, " Copyright (C) 1999 Damjan Lampret, lampret@opencores.org\n"); + fprintf (fo, " Copyright (C) 2008 Embecosm Limited\n"); + fprintf (fo, "\n"); + fprintf (fo, " Contributor Jeremy Bennett \n"); + fprintf (fo, "\n"); + fprintf (fo, " This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.\n"); + fprintf (fo, "\n"); + fprintf (fo, " This program is free software; you can redistribute it and/or modify it\n"); + fprintf (fo, " under the terms of the GNU General Public License as published by the Free\n"); + fprintf (fo, " Software Foundation; either version 3 of the License, or (at your option)\n"); + fprintf (fo, " any later version.\n"); + fprintf (fo, "\n"); + fprintf (fo, " This program is distributed in the hope that it will be useful, but WITHOUT\n"); + fprintf (fo, " ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n"); + fprintf (fo, " FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n"); + fprintf (fo, " more details.\n"); + fprintf (fo, "\n"); + fprintf (fo, " You should have received a copy of the GNU General Public License along\n"); + fprintf (fo, " with this program. If not, see . */\n"); + fprintf (fo, "\n"); + fprintf (fo, "/* This program is commented throughout in a fashion suitable for processing\n"); + fprintf (fo, " with Doxygen. */\n"); + fprintf (fo, "\n"); + + fprintf (fo, "/* This file was automatically generated by generate (see\n"); + fprintf (fo, " cpu/or32/generate.c) */\n\n"); + fprintf (fo, "static void decode_execute (struct iqueue_entry *current)\n{\n"); + fprintf (fo, " uint32_t insn = current->insn;\n"); + out_lines = 5; + return 0; +} + +/* Generates .c file footer */ +static int generate_footer (FILE *fo) +{ + fprintf (fo, "}\n"); + return 0; +} + +/* Decodes all instructions and generates code for that. This function + is similar to insn_decode, except it decodes all instructions. */ +static int generate_body (FILE *fo, unsigned long *a, unsigned long cur_mask, int level) +{ + unsigned long shift = *a; + unsigned long mask; + int i; + int prev_inv = 0; + + if (!(*a & LEAF_FLAG)) { + shift = *a++; + mask = *a++; + shift_fprintf (level, fo, "switch((insn >> %i) & 0x%x) {\n", shift, + mask); + for (i = 0; i <= mask; i++, a++) { + if (!*a) { + shift_fprintf (level, fo, "case 0x%x:\n", i); + prev_inv = 1; + } else { + if(prev_inv) { + shift_fprintf (++level, fo, "/* Invalid instruction(s) */\n"); + shift_fprintf (level--, fo, "break;\n"); + } + shift_fprintf (level, fo, "case 0x%x:\n", i); + generate_body (fo, automata + *a, cur_mask | (mask << shift), ++level); + shift_fprintf (level--, fo, "break;\n"); + prev_inv = 0; + } + } + if (prev_inv) { + shift_fprintf (++level, fo, "/* Invalid instruction(s) */\n"); + shift_fprintf (level--, fo, "break;\n"); + } + shift_fprintf (level, fo, "}\n"); + } else { + i = *a & ~LEAF_FLAG; + + /* Final check - do we have direct match? + (based on or32_opcodes this should be the only possibility, + but in case of invalid/missing instruction we must perform a check) */ + + if (ti[i].insn_mask != cur_mask) { + shift_fprintf (level, fo, "/* Not unique: real mask %08lx and current mask %08lx differ - do final check */\n", ti[i].insn_mask, cur_mask); + shift_fprintf (level++, fo, "if((insn & 0x%x) == 0x%x) {\n", + ti[i].insn_mask, ti[i].insn); + } + shift_fprintf (level, fo, "/* Instruction: %s */\n", or32_opcodes[i].name); + + output_call (fo, i, level); + + if (ti[i].insn_mask != cur_mask) { + shift_fprintf (--level, fo, "} else {\n"); + shift_fprintf (++level, fo, "/* Invalid insn */\n"); + output_call (fo, -1, level); + shift_fprintf (--level, fo, "}\n"); + } + } + return 0; +} + +/* Main function; it takes two parameters: + input_file(possibly insnset.c) output_file(possibly execgen.c)*/ +int main (int argc, char *argv[]) +{ + FILE *fo; + + if (argc != 3) { + fprintf (stderr, "USAGE: generate input_file(possibly insnset.c) output_file(possibly execgen.c)\n"); + exit (-1); + } + + in_file = argv[1]; + out_file = argv[2]; + if (!(fo = fopen (argv[2], "wt+"))) { + fprintf (stderr, "Cannot create '%s'.\n", argv[2]); + exit (1); + } + + build_automata (); + if (generate_header (fo)) { + fprintf (stderr, "generate_header\n"); + return 1; + } + + if (generate_body (fo, automata, 0, 1)) { + fprintf (stderr, "generate_body\n"); + return 1; + } + + if (generate_footer (fo)) { + fprintf (stderr, "generate_footer\n"); + return 1; + } + + fclose (fo); + destruct_automata (); + return 0; +} +

generate.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: i386-regs.h =================================================================== --- i386-regs.h (nonexistent) +++ i386-regs.h (revision 1765) @@ -0,0 +1,26 @@ +/* i386_regs.h -- Register definitions for i386 + Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#define CPU_STATE_REG "ebp" +#define T0_REG "ebx" +#define T1_REG "esi" +#define T2_REG "edi" + +#define NUM_T_REGS 3 Index: op-mac-op.h =================================================================== --- op-mac-op.h (nonexistent) +++ op-mac-op.h (revision 1765) @@ -0,0 +1,30 @@ +/* op-mac-op.h -- Micro operations template for mac operations + Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +__or_dynop void glue(glue(op_, OP_NAME), T)(void) +{ + int64_t temp = env->sprs[SPR_MACLO] | ((int64_t)env->sprs[SPR_MACHI] << 32); + + temp OP (int64_t)T0 * (int64_t)T1; + + env->sprs[SPR_MACLO] = temp & 0xffffffff; + env->sprs[SPR_MACHI] = temp >> 32; +} + Index: op.c =================================================================== --- op.c (nonexistent) +++ op.c (revision 1765) @@ -0,0 +1,971 @@ +/* op.c -- Micro operations for the recompiler + Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include +#include +#include + +#include "config.h" + +#ifdef HAVE_INTTYPES_H +#include +#endif + +#include "port.h" +#include "arch.h" +#include "spr_defs.h" +#include "opcode/or32.h" +#include "sim-config.h" +#include "except.h" +#include "abstract.h" +#include "execute.h" +#include "sprs.h" +#include "sched.h" +#include "immu.h" + +#include "op_support.h" + +#include "i386_regs.h" + +#include "dyn_rec.h" + +register struct cpu_state *env asm(CPU_STATE_REG); + +#include "op_i386.h" + +/* + * WARNING: Before going of and wildly editing everything in this file remember + * the following about its contents: + * 1) The `functions' don't EVER return. In otherwords haveing return state- + * ments _anywere_ in this file is likely not to work. This is because + * dyngen just strips away the ret from the end of the function and just uses + * the function `body'. If a ret statement is executed _anyware_ inside the + * dynamicly generated code, then it is undefined were we shall jump to. + * 2) Because of 1), try not to have overly complicated functions. In too + * complicated functions, gcc may decide to generate premature `exits'. This + * is what passing the -fno-reorder-blocks command line switch to gcc helps + * with. This is ofcourse not desired and is rather flaky as we don't (and + * can't) control the kind of code that gcc generates: It may work for one + * and break for another. The less branches there are the less likely it is + * that a premature return shall occur. + * 3) If gcc decides that it is going to be a basterd then it will optimise a + * very simple condition (if/switch) with a premature exit. But gcc can't + * fuck ME over! Just stick a FORCE_RET; at the END of the offending + * function. + * 4) All operations must start with `op_'. dyngen ignores all other functions. + * 5) Local variables are depriciated: They hinder performance. + * 6) Function calls are expensive as the stack has to be shifted (twice). + */ + +/*#define __or_dynop __attribute__((noreturn))*/ +#define __or_dynop + +/* Temporaries to hold the (simulated) registers in */ +register uint32_t t0 asm(T0_REG); +register uint32_t t1 asm(T1_REG); +register uint32_t t2 asm(T2_REG); + +#define OP_PARAM1 ((uorreg_t)(&__op_param1)) +#define OP_PARAM2 ((uorreg_t)(&__op_param2)) +#define OP_PARAM3 ((uorreg_t)(&__op_param3)) + +extern uorreg_t __op_param1; +extern uorreg_t __op_param2; +extern uorreg_t __op_param3; + + +static inline void save_t_bound(oraddr_t pc) +{ + int reg; + + pc = (pc & immu_state->page_offset_mask) / 4; + reg = env->curr_page->ts_bound[pc]; + + if(reg & 0x1f) + env->reg[reg & 0x1f] = t0; + + if((reg >> 5) & 0x1f) + env->reg[(reg >> 5) & 0x1f] = t1; + + if((reg >> 10) & 0x1f) + env->reg[(reg >> 10) & 0x1f] = t2; +} + +void do_sched_wrap(void) +{ + env->pc += 4; + //runtime.cpu.instructions++; + runtime.sim.cycles -= env->cycles_dec; + scheduler.job_queue->time += env->cycles_dec; + if(scheduler.job_queue->time <= 0) { + save_t_bound(env->pc - 4); + do_scheduler(); + } +} + +/* do_scheduler wrapper for instructions that are in the delay slot */ +void do_sched_wrap_delay(void) +{ + /* FIXME: Can't this be eliminated? */ + env->pc += 4; + //runtime.cpu.instructions++; + runtime.sim.cycles -= env->cycles_dec; + scheduler.job_queue->time += env->cycles_dec; + if(scheduler.job_queue->time <= 0) + do_scheduler(); +} + +void enter_dyn_code(oraddr_t addr, struct dyn_page *dp) +{ + uint16_t reg = 0; + uint32_t t0_reg = t0, t1_reg = t1, t2_reg = t2; + struct cpu_state *cpu_reg = env; + + addr &= immu_state->page_offset_mask; + addr >>= 2; + + if(addr) + reg = dp->ts_bound[addr - 1]; + + t0 = cpu_state.reg[reg & 0x1f]; + t1 = cpu_state.reg[(reg >> 5) & 0x1f]; + + /* Don't we all love gcc? For some heavenly reason gcc 3.2 _knows_ that if I + * don't put a condition around the assignment of t2, _all_ the assignments to + * t{0,1,2} are useless and not needed. I'm pleasently happy that gcc is so + * bright, but on the other hand, t{0,1,2} are globals (!) how can you assume + * that the value of a global won't be used in a function further up or + * further down the stack?? */ + if(addr) + t2 = cpu_state.reg[(reg >> 10) & 0x1f]; + + env = &cpu_state; + + ((gen_code_ent *)dp->locs)[addr](); + t0 = t0_reg; + t1 = t1_reg; + t2 = t2_reg; + env = (struct cpu_state *)cpu_reg; +} + +__or_dynop void op_set_pc_pc_delay(void) +{ + env->sprs[SPR_PPC] = env->pc; + /* pc_delay is pulled back 4 since imediatly after this is run, the scheduler + * runs which also increments it by 4 */ + env->pc = env->pc_delay - 4; +} + +__or_dynop void op_set_pc_delay_imm(void) +{ + env->pc_delay = env->pc + (orreg_t)OP_PARAM1; + env->delay_insn = 1; +} + +__or_dynop void op_set_pc_delay_pc(void) +{ + env->pc_delay = env->pc; + env->delay_insn = 1; +} + +__or_dynop void op_clear_pc_delay(void) +{ + env->pc_delay = 0; + env->delay_insn = 1; +} + +__or_dynop void op_do_jump_delay(void) +{ + env->pc = env->pc_delay; +} + +__or_dynop void op_clear_delay_insn(void) +{ + env->delay_insn = 0; +} + +__or_dynop void op_set_delay_insn(void) +{ + env->delay_insn = 1; +} + +__or_dynop void op_check_delay_slot(void) +{ + if(!env->delay_insn) + OP_JUMP(OP_PARAM1); +} + +__or_dynop void op_jmp_imm(void) +{ + OP_JUMP(OP_PARAM1); +} + +__or_dynop void op_set_flag(void) +{ + env->sprs[SPR_SR] |= SPR_SR_F; +} + +__or_dynop void op_clear_flag(void) +{ + env->sprs[SPR_SR] &= ~SPR_SR_F; +} + +/* Used for the l.bf instruction. Therefore if the flag is not set, jump over + * all the jumping stuff */ +__or_dynop void op_check_flag(void) +{ + if(!(env->sprs[SPR_SR] & SPR_SR_F)) { + SPEEDY_CALL(do_sched_wrap); + OP_JUMP(OP_PARAM1); + } +} + +/* Used for l.bf if the delay slot instruction is on another page */ +__or_dynop void op_check_flag_delay(void) +{ + if(env->sprs[SPR_SR] & SPR_SR_F) { + env->delay_insn = 1; + env->pc_delay = env->pc + (orreg_t)OP_PARAM1; + } +} + +/* Used for the l.bnf instruction. Therefore if the flag is set, jump over all + * the jumping stuff */ +__or_dynop void op_check_not_flag(void) +{ + if(env->sprs[SPR_SR] & SPR_SR_F) { + SPEEDY_CALL(do_sched_wrap); + OP_JUMP(OP_PARAM1); + } +} + +/* Used for l.bnf if the delay slot instruction is on another page */ +__or_dynop void op_check_not_flag_delay(void) +{ + if(!(env->sprs[SPR_SR] & SPR_SR_F)) { + env->delay_insn = 1; + env->pc_delay = env->pc + (orreg_t)OP_PARAM1; + } +} + +__or_dynop void op_add_pc(void) +{ + env->pc += OP_PARAM1; +} + +__or_dynop void op_nop_exit(void) +{ + op_support_nop_exit(); + FORCE_RET; +} + +__or_dynop void op_nop_reset(void) +{ + op_support_nop_reset(); + FORCE_RET; +} + +__or_dynop void op_nop_printf(void) +{ + op_support_nop_printf(); + FORCE_RET; +} + +__or_dynop void op_nop_report(void) +{ + op_support_nop_report(); + FORCE_RET; +} + +__or_dynop void op_nop_report_imm(void) +{ + op_support_nop_report_imm(OP_PARAM1); +} + +/* FIXME: Create another 2 sched functions that to the actual analysis call + * instead of bloating the recompiled code with this */ +__or_dynop void op_analysis(void) +{ + SPEEDY_CALL(op_support_analysis); +} + +__or_dynop void op_move_gpr1_pc_delay(void) +{ + env->pc_delay = env->reg[1]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr2_pc_delay(void) +{ + env->pc_delay = env->reg[2]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr3_pc_delay(void) +{ + env->pc_delay = env->reg[3]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr4_pc_delay(void) +{ + env->pc_delay = env->reg[4]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr5_pc_delay(void) +{ + env->pc_delay = env->reg[5]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr6_pc_delay(void) +{ + env->pc_delay = env->reg[6]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr7_pc_delay(void) +{ + env->pc_delay = env->reg[7]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr8_pc_delay(void) +{ + env->pc_delay = env->reg[8]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr9_pc_delay(void) +{ + env->pc_delay = env->reg[9]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr10_pc_delay(void) +{ + env->pc_delay = env->reg[10]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr11_pc_delay(void) +{ + env->pc_delay = env->reg[11]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr12_pc_delay(void) +{ + env->pc_delay = env->reg[12]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr13_pc_delay(void) +{ + env->pc_delay = env->reg[13]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr14_pc_delay(void) +{ + env->pc_delay = env->reg[14]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr15_pc_delay(void) +{ + env->pc_delay = env->reg[15]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr16_pc_delay(void) +{ + env->pc_delay = env->reg[16]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr17_pc_delay(void) +{ + env->pc_delay = env->reg[17]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr18_pc_delay(void) +{ + env->pc_delay = env->reg[18]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr19_pc_delay(void) +{ + env->pc_delay = env->reg[19]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr20_pc_delay(void) +{ + env->pc_delay = env->reg[20]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr21_pc_delay(void) +{ + env->pc_delay = env->reg[21]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr22_pc_delay(void) +{ + env->pc_delay = env->reg[22]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr23_pc_delay(void) +{ + env->pc_delay = env->reg[23]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr24_pc_delay(void) +{ + env->pc_delay = env->reg[24]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr25_pc_delay(void) +{ + env->pc_delay = env->reg[25]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr26_pc_delay(void) +{ + env->pc_delay = env->reg[26]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr27_pc_delay(void) +{ + env->pc_delay = env->reg[27]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr28_pc_delay(void) +{ + env->pc_delay = env->reg[28]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr29_pc_delay(void) +{ + env->pc_delay = env->reg[29]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr30_pc_delay(void) +{ + env->pc_delay = env->reg[30]; + env->delay_insn = 1; +} + +__or_dynop void op_move_gpr31_pc_delay(void) +{ + env->pc_delay = env->reg[31]; + env->delay_insn = 1; +} + +#define OP_FILE "op_1t_op.h" +#include "op_1t.h" +#undef OP_FILE + +#define OP_FILE "op_2t_op.h" +#include "op_2t.h" +#undef OP_FILE + +#define OP_FILE "op_3t_op.h" +#include "op_3t.h" +#undef OP_FILE + +#define OP_FILE "op_arith_op.h" +#define OP_EXTRA + +#define OP / +#define OP_CAST(x) (orreg_t)(x) +#define OP_NAME div +#include "op_3t.h" +#undef OP_NAME +#undef OP_CAST +#undef OP + +#define OP / +#define OP_CAST(x) (x) +#define OP_NAME divu +#include "op_3t.h" +#undef OP_NAME +#undef OP_CAST +#undef OP + +#define OP * +#define OP_CAST(x) (x) +#define OP_NAME mulu +#include "op_3t.h" +#undef OP_NAME +#undef OP_CAST +#undef OP + +#define OP - +#define OP_CAST(x) (orreg_t)(x) +#define OP_NAME sub +#include "op_3t.h" +#undef OP_NAME +#undef OP_CAST +#undef OP + +#undef OP_EXTRA + +#define OP_EXTRA + ((env->sprs[SPR_SR] & SPR_SR_CY) >> 10) +#define OP + +#define OP_CAST(x) (orreg_t)(x) +#define OP_NAME addc +#include "op_3t.h" +#include "op_2t.h" +#undef OP_NAME +#undef OP_CAST +#undef OP + +#undef OP_EXTRA +#define OP_EXTRA + +#define OP + +#define OP_CAST(x) (orreg_t)(x) +#define OP_NAME add +#include "op_3t.h" +#include "op_2t.h" +#undef OP_NAME +#undef OP_CAST +#undef OP + +#define OP & +#define OP_CAST(x) (x) +#define OP_NAME and +#include "op_3t.h" +#include "op_2t.h" +#undef OP_NAME +#undef OP_CAST +#undef OP + +#define OP * +#define OP_CAST(x) (orreg_t)(x) +#define OP_NAME mul +#include "op_3t.h" +#include "op_2t.h" +#undef OP_NAME +#undef OP_CAST +#undef OP + +#define OP | +#define OP_CAST(x) (x) +#define OP_NAME or +#include "op_3t.h" +#include "op_2t.h" +#undef OP_NAME +#undef OP_CAST +#undef OP + +#define OP << +#define OP_CAST(x) (x) +#define OP_NAME sll +#include "op_3t.h" +#include "op_2t.h" +#undef OP_NAME +#undef OP_CAST +#undef OP + +#define OP >> +#define OP_CAST(x) (orreg_t)(x) +#define OP_NAME sra +#include "op_3t.h" +#include "op_2t.h" +#undef OP_NAME +#undef OP_CAST +#undef OP + +#define OP >> +#define OP_CAST(x) (x) +#define OP_NAME srl +#include "op_3t.h" +#include "op_2t.h" +#undef OP_NAME +#undef OP_CAST +#undef OP + +#define OP ^ +#define OP_CAST(x) (x) +#define OP_NAME xor +#include "op_3t.h" +#include "op_2t.h" +#undef OP_NAME +#undef OP_CAST +#undef OP + +#undef OP_EXTRA +#undef OP_FILE + +#define OP_FILE "op_extend_op.h" + +#define EXT_NAME extbs +#define EXT_TYPE int8_t +#define EXT_CAST (orreg_t) +#include "op_2t.h" +#undef EXT_CAST +#undef EXT_TYPE +#undef EXT_NAME + +#define EXT_NAME extbz +#define EXT_TYPE uint8_t +#define EXT_CAST (uorreg_t) +#include "op_2t.h" +#undef EXT_CAST +#undef EXT_TYPE +#undef EXT_NAME + +#define EXT_NAME exths +#define EXT_TYPE int16_t +#define EXT_CAST (orreg_t) +#include "op_2t.h" +#undef EXT_CAST +#undef EXT_TYPE +#undef EXT_NAME + +#define EXT_NAME exthz +#define EXT_TYPE uint16_t +#define EXT_CAST (uorreg_t) +#include "op_2t.h" +#undef EXT_CAST +#undef EXT_TYPE +#undef EXT_NAME + +#undef OP_FILE + +#define OP_FILE "op_comp_op.h" + +#define COMP == +#define COMP_NAME sfeq +#define COMP_CAST(x) (x) +#include "op_2t.h" +#include "op_1t.h" +#undef COMP_CAST +#undef COMP_NAME +#undef COMP + +#define COMP != +#define COMP_NAME sfne +#define COMP_CAST(x) (x) +#include "op_2t.h" +#include "op_1t.h" +#undef COMP_CAST +#undef COMP_NAME +#undef COMP + +#define COMP > +#define COMP_NAME sfgtu +#define COMP_CAST(x) (x) +#include "op_2t.h" +#include "op_1t.h" +#undef COMP_CAST +#undef COMP_NAME +#undef COMP + +#define COMP >= +#define COMP_NAME sfgeu +#define COMP_CAST(x) (x) +#include "op_2t.h" +#include "op_1t.h" +#undef COMP_CAST +#undef COMP_NAME +#undef COMP + +#define COMP < +#define COMP_NAME sfltu +#define COMP_CAST(x) (x) +#include "op_2t.h" +#include "op_1t.h" +#undef COMP_CAST +#undef COMP_NAME +#undef COMP + +#define COMP <= +#define COMP_NAME sfleu +#define COMP_CAST(x) (x) +#include "op_2t.h" +#include "op_1t.h" +#undef COMP_CAST +#undef COMP_NAME +#undef COMP + +#define COMP > +#define COMP_NAME sfgts +#define COMP_CAST(x) (orreg_t)(x) +#include "op_2t.h" +#include "op_1t.h" +#undef COMP_CAST +#undef COMP_NAME +#undef COMP + +#define COMP >= +#define COMP_NAME sfges +#define COMP_CAST(x) (orreg_t)(x) +#include "op_2t.h" +#include "op_1t.h" +#undef COMP_CAST +#undef COMP_NAME +#undef COMP + +#define COMP < +#define COMP_NAME sflts +#define COMP_CAST(x) (orreg_t)(x) +#include "op_2t.h" +#include "op_1t.h" +#undef COMP_CAST +#undef COMP_NAME +#undef COMP + +#define COMP <= +#define COMP_NAME sfles +#define COMP_CAST(x) (orreg_t)(x) +#include "op_2t.h" +#include "op_1t.h" +#undef COMP_CAST +#undef COMP_NAME +#undef COMP + +#undef OP_FILE + +#define OP_FILE "op_t_reg_mov_op.h" +#include "op_1t.h" +#undef OP_FILE + +#define OP_FILE "op_mftspr_op.h" +#include "op_1t.h" +#include "op_2t.h" +#undef OP_FILE +#include "op_mftspr_op.h" + +#define OP_FILE "op_mac_op.h" + +#define OP += +#define OP_NAME mac +#include "op_2t.h" +#undef OP_NAME +#undef OP + +#define OP -= +#define OP_NAME msb +#include "op_2t.h" +#undef OP_NAME +#undef OP + +#undef OP_FILE + +#define OP_FILE "op_lwhb_op.h" + +#define LS_OP_NAME lbz +#define LS_OP_CAST +#define LS_OP_FUNC eval_mem8 +#include "op_2t.h" +#include "op_1t.h" +#undef LS_OP_FUNC +#undef LS_OP_CAST +#undef LS_OP_NAME + +#define LS_OP_NAME lbs +#define LS_OP_CAST (int8_t) +#define LS_OP_FUNC eval_mem8 +#include "op_2t.h" +#include "op_1t.h" +#undef LS_OP_FUNC +#undef LS_OP_CAST +#undef LS_OP_NAME + +#define LS_OP_NAME lhz +#define LS_OP_CAST +#define LS_OP_FUNC eval_mem16 +#include "op_2t.h" +#include "op_1t.h" +#undef LS_OP_FUNC +#undef LS_OP_CAST +#undef LS_OP_NAME + +#define LS_OP_NAME lhs +#define LS_OP_CAST (int16_t) +#define LS_OP_FUNC eval_mem16 +#include "op_2t.h" +#include "op_1t.h" +#undef LS_OP_FUNC +#undef LS_OP_CAST +#undef LS_OP_NAME + +#define LS_OP_NAME lwz +#define LS_OP_CAST +#define LS_OP_FUNC eval_mem32 +#include "op_2t.h" +#include "op_1t.h" +#undef LS_OP_FUNC +#undef LS_OP_CAST +#undef LS_OP_NAME + +#define LS_OP_NAME lws +#define LS_OP_CAST (int32_t) +#define LS_OP_FUNC eval_mem32 +#include "op_2t.h" +#include "op_1t.h" +#undef LS_OP_FUNC +#undef LS_OP_CAST +#undef LS_OP_NAME + +#undef OP_FILE + +#define OP_FILE "op_swhb_op.h" + +#define S_OP_NAME sb +#define S_FUNC set_mem8 +#include "op_swhb_op.h" +#include "op_2t.h" +#include "op_1t.h" +#undef S_FUNC +#undef S_OP_NAME + +#define S_OP_NAME sh +#define S_FUNC set_mem16 +#include "op_swhb_op.h" +#include "op_2t.h" +#include "op_1t.h" +#undef S_FUNC +#undef S_OP_NAME + +#define S_OP_NAME sw +#define S_FUNC set_mem32 +#include "op_swhb_op.h" +#include "op_2t.h" +#include "op_1t.h" +#undef S_FUNC +#undef S_OP_NAME + +__or_dynop void op_join_mem_cycles(void) +{ + runtime.sim.cycles += runtime.sim.mem_cycles; + scheduler.job_queue->time -= runtime.sim.mem_cycles; + runtime.sim.mem_cycles = 0; +} + +__or_dynop void op_store_link_addr_gpr(void) +{ + env->reg[LINK_REGNO] = env->pc + 8; +} + +__or_dynop void op_prep_rfe(void) +{ + env->sprs[SPR_SR] = env->sprs[SPR_ESR_BASE] | SPR_SR_FO; + env->sprs[SPR_PPC] = env->pc; + env->pc = env->sprs[SPR_EPCR_BASE] - 4; +} + +static inline void prep_except(oraddr_t epcr_base) +{ + env->sprs[SPR_EPCR_BASE] = epcr_base; + + env->sprs[SPR_ESR_BASE] = env->sprs[SPR_SR]; + + /* Address translation is always disabled when starting exception. */ + env->sprs[SPR_SR] &= ~SPR_SR_DME; + env->sprs[SPR_SR] &= ~SPR_SR_IME; + + env->sprs[SPR_SR] &= ~SPR_SR_OVE; /* Disable overflow flag exception. */ + + env->sprs[SPR_SR] |= SPR_SR_SM; /* SUPV mode */ + env->sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE); /* Disable interrupts. */ +} + +/* Before the code in op_{sys,trap}{,_delay} gets run, the scheduler runs. + * Therefore the pc will point to the instruction after the l.sys or l.trap + * instruction */ +__or_dynop void op_prep_sys_delay(void) +{ + env->delay_insn = 0; + prep_except(env->pc - 4); + env->pc = EXCEPT_SYSCALL - 4; +} + +__or_dynop void op_prep_sys(void) +{ + prep_except(env->pc + 4); + env->pc = EXCEPT_SYSCALL - 4; +} + +__or_dynop void op_prep_trap_delay(void) +{ + env->delay_insn = 0; + prep_except(env->pc - 4); + env->pc = EXCEPT_TRAP - 4; +} + +__or_dynop void op_prep_trap(void) +{ + prep_except(env->pc); + env->pc = EXCEPT_TRAP - 4; +} + +/* FIXME: This `instruction' should be split up like the l.trap and l.sys + * instructions are done */ +__or_dynop void op_illegal_delay(void) +{ + env->delay_insn = 0; + env->sprs[SPR_EEAR_BASE] = env->pc - 4; + env->pc = EXCEPT_ILLEGAL - 4; +} + +__or_dynop void op_illegal(void) +{ + env->sprs[SPR_EEAR_BASE] = env->pc; + env->pc = EXCEPT_ILLEGAL; +} + +__or_dynop void op_do_sched(void) +{ + SPEEDY_CALL(do_sched_wrap); +} + +__or_dynop void op_do_sched_delay(void) +{ + SPEEDY_CALL(do_sched_wrap_delay); +} + +__or_dynop void op_macc(void) +{ + env->sprs[SPR_MACLO] = 0; + env->sprs[SPR_MACHI] = 0; +} + +__or_dynop void op_store_insn_ea(void) +{ + env->insn_ea = OP_PARAM1; +} + Index: dyngen.c =================================================================== --- dyngen.c (nonexistent) +++ dyngen.c (revision 1765) @@ -0,0 +1,289 @@ +/* dyngen.c -- Generates micro operation generating functions + Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +#include +#include +#include + +#include "dyngen.h" + +#define OP_FUNC_PREFIX "op_" +#define OP_FUNC_PARAM_PREFIX "__op_param" +/* Have to add to to make sure that the param[] is 0 */ +#define MAX_PARAMS (3 + 1) + +static const char *c_file_head = +"#include \"config.h\"\n" +"\n" +"#include \n" +"\n" +"#include \"arch.h\"\n" +"#include \"opcode/or32.h\"\n" +"#include \"spr_defs.h\"\n" +"#include \"i386_regs.h\"\n" +"#include \"abstract.h\"\n" +"\n" +"#include \"dyn_rec.h\"\n" +"#include \"%s\"\n" +"\n"; + +static const char *gen_code_proto = +"void gen_code(struct op_queue *opq, struct dyn_page *dp);\n" +"void patch_relocs(struct op_queue *opq, void *host_page);\n" +"\n"; + +static const char *c_sw_file_head = +"#include \n" +"#include \n" +"\n" +"#include \"config.h\"\n" +"\n" +"#include \n" +"\n" +"#include \"arch.h\"\n" +"#include \"opcode/or32.h\"\n" +"#include \"spr_defs.h\"\n" +"#include \"i386_regs.h\"\n" +"#include \"abstract.h\"\n" +"#include \"dyn_rec.h\"\n" +"#include \"%s\"\n" +"\n" +"void gen_code(struct op_queue *opq, struct dyn_page *dp)\n" +"{\n" +" unsigned int *ops, i;\n" +" unsigned int host_len = dp->host_len;\n" +" void *host_cur = dp->host_page;\n" +" oraddr_t pc = dp->or_page;\n" +" void **loc = dp->locs;\n" +"\n" +" while(opq) {\n" +" if(opq->next)\n" +" *loc++ = (void *)(host_cur - dp->host_page);" +"\n" +" for(i = 0, ops = opq->ops; i < opq->num_ops; i++, ops++) {\n" +" switch(*ops) {\n" +" case op_mark_loc_indx:\n" +" opq->ops_param[0] = host_cur - dp->host_page;\n" +" break;\n"; + +static const char *c_sw_file_tail = +" }\n" +" }\n" +" opq = opq->next;\n" +" pc += 4;\n" +" }\n" +"\n" +" dp->host_len = host_cur - dp->host_page;\n" +" dp->host_page = realloc(dp->host_page, dp->host_len);\n" +"}\n"; + +static const char *c_rel_file_head = +"#include /* To get printf... */\n" +"#include \n" +"\n" +"#include \"config.h\"\n" +"\n" +"#include \n" +"\n" +"#include \"arch.h\"\n" +"#include \"spr_defs.h\"\n" +"#include \"i386_regs.h\"\n" +"#include \"opcode/or32.h\"\n" +"#include \"abstract.h\"\n" +"#include \"tick.h\"\n" +"#include \"execute.h\"\n" +"#include \"sprs.h\"\n" +"#include \"dyn_rec.h\"\n" +"#include \"op_support.h\"\n" +"#include \"%s\"\n" +"\n" +"void do_scheduler(void); /* FIXME: Remove */\n" +"void do_sched_wrap(void); /* FIXME: Remove */\n" +"void do_sched_wrap_delay(void); /* FIXME: Remove */\n" +"void simprintf(oraddr_t stackaddr, unsigned long regparam); /* FIXME: Remove */\n" +"\n" +"void patch_relocs(struct op_queue *opq, void *host_page)\n" +"{\n" +" unsigned int *ops, *ops_param, i;\n" +"\n" +" while(opq) {\n" +" for(i = 0, ops = opq->ops, ops_param = opq->ops_param; i < opq->num_ops; i++, ops++) {\n" +" switch(*ops) {\n"; + +static const char *c_rel_file_tail = +" }\n" +" }\n" +" opq = opq->next;\n" +" }\n" +"}\n"; + +static void gen_func_proto(FILE *f, const char *name, int *params) +{ + int i; + + fprintf(f, "void gen_%s(struct op_queue *opq, int end", name); + for(i = 0; (i < MAX_PARAMS) && params[i]; i++) { + fprintf(f, ", uorreg_t param%i", i + 1); + } + fprintf(f, ")"); +} + +int main(int argc, char **argv) +{ + void *obj; + int i, j; + unsigned int len; + char *name; + int params[MAX_PARAMS]; + struct reloc reloc; + + FILE *c_file; + FILE *h_file; + FILE *c_sw_file; + FILE *c_rel_file; + + if(argc != 6) { + fprintf(stderr, "Usage: %s

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