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scr/tech_vs_umc18.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: scr/cons_fake_rams.inc =================================================================== --- scr/cons_fake_rams.inc (nonexistent) +++ scr/cons_fake_rams.inc (revision 1765) @@ -0,0 +1,39 @@ +/* We "model" fake ram black boxes by setting input/output delays */ + +current_design art_hssp_128x34 +create_clock clk -period CLK_PERIOD +set_output_delay 1.12 -clock clk q +set_input_delay 0.3 -clock clk cen +set_input_delay 0.35 -clock clk wen +set_input_delay 0.1 -clock clk oen +set_input_delay 0.2 -clock clk a +set_input_delay 0.16 -clock clk d + +current_design art_hssp_512x19 +create_clock clk -period CLK_PERIOD +set_output_delay 1.12 -clock clk q +set_input_delay 0.3 -clock clk cen +set_input_delay 0.32 -clock clk wen +set_input_delay 0.1 -clock clk oen +set_input_delay 0.3 -clock clk a +set_input_delay 0.17 -clock clk d + +current_design art_hssp_2048x8 +create_clock clk -period CLK_PERIOD +set_output_delay 1.12 -clock clk q +set_input_delay 0.35 -clock clk cen +set_input_delay 0.37 -clock clk wen +set_input_delay 0.1 -clock clk oen +set_input_delay 0.35 -clock clk a +set_input_delay 0.2 -clock clk d + +current_design art_hdsp_2048x32 +create_clock clk -period CLK_PERIOD +set_output_delay 1.22 -clock clk q +set_input_delay 0.35 -clock clk cen +set_input_delay 0.41 -clock clk wen +set_input_delay 0.1 -clock clk oen +set_input_delay 0.34 -clock clk a +set_input_delay 0.2 -clock clk d + +current_design TOPLEVEL \ No newline at end of file Index: scr/select_tech.inc =================================================================== --- scr/select_tech.inc (nonexistent) +++ scr/select_tech.inc (revision 1765) @@ -0,0 +1,3 @@ +TECH = vs_umc18 /* vs_umc18, art_umc18 */ +CLK_PERIOD = 2 /* 333 MHz */ +MAX_AREA = 200000 /* Lets start lightly */ Index: scr/read_fake_rams.inc =================================================================== --- scr/read_fake_rams.inc (nonexistent) +++ scr/read_fake_rams.inc (revision 1765) @@ -0,0 +1,17 @@ +/* Set search path for verilog include files */ +search_path = search_path + { RAMS_PATH + fake/ } + +/* Read fake rams' verilog files */ +read -f verilog art_hssp_2048x8.v +read -f verilog art_hdsp_2048x32.v +read -f verilog art_hssp_512x19.v +read -f verilog art_hssp_128x34.v +read -f verilog art_hsdp_32x32.v + +/* Set dont_use attribute on black boxes */ +set_dont_touch art_hssp_512x19 +set_dont_touch art_hssp_128x34 +set_dont_touch art_hssp_2048x8 +set_dont_touch art_hdsp_2048x32 +set_dont_touch art_hsdp_32x32 + Index: scr/top_or1200.scr =================================================================== --- scr/top_or1200.scr (nonexistent) +++ scr/top_or1200.scr (revision 1765) @@ -0,0 +1,115 @@ +/* + * User defines + * + */ +TOPLEVEL = or1200 +include select_tech.inc +CLK = clk +RST = rst +CLK_PERIOD = 2.5 /* 400 MHz */ +MAX_AREA = 0 /* Push it */ +DO_UNGROUP = yes /* yes, no */ +DO_VERIFY = no /* yes, no */ +RAMS = art_rams18 /* fake, art_rams18 */ + +/* Starting timestamp */ +sh date + +/* Set some basic variables related to environment */ +include set_env.inc +STAGE = initial + +/* Load libraries */ +include tech_ + TECH + .inc + +/* Load RAMs */ +if (RAMS == "art_rams18") { + include tech_art_rams18.inc +} else if (RAMS == "fake") { + include read_fake_rams.inc +} else { + echo "Unsupported RAMs" + exit +} + +/* Load HDL source files */ +include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log + +/* Set design top */ +current_design TOPLEVEL + +/* Link all blocks and uniquify them */ +link +/* +include tech_art_rams18.inc +list -libraries > ../logs/libs +link +list -libraries > ../logs/libs +*/ +uniquify +check_design > LOG_PATH + check_design_ + TOPLEVEL + .log + +/* Apply constraints */ +if (TECH == "vs_umc18") { + include cons_vs_umc18.inc +} else if (TECH == "art_umc18") { + include cons_art_umc18.inc +} else { + echo "Error: Unsupported technology" + exit +} + +/* Transform arithmetics */ +transform_csa -group + +/* Lets do initial synthesis */ +if (DO_UNGROUP == "yes") { + ungroup -all +} +compile -incremental -boundary_optimization -map_effort medium + +/* Generate reports for basic synthesis */ +include reports.inc + +/* Dump gate-level from basic synthesis */ +include save_design.inc + +/* Advance to incremental synthesis, push hard */ +if (DO_UNGROUP == "yes") { + ungroup -all +} +STAGE = incremental +compile -incremental -boundary_optimization -ungroup_all -map_effort high + +/* Optimize registers */ +optimize_registers + +/* Dump gate-level from incremental synthesis */ +include save_design.inc + +/* Generate reports for incremental synthesis */ +include reports.inc + +/* Set area constraint */ +STAGE = final +set_max_area MAX_AREA +compile -incremental -boundary_optimization -auto_ungroup -map_effort medium + +/* Dump gate-level from final synthesis */ +include save_design.inc + +/* Generate reports for final synthesis */ +include reports.inc + +/* Verify design */ +if (NO_VERIFY == "yes") { + compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log +} + +/* Finish */ +sh date +exit + + + + Index: scr/tech_art_rams18.inc =================================================================== --- scr/tech_art_rams18.inc (nonexistent) +++ scr/tech_art_rams18.inc (revision 1765) @@ -0,0 +1,19 @@ +/* Set Artisan 0.18u RAMs */ + +search_path = search_path + { RAMS_PATH + art_hssp_2048x8/ } + { RAMS_PATH + art_hdsp_2048x32/ } \ + + { RAMS_PATH + art_hssp_512x19/ } + { RAMS_PATH + art_hssp_128x34/ } + \ + { RAMS_PATH + art_hsdp_32x32/ } +/* +add_module art_hssp_2048x8_typical_syn.lib art_hssp_2048x8_typical_syn +add_module art_hdsp_2048x32_typical_syn.lib art_hdsp_2048x32_typical_syn +add_module art_hssp_512x19_typical_syn.lib art_hssp_512x19_typical_syn +add_module -overwrite art_hssp_128x34_typical_syn.lib typical +*/ + +target_library = target_library + { art_hssp_2048x8_typical_syn.db } + \ + { art_hdsp_2048x32_typical_syn.db } + \ + { art_hssp_512x19_typical_syn.db } + \ + { art_hssp_128x34_typical_syn.db } + \ + { art_hsdp_32x32_typical_syn.db } +link_library = link_library + target_library +

scr/tech_art_rams18.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: scr/dodesign =================================================================== --- scr/dodesign (nonexistent) +++ scr/dodesign (revision 1765) @@ -0,0 +1,9 @@ +#!/bin/sh -f + +# nohup dc_shell -f top.scr | tee ../logs/top.log +dc_shell -f top_multp2_32x32.scr > ../logs/top_multp2_32x32.log +dc_shell -f top_cpu.scr > ../logs/top_cpu.log +dc_shell -f top_dc.scr > ../logs/top_dc.log +dc_shell -f top_ic.scr > ../logs/top_ic.log +dc_shell -f top_or1200.scr > ../logs/top_or1200.log +mv command.log ../logs

scr/dodesign Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: scr/top_multp2_32x32.scr =================================================================== --- scr/top_multp2_32x32.scr (nonexistent) +++ scr/top_multp2_32x32.scr (revision 1765) @@ -0,0 +1,95 @@ +/* + * User defines for synthesizing multiplier + * + */ +TOPLEVEL = multp2_32x32 +include select_tech.inc +CLK = CLK +RST = rst +CLK_PERIOD = 2 /* 500 MHz */ +MAX_AREA = 0 /* Push hard */ +DO_UNGROUP = yes /* yes, no */ +DO_VERIFY = no /* yes, no */ + +/* Starting timestamp */ +sh date + +/* Set some basic variables related to environment */ +include set_env.inc +STAGE = initial + +/* Load libraries */ +include tech_ + TECH + .inc + +/* Load HDL source files */ +include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log + +/* Set design top */ +current_design TOPLEVEL + +/* Link all blocks and uniquify them */ +link +uniquify +check_design > LOG_PATH + check_design_ + TOPLEVEL + .log + +/* Apply constraints */ +if (TECH == "vs_umc18") { + include cons_vs_umc18.inc +} else if (TECH == "art_umc18") { + include cons_art_umc18.inc +} else { + echo "Error: Unsupported technology" + exit +} + +/* Transform arithmetics */ +transform_csa -group + +/* Lets do basic synthesis */ +if (DO_UNGROUP == "yes") { + ungroup -all -flatten +} +compile -boundary_optimization -map_effort low + +/* Generate reports for basic synthesis */ +include reports.inc + +/* Dump gate-level from basic synthesis */ +include save_design.inc + +/* Advance to incremental synthesis, push hard */ +STAGE = incremental +compile -incremental -boundary_optimization -auto_ungroup -map_effort medium + +/* Optimize registers */ +optimize_registers + +/* Dump gate-level from incremental synthesis */ +include save_design.inc + +/* Generate reports for incremental synthesis */ +include reports.inc + +/* Set area constraint */ +STAGE = final +set_max_area MAX_AREA +compile -incremental -boundary_optimization -auto_ungroup -map_effort medium + +/* Dump gate-level from final synthesis */ +include save_design.inc + +/* Generate reports for final synthesis */ +include reports.inc + +/* Verify design */ +if (DO_VERIFY == "yes") { + compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log +} + +/* Finish */ +sh date +exit + + + + Index: scr/cons_art_umc18.inc =================================================================== --- scr/cons_art_umc18.inc (nonexistent) +++ scr/cons_art_umc18.inc (revision 1765) @@ -0,0 +1,47 @@ +/* Constraints */ +CLK_UNCERTAINTY = 0.1 /* 100 ps */ +DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */ +DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */ + +/* Clocks constraints */ +create_clock CLK -period CLK_PERIOD +set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY +set_dont_touch_network all_clocks() + +/* Reset constraints */ +set_driving_cell -none RST +set_drive 0 RST +set_dont_touch_network RST + +/* All inputs except reset and clock */ +all_inputs_wo_rst_clk = all_inputs() - CLK - RST + +/* Set output delays and load for output signals + * + * All outputs are assumed to go directly into + * external flip-flops for the purpose of this + * synthesis + */ +set_output_delay DFFHQX2_SETUP -clock CLK all_outputs() +set_load load_of(typical/DFFHQX2/D) * 4 all_outputs() + +/* Input delay and driving cell of all inputs + * + * All these signals are assumed to come directly from + * flip-flops for the purpose of this synthesis + * + */ +set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk +set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk + +/* Set design fanout */ +/* +set_max_fanout 10 TOPLEVEL +*/ + +/* Optimize all near-critical paths to give extra slack for layout */ +c_range = CLK_PERIOD * 0.1 +group_path -critical_range c_range -name CLK -to CLK + +/* Operating conditions */ +set_operating_conditions typical Index: scr/top_dc.scr =================================================================== --- scr/top_dc.scr (nonexistent) +++ scr/top_dc.scr (revision 1765) @@ -0,0 +1,107 @@ +/* + * User defines for synthesizing data cache / DMMU unit + * + */ +TOPLEVEL = dc +include select_tech.inc +CLK = clk +RST = rst +CLK_PERIOD = 1.8 /* 555 MHz */ +MAX_AREA = 0 /* Push hard */ +DO_UNGROUP = yes /* yes, no */ +DO_VERIFY = yes /* yes, no */ +RAMS = art_rams18 /* fake, art_rams18 */ + +/* Starting timestamp */ +sh date + +/* Set some basic variables related to environment */ +include set_env.inc +STAGE = initial + +/* Load libraries */ +include tech_ + TECH + .inc + +/* Load RAMs */ +if (RAMS == "art_rams18") { + include tech_art_rams18.inc +} else if (RAMS == "fake") { + include read_fake_rams.inc +} else { + echo "Unsupported RAMs" + exit +} + +/* Load HDL source files */ +include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log + +/* Set design top */ +current_design TOPLEVEL + +/* Link all blocks and uniquify them */ +link +transform_csa -group +uniquify +check_design > LOG_PATH + check_design_ + TOPLEVEL + .log + +/* Apply constraints */ +if (TECH == "vs_umc18") { + include cons_vs_umc18.inc +} else if (TECH == "art_umc18") { + include cons_art_umc18.inc +} else { + echo "Error: Unsupported technology" + exit +} + +/* Transform arithmetics */ +transform_csa -group + +/* Lets do basic synthesis */ +if (DO_UNGROUP == "yes") { + ungroup -all -flatten +} +compile -boundary_optimization -map_effort low + +/* Generate reports for basic synthesis */ +include reports.inc + +/* Dump gate-level from basic synthesis */ +include save_design.inc + +/* Advance to incremental synthesis, push hard */ +STAGE = incremental +compile -incremental -boundary_optimization -ungroup_all -map_effort high + +/* Optimize registers */ +optimize_registers + +/* Dump gate-level from incremental synthesis */ +include save_design.inc + +/* Generate reports for incremental synthesis */ +include reports.inc + +/* Set area constraint */ +STAGE = final +set_max_area MAX_AREA +compile -incremental -boundary_optimization -auto_ungroup -map_effort medium + +/* Dump gate-level from final synthesis */ +include save_design.inc + +/* Generate reports for final synthesis */ +include reports.inc + +/* Verify design */ +if (DO_VERIFY == "yes") { + compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log +} + +/* Finish */ +sh date +exit + + + + Index: scr/save_design.inc =================================================================== --- scr/save_design.inc (nonexistent) +++ scr/save_design.inc (revision 1765) @@ -0,0 +1,5 @@ +/* Save current design using synopsys format */ +write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db + +/* Save current design using verilog format */ +write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v Index: scr/cons_vs_umc18.inc =================================================================== --- scr/cons_vs_umc18.inc (nonexistent) +++ scr/cons_vs_umc18.inc (revision 1765) @@ -0,0 +1,50 @@ +/* Constraints */ +CLK_UNCERTAINTY = 0.1 /* 100 ps */ +DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */ +DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */ + +/* Clocks constraints */ +create_clock CLK -period CLK_PERIOD +set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY +set_dont_touch_network all_clocks() + +/* Reset constraints */ +set_driving_cell -none RST +set_drive 0 RST +set_dont_touch_network RST + +/* All inputs except reset and clock */ +all_inputs_wo_rst_clk = all_inputs() - CLK - RST + +/* Set output delays and load for output signals + * + * All outputs are assumed to go directly into + * external flip-flops for the purpose of this + * synthesis + */ +set_output_delay DFFPQ2_SETUP -clock CLK all_outputs() +set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs() + +/* Input delay and driving cell of all inputs + * + * All these signals are assumed to come directly from + * flip-flops for the purpose of this synthesis + * + */ +set_input_delay DFFPQ2_CKQ -clock CLK all_inputs_wo_rst_clk +set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk + +/* Set design fanout */ +/* +set_max_fanout 10 TOPLEVEL +*/ + +/* Set area constraint */ +set_max_area MAX_AREA + +/* Optimize all near-critical paths to give extra slack for layout */ +c_range = CLK_PERIOD * 0.1 +group_path -critical_range c_range -name CLK -to CLK + +/* Operating conditions */ +set_operating_conditions TYPICAL Index: scr/top_cpu.scr =================================================================== --- scr/top_cpu.scr (nonexistent) +++ scr/top_cpu.scr (revision 1765) @@ -0,0 +1,112 @@ +/* + * User defines for synthesizing CPU + * + */ +TOPLEVEL = cpu +include select_tech.inc +CLK = clk +RST = rst +CLK_PERIOD = 2.25 /* 444 MHz */ +MAX_AREA = 0 /* Push hard */ +DO_UNGROUP = yes /* yes, no */ +DO_VERIFY = no /* yes, no */ +RAMS = art_rams18 /* fake, art_rams18 */ + +/* Starting timestamp */ +sh date + +/* Set some basic variables related to environment */ +include set_env.inc +STAGE = initial + +/* Load libraries */ +include tech_ + TECH + .inc + +/* Load RAMs */ +if (RAMS == "art_rams18") { + include tech_art_rams18.inc +} else if (RAMS == "fake") { + include read_fake_rams.inc +} else { + echo "Unsupported RAMs" + exit +} + +/* Load HDL source files */ +include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log + +/* Set design top */ +current_design TOPLEVEL + +/* Link all blocks and uniquify them */ +link +uniquify +check_design > LOG_PATH + check_design_ + TOPLEVEL + .log + +/* Apply constraints */ +if (TECH == "vs_umc18") { + include cons_vs_umc18.inc +} else if (TECH == "art_umc18") { + include cons_art_umc18.inc +} else { + echo "Error: Unsupported technology" + exit +} + +/* Transform arithmetics */ +transform_csa -group + +/* Don't touch multp2_32x32 */ +set_dont_touch multp2_32x32 + +/* Lets do basic synthesis */ +if (DO_UNGROUP == "yes") { + ungroup -all +} +compile -boundary_optimization -ungroup_all -map_effort medium + +/* Generate reports for basic synthesis */ +include reports.inc + +/* Dump gate-level from basic synthesis */ +include save_design.inc + +/* Remove dont_touch from multp2_32x32 */ +remove_attribute multp2_32x32 dont_touch + +/* Advance to incremental synthesis, push hard */ +STAGE = incremental +compile -incremental -boundary_optimization -ungroup_all -map_effort high + +/* Optimize registers */ +optimize_registers + +/* Dump gate-level from incremental synthesis */ +include save_design.inc + +/* Generate reports for incremental synthesis */ +include reports.inc + +/* Set area constraint */ +STAGE = final +set_max_area MAX_AREA +compile -incremental -boundary_optimization -auto_ungroup -map_effort medium + +/* Dump gate-level from final synthesis */ +include save_design.inc + +/* Generate reports for final synthesis */ +include reports.inc + +/* Verify design */ +if (DO_VERIFY == "yes") { + compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log +} + +/* Finish */ +sh date +exit + + + + Index: scr/top_ic.scr =================================================================== --- scr/top_ic.scr (nonexistent) +++ scr/top_ic.scr (revision 1765) @@ -0,0 +1,106 @@ +/* + * User defines for synthesizing insn cache / IMMU unit + * + */ +TOPLEVEL = ic +include select_tech.inc +CLK = clk +RST = rst +CLK_PERIOD = 1.8 /* 555 MHz */ +MAX_AREA = 0 /* Push hard */ +DO_UNGROUP = yes /* yes, no */ +DO_VERIFY = yes /* yes, no */ +RAMS = art_rams18 /* fake, art_rams18 */ + +/* Starting timestamp */ +sh date + +/* Set some basic variables related to environment */ +include set_env.inc +STAGE = initial + +/* Load libraries */ +include tech_ + TECH + .inc + +/* Load RAMs */ +if (RAMS == "art_rams18") { + include tech_art_rams18.inc +} else if (RAMS == "fake") { + include read_fake_rams.inc +} else { + echo "Unsupported RAMs" + exit +} + +/* Load HDL source files */ +include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log + +/* Set design top */ +current_design TOPLEVEL + +/* Link all blocks and uniquify them */ +link +uniquify +check_design > LOG_PATH + check_design_ + TOPLEVEL + .log + +/* Apply constraints */ +if (TECH == "vs_umc18") { + include cons_vs_umc18.inc +} else if (TECH == "art_umc18") { + include cons_art_umc18.inc +} else { + echo "Error: Unsupported technology" + exit +} + +/* Transform arithmetics */ +transform_csa -group + +/* Lets do basic synthesis */ +if (DO_UNGROUP == "yes") { + ungroup -all -flatten +} +compile -boundary_optimization -map_effort low + +/* Generate reports for basic synthesis */ +include reports.inc + +/* Dump gate-level from basic synthesis */ +include save_design.inc + +/* Advance to incremental synthesis, push hard */ +STAGE = incremental +compile -incremental -boundary_optimization -ungroup_all -map_effort high + +/* Optimize registers */ +optimize_registers + +/* Dump gate-level from incremental synthesis */ +include save_design.inc + +/* Generate reports for incremental synthesis */ +include reports.inc + +/* Set area constraint */ +STAGE = final +set_max_area MAX_AREA +compile -incremental -boundary_optimization -auto_ungroup -map_effort medium + +/* Dump gate-level from final synthesis */ +include save_design.inc + +/* Generate reports for final synthesis */ +include reports.inc + +/* Verify design */ +if (DO_VERIFY == "yes") { + compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log +} + +/* Finish */ +sh date +exit + + + + Index: scr/reports.inc =================================================================== --- scr/reports.inc (nonexistent) +++ scr/reports.inc (revision 1765) @@ -0,0 +1,10 @@ +/* Basic reports */ +report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log +report_timing -nworst 10 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log +report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log +report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log +report_constraint > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log +/* +report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log +*/ + Index: scr/set_env.inc =================================================================== --- scr/set_env.inc (nonexistent) +++ scr/set_env.inc (revision 1765) @@ -0,0 +1,21 @@ +/* Enable Verilog HDL preprocessor */ +hdlin_enable_vpp = true + +/* Enable power analysis */ +power_preserve_rtl_hier_names = true + +/* Set log path */ +LOG_PATH = "../logs/" + +/* Set gate-level netlist path */ +GATE_PATH = "../gate/" + +/* Set RAMS_PATH */ +RAMS_PATH = "../../lib/" + +/* Set RTL source path */ +RTL_PATH = "../../rtl/" + +/* Optimize adders */ +synlib_model_map_effort = high +hlo_share_effort = medium Index: scr/read_design.inc =================================================================== --- scr/read_design.inc (nonexistent) +++ scr/read_design.inc (revision 1765) @@ -0,0 +1,56 @@ +/* Set search path for verilog include files */ +search_path = search_path + { RTL_PATH } + { GATE_PATH } + +/* Read verilog files of the Data cache / DMMU */ +if (TOPLEVEL == "dc") { + read -f verilog dc_fsm.v + read -f verilog reg2mem.v + read -f verilog mem2reg.v + read -f verilog dc_ram.v + read -f verilog dc_tag.v + read -f verilog dtlb.v + read -f verilog dc.v +} + +/* Read verilog files for the multiplier */ +if (TOPLEVEL == "multp2_32x32") { + read -f verilog multp2_32x32.v +} + +/* Read verilog files of the CPU */ +if (TOPLEVEL == "cpu") { + read -f verilog alu.v + read -f verilog except.v + read -f verilog frz_logic.v + read -f verilog id.v + read -f verilog ifetch.v + read -f verilog lsu.v + read -f db incremental_multp2_32x32.db + read -f verilog operandmuxes.v + read -f verilog rf.v + read -f verilog sprs.v + read -f verilog traceport.v + read -f verilog wbmux.v + read -f verilog cpu.v +} + +/* Read verilog files of the Instructino cache / IMMU */ +if (TOPLEVEL == "ic") { + read -f verilog ic_fsm.v + read -f verilog ic_ram.v + read -f verilog ic_tag.v + read -f verilog itlb.v + read -f verilog ic.v +} + +/* Top level OR1200 + various smaller OR1200 units */ +if (TOPLEVEL == "or1200") { + read -f verilog pic.v + read -f verilog pm.v + read -f verilog tt.v + read -f verilog wb_biu.v + read -f db incremental_dc.db + read -f db incremental_cpu.db + read -f db incremental_ic.db + read -f verilog or1200.v +} Index: scr/tech_art_umc18.inc =================================================================== --- scr/tech_art_umc18.inc (nonexistent) +++ scr/tech_art_umc18.inc (revision 1765) @@ -0,0 +1,17 @@ +/* Set Virtual Silicon UMC 0.18u standard cell library */ + +search_path = {. /libs/Artisan/aci/sc-x/synopsys/ } + \ + { /libs/Artisan/aci/sc-x/symbols/synopsys/ } +snps = get_unix_variable("SYNOPSYS") +synthetic_library = { \ + snps + "/libraries/syn/dw01.sldb" \ + snps + "/libraries/syn/dw02.sldb" \ + snps + "/libraries/syn/dw03.sldb" \ + snps + "/libraries/syn/dw04.sldb" \ + snps + "/libraries/syn/dw05.sldb" \ + snps + "/libraries/syn/dw06.sldb" \ + snps + "/libraries/syn/dw07.sldb" } +target_library = { typical.db } +link_library = target_library + synthetic_library +symbol_library = { umc18.sdb } +

scr/tech_art_umc18.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property