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    /or1k/tags/stable/mp3/rtl/verilog/audio
    from Rev 392 to Rev 1765
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Rev 392 → Rev 1765

/audio_codec_if.v
0,0 → 1,144
//////////////////////////////////////////////////////////////////////
//// ////
//// MP3 demo Audio CODEC interface ////
//// ////
//// This file is part of the MP3 demo application ////
//// http://www.opencores.org/cores/or1k/mp3/ ////
//// ////
//// Description ////
//// Connects Audio block to XSV board AK4520 codec chip. ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Lior Shtram, lior.shtram@flextronicssemi.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module audio_codec_if (
rstn,
clk,
fifo_clk,
fifo_data,
fifo_rd_en,
 
sclk,
mclk,
lrclk,
sdout,
sdin
);
 
parameter fifo_width = 16;
parameter count_bits = 11;
 
input rstn;
input clk;
output fifo_clk;
input [fifo_width-1:0] fifo_data;
output fifo_rd_en;
 
output sclk;
output mclk;
output lrclk;
input sdout;
output sdin;
 
 
reg [count_bits-1:0] counter;
reg [16:0] shift_reg;
reg f_rd_en;
reg sd_sig;
 
always @(posedge clk or negedge rstn)
begin
if(!rstn)
counter <= 0;
else
counter <= #1 counter + 1;
end
 
assign fifo_clk = clk ;
assign fifo_rd_en = f_rd_en ;
assign mclk = counter[0]; // mclk = clk/2 = 256fs
assign sclk = counter[2]; // sclk = mclk/4 = 64fs
assign lrclk = counter[8]; //lrclk = sclk/64
 
always @(posedge clk or negedge rstn)
begin
if(!rstn)
begin
sd_sig <= 1'b0;
shift_reg <= 0;
end
else
begin
if(counter[7:3] < 5'd16)
begin
if( counter[2:0] == 3'b101)
shift_reg[fifo_width:1] <= #1 shift_reg[fifo_width-1:0];
else
shift_reg <= #1 shift_reg;
sd_sig <= #1 shift_reg[16];
end
else
begin
sd_sig <= #1 1'b0;
if(counter[7:0] == 8'h80)
shift_reg[16:0] <= { fifo_data[fifo_width-1:0], 1'b0 };
end
end
end
 
// To je nase. Sve ostalo je garbidz.
always @(posedge clk or negedge rstn)
begin
if(!rstn)
f_rd_en <= 1'b0;
else
if(counter[9:0] == 10'h200)
f_rd_en <= #1 1'b1;
else
f_rd_en <= #1 1'b0;
end
 
 
assign sdin = sd_sig;
 
 
endmodule
/audio_top.v
0,0 → 1,230
//////////////////////////////////////////////////////////////////////
//// ////
//// MP3 demo Audio Interface Top Level ////
//// ////
//// This file is part of the MP3 demo application ////
//// http://www.opencores.org/cores/or1k/mp3/ ////
//// ////
//// Description ////
//// Audio interface top level for XSV board instantiating ////
//// FIFOs, WISHBONE interface and XSV CODEC interface. ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Lior Shtram, lior.shtram@flextronicssemi.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module audio_top (
clk, rstn,
 
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
 
mclk, lrclk, sclk, sdin, sdout,
 
audio_dreq,
igor, simon, USB_VPO, USB_VMO
 
);
 
input clk;
input rstn;
 
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
 
output mclk;
output lrclk;
output sclk;
output sdin;
input sdout;
 
output audio_dreq;
 
input igor;
input simon;
output USB_VPO;
output USB_VMO;
 
parameter fifo_width = 16;
 
wire [fifo_width-1:0] fifo_data_i;
wire [fifo_width-1:0] fifo_data_o;
wire fifo_clk_wr;
wire fifo_clk_rd;
wire fifo_full;
wire fifo_empty;
wire fifo_almost_full;
wire fifo_almost_empty;
wire fifo_rd_en;
wire fifo_wr_en;
 
assign audio_dreq = fifo_almost_empty;
assign USB_VPO = fifo_almost_full;
assign USB_VMO = fifo_almost_empty;
 
 
 
audio_wb_if i_audio_wb_if(
.rstn( rstn ),
.clk( clk ),
.wb_dat_i( wb_dat_i ),
.wb_dat_o( wb_dat_o ),
.wb_adr_i( wb_adr_i ),
.wb_sel_i( wb_sel_i ),
.wb_we_i( wb_we_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_ack_o( wb_ack_o ),
.wb_err_o( wb_err_o ),
.fifo_dat_o( fifo_data_i ),
.fifo_clk_o( fifo_clk_wr ),
.fifo_wr_en( fifo_wr_en ),
.fifo_full( fifo_full ),
.fifo_empty( fifo_empty ),
.fifo_almost_full( fifo_almost_full ),
.fifo_almost_empty( fifo_almost_empty ),
.simon(igor),
.igor(simon)
 
);
 
`ifdef AUDIO_NO_FIFO
fifo_empty_16 i_audio_fifo (
.AINIT( !rstn ),
.DIN( fifo_data_i ),
.DOUT( fifo_data_o ),
// .WR_CLK( fifo_clk_rd ),
// .RD_CLK( fifo_clk_wr ),
.WR_CLK( fifo_clk_wr ),
.RD_CLK( fifo_clk_rd ),
.RD_EN( fifo_rd_en ),
.WR_EN( fifo_wr_en ),
.EMPTY( fifo_empty ),
.FULL( fifo_full ),
.ALMOST_EMPTY( fifo_almost_empty ),
.ALMOST_FULL( fifo_almost_full )
);
`else
/*
fifo8kx16 i_audio_fifo (
.AINIT( !rstn ),
.DIN( fifo_data_i ),
.DOUT( fifo_data_o ),
// .WR_CLK( fifo_clk_rd ),
// .RD_CLK( fifo_clk_wr ),
.WR_CLK( fifo_clk_wr ),
.RD_CLK( fifo_clk_rd ),
.RD_EN( fifo_rd_en ),
.WR_EN( fifo_wr_en ),
.EMPTY( fifo_empty ),
.FULL( fifo_full ),
.ALMOST_EMPTY( fifo_almost_empty ),
.ALMOST_FULL( fifo_almost_full )
);
*/
 
fifo_4095_16 i_audio_fifo (
.AINIT( !rstn ),
.DIN( fifo_data_i ),
.DOUT( fifo_data_o ),
// .WR_CLK( fifo_clk_rd ),
// .RD_CLK( fifo_clk_wr ),
.WR_CLK( fifo_clk_wr ),
.RD_CLK( fifo_clk_rd ),
.RD_EN( fifo_rd_en ),
.WR_EN( fifo_wr_en ),
.EMPTY( fifo_empty ),
.FULL( fifo_full ),
.ALMOST_EMPTY( fifo_almost_empty ),
.ALMOST_FULL( fifo_almost_full )
);
 
 
`endif
/*
fifo_1023_16 i_audio_fifo (
.AINIT( !rstn ),
.DIN( fifo_data_i ),
.DOUT( fifo_data_o ),
.WR_CLK( clk ),
.RD_CLK( clk ),
.RD_EN( fifo_rd_en ),
.WR_EN( fifo_wr_en ),
.EMPTY( fifo_empty ),
.FULL( fifo_full ),
.ALMOST_EMPTY( fifo_almost_empty ),
.ALMOST_FULL( fifo_almost_full )
); // synthesis black_box
*/
 
 
 
 
`ifdef UNUSED
assign fifo_data_o = fifo_data_i;
assign fifo_full = 1'b0;
assign fifo_empty = 1'b0;
assign fifo_almost_full = 1'b0;
assign fifo_almost_empty = 1'b0;
`endif
 
audio_codec_if i_audio_codec_if (
.rstn( rstn ),
.clk( clk ),
.fifo_clk( fifo_clk_rd ),
.fifo_data( fifo_data_o ),
.fifo_rd_en( fifo_rd_en ),
.sclk( sclk ),
.mclk( mclk ),
.lrclk( lrclk ),
.sdout( sdout ),
.sdin( sdin )
);
endmodule
/audio_wb_if.v
0,0 → 1,132
//////////////////////////////////////////////////////////////////////
//// ////
//// MP3 demo WISHBONE i/f of Audio block ////
//// ////
//// This file is part of the MP3 demo application ////
//// http://www.opencores.org/cores/or1k/mp3/ ////
//// ////
//// Description ////
//// Connect the audio block to the WISHBONE bus. ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Lior Shtram, lior.shtram@flextronicssemi.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module audio_wb_if (
rstn,
clk,
wb_dat_i,
wb_dat_o,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_cyc_i,
wb_stb_i,
wb_ack_o,
wb_err_o,
 
fifo_dat_o,
fifo_clk_o,
fifo_wr_en,
fifo_full,
fifo_empty,
fifo_almost_full,
fifo_almost_empty,
simon,
igor
);
 
parameter fifo_width = 16;
 
input rstn;
input clk;
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
 
output [fifo_width-1:0] fifo_dat_o;
output fifo_clk_o;
output fifo_wr_en;
input fifo_full;
input fifo_empty;
input fifo_almost_full;
input fifo_almost_empty;
 
input simon;
input igor;
 
reg [3:0] fifo_status;
reg f_wr_en;
 
always @(posedge clk or negedge rstn)
if (!rstn) fifo_status <= 4'b0;
else
fifo_status <= #1 { fifo_full, fifo_empty,
fifo_almost_full, fifo_almost_empty };
 
assign fifo_dat_o = wb_dat_i[fifo_width-1:0];
assign wb_dat_o = { simon, igor, 26'b0, fifo_status };
//assign wb_ack_o = wb_cyc_i & !fifo_almost_full;
assign wb_err_o = 1'b0;
assign fifo_clk_o = clk;
 
always @(posedge clk or negedge rstn)
begin
if(!rstn)
f_wr_en <= 1'b0;
else
if(wb_cyc_i & wb_we_i & !fifo_almost_full & ~f_wr_en)
f_wr_en <= #1 1'b1;
else
f_wr_en <= #1 1'b0;
end
 
assign fifo_wr_en = f_wr_en;
//assign wb_ack_o = f_wr_en;
assign wb_ack_o = f_wr_en | (wb_cyc_i & wb_stb_i & ~wb_we_i);
 
endmodule
/fifo_empty_16.v
0,0 → 1,35
`include "timescale.v"
 
module fifo_empty_16 (
DIN,
WR_EN,
WR_CLK,
RD_EN,
RD_CLK,
AINIT,
DOUT,
FULL,
EMPTY,
ALMOST_FULL,
ALMOST_EMPTY);
 
input [15 : 0] DIN;
input WR_EN;
input WR_CLK;
input RD_EN;
input RD_CLK;
input AINIT;
output [15 : 0] DOUT;
output FULL;
output EMPTY;
output ALMOST_FULL;
output ALMOST_EMPTY;
 
 
assign DOUT = DIN;
assign FULL = 1'b0;
assign EMPTY = 1'b0;
assign ALMOST_FULL = 1'b0;
assign ALMOST_EMPTY = 1'b0;
 
endmodule
/fifo_4095_16.v
0,0 → 1,101
/*******************************************************************
* This file was created by the Xilinx CORE Generator tool, and *
* is (c) Xilinx, Inc. 1998, 1999. No part of this file may be *
* transmitted to any third party (other than intended by Xilinx) *
* or used without a Xilinx programmable or hardwire device without *
* Xilinx's prior written permission. *
*******************************************************************/
 
// The following line must appear at the top of the file in which
// the core instantiation will be made. Ensure that the translate_off/_on
// compiler directives are correct for your synthesis tool(s)
 
// Your Verilog compiler/interpreter might require the following
// option or it's equivalent to help locate the Xilinx Core Library
// +incdir+${XILINX}/verilog/src
// Here ${XILINX} refers to the XILINX software installation directory.
 
//----------- Begin Cut here for LIBRARY inclusion --------// LIB_TAG
 
// synopsys translate_off
 
//`include "XilinxCoreLib/async_fifo_v3_0.v"
 
// synopsys translate_on
 
// LIB_TAG_END ------- End LIBRARY inclusion --------------
 
// The following code must appear after the module in which it
// is to be instantiated. Ensure that the translate_off/_on compiler
// directives are correct for your synthesis tool(s).
 
//----------- Begin Cut here for MODULE Declaration -------// MOD_TAG
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module fifo_4095_16 (
DIN,
WR_EN,
WR_CLK,
RD_EN,
RD_CLK,
AINIT,
DOUT,
FULL,
EMPTY,
ALMOST_FULL,
ALMOST_EMPTY);
 
input [15 : 0] DIN;
input WR_EN;
input WR_CLK;
input RD_EN;
input RD_CLK;
input AINIT;
output [15 : 0] DOUT;
output FULL;
output EMPTY;
output ALMOST_FULL;
output ALMOST_EMPTY;
 
// synopsys translate_off
 
ASYNC_FIFO_V3_0 #(
16,
0,
100,
1,
1,
0,
0,
0,
0,
0,
0,
0,
2,
0,
1,
0,
2,
0)
inst (
.DIN(DIN),
.WR_EN(WR_EN),
.WR_CLK(WR_CLK),
.RD_EN(RD_EN),
.RD_CLK(RD_CLK),
.AINIT(AINIT),
.DOUT(DOUT),
.FULL(FULL),
.EMPTY(EMPTY),
.ALMOST_FULL(ALMOST_FULL),
.ALMOST_EMPTY(ALMOST_EMPTY));
 
// synopsys translate_on
 
endmodule
 
// MOD_TAG_END ------- End MODULE Declaration -------------

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