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/synplify/xfpga_top.prj File deleted

synplify/xfpga_top.prj Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: synplify/src/xfpga_top.ucf =================================================================== --- synplify/src/xfpga_top.ucf (revision 1765) +++ synplify/src/xfpga_top.ucf (nonexistent) @@ -1,522 +0,0 @@ -#PINLOCK_BEGIN -NET "rstn" LOC = "P174"; -NET "sw[1]" LOC = "P175"; -NET "sw[2]" LOC = "P176"; -NET "USB_VPO" LOC = "P13"; -NET "USB_VMO" LOC = "P17"; -NET "clk" LOC = "P89"; -NET "vga_pclk" LOC = "P52"; -NET "vga_blank" LOC = "P50"; -NET "vga_hsyncn" LOC = "P48"; -NET "vga_vsyncn" LOC = "P49"; -NET "vga_g[3]" LOC = "P118"; -NET "vga_g[2]" LOC = "P117"; -NET "vga_g[1]" LOC = "P116"; -NET "vga_g[0]" LOC = "P115"; -NET "vga_b[3]" LOC = "P128"; -NET "vga_b[2]" LOC = "P127"; -NET "vga_b[1]" LOC = "P126"; -NET "vga_b[0]" LOC = "P125"; -NET "vga_r[3]" LOC = "P114"; -NET "vga_r[2]" LOC = "P113"; -NET "vga_r[1]" LOC = "P111"; -NET "vga_r[0]" LOC = "P110"; -NET "vga_pclk" FAST; -NET "vga_blank" FAST; -NET "vga_hsyncn" FAST; -NET "vga_vsyncn" FAST; -NET "vga_g[3]" FAST; -NET "vga_g[2]" FAST; -NET "vga_g[1]" FAST; -NET "vga_g[0]" FAST; -NET "vga_b[3]" FAST; -NET "vga_b[2]" FAST; -NET "vga_b[1]" FAST; -NET "vga_b[0]" FAST; -NET "vga_r[3]" FAST; -NET "vga_r[2]" FAST; -NET "vga_r[1]" FAST; -NET "vga_r[0]" FAST; -NET "vga_pclk" DRIVE = 24; -NET "vga_blank" DRIVE = 24; -NET "vga_hsyncn" DRIVE = 24; -NET "vga_vsyncn" DRIVE = 24; -NET "vga_g[3]" DRIVE = 24; -NET "vga_g[2]" DRIVE = 24; -NET "vga_g[1]" DRIVE = 24; -NET "vga_g[0]" DRIVE = 24; -NET "vga_b[3]" DRIVE = 24; -NET "vga_b[2]" DRIVE = 24; -NET "vga_b[1]" DRIVE = 24; -NET "vga_b[0]" DRIVE = 24; -NET "vga_r[3]" DRIVE = 24; -NET "vga_r[2]" DRIVE = 24; -NET "vga_r[1]" DRIVE = 24; -NET "vga_r[0]" DRIVE = 24; -NET "codec_sdin" LOC = "P6"; -NET "codec_mclk" LOC = "P3"; -NET "codec_lrclk" LOC = "P4"; -NET "codec_sclk" LOC = "P5"; -#NET "codec_sdout" LOC = "P7" -NET "codec_sdin" FAST; -NET "codec_mclk" FAST; -NET "codec_lrclk" FAST; -NET "codec_sclk" FAST; -NET "codec_sdin" DRIVE = 24; -NET "codec_mclk" DRIVE = 24; -NET "codec_lrclk" DRIVE = 24; -NET "codec_sclk" DRIVE = 24; -NET "sram_r_d[0]" DRIVE = 24; -NET "sram_r_d[1]" DRIVE = 24; -NET "sram_r_d[2]" DRIVE = 24; -NET "sram_r_d[3]" DRIVE = 24; -NET "sram_r_d[4]" DRIVE = 24; -NET "sram_r_d[5]" DRIVE = 24; -NET "sram_r_d[6]" DRIVE = 24; -NET "sram_r_d[7]" DRIVE = 24; -NET "sram_r_d[8]" DRIVE = 24; -NET "sram_r_d[9]" DRIVE = 24; -NET "sram_r_d[10]" DRIVE = 24; -NET "sram_r_d[11]" DRIVE = 24; -NET "sram_r_d[12]" DRIVE = 24; -NET "sram_r_d[13]" DRIVE = 24; -NET "sram_r_d[14]" DRIVE = 24; -NET "sram_r_d[15]" DRIVE = 24; -NET "sram_r_d[0]" FAST; -NET "sram_r_d[1]" FAST; -NET "sram_r_d[2]" FAST; -NET "sram_r_d[3]" FAST; -NET "sram_r_d[4]" FAST; -NET "sram_r_d[5]" FAST; -NET "sram_r_d[6]" FAST; -NET "sram_r_d[7]" FAST; -NET "sram_r_d[8]" FAST; -NET "sram_r_d[9]" FAST; -NET "sram_r_d[10]" FAST; -NET "sram_r_d[11]" FAST; -NET "sram_r_d[12]" FAST; -NET "sram_r_d[13]" FAST; -NET "sram_r_d[14]" FAST; -NET "sram_r_d[15]" FAST; -NET "sram_r_a[0]" DRIVE = 24; -NET "sram_r_a[1]" DRIVE = 24; -NET "sram_r_a[2]" DRIVE = 24; -NET "sram_r_a[3]" DRIVE = 24; -NET "sram_r_a[4]" DRIVE = 24; -NET "sram_r_a[5]" DRIVE = 24; -NET "sram_r_a[6]" DRIVE = 24; -NET "sram_r_a[7]" DRIVE = 24; -NET "sram_r_a[8]" DRIVE = 24; -NET "sram_r_a[9]" DRIVE = 24; -NET "sram_r_a[10]" DRIVE = 24; -NET "sram_r_a[11]" DRIVE = 24; -NET "sram_r_a[12]" DRIVE = 24; -NET "sram_r_a[13]" DRIVE = 24; -NET "sram_r_a[14]" DRIVE = 24; -NET "sram_r_a[15]" DRIVE = 24; -NET "sram_r_a[16]" DRIVE = 24; -NET "sram_r_a[17]" DRIVE = 24; -NET "sram_r_a[18]" DRIVE = 24; -NET "sram_r_a[0]" FAST; -NET "sram_r_a[1]" FAST; -NET "sram_r_a[2]" FAST; -NET "sram_r_a[3]" FAST; -NET "sram_r_a[4]" FAST; -NET "sram_r_a[5]" FAST; -NET "sram_r_a[6]" FAST; -NET "sram_r_a[7]" FAST; -NET "sram_r_a[8]" FAST; -NET "sram_r_a[9]" FAST; -NET "sram_r_a[10]" FAST; -NET "sram_r_a[11]" FAST; -NET "sram_r_a[12]" FAST; -NET "sram_r_a[13]" FAST; -NET "sram_r_a[14]" FAST; -NET "sram_r_a[15]" FAST; -NET "sram_r_a[16]" FAST; -NET "sram_r_a[17]" FAST; -NET "sram_r_a[18]" FAST; -NET "sram_l_d[0]" DRIVE = 24; -NET "sram_l_d[1]" DRIVE = 24; -NET "sram_l_d[2]" DRIVE = 24; -NET "sram_l_d[3]" DRIVE = 24; -NET "sram_l_d[4]" DRIVE = 24; -NET "sram_l_d[5]" DRIVE = 24; -NET "sram_l_d[6]" DRIVE = 24; -NET "sram_l_d[7]" DRIVE = 24; -NET "sram_l_d[8]" DRIVE = 24; -NET "sram_l_d[9]" DRIVE = 24; -NET "sram_l_d[10]" DRIVE = 24; -NET "sram_l_d[11]" DRIVE = 24; -NET "sram_l_d[12]" DRIVE = 24; -NET "sram_l_d[13]" DRIVE = 24; -NET "sram_l_d[14]" DRIVE = 24; -NET "sram_l_d[15]" DRIVE = 24; -NET "sram_l_d[0]" FAST; -NET "sram_l_d[1]" FAST; -NET "sram_l_d[2]" FAST; -NET "sram_l_d[3]" FAST; -NET "sram_l_d[4]" FAST; -NET "sram_l_d[5]" FAST; -NET "sram_l_d[6]" FAST; -NET "sram_l_d[7]" FAST; -NET "sram_l_d[8]" FAST; -NET "sram_l_d[9]" FAST; -NET "sram_l_d[10]" FAST; -NET "sram_l_d[11]" FAST; -NET "sram_l_d[12]" FAST; -NET "sram_l_d[13]" FAST; -NET "sram_l_d[14]" FAST; -NET "sram_l_d[15]" FAST; -NET "sram_l_a[0]" DRIVE = 24; -NET "sram_l_a[1]" DRIVE = 24; -NET "sram_l_a[2]" DRIVE = 24; -NET "sram_l_a[3]" DRIVE = 24; -NET "sram_l_a[4]" DRIVE = 24; -NET "sram_l_a[5]" DRIVE = 24; -NET "sram_l_a[6]" DRIVE = 24; -NET "sram_l_a[7]" DRIVE = 24; -NET "sram_l_a[8]" DRIVE = 24; -NET "sram_l_a[9]" DRIVE = 24; -NET "sram_l_a[10]" DRIVE = 24; -NET "sram_l_a[11]" DRIVE = 24; -NET "sram_l_a[12]" DRIVE = 24; -NET "sram_l_a[13]" DRIVE = 24; -NET "sram_l_a[14]" DRIVE = 24; -NET "sram_l_a[15]" DRIVE = 24; -NET "sram_l_a[16]" DRIVE = 24; -NET "sram_l_a[17]" DRIVE = 24; -NET "sram_l_a[18]" DRIVE = 24; -NET "sram_l_a[0]" FAST; -NET "sram_l_a[1]" FAST; -NET "sram_l_a[2]" FAST; -NET "sram_l_a[3]" FAST; -NET "sram_l_a[4]" FAST; -NET "sram_l_a[5]" FAST; -NET "sram_l_a[6]" FAST; -NET "sram_l_a[7]" FAST; -NET "sram_l_a[8]" FAST; -NET "sram_l_a[9]" FAST; -NET "sram_l_a[10]" FAST; -NET "sram_l_a[11]" FAST; -NET "sram_l_a[12]" FAST; -NET "sram_l_a[13]" FAST; -NET "sram_l_a[14]" FAST; -NET "sram_l_a[15]" FAST; -NET "sram_l_a[16]" FAST; -NET "sram_l_a[17]" FAST; -NET "sram_l_a[18]" FAST; -NET "sram_l0_wen" DRIVE = 24; -NET "sram_l1_wen" DRIVE = 24; -NET "sram_r0_wen" DRIVE = 24; -NET "sram_r1_wen" DRIVE = 24; -NET "sram_r_oen" DRIVE = 24; -NET "sram_l_oen" DRIVE = 24; -NET "sram_r_cen" DRIVE = 24; -NET "sram_l_cen" DRIVE = 24; -NET "sram_l0_wen" FAST; -NET "sram_l1_wen" FAST; -NET "sram_r0_wen" FAST; -NET "sram_r1_wen" FAST; -NET "sram_r_oen" FAST; -NET "sram_l_oen" FAST; -NET "sram_r_cen" FAST; -NET "sram_l_cen" FAST; -NET "sram_l_a[0]" LOC = "P200"; -NET "sram_l_a[6]" LOC = "P191"; -NET "sram_l_d[14]" LOC = "P223"; -NET "sram_r_d[12]" LOC = "P86"; -NET "sram_l_a[5]" LOC = "P192"; -NET "sram_l_d[3]" LOC = "P206"; -NET "sram_l_d[10]" LOC = "P218"; -NET "sram_l_a[2]" LOC = "P195"; -NET "sram_l_a[1]" LOC = "P199"; -NET "sram_r_a[3]" LOC = "P64"; -NET "sram_r_a[5]" LOC = "P57"; -NET "sram_l_a[3]" LOC = "P194"; -NET "sram_r_a[10]" LOC = "P108"; -NET "sram_r_d[11]" LOC = "P85"; -NET "sram_r_d[13]" LOC = "P87"; -NET "sram_r_d[15]" LOC = "P94"; -NET "sram_r_d[14]" LOC = "P93"; -NET "sram_l_d[2]" LOC = "P205"; -NET "sram_r_a[7]" LOC = "P55"; -NET "sram_l_d[13]" LOC = "P222"; -NET "sram_r_a[6]" LOC = "P56"; -NET "sram_l_a[7]" LOC = "P189"; -NET "sram_l_d[0]" LOC = "P202"; -NET "sram_l_a[10]" LOC = "P238"; -NET "sram_l_d[11]" LOC = "P220"; -NET "sram_r_d[3]" LOC = "P73"; -NET "sram_r_a[0]" LOC = "P67"; -NET "sram_r_d[10]" LOC = "P84"; -NET "sram_l_d[15]" LOC = "P224"; -NET "sram_l_oen" LOC = "P228"; -NET "sram_r_a[1]" LOC = "P66"; -NET "sram_r_a[2]" LOC = "P65"; -NET "sram_r_a[8]" LOC = "P54"; -NET "sram_r_a[15]" LOC = "P100"; -NET "sram_r_a[12]" LOC = "P103"; -NET "sram_r_d[6]" LOC = "P79"; -NET "sram_l_a[8]" LOC = "P188"; -NET "sram_r_a[11]" LOC = "P107"; -NET "sram_r_a[14]" LOC = "P101"; -NET "sram_r_d[8]" LOC = "P81"; -NET "sram_l_a[11]" LOC = "P237"; -NET "sram_r_d[7]" LOC = "P80"; -NET "sram_l1_wen" LOC = "P9"; -NET "sram_r_a[9]" LOC = "P53"; -NET "sram_l_d[9]" LOC = "P217"; -NET "sram_r_a[13]" LOC = "P102"; -NET "sram_r_d[9]" LOC = "P82"; -NET "sram_l_a[9]" LOC = "P187"; -NET "sram_l_d[6]" LOC = "P209"; -NET "sram_l_a[12]" LOC = "P236"; -NET "sram_r_d[5]" LOC = "P78"; -NET "sram_r_oen" LOC = "P95"; -NET "sram_r_d[2]" LOC = "P72"; -NET "sram_l_d[12]" LOC = "P221"; -NET "sram_l_a[4]" LOC = "P193"; -NET "sram_r_a[4]" LOC = "P63"; -NET "sram_l_d[1]" LOC = "P203"; -NET "sram_r_d[1]" LOC = "P71"; -NET "sram_r_d[0]" LOC = "P70"; -NET "sram_l0_wen" LOC = "P201"; -NET "sram_l_d[7]" LOC = "P215"; -NET "sram_l_d[8]" LOC = "P216"; -NET "sram_l_d[4]" LOC = "P207"; -NET "sram_r_d[4]" LOC = "P74"; -NET "sram_l_d[5]" LOC = "P208"; -NET "sram_r_a[18]" LOC = "P96"; -NET "sram_r1_wen" LOC = "P68"; -NET "sram_r0_wen" LOC = "P10"; -NET "sram_l_a[13]" LOC = "P235"; -NET "sram_l_a[17]" LOC = "P230"; -NET "sram_r_cen" LOC = "P109"; -NET "sram_l_a[16]" LOC = "P231"; -NET "sram_r_a[16]" LOC = "P99"; -NET "sram_l_a[18]" LOC = "P229"; -NET "sram_l_a[14]" LOC = "P234"; -NET "sram_l_cen" LOC = "P186"; -NET "sram_l_a[15]" LOC = "P232"; -NET "sram_r_a[17]" LOC = "P97"; -NET "flash_a[15]" LOC = "P155"; -NET "flash_d[7]" LOC = "P124"; -NET "flash_a[17]" LOC = "P149"; -NET "flash_a[14]" LOC = "P159"; -NET "flash_a[4]" LOC = "P144"; -NET "flash_a[9]" LOC = "P160"; -NET "flash_a[5]" LOC = "P147"; -NET "flash_oen" LOC = "P173"; -NET "flash_a[18]" LOC = "P146"; -NET "flash_a[6]" LOC = "P152"; -NET "flash_a[8]" LOC = "P157"; -NET "flash_a[3]" LOC = "P141"; -NET "flash_d[1]" LOC = "P167"; -NET "flash_d[3]" LOC = "P156"; -NET "flash_d[0]" LOC = "P177"; -#NET "flash_rstn" LOC = "P????" -NET "flash_a[12]" LOC = "P168"; -NET "flash_a[7]" LOC = "P154"; -NET "flash_d[2]" LOC = "P163"; -NET "flash_d[4]" LOC = "P145"; -NET "flash_a[10]" LOC = "P162"; -NET "flash_a[16]" LOC = "P153"; -NET "flash_a[0]" LOC = "P132"; -NET "flash_a[13]" LOC = "P161"; -NET "flash_a[1]" LOC = "P133"; -NET "flash_a[11]" LOC = "P169"; -NET "flash_a[2]" LOC = "P139"; -NET "flash_d[5]" LOC = "P138"; -NET "flash_d[6]" LOC = "P134"; -NET "flash_a[20]" LOC = "P140"; -NET "flash_cen" LOC = "P170"; -NET "flash_wen" LOC = "P131"; -NET "flash_a[19]" LOC = "P142"; -NET "flash_a[15]" FAST; -NET "flash_d[7]" FAST; -NET "flash_a[17]" FAST; -NET "flash_a[14]" FAST; -NET "flash_a[4]" FAST; -NET "flash_a[9]" FAST; -NET "flash_a[5]" FAST; -NET "flash_oen" FAST; -NET "flash_a[18]" FAST; -NET "flash_a[6]" FAST; -NET "flash_a[8]" FAST; -NET "flash_a[3]" FAST; -NET "flash_d[1]" FAST; -NET "flash_d[3]" FAST; -NET "flash_d[0]" FAST; -#NET "flash_rstn" LOC = "P????" -NET "flash_a[12]" FAST; -NET "flash_a[7]" FAST; -NET "flash_d[2]" FAST; -NET "flash_d[4]" FAST; -NET "flash_a[10]" FAST; -NET "flash_a[16]" FAST; -NET "flash_a[0]" FAST; -NET "flash_a[13]" FAST; -NET "flash_a[1]" FAST; -NET "flash_a[11]" FAST; -NET "flash_a[2]" FAST; -NET "flash_d[5]" FAST; -NET "flash_d[6]" FAST; -NET "flash_a[20]" FAST; -NET "flash_cen" FAST; -NET "flash_wen" FAST; -NET "flash_a[19]" FAST; -NET "flash_a[15]" DRIVE = 24; -NET "flash_d[7]" DRIVE = 24; -NET "flash_a[17]" DRIVE = 24; -NET "flash_a[14]" DRIVE = 24; -NET "flash_a[4]" DRIVE = 24; -NET "flash_a[9]" DRIVE = 24; -NET "flash_a[5]" DRIVE = 24; -NET "flash_oen" DRIVE = 24; -NET "flash_a[18]" DRIVE = 24; -NET "flash_a[6]" DRIVE = 24; -NET "flash_a[8]" DRIVE = 24; -NET "flash_a[3]" DRIVE = 24; -NET "flash_d[1]" DRIVE = 24; -NET "flash_d[3]" DRIVE = 24; -NET "flash_d[0]" DRIVE = 24; -#NET "flash_rstn" LOC = "P????" -NET "flash_a[12]" DRIVE = 24; -NET "flash_a[7]" DRIVE = 24; -NET "flash_d[2]" DRIVE = 24; -NET "flash_d[4]" DRIVE = 24; -NET "flash_a[10]" DRIVE = 24; -NET "flash_a[16]" DRIVE = 24; -NET "flash_a[0]" DRIVE = 24; -NET "flash_a[13]" DRIVE = 24; -NET "flash_a[1]" DRIVE = 24; -NET "flash_a[11]" DRIVE = 24; -NET "flash_a[2]" DRIVE = 24; -NET "flash_d[5]" DRIVE = 24; -NET "flash_d[6]" DRIVE = 24; -NET "flash_a[20]" DRIVE = 24; -NET "flash_cen" DRIVE = 24; -NET "flash_wen" DRIVE = 24; -NET "flash_a[19]" DRIVE = 24; -NET "cpld_tdo" LOC = "P123"; -NET "cpld_tdo" DRIVE = 24; -NET "cpld_tdo" FAST; -NET "clk" TNM_NET = "clk"; -TIMESPEC "TS_clk" = PERIOD "clk" 45 ns HIGH 50 %; -#NET "sram_r_oen" OFFSET = OUT 10 ns AFTER "clk"; -#NET "sram_l_oen" OFFSET = OUT 10 ns AFTER "clk"; -#NET "sram_r0_wen" OFFSET = OUT 10 ns AFTER "clk"; -#NET "sram_r1_wen" OFFSET = OUT 10 ns AFTER "clk"; -INST "sram_l_a[0].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[1].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[2].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[3].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[4].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[5].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[6].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[7].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[8].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[9].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[10].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[11].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[12].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[13].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[14].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[15].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[16].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[17].PAD" TNM = "SRAM_TN"; -INST "sram_l_a[18].PAD" TNM = "SRAM_TN"; -INST "sram_l_cen.PAD" TNM = "SRAM_TN"; -INST "sram_l_d[0].PAD" TNM = "SRAM_TN"; -INST "sram_l_d[1].PAD" TNM = "SRAM_TN"; -INST "sram_l_d[2].PAD" TNM = "SRAM_TN"; -INST "sram_l_d[3].PAD" TNM = "SRAM_TN"; -INST "sram_l_d[4].PAD" TNM = "SRAM_TN"; -INST "sram_l_d[5].PAD" TNM = "SRAM_TN"; -INST "sram_l_d[6].PAD" TNM = "SRAM_TN"; -INST "sram_l_d[7].PAD" TNM = "SRAM_TN"; -INST "sram_l_d[8].PAD" TNM = "SRAM_TN"; -INST "sram_l_d[9].PAD" TNM = "SRAM_TN"; -INST "sram_l_d[10].PAD" TNM = "SRAM_TN"; -INST "sram_l_d[11].PAD" TNM = "SRAM_TN"; -INST "sram_l_d[12].PAD" TNM = "SRAM_TN"; -INST "sram_l_d[13].PAD" TNM = "SRAM_TN"; -INST "sram_l_d[14].PAD" TNM = "SRAM_TN"; -INST "sram_l_d[15].PAD" TNM = "SRAM_TN"; -INST "sram_l_oen.PAD" TNM = "SRAM_TN"; -INST "sram_l0_wen.PAD" TNM = "SRAM_TN"; -INST "sram_l1_wen.PAD" TNM = "SRAM_TN"; -INST "sram_r_a[0].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[1].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[2].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[3].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[4].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[5].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[6].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[7].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[8].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[9].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[10].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[11].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[12].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[13].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[14].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[15].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[16].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[17].PAD" TNM = "SRAM_TN"; -INST "sram_r_a[18].PAD" TNM = "SRAM_TN"; -INST "sram_r_cen.PAD" TNM = "SRAM_TN"; -INST "sram_r_d[0].PAD" TNM = "SRAM_TN"; -INST "sram_r_d[1].PAD" TNM = "SRAM_TN"; -INST "sram_r_d[2].PAD" TNM = "SRAM_TN"; -INST "sram_r_d[3].PAD" TNM = "SRAM_TN"; -INST "sram_r_d[4].PAD" TNM = "SRAM_TN"; -INST "sram_r_d[5].PAD" TNM = "SRAM_TN"; -INST "sram_r_d[6].PAD" TNM = "SRAM_TN"; -INST "sram_r_d[7].PAD" TNM = "SRAM_TN"; -INST "sram_r_d[8].PAD" TNM = "SRAM_TN"; -INST "sram_r_d[9].PAD" TNM = "SRAM_TN"; -INST "sram_r_d[10].PAD" TNM = "SRAM_TN"; -INST "sram_r_d[11].PAD" TNM = "SRAM_TN"; -INST "sram_r_d[12].PAD" TNM = "SRAM_TN"; -INST "sram_r_d[13].PAD" TNM = "SRAM_TN"; -INST "sram_r_d[14].PAD" TNM = "SRAM_TN"; -INST "sram_r_d[15].PAD" TNM = "SRAM_TN"; -INST "sram_r_oen.PAD" TNM = "SRAM_TN"; -INST "sram_r0_wen.PAD" TNM = "SRAM_TN"; -INST "sram_r1_wen.PAD" TNM = "SRAM_TN"; -#TIMEGRP "SRAM_TN" OFFSET = OUT 10 ns AFTER "clk"; -INST "sram/l_read[0]" TNM = "SRAM_DATA_IN"; -INST "sram/l_read[1]" TNM = "SRAM_DATA_IN"; -INST "sram/l_read[2]" TNM = "SRAM_DATA_IN"; -INST "sram/l_read[3]" TNM = "SRAM_DATA_IN"; -INST "sram/l_read[4]" TNM = "SRAM_DATA_IN"; -INST "sram/l_read[5]" TNM = "SRAM_DATA_IN"; -INST "sram/l_read[6]" TNM = "SRAM_DATA_IN"; -INST "sram/l_read[7]" TNM = "SRAM_DATA_IN"; -INST "sram/l_read[8]" TNM = "SRAM_DATA_IN"; -INST "sram/l_read[9]" TNM = "SRAM_DATA_IN"; -INST "sram/l_read[10]" TNM = "SRAM_DATA_IN"; -INST "sram/l_read[11]" TNM = "SRAM_DATA_IN"; -INST "sram/l_read[12]" TNM = "SRAM_DATA_IN"; -INST "sram/l_read[13]" TNM = "SRAM_DATA_IN"; -INST "sram/l_read[14]" TNM = "SRAM_DATA_IN"; -INST "sram/l_read[15]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[0]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[1]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[2]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[3]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[4]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[5]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[6]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[7]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[8]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[9]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[10]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[11]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[12]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[13]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[14]" TNM = "SRAM_DATA_IN"; -INST "sram/r_read[15]" TNM = "SRAM_DATA_IN"; -#TIMESPEC "TS_PAD_SRAM_TO_SRAM_DATA_LATCH" = FROM "SRAM_TN" TO "SRAM_DATA_IN" 4 ns; Index: synplify/xfpga_top.prd =================================================================== --- synplify/xfpga_top.prd (revision 1765) +++ synplify/xfpga_top.prd (nonexistent) @@ -1,13 +0,0 @@ -#-- Synplicity, Inc. -#-- Version 7.0 Beta3 -#-- Project file G:\mp3\simon\or1k\mp3\syn\synplify\xfpga_top.prd -#-- Written on Mon Nov 05 10:27:17 2001 - -# -### Watch Implementation type ### -# -watch_impl -active -# -### Watch Implementation properties ### -# -watch_prop -clear

synplify/xfpga_top.prd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: design_compiler/run/dodesign =================================================================== --- design_compiler/run/dodesign (revision 1765) +++ design_compiler/run/dodesign (nonexistent) @@ -1,5 +0,0 @@ -#!/bin/sh -f - -# nohup dc_shell -f ../bin/top.scr | tee ../log/top.log -dc_shell -f ../bin/top.scr > ../log/top.log -mv command.log ../log

design_compiler/run/dodesign Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: design_compiler/out/README =================================================================== --- design_compiler/out/README (revision 1765) +++ design_compiler/out/README (nonexistent) @@ -1 +0,0 @@ -This directory containts gate-level netlists. Index: design_compiler/bin/cons_vs_umc18.inc =================================================================== --- design_compiler/bin/cons_vs_umc18.inc (revision 1765) +++ design_compiler/bin/cons_vs_umc18.inc (nonexistent) @@ -1,50 +0,0 @@ -/* Constraints */ -CLK_UNCERTAINTY = 0.1 /* 100 ps */ -DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */ -DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */ - -/* Clocks constraints */ -create_clock CLK -period CLK_PERIOD -set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY -set_dont_touch_network all_clocks() - -/* Reset constraints */ -set_driving_cell -none RST -set_drive 0 RST -set_dont_touch_network RST - -/* All inputs except reset and clock */ -all_inputs_wo_rst_clk = all_inputs() - CLK - RST - -/* Set output delays and load for output signals - * - * All outputs are assumed to go directly into - * external flip-flops for the purpose of this - * synthesis - */ -set_output_delay DFFPQ2_SETUP -clock CLK all_outputs() -set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs() - -/* Input delay and driving cell of all inputs - * - * All these signals are assumed to come directly from - * flip-flops for the purpose of this synthesis - * - */ -set_input_delay DFFPQ2_CKQ -clock CLK all_inputs_wo_rst_clk -set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk - -/* Set design fanout */ -/* -set_max_fanout 10 TOPLEVEL -*/ - -/* Set area constraint */ -set_max_area MAX_AREA - -/* Optimize all near-critical paths to give extra slack for layout */ -c_range = CLK_PERIOD * 0.1 -group_path -critical_range c_range -name CLK -to CLK - -/* Operating conditions */ -set_operating_conditions TYPICAL Index: design_compiler/bin/save_design.inc =================================================================== --- design_compiler/bin/save_design.inc (revision 1765) +++ design_compiler/bin/save_design.inc (nonexistent) @@ -1,5 +0,0 @@ -/* Save current design using synopsys format */ -write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db - -/* Save current design using verilog format */ -write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v Index: design_compiler/bin/tech_vs_umc18.inc =================================================================== --- design_compiler/bin/tech_vs_umc18.inc (revision 1765) +++ design_compiler/bin/tech_vs_umc18.inc (nonexistent) @@ -1,16 +0,0 @@ -/* Set Virtual Silicon UMC 0.18u standard cell library */ - -search_path = {. /libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ } -snps = get_unix_variable("SYNOPSYS") -synthetic_library = { \ - snps + "/libraries/syn/dw01.sldb" \ - snps + "/libraries/syn/dw02.sldb" \ - snps + "/libraries/syn/dw03.sldb" \ - snps + "/libraries/syn/dw04.sldb" \ - snps + "/libraries/syn/dw05.sldb" \ - snps + "/libraries/syn/dw06.sldb" \ - snps + "/libraries/syn/dw07.sldb" } -target_library = { umcl18u250t2_typ.db } -link_library = target_library + synthetic_library -symbol_library = { umcl18u250t2.sdb } - Index: design_compiler/bin/reports.inc =================================================================== --- design_compiler/bin/reports.inc (revision 1765) +++ design_compiler/bin/reports.inc (nonexistent) @@ -1,10 +0,0 @@ -/* Basic reports */ -report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log -report_timing -nworst 10 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log -report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log -report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log -report_constraint > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log -/* -report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log -*/ - Index: design_compiler/bin/top.scr =================================================================== --- design_compiler/bin/top.scr (revision 1765) +++ design_compiler/bin/top.scr (nonexistent) @@ -1,64 +0,0 @@ -/* - * User defines for synthesizing RTC IP core - * - */ -TOPLEVEL = xfpga_top -include ../bin/select_tech.inc -CLK = clk -RST = rstn -CLK_PERIOD = 5 /* 200 MHz */ -MAX_AREA = 0 /* Push hard */ -DO_UNGROUP = yes /* yes, no */ -DO_VERIFY = yes /* yes, no */ - -/* Starting timestamp */ -sh date - -/* Set some basic variables related to environment */ -include ../bin/set_env.inc -STAGE = final - -/* Load libraries */ -include ../bin/tech_ + TECH + .inc - -/* Load HDL source files */ -include ../bin/read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log - -/* Set design top */ -current_design TOPLEVEL - -/* Link all blocks and uniquify them */ -link -uniquify -check_design > LOG_PATH + check_design_ + TOPLEVEL + .log - -/* Apply constraints */ -if (TECH == "vs_umc18") { - include ../bin/cons_vs_umc18.inc -} else if (TECH == "art_umc18") { - include ../bin/cons_art_umc18.inc -} else { - echo "Error: Unsupported technology" - exit -} - -/* Lets do basic synthesis */ -if (DO_UNGROUP == "yes") { - ungroup -all -} -compile -boundary_optimization -map_effort low - -/* Dump gate-level from incremental synthesis */ -include ../bin/save_design.inc - -/* Generate reports for incremental synthesis */ -include ../bin/reports.inc - -/* Verify design */ -if (DO_VERIFY == "yes") { - compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log -} - -/* Finish */ -sh date -exit Index: design_compiler/bin/select_tech.inc =================================================================== --- design_compiler/bin/select_tech.inc (revision 1765) +++ design_compiler/bin/select_tech.inc (nonexistent) @@ -1,5 +0,0 @@ -/* Defaults */ - -TECH = vs_umc18 /* vs_umc18, art_umc18 */ -CLK_PERIOD = 5 /* 200 MHz */ -MAX_AREA = 0 /* Push hard */ Index: design_compiler/bin/set_env.inc =================================================================== --- design_compiler/bin/set_env.inc (revision 1765) +++ design_compiler/bin/set_env.inc (nonexistent) @@ -1,20 +0,0 @@ -/* Enable Verilog HDL preprocessor */ -hdlin_enable_vpp = true - -/* Set log path */ -LOG_PATH = "../log/" - -/* Set gate-level netlist path */ -GATE_PATH = "../out/" - -/* Set RAMS_PATH */ -RAMS_PATH = "../../../lib/" - -/* Set RTL source path */ -RTL_PATH = { "../../../rtl/verilog/", "../../../rtl/verilog/audio/", \ - "../../../rtl/verilog/dbg_interface/", "../../../rtl/verilog/or1200/", \ - "../../../rtl/verilog/mem_if/", "../../../rtl/verilog/ssvga/" } - -/* Optimize adders */ -synlib_model_map_effort = high -hlo_share_effort = medium Index: design_compiler/bin/read_design.inc =================================================================== --- design_compiler/bin/read_design.inc (revision 1765) +++ design_compiler/bin/read_design.inc (nonexistent) @@ -1,87 +0,0 @@ -/* Set search path for verilog include files */ -search_path = search_path + RTL_PATH + { GATE_PATH } - -/* Read verilog files of the RTC IP core */ -if (TOPLEVEL == "xfpga_top") { - read -f verilog tcop_top.v - read -f verilog xfpga_top.v - - read -f verilog audio_codec_if.v - read -f verilog audio_top.v - read -f verilog audio_wb_if.v - read -f verilog fifo_4095_16.v - read -f verilog fifo_empty_16.v - - read -f verilog dbg_crc8_d1.v - read -f verilog dbg_defines.v - read -f verilog dbg_register.v - read -f verilog dbg_registers.v - read -f verilog dbg_sync_clk1_clk2.v - read -f verilog dbg_timescale.v - read -f verilog dbg_top.v - read -f verilog dbg_trace.v - - read -f verilog flash_top.v - read -f verilog sram_top.v - - read -f verilog alu.v - read -f verilog cfgr.v - read -f verilog cpu.v - read -f verilog dc.v - read -f verilog dc_fsm.v - read -f verilog dc_ram.v - read -f verilog dc_tag.v - read -f verilog defines.v - read -f verilog dmmu.v - read -f verilog dtlb.v - read -f verilog du.v - read -f verilog except.v - read -f verilog frz_logic.v - read -f verilog generic_dpram_32x32.v - read -f verilog generic_multp2_32x32.v - read -f verilog generic_spram_2048x32.v - read -f verilog generic_spram_2048x8.v - read -f verilog generic_spram_512x19.v - read -f verilog generic_spram_512x20.v - read -f verilog generic_spram_64x14.v - read -f verilog generic_spram_64x21.v - read -f verilog generic_spram_64x23.v - read -f verilog generic_spram_64x37.v - read -f verilog generic_tpram_32x32.v - read -f verilog ic.v - read -f verilog ic_fsm.v - read -f verilog ic_ram.v - read -f verilog ic_tag.v - read -f verilog id.v - read -f verilog ifetch.v - read -f verilog immu.v - read -f verilog itlb.v - read -f verilog lsu.v - read -f verilog mem2reg.v - read -f verilog mult_mac.v - read -f verilog operandmuxes.v - read -f verilog or1200.v - read -f verilog pic.v - read -f verilog pm.v - read -f verilog reg2mem.v - read -f verilog rf.v - read -f verilog sprs.v - read -f verilog tt.v - read -f verilog wb_biu.v - read -f verilog wbmux.v - - read -f verilog xcv_ram32x8d.v - - read -f verilog crtc_iob.v - read -f verilog ssvga_crtc.v - read -f verilog ssvga_defines.v - read -f verilog ssvga_fifo.v - read -f verilog ssvga_top.v - read -f verilog ssvga_wbm_if.v - read -f verilog ssvga_wbs_if.v - -} else { - echo "Non-existing top level." - exit -} - Index: design_compiler/bin/cons_art_umc18.inc =================================================================== --- design_compiler/bin/cons_art_umc18.inc (revision 1765) +++ design_compiler/bin/cons_art_umc18.inc (nonexistent) @@ -1,50 +0,0 @@ -/* Constraints */ -CLK_UNCERTAINTY = 0.1 /* 100 ps */ -DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */ -DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */ - -/* Clocks constraints */ -create_clock CLK -period CLK_PERIOD -set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY -set_dont_touch_network all_clocks() - -/* Reset constraints */ -set_driving_cell -none RST -set_drive 0 RST -set_dont_touch_network RST - -/* All inputs except reset and clock */ -all_inputs_wo_rst_clk = all_inputs() - CLK - RST - -/* Set output delays and load for output signals - * - * All outputs are assumed to go directly into - * external flip-flops for the purpose of this - * synthesis - */ -set_output_delay DFFHQX2_SETUP -clock CLK all_outputs() -set_load load_of(typical/DFFHQX2/D) * 1 all_outputs() - -/* Input delay and driving cell of all inputs - * - * All these signals are assumed to come directly from - * flip-flops for the purpose of this synthesis - * - */ -set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk -set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk - -/* Set design fanout */ -/* -set_max_fanout 10 TOPLEVEL -*/ - -/* Set area constraint */ -set_max_area MAX_AREA - -/* Optimize all near-critical paths to give extra slack for layout */ -c_range = CLK_PERIOD * 0.05 -group_path -critical_range c_range -name CLK -to CLK - -/* Operating conditions */ -set_operating_conditions typical Index: design_compiler/bin/tech_art_umc18.inc =================================================================== --- design_compiler/bin/tech_art_umc18.inc (revision 1765) +++ design_compiler/bin/tech_art_umc18.inc (nonexistent) @@ -1,17 +0,0 @@ -/* Set Artisan Sage-X UMC 0.18u standard cell library */ - -search_path = {. /libs/Artisan/aci/sc-x/synopsys/ } + \ - { /libs/Artisan/aci/sc-x/symbols/synopsys/ } -snps = get_unix_variable("SYNOPSYS") -synthetic_library = { \ - snps + "/libraries/syn/dw01.sldb" \ - snps + "/libraries/syn/dw02.sldb" \ - snps + "/libraries/syn/dw03.sldb" \ - snps + "/libraries/syn/dw04.sldb" \ - snps + "/libraries/syn/dw05.sldb" \ - snps + "/libraries/syn/dw06.sldb" \ - snps + "/libraries/syn/dw07.sldb" } -target_library = { typical.db } -link_library = target_library + synthetic_library -symbol_library = { umc18.sdb } -