Subversion Repositories or1k

or32/generate.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: or32/Makefile.in =================================================================== --- or32/Makefile.in (nonexistent) +++ or32/Makefile.in (revision 1765) @@ -0,0 +1,368 @@ +# Makefile.in generated by automake 1.6.3 from Makefile.am. +# @configure_input@ + +# Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 +# Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + +# Makefile -- Makefile for OR32 dependent simulation +# Copyright (C) 1999 Damjan Lampret, lampret@opencores.org +# +# This file is part of OpenRISC 1000 Architectural Simulator. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +SHELL = @SHELL@ + +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +VPATH = @srcdir@ +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +bindir = @bindir@ +sbindir = @sbindir@ +libexecdir = @libexecdir@ +datadir = @datadir@ +sysconfdir = @sysconfdir@ +sharedstatedir = @sharedstatedir@ +localstatedir = @localstatedir@ +libdir = @libdir@ +infodir = @infodir@ +mandir = @mandir@ +includedir = @includedir@ +oldincludedir = /usr/include +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +top_builddir = ../.. + +ACLOCAL = @ACLOCAL@ +AUTOCONF = @AUTOCONF@ +AUTOMAKE = @AUTOMAKE@ +AUTOHEADER = @AUTOHEADER@ + +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +INSTALL = @INSTALL@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_DATA = @INSTALL_DATA@ +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +INSTALL_HEADER = $(INSTALL_DATA) +transform = @program_transform_name@ +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_alias = @build_alias@ +build_triplet = @build@ +host_alias = @host_alias@ +host_triplet = @host@ +target_alias = @target_alias@ +target_triplet = @target@ + +EXEEXT = @EXEEXT@ +OBJEXT = @OBJEXT@ +PATH_SEPARATOR = @PATH_SEPARATOR@ +AMTAR = @AMTAR@ +AR = @AR@ +ARFLAGS = @ARFLAGS@ +AWK = @AWK@ +BUILD_DIR = @BUILD_DIR@ +CC = @CC@ +CFLAGS = @CFLAGS@ +CPU_ARCH = @CPU_ARCH@ +DEPDIR = @DEPDIR@ +INCLUDES = @INCLUDES@ +INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ +LOCAL_CFLAGS = @LOCAL_CFLAGS@ +LOCAL_DEFS = @LOCAL_DEFS@ +MAKE_SHELL = @MAKE_SHELL@ +PACKAGE = @PACKAGE@ +RANLIB = @RANLIB@ +STRIP = @STRIP@ +SUMVERSION = @SUMVERSION@ +TERMCAP_LIB = @TERMCAP_LIB@ +VERSION = @VERSION@ +am__include = @am__include@ +am__quote = @am__quote@ +host = @host@ +host_cpu = @host_cpu@ +host_os = @host_os@ +install_sh = @install_sh@ + +noinst_LIBRARIES = libarch.a +libarch_a_SOURCES = execute.c or32.c + +@SIMPLE_EXECUTION_TRUE@noinst_PROGRAMS = +@SIMPLE_EXECUTION_FALSE@noinst_PROGRAMS = generate +@SIMPLE_EXECUTION_TRUE@generate_SOURCES = +@SIMPLE_EXECUTION_FALSE@generate_SOURCES = or32.c generate.c +@SIMPLE_EXECUTION_FALSE@BUILT_SOURCES = execgen.c + +# If the simulator was first built without --enable-simple and then with it, +# then also remove these two files +CLEANFILES = execgen.c generate +subdir = cpu/or32 +mkinstalldirs = $(SHELL) $(top_srcdir)/mkinstalldirs +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +LIBRARIES = $(noinst_LIBRARIES) + +libarch_a_AR = $(AR) cru +libarch_a_LIBADD = +am_libarch_a_OBJECTS = execute.$(OBJEXT) or32.$(OBJEXT) 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$(generate_SOURCES) +DIST_COMMON = Makefile.am Makefile.in +SOURCES = $(libarch_a_SOURCES) $(generate_SOURCES) + +all: $(BUILT_SOURCES) + $(MAKE) $(AM_MAKEFLAGS) all-am + +.SUFFIXES: +.SUFFIXES: .c .o .obj +$(srcdir)/Makefile.in: Makefile.am $(top_srcdir)/configure.in $(ACLOCAL_M4) + cd $(top_srcdir) && \ + $(AUTOMAKE) --gnu cpu/or32/Makefile +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe) + +clean-noinstLIBRARIES: + -test -z "$(noinst_LIBRARIES)" || rm -f $(noinst_LIBRARIES) +libarch.a: $(libarch_a_OBJECTS) $(libarch_a_DEPENDENCIES) + -rm -f libarch.a + $(libarch_a_AR) libarch.a $(libarch_a_OBJECTS) $(libarch_a_LIBADD) + $(RANLIB) libarch.a + +clean-noinstPROGRAMS: + -test -z "$(noinst_PROGRAMS)" || rm -f $(noinst_PROGRAMS) +generate$(EXEEXT): $(generate_OBJECTS) $(generate_DEPENDENCIES) + @rm -f generate$(EXEEXT) + $(LINK) $(generate_LDFLAGS) $(generate_OBJECTS) $(generate_LDADD) $(LIBS) + +mostlyclean-compile: + -rm -f *.$(OBJEXT) core *.core + +distclean-compile: + -rm -f *.tab.c + +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/execute.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/generate.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/or32.Po@am__quote@ + +distclean-depend: + -rm -rf ./$(DEPDIR) + +.c.o: +@AMDEP_TRUE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@ depfile='$(DEPDIR)/$*.Po' tmpdepfile='$(DEPDIR)/$*.TPo' @AMDEPBACKSLASH@ +@AMDEP_TRUE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ + $(COMPILE) -c `test -f '$<' || echo '$(srcdir)/'`$< + +.c.obj: +@AMDEP_TRUE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@ depfile='$(DEPDIR)/$*.Po' tmpdepfile='$(DEPDIR)/$*.TPo' @AMDEPBACKSLASH@ +@AMDEP_TRUE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ + $(COMPILE) -c `cygpath -w $<` +CCDEPMODE = @CCDEPMODE@ +uninstall-info-am: + +ETAGS = etags +ETAGSFLAGS = + +tags: TAGS + +ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES) + list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ + unique=`for i in $$list; do \ + if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ + done | \ + $(AWK) ' { files[$$0] = 1; } \ + END { for (i in files) print i; }'`; \ + mkid -fID $$unique + +TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \ + $(TAGS_FILES) $(LISP) + tags=; \ + here=`pwd`; \ + list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ + unique=`for i in $$list; do \ + if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ + done | \ + $(AWK) ' { files[$$0] = 1; } \ + END { for (i in files) print i; }'`; \ + test -z "$(ETAGS_ARGS)$$tags$$unique" \ + || $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \ + $$tags $$unique + +GTAGS: + here=`$(am__cd) $(top_builddir) && pwd` \ + && cd $(top_srcdir) \ + && gtags -i $(GTAGS_ARGS) $$here + +distclean-tags: + -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH +DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) + +top_distdir = ../.. +distdir = $(top_distdir)/$(PACKAGE)-$(VERSION) + +distdir: $(DISTFILES) + @list='$(DISTFILES)'; for file in $$list; do \ + if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ + dir=`echo "$$file" | sed -e 's,/[^/]*$$,,'`; \ + if test "$$dir" != "$$file" && test "$$dir" != "."; then \ + dir="/$$dir"; \ + $(mkinstalldirs) "$(distdir)$$dir"; \ + else \ + dir=''; \ + fi; \ + if test -d $$d/$$file; then \ + if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ + cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \ + fi; \ + cp -pR $$d/$$file $(distdir)$$dir || exit 1; \ + else \ + test -f $(distdir)/$$file \ + || cp -p $$d/$$file $(distdir)/$$file \ + || exit 1; \ + fi; \ + done +check-am: all-am +check: check-am +all-am: Makefile $(LIBRARIES) $(PROGRAMS) + +installdirs: + +install: install-am +install-exec: install-exec-am +install-data: install-data-am +uninstall: uninstall-am + +install-am: all-am + @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am + +installcheck: installcheck-am +install-strip: + $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ + INSTALL_STRIP_FLAG=-s \ + `test -z '$(STRIP)' || \ + echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install +mostlyclean-generic: + +clean-generic: + -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES) + +distclean-generic: + -rm -f Makefile $(CONFIG_CLEAN_FILES) + +maintainer-clean-generic: + @echo "This command is intended for maintainers to use" + @echo "it deletes files that may require special tools to rebuild." + -test -z "$(BUILT_SOURCES)" || rm -f $(BUILT_SOURCES) +clean: clean-am + +clean-am: clean-generic clean-noinstLIBRARIES clean-noinstPROGRAMS \ + mostlyclean-am + +distclean: distclean-am + +distclean-am: clean-am distclean-compile distclean-depend \ + distclean-generic distclean-tags + +dvi: dvi-am + +dvi-am: + +info: info-am + +info-am: + +install-data-am: + +install-exec-am: + +install-info: install-info-am + +install-man: + +installcheck-am: + +maintainer-clean: maintainer-clean-am + +maintainer-clean-am: distclean-am maintainer-clean-generic + +mostlyclean: mostlyclean-am + +mostlyclean-am: mostlyclean-compile mostlyclean-generic + +uninstall-am: uninstall-info-am + +.PHONY: GTAGS all all-am check check-am clean clean-generic \ + clean-noinstLIBRARIES clean-noinstPROGRAMS distclean \ + distclean-compile distclean-depend distclean-generic \ + distclean-tags distdir dvi dvi-am info info-am install \ + install-am install-data install-data-am install-exec \ + install-exec-am install-info install-info-am install-man \ + install-strip installcheck installcheck-am installdirs \ + maintainer-clean maintainer-clean-generic mostlyclean \ + mostlyclean-compile mostlyclean-generic tags uninstall \ + uninstall-am uninstall-info-am + + +@SIMPLE_EXECUTION_FALSE@execgen.c: generate $(srcdir)/insnset.c +@SIMPLE_EXECUTION_FALSE@ ./generate $(srcdir)/insnset.c execgen.c +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: Index: or32 =================================================================== --- or32 (nonexistent) +++ or32 (revision 1765)

or32 Property changes : Added: svn:ignore ## -0,0 +1,3 ## +Makefile +.deps +generate Index: common/stats.c =================================================================== --- common/stats.c (nonexistent) +++ common/stats.c (revision 1765) @@ -0,0 +1,293 @@ +/* stats.c -- Various statistics about instruction scheduling etc. + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include +#include +#include + +#include "config.h" + +#ifdef HAVE_INTTYPES_H +#include +#endif + +#include "port.h" +#include "arch.h" +#include "abstract.h" +#include "sim-config.h" +#include "spr_defs.h" +#include "opcode/or32.h" +#include "execute.h" +#include "sprs.h" +#include "debug.h" +#include "stats.h" + +struct branchstat { + int taken; + int nottaken; + int forward; + int backward; +}; + +/* See also enum insn_type in abstract.h */ +const char func_unit_str[30][30] = { "unknown", "exception", "arith", "shift", "compare", + "branch", "jump", "load", "store", "movimm", "move", "extend", "nop", "mac" }; + +struct dstats_entry dstats[DSTATS_LEN]; /* dependency stats */ +struct sstats_entry sstats[SSTATS_LEN]; /* single stats */ +struct fstats_entry fstats[FSTATS_LEN]; /* functional units stats */ +struct mstats_entry or1k_mstats = {0}; /* misc units stats */ +struct cachestats_entry ic_stats = {0}; /* instruction cache stats */ +struct cachestats_entry dc_stats = {0}; /* data cache stats */ +struct immustats_entry immu_stats = {0}; /* insn mmu stats */ +struct dmmustats_entry dmmu_stats = {0}; /* data mmu stats */ +struct raw_stats raw_stats; /* RAW hazard stats */ + +void addsstats(int item, int cnt_dynamic) +{ + int i = 0; + + while(sstats[i].insn != item && sstats[i].insn >= 0 && i < SSTATS_LEN) i++; + + if (i >= SSTATS_LEN - 1) return; + + if (sstats[i].insn >= 0) { + sstats[i].cnt_dynamic += cnt_dynamic; + } else { + sstats[i].insn = item; + sstats[i].cnt_dynamic = cnt_dynamic; + } +} + +void adddstats(int item1, int item2, int cnt_dynamic, int depend) +{ + int i = 0; + + debug(7,"adddstats start\n"); + + while((dstats[i].insn1 != item1 || dstats[i].insn2 != item2) && (i < DSTATS_LEN) && dstats[i].insn1 >= 0) i++; + + if (i >= DSTATS_LEN - 1) return; + + if (dstats[i].insn1 >= 0) { + dstats[i].cnt_dynamic += cnt_dynamic; + dstats[i].depend += depend; + } else { + dstats[i].insn1 = item1; + dstats[i].insn2 = item2; + dstats[i].cnt_dynamic = cnt_dynamic; + dstats[i].depend = depend; + } +} + +void addfstats(enum insn_type item1, enum insn_type item2, int cnt_dynamic, int depend) +{ + int i = 0; + + while(((fstats[i].insn1 != item1) || (fstats[i].insn2 != item2)) && + (fstats[i].insn1 != it_unknown) && + (i < FSTATS_LEN)) + i++; + + if (i >= FSTATS_LEN - 1) return; + + if ((fstats[i].insn1 == item1) && + (fstats[i].insn2 == item2)) { + fstats[i].cnt_dynamic += cnt_dynamic; + fstats[i].depend += depend; + } + else { + fstats[i].insn1 = item1; + fstats[i].insn2 = item2; + fstats[i].cnt_dynamic = cnt_dynamic; + fstats[i].depend = depend; + } +} + +void initstats() +{ + int i; + memset(sstats, 0, sizeof(sstats)); + for (i = 0; i < SSTATS_LEN; i++) + sstats[i].insn = -1; + memset(dstats, 0, sizeof(dstats)); + for (i = 0; i < DSTATS_LEN; i++) + dstats[i].insn1 = dstats[i].insn2 = -1; + memset(fstats, 0, sizeof(fstats)); + memset(&or1k_mstats, 0, sizeof(or1k_mstats)); + memset(&ic_stats, 0, sizeof(ic_stats)); + memset(&dc_stats, 0, sizeof(dc_stats)); + memset(&raw_stats, 0, sizeof(raw_stats)); +} + +void printotherstats(int which) +{ + PRINTF ("\n"); + if (config.bpb.enabled) { + struct branchstat bf; + struct branchstat bnf; + long bf_all, bnf_all; + bf.taken = or1k_mstats.bf[1][0] + or1k_mstats.bf[1][1]; + bf.nottaken = or1k_mstats.bf[0][0] + or1k_mstats.bf[0][1]; + bf.forward = or1k_mstats.bf[0][1] + or1k_mstats.bf[1][1]; + bf.backward = or1k_mstats.bf[0][0] + or1k_mstats.bf[1][0]; + bf_all = bf.forward + bf.backward; + + bnf.taken = or1k_mstats.bnf[1][0] + or1k_mstats.bf[1][1]; + bnf.nottaken = or1k_mstats.bnf[0][0] + or1k_mstats.bf[0][1]; + bnf.forward = or1k_mstats.bnf[0][1] + or1k_mstats.bf[1][1]; + bnf.backward = or1k_mstats.bnf[0][0] + or1k_mstats.bf[1][0]; + bnf_all = bnf.forward + bnf.backward; + + PRINTF("bnf: %d (%ld%%) taken,", bf.taken, (bf.taken * 100) / SD(bf_all)); + PRINTF(" %d (%ld%%) not taken,", bf.nottaken, (bf.nottaken * 100) / SD(bf_all)); + PRINTF(" %d (%ld%%) forward,", bf.forward, (bf.forward * 100) / SD(bf_all)); + PRINTF(" %d (%ld%%) backward\n", bf.backward, (bf.backward * 100) / SD(bf_all)); + PRINTF("bf: %d (%ld%%) taken,", bnf.taken, (bnf.taken * 100) / SD(bnf_all)); + PRINTF(" %d (%ld%%) not taken,", bnf.nottaken, (bnf.nottaken * 100) / SD(bnf_all)); + PRINTF(" %d (%ld%%) forward,", bnf.forward, (bnf.forward * 100) / SD(bnf_all)); + PRINTF(" %d (%ld%%) backward\n", bnf.backward, (bnf.backward * 100) / SD(bnf_all)); + + PRINTF("StaticBP bnf(%s): correct %ld%%\n", config.bpb.sbp_bnf_fwd ? "forward" : "backward", + (or1k_mstats.bnf[0][config.bpb.sbp_bnf_fwd] * 100) / SD(bnf_all)); + PRINTF("StaticBP bf(%s): correct %ld%%\n", config.bpb.sbp_bf_fwd ? "forward" : "backward", + (or1k_mstats.bnf[1][config.bpb.sbp_bf_fwd] * 100) / SD(bf_all)); + PRINTF("BPB: hit %d (correct %d%%), miss %d\n", or1k_mstats.bpb.hit, (or1k_mstats.bpb.correct * 100) / SD(or1k_mstats.bpb.hit), or1k_mstats.bpb.miss); + } else + PRINTF("BPB simulation disabled. Enable it to see BPB analysis\n"); + + if (config.bpb.btic) { + PRINTF("BTIC: hit %d(%d%%), miss %d\n", or1k_mstats.btic.hit, (or1k_mstats.btic.hit * 100) / SD(or1k_mstats.btic.hit + or1k_mstats.btic.miss), or1k_mstats.btic.miss); + } else + PRINTF("BTIC simulation disabled. Enabled it to see BTIC analysis\n"); + + if (config.ic.enabled) { + PRINTF("IC read: hit %d(%d%%), miss %d\n", ic_stats.readhit, (ic_stats.readhit * 100) / SD(ic_stats.readhit + ic_stats.readmiss), ic_stats.readmiss); + } else + PRINTF("No ICache. Enable it to see IC results.\n"); + + if (config.dc.enabled) { + PRINTF("DC read: hit %d(%d%%), miss %d\n", dc_stats.readhit, (dc_stats.readhit * 100) / SD(dc_stats.readhit + dc_stats.readmiss), dc_stats.readmiss); + PRINTF("DC write: hit %d(%d%%), miss %d\n", dc_stats.writehit, (dc_stats.writehit * 100) / SD(dc_stats.writehit + dc_stats.writemiss), dc_stats.writemiss); + } else + PRINTF("No DCache. Enable it to see DC results.\n"); + + if (cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP) { + PRINTF("IMMU read: hit %d(%d%%), miss %d\n", immu_stats.fetch_tlbhit, (immu_stats.fetch_tlbhit * 100) / SD(immu_stats.fetch_tlbhit + immu_stats.fetch_tlbmiss), immu_stats.fetch_tlbmiss); + } else + PRINTF("No IMMU. Set UPR[IMP]\n"); + + if (cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP) { + PRINTF("DMMU read: hit %d(%d%%), miss %d\n", dmmu_stats.loads_tlbhit, (dmmu_stats.loads_tlbhit * 100) / SD(dmmu_stats.loads_tlbhit + dmmu_stats.loads_tlbmiss), dmmu_stats.loads_tlbmiss); + } else + PRINTF("No DMMU. Set UPR[DMP]\n"); + + PRINTF("Additional LOAD CYCLES: %u STORE CYCLES: %u\n", runtime.sim.loadcycles, runtime.sim.storecycles); +} + +void printstats(int which) +{ + int i, all = 0, dependall = 0; + + if (which > 1 && which <= 5 && !config.cpu.dependstats) { + PRINTF("Hazard analysis disabled. Enable it to see analysis results.\n"); + return; + } + + switch (which) { + case 1: + PRINTF("stats 1: Misc stats\n"); + printotherstats(which); + break; + case 2: + PRINTF ("stats 2: Instruction usage\n"); + for(i = 0; i < SSTATS_LEN; i++) + all += sstats[i].cnt_dynamic; + + for(i = 0; i < SSTATS_LEN; i++) + if (sstats[i].cnt_dynamic) + PRINTF(" %-15s used %6dx (%5.1f%%)\n", insn_name(sstats[i].insn), sstats[i].cnt_dynamic, (sstats[i].cnt_dynamic * 100.)/SD(all)); + + PRINTF("%d instructions (dynamic, single stats)\n", all); + break; + + case 3: + PRINTF ("stats 3: Instruction dependencies\n"); + for(i = 0; i < DSTATS_LEN; i++) { + all += dstats[i].cnt_dynamic; + dependall += dstats[i].depend; + } + + for(i = 0; i < DSTATS_LEN; i++) + if (dstats[i].cnt_dynamic) { + char temp[100]; + sprintf(temp, "%s, %s ", insn_name(dstats[i].insn1), insn_name(dstats[i].insn2)); + PRINTF(" %-30s %6dx (%5.1f%%)", temp, dstats[i].cnt_dynamic, (dstats[i].cnt_dynamic * 100.)/SD(all)); + PRINTF(" depend: %5.1f%%\n", (dstats[i].depend * 100.) / dstats[i].cnt_dynamic); + } + + PRINTF("%d instructions (dynamic, dependency stats) depend: %d%%\n", all, (dependall * 100) / SD(all)); + break; + + case 4: + PRINTF("stats 4: Functional units dependencies\n"); + for(i = 0; i < FSTATS_LEN; i++) { + all += fstats[i].cnt_dynamic; + dependall += fstats[i].depend; + } + + for(i = 0; i < FSTATS_LEN; i++) + if (fstats[i].cnt_dynamic) { + char temp[100]; + sprintf(temp, "%s, %s", func_unit_str[fstats[i].insn1], func_unit_str[fstats[i].insn2]); + PRINTF(" %-30s %6dx (%5.1f%%)", temp, fstats[i].cnt_dynamic, (fstats[i].cnt_dynamic * 100.)/SD(all)); + PRINTF(" depend: %5.1f%%\n", (fstats[i].depend * 100.) / fstats[i].cnt_dynamic); + } + PRINTF ("%d instructions (dynamic, functional units stats) depend: %d%%\n\n", all, (dependall * 100) / SD(all)); + break; + + case 5: + PRINTF("stats 5: Raw register usage over time\n"); +#if RAW_RANGE_STATS + for(i = 0; (i < MAX_RANGE); i++) + PRINTF(" Register set and reused in %d. cycle: %d cases\n", i, raw_stats.range[i]); +#endif + break; + case 6: + if (config.cpu.sbuf_len) { + extern int sbuf_total_cyc, sbuf_wait_cyc; + PRINTF ("stats 6: Store buffer analysis\n"); + PRINTF ("Using store buffer of length %i.\n", config.cpu.sbuf_len); + PRINTF ("Number of total memory store cycles: %i/%lli\n", sbuf_total_cyc, + runtime.sim.cycles + sbuf_total_cyc - sbuf_wait_cyc); + PRINTF ("Number of cycles waiting for memory stores: %i\n", sbuf_wait_cyc); + PRINTF ("Number of memory cycles spared: %i\n", sbuf_total_cyc - sbuf_wait_cyc); + PRINTF ("Store speedup %3.2f%%, total speedup %3.2f%%\n", 100.*(sbuf_total_cyc - sbuf_wait_cyc)/sbuf_total_cyc, + 100.*(sbuf_total_cyc - sbuf_wait_cyc) / (runtime.sim.cycles + sbuf_total_cyc - sbuf_wait_cyc)); + } else + PRINTF ("Store buffer analysis disabled. Enable it to see analysis results.\n"); + break; + default: + PRINTF ("Please specify a stats group (1-6).\n"); + break; + } + #if 0 + PRINTF("Byte ADD: %d instructions\n", or1k_mstats.byteadd); + #endif +} Index: common/abstract.c =================================================================== --- common/abstract.c (nonexistent) +++ common/abstract.c (revision 1765) @@ -0,0 +1,1068 @@ +/* abstract.c -- Abstract entities + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Abstract memory and routines that go with this. I need to +add all sorts of other abstract entities. Currently we have +only memory. */ + +#include +#include +#include +#include + +#include "config.h" + +#ifdef HAVE_INTTYPES_H +#include +#endif + +#include "port.h" + +#include "arch.h" +#include "parse.h" +#include "abstract.h" +#include "sim-config.h" +#include "labels.h" +#include "except.h" +#include "debug_unit.h" +#include "opcode/or32.h" +#include "spr_defs.h" +#include "execute.h" +#include "sprs.h" +#include "support/profile.h" +#include "dmmu.h" +#include "immu.h" +#include "dcache_model.h" +#include "icache_model.h" +#include "debug.h" +#include "stats.h" + +#if DYNAMIC_EXECUTION +#include "dyn_rec.h" +#endif + +extern char *disassembled; + +/* Pointer to memory area descriptions that are assigned to individual + peripheral devices. */ +struct dev_memarea *dev_list; + +/* Temporary variable to increase speed. */ +struct dev_memarea *cur_area; + +/* Pointer to memory controller device descriptor. */ +struct dev_memarea *mc_area = NULL; + +/* These are set by mmu if cache inhibit bit is set for current acces. */ +int data_ci, insn_ci; + +/* Virtual address of current access. */ +static oraddr_t cur_vadd; + +/* Read functions */ +uint32_t eval_mem_32_inv(oraddr_t, void *); +uint16_t eval_mem_16_inv(oraddr_t, void *); +uint8_t eval_mem_8_inv(oraddr_t, void *); +uint32_t eval_mem_32_inv_direct(oraddr_t, void *); +uint16_t eval_mem_16_inv_direct(oraddr_t, void *); +uint8_t eval_mem_8_inv_direct(oraddr_t, void *); + +/* Write functions */ +void set_mem_32_inv(oraddr_t, uint32_t, void *); +void set_mem_16_inv(oraddr_t, uint16_t, void *); +void set_mem_8_inv(oraddr_t, uint8_t, void *); +void set_mem_32_inv_direct(oraddr_t, uint32_t, void *); +void set_mem_16_inv_direct(oraddr_t, uint16_t, void *); +void set_mem_8_inv_direct(oraddr_t, uint8_t, void *); + +/* Calculates bit mask to fit the data */ +static unsigned int bit_mask (uint32_t data) { + int i = 0; + data--; + while (data >> i) + data |= 1 << i++; + return data; +} + +/* Register read and write function for a memory area. + addr is inside the area, if addr & addr_mask == addr_compare + (used also by peripheral devices like 16450 UART etc.) */ +struct dev_memarea *register_memoryarea_mask(oraddr_t addr_mask, + oraddr_t addr_compare, + uint32_t size, unsigned mc_dev) +{ + struct dev_memarea **pptmp; + unsigned int size_mask = bit_mask (size); + int found_error = 0; + addr_compare &= addr_mask; + + debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32"\n", + addr_mask, addr_compare, addr_compare | bit_mask (size), size); + /* Go to the end of the list. */ + for(pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next) + if (((addr_compare >= (*pptmp)->addr_compare) && + (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) || + ((addr_compare + size > (*pptmp)->addr_compare) && + (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size))) { + if (!found_error) { + fprintf (stderr, "ERROR: Overlapping memory area(s):\n"); + fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR + ", size %08"PRIx32"\n", + addr_mask, addr_compare, addr_compare | bit_mask (size), size); + } + found_error = 1; + fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR + ", size %08"PRIx32"\n", + (*pptmp)->addr_mask, (*pptmp)->addr_compare, + (*pptmp)->addr_compare | (*pptmp)->size_mask, (*pptmp)->size); + } + + if (found_error) + exit (-1); + + cur_area = *pptmp = (struct dev_memarea *)malloc(sizeof(struct dev_memarea)); + + if (mc_dev) + mc_area = *pptmp; + + (*pptmp)->addr_mask = addr_mask; + (*pptmp)->addr_compare = addr_compare; + (*pptmp)->size = size; + (*pptmp)->size_mask = size_mask; + (*pptmp)->log = NULL; + (*pptmp)->valid = 1; + (*pptmp)->next = NULL; + + return *pptmp; +} + +/* Register read and write function for a memory area. + Memory areas should be aligned. Memory area is rounded up to + fit the nearest 2^n aligment. + (used also by peripheral devices like 16450 UART etc.) + If mc_dev is 1, this device will be checked first for a match + and will be accessed in case of overlaping memory areas. + Only one device can have this set to 1 (used for memory controller) */ +struct dev_memarea *reg_mem_area(oraddr_t addr, uint32_t size, unsigned mc_dev, + struct mem_ops *ops) +{ + unsigned int size_mask = bit_mask (size); + unsigned int addr_mask = ~size_mask; + struct dev_memarea *mem; + + mem = register_memoryarea_mask(addr_mask, addr & addr_mask, size_mask + 1, + mc_dev); + + memcpy(&mem->ops, ops, sizeof(struct mem_ops)); + memcpy(&mem->direct_ops, ops, sizeof(struct mem_ops)); + + if(!ops->readfunc32) { + mem->ops.readfunc32 = eval_mem_32_inv; + mem->direct_ops.readfunc32 = eval_mem_32_inv_direct; + mem->direct_ops.read_dat32 = mem; + } + if(!ops->readfunc16) { + mem->ops.readfunc16 = eval_mem_16_inv; + mem->direct_ops.readfunc16 = eval_mem_16_inv_direct; + mem->direct_ops.read_dat16 = mem; + } + if(!ops->readfunc8) { + mem->ops.readfunc8 = eval_mem_8_inv; + mem->direct_ops.readfunc8 = eval_mem_8_inv_direct; + mem->direct_ops.read_dat8 = mem; + } + + if(!ops->writefunc32) { + mem->ops.writefunc32 = set_mem_32_inv; + mem->direct_ops.writefunc32 = set_mem_32_inv_direct; + mem->direct_ops.write_dat32 = mem; + } + if(!ops->writefunc16) { + mem->ops.writefunc16 = set_mem_16_inv; + mem->direct_ops.writefunc16 = set_mem_16_inv_direct; + mem->direct_ops.write_dat16 = mem; + } + if(!ops->writefunc8) { + mem->ops.writefunc8 = set_mem_8_inv; + mem->direct_ops.writefunc8 = set_mem_8_inv_direct; + mem->direct_ops.write_dat8 = mem; + } + + if(!ops->writeprog8) { + mem->ops.writeprog8 = mem->ops.writefunc8; + mem->ops.writeprog8_dat = mem->ops.write_dat8; + } + + if(!ops->writeprog32) { + mem->ops.writeprog32 = mem->ops.writefunc32; + mem->ops.writeprog32_dat = mem->ops.write_dat32; + } + + if(ops->log) { + if(!(mem->log = fopen(ops->log, "w"))) + PRINTF("ERR: Unable to open %s to log memory acesses to\n", ops->log); + } + + return mem; +} + +/* Check if access is to registered area of memory. */ +inline struct dev_memarea *verify_memoryarea(oraddr_t addr) +{ + struct dev_memarea *ptmp; + + /* Check memory controller space first */ + if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask)) + return cur_area = mc_area; + + /* Check cached value */ + if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask)) + return cur_area; + + /* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */ + /* Check list of registered devices. */ + for(ptmp = dev_list; ptmp; ptmp = ptmp->next) + if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid) + return cur_area = ptmp; + return cur_area = NULL; +} + +/* Sets the valid bit (Used only by memory controllers) */ +void set_mem_valid(struct dev_memarea *mem, int valid) +{ + mem->valid = valid; +} + +/* Adjusts the read and write delays for the memory area pointed to by mem. */ +void adjust_rw_delay(struct dev_memarea *mem, int delayr, int delayw) +{ + mem->ops.delayr = delayr; + mem->ops.delayw = delayw; +} + +uint8_t eval_mem_8_inv(oraddr_t memaddr, void *dat) +{ + except_handle(EXCEPT_BUSERR, cur_vadd); + return 0; +} + +uint16_t eval_mem_16_inv(oraddr_t memaddr, void *dat) +{ + except_handle(EXCEPT_BUSERR, cur_vadd); + return 0; +} + +uint32_t eval_mem_32_inv(oraddr_t memaddr, void *dat) +{ + except_handle(EXCEPT_BUSERR, cur_vadd); + return 0; +} + +void set_mem_8_inv(oraddr_t memaddr, uint8_t val, void *dat) +{ + except_handle(EXCEPT_BUSERR, cur_vadd); +} + +void set_mem_16_inv(oraddr_t memaddr, uint16_t val, void *dat) +{ + except_handle(EXCEPT_BUSERR, cur_vadd); +} + +void set_mem_32_inv(oraddr_t memaddr, uint32_t val, void *dat) +{ + except_handle(EXCEPT_BUSERR, cur_vadd); +} + +uint8_t eval_mem_8_inv_direct(oraddr_t memaddr, void *dat) +{ + struct dev_memarea *mem = dat; + + PRINTF("ERROR: Invalid 8-bit direct read from memory %"PRIxADDR"\n", + mem->addr_compare | memaddr); + return 0; +} + +uint16_t eval_mem_16_inv_direct(oraddr_t memaddr, void *dat) +{ + struct dev_memarea *mem = dat; + + PRINTF("ERROR: Invalid 16-bit direct read from memory %"PRIxADDR"\n", + mem->addr_compare | memaddr); + return 0; +} + +uint32_t eval_mem_32_inv_direct(oraddr_t memaddr, void *dat) +{ + struct dev_memarea *mem = dat; + + PRINTF("ERROR: Invalid 32-bit direct read from memory %"PRIxADDR"\n", + mem->addr_compare | memaddr); + return 0; +} + +void set_mem_8_inv_direct(oraddr_t memaddr, uint8_t val, void *dat) +{ + struct dev_memarea *mem = dat; + + PRINTF("ERROR: Invalid 32-bit direct write to memory %"PRIxADDR"\n", + mem->addr_compare | memaddr); +} + +void set_mem_16_inv_direct(oraddr_t memaddr, uint16_t val, void *dat) +{ + struct dev_memarea *mem = dat; + + PRINTF("ERROR: Invalid 16-bit direct write to memory %"PRIxADDR"\n", + mem->addr_compare | memaddr); +} + +void set_mem_32_inv_direct(oraddr_t memaddr, uint32_t val, void *dat) +{ + struct dev_memarea *mem = dat; + + PRINTF("ERROR: Invalid 32-bit direct write to memory %"PRIxADDR"\n", + mem->addr_compare | memaddr); +} + +/* For cpu accesses + * + * NOTE: This function _is_ only called from eval_mem32 below and + * {i,d}c_simulate_read. _Don't_ call it from anywere else. + */ +inline uint32_t evalsim_mem32(oraddr_t memaddr, oraddr_t vaddr) +{ + struct dev_memarea *mem; + + if((mem = verify_memoryarea(memaddr))) { + runtime.sim.mem_cycles += mem->ops.delayr; + return mem->ops.readfunc32(memaddr & mem->size_mask, mem->ops.read_dat32); + } else { + PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n", + memaddr); + except_handle(EXCEPT_BUSERR, vaddr); + } + + return 0; +} + +/* For cpu accesses + * + * NOTE: This function _is_ only called from eval_mem16 below and + * {i,d}c_simulate_read. _Don't_ call it from anywere else. + */ +inline uint16_t evalsim_mem16(oraddr_t memaddr, oraddr_t vaddr) +{ + struct dev_memarea *mem; + + if((mem = verify_memoryarea(memaddr))) { + runtime.sim.mem_cycles += mem->ops.delayr; + return mem->ops.readfunc16(memaddr & mem->size_mask, mem->ops.read_dat16); + } else { + PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n", + memaddr); + except_handle(EXCEPT_BUSERR, vaddr); + } + + return 0; +} + +/* For cpu accesses + * + * NOTE: This function _is_ only called from eval_mem8 below and + * {i,d}c_simulate_read. _Don't_ call it from anywere else. + */ +inline uint8_t evalsim_mem8(oraddr_t memaddr, oraddr_t vaddr) +{ + struct dev_memarea *mem; + + if((mem = verify_memoryarea(memaddr))) { + runtime.sim.mem_cycles += mem->ops.delayr; + return mem->ops.readfunc8(memaddr & mem->size_mask, mem->ops.read_dat8); + } else { + PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n", + memaddr); + except_handle(EXCEPT_BUSERR, vaddr); + } + + return 0; +} + +/* Returns 32-bit values from mem array. Big endian version. + * + * STATISTICS OK (only used for cpu_access, that is architectural access) + */ +uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint) +{ + uint32_t temp; + oraddr_t phys_memaddr; + + if (config.sim.mprofile) + mprofile (memaddr, MPROF_32 | MPROF_READ); + + if (memaddr & 3) { + except_handle (EXCEPT_ALIGN, memaddr); + return 0; + } + + if (config.debug.enabled) + *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */ + + phys_memaddr = dmmu_translate(memaddr, 0); + if (except_pending) + return 0; + + if (config.dc.enabled) + temp = dc_simulate_read(phys_memaddr, memaddr, 4); + else + temp = evalsim_mem32(phys_memaddr, memaddr); + + if (config.debug.enabled) + *breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */ + + return temp; +} + +/* for simulator accesses, the ones that cpu wouldn't do + * + * STATISTICS OK + */ +uint32_t eval_direct32(oraddr_t memaddr, int through_mmu, int through_dc) +{ + oraddr_t phys_memaddr; + struct dev_memarea *mem; + + if (memaddr & 3) { + PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__); + return 0; + } + + phys_memaddr = memaddr; + + if (through_mmu) + phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc); + + if (through_dc) + return dc_simulate_read(phys_memaddr, memaddr, 4); + else { + if((mem = verify_memoryarea(phys_memaddr))) + return mem->direct_ops.readfunc32(phys_memaddr & mem->size_mask, + mem->direct_ops.read_dat32); + else + PRINTF("ERR: 32-bit read out of memory area: %"PRIxADDR" (physical: %" + PRIxADDR"\n", memaddr, phys_memaddr); + } + + return 0; +} + + +/* Returns 32-bit values from mem array. Big endian version. + * + * STATISTICS OK (only used for cpu_access, that is architectural access) + */ +uint32_t eval_insn(oraddr_t memaddr, int* breakpoint) +{ + uint32_t temp; + oraddr_t phys_memaddr; + + if (config.sim.mprofile) + mprofile (memaddr, MPROF_32 | MPROF_FETCH); +// memaddr = simulate_ic_mmu_fetch(memaddr); + + phys_memaddr = memaddr; +#if !(DYNAMIC_EXECUTION) + phys_memaddr = immu_translate(memaddr); + + if (except_pending) + return 0; +#endif + + if (config.debug.enabled) + *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); + + if (config.ic.enabled) + temp = ic_simulate_fetch(phys_memaddr, memaddr); + else + temp = evalsim_mem32(phys_memaddr, memaddr); + + if (config.debug.enabled) + *breakpoint += CheckDebugUnit(DebugLoadData,temp); + return temp; +} + +/* Returns 32-bit values from mem array. Big endian version. + * + * STATISTICS OK + */ +uint32_t eval_insn_direct(oraddr_t memaddr, int through_mmu) +{ + if(through_mmu) + memaddr = peek_into_itlb(memaddr); + + return eval_direct32(memaddr, 0, 0); +} + + +/* Returns 16-bit values from mem array. Big endian version. + * + * STATISTICS OK (only used for cpu_access, that is architectural access) + */ +uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint) +{ + uint16_t temp; + oraddr_t phys_memaddr; + + if (config.sim.mprofile) + mprofile (memaddr, MPROF_16 | MPROF_READ); + + if (memaddr & 1) { + except_handle (EXCEPT_ALIGN, memaddr); + return 0; + } + + if (config.debug.enabled) + *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */ + + phys_memaddr = dmmu_translate(memaddr, 0); + if (except_pending) + return 0; + + if (config.dc.enabled) + temp = dc_simulate_read(phys_memaddr, memaddr, 2); + else + temp = evalsim_mem16(phys_memaddr, memaddr); + + if (config.debug.enabled) + *breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */ + + return temp; +} + +/* for simulator accesses, the ones that cpu wouldn't do + * + * STATISTICS OK. + */ +uint16_t eval_direct16(oraddr_t memaddr, int through_mmu, int through_dc) +{ + oraddr_t phys_memaddr; + struct dev_memarea *mem; + + if (memaddr & 1) { + PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__); + return 0; + } + + phys_memaddr = memaddr; + + if (through_mmu) + phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc); + + if (through_dc) + return dc_simulate_read(phys_memaddr, memaddr, 2); + else { + if((mem = verify_memoryarea(phys_memaddr))) + return mem->direct_ops.readfunc16(phys_memaddr & mem->size_mask, + mem->direct_ops.read_dat16); + else + PRINTF("ERR: 16-bit read out of memory area: %"PRIxADDR" (physical: %" + PRIxADDR"\n", memaddr, phys_memaddr); + } + + return 0; +} + +/* Returns 8-bit values from mem array. + * + * STATISTICS OK (only used for cpu_access, that is architectural access) + */ +uint8_t eval_mem8(oraddr_t memaddr,int* breakpoint) +{ + uint8_t temp; + oraddr_t phys_memaddr; + + if (config.sim.mprofile) + mprofile (memaddr, MPROF_8 | MPROF_READ); + + if (config.debug.enabled) + *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */ + + phys_memaddr = dmmu_translate(memaddr, 0); + if (except_pending) + return 0; + + if (config.dc.enabled) + temp = dc_simulate_read(phys_memaddr, memaddr, 1); + else + temp = evalsim_mem8(phys_memaddr, memaddr); + + if (config.debug.enabled) + *breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */ + return temp; +} + +/* for simulator accesses, the ones that cpu wouldn't do + * + * STATISTICS OK. + */ +uint8_t eval_direct8(oraddr_t memaddr, int through_mmu, int through_dc) +{ + oraddr_t phys_memaddr; + struct dev_memarea *mem; + + phys_memaddr = memaddr; + + if (through_mmu) + phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc); + + if (through_dc) + return dc_simulate_read(phys_memaddr, memaddr, 1); + else { + if((mem = verify_memoryarea(phys_memaddr))) + return mem->direct_ops.readfunc8(phys_memaddr & mem->size_mask, + mem->direct_ops.read_dat8); + else + PRINTF("ERR: 8-bit read out of memory area: %"PRIxADDR" (physical: %" + PRIxADDR"\n", memaddr, phys_memaddr); + } + + return 0; +} + +/* For cpu accesses + * + * NOTE: This function _is_ only called from set_mem32 below and + * dc_simulate_write. _Don't_ call it from anywere else. + */ +inline void setsim_mem32(oraddr_t memaddr, oraddr_t vaddr, uint32_t value) +{ + struct dev_memarea *mem; + + if((mem = verify_memoryarea(memaddr))) { + cur_vadd = vaddr; + runtime.sim.mem_cycles += mem->ops.delayw; + mem->ops.writefunc32(memaddr & mem->size_mask, value, mem->ops.write_dat32); +#if DYNAMIC_EXECUTION + dyn_checkwrite(memaddr); +#endif + } else { + PRINTF("EXCEPTION: write out of memory (32-bit access to %"PRIxADDR")\n", + memaddr); + except_handle(EXCEPT_BUSERR, vaddr); + } +} + +/* For cpu accesses + * + * NOTE: This function _is_ only called from set_mem16 below and + * dc_simulate_write. _Don't_ call it from anywere else. + */ +inline void setsim_mem16(oraddr_t memaddr, oraddr_t vaddr, uint16_t value) +{ + struct dev_memarea *mem; + + if((mem = verify_memoryarea(memaddr))) { + cur_vadd = vaddr; + runtime.sim.mem_cycles += mem->ops.delayw; + mem->ops.writefunc16(memaddr & mem->size_mask, value, mem->ops.write_dat16); +#if DYNAMIC_EXECUTION + dyn_checkwrite(memaddr); +#endif + } else { + PRINTF("EXCEPTION: write out of memory (16-bit access to %"PRIxADDR")\n", + memaddr); + except_handle(EXCEPT_BUSERR, vaddr); + } +} + +/* For cpu accesses + * + * NOTE: This function _is_ only called from set_mem8 below and + * dc_simulate_write. _Don't_ call it from anywere else. + */ +inline void setsim_mem8(oraddr_t memaddr, oraddr_t vaddr, uint8_t value) +{ + struct dev_memarea *mem; + + if((mem = verify_memoryarea(memaddr))) { + cur_vadd = vaddr; + runtime.sim.mem_cycles += mem->ops.delayw; + mem->ops.writefunc8(memaddr & mem->size_mask, value, mem->ops.write_dat8); +#if DYNAMIC_EXECUTION + dyn_checkwrite(memaddr); +#endif + } else { + PRINTF("EXCEPTION: write out of memory (8-bit access to %"PRIxADDR")\n", + memaddr); + except_handle(EXCEPT_BUSERR, vaddr); + } +} + +/* Set mem, 32-bit. Big endian version. + * + * STATISTICS OK. (the only suspicious usage is in sim-cmd.c, + * where this instruction is used for patching memory, + * wether this is cpu or architectual access is yet to + * be decided) + */ +void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint) +{ + oraddr_t phys_memaddr; + + if (config.sim.mprofile) + mprofile (memaddr, MPROF_32 | MPROF_WRITE); + + if (memaddr & 3) { + except_handle (EXCEPT_ALIGN, memaddr); + return; + } + + phys_memaddr = dmmu_translate(memaddr, 1);; + /* If we produced exception don't set anything */ + if (except_pending) + return; + + if (config.debug.enabled) { + *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */ + *breakpoint += CheckDebugUnit(DebugStoreData,value); + } + + if(config.dc.enabled) + dc_simulate_write(phys_memaddr, memaddr, value, 4); + else + setsim_mem32(phys_memaddr, memaddr, value); + + if (cur_area && cur_area->log) + fprintf (cur_area->log, "[%"PRIxADDR"] -> write %08"PRIx32"\n", memaddr, + value); +} + +/* + * STATISTICS NOT OK. + */ +void set_direct32(oraddr_t memaddr, uint32_t value, int through_mmu, + int through_dc) +{ + oraddr_t phys_memaddr; + struct dev_memarea *mem; + + if (memaddr & 3) { + PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__); + return; + } + + phys_memaddr = memaddr; + + if (through_mmu) { + /* 0 - no write access, we do not want a DPF exception do we ;) + */ + phys_memaddr = peek_into_dtlb(memaddr, 1, through_dc); + } + + if(through_dc) + dc_simulate_write(memaddr, memaddr, value, 4); + else { + if((mem = verify_memoryarea(phys_memaddr))) + mem->direct_ops.writefunc32(phys_memaddr & mem->size_mask, value, + mem->direct_ops.write_dat32); + else + PRINTF("ERR: 32-bit write out of memory area: %"PRIxADDR" (physical: %" + PRIxADDR")\n", memaddr, phys_memaddr); + } + + if (cur_area && cur_area->log) + fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %08"PRIx32"\n", + memaddr, value); +} + + +/* Set mem, 16-bit. Big endian version. */ + +void set_mem16(oraddr_t memaddr, uint16_t value, int* breakpoint) +{ + oraddr_t phys_memaddr; + + if (config.sim.mprofile) + mprofile (memaddr, MPROF_16 | MPROF_WRITE); + + if (memaddr & 1) { + except_handle (EXCEPT_ALIGN, memaddr); + return; + } + + phys_memaddr = dmmu_translate(memaddr, 1);; + /* If we produced exception don't set anything */ + if (except_pending) + return; + + if (config.debug.enabled) { + *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */ + *breakpoint += CheckDebugUnit(DebugStoreData,value); + } + + if(config.dc.enabled) + dc_simulate_write(phys_memaddr, memaddr, value, 2); + else + setsim_mem16(phys_memaddr, memaddr, value); + + if (cur_area && cur_area->log) + fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr, + value); +} + +/* + * STATISTICS NOT OK. + */ +void set_direct16(oraddr_t memaddr, uint16_t value, int through_mmu, + int through_dc) +{ + oraddr_t phys_memaddr; + struct dev_memarea *mem; + + if (memaddr & 1) { + PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__); + return; + } + + phys_memaddr = memaddr; + + if (through_mmu) { + /* 0 - no write access, we do not want a DPF exception do we ;) + */ + phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc); + } + + if(through_dc) + dc_simulate_write(memaddr, memaddr, value, 2); + else { + if((mem = verify_memoryarea(phys_memaddr))) + mem->direct_ops.writefunc16(phys_memaddr & mem->size_mask, value, + mem->direct_ops.write_dat16); + else + PRINTF("ERR: 16-bit write out of memory area: %"PRIxADDR" (physical: %" + PRIxADDR"\n", memaddr, phys_memaddr); + } + + if (cur_area && cur_area->log) + fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %04"PRIx16"\n", + memaddr, value); +} + +/* Set mem, 8-bit. */ +void set_mem8(oraddr_t memaddr, uint8_t value, int* breakpoint) +{ + oraddr_t phys_memaddr; + + if (config.sim.mprofile) + mprofile (memaddr, MPROF_8 | MPROF_WRITE); + + phys_memaddr = memaddr; + + phys_memaddr = dmmu_translate(memaddr, 1);; + /* If we produced exception don't set anything */ + if (except_pending) return; + + if (config.debug.enabled) { + *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */ + *breakpoint += CheckDebugUnit(DebugStoreData,value); + } + + if(config.dc.enabled) + dc_simulate_write(phys_memaddr, memaddr, value, 1); + else + setsim_mem8(phys_memaddr, memaddr, value); + + if (cur_area && cur_area->log) + fprintf (cur_area->log, "[%"PRIxADDR"] -> write %02"PRIx8"\n", memaddr, + value); +} + +/* + * STATISTICS NOT OK. + */ +void set_direct8(oraddr_t memaddr, uint8_t value, int through_mmu, + int through_dc) +{ + oraddr_t phys_memaddr; + struct dev_memarea *mem; + + phys_memaddr = memaddr; + + if (through_mmu) { + /* 0 - no write access, we do not want a DPF exception do we ;) + */ + phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc); + } + + if(through_dc) + dc_simulate_write(phys_memaddr, memaddr, value, 1); + else { + if((mem = verify_memoryarea(phys_memaddr))) + mem->direct_ops.writefunc8(phys_memaddr & mem->size_mask, value, + mem->direct_ops.write_dat8); + else + PRINTF("ERR: 8-bit write out of memory area: %"PRIxADDR" (physical: %" + PRIxADDR"\n", memaddr, phys_memaddr); + } + + if (cur_area && cur_area->log) + fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %02"PRIx8"\n", + memaddr, value); +} + + +/* set_program32 - same as set_direct32, but it also writes to memory that is + * non-writeable to the rest of the sim. Used to do program + * loading. + */ +void set_program32(oraddr_t memaddr, uint32_t value) +{ + struct dev_memarea *mem; + + if(memaddr & 3) { + PRINTF("%s(): ERR unaligned 32-bit program write\n", __FUNCTION__); + return; + } + + if((mem = verify_memoryarea(memaddr))) { + mem->ops.writeprog32(memaddr & mem->size_mask, value, + mem->ops.writeprog32_dat); + } else + PRINTF("ERR: 32-bit program load out of memory area: %"PRIxADDR"\n", + memaddr); +} + +/* set_program8 - same as set_direct8, but it also writes to memory that is + * non-writeable to the rest of the sim. Used to do program + * loading. + */ +void set_program8(oraddr_t memaddr, uint8_t value) +{ + struct dev_memarea *mem; + + if((mem = verify_memoryarea(memaddr))) { + mem->ops.writeprog8(memaddr & mem->size_mask, value, + mem->ops.writeprog8_dat); + } else + PRINTF("ERR: 8-bit program load out of memory area: %"PRIxADDR"\n", + memaddr); +} + +void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl) +{ + oraddr_t i, j; + struct label_entry *tmp; + int ilen = disasm ? 4 : 16; + + for(i = from; i < to; i += ilen) { + PRINTF("%"PRIxADDR": ", i); + for (j = 0; j < ilen;) { + if (!disasm) { + tmp = NULL; + if (verify_memoryarea(i + j)) { + struct label_entry *entry; + entry = get_label(i + j); + if (entry) + PRINTF("(%s)", entry->name); + PRINTF("%02"PRIx8" ", eval_direct8(i + j, 0, 0)); + } else PRINTF("XX "); + j++; + } else { + uint32_t _insn = eval_direct32(i, 0, 0); + int index = insn_decode (_insn); + int len = insn_len (index); + + tmp = NULL; + if (verify_memoryarea(i + j)) { + struct label_entry *entry; + entry = get_label(i + j); + if (entry) + PRINTF("(%s)", entry->name); + + PRINTF(": %08"PRIx32" ", _insn); + if (index >= 0) { + disassemble_insn (_insn); + PRINTF(" %s", disassembled); + } else + PRINTF(""); + } else PRINTF("XXXXXXXX"); + j += len; + } + } + if (nl) + PRINTF ("\n"); + } +} + +/* Closes files, etc. */ + +void done_memory_table (void) +{ + struct dev_memarea *ptmp; + + /* Check list of registered devices. */ + for(ptmp = dev_list; ptmp; ptmp = ptmp->next) { + if (ptmp->log) + fclose (ptmp->log); + } +} + +/* Displays current memory configuration */ + +void memory_table_status (void) +{ + struct dev_memarea *ptmp; + + /* Check list of registered devices. */ + for(ptmp = dev_list; ptmp; ptmp = ptmp->next) { + PRINTF ("addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %"PRIx32"\n", + ptmp->addr_mask, ptmp->addr_compare, ptmp->addr_compare | bit_mask (ptmp->size), + ptmp->size); + PRINTF ("\t"); + if (ptmp->ops.delayr >= 0) + PRINTF ("read delay = %i cycles, ", ptmp->ops.delayr); + else + PRINTF ("reads not possible, "); + + if (ptmp->ops.delayw >= 0) + PRINTF ("write delay = %i cycles", ptmp->ops.delayw); + else + PRINTF ("writes not possible"); + + if (ptmp->log) + PRINTF (", (logged)\n"); + else + PRINTF ("\n"); + } +} + +/* Outputs time in pretty form to dest string */ + +char *generate_time_pretty (char *dest, long time_ps) +{ + int exp3 = 0; + if (time_ps) { + while ((time_ps % 1000) == 0) { + time_ps /= 1000; + exp3++; + } + } + sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]); + return dest; +} Index: common/parse.c =================================================================== --- common/parse.c (nonexistent) +++ common/parse.c (revision 1765) @@ -0,0 +1,710 @@ +/* parce.c -- Architecture independent load + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include +#include +#include +#include + +#include "config.h" + +#ifdef HAVE_INTTYPES_H +#include +#endif + +#include "port.h" +#include "arch.h" +#include "abstract.h" +#include "dmmu.h" +#include "coff.h" +#include "elf.h" +#include "debug_unit.h" +#include "opcode/or32.h" +#include "parse.h" +#include "sim-config.h" +#include "labels.h" +#include "debug.h" + +#define MEMORY_LEN 0x100000000 +#define MAXLINE_LEN 18000 + +/* Whether to do immediate statistics */ +#define IMM_STATS 0 + +extern char *disassembled; + +/* Unused mem memory marker. It is used when allocating program and data memory + during parsing */ +unsigned int freemem; + +/* Translation table provided by microkernel. Only used if simulating microkernel. */ +static oraddr_t transl_table; + +/* Used to signal whether during loading of programs a translation fault occured. */ +static unsigned long transl_error; + +char * +stripwhite (string) + char *string; +{ + register char *s, *t; + + for (s = string; whitespace (*s); s++) + ; + + if (*s == 0) + return (s); + + t = s + strlen (s) - 1; + while (t > s && whitespace (*t)) + t--; + *++t = '\0'; + + return s; +} + +/* This function is very similar to strncpy, except it null terminates the string */ +char *strstrip (char *dst, const char *src, int n) +{ + strncpy (dst, src, n); + *(dst + n) = '\0'; + return dst; +} + +/* Used only by the simulator loader to translate logical addresses into physical. + If loadcode() is called with valid virtphy_transl pointer to a table of + translations then translate() performs translation otherwise phy address is + equal to logical. */ +static oraddr_t translate(oraddr_t laddr,int* breakpoint) +{ + int i; + + /* No translation (i.e. when loading kernel into simulator) */ +/* PRINTF("transl_table=%x laddr=%x\n", transl_table, laddr); + PRINTF("laddr=%x\n", laddr);*/ + if (transl_table == 0) + return laddr; + + /* Try to find our translation in the table. */ + for(i = 0; i < (MEMORY_LEN / PAGE_SIZE) * 16; i += 16) + if ((laddr & ~(PAGE_SIZE - 1)) == eval_direct32(transl_table + i, 0, 0)) { + /* Page modified */ + set_direct32(transl_table + i + 8, -2, 0, 0); + PRINTF("found paddr=%"PRIx32"\n", + eval_direct32(transl_table + i + 4, 0, 0) | + (laddr & (PAGE_SIZE - 1))); + return (oraddr_t)eval_direct32(transl_table + i + 4, 0, 0) | + (laddr & (oraddr_t)(PAGE_SIZE - 1)); + } + + /* Allocate new phy page for us. */ + for(i = 0; i < (MEMORY_LEN / PAGE_SIZE) * 16; i += 16) + if (eval_direct32(transl_table + i + 8, 0, 0) == 0) { + /* VPN */ + set_direct32(transl_table + i, laddr & ~(PAGE_SIZE - 1), 0, 0); + /* PPN */ + set_direct32(transl_table + i + 4, (i/16) * PAGE_SIZE, 0, 0); + /* Page modified */ + set_direct32(transl_table + i + 8, -2, 0, 0); + PRINTF("newly allocated ppn=%"PRIx32"\n", + eval_direct32(transl_table + i + 4, 0, 0)); + PRINTF("newly allocated .ppn=%"PRIxADDR"\n", transl_table + i + 4); + PRINTF("newly allocated ofs=%"PRIxADDR"\n", (laddr & (PAGE_SIZE - 1))); + PRINTF("newly allocated paddr=%"PRIx32"\n", + eval_direct32(transl_table + i + 4, 0, 0) | + (laddr & (PAGE_SIZE - 1))); + return (oraddr_t)eval_direct32(transl_table + i + 4, 0, 0) | + (laddr & (oraddr_t)(PAGE_SIZE - 1)); + } + /* If we come this far then all phy memory is used and we can't find our page + nor allocate new page. */ + transl_error = 1; + + PRINTF("can't translate %"PRIxADDR"\n", laddr); + exit(1); + return -1; +} + +#if IMM_STATS +int bcnt[33][3] = {0}; +int bsum[3] = {0}; +unsigned long movhi = 0; + +int bits (unsigned long val) { + int i = 1; + if (!val) return 0; + while (val != 0 && (signed long)val != -1) {i++; val = (signed long)val >> 1;} + return i; +} + +void check_insn (uint32_t insn) { + int insn_index = insn_decode (insn); + struct insn_op_struct *opd = op_start[insn_index]; + uint32_t data = 0; + int dis = 0; + const char *name; + if (!insn || insn_index < 0) return; + name = insn_name (insn_index); + if (strcmp (name, "l.nop") == 0 || strcmp (name, "l.sys") == 0) return; + + while (1) + { + uint32_t tmp = 0 + unsigned int nbits = 0; + while (1) + { + tmp |= ((insn >> (opd->type & OPTYPE_SHR)) & ((1 << opd->data) - 1)) << nbits; + nbits += opd->data; + if (opd->type & OPTYPE_OP) + break; + opd++; + } + + /* Do we have to sign extend? */ + if (opd->type & OPTYPE_SIG) + { + int sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR; + if (tmp & (1 << sbit)) + tmp |= 0xFFFFFFFF << sbit; + } + if (opd->type & OPTYPE_DIS) { + /* We have to read register later. */ + data += tmp; + dis = 1; + } else + { + if (!(opd->type & OPTYPE_REG) || dis) { + if (!dis) data = tmp; + if (strcmp (name, "l.movhi") == 0) { + movhi = data << 16; + } else { + data |= movhi; + //PRINTF ("%08x %s\n", data, name); + if (!(or32_opcodes[insn_index].flags & OR32_IF_DELAY)) { + bcnt[bits(data)][0]++; bsum[0]++; + } else { + if (strcmp (name, "l.bf") == 0 || strcmp (name, "l.bnf") == 0) { + bcnt[bits(data)][1]++; bsum[1]++; + } else { + bcnt[bits(data)][2]++; bsum[2]++; + } + } + } + } + data = 0; + dis = 0; + } + if(opd->type & OPTYPE_LAST) { + return; + } + opd++; + } +} +#endif + +/* Replaced several calls to translate(freemem) with vaddr */ +/* Added new mode execution code */ +/* Changed parameters so address can be passed as argument */ +void addprogram(oraddr_t address, uint32_t insn, int* breakpoint) +{ + int vaddr = (!runtime.sim.filename) ? translate(address,breakpoint) : translate(freemem,breakpoint); + + /* We can't have set_program32 functions since it is not gauranteed that the + * section we're loading is aligned on a 4-byte boundry */ + set_program8 (vaddr, (insn >> 24) & 0xff); + set_program8 (vaddr + 1, (insn >> 16) & 0xff); + set_program8 (vaddr + 2, (insn >> 8) & 0xff); + set_program8 (vaddr + 3, insn & 0xff); +#if IMM_STATS + check_insn (insn); +#endif + if(runtime.sim.filename) + freemem += insn_len (insn_decode (insn)); +} + +/* Load big-endian COFF file. */ + +void readfile_coff(char *filename, short sections) +{ + FILE *inputfs; + char inputbuf[4]; + uint32_t insn; + signed long sectsize; + COFF_AOUTHDR coffaouthdr; + struct COFF_scnhdr coffscnhdr; + int len; + int firstthree = 0; + int breakpoint = 0; + + if (!(inputfs = fopen(filename, "r"))) { + perror("readfile_coff"); + exit(1); + } + + if (fseek(inputfs, sizeof(struct COFF_filehdr), SEEK_SET) == -1) { + fclose(inputfs); + perror("readfile_coff"); + exit(1); + } + + if (fread(&coffaouthdr, sizeof(coffaouthdr), 1, inputfs) != 1) { + fclose(inputfs); + perror("readfile_coff"); + exit(1); + } + + while(sections--) { + long scnhdr_pos = sizeof(struct COFF_filehdr) + sizeof(coffaouthdr) + + sizeof(struct COFF_scnhdr) * firstthree; + if (fseek(inputfs, scnhdr_pos, SEEK_SET) == -1) { + fclose(inputfs); + perror("readfile_coff"); + exit(1); + } + if (fread(&coffscnhdr, sizeof(struct COFF_scnhdr), 1, inputfs) != 1) { + fclose(inputfs); + perror("readfile_coff"); + exit(1); + } + PRINTF("Section: %s,", coffscnhdr.s_name); + PRINTF(" paddr: 0x%.8lx,", COFF_LONG_H(coffscnhdr.s_paddr)); + PRINTF(" vaddr: 0x%.8lx,", COFF_LONG_H(coffscnhdr.s_vaddr)); + PRINTF(" size: 0x%.8lx,", COFF_LONG_H(coffscnhdr.s_size)); + PRINTF(" scnptr: 0x%.8lx\n", COFF_LONG_H(coffscnhdr.s_scnptr)); + + sectsize = COFF_LONG_H(coffscnhdr.s_size); +#if 0 + /* A couple of sanity checks. */ + if (translate(COFF_LONG_H(coffscnhdr.s_vaddr),&breakpoint) < MEMORY_START) { + PRINTF("Section %s starts out of ", coffscnhdr.s_name); + PRINTF("memory (at %x)\n", COFF_LONG_H(coffscnhdr.s_vaddr)); + exit(1); + } + if (translate(COFF_LONG_H(coffscnhdr.s_vaddr) + sectsize,&breakpoint) > + MEMORY_START + MEMORY_LEN) { + PRINTF("Section %s ends out of ", coffscnhdr.s_name); + PRINTF("memory.\n"); + exit(1); + } +#endif +#if 0 + if (++firstthree == 1 && strcmp(coffscnhdr.s_name, ".text") != 0) { + PRINTF("First section should be .text (%s instead)\n", coffscnhdr.s_name); + exit(1); + } + if (firstthree == 2 && strcmp(coffscnhdr.s_name, ".data") != 0) { + PRINTF("Second section should be .data (%s instead)\n", coffscnhdr.s_name); + exit(1); + } + if (firstthree == 3 && strcmp(coffscnhdr.s_name, ".bss") != 0) { + PRINTF("Third section should be .bss (%s instead)\n", coffscnhdr.s_name); + exit(1); + } +#else + ++firstthree; +#endif + + /* loading section */ + freemem = COFF_LONG_H(coffscnhdr.s_paddr); + debug(2,"Starting to load at 0x%x\n", freemem); + if (fseek(inputfs, COFF_LONG_H(coffscnhdr.s_scnptr), SEEK_SET) == -1) { + fclose(inputfs); + perror("readfile_coff"); + exit(1); + } + while (sectsize > 0 && (len = fread(&inputbuf, sizeof(inputbuf), 1, inputfs))) { + insn = COFF_LONG_H(inputbuf); + len = insn_len (insn_decode (insn)); + if (len == 2) + { + fseek(inputfs, -2, SEEK_CUR); + debug(8,"readfile_coff: %lx 0x%x \n", sectsize, insn >> 16); + } + else + debug(8,"readfile_coff: %lx 0x%x \n", sectsize, insn); + addprogram (freemem, insn, &breakpoint); + sectsize -= len; + } + } + if (firstthree < 3) { + PRINTF("One or more missing sections. At least"); + PRINTF(" three sections expected (.text, .data, .bss).\n"); + exit(1); + } + if (firstthree > 3) { + PRINTF("Warning: one or more extra sections. These"); + PRINTF(" sections were handled as .data sections.\n"); + } + + fclose(inputfs); + PRINTF("Finished loading COFF.\n"); + return; +} + +/* Load symbols from big-endian COFF file. */ + +void readsyms_coff(char *filename, unsigned long symptr, long syms) +{ + FILE *inputfs; + struct COFF_syment coffsymhdr; + int count = 0; + long nsyms = syms; + if (!(inputfs = fopen(filename, "r"))) { + perror("readsyms_coff"); + exit(1); + } + + if (fseek(inputfs, symptr, SEEK_SET) == -1) { + fclose(inputfs); + perror("readsyms_coff"); + exit(1); + } + + while(syms--) { + int i, n; + if (fread(&coffsymhdr, COFF_SYMESZ, 1, inputfs) != 1) { + fclose(inputfs); + perror("readsyms_coff"); + exit(1); + } + + n = (unsigned char)coffsymhdr.e_numaux[0]; + + /* check whether this symbol belongs to a section and is external symbol; ignore all others */ + if (COFF_SHORT_H(coffsymhdr.e_scnum) >= 0 && coffsymhdr.e_sclass[0] == C_EXT) { +#if 0 + /* If not important or not in text, skip. */ + if(COFF_SHORT_H(coffsymhdr.e_type) & COFF_N_TMASK & COFF_STYP_TEXT) { +#endif + + if (*((unsigned long *)coffsymhdr.e.e.e_zeroes)) { + if (strlen(coffsymhdr.e.e_name) && strlen(coffsymhdr.e.e_name) < 9) + add_label(COFF_LONG_H(coffsymhdr.e_value), coffsymhdr.e.e_name); + debug(8, "[%i] Symbol: %s,", count++, coffsymhdr.e.e_name); + } else { + long fpos = ftell (inputfs); + + if (fseek(inputfs, symptr + nsyms * COFF_SYMESZ + COFF_LONG_H(coffsymhdr.e.e.e_offset), SEEK_SET) == 0) { + char tmp[33], *s = &tmp[0]; + while (s != &tmp[32]) + if ((*(s++) = fgetc(inputfs)) == 0) break; + tmp[32] = 0; + add_label(COFF_LONG_H(coffsymhdr.e_value), &tmp[0]); + debug(8, "[%i] Symbol: %s,", count++, &tmp[0]); + } + fseek(inputfs, fpos, SEEK_SET); + } + + debug(9, " val: 0x%.8lx,", COFF_LONG_H(coffsymhdr.e_value)); + debug(9, " type: %x, %x, auxs: %i\n", COFF_SHORT_H(coffsymhdr.e_type), *((unsigned short *)coffsymhdr.e_type), n); + } + + for (i = 0; i < n; i++) + if (fread(&coffsymhdr, COFF_SYMESZ, 1, inputfs) != 1) { + fclose(inputfs); + perror("readsyms_coff3"); + exit(1); + } + syms -= n; + count += n; + } + + fclose(inputfs); + PRINTF("Finished loading symbols.\n"); + return; +} + +void readfile_elf(char *filename) +{ + + FILE *inputfs; + struct elf32_hdr elfhdr; + struct elf32_phdr *elf_phdata = NULL; + struct elf32_shdr *elf_spnt, *elf_shdata; + struct elf32_sym *sym_tbl = (struct elf32_sym *)0; + unsigned long syms = 0; + char *str_tbl = (char *)0; + char *s_str = (char *)0; + int breakpoint = 0; + unsigned long inputbuf; + unsigned long padd; + uint32_t insn; + int i, j, sectsize, len; + + if (!(inputfs = fopen(filename, "r"))) { + perror("readfile_elf"); + exit(1); + } + + if (fread(&elfhdr, sizeof(elfhdr), 1, inputfs) != 1) { + perror("readfile_elf"); + exit(1); + } + + if ((elf_shdata = (struct elf32_shdr *)malloc(ELF_SHORT_H(elfhdr.e_shentsize) * ELF_SHORT_H(elfhdr.e_shnum))) == NULL) { + perror("readfile_elf"); + exit(1); + } + + if (fseek(inputfs, ELF_LONG_H(elfhdr.e_shoff), SEEK_SET) != 0) { + perror("readfile_elf"); + exit(1); + } + + if (fread(elf_shdata, ELF_SHORT_H(elfhdr.e_shentsize) * ELF_SHORT_H(elfhdr.e_shnum), 1, inputfs) != 1) { + perror("readfile_elf"); + exit(1); + } + + if (ELF_LONG_H(elfhdr.e_phoff)) { + + if((elf_phdata = (struct elf32_phdr *)malloc(ELF_SHORT_H(elfhdr.e_phnum) * ELF_SHORT_H(elfhdr.e_phentsize))) == NULL) { + perror("readfile_elf"); + exit(1); + } + + if (fseek(inputfs, ELF_LONG_H(elfhdr.e_phoff), SEEK_SET) != 0) { + perror("readfile_elf"); + exit(1); + } + + if (fread(elf_phdata, ELF_SHORT_H(elfhdr.e_phnum) * ELF_SHORT_H(elfhdr.e_phentsize), 1, inputfs) != 1) { + perror("readfile_elf"); + exit(1); + } + } + + for(i = 0, elf_spnt = elf_shdata; i < ELF_SHORT_H(elfhdr.e_shnum); i++, elf_spnt++) { + + if(ELF_LONG_H(elf_spnt->sh_type) == SHT_STRTAB) { + + if((str_tbl = (char *)malloc(ELF_LONG_H(elf_spnt->sh_size))) == NULL) { + perror("readfile_elf"); + exit(1); + } + + if (fseek(inputfs, ELF_LONG_H(elf_spnt->sh_offset), SEEK_SET) != 0) { + perror("readfile_elf"); + exit(1); + } + + if (fread(str_tbl, ELF_LONG_H(elf_spnt->sh_size), 1, inputfs) != 1) { + perror("readfile_elf"); + exit(1); + } + } + else if(ELF_LONG_H(elf_spnt->sh_type) == SHT_SYMTAB) { + + if((sym_tbl = (struct elf32_sym *)malloc(ELF_LONG_H(elf_spnt->sh_size))) == NULL) { + perror("readfile_elf"); + exit(1); + } + + if (fseek(inputfs, ELF_LONG_H(elf_spnt->sh_offset), SEEK_SET) != 0) { + perror("readfile_elf"); + exit(1); + } + + if (fread(sym_tbl, ELF_LONG_H(elf_spnt->sh_size), 1, inputfs) != 1) { + perror("readfile_elf"); + exit(1); + } + + syms = ELF_LONG_H(elf_spnt->sh_size) / ELF_LONG_H(elf_spnt->sh_entsize); + } + } + + if (ELF_SHORT_H(elfhdr.e_shstrndx) != SHN_UNDEF) { + elf_spnt = &elf_shdata[ELF_SHORT_H(elfhdr.e_shstrndx)]; + + if((s_str = (char *)malloc(ELF_LONG_H(elf_spnt->sh_size))) == NULL) { + perror("readfile_elf"); + exit(1); + } + + if (fseek(inputfs, ELF_LONG_H(elf_spnt->sh_offset), SEEK_SET) != 0) { + perror("readfile_elf"); + exit(1); + } + + if (fread(s_str, ELF_LONG_H(elf_spnt->sh_size), 1, inputfs) != 1) { + perror("readfile_elf"); + exit(1); + } + } + + + for(i = 0, elf_spnt = elf_shdata; i < ELF_SHORT_H(elfhdr.e_shnum); i++, elf_spnt++) { + + if((ELF_LONG_H(elf_spnt->sh_type) & SHT_PROGBITS) && (ELF_LONG_H(elf_spnt->sh_flags) & SHF_ALLOC)) { + + padd = ELF_LONG_H(elf_spnt->sh_addr); + for(j = 0; j < ELF_SHORT_H(elfhdr.e_phnum); j++) { + if(ELF_LONG_H(elf_phdata[j].p_offset) && + ELF_LONG_H(elf_phdata[j].p_offset) <= ELF_LONG_H(elf_spnt->sh_offset) && + (ELF_LONG_H(elf_phdata[j].p_offset) + ELF_LONG_H(elf_phdata[j].p_memsz)) > ELF_LONG_H(elf_spnt->sh_offset)) + padd = ELF_LONG_H(elf_phdata[j].p_paddr) + ELF_LONG_H(elf_spnt->sh_offset) - ELF_LONG_H(elf_phdata[j].p_offset); + } + + + + if (ELF_LONG_H(elf_spnt->sh_name) && s_str) + PRINTF("Section: %s,", &s_str[ELF_LONG_H(elf_spnt->sh_name)]); + else + PRINTF("Section: noname,"); + PRINTF(" vaddr: 0x%.8lx,", ELF_LONG_H(elf_spnt->sh_addr)); + PRINTF(" paddr: 0x%.8lx,", padd); + PRINTF(" offset: 0x%.8lx,", ELF_LONG_H(elf_spnt->sh_offset)); + PRINTF(" size: 0x%.8lx\n", ELF_LONG_H(elf_spnt->sh_size)); + + freemem = padd; + sectsize = ELF_LONG_H(elf_spnt->sh_size); + + if (fseek(inputfs, ELF_LONG_H(elf_spnt->sh_offset), SEEK_SET) != 0) { + perror("readfile_elf"); + exit(1); + } + + while (sectsize > 0 && (len = fread(&inputbuf, sizeof(inputbuf), 1, inputfs))) { + insn = ELF_LONG_H(inputbuf); + len = insn_len (insn_decode (insn)); + if (len == 2) + { + fseek(inputfs, -2, SEEK_CUR); + debug(8, "readfile_elf: %x 0x%x \n", sectsize, insn >> 16); + } + else + debug(8, "readfile_elf: %x 0x%x \n", sectsize, insn); + addprogram (freemem, insn, &breakpoint); + sectsize -= len; + } + } + } + + if (str_tbl) { + i = 0; + while(syms--) { + if (sym_tbl[i].st_name && sym_tbl[i].st_info && ELF_SHORT_H(sym_tbl[i].st_shndx) < 0x8000) { + add_label(ELF_LONG_H(sym_tbl[i].st_value), &str_tbl[ELF_LONG_H(sym_tbl[i].st_name)]); + debug (8, "%08lx(%s): %x %x %x\n", ELF_LONG_H(sym_tbl[i].st_value), &str_tbl[ELF_LONG_H(sym_tbl[i].st_name)], sym_tbl[i].st_info, sym_tbl[i].st_other, ELF_SHORT_H(sym_tbl[i].st_shndx)); + } + i++; + } + } +} + +/* Identify file type and call appropriate readfile_X routine. It only +handles orX-coff-big executables at the moment. */ + +void identifyfile(char *filename) +{ + FILE *inputfs; + struct COFF_filehdr coffhdr; + struct elf32_hdr elfhdr; + + if (!(inputfs = fopen(filename, "r"))) { + perror(filename); + fflush(stdout); + fflush(stderr); + exit(1); + } + + if (fread(&coffhdr, sizeof(coffhdr), 1, inputfs) == 1) { + if (COFF_SHORT_H(coffhdr.f_magic) == 0x17a) { + unsigned long opthdr_size; + PRINTF("COFF magic: 0x%.4x\n", COFF_SHORT_H(coffhdr.f_magic)); + PRINTF("COFF flags: 0x%.4x\n", COFF_SHORT_H(coffhdr.f_flags)); + PRINTF("COFF symptr: 0x%.8lx\n", COFF_LONG_H(coffhdr.f_symptr)); + if ((COFF_SHORT_H(coffhdr.f_flags) & COFF_F_EXEC) != COFF_F_EXEC) { + PRINTF("This COFF is not an executable.\n"); + exit(1); + } + opthdr_size = COFF_SHORT_H(coffhdr.f_opthdr); + if (opthdr_size != sizeof(COFF_AOUTHDR)) { + PRINTF("COFF optional header is missing or not recognized.\n"); + PRINTF("COFF f_opthdr: 0x%.2lx\n", opthdr_size); + exit(1); + } + fclose(inputfs); + readfile_coff(filename, COFF_SHORT_H(coffhdr.f_nscns)); + readsyms_coff(filename, COFF_LONG_H(coffhdr.f_symptr), COFF_LONG_H(coffhdr.f_nsyms)); + return; + } + else { + PRINTF("Not COFF file format\n"); + fseek(inputfs, 0, SEEK_SET); + } + } + if (fread(&elfhdr, sizeof(elfhdr), 1, inputfs) == 1) { + if (elfhdr.e_ident[0] == 0x7f && elfhdr.e_ident[1] == 0x45 && elfhdr.e_ident[2] == 0x4c && elfhdr.e_ident[3] == 0x46) { + PRINTF("ELF type: 0x%.4x\n", ELF_SHORT_H(elfhdr.e_type)); + PRINTF("ELF machine: 0x%.4x\n", ELF_SHORT_H(elfhdr.e_machine)); + PRINTF("ELF version: 0x%.8lx\n", ELF_LONG_H(elfhdr.e_version)); + PRINTF("ELF sec = %d\n", ELF_SHORT_H(elfhdr.e_shnum)); + if (ELF_SHORT_H(elfhdr.e_type) != ET_EXEC ) { + PRINTF("This ELF is not an executable.\n"); + exit(1); + } + fclose(inputfs); + readfile_elf(filename); + return; + } + else { + PRINTF("Not ELF file format.\n"); + fseek(inputfs, 0, SEEK_SET); + } + } + + perror("identifyfile2"); + fclose(inputfs); + + return; +} + + +/* Loads file to memory starting at address startaddr and returns freemem. */ +unsigned long loadcode(char *filename, oraddr_t startaddr, oraddr_t virtphy_transl) +{ + int breakpoint = 0; + + transl_error = 0; + transl_table = virtphy_transl; + freemem = startaddr; + PRINTF("loadcode: filename %s startaddr=%"PRIxADDR" virtphy_transl=%"PRIxADDR"\n", + filename, startaddr, virtphy_transl); + identifyfile(filename); + +#if IMM_STATS + { + int i = 0, a = 0, b = 0, c = 0; + PRINTF ("index:arith/branch/jump\n"); + for (i = 0; i < 33; i++) + PRINTF ("%2i:\t%3.0f%% / %3.0f%%/ %3.0f%%\t%5i / %5i / %5i\n", i, + 100.* (a += bcnt[i][0])/bsum[0], 100.* (b += bcnt[i][1])/bsum[1], + 100.* (c += bcnt[i][2])/bsum[2], bcnt[i][0], bcnt[i][1], bcnt[i][2]); + PRINTF ("\nsum %i %i %i\n", bsum[0], bsum[1], bsum[2]); + } +#endif + + if (transl_error) + return -1; + else + return translate(freemem,&breakpoint); + +} Index: common/abstract.h =================================================================== --- common/abstract.h (nonexistent) +++ common/abstract.h (revision 1765) @@ -0,0 +1,178 @@ +/* abstract.h -- Abstract entities header file + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include + +#define DEFAULT_MEMORY_START 0 +#define DEFAULT_MEMORY_LEN 0x800000 +#define STACK_SIZE 20 +#define LABELNAME_LEN 50 +#define INSNAME_LEN 15 +#define OPERANDNAME_LEN 50 + +#define MAX_OPERANDS (5) + +#define OP_MEM_ACCESS 0x80000000 + +/* Cache tag types. */ +#define CT_NONE 0 +#define CT_VIRTUAL 1 +#define CT_PHYSICAL 2 + +/* Instruction queue */ +struct iqueue_entry { + int insn_index; + uint32_t insn; + oraddr_t insn_addr; +}; + +struct mem_ops { + /* Read functions */ + uint32_t (*readfunc32)(oraddr_t, void *); + uint16_t (*readfunc16)(oraddr_t, void *); + uint8_t (*readfunc8)(oraddr_t, void *); + + /* Read functions' data */ + void *read_dat8; + void *read_dat16; + void *read_dat32; + + /* Write functions */ + void (*writefunc32)(oraddr_t, uint32_t, void *); + void (*writefunc16)(oraddr_t, uint16_t, void *); + void (*writefunc8)(oraddr_t, uint8_t, void *); + + /* Write functions' data */ + void *write_dat8; + void *write_dat16; + void *write_dat32; + + /* Program load function. If you have unwritteable memory but you would like + * it if a program would be loaded here, make sure to set this. If this is + * not set, then writefunc8 will be called to load the program */ + void (*writeprog32)(oraddr_t, uint32_t, void *); + void (*writeprog8)(oraddr_t, uint8_t, void *); + + void *writeprog32_dat; + void *writeprog8_dat; + + /* Read/Write delays */ + int delayr; + int delayw; + + /* Name of log file */ + const char *log; +}; + +/* Memory regions assigned to devices */ +struct dev_memarea { + struct dev_memarea *next; + oraddr_t addr_mask; + oraddr_t addr_compare; + uint32_t size; + oraddr_t size_mask; /* Address mask, calculated out of size */ + + int valid; /* This bit reflects the memory controler valid bit */ + FILE *log; /* log file if this device is to be logged, NULL otherwise */ + + struct mem_ops ops; + struct mem_ops direct_ops; +}; + +extern void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl); +extern uint32_t eval_mem32(oraddr_t memaddr,int*); +extern uint16_t eval_mem16(oraddr_t memaddr,int*); +extern uint8_t eval_mem8(oraddr_t memaddr,int*); +void set_mem32(oraddr_t memaddr, uint32_t value,int*); +extern void set_mem16(oraddr_t memaddr, uint16_t value,int*); +extern void set_mem8(oraddr_t memaddr, uint8_t value,int*); + +uint32_t evalsim_mem32(oraddr_t, oraddr_t); +uint16_t evalsim_mem16(oraddr_t, oraddr_t); +uint8_t evalsim_mem8(oraddr_t, oraddr_t); + +void setsim_mem32(oraddr_t, oraddr_t, uint32_t); +void setsim_mem16(oraddr_t, oraddr_t, uint16_t); +void setsim_mem8(oraddr_t, oraddr_t, uint8_t); + +/* Closes files, etc. */ +void done_memory_table (void); + +/* Displays current memory configuration */ +void memory_table_status (void); + +/* Register memory area */ +struct dev_memarea *reg_mem_area(oraddr_t addr, uint32_t size, unsigned mc_dev, + struct mem_ops *ops); + +/* Adjusts the read and write delays for the memory area pointed to by mem. */ +void adjust_rw_delay(struct dev_memarea *mem, int delayr, int delayw); + +/* Sets the valid bit (Used only by memory controllers) */ +void set_mem_valid(struct dev_memarea *mem, int valid); + +/* Check if access is to registered area of memory. */ +struct dev_memarea *verify_memoryarea(oraddr_t addr); + +/* Outputs time in pretty form to dest string. */ +char *generate_time_pretty (char *dest, long time_ps); + +/* Returns 32-bit values from mem array. */ +uint32_t eval_insn(oraddr_t, int *); + +uint32_t eval_insn_direct(oraddr_t memaddr, int through_mmu); + +uint8_t eval_direct8(oraddr_t memaddr, int through_mmu, int through_dc); +uint16_t eval_direct16(oraddr_t memaddr, int through_mmu, int through_dc); +uint32_t eval_direct32(oraddr_t addr, int through_mmu, int through_dc); + +void set_direct8(oraddr_t, uint8_t, int, int); +void set_direct16(oraddr_t, uint16_t, int, int); +void set_direct32(oraddr_t, uint32_t, int, int); + +/* Same as set_direct32, but it also writes to memory that is non-writeable to + * the rest of the sim. Used to do program loading. */ +void set_program32(oraddr_t memaddr, uint32_t value); +void set_program8(oraddr_t memaddr, uint8_t value); + +/* Temporary variable to increase speed. */ +extern struct dev_memarea *cur_area; + +/* These are set by mmu if cache inhibit bit is set for current acces. */ +extern int data_ci, insn_ci; + +/* Added by MM */ +#ifndef LONGEST +#define LONGEST long long +#define ULONGEST unsigned long long +#endif /* ! LONGEST */ + +/* Returns the page that addr belongs to */ +#define IADDR_PAGE(addr) ((addr) & config.immu.page_mask) +#define DADDR_PAGE(addr) ((addr) & config.dmmu.page_mask) + +/* History of execution */ +#define HISTEXEC_LEN 200 +struct hist_exec { + oraddr_t addr; + struct hist_exec *prev; + struct hist_exec *next; +}; + +extern struct hist_exec *hist_exec_tail; Index: common/execute.h =================================================================== --- common/execute.h (nonexistent) +++ common/execute.h (revision 1765) @@ -0,0 +1,85 @@ +/* execute.h -- Header file for architecture dependent execute.c + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#if DYNAMIC_EXECUTION +#include "dyn_rec.h" +#endif + +struct cpu_state { + /* General purpose registers. */ + uorreg_t reg[MAX_GPRS]; + + /* Sprs */ + uorreg_t sprs[MAX_SPRS]; + + /* Effective address of instructions that have an effective address. This is + * only used to get dump_exe_log correct */ + oraddr_t insn_ea; + + /* Is current instruction in execution in a delay slot? */ + int delay_insn; + + /* Program counter (and translated PC) */ + oraddr_t pc; + + /* Delay instruction effective address register */ + oraddr_t pc_delay; + + /* Decoding of the just executed instruction. Only used in analysis(). */ + struct iqueue_entry iqueue; + + /* decoding of the instruction that was executed before this one. Only used + * in analysis(). */ + struct iqueue_entry icomplet; + +#if DYNAMIC_EXECUTION + /* Current page in execution */ + struct dyn_page *curr_page; + + /* Pointers to recompiled pages */ + struct dyn_page **dyn_pages; + + /* Micro operation queue. Only used to speed up recompile_page */ + struct op_queue *opqs; + + /* Set if all temporaries are stored */ + int ts_current; + + /* The contents of the temporaries. Only used in except_handle */ + uorreg_t t0; + uorreg_t t1; + uorreg_t t2; +#endif +}; + +extern struct cpu_state cpu_state; + +#define CURINSN(INSN) (strcmp(cur->insn, (INSN)) == 0) + +/*extern machword eval_operand(char *srcoperand,int* breakpoint); +extern void set_operand(char *dstoperand, unsigned long value,int* breakpoint);*/ +void dumpreg(); +inline void dump_exe_log(); +inline int cpu_clock (); +void cpu_reset (); +uorreg_t evalsim_reg(unsigned int regno); +void setsim_reg(unsigned int regno, uorreg_t value); + +extern oraddr_t pcnext; +int depend_operands(struct iqueue_entry *prev, struct iqueue_entry *next); Index: common/trace.c =================================================================== --- common/trace.c (nonexistent) +++ common/trace.c (revision 1765) @@ -0,0 +1,54 @@ +/* trace.c -- Simulator breakpoints + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include + +#include "config.h" + +#ifdef HAVE_INTTYPES_H +#include +#endif + +#include "port.h" +#include "arch.h" +#include "abstract.h" +#include "labels.h" +#include "sim-config.h" +#include "trace.h" + +/* Set instruction execution breakpoint. */ + +void set_insnbrkpoint(oraddr_t addr) +{ + addr &= ~ADDR_C(3); /* 32-bit aligned */ + + if (!verify_memoryarea(addr)) + PRINTF("WARNING: This breakpoint is out of the simulated memory range.\n"); + + if (has_breakpoint (addr)) { + remove_breakpoint (addr); + PRINTF("\nBreakpoint at 0x%"PRIxADDR" cleared.\n", addr); + } else { + add_breakpoint (addr); + PRINTF("\nBreakpoint at 0x%"PRIxADDR" set.\n", addr); + } + + return; +} + Index: common/stats.h =================================================================== --- common/stats.h (nonexistent) +++ common/stats.h (revision 1765) @@ -0,0 +1,109 @@ +/* stats.h -- Header file for stats.c + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#define DSTATS_LEN 3000 +#define SSTATS_LEN 300 +#define FSTATS_LEN 200 +#define RAW_RANGE 1000 + +/* Used by safe division - increment divisor by one if it is zero */ +#define SD(X) (X != 0 ? X : 1) + +struct dstats_entry { + int insn1; + int insn2; + int cnt_dynamic; + int depend; +}; + +struct sstats_entry { + int insn; + int cnt_dynamic; +}; /* single stats */ + +struct fstats_entry { + enum insn_type insn1; + enum insn_type insn2; + int cnt_dynamic; + int depend; +}; /* functional units stats */ + +struct bpbstat { + int hit; + int miss; + int correct; + int incorrect; +}; + +struct bticstat { + int hit; + int miss; +}; + +struct mstats_entry { + int byteadd; + int bf[2][2]; /* [taken][fwd/bwd] */ + int bnf[2][2]; /* [taken][fwd/bwd] */ + struct bpbstat bpb; + struct bticstat btic; +}; /* misc units stats */ + +struct cachestats_entry { + int readhit; + int readmiss; + int writehit; + int writemiss; +}; /* cache stats */ + +struct immustats_entry { + int fetch_tlbhit; + int fetch_tlbmiss; + int fetch_pagefaults; +}; /* IMMU stats */ + +struct dmmustats_entry { + int loads_tlbhit; + int loads_tlbmiss; + int loads_pagefaults; + int stores_tlbhit; + int stores_tlbmiss; + int stores_pagefaults; +}; /* DMMU stats */ + +struct raw_stats { + int reg[64]; + int range[RAW_RANGE]; +}; /* RAW hazard stats */ + +/* Renamed mstats to or1k_mstats because Mac OS X has a lib function called mstats */ +extern struct mstats_entry or1k_mstats; +extern struct sstats_entry sstats[SSTATS_LEN]; +extern struct dstats_entry dstats[DSTATS_LEN]; +extern struct fstats_entry fstats[FSTATS_LEN]; +extern struct cachestats_entry ic_stats; +extern struct cachestats_entry dc_stats; +extern struct immustats_entry immu_stats; +extern struct dmmustats_entry dmmu_stats; +extern struct raw_stats raw_stats; + +extern void addsstats(int item, int cnt_dynamic); +extern void adddstats(int item1, int item2, int cnt_dynamic, int depend); +extern void addfstats(enum insn_type item1, enum insn_type item2, int cnt_dynamic, int depend); +extern void initstats(); +extern void printstats(); Index: common/Makefile.in =================================================================== --- common/Makefile.in (nonexistent) +++ common/Makefile.in (revision 1765) @@ -0,0 +1,338 @@ +# Makefile.in generated by automake 1.6.3 from Makefile.am. +# @configure_input@ + +# Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 +# Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + +# Makefile -- Makefile for cpu architecture independent simulation +# Copyright (C) 1999 Damjan Lampret, lampret@opencores.org +# +# This file is part of OpenRISC 1000 Architectural Simulator. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +SHELL = @SHELL@ + +srcdir = @srcdir@ +top_srcdir = @top_srcdir@ +VPATH = @srcdir@ +prefix = @prefix@ +exec_prefix = @exec_prefix@ + +bindir = @bindir@ +sbindir = @sbindir@ +libexecdir = @libexecdir@ +datadir = @datadir@ +sysconfdir = @sysconfdir@ +sharedstatedir = @sharedstatedir@ +localstatedir = @localstatedir@ +libdir = @libdir@ +infodir = @infodir@ +mandir = @mandir@ +includedir = @includedir@ +oldincludedir = /usr/include +pkgdatadir = $(datadir)/@PACKAGE@ +pkglibdir = $(libdir)/@PACKAGE@ +pkgincludedir = $(includedir)/@PACKAGE@ +top_builddir = ../.. + +ACLOCAL = @ACLOCAL@ +AUTOCONF = @AUTOCONF@ +AUTOMAKE = @AUTOMAKE@ +AUTOHEADER = @AUTOHEADER@ + +am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +INSTALL = @INSTALL@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_DATA = @INSTALL_DATA@ +install_sh_DATA = $(install_sh) -c -m 644 +install_sh_PROGRAM = $(install_sh) -c +install_sh_SCRIPT = $(install_sh) -c +INSTALL_SCRIPT = @INSTALL_SCRIPT@ +INSTALL_HEADER = $(INSTALL_DATA) +transform = @program_transform_name@ +NORMAL_INSTALL = : +PRE_INSTALL = : +POST_INSTALL = : +NORMAL_UNINSTALL = : +PRE_UNINSTALL = : +POST_UNINSTALL = : +build_alias = @build_alias@ +build_triplet = @build@ +host_alias = @host_alias@ +host_triplet = @host@ +target_alias = @target_alias@ +target_triplet = @target@ + +EXEEXT = @EXEEXT@ +OBJEXT = @OBJEXT@ +PATH_SEPARATOR = @PATH_SEPARATOR@ +AMTAR = @AMTAR@ +AR = @AR@ +ARFLAGS = @ARFLAGS@ +AWK = @AWK@ +BUILD_DIR = @BUILD_DIR@ +CC = @CC@ +CFLAGS = @CFLAGS@ +CPU_ARCH = @CPU_ARCH@ +DEPDIR = @DEPDIR@ +INCLUDES = @INCLUDES@ +INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ +LOCAL_CFLAGS = @LOCAL_CFLAGS@ +LOCAL_DEFS = @LOCAL_DEFS@ +MAKE_SHELL = @MAKE_SHELL@ +PACKAGE = @PACKAGE@ +RANLIB = @RANLIB@ +STRIP = @STRIP@ +SUMVERSION = @SUMVERSION@ +TERMCAP_LIB = @TERMCAP_LIB@ +VERSION = @VERSION@ +am__include = @am__include@ +am__quote = @am__quote@ +host = @host@ +host_cpu = @host_cpu@ +host_os = @host_os@ +install_sh = @install_sh@ + +noinst_LIBRARIES = libcommon.a +libcommon_a_SOURCES = abstract.c parse.c stats.c trace.c labels.c +subdir = cpu/common +mkinstalldirs = $(SHELL) $(top_srcdir)/mkinstalldirs +CONFIG_HEADER = $(top_builddir)/config.h +CONFIG_CLEAN_FILES = +LIBRARIES = $(noinst_LIBRARIES) + +libcommon_a_AR = $(AR) cru +libcommon_a_LIBADD = +am_libcommon_a_OBJECTS = abstract.$(OBJEXT) parse.$(OBJEXT) \ + stats.$(OBJEXT) trace.$(OBJEXT) labels.$(OBJEXT) +libcommon_a_OBJECTS = $(am_libcommon_a_OBJECTS) + +DEFS = @DEFS@ +DEFAULT_INCLUDES = -I. -I$(srcdir) -I$(top_builddir) +CPPFLAGS = @CPPFLAGS@ +LDFLAGS = @LDFLAGS@ +LIBS = @LIBS@ +depcomp = $(SHELL) $(top_srcdir)/depcomp +am__depfiles_maybe = depfiles +@AMDEP_TRUE@DEP_FILES = ./$(DEPDIR)/abstract.Po ./$(DEPDIR)/labels.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/parse.Po ./$(DEPDIR)/stats.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/trace.Po +COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +CCLD = $(CC) +LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@ +DIST_SOURCES = $(libcommon_a_SOURCES) +DIST_COMMON = Makefile.am Makefile.in +SOURCES = $(libcommon_a_SOURCES) + +all: all-am + +.SUFFIXES: +.SUFFIXES: .c .o .obj +$(srcdir)/Makefile.in: Makefile.am $(top_srcdir)/configure.in $(ACLOCAL_M4) + cd $(top_srcdir) && \ + $(AUTOMAKE) --gnu cpu/common/Makefile +Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status + cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe) + +clean-noinstLIBRARIES: + -test -z "$(noinst_LIBRARIES)" || rm -f $(noinst_LIBRARIES) +libcommon.a: $(libcommon_a_OBJECTS) $(libcommon_a_DEPENDENCIES) + -rm -f libcommon.a + $(libcommon_a_AR) libcommon.a $(libcommon_a_OBJECTS) $(libcommon_a_LIBADD) + $(RANLIB) libcommon.a + +mostlyclean-compile: + -rm -f *.$(OBJEXT) core *.core + +distclean-compile: + -rm -f *.tab.c + +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/abstract.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/labels.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/parse.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/stats.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/trace.Po@am__quote@ + +distclean-depend: + -rm -rf ./$(DEPDIR) + +.c.o: +@AMDEP_TRUE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@ depfile='$(DEPDIR)/$*.Po' tmpdepfile='$(DEPDIR)/$*.TPo' @AMDEPBACKSLASH@ +@AMDEP_TRUE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ + $(COMPILE) -c `test -f '$<' || echo '$(srcdir)/'`$< + +.c.obj: +@AMDEP_TRUE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@ depfile='$(DEPDIR)/$*.Po' tmpdepfile='$(DEPDIR)/$*.TPo' @AMDEPBACKSLASH@ +@AMDEP_TRUE@ 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install-info-am + +install-man: + +installcheck-am: + +maintainer-clean: maintainer-clean-am + +maintainer-clean-am: distclean-am maintainer-clean-generic + +mostlyclean: mostlyclean-am + +mostlyclean-am: mostlyclean-compile mostlyclean-generic + +uninstall-am: uninstall-info-am + +.PHONY: GTAGS all all-am check check-am clean clean-generic \ + clean-noinstLIBRARIES distclean distclean-compile \ + distclean-depend distclean-generic distclean-tags distdir dvi \ + dvi-am info info-am install install-am install-data \ + install-data-am install-exec install-exec-am install-info \ + install-info-am install-man install-strip installcheck \ + installcheck-am installdirs maintainer-clean \ + maintainer-clean-generic mostlyclean mostlyclean-compile \ + mostlyclean-generic tags uninstall uninstall-am \ + uninstall-info-am + +# Tell versions [3.59,3.63) of GNU make to not export all variables. +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: Index: common/labels.c =================================================================== --- common/labels.c (nonexistent) +++ common/labels.c (revision 1765) @@ -0,0 +1,153 @@ +/* abstract.c -- Abstract entities, handling labels + Copyright (C) 2001 Marko Mlinar, markom@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Abstract memory and routines that go with this. I need to +add all sorts of other abstract entities. Currently we have +only memory. */ + +#include +#include +#include +#include + +#include "config.h" + +#ifdef HAVE_INTTYPES_H +#include +#endif + +#include "port.h" +#include "config.h" + +#include "arch.h" +#include "sim-config.h" +#include "labels.h" + +static struct label_entry *label_hash[LABELS_HASH_SIZE]; +struct breakpoint_entry *breakpoints; + +void init_labels () { + int i; + for (i = 0; i < LABELS_HASH_SIZE; i++) + label_hash[i] = NULL; +} + +void add_label (oraddr_t addr, char *name) { + struct label_entry **tmp; + tmp = &(label_hash[addr % LABELS_HASH_SIZE]); + for (; *tmp; tmp = &((*tmp)->next)); + *tmp = malloc(sizeof(**tmp)); + (*tmp)->name = malloc(strlen(name) + 1); + (*tmp)->addr = addr; + strcpy((*tmp)->name, name); + (*tmp)->next = NULL; +} + +struct label_entry *get_label (oraddr_t addr) { + struct label_entry *tmp = label_hash[addr % LABELS_HASH_SIZE]; + while (tmp) { + if (tmp->addr == addr) + return tmp; + tmp = tmp->next; + } + return NULL; +} + +struct label_entry *find_label (char *name) { + int i; + for (i = 0; i < LABELS_HASH_SIZE; i++) { + struct label_entry *tmp = label_hash[i % LABELS_HASH_SIZE]; + while (tmp) { + if (strcmp (tmp->name, name) == 0) + return tmp; + tmp = tmp->next; + } + } + return NULL; +} + +/* Searches mem array for a particular label and returns label's address. + If label does not exist, returns 0. */ +oraddr_t eval_label (char *name) { + struct label_entry *le; + char *plus; + char *minus; + int positive_offset = 0; + int negative_offset = 0; + + if ((plus = strchr(name, '+'))) { + *plus = '\0'; + positive_offset = atoi(++plus); + } + + if ((minus = strchr(name, '-'))) { + *minus = '\0'; + negative_offset = atoi(++minus); + } + le = find_label (name); + if (!le) + return 0; + + return le->addr + positive_offset - negative_offset; +} + +void init_breakpoints () { + breakpoints = 0; +} + +void add_breakpoint (oraddr_t addr) { + struct breakpoint_entry *tmp; + tmp = (struct breakpoint_entry *) malloc (sizeof (struct breakpoint_entry)); + tmp->next = breakpoints; + tmp->addr = addr; + breakpoints = tmp; +} + +void remove_breakpoint (oraddr_t addr) { + struct breakpoint_entry **tmp = &breakpoints; + while (*tmp) { + if ((*tmp)->addr == addr) { + struct breakpoint_entry *t = *tmp; + (*tmp) = t->next; + free (t); + } else + tmp = &((*tmp)->next); + } +} + +void print_breakpoints () { + struct breakpoint_entry **tmp = &breakpoints; + int i = 1; + printf ("---[breakpoints]------------------\n"); + while (*tmp) { + printf ("Breakpoint %i at 0x%"PRIxADDR"\n", i, (*tmp)->addr); + tmp = &((*tmp)->next); + } + printf ("---[breakpoints end]--------------\n"); +} + +inline int has_breakpoint (oraddr_t addr) { + struct breakpoint_entry *tmp = breakpoints; + while (tmp) { + if (tmp->addr == addr) + return 1; + tmp = tmp->next; + } + return 0; +}

common/labels.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: common/parse.h =================================================================== --- common/parse.h (nonexistent) +++ common/parse.h (revision 1765) @@ -0,0 +1,41 @@ +/* parse.h -- Header file for parse.c + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Here we define some often used caharcters in assembly files. +This wil probably go into architecture dependent directory. */ + +#define COMMENT_CHAR '#' +#define DIRECTIVE_CHAR '.' +#define LABELEND_CHAR ":" +/*#define OPERAND_DELIM ","*/ + +/* Strip whitespace from the start and end of STRING. Return a pointer + into STRING. */ +#ifndef whitespace +#define whitespace(a) ((a) == '\t' ? 1 : ((a) == ' '? 1 : 0)) +#endif + +/* Strips white spaces at beginning and at the end of the string */ +char *stripwhite (char *string); + +/* This function is very similar to strncpy, except it null terminates the string */ +char *strstrip (char *dst, const char *src, int n); + +/* Loads file to memory starting at address startaddr and returns freemem. */ +unsigned long loadcode(char *filename, oraddr_t startaddr, oraddr_t virtphy_transl); Index: common/trace.h =================================================================== --- common/trace.h (nonexistent) +++ common/trace.h (revision 1765) @@ -0,0 +1,2 @@ + +void set_insnbrkpoint(oraddr_t addr); Index: common/labels.h =================================================================== --- common/labels.h (nonexistent) +++ common/labels.h (revision 1765) @@ -0,0 +1,58 @@ +/* labels.h -- Abstract entities header file handling labels + Copyright (C) 2001 Marko Mlinar, markom@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifndef _LABELS_H_ +#define _LABELS_H_ + +#define LABELS_HASH_SIZE 119 + +/* Structure for holding one label per particular memory location */ +struct label_entry { + char *name; + oraddr_t addr; + struct label_entry *next; +}; + +struct breakpoint_entry { + oraddr_t addr; + struct breakpoint_entry *next; +}; + +/* Label handling */ +void init_labels(); +void add_label (oraddr_t addr, char *name); +struct label_entry *get_label (oraddr_t addr); +struct label_entry *find_label (char *name); + +/* Searches mem array for a particular label and returns label's address. + If label does not exist, returns 0. */ +oraddr_t eval_label (char *name); + +/* Breakpoint handling */ +void breakpoints_init (); +void add_breakpoint (oraddr_t addr); +void remove_breakpoint (oraddr_t addr); +void print_breakpoints (); +int has_breakpoint (oraddr_t addr); +void init_breakpoints (); + +extern struct breakpoint_entry *breakpoints; +#define CHECK_BREAKPOINTS (breakpoints) + +#endif /* _LABELS_H_ */

common/labels.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: common/coff.h =================================================================== --- common/coff.h (nonexistent) +++ common/coff.h (revision 1765) @@ -0,0 +1,457 @@ +#if HAVE_CONFIG_H +#include +#endif + +/* This file is derived from the GAS 2.1.4 assembler control file. + The GAS product is under the GNU Public License, version 2 or later. + As such, this file is also under that license. + + If the file format changes in the COFF object, this file should be + subsequently updated to reflect the changes. + + The actual loader module only uses a few of these structures. The full + set is documented here because I received the full set. If you wish + more information about COFF, then O'Reilly has a very excellent book. +*/ + +#define E_SYMNMLEN 8 /* Number of characters in a symbol name */ +#define E_FILNMLEN 14 /* Number of characters in a file name */ +#define E_DIMNUM 4 /* Number of array dimensions in auxiliary entry */ + +/* + * These defines are byte order independent. There is no alignment of fields + * permitted in the structures. Therefore they are declared as characters + * and the values loaded from the character positions. It also makes it + * nice to have it "endian" independent. + */ +#if !defined(WORDS_BIGENDIAN) +/* Load a short int from the following tables with little-endian formats */ +#define COFF_SHORT_L SWAP_ENDIAN_SHORT +/* Load a long int from the following tables with little-endian formats */ +#define COFF_LONG_L SWAP_ENDIAN_LONG +/* Load a short int from the following tables with big-endian formats */ +#define COFF_SHORT_H KEEP_ENDIAN_SHORT +/* Load a long int from the following tables with big-endian formats */ +#define COFF_LONG_H KEEP_ENDIAN_LONG +#else +#define COFF_SHORT_L KEEP_ENDIAN_SHORT +#define COFF_LONG_L KEEP_ENDIAN_LONG +#define COFF_SHORT_H SWAP_ENDIAN_SHORT +#define COFF_LONG_H SWAP_ENDIAN_LONG +#endif + +#define SWAP_ENDIAN_SHORT(ps) ((short)(((unsigned short)((unsigned char)ps[1])<<8)|\ + ((unsigned short)((unsigned char)ps[0])))) + +#define SWAP_ENDIAN_LONG(ps) (((long)(((unsigned long)((unsigned char)ps[3])<<24) |\ + ((unsigned long)((unsigned char)ps[2])<<16) |\ + ((unsigned long)((unsigned char)ps[1])<<8) |\ + ((unsigned long)((unsigned char)ps[0]))))) + +#define KEEP_ENDIAN_SHORT(ps) ((short)(((unsigned short)((unsigned char)ps[0])<<8)|\ + ((unsigned short)((unsigned char)ps[1])))) + +#define KEEP_ENDIAN_LONG(ps) (((long)(((unsigned long)((unsigned char)ps[0])<<24) |\ + ((unsigned long)((unsigned char)ps[1])<<16) |\ + ((unsigned long)((unsigned char)ps[2])<<8) |\ + ((unsigned long)((unsigned char)ps[3]))))) + +/* These may be overridden later by brain dead implementations which generate + a big-endian header with little-endian data. In that case, generate a + replacement macro which tests a flag and uses either of the two above + as appropriate. */ + +#define COFF_LONG(v) COFF_LONG_L(v) +#define COFF_SHORT(v) COFF_SHORT_L(v) + +/*** coff information for Intel 386/486. */ + +/********************** FILE HEADER **********************/ + +struct COFF_filehdr { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + +/* + * Bits for f_flags: + * + * F_RELFLG relocation info stripped from file + * F_EXEC file is executable (i.e. no unresolved external + * references) + * F_LNNO line numbers stripped from file + * F_LSYMS local symbols stripped from file + * F_MINMAL this is a minimal object file (".m") output of fextract + * F_UPDATE this is a fully bound update file, output of ogen + * F_SWABD this file has had its bytes swabbed (in names) + * F_AR16WR this file has the byte ordering of an AR16WR + * (e.g. 11/70) machine + * F_AR32WR this file has the byte ordering of an AR32WR machine + * (e.g. vax and iNTEL 386) + * F_AR32W this file has the byte ordering of an AR32W machine + * (e.g. 3b,maxi) + * F_PATCH file contains "patch" list in optional header + * F_NODF (minimal file only) no decision functions for + * replaced functions + */ + +#define COFF_F_RELFLG 0000001 +#define COFF_F_EXEC 0000002 +#define COFF_F_LNNO 0000004 +#define COFF_F_LSYMS 0000010 +#define COFF_F_MINMAL 0000020 +#define COFF_F_UPDATE 0000040 +#define COFF_F_SWABD 0000100 +#define COFF_F_AR16WR 0000200 +#define COFF_F_AR32WR 0000400 +#define COFF_F_AR32W 0001000 +#define COFF_F_PATCH 0002000 +#define COFF_F_NODF 0002000 + +#define COFF_I386MAGIC 0x14c /* Linux's system */ + +#if 0 /* Perhaps, someday, these formats may be used. */ +#define COFF_I386PTXMAGIC 0x154 +#define COFF_I386AIXMAGIC 0x175 /* IBM's AIX system */ +#define COFF_I386BADMAG(x) ((COFF_SHORT((x).f_magic) != COFF_I386MAGIC) \ + && COFF_SHORT((x).f_magic) != COFF_I386PTXMAGIC \ + && COFF_SHORT((x).f_magic) != COFF_I386AIXMAGIC) +#else +#define COFF_I386BADMAG(x) (COFF_SHORT((x).f_magic) != COFF_I386MAGIC) +#endif + +#define COFF_FILHDR struct COFF_filehdr +#define COFF_FILHSZ sizeof(COFF_FILHDR) + +/********************** AOUT "OPTIONAL HEADER" **********************/ + +/* Linux COFF must have this "optional" header. Standard COFF has no entry + location for the "entry" point. They normally would start with the first + location of the .text section. This is not a good idea for linux. So, + the use of this "optional" header is not optional. It is required. + + Do not be tempted to assume that the size of the optional header is + a constant and simply index the next byte by the size of this structure. + Use the 'f_opthdr' field in the main coff header for the size of the + structure actually written to the file!! +*/ + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry */ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} +COFF_AOUTHDR; + +#define COFF_AOUTSZ (sizeof(COFF_AOUTHDR)) + +#define COFF_STMAGIC 0401 +#define COFF_OMAGIC 0404 +#define COFF_JMAGIC 0407 /* dirty text and data image, can't share */ +#define COFF_DMAGIC 0410 /* dirty text segment, data aligned */ +#define COFF_ZMAGIC 0413 /* The proper magic number for executables */ +#define COFF_SHMAGIC 0443 /* shared library header */ + +/********************** STORAGE CLASSES **********************/ + +/* This used to be defined as -1, but now n_sclass is unsigned. */ +#define C_EFCN 0xff /* physical end of function */ +#define C_NULL 0 +#define C_AUTO 1 /* automatic variable */ +#define C_EXT 2 /* external symbol */ +#define C_STAT 3 /* static */ +#define C_REG 4 /* register variable */ +#define C_EXTDEF 5 /* external definition */ +#define C_LABEL 6 /* label */ +#define C_ULABEL 7 /* undefined label */ +#define C_MOS 8 /* member of structure */ +#define C_ARG 9 /* function argument */ +#define C_STRTAG 10 /* structure tag */ +#define C_MOU 11 /* member of union */ +#define C_UNTAG 12 /* union tag */ +#define C_TPDEF 13 /* type definition */ +#define C_USTATIC 14 /* undefined static */ +#define C_ENTAG 15 /* enumeration tag */ +#define C_MOE 16 /* member of enumeration */ +#define C_REGPARM 17 /* register parameter */ +#define C_FIELD 18 /* bit field */ +#define C_AUTOARG 19 /* auto argument */ +#define C_LASTENT 20 /* dummy entry (end of block) */ +#define C_BLOCK 100 /* ".bb" or ".eb" */ +#define C_FCN 101 /* ".bf" or ".ef" */ +#define C_EOS 102 /* end of structure */ +#define C_FILE 103 /* file name */ +#define C_LINE 104 /* line # reformatted as symbol table entry */ +#define C_ALIAS 105 /* duplicate tag */ +#define C_HIDDEN 106 /* ext symbol in dmert public lib */ + +#define C_WEAKEXT 127 /* weak symbol -- GNU extension */ + +/* New storage classes for TI COFF */ +#define C_UEXT 19 /* Tentative external definition */ +#define C_STATLAB 20 /* Static load time label */ +#define C_EXTLAB 21 /* External load time label */ +#define C_SYSTEM 23 /* System Wide variable */ + +/* New storage classes for WINDOWS_NT */ +#define C_SECTION 104 /* section name */ +#define C_NT_WEAK 105 /* weak external */ + + /* New storage classes for 80960 */ + +/* C_LEAFPROC is obsolete. Use C_LEAFEXT or C_LEAFSTAT */ +#define C_LEAFPROC 108 /* Leaf procedure, "call" via BAL */ + +#define C_SCALL 107 /* Procedure reachable via system call */ +#define C_LEAFEXT 108 /* External leaf */ +#define C_LEAFSTAT 113 /* Static leaf */ +#define C_OPTVAR 109 /* Optimized variable */ +#define C_DEFINE 110 /* Preprocessor #define */ +#define C_PRAGMA 111 /* Advice to compiler or linker */ +#define C_SEGMENT 112 /* 80960 segment name */ + + /* Storage classes for m88k */ +#define C_SHADOW 107 /* shadow symbol */ +#define C_VERSION 108 /* coff version symbol */ + + /* New storage classes for RS/6000 */ +#define C_HIDEXT 107 /* Un-named external symbol */ +#define C_BINCL 108 /* Marks beginning of include file */ +#define C_EINCL 109 /* Marks ending of include file */ + + /* storage classes for stab symbols for RS/6000 */ +#define C_GSYM (0x80) +#define C_LSYM (0x81) +#define C_PSYM (0x82) +#define C_RSYM (0x83) +#define C_RPSYM (0x84) +#define C_STSYM (0x85) +#define C_TCSYM (0x86) +#define C_BCOMM (0x87) +#define C_ECOML (0x88) +#define C_ECOMM (0x89) +#define C_DECL (0x8c) +#define C_ENTRY (0x8d) +#define C_FUN (0x8e) +#define C_BSTAT (0x8f) +#define C_ESTAT (0x90) + +/* Storage classes for Thumb symbols */ +#define C_THUMBEXT (128 + C_EXT) /* 130 */ +#define C_THUMBSTAT (128 + C_STAT) /* 131 */ +#define C_THUMBLABEL (128 + C_LABEL) /* 134 */ +#define C_THUMBEXTFUNC (C_THUMBEXT + 20) /* 150 */ +#define C_THUMBSTATFUNC (C_THUMBSTAT + 20) /* 151 */ + +/********************** SECTION HEADER **********************/ + +struct COFF_scnhdr { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries */ + char s_flags[4]; /* flags */ +}; + +#define COFF_SCNHDR struct COFF_scnhdr +#define COFF_SCNHSZ sizeof(COFF_SCNHDR) + +/* + * names of "special" sections + */ + +#define COFF_TEXT ".text" +#define COFF_DATA ".data" +#define COFF_BSS ".bss" +#define COFF_COMMENT ".comment" +#define COFF_LIB ".lib" + +#define COFF_SECT_TEXT 0 /* Section for instruction code */ +#define COFF_SECT_DATA 1 /* Section for initialized globals */ +#define COFF_SECT_BSS 2 /* Section for un-initialized globals */ +#define COFF_SECT_REQD 3 /* Minimum number of sections for good file */ + +#define COFF_STYP_REG 0x00 /* regular segment */ +#define COFF_STYP_DSECT 0x01 /* dummy segment */ +#define COFF_STYP_NOLOAD 0x02 /* no-load segment */ +#define COFF_STYP_GROUP 0x04 /* group segment */ +#define COFF_STYP_PAD 0x08 /* .pad segment */ +#define COFF_STYP_COPY 0x10 /* copy section */ +#define COFF_STYP_TEXT 0x20 /* .text segment */ +#define COFF_STYP_DATA 0x40 /* .data segment */ +#define COFF_STYP_BSS 0x80 /* .bss segment */ +#define COFF_STYP_INFO 0x200 /* .comment section */ +#define COFF_STYP_OVER 0x400 /* overlay section */ +#define COFF_STYP_LIB 0x800 /* library section */ + +/* + * Shared libraries have the following section header in the data field for + * each library. + */ + +struct COFF_slib { + char sl_entsz[4]; /* Size of this entry */ + char sl_pathndx[4]; /* size of the header field */ +}; + +#define COFF_SLIBHD struct COFF_slib +#define COFF_SLIBSZ sizeof(COFF_SLIBHD) + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ + +struct COFF_lineno { + union { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[2]; /* line number */ +}; + +#define COFF_LINENO struct COFF_lineno +#define COFF_LINESZ 6 + +/********************** SYMBOLS **********************/ + +#define COFF_E_SYMNMLEN 8 /* # characters in a short symbol name */ +#define COFF_E_FILNMLEN 14 /* # characters in a file name */ +#define COFF_E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +/* + * All symbols and sections have the following definition + */ + +struct COFF_syment +{ + union { + char e_name[E_SYMNMLEN]; /* Symbol name (first 8 characters) */ + struct { + char e_zeroes[4]; /* Leading zeros */ + char e_offset[4]; /* Offset if this is a header section */ + } e; + } e; + + char e_value[4]; /* Value (address) of the segment */ + char e_scnum[2]; /* Section number */ + char e_type[2]; /* Type of section */ + char e_sclass[1]; /* Loader class */ + char e_numaux[1]; /* Number of auxiliary entries which follow */ +}; + +#define COFF_N_BTMASK (0xf) /* Mask for important class bits */ +#define COFF_N_TMASK (0x30) /* Mask for important type bits */ +#define COFF_N_BTSHFT (4) /* # bits to shift class field */ +#define COFF_N_TSHIFT (2) /* # bits to shift type field */ + +/* + * Auxiliary entries because the main table is too limiting. + */ + +union COFF_auxent { + +/* + * Debugger information + */ + + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + + char x_tvndx[2]; /* tv index */ + } x_sym; + +/* + * Source file names (debugger information) + */ + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + +/* + * Section information + */ + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } x_scn; + +/* + * Transfer vector (branch table) + */ + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ +}; + +#define COFF_SYMENT struct COFF_syment +#define COFF_SYMESZ 18 +#define COFF_AUXENT union COFF_auxent +#define COFF_AUXESZ 18 + +#define COFF_ETEXT "etext" + +/********************** RELOCATION DIRECTIVES **********************/ + +struct COFF_reloc { + char r_vaddr[4]; /* Virtual address of item */ + char r_symndx[4]; /* Symbol index in the symtab */ + char r_type[2]; /* Relocation type */ +}; + +#define COFF_RELOC struct COFF_reloc +#define COFF_RELSZ 10 + +#define COFF_DEF_DATA_SECTION_ALIGNMENT 4 +#define COFF_DEF_BSS_SECTION_ALIGNMENT 4 +#define COFF_DEF_TEXT_SECTION_ALIGNMENT 4 + +/* For new sections we haven't heard of before */ +#define COFF_DEF_SECTION_ALIGNMENT 4 Index: common/elf.h =================================================================== --- common/elf.h (nonexistent) +++ common/elf.h (revision 1765) @@ -0,0 +1,439 @@ +#ifndef _LINUX_ELF_H +#define _LINUX_ELF_H + +#if HAVE_CONFIG_H +#include +#endif + +#ifdef WORDS_BIGENDIAN +#define ELF_SHORT_H +#define ELF_LONG_H +#else +/* Load a short int from the following tables with big-endian formats */ +#define ELF_SHORT_H(ps) ((((unsigned short)(ps) >> 8) & 0xff) |\ + (((unsigned short)(ps) << 8) & 0xff00)) + +/* Load a long int from the following tables with big-endian formats */ +#define ELF_LONG_H(ps) ((((unsigned long)(ps) >> 24) & 0xff) |\ + (((unsigned long)(ps) >> 8) & 0xff00)|\ + (((unsigned long)(ps) << 8) & 0xff0000)|\ + (((unsigned long)(ps) << 24) & 0xff000000)) +#endif + +typedef unsigned long Elf32_Addr; +typedef unsigned short Elf32_Half; +typedef unsigned long Elf32_Off; +typedef long Elf32_Sword; +typedef unsigned long Elf32_Word; + +/* These constants are for the segment types stored in the image headers */ +#define PT_NULL 0 +#define PT_LOAD 1 +#define PT_DYNAMIC 2 +#define PT_INTERP 3 +#define PT_NOTE 4 +#define PT_SHLIB 5 +#define PT_PHDR 6 +#define PT_LOPROC 0x70000000 +#define PT_HIPROC 0x7fffffff + +/* These constants define the different elf file types */ +#define ET_NONE 0 +#define ET_REL 1 +#define ET_EXEC 2 +#define ET_DYN 3 +#define ET_CORE 4 +#define ET_LOPROC 5 +#define ET_HIPROC 6 + +/* These constants define the various ELF target machines */ +#define EM_NONE 0 +#define EM_M32 1 +#define EM_SPARC 2 +#define EM_386 3 +#define EM_68K 4 +#define EM_88K 5 +#define EM_486 6 /* Perhaps disused */ +#define EM_860 7 + +#define EM_MIPS 8 /* MIPS R3000 (officially, big-endian only) */ + +#define EM_MIPS_RS4_BE 10 /* MIPS R4000 big-endian */ + +#define EM_SPARC64 11 /* SPARC v9 (not official) 64-bit */ + +#define EM_PARISC 15 /* HPPA */ + +#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ + +#define EM_PPC 20 /* PowerPC */ + +/* + * This is an interim value that we will use until the committee comes + * up with a final number. + */ +#define EM_ALPHA 0x9026 + + +/* This is the info that is needed to parse the dynamic section of the file */ +#define DT_NULL 0 +#define DT_NEEDED 1 +#define DT_PLTRELSZ 2 +#define DT_PLTGOT 3 +#define DT_HASH 4 +#define DT_STRTAB 5 +#define DT_SYMTAB 6 +#define DT_RELA 7 +#define DT_RELASZ 8 +#define DT_RELAENT 9 +#define DT_STRSZ 10 +#define DT_SYMENT 11 +#define DT_INIT 12 +#define DT_FINI 13 +#define DT_SONAME 14 +#define DT_RPATH 15 +#define DT_SYMBOLIC 16 +#define DT_REL 17 +#define DT_RELSZ 18 +#define DT_RELENT 19 +#define DT_PLTREL 20 +#define DT_DEBUG 21 +#define DT_TEXTREL 22 +#define DT_JMPREL 23 +#define DT_LOPROC 0x70000000 +#define DT_HIPROC 0x7fffffff + +/* This info is needed when parsing the symbol table */ +#define STB_LOCAL 0 +#define STB_GLOBAL 1 +#define STB_WEAK 2 + +#define STT_NOTYPE 0 +#define STT_OBJECT 1 +#define STT_FUNC 2 +#define STT_SECTION 3 +#define STT_FILE 4 + +#define ELF32_ST_BIND(x) ((x) >> 4) +#define ELF32_ST_TYPE(x) (((unsigned int) x) & 0xf) + +/* Symbolic values for the entries in the auxiliary table + put on the initial stack */ +#define AT_NULL 0 /* end of vector */ +#define AT_IGNORE 1 /* entry should be ignored */ +#define AT_EXECFD 2 /* file descriptor of program */ +#define AT_PHDR 3 /* program headers for program */ +#define AT_PHENT 4 /* size of program header entry */ +#define AT_PHNUM 5 /* number of program headers */ +#define AT_PAGESZ 6 /* system page size */ +#define AT_BASE 7 /* base address of interpreter */ +#define AT_FLAGS 8 /* flags */ +#define AT_ENTRY 9 /* entry point of program */ +#define AT_NOTELF 10 /* program is not ELF */ +#define AT_UID 11 /* real uid */ +#define AT_EUID 12 /* effective uid */ +#define AT_GID 13 /* real gid */ +#define AT_EGID 14 /* effective gid */ + + +typedef struct dynamic{ + Elf32_Sword d_tag; + union{ + Elf32_Sword d_val; + Elf32_Addr d_ptr; + } d_un; +} Elf32_Dyn; + +typedef struct { + unsigned long long d_tag; /* entry tag value */ + union { + unsigned long long d_val; + unsigned long long d_ptr; + } d_un; +} Elf64_Dyn; + +/* The following are used with relocations */ +#define ELF32_R_SYM(x) ((x) >> 8) +#define ELF32_R_TYPE(x) ((x) & 0xff) + +#define R_386_NONE 0 +#define R_386_32 1 +#define R_386_PC32 2 +#define R_386_GOT32 3 +#define R_386_PLT32 4 +#define R_386_COPY 5 +#define R_386_GLOB_DAT 6 +#define R_386_JMP_SLOT 7 +#define R_386_RELATIVE 8 +#define R_386_GOTOFF 9 +#define R_386_GOTPC 10 +#define R_386_NUM 11 + +#define R_68K_NONE 0 +#define R_68K_32 1 +#define R_68K_16 2 +#define R_68K_8 3 +#define R_68K_PC32 4 +#define R_68K_PC16 5 +#define R_68K_PC8 6 +#define R_68K_GOT32 7 +#define R_68K_GOT16 8 +#define R_68K_GOT8 9 +#define R_68K_GOT32O 10 +#define R_68K_GOT16O 11 +#define R_68K_GOT8O 12 +#define R_68K_PLT32 13 +#define R_68K_PLT16 14 +#define R_68K_PLT8 15 +#define R_68K_PLT32O 16 +#define R_68K_PLT16O 17 +#define R_68K_PLT8O 18 +#define R_68K_COPY 19 +#define R_68K_GLOB_DAT 20 +#define R_68K_JMP_SLOT 21 +#define R_68K_RELATIVE 22 + +typedef struct elf32_rel { + Elf32_Addr r_offset; + Elf32_Word r_info; +} Elf32_Rel; + +typedef struct elf64_rel { + unsigned long long r_offset; /* Location at which to apply the action */ + unsigned long long r_info; /* index and type of relocation */ +} Elf64_Rel; + +typedef struct elf32_rela{ + Elf32_Addr r_offset; + Elf32_Word r_info; + Elf32_Sword r_addend; +} Elf32_Rela; + +typedef struct elf64_rela { + unsigned long long r_offset; /* Location at which to apply the action */ + unsigned long long r_info; /* index and type of relocation */ + unsigned long long r_addend; /* Constant addend used to compute value */ +} Elf64_Rela; + +typedef struct elf32_sym{ + Elf32_Word st_name; + Elf32_Addr st_value; + Elf32_Word st_size; + unsigned char st_info; + unsigned char st_other; + Elf32_Half st_shndx; +} Elf32_Sym; + +typedef struct elf64_sym { + unsigned int st_name; /* Symbol name, index in string tbl */ + unsigned char st_info; /* Type and binding attributes */ + unsigned char st_other; /* No defined meaning, 0 */ + unsigned short st_shndx; /* Associated section index */ + unsigned long long st_value; /* Value of the symbol */ + unsigned long long st_size; /* Associated symbol size */ +} Elf64_Sym; + + +#define EI_NIDENT 16 + +typedef struct elf32_hdr{ + unsigned char e_ident[EI_NIDENT]; + Elf32_Half e_type; + Elf32_Half e_machine; + Elf32_Word e_version; + Elf32_Addr e_entry; /* Entry point */ + Elf32_Off e_phoff; + Elf32_Off e_shoff; + Elf32_Word e_flags; + Elf32_Half e_ehsize; + Elf32_Half e_phentsize; + Elf32_Half e_phnum; + Elf32_Half e_shentsize; + Elf32_Half e_shnum; + Elf32_Half e_shstrndx; +} Elf32_Ehdr; + +typedef struct elf64_hdr { + unsigned char e_ident[16]; /* ELF "magic number" */ + short int e_type; + short unsigned int e_machine; + int e_version; + unsigned long long e_entry; /* Entry point virtual address */ + unsigned long long e_phoff; /* Program header table file offset */ + unsigned long long e_shoff; /* Section header table file offset */ + int e_flags; + short int e_ehsize; + short int e_phentsize; + short int e_phnum; + short int e_shentsize; + short int e_shnum; + short int e_shstrndx; +} Elf64_Ehdr; + +/* These constants define the permissions on sections in the program + header, p_flags. */ +#define PF_R 0x4 +#define PF_W 0x2 +#define PF_X 0x1 + +typedef struct elf32_phdr{ + Elf32_Word p_type; + Elf32_Off p_offset; + Elf32_Addr p_vaddr; + Elf32_Addr p_paddr; + Elf32_Word p_filesz; + Elf32_Word p_memsz; + Elf32_Word p_flags; + Elf32_Word p_align; +} Elf32_Phdr; + +typedef struct elf64_phdr { + int p_type; + int p_flags; + unsigned long long p_offset; /* Segment file offset */ + unsigned long long p_vaddr; /* Segment virtual address */ + unsigned long long p_paddr; /* Segment physical address */ + unsigned long long p_filesz; /* Segment size in file */ + unsigned long long p_memsz; /* Segment size in memory */ + unsigned long long p_align; /* Segment alignment, file & memory */ +} Elf64_Phdr; + +/* sh_type */ +#define SHT_NULL 0 +#define SHT_PROGBITS 1 +#define SHT_SYMTAB 2 +#define SHT_STRTAB 3 +#define SHT_RELA 4 +#define SHT_HASH 5 +#define SHT_DYNAMIC 6 +#define SHT_NOTE 7 +#define SHT_NOBITS 8 +#define SHT_REL 9 +#define SHT_SHLIB 10 +#define SHT_DYNSYM 11 +#define SHT_NUM 12 +#define SHT_LOPROC 0x70000000 +#define SHT_HIPROC 0x7fffffff +#define SHT_LOUSER 0x80000000 +#define SHT_HIUSER 0xffffffff + +/* sh_flags */ +#define SHF_WRITE 0x1 +#define SHF_ALLOC 0x2 +#define SHF_EXECINSTR 0x4 +#define SHF_MASKPROC 0xf0000000 + +/* special section indexes */ +#define SHN_UNDEF 0 +#define SHN_LORESERVE 0xff00 +#define SHN_LOPROC 0xff00 +#define SHN_HIPROC 0xff1f +#define SHN_ABS 0xfff1 +#define SHN_COMMON 0xfff2 +#define SHN_HIRESERVE 0xffff + +typedef struct elf32_shdr { + Elf32_Word sh_name; + Elf32_Word sh_type; + Elf32_Word sh_flags; + Elf32_Addr sh_addr; + Elf32_Off sh_offset; + Elf32_Word sh_size; + Elf32_Word sh_link; + Elf32_Word sh_info; + Elf32_Word sh_addralign; + Elf32_Word sh_entsize; +} Elf32_Shdr; + +typedef struct elf64_shdr { + unsigned int sh_name; /* Section name, index in string tbl */ + unsigned int sh_type; /* Type of section */ + unsigned long long sh_flags; /* Miscellaneous section attributes */ + unsigned long long sh_addr; /* Section virtual addr at execution */ + unsigned long long sh_offset; /* Section file offset */ + unsigned long long sh_size; /* Size of section in bytes */ + unsigned int sh_link; /* Index of another section */ + unsigned int sh_info; /* Additional section information */ + unsigned long long sh_addralign; /* Section alignment */ + unsigned long long sh_entsize; /* Entry size if section holds table */ +} Elf64_Shdr; + +#define EI_MAG0 0 /* e_ident[] indexes */ +#define EI_MAG1 1 +#define EI_MAG2 2 +#define EI_MAG3 3 +#define EI_CLASS 4 +#define EI_DATA 5 +#define EI_VERSION 6 +#define EI_PAD 7 + +#define ELFMAG0 0x7f /* EI_MAG */ +#define ELFMAG1 'E' +#define ELFMAG2 'L' +#define ELFMAG3 'F' +#define ELFMAG "\177ELF" +#define SELFMAG 4 + +#define ELFCLASSNONE 0 /* EI_CLASS */ +#define ELFCLASS32 1 +#define ELFCLASS64 2 +#define ELFCLASSNUM 3 + +#define ELFDATANONE 0 /* e_ident[EI_DATA] */ +#define ELFDATA2LSB 1 +#define ELFDATA2MSB 2 + +#define EV_NONE 0 /* e_version, EI_VERSION */ +#define EV_CURRENT 1 +#define EV_NUM 2 + +/* Notes used in ET_CORE */ +#define NT_PRSTATUS 1 +#define NT_PRFPREG 2 +#define NT_PRPSINFO 3 +#define NT_TASKSTRUCT 4 + +/* Note header in a PT_NOTE section */ +typedef struct elf32_note { + Elf32_Word n_namesz; /* Name size */ + Elf32_Word n_descsz; /* Content size */ + Elf32_Word n_type; /* Content type */ +} Elf32_Nhdr; + +/* Note header in a PT_NOTE section */ +/* + * For now we use the 32 bit version of the structure until we figure + * out whether we need anything better. Note - on the Alpha, "unsigned int" + * is only 32 bits. + */ +typedef struct elf64_note { + unsigned int n_namesz; /* Name size */ + unsigned int n_descsz; /* Content size */ + unsigned int n_type; /* Content type */ +} Elf64_Nhdr; + +#ifdef __mc68000__ +#define ELF_START_MMAP 0xC0000000 +#endif +#ifdef __i386__ +#define ELF_START_MMAP 0x80000000 +#endif + +#if ELF_CLASS == ELFCLASS32 + +extern Elf32_Dyn _DYNAMIC []; +#define elfhdr elf32_hdr +#define elf_phdr elf32_phdr +#define elf_note elf32_note + +#else + +extern Elf64_Dyn _DYNAMIC []; +#define elfhdr elf64_hdr +#define elf_phdr elf64_phdr +#define elf_note elf64_note + +#endif + + +#endif /* _LINUX_ELF_H */ Index: common/Makefile.am =================================================================== --- common/Makefile.am (nonexistent) +++ common/Makefile.am (revision 1765) @@ -0,0 +1,22 @@ +# Makefile -- Makefile for cpu architecture independent simulation +# Copyright (C) 1999 Damjan Lampret, lampret@opencores.org +# +# This file is part of OpenRISC 1000 Architectural Simulator. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +noinst_LIBRARIES = libcommon.a +libcommon_a_SOURCES = abstract.c parse.c stats.c trace.c labels.c Index: common =================================================================== --- common (nonexistent) +++ common (revision 1765)

common Property changes : Added: svn:ignore ## -0,0 +1,2 ## +Makefile +.deps Index: or1k/sprs.c =================================================================== --- or1k/sprs.c (nonexistent) +++ or1k/sprs.c (revision 1765) @@ -0,0 +1,249 @@ +/* sprs.c -- Simulation of OR1K special-purpose registers + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include +#include +#include +#include + +#include "config.h" + +#ifdef HAVE_INTTYPES_H +#include +#endif + +#include "port.h" +#include "arch.h" +#include "abstract.h" +#include "sim-config.h" +#include "except.h" +#include "opcode/or32.h" +#include "spr_defs.h" +#include "execute.h" +#include "sprs.h" +#include "dcache_model.h" +#include "icache_model.h" +#include "tick.h" +#include "dmmu.h" +#include "immu.h" +#include "debug.h" + +DEFAULT_DEBUG_CHANNEL(spr); +DECLARE_DEBUG_CHANNEL(immu); + +static int audio_cnt = 0; + +static FILE *fo = 0; + +/* Set a specific SPR with a value. */ +void mtspr(uint16_t regno, const uorreg_t value) +{ + uorreg_t prev_val; + + prev_val = cpu_state.sprs[regno]; + cpu_state.sprs[regno] = value; + + TRACE("%s\n", dump_spr(regno, value)); + + /* MM: Register hooks. */ + switch (regno) { + case SPR_TTCR: + spr_write_ttcr (value); + break; + case SPR_TTMR: + spr_write_ttmr (prev_val); + break; + /* Data cache simulateing stuff */ + case SPR_DCBPR: + /* FIXME: This is not correct. The arch. manual states: "Memory accesses + * are not recorded (Unlike load or store instructions) and cannot invoke + * any exception". If the physical address is invalid a bus error will be + * generated. Also if the effective address is not resident in the mmu + * the read will happen from address 0, which is naturally not correct. */ + dc_simulate_read(peek_into_dtlb(value, 0, 1), value, 4); + cpu_state.sprs[SPR_DCBPR] = 0; + break; + case SPR_DCBFR: + dc_inv(value); + cpu_state.sprs[SPR_DCBFR] = -1; + break; + case SPR_DCBIR: + dc_inv(value); + cpu_state.sprs[SPR_DCBIR] = 0; + break; + case SPR_DCBWR: + cpu_state.sprs[SPR_DCBWR] = 0; + break; + case SPR_DCBLR: + cpu_state.sprs[SPR_DCBLR] = 0; + break; + /* Instruction cache simulateing stuff */ + case SPR_ICBPR: + /* FIXME: The arch manual does not say what happens when an invalid memory + * location is specified. I guess the same as for the DCBPR register */ + ic_simulate_fetch(peek_into_itlb(value), value); + cpu_state.sprs[SPR_ICBPR] = 0; + break; + case SPR_ICBIR: + ic_inv(value); + cpu_state.sprs[SPR_ICBIR] = 0; + break; + case SPR_ICBLR: + cpu_state.sprs[SPR_ICBLR] = 0; + break; + case SPR_SR: + cpu_state.sprs[regno] |= SPR_SR_FO; +#if DYNAMIC_EXECUTION + if((value & SPR_SR_IME) && !(prev_val & SPR_SR_IME)) { + TRACE_(immu)("IMMU just became enabled (%lli).\n", runtime.sim.cycles); + recheck_immu(IMMU_GOT_ENABLED); + } else if(!(value & SPR_SR_IME) && (prev_val & SPR_SR_IME)) { + TRACE_(immu)("Remove counting of mmu hit delay with cycles (%lli)\n", + runtime.sim.cycles); + recheck_immu(IMMU_GOT_DISABLED); + } +#endif + break; + case SPR_NPC: + { + /* The debugger has redirected us to a new address */ + /* This is usually done to reissue an instruction + which just caused a breakpoint exception. */ + cpu_state.pc = value; + + if(!value && config.sim.verbose) + PRINTF("WARNING: PC just set to 0!\n"); + + /* Clear any pending delay slot jumps also */ + cpu_state.delay_insn = 0; + pcnext = value + 4; + } + break; + case 0xFFFD: + fo = fopen ("audiosim.pcm", "wb+"); + if (!fo) PRINTF("Cannot open audiosim.pcm\n"); + PRINTF("Audio opened.\n"); + break; + case 0xFFFE: + if (!fo) PRINTF("audiosim.pcm not opened\n"); + fputc (value & 0xFF, fo); + if ((audio_cnt % 1024) == 0) + PRINTF("%i\n", audio_cnt); + audio_cnt++; + break; + case 0xFFFF: + fclose(fo); + PRINTF("Audio closed.\n"); + sim_done(); + break; + case SPR_PMR: + /* PMR[SDF] and PMR[DCGE] are ignored completely. */ + if (value & SPR_PMR_SUME) { + PRINTF ("SUSPEND: PMR[SUME] bit was set.\n"); + sim_done(); + } + break; + default: + /* Mask reserved bits in DTLBMR and DTLBMR registers */ + if ( (regno >= SPR_DTLBMR_BASE(0)) && (regno < SPR_DTLBTR_LAST(3))) { + if((regno & 0xff) < 0x80) + cpu_state.sprs[regno] = ((value / config.dmmu.pagesize) * config.dmmu.pagesize) | + (value & (SPR_DTLBMR_V | SPR_DTLBMR_PL1 | SPR_DTLBMR_CID | SPR_DTLBMR_LRU)); + else + cpu_state.sprs[regno] = ((value / config.dmmu.pagesize) * config.dmmu.pagesize) | + (value & (SPR_DTLBTR_CC | SPR_DTLBTR_CI | SPR_DTLBTR_WBC | SPR_DTLBTR_WOM | + SPR_DTLBTR_A | SPR_DTLBTR_D | SPR_DTLBTR_URE | SPR_DTLBTR_UWE | SPR_DTLBTR_SRE | + SPR_DTLBTR_SWE)); + } + + /* Mask reseved bits in ITLBMR and ITLBMR registers */ + if ( (regno >= SPR_ITLBMR_BASE(0)) && (regno < SPR_ITLBTR_LAST(3))) { + TRACE_(immu)("Writting to an mmu way (reg: %"PRIx16", value: %"PRIx32")\n", + regno, value); + if((regno & 0xff) < 0x80) + cpu_state.sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) | + (value & (SPR_ITLBMR_V | SPR_ITLBMR_PL1 | SPR_ITLBMR_CID | SPR_ITLBMR_LRU)); + else + cpu_state.sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) | + (value & (SPR_ITLBTR_CC | SPR_ITLBTR_CI | SPR_ITLBTR_WBC | SPR_ITLBTR_WOM | + SPR_ITLBTR_A | SPR_ITLBTR_D | SPR_ITLBTR_SXE | SPR_ITLBTR_UXE)); + +#if DYNAMIC_EXECUTION + if(cpu_state.sprs[SPR_SR] & SPR_SR_IME) { + /* The immu got reconfigured. Recheck if the current page in execution + * is resident in the immu ways. This check would be done during the + * instruction fetch but since the dynamic execution model does not do + * instruction fetchs, do it now. */ + recheck_immu(0); + } +#endif + } + + /* Links to GPRS */ + if(regno >= 0x0400 && regno < 0x0420) { + cpu_state.reg[regno - 0x0400] = value; + } + break; + } +} + +/* Get a specific SPR. */ +uorreg_t mfspr(const uint16_t regno) +{ + uorreg_t ret; + + ret = cpu_state.sprs[regno]; + + switch (regno) { + case SPR_NPC: + ret = cpu_state.pc; + case SPR_TTCR: + ret = spr_read_ttcr(); + default: + /* Links to GPRS */ + if(regno >= 0x0400 && regno < 0x0420) + ret = cpu_state.reg[regno - 0x0400]; + } + + TRACE("%s\n", dump_spr(regno, ret)); + + return ret; +} + +/* Show status of important SPRs. */ +void sprs_status(void) +{ + PRINTF("VR : 0x%"PRIxREG" UPR : 0x%"PRIxREG"\n", cpu_state.sprs[SPR_VR], + cpu_state.sprs[SPR_UPR]); + PRINTF("SR : 0x%"PRIxREG"\n", cpu_state.sprs[SPR_SR]); + PRINTF("MACLO: 0x%"PRIxREG" MACHI: 0x%"PRIxREG"\n", + cpu_state.sprs[SPR_MACLO], cpu_state.sprs[SPR_MACHI]); + PRINTF("EPCR0: 0x%"PRIxADDR" EPCR1: 0x%"PRIxADDR"\n", + cpu_state.sprs[SPR_EPCR_BASE], cpu_state.sprs[SPR_EPCR_BASE+1]); + PRINTF("EEAR0: 0x%"PRIxADDR" EEAR1: 0x%"PRIxADDR"\n", + cpu_state.sprs[SPR_EEAR_BASE], cpu_state.sprs[SPR_EEAR_BASE+1]); + PRINTF("ESR0 : 0x%"PRIxREG" ESR1 : 0x%"PRIxREG"\n", + cpu_state.sprs[SPR_ESR_BASE], cpu_state.sprs[SPR_ESR_BASE+1]); + PRINTF("TTMR : 0x%"PRIxREG" TTCR : 0x%"PRIxREG"\n", + cpu_state.sprs[SPR_TTMR], cpu_state.sprs[SPR_TTCR]); + PRINTF("PICMR: 0x%"PRIxREG" PICSR: 0x%"PRIxREG"\n", + cpu_state.sprs[SPR_PICMR], cpu_state.sprs[SPR_PICSR]); + PRINTF("PPC: 0x%"PRIxADDR" NPC : 0x%"PRIxADDR"\n", + cpu_state.sprs[SPR_PPC], cpu_state.sprs[SPR_NPC]); +} Index: or1k/spr_dump.c =================================================================== --- or1k/spr_dump.c (nonexistent) +++ or1k/spr_dump.c (revision 1765) @@ -0,0 +1,526 @@ +/* spr_dump.c -- Dump given spr in human readable form + Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include + +#include "config.h" + +#ifdef HAVE_INTTYPES_H +#include +#endif + +#include "port.h" +#include "arch.h" +#include "abstract.h" +#include "opcode/or32.h" +#include "spr_defs.h" +#include "execute.h" +#include "debug.h" +#include "misc.h" + +DEFAULT_DEBUG_CHANNEL(spr); + +struct spr_bit_def { + const char *name; + uorreg_t mask; +}; + +struct spr_def { + uint16_t from_spr; + uint16_t to_spr; + const char *name; + const struct spr_bit_def *bits; +}; + +/* One value spr */ +static const struct spr_bit_def spr_one_val[] = { + { "", 0xffffffff }, + { NULL, 0 } }; + +/*---------------------------------------------------------[ System group ]---*/ +/* Supervisor register */ +static const struct spr_bit_def spr_sr[] = { + { "SR_CID", SPR_SR_CID }, + { "SR_SUMRA", SPR_SR_SUMRA }, + { "SR_FO", SPR_SR_FO }, + { "SR_EPH", SPR_SR_EPH }, + { "SR_DSX", SPR_SR_DSX }, + { "SR_OVE", SPR_SR_OVE }, + { "SR_OV", SPR_SR_OV }, + { "SR_CY", SPR_SR_CY }, + { "SR_F", SPR_SR_F }, + { "SR_CE", SPR_SR_CE }, + { "SR_IME", SPR_SR_IME }, + { "SR_DME", SPR_SR_DME }, + { "SR_ICE", SPR_SR_ICE }, + { "SR_DCE", SPR_SR_DCE }, + { "SR_IEE", SPR_SR_IEE }, + { "SR_TEE", SPR_SR_TEE }, + { "SR_SM", SPR_SR_SM }, + { NULL, 0 } }; + +/* Version register */ +static const struct spr_bit_def spr_vr[] = { + { "VR_VER", SPR_VR_VER }, + { "VR_REV", SPR_VR_REV }, + { NULL, 0 } }; + +/* upr register */ +static const struct spr_bit_def spr_upr[] = { + { "UPR_UP", SPR_UPR_UP }, + { "UPR_DCP", SPR_UPR_DCP }, + { "UPR_ICP", SPR_UPR_ICP }, + { "UPR_DMP", SPR_UPR_DMP }, + { "UPR_IMP", SPR_UPR_IMP }, + { "UPR_OB32P", SPR_UPR_OB32P }, + { "UPR_OB64P", SPR_UPR_OB64P }, + { "UPR_OF32P", SPR_UPR_OF32P }, + { "UPR_OF64P", SPR_UPR_OF64P }, + { "UPR_OV32P", SPR_UPR_OV32P }, + { "UPR_OV64P", SPR_UPR_OV64P }, + { "UPR_DUP", SPR_UPR_DUP }, + { "UPR_PCUP", SPR_UPR_PCUP }, + { "UPR_PMP", SPR_UPR_PMP }, + { "UPR_PICP", SPR_UPR_PICP }, + { "UPR_TTP", SPR_UPR_TTP }, + { "UPR_SRP", SPR_UPR_SRP }, + { "UPR_RES", SPR_UPR_RES }, + { "UPR_CUST", SPR_UPR_CUST }, + { NULL, 0 } }; + +/* dmmucfgr register */ +static const struct spr_bit_def spr_dmmucfgr[] = { + { "DMMUCFGR_NTW", SPR_DMMUCFGR_NTW }, + { "DMMUCFGR_NTS", SPR_DMMUCFGR_NTS }, + { "DMMUCFGR_NAE", SPR_DMMUCFGR_NAE }, + { "DMMUCFGR_CRI", SPR_DMMUCFGR_CRI }, + { "DMMUCFGR_PRI", SPR_DMMUCFGR_PRI }, + { "DMMUCFGR_TEIRI", SPR_DMMUCFGR_TEIRI }, + { "DMMUCFGR_HTR", SPR_DMMUCFGR_HTR }, + { NULL, 0 } }; + +/* immucfgr register */ +static const struct spr_bit_def spr_immucfgr[] = { + { "IMMUCFGR_NTW", SPR_IMMUCFGR_NTW }, + { "IMMUCFGR_NTS", SPR_IMMUCFGR_NTS }, + { "IMMUCFGR_NAE", SPR_IMMUCFGR_NAE }, + { "IMMUCFGR_CRI", SPR_IMMUCFGR_CRI }, + { "IMMUCFGR_PRI", SPR_IMMUCFGR_PRI }, + { "IMMUCFGR_TEIRI", SPR_IMMUCFGR_TEIRI }, + { "IMMUCFGR_HTR", SPR_IMMUCFGR_HTR }, + { NULL, 0 } }; + +/* dccfgr register */ +static const struct spr_bit_def spr_dccfgr[] = { + { "DCCFGR_NCW", SPR_DCCFGR_NCW }, + { "DCCFGR_NCS", SPR_DCCFGR_NCS }, + { "DCCFGR_CBS", SPR_DCCFGR_CBS }, + { "DCCFGR_CWS", SPR_DCCFGR_CWS }, + { "DCCFGR_CCRI", SPR_DCCFGR_CCRI }, + { "DCCFGR_CBIRI", SPR_DCCFGR_CBIRI }, + { "DCCFGR_CBPRI", SPR_DCCFGR_CBPRI }, + { "DCCFGR_CBLRI", SPR_DCCFGR_CBLRI }, + { "DCCFGR_CBFRI", SPR_DCCFGR_CBFRI }, + { "DCCFGR_CBWBRI", SPR_DCCFGR_CBWBRI }, + { NULL, 0 } }; + +/* iccfgr register */ +static const struct spr_bit_def spr_iccfgr[] = { + { "ICCFGR_NCW", SPR_ICCFGR_NCW }, + { "ICCFGR_NCS", SPR_ICCFGR_NCS }, + { "ICCFGR_CBS", SPR_ICCFGR_CBS }, + { "ICCFGR_CCRI", SPR_ICCFGR_CCRI }, + { "ICCFGR_CBIRI", SPR_ICCFGR_CBIRI }, + { "ICCFGR_CBPRI", SPR_ICCFGR_CBPRI }, + { "ICCFGR_CBLRI", SPR_ICCFGR_CBLRI }, + { NULL, 0 } }; + +/* System group */ +static const struct spr_def spr_sys_group[] = { + /* 000-000 */ { 0x000, 0x000, "SPR_VR", spr_vr }, + /* 001-001 */ { 0x001, 0x001, "SPR_UPR", spr_upr }, + /* 003-003 */ { 0x003, 0x003, "SPR_DMMUCFGR", spr_dmmucfgr }, + /* 004-004 */ { 0x004, 0x004, "SPR_IMMUCFGR", spr_immucfgr }, + /* 005-005 */ { 0x005, 0x005, "SPR_DCCFGR", spr_dccfgr }, + /* 006-006 */ { 0x006, 0x006, "SPR_ICCFGR", spr_iccfgr }, + /* 010-010 */ { 0x010, 0x010, "SPR_NPC", spr_one_val }, + /* 011-011 */ { 0x011, 0x011, "SPR_SR", spr_sr }, + /* 012-012 */ { 0x012, 0x012, "SPR_PPC", spr_one_val }, + /* 020-02f */ { 0x020, 0x02f, "SPR_EPCR(%i)", spr_one_val }, + /* 030-03f */ { 0x030, 0x03f, "SPR_EEAR(%i)", spr_one_val }, + /* 040-04f */ { 0x040, 0x04f, "SPR_ESR(%i)", spr_sr }, + /* 400-41f */ { 0x400, 0x41f, "GPR(%i)", spr_one_val }, + /* ----- */ { -1, -1, NULL, NULL } }; + +/*-----------------------------------------------------------[ DMMU group ]---*/ +/* Data MMU conrtol reg */ +static const struct spr_bit_def spr_dmmucr[] = { + { "DMMUCR_P2S", SPR_DMMUCR_P2S }, + { "DMMUCR_P1S", SPR_DMMUCR_P1S }, + { "DMMUCR_VADDR_WIDTH", SPR_DMMUCR_VADDR_WIDTH }, + { "DMMUCR_PADDR_WIDTH", SPR_DMMUCR_PADDR_WIDTH }, + { NULL, 0 } }; + +/* dtlbmr register */ +static const struct spr_bit_def spr_dtlbmr[] = { + { "DTLBMR_V", SPR_DTLBMR_V }, + { "DTLBMR_PL1", SPR_DTLBMR_PL1 }, + { "DTLBMR_CID", SPR_DTLBMR_CID }, + { "DTLBMR_LRU", SPR_DTLBMR_LRU }, + { "DTLBMR_VPN", SPR_DTLBMR_VPN }, + { NULL, 0 } }; + +/* dtlbtr register */ +static const struct spr_bit_def spr_dtlbtr[] = { + { "DTLBTR_CC", SPR_DTLBTR_CC }, + { "DTLBTR_CI", SPR_DTLBTR_CI }, + { "DTLBTR_WBC", SPR_DTLBTR_WBC }, + { "DTLBTR_WOM", SPR_DTLBTR_WOM }, + { "DTLBTR_A", SPR_DTLBTR_A }, + { "DTLBTR_D", SPR_DTLBTR_D }, + { "DTLBTR_URE", SPR_DTLBTR_URE }, + { "DTLBTR_UWE", SPR_DTLBTR_UWE }, + { "DTLBTR_SRE", SPR_DTLBTR_SRE }, + { "DTLBTR_SWE", SPR_DTLBTR_SWE }, + { "DTLBTR_PPN", SPR_DTLBTR_PPN }, + { NULL, 0 } }; + +/* DMMU group */ +static const struct spr_def spr_dmmu_group[] = { + /* 000-000 */ { 0, 0, "SPR_DMMUCR", spr_dmmucr }, + /* 200-27f */ { 0x200, 0x27f, "SPR_DTLBMR way 0 set %i", spr_dtlbmr }, + /* 280-2ff */ { 0x280, 0x2ff, "SPR_DTLBTR way 0 set %i", spr_dtlbtr }, + /* 300-37f */ { 0x300, 0x37f, "SPR_DTLBMR way 1 set %i", spr_dtlbmr }, + /* 380-3ff */ { 0x380, 0x3ff, "SPR_DTLBTR way 1 set %i", spr_dtlbtr }, + /* 400-47f */ { 0x400, 0x47f, "SPR_DTLBMR way 2 set %i", spr_dtlbmr }, + /* 480-4ff */ { 0x480, 0x4ff, "SPR_DTLBTR way 2 set %i", spr_dtlbtr }, + /* 500-57f */ { 0x500, 0x57f, "SPR_DTLBMR way 3 set %i", spr_dtlbmr }, + /* 580-5ff */ { 0x580, 0x5ff, "SPR_DTLBTR way 3 set %i", spr_dtlbtr }, + /* ------- */ { -1, -1, NULL, NULL } }; + +/*-----------------------------------------------------------[ IMMU group ]---*/ +/* Instruction MMU conrtol reg */ +static const struct spr_bit_def spr_immucr[] = { + { "IMMUCR_P2S", SPR_IMMUCR_P2S }, + { "IMMUCR_P1S", SPR_IMMUCR_P1S }, + { "IMMUCR_VADDR_WIDTH", SPR_IMMUCR_VADDR_WIDTH }, + { "IMMUCR_PADDR_WIDTH", SPR_IMMUCR_PADDR_WIDTH }, + { NULL, 0 } }; + +/* itlbmr register */ +static const struct spr_bit_def spr_itlbmr[] = { + { "ITLBMR_V", SPR_ITLBMR_V }, + { "ITLBMR_PL1", SPR_ITLBMR_PL1 }, + { "ITLBMR_CID", SPR_ITLBMR_CID }, + { "ITLBMR_LRU", SPR_ITLBMR_LRU }, + { "ITLBMR_VPN", SPR_ITLBMR_VPN }, + { NULL, 0 } }; + +/* itlbtr register */ +static const struct spr_bit_def spr_itlbtr[] = { + { "ITLBTR_CC", SPR_ITLBTR_CC }, + { "ITLBTR_CI", SPR_ITLBTR_CI }, + { "ITLBTR_WBC", SPR_ITLBTR_WBC }, + { "ITLBTR_WOM", SPR_ITLBTR_WOM }, + { "ITLBTR_A", SPR_ITLBTR_A }, + { "ITLBTR_D", SPR_ITLBTR_D }, + { "ITLBTR_URE", SPR_ITLBTR_SXE }, + { "ITLBTR_UWE", SPR_ITLBTR_UXE }, + { "ITLBTR_PPN", SPR_ITLBTR_PPN }, + { NULL, 0 } }; + +/* IMMU group */ +static const struct spr_def spr_immu_group[] = { + /* 000-000 */ { 0, 0, "SPR_IMMUCR", spr_immucr }, + /* 200-27f */ { 0x200, 0x27f, "SPR_ITLBMR way 0 set %i", spr_itlbmr }, + /* 280-2ff */ { 0x280, 0x2ff, "SPR_ITLBTR way 0 set %i", spr_itlbtr }, + /* 300-37f */ { 0x300, 0x37f, "SPR_ITLBMR way 1 set %i", spr_itlbmr }, + /* 380-3ff */ { 0x380, 0x3ff, "SPR_ITLBTR way 1 set %i", spr_itlbtr }, + /* 400-47f */ { 0x400, 0x47f, "SPR_ITLBMR way 2 set %i", spr_itlbmr }, + /* 480-4ff */ { 0x480, 0x4ff, "SPR_ITLBTR way 2 set %i", spr_itlbtr }, + /* 500-57f */ { 0x500, 0x57f, "SPR_ITLBMR way 3 set %i", spr_itlbmr }, + /* 580-5ff */ { 0x580, 0x5ff, "SPR_ITLBTR way 3 set %i", spr_itlbtr }, + /* ------- */ { -1, -1, NULL, NULL } }; + +/*-----------------------------------------------------[ Data cache group ]---*/ +static const struct spr_bit_def spr_dccr[] = { + { "DCCR_EW", SPR_DCCR_EW }, + { NULL, 0 } }; + +static const struct spr_def spr_dc_group[] = { + /* 000-000 */ { 0x000, 0x000, "SPR_DCCR", spr_dccr }, + /* 001-001 */ { 0x001, 0x001, "SPR_DCBPR", spr_one_val }, + /* 002-002 */ { 0x002, 0x002, "SPR_DCBFR", spr_one_val }, + /* 003-003 */ { 0x003, 0x003, "SPR_DCBIR", spr_one_val }, + /* 004-004 */ { 0x004, 0x004, "SPR_DCBWR", spr_one_val }, + /* 005-005 */ { 0x005, 0x005, "SPR_DCBLR", spr_one_val }, + /* 200-3ff */ { 0x200, 0x3ff, "SPR_DCR way 0 set %i", spr_one_val }, + /* 400-5ff */ { 0x400, 0x5ff, "SPR_DCR way 1 set %i", spr_one_val }, + /* 600-7ff */ { 0x600, 0x7ff, "SPR_DCR way 2 set %i", spr_one_val }, + /* 800-9ff */ { 0x800, 0x9ff, "SPR_DCR way 3 set %i", spr_one_val }, + /* ------- */ { -1, -1, NULL, NULL } }; + +/*----------------------------------------------[ Instruction cache group ]---*/ +static const struct spr_bit_def spr_iccr[] = { + { "ICCR_EW", SPR_ICCR_EW }, + { NULL, 0 } }; + +static const struct spr_def spr_ic_group[] = { + /* 000-000 */ { 0x000, 0x000, "SPR_ICCR", spr_iccr }, + /* 001-001 */ { 0x001, 0x001, "SPR_ICBPR", spr_one_val }, + /* 002-002 */ { 0x002, 0x002, "SPR_ICBFR", spr_one_val }, + /* 003-003 */ { 0x003, 0x003, "SPR_ICBIR", spr_one_val }, + /* 200-3ff */ { 0x200, 0x3ff, "SPR_ICR way 0 set %i", spr_one_val }, + /* 400-5ff */ { 0x400, 0x5ff, "SPR_ICR way 1 set %i", spr_one_val }, + /* 600-7ff */ { 0x600, 0x7ff, "SPR_ICR way 2 set %i", spr_one_val }, + /* 800-9ff */ { 0x800, 0x9ff, "SPR_ICR way 3 set %i", spr_one_val }, + /* ------- */ { -1, -1, NULL, NULL } }; + +/*------------------------------------------------------------[ MAC group ]---*/ +static const struct spr_def spr_mac_group[] = { + /* 1-1 */ { 0x1, 0x1, "SPR_MACLO", spr_one_val }, + /* 2-2 */ { 0x2, 0x2, "SPR_MACHI", spr_one_val }, + /* ------- */ { -1, -1, NULL, NULL } }; + +/*----------------------------------------------------------[ Debug group ]---*/ +/* dmr1 register */ +static const struct spr_bit_def spr_dmr1[] = { + { "DMR1_CW0", SPR_DMR1_CW0 }, + { "DMR1_CW1", SPR_DMR1_CW1 }, + { "DMR1_CW2", SPR_DMR1_CW2 }, + { "DMR1_CW3", SPR_DMR1_CW3 }, + { "DMR1_CW4", SPR_DMR1_CW4 }, + { "DMR1_CW5", SPR_DMR1_CW5 }, + { "DMR1_CW6", SPR_DMR1_CW6 }, + { "DMR1_CW7", SPR_DMR1_CW7 }, + { "DMR1_CW8", SPR_DMR1_CW8 }, + { "DMR1_CW9", SPR_DMR1_CW9 }, + { "DMR1_CW10", SPR_DMR1_CW10 }, + { "DMR1_ST", SPR_DMR1_ST }, + { "DMR1_BT", SPR_DMR1_BT }, + { "DMR1_DXFW", SPR_DMR1_DXFW }, + { NULL, 0 } }; + +/* dmr2 register */ +static const struct spr_bit_def spr_dmr2[] = { + { "DMR2_WCE0", SPR_DMR2_WCE0 }, + { "DMR2_WCE1", SPR_DMR2_WCE1 }, + { "DMR2_AWTC", SPR_DMR2_AWTC }, + { "DMR2_WGB", SPR_DMR2_WGB }, + { NULL, 0 } }; + +/* dwcr register */ +static const struct spr_bit_def spr_dwcr[] = { + { "DWCR_COUNT", SPR_DWCR_COUNT }, + { "DWCR_MATCH", SPR_DWCR_MATCH }, + { NULL, 0 } }; + +/* dsr register */ +static const struct spr_bit_def spr_dsr[] = { + { "DSR_RSTE", SPR_DSR_RSTE }, + { "DSR_BUSE", SPR_DSR_BUSEE }, + { "DSR_DPFE", SPR_DSR_DPFE }, + { "DSR_IPFE", SPR_DSR_IPFE }, + { "DSR_TTE", SPR_DSR_TTE }, + { "DSR_AE", SPR_DSR_AE }, + { "DSR_IIE", SPR_DSR_IIE }, + { "DSR_IE", SPR_DSR_IE }, + { "DSR_DME", SPR_DSR_DME }, + { "DSR_IME", SPR_DSR_IME }, + { "DSR_RE", SPR_DSR_RE }, + { "DSR_SCE", SPR_DSR_SCE }, + { "DSR_SSE", SPR_DSR_SSE }, + { "DSR_TE", SPR_DSR_TE }, + { NULL, 0 } }; + +/* drr register */ +static const struct spr_bit_def spr_drr[] = { + { "DRR_RSTE", SPR_DRR_RSTE }, + { "DRR_BUSE", SPR_DRR_BUSEE }, + { "DRR_DPFE", SPR_DRR_DPFE }, + { "DRR_IPFE", SPR_DRR_IPFE }, + { "DRR_TTE", SPR_DRR_TTE }, + { "DRR_AE", SPR_DRR_AE }, + { "DRR_IIE", SPR_DRR_IIE }, + { "DRR_IE", SPR_DRR_IE }, + { "DRR_DME", SPR_DRR_DME }, + { "DRR_IME", SPR_DRR_IME }, + { "DRR_RE", SPR_DRR_RE }, + { "DRR_SCE", SPR_DRR_SCE }, + { "DRR_TE", SPR_DRR_TE }, + { NULL, 0 } }; + +/* Debug group */ +static const struct spr_def spr_d_group[] = { +#if 0 + /* 00-07 */ { 0x00, 0x07, "SPR_DVR(%i)", spr_dvr }, + /* 08-0f */ { 0x08, 0x0f, "SPR_DCR(%i)", spr_dcr }, +#endif + /* 10-10 */ { 0x10, 0x10, "SPR_DMR1", spr_dmr1 }, + /* 11-11 */ { 0x11, 0x11, "SPR_DMR2", spr_dmr2 }, + /* 12-12 */ { 0x12, 0x12, "SPR_DWCR0", spr_dwcr }, + /* 13-13 */ { 0x13, 0x13, "SPR_DWCR1", spr_dwcr }, + /* 14-14 */ { 0x14, 0x14, "SPR_DSR", spr_dsr }, + /* 15-15 */ { 0x15, 0x15, "SPR_DRR", spr_drr }, + /* ----- */ { -1, -1, NULL, NULL } }; + +/*-------------------------------------------[ Performance counters group ]---*/ +static const struct spr_bit_def spr_pcmr[] = { + { "PCMR_CP", SPR_PCMR_CP }, + { "PCMR_UMRA", SPR_PCMR_UMRA }, + { "PCMR_CISM", SPR_PCMR_CISM }, + { "PCMR_CIUM", SPR_PCMR_CIUM }, + { "PCMR_LA", SPR_PCMR_LA }, + { "PCMR_SA", SPR_PCMR_SA }, + { "PCMR_IF", SPR_PCMR_IF }, + { "PCMR_DCM", SPR_PCMR_DCM }, + { "PCMR_ICM", SPR_PCMR_ICM }, + { "PCMR_IFS", SPR_PCMR_IFS }, + { "PCMR_LSUS", SPR_PCMR_LSUS }, + { "PCMR_BS", SPR_PCMR_BS }, + { "PCMR_DTLBM", SPR_PCMR_DTLBM }, + { "PCMR_ITLBM", SPR_PCMR_ITLBM }, + { "PCMR_DDS", SPR_PCMR_DDS }, + { "PCMR_WPE", SPR_PCMR_WPE }, + { NULL, 0 } }; + +static const struct spr_def spr_pc_group[] = { + /* 00-07 */ { 0x00, 0x07, "PCCR", spr_one_val }, + /* 08-0f */ { 0x08, 0x0f, "PCMR", spr_pcmr }, + /* ----- */ { -1, -1, NULL, NULL } }; + +/*------------------------------------------------[ Power managment group ]---*/ +static const struct spr_bit_def spr_pmr[] = { + { "PMR_SDF", SPR_PMR_SDF }, + { "PMR_DME", SPR_PMR_DME }, + { "PMR_SME", SPR_PMR_SME }, + { "PMR_DCGE", SPR_PMR_DCGE }, + { "PMR_SUME", SPR_PMR_SUME }, + { NULL, 0 } }; + +static const struct spr_def spr_pm_group[] = { + /* 0-0 */ { 0x0, 0x0, "SPR_PMR", spr_pmr }, + /* --- */ { -1, -1, NULL, NULL } }; + +/*------------------------------------------------------------[ PIC group ]---*/ +/* picmr register */ +static const struct spr_bit_def spr_picmr[] = { + { "PICMR_IUM", SPR_PICMR_IUM }, + { NULL, 0 } }; + +static const struct spr_def spr_pic_group[] = { + /* 0-0 */ { 0, 0, "PICMR", spr_picmr }, + /* 2-2 */ { 2, 2, "PICSR", spr_one_val }, + /* --- */ { -1, -1, NULL, NULL } }; + +/*-----------------------------------------------------[ Tick timer group ]---*/ +static const struct spr_bit_def spr_ttmr[] = { + { "TTMR_PERIOD", SPR_TTMR_PERIOD }, + { "TTMR_IP", SPR_TTMR_IP }, + { "TTMR_IE", SPR_TTMR_IE }, + { "TTMR_M", SPR_TTMR_M }, + { NULL, 0 } }; + +static const struct spr_def spr_tt_group[] = { + /* 0-0 */ { 0, 0, "TTMR", spr_ttmr }, + /* 1-1 */ { 0, 0, "TTCR", spr_one_val }, + /* --- */ { -1, -1, NULL, NULL } }; + +/* Spr groups */ +static const struct spr_def *spr_groups[] = { + /* 00 */ spr_sys_group, + /* 01 */ spr_dmmu_group, + /* 02 */ spr_immu_group, + /* 03 */ spr_dc_group, + /* 04 */ spr_ic_group, + /* 05 */ spr_mac_group, + /* 06 */ spr_d_group, + /* 07 */ spr_pc_group, + /* 08 */ spr_pm_group, + /* 09 */ spr_pic_group, + /* 0a */ spr_tt_group }; + +/* Should be long enough for everything */ +static char ret_spr[1000]; + +/* Dumps the given spr in nice, human readable form */ +char *dump_spr(uint16_t spr, uorreg_t spr_val) +{ + const struct spr_def *spr_def; + uint16_t spr_in_group = spr & (MAX_SPRS_PER_GRP - 1); + uint16_t spr_group = spr >> MAX_SPRS_PER_GRP_BITS; + const struct spr_bit_def *spr_bit_def; + + int first_bit = 1; + int i; + uorreg_t tmp; + + spr_def = spr_groups[spr_group]; + + /* Find the given spr */ + for(; spr_def->from_spr != 0xffff; spr_def++) { + if((spr_def->from_spr <= spr_in_group) && (spr_def->to_spr >= spr_in_group)) + break; + } + + if(spr_def->from_spr == 0xffff) { + sprintf(ret_spr, "Spr %"PRIx16", group %"PRIx16" = 0x%"PRIxREG"\n", + spr_in_group, spr_group, spr_val); + return ret_spr; + } + + /* Decode the spr bits and show them in a pretty format */ + if(spr_def->from_spr == spr_def->to_spr) + sprintf(ret_spr, "%s", spr_def->name); + else + sprintf(ret_spr, spr_def->name, spr_in_group - spr_def->from_spr); + strcat(ret_spr, " = "); + + /* First get all the single-bit bit fields and dump them */ + for(spr_bit_def = spr_def->bits; spr_bit_def->name; spr_bit_def++) { + if(!is_power2(spr_bit_def->mask)) + continue; + + if(!(spr_bit_def->mask & spr_val)) + continue; + + if(!first_bit) + strcat(ret_spr, " | "); + else + first_bit = 0; + strcat(ret_spr, spr_bit_def->name); + } + + /* Now dump all the multi-bit bit fields */ + for(spr_bit_def = spr_def->bits; spr_bit_def->name; spr_bit_def++) { + if(is_power2(spr_bit_def->mask)) + continue; + if(!first_bit) + strcat(ret_spr, " | "); + else + first_bit = 0; + for(tmp = spr_bit_def->mask, i = 0; !(tmp & 1); i++) + tmp >>= 1; + + sprintf(ret_spr, "%s%s = %x", ret_spr, spr_bit_def->name, + (spr_val >> i) & tmp); + } + return ret_spr; +} + Index: or1k/Makefile.am =================================================================== --- or1k/Makefile.am (nonexistent) +++ or1k/Makefile.am (revision 1765) @@ -0,0 +1,23 @@ +# Makefile -- Makefile for OR1K architecture dependent simulation +# Copyright (C) 1999 Damjan Lampret, lampret@opencores.org +# +# This file is part of OpenRISC 1000 Architectural Simulator. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +noinst_LIBRARIES = libor1k.a +libor1k_a_SOURCES = sprs.c except.c spr_dump.c + Index: or1k/sprs.h =================================================================== --- or1k/sprs.h (nonexistent) +++ or1k/sprs.h (revision 1765) @@ -0,0 +1,26 @@ +/* sprs.h -- OR1K architecture specific special-purpose registers + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* Prototypes */ +void mtspr(uint16_t regno, const uorreg_t value); +uorreg_t mfspr(const uint16_t regno); +void sprs_status(void); +char *dump_spr(uint16_t spr, uorreg_t spr_val); + + Index: or1k/except.c =================================================================== --- or1k/except.c (nonexistent) +++ or1k/except.c (revision 1765) @@ -0,0 +1,226 @@ +/* except.c -- Simulation of OR1K exceptions + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#include +#include +#include + +#include "config.h" + +#ifdef HAVE_INTTYPES_H +#include +#endif + +#include "port.h" +#include "arch.h" +#include "abstract.h" +#include "except.h" +#include "sim-config.h" +#include "debug_unit.h" +#include "opcode/or32.h" +#include "spr_defs.h" +#include "execute.h" +#include "sprs.h" +#include "debug.h" + +#if DYNAMIC_EXECUTION +#include "sched.h" +#include "rec_i386.h" +#include "op_support.h" +#endif + +DEFAULT_DEBUG_CHANNEL(except); + +int except_pending = 0; + +static const char *except_names[] = { + NULL, + "Reset", + "Bus Error", + "Data Page Fault", + "Insn Page Fault", + "Tick timer", + "Alignment", + "Illegal instruction", + "Interrupt", + "Data TLB Miss", + "Insn TLB Miss", + "Range", + "System Call", + "Trap" }; + +const char *except_name(oraddr_t except) +{ + return except_names[except >> 8]; +} + +#if DYNAMIC_EXECUTION +/* FIXME: Remove the need for this */ +/* This is needed because immu_translate can be called from do_rfe and do_jump + * in which case the scheduler does not need to get run. immu_translate can also + * be called from mtspr in which case the exceptions that it generates happen + * during an instruction and the scheduler needs to get run. */ +int immu_ex_from_insn = 0; +#endif + +/* Asserts OR1K exception. */ +/* WARNING: Don't excpect except_handle to return. Sometimes it _may_ return at + * other times it may not. */ +void except_handle(oraddr_t except, oraddr_t ea) +{ + oraddr_t except_vector; + + if(debug_ignore_exception (except)) + return; + +#if !(DYNAMIC_EXECUTION) + /* In the dynamic recompiler, this function never returns, so this is not + * needed. Ofcourse we could set it anyway, but then all code that checks + * this variable would break, since it is never reset */ + except_pending = 1; +#endif + + TRACE("Exception 0x%"PRIxADDR" (%s) at 0x%"PRIxADDR", EA: 0x%"PRIxADDR + ", cycles %lld, #%lld\n", + except, except_name(except), cpu_state.pc, ea, runtime.sim.cycles, + runtime.cpu.instructions); + + except_vector = except + (cpu_state.sprs[SPR_SR] & SPR_SR_EPH ? 0xf0000000 : 0x00000000); + +#if !(DYNAMIC_EXECUTION) + pcnext = except_vector; +#endif + + cpu_state.sprs[SPR_EEAR_BASE] = ea; + cpu_state.sprs[SPR_ESR_BASE] = cpu_state.sprs[SPR_SR]; + + cpu_state.sprs[SPR_SR] &= ~SPR_SR_OVE; /* Disable overflow flag exception. */ + + cpu_state.sprs[SPR_SR] |= SPR_SR_SM; /* SUPV mode */ + cpu_state.sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE); /* Disable interrupts. */ + + /* Address translation is always disabled when starting exception. */ + cpu_state.sprs[SPR_SR] &= ~SPR_SR_DME; + +#if DYNAMIC_EXECUTION + /* If we were called from do_scheduler and there were more jobs scheduled to + * run after this, they won't run unless the following call is made since this + * function never returns. (If we weren't called from do_scheduler, then the + * job at the head of the queue will still have some time remaining) */ + if(scheduler.job_queue->time <= 0) + do_scheduler(); +#endif + + switch(except) { + /* EPCR is irrelevent */ + case EXCEPT_RESET: + break; + /* EPCR is loaded with address of instruction that caused the exception */ + case EXCEPT_ITLBMISS: + case EXCEPT_IPF: +#if DYNAMIC_EXECUTION + /* In immu_translate except_handle is called with except_handle(..., virtaddr) */ + /* Add the immu miss delay to the cycle counter */ + if(!immu_ex_from_insn) { + cpu_state.sprs[SPR_EPCR_BASE] = get_pc() - (cpu_state.delay_insn ? 4 : 0); + } else + /* This exception came from an l.mtspr instruction in which case the pc + * points to the l.mtspr instruction when in acutal fact, it is the next + * instruction that would have faulted/missed. ea is used instead of + * cpu_state.pc + 4 because in the event that the l.mtspr instruction is + * in the delay slot of a page local jump the fault must happen on the + * instruction that was jumped to. This is handled in recheck_immu. */ + cpu_state.sprs[SPR_EPCR_BASE] = ea; + run_sched_out_of_line(immu_ex_from_insn); + /* Save the registers that are in the temporaries */ + if(!cpu_state.ts_current) + upd_reg_from_t(cpu_state.pc, !immu_ex_from_insn); + immu_ex_from_insn = 0; + break; +#endif + /* All these exceptions happen during a simulated instruction */ + case EXCEPT_BUSERR: + case EXCEPT_DPF: + case EXCEPT_ALIGN: + case EXCEPT_ILLEGAL: + case EXCEPT_DTLBMISS: + case EXCEPT_RANGE: + case EXCEPT_TRAP: +#if DYNAMIC_EXECUTION + /* Since these exceptions happen during a simulated instruction and this + * function jumps out to the exception vector the scheduler would never have + * a chance to run, therefore run it now */ + run_sched_out_of_line(1); + /* Save the registers that are in the temporaries */ + if(!cpu_state.ts_current) { + if(cpu_state.delay_insn && + (IADDR_PAGE(cpu_state.pc) == IADDR_PAGE(cpu_state.pc - 4))) + upd_reg_from_t(cpu_state.pc - 4, 0); + else + upd_reg_from_t(cpu_state.pc, 0); + } +#endif + cpu_state.sprs[SPR_EPCR_BASE] = cpu_state.pc - (cpu_state.delay_insn ? 4 : 0); + break; + /* EPCR is loaded with address of next not-yet-executed instruction */ + case EXCEPT_SYSCALL: + cpu_state.sprs[SPR_EPCR_BASE] = (cpu_state.pc + 4) - (cpu_state.delay_insn ? 4 : 0); + break; + /* These exceptions happen AFTER (or before) an instruction has been + * simulated, therefore the pc already points to the *next* instruction */ + case EXCEPT_TICK: + case EXCEPT_INT: + cpu_state.sprs[SPR_EPCR_BASE] = cpu_state.pc - (cpu_state.delay_insn ? 4 : 0); +#if !(DYNAMIC_EXECUTION) + /* If we don't update the pc now, then it will only happen *after* the next + * instruction (There would be serious problems if the next instruction just + * happens to be a branch), when it should happen NOW. */ + cpu_state.pc = pcnext; + pcnext += 4; +#else + /* except_handle() mucks around with the temporaries, which are in the state + * of the last instruction executed and not the next one, to which the pc + * now points to */ + cpu_state.pc -= 4; + + /* Save the registers that are in the temporaries */ + if(!cpu_state.ts_current) + upd_reg_from_t(cpu_state.pc, 1); +#endif + break; + } + + /* Address trnaslation is here because run_sched_out_of_line calls + * eval_insn_direct which checks out the immu for the address translation but + * if it would be disabled above then there would be not much point... */ + cpu_state.sprs[SPR_SR] &= ~SPR_SR_IME; + + /* Complex/simple execution strictly don't need this because of the + * next_delay_insn thingy but in the dynamic execution modell that doesn't + * exist and thus cpu_state.delay_insn would stick in the exception handler + * causeing grief if the first instruction of the exception handler is also in + * the delay slot of the previous instruction */ + cpu_state.delay_insn = 0; + +#if DYNAMIC_EXECUTION + cpu_state.pc = except_vector; + cpu_state.ts_current = 0; + jump_dyn_code(except_vector); +#endif +} Index: or1k/spr_defs.h =================================================================== --- or1k/spr_defs.h (nonexistent) +++ or1k/spr_defs.h (revision 1765) @@ -0,0 +1,486 @@ +/* spr_defs.h -- Defines OR1K architecture specific special-purpose registers + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +/* This file is also used by microkernel test bench. Among +others it is also used in assembly file(s). */ + +/* Definition of special-purpose registers (SPRs) */ + +#define MAX_GRPS (32) +#define MAX_SPRS_PER_GRP_BITS (11) +#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS) +#define MAX_SPRS (0x10000) + +/* Base addresses for the groups */ +#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS) + +/* System control and status group */ +#define SPR_VR (SPRGROUP_SYS + 0) +#define SPR_UPR (SPRGROUP_SYS + 1) +#define SPR_CPUCFGR (SPRGROUP_SYS + 2) +#define SPR_DMMUCFGR (SPRGROUP_SYS + 3) +#define SPR_IMMUCFGR (SPRGROUP_SYS + 4) +#define SPR_DCCFGR (SPRGROUP_SYS + 5) +#define SPR_ICCFGR (SPRGROUP_SYS + 6) +#define SPR_DCFGR (SPRGROUP_SYS + 7) +#define SPR_PCCFGR (SPRGROUP_SYS + 8) +#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */ +#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */ +#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */ +#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */ +#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */ +#define SPR_EEAR_BASE (SPRGROUP_SYS + 48) +#define SPR_EEAR_LAST (SPRGROUP_SYS + 63) +#define SPR_ESR_BASE (SPRGROUP_SYS + 64) +#define SPR_ESR_LAST (SPRGROUP_SYS + 79) + +/* Data MMU group */ +#define SPR_DMMUCR (SPRGROUP_DMMU + 0) +#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) +#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) +#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) +#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) + +/* Instruction MMU group */ +#define SPR_IMMUCR (SPRGROUP_IMMU + 0) +#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) +#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) +#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) +#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) + +/* Data cache group */ +#define SPR_DCCR (SPRGROUP_DC + 0) +#define SPR_DCBPR (SPRGROUP_DC + 1) +#define SPR_DCBFR (SPRGROUP_DC + 2) +#define SPR_DCBIR (SPRGROUP_DC + 3) +#define SPR_DCBWR (SPRGROUP_DC + 4) +#define SPR_DCBLR (SPRGROUP_DC + 5) +#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) +#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) + +/* Instruction cache group */ +#define SPR_ICCR (SPRGROUP_IC + 0) +#define SPR_ICBPR (SPRGROUP_IC + 1) +#define SPR_ICBIR (SPRGROUP_IC + 2) +#define SPR_ICBLR (SPRGROUP_IC + 3) +#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) +#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) + +/* MAC group */ +#define SPR_MACLO (SPRGROUP_MAC + 1) +#define SPR_MACHI (SPRGROUP_MAC + 2) + +/* Debug group */ +#define SPR_DVR(N) (SPRGROUP_D + (N)) +#define SPR_DCR(N) (SPRGROUP_D + 8 + (N)) +#define SPR_DMR1 (SPRGROUP_D + 16) +#define SPR_DMR2 (SPRGROUP_D + 17) +#define SPR_DWCR0 (SPRGROUP_D + 18) +#define SPR_DWCR1 (SPRGROUP_D + 19) +#define SPR_DSR (SPRGROUP_D + 20) +#define SPR_DRR (SPRGROUP_D + 21) + +/* Performance counters group */ +#define SPR_PCCR(N) (SPRGROUP_PC + (N)) +#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N)) + +/* Power management group */ +#define SPR_PMR (SPRGROUP_PM + 0) + +/* PIC group */ +#define SPR_PICMR (SPRGROUP_PIC + 0) +#define SPR_PICPR (SPRGROUP_PIC + 1) +#define SPR_PICSR (SPRGROUP_PIC + 2) + +/* Tick Timer group */ +#define SPR_TTMR (SPRGROUP_TT + 0) +#define SPR_TTCR (SPRGROUP_TT + 1) + +/* + * Bit definitions for the Version Register + * + */ +#define SPR_VR_VER 0xffff0000 /* Processor version */ +#define SPR_VR_REV 0x0000003f /* Processor revision */ + +/* + * Bit definitions for the Unit Present Register + * + */ +#define SPR_UPR_UP 0x00000001 /* UPR present */ +#define SPR_UPR_DCP 0x00000002 /* Data cache present */ +#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */ +#define SPR_UPR_DMP 0x00000008 /* Data MMU present */ +#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */ +#define SPR_UPR_OB32P 0x00000020 /* ORBIS32 present */ +#define SPR_UPR_OB64P 0x00000040 /* ORBIS64 present */ +#define SPR_UPR_OF32P 0x00000080 /* ORFPX32 present */ +#define SPR_UPR_OF64P 0x00000100 /* ORFPX64 present */ +#define SPR_UPR_OV32P 0x00000200 /* ORVDX32 present */ +#define SPR_UPR_OV64P 0x00000400 /* ORVDX64 present */ +#define SPR_UPR_DUP 0x00000800 /* Debug unit present */ +#define SPR_UPR_PCUP 0x00001000 /* Performance counters unit present */ +#define SPR_UPR_PMP 0x00002000 /* Power management present */ +#define SPR_UPR_PICP 0x00004000 /* PIC present */ +#define SPR_UPR_TTP 0x00008000 /* Tick timer present */ +#define SPR_UPR_SRP 0x00010000 /* Shadow registers present */ +#define SPR_UPR_RES 0x00fe0000 /* ORVDX32 present */ +#define SPR_UPR_CUST 0xff000000 /* Custom units */ + +/* + * Bit definitions for the Supervision Register + * + */ +#define SPR_SR_CID 0xf0000000 /* Context ID */ +#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */ +#define SPR_SR_FO 0x00008000 /* Fixed one */ +#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */ +#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ +#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ +#define SPR_SR_OV 0x00000800 /* Overflow flag */ +#define SPR_SR_CY 0x00000400 /* Carry flag */ +#define SPR_SR_F 0x00000200 /* Condition Flag */ +#define SPR_SR_CE 0x00000100 /* CID Enable */ +#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ +#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ +#define SPR_SR_DME 0x00000020 /* Data MMU Enable */ +#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ +#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ +#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ +#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ +#define SPR_SR_SM 0x00000001 /* Supervisor Mode */ + +/* + * Bit definitions for the Data MMU Control Register + * + */ +#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Instruction MMU Control Register + * + */ +#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Data TLB Match Register + * + */ +#define SPR_DTLBMR_V 0x00000001 /* Valid */ +#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_DTLBMR_CID 0x0000003c /* Context ID */ +#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Data TLB Translate Register + * + */ +#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_DTLBTR_A 0x00000010 /* Accessed */ +#define SPR_DTLBTR_D 0x00000020 /* Dirty */ +#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */ +#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */ +#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */ +#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */ +#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */ + +/* + * Bit definitions for the Instruction TLB Match Register + * + */ +#define SPR_ITLBMR_V 0x00000001 /* Valid */ +#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_ITLBMR_CID 0x0000003c /* Context ID */ +#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Instruction TLB Translate Register + * + */ +#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_ITLBTR_A 0x00000010 /* Accessed */ +#define SPR_ITLBTR_D 0x00000020 /* Dirty */ +#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */ +#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */ +#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */ + +/* + * Bit definitions for Data Cache Control register + * + */ +#define SPR_DCCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Insn Cache Control register + * + */ +#define SPR_ICCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Data Cache Configuration Register + * + */ + +#define SPR_DCCFGR_NCW 0x00000007 +#define SPR_DCCFGR_NCS 0x00000078 +#define SPR_DCCFGR_CBS 0x00000080 +#define SPR_DCCFGR_CWS 0x00000100 +#define SPR_DCCFGR_CCRI 0x00000200 +#define SPR_DCCFGR_CBIRI 0x00000400 +#define SPR_DCCFGR_CBPRI 0x00000800 +#define SPR_DCCFGR_CBLRI 0x00001000 +#define SPR_DCCFGR_CBFRI 0x00002000 +#define SPR_DCCFGR_CBWBRI 0x00004000 + +/* + * Bit definitions for Instruction Cache Configuration Register + * + */ +#define SPR_ICCFGR_NCW 0x00000007 +#define SPR_ICCFGR_NCS 0x00000078 +#define SPR_ICCFGR_CBS 0x00000080 +#define SPR_ICCFGR_CCRI 0x00000200 +#define SPR_ICCFGR_CBIRI 0x00000400 +#define SPR_ICCFGR_CBPRI 0x00000800 +#define SPR_ICCFGR_CBLRI 0x00001000 + +/* + * Bit definitions for Data MMU Configuration Register + * + */ + +#define SPR_DMMUCFGR_NTW 0x00000003 +#define SPR_DMMUCFGR_NTS 0x0000001C +#define SPR_DMMUCFGR_NAE 0x000000E0 +#define SPR_DMMUCFGR_CRI 0x00000100 +#define SPR_DMMUCFGR_PRI 0x00000200 +#define SPR_DMMUCFGR_TEIRI 0x00000400 +#define SPR_DMMUCFGR_HTR 0x00000800 + +/* + * Bit definitions for Instruction MMU Configuration Register + * + */ + +#define SPR_IMMUCFGR_NTW 0x00000003 +#define SPR_IMMUCFGR_NTS 0x0000001C +#define SPR_IMMUCFGR_NAE 0x000000E0 +#define SPR_IMMUCFGR_CRI 0x00000100 +#define SPR_IMMUCFGR_PRI 0x00000200 +#define SPR_IMMUCFGR_TEIRI 0x00000400 +#define SPR_IMMUCFGR_HTR 0x00000800 + +/* + * Bit definitions for Debug Control registers + * + */ +#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */ +#define SPR_DCR_CC 0x0000000e /* Compare condition */ +#define SPR_DCR_SC 0x00000010 /* Signed compare */ +#define SPR_DCR_CT 0x000000e0 /* Compare to */ + +/* Bit results with SPR_DCR_CC mask */ +#define SPR_DCR_CC_MASKED 0x00000000 +#define SPR_DCR_CC_EQUAL 0x00000002 +#define SPR_DCR_CC_LESS 0x00000004 +#define SPR_DCR_CC_LESSE 0x00000006 +#define SPR_DCR_CC_GREAT 0x00000008 +#define SPR_DCR_CC_GREATE 0x0000000a +#define SPR_DCR_CC_NEQUAL 0x0000000c + +/* Bit results with SPR_DCR_CT mask */ +#define SPR_DCR_CT_DISABLED 0x00000000 +#define SPR_DCR_CT_IFEA 0x00000020 +#define SPR_DCR_CT_LEA 0x00000040 +#define SPR_DCR_CT_SEA 0x00000060 +#define SPR_DCR_CT_LD 0x00000080 +#define SPR_DCR_CT_SD 0x000000a0 +#define SPR_DCR_CT_LSEA 0x000000c0 +#define SPR_DCR_CT_LSD 0x000000e0 +/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */ + +/* + * Bit definitions for Debug Mode 1 register + * + */ +#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */ +#define SPR_DMR1_CW1 0x0000000c /* Chain watchpoint 1 */ +#define SPR_DMR1_CW2 0x00000030 /* Chain watchpoint 2 */ +#define SPR_DMR1_CW3 0x000000c0 /* Chain watchpoint 3 */ +#define SPR_DMR1_CW4 0x00000300 /* Chain watchpoint 4 */ +#define SPR_DMR1_CW5 0x00000c00 /* Chain watchpoint 5 */ +#define SPR_DMR1_CW6 0x00003000 /* Chain watchpoint 6 */ +#define SPR_DMR1_CW7 0x0000c000 /* Chain watchpoint 7 */ +#define SPR_DMR1_CW8 0x00030000 /* Chain watchpoint 8 */ +#define SPR_DMR1_CW9 0x000c0000 /* Chain watchpoint 9 */ +#define SPR_DMR1_CW10 0x00300000 /* Chain watchpoint 10 */ +#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/ +#define SPR_DMR1_BT 0x00800000 /* Branch trace */ +#define SPR_DMR1_DXFW 0x01000000 /* Disable external force watchpoint */ + +/* + * Bit definitions for Debug Mode 2 register + * + */ +#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_AWTC 0x00001ffc /* Assign watchpoints to counters */ +#define SPR_DMR2_WGB 0x00ffe000 /* Watchpoints generating breakpoint */ + +/* + * Bit definitions for Debug watchpoint counter registers + * + */ +#define SPR_DWCR_COUNT 0x0000ffff /* Count */ +#define SPR_DWCR_MATCH 0xffff0000 /* Match */ + +/* + * Bit definitions for Debug stop register + * + */ +#define SPR_DSR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */ +#define SPR_DSR_AE 0x00000020 /* Alignment exception */ +#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DSR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DSR_RE 0x00000400 /* Range exception */ +#define SPR_DSR_SCE 0x00000800 /* System call exception */ +#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */ +#define SPR_DSR_TE 0x00002000 /* Trap exception */ + +/* + * Bit definitions for Debug reason register + * + */ +#define SPR_DRR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */ +#define SPR_DRR_AE 0x00000020 /* Alignment exception */ +#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DRR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DRR_RE 0x00000400 /* Range exception */ +#define SPR_DRR_SCE 0x00000800 /* System call exception */ +#define SPR_DRR_TE 0x00001000 /* Trap exception */ + +/* + * Bit definitions for Performance counters mode registers + * + */ +#define SPR_PCMR_CP 0x00000001 /* Counter present */ +#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */ +#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */ +#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */ +#define SPR_PCMR_LA 0x00000010 /* Load access event */ +#define SPR_PCMR_SA 0x00000020 /* Store access event */ +#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/ +#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */ +#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */ +#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */ +#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */ +#define SPR_PCMR_BS 0x00000800 /* Branch stall event */ +#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */ +#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */ +#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */ +#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */ + +/* + * Bit definitions for the Power management register + * + */ +#define SPR_PMR_SDF 0x0000000f /* Slow down factor */ +#define SPR_PMR_DME 0x00000010 /* Doze mode enable */ +#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */ +#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */ +#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */ + +/* + * Bit definitions for PICMR + * + */ +#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */ + +/* + * Bit definitions for PICPR + * + */ +#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */ + +/* + * Bit definitions for PICSR + * + */ +#define SPR_PICSR_IS 0xffffffff /* Interrupt status */ + +/* + * Bit definitions for Tick Timer Control Register + * + */ +#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */ +#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD +#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */ +#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */ +#define SPR_TTMR_RT 0x40000000 /* Restart tick */ +#define SPR_TTMR_SR 0x80000000 /* Single run */ +#define SPR_TTMR_CR 0xc0000000 /* Continuous run */ +#define SPR_TTMR_M 0xc0000000 /* Tick mode */ + +/* + * l.nop constants + * + */ +#define NOP_NOP 0x0000 /* Normal nop instruction */ +#define NOP_EXIT 0x0001 /* End of simulation */ +#define NOP_REPORT 0x0002 /* Simple report */ +#define NOP_PRINTF 0x0003 /* Simprintf instruction */ +#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */ +#define NOP_REPORT_FIRST 0x0400 /* Report with number */ +#define NOP_REPORT_LAST 0x03ff /* Report with number */ Index: or1k/arch.h =================================================================== --- or1k/arch.h (nonexistent) +++ or1k/arch.h (revision 1765) @@ -0,0 +1,61 @@ +/* arch.h -- OR1K architecture specific macros + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#define LINK_REG "r9" +#define LINK_REGNO (9) +#define STACK_REG "r1" +#define STACK_REGNO (1) +#define FRAME_REG "r2" +#define FRAME_REGNO (2) +#define RETURNV_REG "r11" +#define RETURNV_REGNO (11) + +/* Basic types for openrisc */ +typedef uint32_t oraddr_t; /* Address as addressed by openrisc */ +typedef uint32_t uorreg_t; /* An unsigned register of openrisc */ +typedef int32_t orreg_t; /* A signed register of openrisc */ + +#define PRIxADDR "08" PRIx32 /* How to print an openrisc address in hex */ +#define PRIxREG "08" PRIx32 /* How to print an openrisc register in hex */ +#define PRIdREG PRId32 /* How to print an openrisc register in decimals */ + +#define ADDR_C(c) UINT32_C(c) +#define REG_C(c) UINT32_C(c) + +/* Should args be passed on stack for simprintf + * + * FIXME: do not enable this since it causes problems + * in some cases (an example beeing cbasic test + * from orp testbench). the problems is in + * + * or1k/support/simprintf.c + * + * #if STACK_ARGS + * arg = eval_mem32(argaddr,&breakpoint); + * argaddr += 4; + * #else + * sprintf(regstr, "r%u", ++argaddr); + * arg = evalsim_reg(atoi(regstr)); + * #endif + * + * the access to memory should be without any + * checks (ie not like or32 application accessed it) + * + */ +#define STACK_ARGS 0 Index: or1k/opcode/or32.h =================================================================== --- or1k/opcode/or32.h (nonexistent) +++ or1k/opcode/or32.h (revision 1765) @@ -0,0 +1,208 @@ +/* Table of opcodes for the OpenRISC 1000 ISA. + Copyright 1990, 1991, 1992, 1993 Free Software Foundation, Inc. + Contributed by Damjan Lampret (lampret@opencores.org). + +This file is part of or1k_gen_isa, or1ksim, GDB and GAS. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* We treat all letters the same in encode/decode routines so + we need to assign some characteristics to them like signess etc.*/ + +#ifndef OR32_H_ISA +#define OR32_H_ISA + +#define NUM_UNSIGNED (0) +#define NUM_SIGNED (1) + +#ifndef PARAMS +#define PARAMS(x) x +#endif + +#ifndef CONST +#define CONST const +#endif + +#define MAX_GPRS 32 +#define PAGE_SIZE 8192 +#undef __HALF_WORD_INSN__ + +#define OPERAND_DELIM (',') + +#define OR32_IF_DELAY (1) +#define OR32_W_FLAG (2) +#define OR32_R_FLAG (4) + +#if defined(HAS_EXECUTION) +# if SIMPLE_EXECUTION +# include "simpl32_defs.h" +# elif DYNAMIC_EXECUTION +# include "dyn32_defs.h" +# else +extern void l_none PARAMS((void)); +# endif +#else +extern void l_none PARAMS((void)); +#endif + + +struct or32_letter { + char letter; + int sign; + /* int reloc; relocation per letter ??*/ +}; + +enum insn_type { + it_unknown, + it_exception, + it_arith, + it_shift, + it_compare, + it_branch, + it_jump, + it_load, + it_store, + it_movimm, + it_move, + it_extend, + it_nop, + it_mac, + it_float }; + +/* Main instruction specification array. */ +struct or32_opcode { + /* Name of the instruction. */ + char *name; + + /* A string of characters which describe the operands. + Valid characters are: + ,() Itself. Characters appears in the assembly code. + rA Register operand. + rB Register operand. + rD Register operand (destination). + I An immediate operand, range -32768 to 32767. + J An immediate operand, range . (unused) + K An immediate operand, range 0 to 65535. + L An immediate operand, range 0 to 63. + M An immediate operand, range . (unused) + N An immediate operand, range -33554432 to 33554431. + O An immediate operand, range . (unused) */ + char *args; + + /* Opcode and operand encoding. */ + char *encoding; + +#ifdef HAS_EXECUTION +# if COMPLEX_EXECUTION + char *function_name; +# elif SIMPLE_EXECUTION + void (*exec)(struct iqueue_entry *); +# else /* DYNAMIC_EXECUTION */ + void (*exec)(struct op_queue *opq, int param_t[3], orreg_t param[3], int); +# endif +#else /* HAS_EXECUTION */ + void (*exec)(void); +#endif + + unsigned int flags; + enum insn_type func_unit; +}; + +/* This operand is the last in the list */ +#define OPTYPE_LAST (0x80000000) +/* This operand marks the end of the operand sequence (for things like I(rD)) */ +#define OPTYPE_OP (0x40000000) +/* The operand specifies a register index */ +#define OPTYPE_REG (0x20000000) +/* The operand must be sign extended */ +#define OPTYPE_SIG (0x10000000) +/* Operand is a relative address, the `I' in `I(rD)' */ +#define OPTYPE_DIS (0x08000000) +/* The operand is a destination */ +#define OPTYPE_DST (0x04000000) +/* Which bit of the operand is the sign bit */ +#define OPTYPE_SBIT (0x00001F00) +/* Amount to shift the instruction word right to get the operand */ +#define OPTYPE_SHR (0x0000001F) +#define OPTYPE_SBIT_SHR (8) + +/* MM: Data how to decode operands. */ +extern struct insn_op_struct { + unsigned long type; + unsigned long data; +} **op_start; + +/* Leaf flag used in automata building */ +#define LEAF_FLAG (0x80000000) + +struct temp_insn_struct +{ + unsigned long insn; + unsigned long insn_mask; + int in_pass; +}; + +extern unsigned long *automata; +extern struct temp_insn_struct *ti; + +extern CONST struct or32_letter or32_letters[]; + +extern CONST struct or32_opcode or32_opcodes[]; + +extern CONST int num_opcodes; + +/* Calculates instruction length in bytes. Always 4 for OR32. */ +extern int insn_len PARAMS((int insn_index)); + +/* Is individual insn's operand signed or unsigned? */ +extern int letter_signed PARAMS((char l)); + +/* Number of letters in the individual lettered operand. */ +extern int letter_range PARAMS((char l)); + +/* MM: Returns index of given instruction name. */ +extern int insn_index PARAMS((char *insn)); + +/* MM: Returns instruction name from index. */ +extern CONST char *insn_name PARAMS ((int index)); + +/* MM: Constructs new FSM, based on or32_opcodes. */ +extern void build_automata PARAMS ((void)); + +/* MM: Destructs FSM. */ +extern void destruct_automata PARAMS ((void)); + +/* MM: Decodes instruction using FSM. Call build_automata first. */ +extern int insn_decode PARAMS((unsigned int insn)); + +/* Disassemble one instruction from insn to disassemble. + Return the size of the instruction. */ +int disassemble_insn (unsigned long insn); + +/* Disassemble one instruction from insn index. + Return the size of the instruction. */ +int disassemble_index (unsigned long insn, int index); + +/* FOR INTERNAL USE ONLY */ +/* Automatically does zero- or sign- extension and also finds correct + sign bit position if sign extension is correct extension. Which extension + is proper is figured out from letter description. */ +unsigned long extend_imm(unsigned long imm, char l); + +/* Extracts value from opcode */ +unsigned long or32_extract(char param_ch, char *enc_initial, unsigned long insn); + +#endif + Index: or1k/except.h =================================================================== --- or1k/except.h (nonexistent) +++ or1k/except.h (revision 1765) @@ -0,0 +1,52 @@ +/* except.h -- OR1K architecture specific exceptions + Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +#ifndef _EXCEPT_H_ +#define _EXCEPT_H_ + +/* Define if you want pure virtual machine simulation (no exceptions etc.) */ +#define ONLY_VIRTUAL_MACHINE 0 + +/* Definition of OR1K exceptions */ + +#define EXCEPT_RESET 0x0100 +#define EXCEPT_BUSERR 0x0200 +#define EXCEPT_DPF 0x0300 +#define EXCEPT_IPF 0x0400 +#define EXCEPT_TICK 0x0500 +#define EXCEPT_ALIGN 0x0600 +#define EXCEPT_ILLEGAL 0x0700 +#define EXCEPT_INT 0x0800 +#define EXCEPT_DTLBMISS 0x0900 +#define EXCEPT_ITLBMISS 0x0a00 +#define EXCEPT_RANGE 0x0b00 +#define EXCEPT_SYSCALL 0x0c00 +#define EXCEPT_TRAP 0x0e00 + +/* Non maskable exceptions */ +#define IS_NME(E) ((E) == EXCEPT_RESET) + +/* Prototypes */ +void except_handle(oraddr_t except, oraddr_t ea); +const char *except_name(oraddr_t except); + +/* Has an exception been raised in this cycle ? */ +extern int except_pending; + +#endif Index: or1k/Makefile.in =================================================================== --- or1k/Makefile.in (nonexistent) +++ or1k/Makefile.in (revision 1765) @@ -0,0 +1,332 @@ +# Makefile.in generated by automake 1.6.3 from Makefile.am. +# @configure_input@ + +# Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 +# Free Software Foundation, Inc. +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + +# Makefile -- Makefile for OR1K architecture dependent simulation +# Copyright (C) 1999 Damjan Lampret, lampret@opencores.org +# +# This file is part of OpenRISC 1000 Architectural Simulator. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 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or16 Property changes : Added: svn:ignore ## -0,0 +1 ## +Makefile Index: Makefile.am =================================================================== --- Makefile.am (nonexistent) +++ Makefile.am (revision 1765) @@ -0,0 +1,5 @@ +# +# +# + +SUBDIRS = common or1k $(CPU_ARCH) Index: . =================================================================== --- . (nonexistent) +++ . (revision 1765)

. Property changes : Added: svn:ignore ## -0,0 +1,2 ## +Makefile +.deps