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- This comparison shows the changes necessary to convert path
/or1k/trunk/ecos-2.0/packages/devs/eth/powerpc/quicc2/v2_0
- from Rev 1254 to Rev 1765
- ↔ Reverse comparison
Rev 1254 → Rev 1765
/cdl/quicc2_eth_drivers.cdl
0,0 → 1,115
# ==================================================================== |
# |
# fec_eth_drivers.cdl |
# |
# Ethernet drivers - platform dependent support for PowerPC MPC8260 |
# |
# ==================================================================== |
#####ECOSGPLCOPYRIGHTBEGIN#### |
## ------------------------------------------- |
## This file is part of eCos, the Embedded Configurable Operating System. |
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
## Copyright (C) 2002 Gary Thomas |
## |
## eCos is free software; you can redistribute it and/or modify it under |
## the terms of the GNU General Public License as published by the Free |
## Software Foundation; either version 2 or (at your option) any later version. |
## |
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
## WARRANTY; without even the implied warranty of MERCHANTABILITY or |
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
## for more details. |
## |
## You should have received a copy of the GNU General Public License along |
## with eCos; if not, write to the Free Software Foundation, Inc., |
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
## |
## As a special exception, if other files instantiate templates or use macros |
## or inline functions from this file, or you compile this file and link it |
## with other works to produce a work based on this file, this file does not |
## by itself cause the resulting work to be covered by the GNU General Public |
## License. However the source code for this file must still be made available |
## in accordance with section (3) of the GNU General Public License. |
## |
## This exception does not invalidate any other reasons why a work based on |
## this file might be covered by the GNU General Public License. |
## |
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
## at http://sources.redhat.com/ecos/ecos-license/ |
## ------------------------------------------- |
#####ECOSGPLCOPYRIGHTEND#### |
# ==================================================================== |
######DESCRIPTIONBEGIN#### |
# |
# Author(s): mtek |
# Original data: gthomas |
# Contributors: |
# Date: 2002-02-20 |
# |
#####DESCRIPTIONEND#### |
# |
# ==================================================================== |
|
cdl_package CYGPKG_DEVS_ETH_POWERPC_QUICC2 { |
display "MPC8260 FEC ethernet driver" |
|
parent CYGPKG_IO_ETH_DRIVERS |
active_if CYGPKG_IO_ETH_DRIVERS |
active_if CYGPKG_HAL_POWERPC |
active_if CYGPKG_HAL_POWERPC_MPC8260 |
|
implements CYGHWR_NET_DRIVERS |
implements CYGHWR_NET_DRIVER_ETH0 |
include_dir . |
include_files ; # none _exported_ whatsoever |
|
description "Fast ethernet driver for PowerPC MPC8260 boards." |
compile -library=libextras.a if_fec.c EnetPHY.c |
|
cdl_option CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE { |
display "Buffer size" |
flavor data |
default_value 1540 |
description " |
This option specifies the size of the internal buffers used |
for the PowerPC FEC/ethernet device." |
} |
|
cdl_option CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM { |
display "Number of output buffers" |
flavor data |
legal_values 2 to 16 |
default_value 4 |
description " |
This option specifies the number of output buffer packets |
to be used for the PowerPC FEC/ethernet device." |
} |
|
cdl_option CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM { |
display "Number of input buffers" |
flavor data |
legal_values 2 to 16 |
default_value 4 |
description " |
This option specifies the number of input buffer packets |
to be used for the PowerPC FEC/ethernet device." |
} |
|
cdl_component CYGPKG_DEVS_ETH_POWERPC_QUICC2_OPTIONS { |
display "MPC8260 FEC ethernet driver build options" |
flavor none |
no_define |
|
cdl_option CYGPKG_DEVS_ETH_POWERPC_QUICC2_CFLAGS_ADD { |
display "Additional compiler flags" |
flavor data |
no_define |
default_value { "-D_KERNEL -D__ECOS" } |
description " |
This option modifies the set of compiler flags for |
building the MPC8260 FEC ethernet driver package. |
These flags are used in addition to the set of global |
flags." |
} |
} |
} |
/ChangeLog
0,0 → 1,49
2002-12-12 Gary Thomas <gthomas@ecoscentric.com> |
2002-12-12 Patrick Doyle <wpd@delcomsys.com> |
|
* src/types.h: |
* src/if_fec.c: |
* src/fec.h: |
* src/EnetPHY.h: |
* src/EnetPHY.c: |
* cdl/quicc2_eth_drivers.cdl: New package; ethernet drivers for |
PowerPC/QUICC2 based systems (like MPC8260). |
|
//=========================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// Copyright (C) 2002 Gary Thomas |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//=========================================================================== |
|
|
|
/src/EnetPHY.h
0,0 → 1,111
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// Copyright (C) 2002 Gary Thomas |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
/*------------------------------------------------------------------ |
* |
* FILE: EnetPHY.c |
* |
* DESCRIPTION: LXT970a driver header file |
* |
* |
* Modified for MPC8260 VADS board |
*-------------------------------------------------------------------*/ |
|
#ifndef _EnetPHY_H |
#define _EnetPHY_H |
|
#include "types.h" |
|
// Board control and status registers |
typedef struct bcsr { |
UINT32 bcsr0; |
UINT32 bcsr1; |
UINT32 bcsr2; |
UINT32 bcsr3; |
} t_BCSR; |
|
// Fast ethernet enable/reset pins on bcsr |
#define FETHIEN_ 0x08000000 |
#define FETHRST_ 0x04000000 |
|
|
/**************************/ |
/* The API for PHY Device */ |
/**************************/ |
|
void EnableResetPHY(volatile t_BCSR *pBCSR); |
UINT16 InitEthernetPHY(VUINT32* pdir, VUINT32* pdat, UINT16 link); |
UINT16 EthernetPHYInterruptHandler(void); |
void EnablePHYinterrupt(UINT8 enable); |
UINT16 LinkTestPHY(void); |
|
|
typedef enum MDIORW {READ, WRITE} MDIORW; |
|
|
#define LINKERROR 0xFFFF |
#define NOTLINKED 0x0000 |
#define TEN_HD 0x0020 |
#define TEN_FD 0x0040 |
#define HUNDRED_HD 0x0080 |
#define HUNDRED_FD 0x0100 |
|
#define MD_TEST_FRAME 0xDEAD |
|
//8260 VADS Pin Connections |
#define MDIO_PIN_MASK 0x00400000 //PC9 for 8260 VADS |
#define MDC_PIN_MASK 0x00200000 //PC10 for 8260 VADS |
|
//#define MDIO_PIN_MASK 0x00000200 //PC9 for 8260 VADS |
//#define MDC_PIN_MASK 0x00000400 //PC10 for 8260 VADS |
|
//IEEE 802.3 PHY Register Definitions |
#define CONTROL_REG 0 |
#define STATUS_REG 1 |
#define PHY_ID_REG_A 2 |
#define PHY_ID_REG_B 3 |
#define AUTONEG_AD_REG 4 |
#define AUTONEG_LINKPARTNER_REG 5 |
#define AUTONEG_EXP_REG 6 |
|
//LXT970a Specific Register Definitions |
#define MIRROR_REG 16 |
#define INT_EN_REG 17 |
#define INT_STAT_REG 18 |
#define CONFIG_REG 19 |
#define CHIP_STAT_REG 20 |
|
//Clock Timing Control |
#define MDC_HOLD_TIME 50 |
|
#endif |
/src/fec.h
0,0 → 1,173
//========================================================================== |
// |
// fec.h |
// |
// PowerPC MPC8260 fast ethernet (FEC) |
// |
//========================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// Copyright (C) 2002 Gary Thomas |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//========================================================================== |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): mtek |
// Contributors: pfine |
// Date: 2002-02-20 |
// Purpose: |
// Description: |
// |
// |
//####DESCRIPTIONEND#### |
// |
//========================================================================== |
|
// The port connected to the ethernet |
#define QUICC2_VADS_IMM_BASE 0x04700000 |
#define FCC2 1 |
|
/* ------------------------ */ |
/* FCC REGISTER CONSTANTS */ |
/* ------------------------ */ |
|
// GFMR masks (RESET: 0x00000000) |
#define FEC_GFMR_EN_Rx 0x00000020 // Receive enable |
#define FEC_GFMR_EN_Tx 0x00000010 // Transmit enable |
#define FEC_GFMR_INIT 0x0000000C // mode=ethernet |
#define FEC_GFMR_OFFSET 0x11320 |
|
//PSMR masks (RESET: 0x00000000) |
#define FEC_PSMR_INIT 0x00000080 // 32-bit CRC |
#define FEC_PSMR_OFFSET 0x11324 |
|
//TODR masks (RESET: 0x0000) |
#define FEC_TOD_INIT 0x0000 |
#define FEC_TOD_SET 0x8000 |
#define FEC_TOD_OFFSET 0x11328 |
|
//DSR masks (RESET: 0x7E7E) |
#define FEC_DSR_INIT 0xD555 |
#define FEC_DSR_OFFSET 0x1132C |
|
//FCCE & FCCM (RESET: 0x0000) |
#define FEC_EV_GRA 0x00800000 // Graceful stop |
#define FEC_EV_RXC 0x00400000 // A control frame has been received |
#define FEC_EV_TXC 0x00200000 // Out of sequence frame sent |
#define FEC_EV_TXE 0x00100000 // Error in transmission channel |
#define FEC_EV_RXF 0x00080000 // A complete frame received |
#define FEC_EV_BSY 0x00040000 // A received frame discarded due to lack |
// of buffers |
#define FEC_EV_TXB 0x00020000 // A buffer sent to ethernet |
#define FEC_EV_RXB 0x00010000 // A buffer that is a non-complete frame |
// is received |
#define FEC_FCCE_OFFSET 0x11330 |
#define FEC_FCCM_OFFSET 0x11334 |
|
/* ------------------------------ */ |
/* FCC PARAMETER RAM CONSTANTS */ |
/* ------------------------------ */ |
|
#define FEC_PRAM_RIPTR 0x3000 // 32 byte buffer in dual port RAM |
#define FEC_PRAM_TIPTR 0xB000 // 32 byte buffer in dual port RAM |
#define FEC_FCR_INIT 0x00000000 // Clear the reserved bits |
#define FEC_FCR_MOT_BO 0x10000000 // Motorola byte ordering |
#define FEC_PRAM_C_MASK 0xDEBB20E3 // Constant MASK for CRC |
#define FEC_PRAM_C_PRES 0xFFFFFFFF // CRC Preset |
#define FEC_PRAM_RETLIM 15 // Retry limit |
#define FEC_PRAM_PER_LO 5 // Persistance |
#define FEC_PRAM_PER_HI 0 |
#define FEC_PRAM_MRBLR 1536 |
#define FEC_MAX_FLR 1518 // Max frame length |
#define FEC_MIN_FLR 64 // Min frame length |
#define FEC_PRAM_PAD_CH 0x8888 |
#define FEC_PRAM_MAXD 1520 |
#define FEC_PRAM_OFFSET 0x8500 // Offset of t_Fcc_Pram in 82xx |
|
/* ------------------------------ */ |
/* BUFFER DESCRIPTOR CONSTANTS */ |
/* ------------------------------ */ |
#define FEC_PRAM_RxBD_Base (FEC_PRAM_RIPTR + 0x400) |
#define FEC_BD_Rx_Empty 0x8000 // Buffer is empty, FEC can fill |
#define FEC_BD_Rx_Wrap 0x2000 // Wrap: Last buffer in ring |
#define FEC_BD_Rx_Int 0x1000 // Interrupt |
#define FEC_BD_Rx_Last 0x0800 // Last buffer in frame |
#define FEC_BD_Rx_Miss 0x0100 // Miss: promiscious mode |
#define FEC_BD_Rx_BC 0x0080 // Broadcast address |
#define FEC_BD_Rx_MC 0x0040 // Multicast address |
#define FEC_BD_Rx_LG 0x0020 // Frame length violation |
#define FEC_BD_Rx_NO 0x0010 // Non-octet aligned frame |
#define FEC_BD_Rx_SH 0x0008 // Short frame |
#define FEC_BD_Rx_CR 0x0004 // CRC error |
#define FEC_BD_Rx_OV 0x0002 // Overrun |
#define FEC_BD_Rx_TR 0x0001 // Frame truncated. late collision |
|
#define FEC_PRAM_TxBD_Base (FEC_PRAM_TIPTR + 0x400) |
#define FEC_BD_Tx_Ready 0x8000 // Frame ready |
#define FEC_BD_Tx_Pad 0x4000 // Pad short frames |
#define FEC_BD_Tx_Wrap 0x2000 // Wrap: Last buffer in ring |
#define FEC_BD_Tx_Int 0x1000 // Interrupt |
#define FEC_BD_Tx_Last 0x0800 // Last buffer in frame |
#define FEC_BD_Tx_TC 0x0400 // Send CRC after data |
#define FEC_BD_Tx_DEF 0x0200 // Defer indication |
#define FEC_BD_Tx_HB 0x0100 // Heartbeat |
#define FEC_BD_Tx_LC 0x0080 // Late collision |
#define FEC_BD_Tx_RL 0x0040 // Retransmission limit |
#define FEC_BD_Tx_RC 0x003C // Retry count |
#define FEC_BD_Tx_UN 0x0002 // Underrun |
#define FEC_BD_Tx_CSL 0x0001 // Carrier sense lost |
|
|
// Buffer descriptor |
struct fec_bd { |
volatile unsigned short ctrl; |
volatile unsigned short length; |
volatile unsigned char *buffer; |
}; |
|
|
struct fec_eth_info { |
volatile struct fcc_regs *fcc_reg; // See "mpc8260.h" |
struct fec_bd *txbd, *rxbd; // Next Tx,Rx descriptor to use |
struct fec_bd *tbase, *rbase; // First Tx,Rx descriptor |
struct fec_bd *tnext, *rnext; // Next descriptor to check for interrupt |
int txsize, rxsize; // Length of individual buffers |
unsigned long txkey[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM]; |
}; |
|
// CPM_CPCR masks |
#define CPCR_FLG 0x00010000 |
#define CPCR_FCC2_CH 0x16200000 |
#define CPCR_GRSTOP_TX 0x00000005 |
#define CPCR_INIT_TX_RX_PARAMS 0x00000000 |
#define CPCR_MCN_FEC 0x00000300 |
#define CPCR_READY_TO_RX_CMD 0 /* Ready to receive a command */ |
/src/types.h
0,0 → 1,100
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// Copyright (C) 2002 Gary Thomas |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
/********************************************************************** |
* Copyright (c) 1999 Delphi Communication Systems |
* Maynard, MA. ALL RIGHTS RESERVED |
***********************************************************************/ |
/********************************************************************** |
* File: |
* $RCSfile: types.h,v $ |
* $Revision: 1.1.1.1 $ |
* $Date: 2004-02-14 13:33:31 $ |
* |
* Purpose: |
* This file defines basic types used in the ITU-T G.729A Speech |
* codec. These are defined here so that we may control |
* how many bits of precision a type has on a particular |
* platform. |
* |
* Operation: |
* We define the following in this file: |
* |
* typedef ... INT16 |
* This type definition defines the data type used for |
* variables that must hold exactly 16 bits (signed). |
* |
* typedef ... INT32 |
* This type definition defines the data type used for |
* variables that must hold exactly 32 bits (signed). |
* |
* Notes/Issues: |
* This file is correct for the following platforms (so far): |
* |
* GNUWIN32 compiled with GCC |
* |
* $Log: not supported by cvs2svn $ |
* Revision 1.1.1.2 2002/03/14 17:54:24 pfine |
* Fixed CR/LF Problem |
* |
* Revision 1.1.1.1 2002/03/13 18:20:24 pfine |
* DCS Ecos with Device Drivers |
* |
* |
***********************************************************************/ |
#ifndef TYPES_H |
#define TYPES_H |
|
typedef char INT8; |
typedef unsigned char UINT8; |
typedef short INT16; |
typedef unsigned short UINT16; |
typedef long INT32; |
typedef unsigned long UINT32; |
|
typedef volatile char VINT8; |
typedef volatile unsigned char VUINT8; |
typedef volatile short VINT16; |
typedef volatile unsigned short VUINT16; |
typedef volatile long VINT32; |
typedef volatile unsigned long VUINT32; |
|
typedef char OCTET; |
typedef int INT_NATIVE; |
typedef unsigned int UINT_NATIVE; |
|
#endif /* TYPES_H */ |
|
|
|
|
/src/if_fec.c
0,0 → 1,721
//========================================================================== |
// |
// dev/if_fec.c |
// |
// Fast ethernet device driver for PowerPC MPC8260 boards |
// |
//========================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// Copyright (C) 2002 Gary Thomas |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//========================================================================== |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): mtek |
// Contributors: pfine |
// Date: 2002-02-20 |
// Purpose: |
// Description: hardware driver for MPC8260 FEC |
// |
// |
//####DESCRIPTIONEND#### |
// |
//========================================================================== |
|
#include <pkgconf/devs_eth_powerpc_quicc2.h> |
#include <cyg/infra/cyg_type.h> |
#include <cyg/infra/diag.h> |
|
#include <cyg/hal/hal_arch.h> |
#include <cyg/hal/hal_cache.h> |
#include <cyg/hal/hal_intr.h> |
#include <cyg/hal/var_intr.h> |
#include <cyg/hal/drv_api.h> |
#include <cyg/hal/hal_if.h> |
#include <cyg/hal/mpc8260.h> |
|
#include <cyg/io/eth/netdev.h> |
#include <cyg/io/eth/eth_drv.h> |
|
#ifdef CYGPKG_NET |
#include <pkgconf/net.h> |
#endif |
|
#include "fec.h" |
#include "EnetPHY.h" |
|
#define ALIGN_TO_CACHE_LINES(x) ( (long)((x) + 31) & 0xffffffe0 ) |
|
static unsigned char fec_eth_rxbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM * |
(CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE + 32)]; |
static unsigned char fec_eth_txbufs[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM * |
(CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE + 32)]; |
|
// Buffer descriptors are in dual ported RAM, which is marked non-cached |
#define FEC_BDs_NONCACHED |
static struct fec_bd *const fec_eth_rxring = (struct fec_bd *) |
(QUICC2_VADS_IMM_BASE + FEC_PRAM_RxBD_Base); |
static struct fec_bd *const fec_eth_txring = (struct fec_bd *) |
(QUICC2_VADS_IMM_BASE + FEC_PRAM_TxBD_Base); |
|
static struct fec_eth_info fec_eth0_info; |
|
static unsigned short _default_enaddr[] = {0x1234, 0x5678, 0x90a1}; |
static unsigned char enaddr[6]; |
|
#ifdef CYGPKG_REDBOOT |
#include <pkgconf/redboot.h> |
#ifdef CYGSEM_REDBOOT_FLASH_CONFIG |
#include <redboot.h> |
#include <flash_config.h> |
RedBoot_config_option("Network hardware address [MAC]", |
fec_esa, |
ALWAYS_ENABLED, true, |
CONFIG_ESA, 0 |
); |
RedBoot_config_option("Attempt to find 100 Mbps Ethernet", |
fec_100, |
ALWAYS_ENABLED, true, |
CONFIG_BOOL, 0 |
); |
#endif |
#endif |
|
#define os_printf diag_printf |
|
// CONFIG_ESA and CONFIG_BOOL are defined in redboot/include/flash_config.h |
#ifndef CONFIG_ESA |
#define CONFIG_ESA 6 // ethernet address length ... |
#endif |
|
#ifndef CONFIG_BOOL |
#define CONFIG_BOOL 1 |
#endif |
|
ETH_DRV_SC(fec_eth0_sc, |
&fec_eth0_info, // Driver specific data |
"eth0", // Name for this interface |
fec_eth_start, |
fec_eth_stop, |
fec_eth_control, |
fec_eth_can_send, |
fec_eth_send, |
fec_eth_recv, |
fec_eth_deliver, |
fec_eth_int, |
fec_eth_int_vector); |
|
NETDEVTAB_ENTRY(fec_netdev, |
"fec_eth", |
fec_eth_init, |
&fec_eth0_sc); |
|
#ifdef CYGPKG_NET |
static cyg_interrupt fec_eth_interrupt; |
static cyg_handle_t fec_eth_interrupt_handle; |
#endif |
static void fec_eth_int(struct eth_drv_sc *data); |
|
#define FEC_ETH_INT CYGNUM_HAL_INTERRUPT_FCC2 |
|
// This ISR is called when the ethernet interrupt occurs |
#ifdef CYGPKG_NET |
static int |
fec_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) |
{ |
cyg_drv_interrupt_mask(FEC_ETH_INT); |
return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR |
} |
#endif |
|
// Deliver function (ex-DSR) handles the ethernet [logical] processing |
static void |
fec_eth_deliver(struct eth_drv_sc * sc) |
{ |
fec_eth_int(sc); |
#ifdef CYGPKG_NET |
// Clearing the event register acknowledges FCC2 interrupt ... |
// cyg_drv_interrupt_acknowledge(FEC_ETH_INT); |
cyg_drv_interrupt_unmask(FEC_ETH_INT); |
#endif |
|
} |
|
|
// Initialize the interface - performed at system startup |
// This function must set up the interface, including arranging to |
// handle interrupts, etc, so that it may be "started" cheaply later. |
static bool |
fec_eth_init(struct cyg_netdevtab_entry *tab) |
{ |
struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance; |
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; |
|
volatile t_PQ2IMM *IMM = (volatile t_PQ2IMM *) QUICC2_VADS_IMM_BASE; |
volatile t_Fcc_Pram *fcc = (volatile t_Fcc_Pram *) (QUICC2_VADS_IMM_BASE + FEC_PRAM_OFFSET); |
volatile t_EnetFcc_Pram *E_fcc = &(fcc->SpecificProtocol.e); |
#ifdef CYGPKG_HAL_POWERPC_VADS |
volatile t_BCSR *CSR = (t_BCSR *) 0x04500000; |
#endif |
|
int cache_state; |
int i; |
bool esa_ok; |
bool fec_100; |
unsigned char *c_ptr; |
UINT16 link_speed; |
|
// Ensure consistent state between cache and what the FEC sees |
HAL_DCACHE_IS_ENABLED(cache_state); |
if (cache_state) { |
HAL_DCACHE_DISABLE(); |
HAL_DCACHE_INVALIDATE_ALL(); |
} |
|
// Link the memory to the driver control memory |
qi->fcc_reg = & (IMM->fcc_regs[FCC2]); |
|
// just in case : disable Transmit and Receive |
qi->fcc_reg->fcc_gfmr &= ~(FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx); |
|
// Via BCSR, (re)start LXT970 |
#ifdef CYGPKG_HAL_POWERPC_VADS |
EnableResetPHY(CSR); |
#endif |
|
// Try to read the ethernet address of the transciever ... |
#ifdef CYGPKG_REDBOOT |
esa_ok = flash_get_config("fec_100", &fec_100, CONFIG_BOOL); |
#else |
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET, |
"fec_100", &fec_100, CONFIG_BOOL); |
#endif |
|
link_speed = NOTLINKED; |
if(esa_ok && fec_100){ |
// Via MII Management pins, tell LXT970 to initialize |
os_printf("Attempting to acquire 100 Mbps half_duplex link ..."); |
InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir), |
(VUINT32 *) &(IMM->io_regs[PORT_C].pdat), |
HUNDRED_HD); |
|
link_speed = LinkTestPHY(); |
os_printf("\n"); |
if(link_speed == NOTLINKED){ |
os_printf("Failed to get 100 Mbps half_duplex link.\n"); |
} |
} |
if(link_speed == NOTLINKED){ |
os_printf("Attempting to acquire 10 Mbps half_duplex link ..."); |
InitEthernetPHY((VUINT32 *) &(IMM->io_regs[PORT_C].pdir), |
(VUINT32 *) &(IMM->io_regs[PORT_C].pdat), |
TEN_HD); |
link_speed = LinkTestPHY(); |
os_printf("\n"); |
if(link_speed == NOTLINKED){ |
link_speed = LinkTestPHY(); |
os_printf("Failed to get 10 Mbps half_duplex link.\n"); |
} |
|
} |
switch ( link_speed ) { |
|
case HUNDRED_FD: |
os_printf("100 MB full-duplex ethernet link \n"); |
break; |
case HUNDRED_HD: |
os_printf("100 MB half-duplex ethernet link \n"); |
break; |
case TEN_FD: |
os_printf("10 MB full-duplex ethernet link \n"); |
break; |
case TEN_HD: |
os_printf("10 MB half-duplex ethernet link \n"); |
break; |
default: |
os_printf("NO ethernet link \n"); |
} |
|
// Connect PORTC pins: (C19) to clk13, (C18) to clk 14 |
IMM->io_regs[PORT_C].ppar |= 0x00003000; |
IMM->io_regs[PORT_C].podr &= ~(0x00003000); |
IMM->io_regs[PORT_C].psor &= ~(0x00003000); |
IMM->io_regs[PORT_C].pdir &= ~(0x00003000); |
|
// Connect clk13 to RxClk and clk14 to TxClk on FCC2 |
IMM->cpm_mux_cmxfcr &= 0x7f007f00; // clear fcc2 clocks |
IMM->cpm_mux_cmxfcr |= 0x00250000; // set fcc2 clocks (see 15-14) |
IMM->cpm_mux_cmxuar = 0x0000; // Utopia address reg, just clear |
|
// Initialize parallel port registers to connect FCC2 to MII |
IMM->io_regs[PORT_B].podr &= 0xffffc000; // clear bits 18-31 |
IMM->io_regs[PORT_B].psor &= 0xffffc000; |
IMM->io_regs[PORT_B].pdir &= 0xffffc000; |
|
IMM->io_regs[PORT_B].psor |= 0x00000004; |
IMM->io_regs[PORT_B].pdir |= 0x000003c5; |
IMM->io_regs[PORT_B].ppar |= 0x00003fff; |
|
// Initialize Receive Buffer Descriptors |
qi->rbase = fec_eth_rxring; |
qi->rxbd = fec_eth_rxring; |
qi->rnext = fec_eth_rxring; |
c_ptr = fec_eth_rxbufs; |
|
for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM; i++) { |
|
fec_eth_rxring[i].ctrl = (FEC_BD_Rx_Empty | FEC_BD_Rx_Int); |
fec_eth_rxring[i].length = 0; // reset |
c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr); |
fec_eth_rxring[i].buffer = (volatile unsigned char *)c_ptr; |
c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE; |
} |
|
fec_eth_rxring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM-1].ctrl |= FEC_BD_Rx_Wrap; |
|
// Initialize Transmit Buffer Descriptors |
qi->tbase = fec_eth_txring; |
qi->txbd = fec_eth_txring; |
qi->tnext = fec_eth_txring; |
c_ptr = fec_eth_txbufs; |
|
for(i=0; i<CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM; i++) { |
|
fec_eth_txring[i].ctrl = (FEC_BD_Tx_Pad | FEC_BD_Tx_Int); |
fec_eth_txring[i].length = 0; // reset : Write before send |
c_ptr = (unsigned char *) ALIGN_TO_CACHE_LINES(c_ptr); |
fec_eth_txring[i].buffer = (volatile unsigned char *)c_ptr; |
c_ptr += CYGNUM_DEVS_ETH_POWERPC_QUICC2_BUFSIZE; |
} |
|
fec_eth_txring[CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM-1].ctrl |= FEC_BD_Tx_Wrap; |
|
// Common FCC Parameter RAM initialization |
fcc->riptr = FEC_PRAM_RIPTR; // in dual port RAM (see 28-11) |
fcc->tiptr = FEC_PRAM_TIPTR; // in dual port RAM (see 28-11) |
fcc->mrblr = FEC_PRAM_MRBLR; // ?? FROM 8101 code ... |
fcc->rstate &= FEC_FCR_INIT; |
fcc->rstate |= FEC_FCR_MOT_BO; |
fcc->rbase = (long) fec_eth_rxring; |
fcc->tstate &= FEC_FCR_INIT; |
fcc->tstate |= FEC_FCR_MOT_BO; |
fcc->tbase = (long) fec_eth_txring; |
|
// Ethernet Specific FCC Parameter RAM Initialization |
E_fcc->c_mask = FEC_PRAM_C_MASK; // (see 30-9) |
E_fcc->c_pres = FEC_PRAM_C_PRES; |
E_fcc->crcec = 0; |
E_fcc->alec = 0; |
E_fcc->disfc = 0; |
E_fcc->ret_lim = FEC_PRAM_RETLIM; |
E_fcc->p_per = FEC_PRAM_PER_LO; |
E_fcc->gaddr_h = 0; |
E_fcc->gaddr_l = 0; |
E_fcc->tfcstat = 0; |
E_fcc->mflr = FEC_MAX_FLR; |
|
// Try to read the ethernet address of the transciever ... |
#ifdef CYGPKG_REDBOOT |
esa_ok = flash_get_config("fec_esa", enaddr, CONFIG_ESA); |
#else |
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET, |
"fec_esa", enaddr, CONFIG_ESA); |
#endif |
if (!esa_ok) { |
// If can't use the default ... |
os_printf("FEC_ETH - Warning! ESA unknown\n"); |
memcpy(enaddr, _default_enaddr, sizeof(enaddr)); |
} |
|
E_fcc->paddr1_h = ((short)enaddr[5] << 8) | enaddr[4]; // enaddr[2]; |
E_fcc->paddr1_m = ((short)enaddr[3] << 8) | enaddr[2]; // enaddr[1]; |
E_fcc->paddr1_l = ((short)enaddr[1] << 8) | enaddr[0]; // enaddr[0]; |
|
E_fcc->iaddr_h = 0; |
E_fcc->iaddr_l = 0; |
E_fcc->minflr = FEC_MIN_FLR; |
E_fcc->taddr_h = 0; |
E_fcc->taddr_m = 0; |
E_fcc->taddr_l = 0; |
E_fcc->pad_ptr = FEC_PRAM_TIPTR; // No special padding char ... |
E_fcc->cf_type = 0; |
E_fcc->maxd1 = FEC_PRAM_MAXD; |
E_fcc->maxd2 = FEC_PRAM_MAXD; |
|
// FCC register initialization |
IMM->fcc_regs[FCC2].fcc_gfmr = FEC_GFMR_INIT; |
IMM->fcc_regs[FCC2].fcc_psmr = FEC_PSMR_INIT; |
IMM->fcc_regs[FCC2].fcc_dsr = FEC_DSR_INIT; |
|
#ifdef CYGPKG_NET |
// clear the events of FCC2 |
IMM->fcc_regs[FCC2].fcc_fcce = 0xFFFF0000; |
IMM->fcc_regs[FCC2].fcc_fccm = FEC_EV_TXE | FEC_EV_TXB | FEC_EV_RXF; |
|
// Set up to handle interrupts |
cyg_drv_interrupt_create(FEC_ETH_INT, |
0, // Highest //CYGARC_SIU_PRIORITY_HIGH, |
(cyg_addrword_t)sc, // Data passed to ISR |
(cyg_ISR_t *)fec_eth_isr, |
(cyg_DSR_t *)eth_drv_dsr, |
&fec_eth_interrupt_handle, |
&fec_eth_interrupt); |
cyg_drv_interrupt_attach(fec_eth_interrupt_handle); |
cyg_drv_interrupt_acknowledge(FEC_ETH_INT); |
cyg_drv_interrupt_unmask(FEC_ETH_INT); |
#else |
|
// Mask the interrupts |
IMM->fcc_regs[FCC2].fcc_fccm = 0; |
#endif |
|
// Issue Init RX & TX Parameters Command for FCC2 |
while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD); |
|
IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS | |
CPCR_FCC2_CH | |
CPCR_MCN_FEC | |
CPCR_FLG; /* ISSUE COMMAND */ |
|
while ((IMM->cpm_cpcr & CPCR_FLG) != CPCR_READY_TO_RX_CMD); |
|
if (cache_state) |
HAL_DCACHE_ENABLE(); |
|
// Initialize upper level driver for ecos |
(sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr); |
|
return true; |
} |
|
// |
// This function is called to "start up" the interface. It may be called |
// multiple times, even when the hardware is already running. It will be |
// called whenever something "hardware oriented" changes and should leave |
// the hardware ready to send/receive packets. |
// |
static void |
fec_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags) |
{ |
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; |
|
// Enable the device : |
// Set the ENT/ENR bits in the GFMR -- Enable Transmit/Receive |
qi->fcc_reg->fcc_gfmr |= (FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx); |
|
} |
|
// |
// This function is called to shut down the interface. |
// |
static void |
fec_eth_stop(struct eth_drv_sc *sc) |
{ |
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; |
|
// Disable the device : |
// Clear the ENT/ENR bits in the GFMR -- Disable Transmit/Receive |
qi->fcc_reg->fcc_gfmr &= ~(FEC_GFMR_EN_Rx | FEC_GFMR_EN_Tx); |
} |
|
|
// |
// This function is called for low level "control" operations |
// |
static int |
fec_eth_control(struct eth_drv_sc *sc, unsigned long key, |
void *data, int length) |
{ |
switch (key) { |
case ETH_DRV_SET_MAC_ADDRESS: |
return 0; |
break; |
default: |
return 1; |
break; |
} |
} |
|
|
// |
// This function is called to see if another packet can be sent. |
// It should return the number of packets which can be handled. |
// Zero should be returned if the interface is busy and can not send any more. |
// |
static int |
fec_eth_can_send(struct eth_drv_sc *sc) |
{ |
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; |
volatile struct fec_bd *txbd = qi->txbd; |
int cache_state; |
|
HAL_DCACHE_IS_ENABLED(cache_state); |
#ifndef FEC_BDs_NONCACHED |
if (cache_state) { |
HAL_DCACHE_INVALIDATE(fec_eth_txring, |
8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM); |
} |
#endif |
|
return ((txbd->ctrl & FEC_BD_Tx_Ready) == 0); |
} |
|
// |
// This routine is called to send data to the hardware. |
static void |
fec_eth_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len, |
int total_len, unsigned long key) |
{ |
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; |
struct fec_bd *txbd, *txfirst; |
volatile char *bp; |
int i, txindex, cache_state; |
|
HAL_DCACHE_IS_ENABLED(cache_state); |
#ifndef FEC_BDs_NONCACHED |
if (cache_state) { |
HAL_DCACHE_INVALIDATE(fec_eth_txring, |
8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM); |
} |
#endif |
|
// Find a free buffer |
txbd = txfirst = qi->txbd; |
while (txbd->ctrl & FEC_BD_Tx_Ready) { |
// This buffer is busy, move to next one |
if (txbd->ctrl & FEC_BD_Tx_Wrap) { |
txbd = qi->tbase; |
} else { |
txbd++; |
} |
if (txbd == txfirst) { |
#ifdef CYGPKG_NET |
panic ("No free xmit buffers"); |
#else |
os_printf("FEC Ethernet: No free xmit buffers\n"); |
#endif |
} |
} |
|
// Remember the next buffer to try |
if (txbd->ctrl & FEC_BD_Tx_Wrap) { |
qi->txbd = qi->tbase; |
} else { |
qi->txbd = txbd+1; |
} |
|
txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd); |
qi->txkey[txindex] = key; |
|
// Set up buffer |
txbd->length = total_len; |
bp = txbd->buffer; |
for (i = 0; i < sg_len; i++) { |
memcpy((void *)bp, (void *)sg_list[i].buf, sg_list[i].len); |
bp += sg_list[i].len; |
} |
|
// Make sure no stale data buffer ... |
if (cache_state) { |
HAL_DCACHE_FLUSH(txbd->buffer, txbd->length); |
} |
// Send it on it's way |
txbd->ctrl |= FEC_BD_Tx_Ready | FEC_BD_Tx_Last | FEC_BD_Tx_TC; |
#ifndef FEC_BDs_NONCACHED |
if (cache_state) { |
HAL_DCACHE_FLUSH(fec_eth_txring, |
8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM); |
} |
#endif |
|
} |
|
// |
// This function is called when a packet has been received. It's job is |
// to prepare to unload the packet from the hardware. Once the length of |
// the packet is known, the upper layer of the driver can be told. When |
// the upper layer is ready to unload the packet, the internal function |
// 'fec_eth_recv' will be called to actually fetch it from the hardware. |
// |
static void |
fec_eth_RxEvent(struct eth_drv_sc *sc) |
{ |
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; |
struct fec_bd *rxbd; |
int cache_state; |
|
HAL_DCACHE_IS_ENABLED(cache_state); |
#ifndef FEC_BDs_NONCACHED |
if (cache_state) { |
HAL_DCACHE_INVALIDATE(fec_eth_rxring, |
8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM); |
} |
#endif |
|
rxbd = qi->rnext; |
while ((rxbd->ctrl & FEC_BD_Rx_Empty) == 0) { |
qi->rxbd = rxbd; // Save for callback |
|
// This is the right way of doing it, but dcbi has a bug ... |
// if (cache_state) { |
// HAL_DCACHE_INVALIDATE(rxbd->buffer, rxbd->length); |
// } |
(sc->funs->eth_drv->recv)(sc, rxbd->length); |
if (cache_state) { |
HAL_DCACHE_FLUSH(rxbd->buffer, rxbd->length); |
} |
|
rxbd->ctrl |= FEC_BD_Rx_Empty; |
if (rxbd->ctrl & FEC_BD_Rx_Wrap) { |
rxbd = qi->rbase; |
} else { |
rxbd++; |
} |
} |
// Remember where we left off |
qi->rnext = (struct fec_bd *)rxbd; |
|
// Make sure no stale data |
#ifndef FEC_BDs_NONCACHED |
if (cache_state) { |
HAL_DCACHE_FLUSH(fec_eth_rxring, |
8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_RxNUM); |
} |
#endif |
|
} |
|
// |
// This function is called as a result of the "eth_drv_recv()" call above. |
// It's job is to actually fetch data for a packet from the hardware once |
// memory buffers have been allocated for the packet. Note that the buffers |
// may come in pieces, using a scatter-gather list. This allows for more |
// efficient processing in the upper layers of the stack. |
// |
static void |
fec_eth_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len) |
{ |
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; |
unsigned char *bp; |
int i; |
|
bp = (unsigned char *)qi->rxbd->buffer; |
|
for (i = 0; i < sg_len; i++) { |
if (sg_list[i].buf != 0) { |
memcpy((void *)sg_list[i].buf, bp, sg_list[i].len); |
bp += sg_list[i].len; |
} |
} |
|
} |
|
static void |
fec_eth_TxEvent(struct eth_drv_sc *sc, int stat) |
{ |
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; |
struct fec_bd *txbd; |
int txindex, cache_state; |
|
// Make sure no stale data |
HAL_DCACHE_IS_ENABLED(cache_state); |
#ifndef FEC_BDs_NONCACHED |
if (cache_state) { |
HAL_DCACHE_INVALIDATE(fec_eth_txring, |
8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM); |
} |
#endif |
|
txbd = qi->tnext; |
// Note: TC field is used to indicate the buffer has/had data in it |
while ( (txbd->ctrl & (FEC_BD_Tx_TC | FEC_BD_Tx_Ready)) == FEC_BD_Tx_TC ) { |
txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd); |
(sc->funs->eth_drv->tx_done)(sc, qi->txkey[txindex], 0); |
txbd->ctrl &= ~FEC_BD_Tx_TC; |
if (txbd->ctrl & FEC_BD_Tx_Wrap) { |
txbd = qi->tbase; |
} else { |
txbd++; |
} |
} |
// Remember where we left off |
qi->tnext = (struct fec_bd *)txbd; |
|
// Make sure no stale data |
#ifndef FEC_BDs_NONCACHED |
if (cache_state) { |
HAL_DCACHE_FLUSH(fec_eth_txring, |
8*CYGNUM_DEVS_ETH_POWERPC_QUICC2_TxNUM); |
} |
#endif |
|
} |
|
// |
// Interrupt processing |
// |
static void |
fec_eth_int(struct eth_drv_sc *sc) |
{ |
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private; |
unsigned long iEvent; |
|
while ((iEvent = qi->fcc_reg->fcc_fcce) != 0){ |
|
// Writing 1's clear fcce, Writing 0's have no effect |
qi->fcc_reg->fcc_fcce = iEvent; |
|
// Tx Done or Tx Error |
if ( iEvent & (FEC_EV_TXB | FEC_EV_TXE) ) { |
fec_eth_TxEvent(sc, iEvent); |
} |
|
// Complete or non-complete frame receive |
if (iEvent & (FEC_EV_RXF | FEC_EV_RXB) ) { |
fec_eth_RxEvent(sc); |
} |
|
} |
|
|
} |
|
// |
// Interrupt vector |
// |
static int |
fec_eth_int_vector(struct eth_drv_sc *sc) |
{ |
return (FEC_ETH_INT); |
} |
|
/src/EnetPHY.c
0,0 → 1,362
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// Copyright (C) 2002 Gary Thomas |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
/*------------------------------------------------------------------- |
* |
* FILE: enetPHY.c |
* |
* DESCRIPTION: GPIO Management Pins driver for the LXT970a |
* |
* |
* Modified for the mpc8260 VADS board |
*--------------------------------------------------------------------*/ |
#include "types.h" |
#include "EnetPHY.h" |
|
/* Internal functions */ |
void MdioSend(UINT32, UINT16); |
UINT16 MdioReceive(UINT16); |
UINT16 MdioFrame(MDIORW, UINT16, UINT16, UINT32); |
|
VUINT32 * pPortDir; |
VUINT32 * pPortData; |
|
/*------------------------------------------------------------------- |
* |
* FUNCTION NAME: |
* |
* DESCRIPTION: |
* |
* EXTERNAL EFFECT: Turns on the LXT970 transciever |
* |
* PARAMETERS: |
* |
* RETURNS: None |
* |
* ASSUMPTIONS: |
* |
*-------------------------------------------------------------------*/ |
void |
EnableResetPHY(volatile t_BCSR *pBCSR) |
{ |
// active low FETHIEN on BSCR1, assert reset low |
pBCSR->bcsr1 &= ~(FETHIEN_ | FETHRST_); |
// de-assert reset |
pBCSR->bcsr1 |= FETHRST_; |
|
} |
|
|
/*------------------------------------------------------------------- |
* |
* FUNCTION NAME: |
* |
* DESCRIPTION: Writes parameters to the control registers of LXT970 |
* |
* EXTERNAL EFFECT: |
* |
* PARAMETERS: |
* |
* RETURNS: None |
* |
* ASSUMPTIONS: |
* |
*-------------------------------------------------------------------*/ |
UINT16 |
InitEthernetPHY(VUINT32* pdir, VUINT32* pdat, UINT16 link) |
{ |
|
VUINT16 FrameValue; |
|
/* 8101 Ethernet Management Pin Assignments */ |
pPortDir = pdir; |
pPortData = pdat; |
|
(*pPortDir) |= MDC_PIN_MASK; /* MD_Clock will always be output only */ |
|
/* Test MDC & MDIO Pin Connection to PHY */ |
MdioFrame(WRITE, 0, MIRROR_REG, MD_TEST_FRAME); //send test frame |
MdioFrame(WRITE, 0, MIRROR_REG, MD_TEST_FRAME); //send test frame |
FrameValue = MdioFrame(READ, 0, MIRROR_REG, 0); //read test frame |
|
if (FrameValue != MD_TEST_FRAME) |
return LINKERROR; //test data integrity |
|
/* General Configuration */ |
MdioFrame(WRITE, 0, CONFIG_REG, 0x0000); |
|
if(link == HUNDRED_HD) |
MdioFrame(WRITE, 0, AUTONEG_AD_REG, 0x0081); //100 Mbps Half, 802.3 |
else |
MdioFrame(WRITE, 0, AUTONEG_AD_REG, 0x0021); //10 Mbps Half, 802.3 |
|
// 100 Mbps full duplex not supported |
// MdioFrame(WRITE, 0, AUTONEG_AD_REG, 0x0101); //100 Mbps Full, 802.3 |
|
MdioFrame(WRITE, 0, CONTROL_REG, 0x1300); |
|
return 0; |
} |
|
/*------------------------------------------------------------------- |
* |
* FUNCTION NAME: |
* |
* DESCRIPTION: |
* |
* EXTERNAL EFFECT: |
* |
* PARAMETERS: |
* |
* RETURNS: None |
* |
* ASSUMPTIONS: |
* |
*-------------------------------------------------------------------*/ |
UINT16 |
EthernetPHYInterruptHandler() |
{ |
// Reading registers 1 and 18 in sequence |
// clears the transceiver interrupt |
|
MdioFrame(READ, 0, STATUS_REG, 0); |
MdioFrame(READ, 0, INT_STAT_REG, 0); |
|
return LinkTestPHY(); |
} /* end EthernetPHYInterruptHandler */ |
|
/*------------------------------------------------------------------- |
* |
* FUNCTION NAME: |
* |
* DESCRIPTION: |
* |
* EXTERNAL EFFECT: |
* |
* PARAMETERS: |
* |
* RETURNS: None |
* |
* ASSUMPTIONS: |
* |
*-------------------------------------------------------------------*/ |
UINT16 |
LinkTestPHY() |
{ |
UINT32 j, cnt; |
UINT16 FrameValue; |
|
//for (j = 0; j < 10; j++) { |
for (j = 0; j < 5; j++) { |
|
for (cnt = 0; cnt < 1000000; cnt ++) { |
|
asm("nop"); |
asm("nop"); |
asm("nop"); |
} |
|
FrameValue = MdioFrame(READ,0,CHIP_STAT_REG,0); |
|
if ( (FrameValue & 0x0200) != 0 ) |
break; |
} |
|
FrameValue &= 0x3800; |
|
switch (FrameValue) { |
|
case 0x3800: return HUNDRED_FD; |
case 0x2800: return HUNDRED_HD; |
case 0x3000: return TEN_FD; |
case 0x2000: return TEN_HD; |
default: return NOTLINKED; |
} |
|
} |
|
/*------------------------------------------------------------------- |
* |
* FUNCTION NAME: |
* |
* DESCRIPTION: |
* |
* EXTERNAL EFFECT: |
* |
* PARAMETERS: |
* |
* RETURNS: None |
* |
* ASSUMPTIONS: |
* |
*-------------------------------------------------------------------*/ |
void EnablePHYinterrupt(UINT8 enable) |
{ |
MdioFrame(WRITE, 0, INT_EN_REG, enable?0x2:0x0); |
} |
|
/*---------------------------------------------------------------------- |
* |
* FUNCTION NAME: |
* |
* DESCRIPTION: generic READ/WRITE function of LXT970 |
* through the MDC/MDIO interface. |
* |
* EXTERNAL EFFECT: |
* |
* PARAMETERS: |
* |
* RETURNS: None |
* |
* ASSUMPTIONS: |
* |
*---------------------------------------------------------------------*/ |
UINT16 |
MdioFrame(MDIORW R_W, UINT16 PhyAddr, UINT16 RegAddr, UINT32 PutData) { |
|
UINT16 GetData; |
|
*pPortDir |= MDIO_PIN_MASK; //set to output mode |
|
MdioSend(0xFFFFFFFF,32); //PreAmble |
MdioSend(0x1,2); //Start Frame Delimiter |
if (R_W==READ) |
MdioSend(0x2,2); //Read OpCode |
else |
MdioSend(0x1,2); //Write OpCode |
|
MdioSend(PhyAddr,5); //Send PHY transciever Address |
MdioSend(RegAddr,5); //Send Register Address |
|
if (R_W==READ) { |
*pPortDir &= ~MDIO_PIN_MASK; //set to input mode |
GetData = MdioReceive(17); //Drive TurnAround and Data |
MdioReceive(2); |
} |
else { |
MdioSend(0x2,2); //Drive TurnAround |
MdioSend(PutData, 16); //Send Data |
GetData = 0; |
*pPortDir &= ~MDIO_PIN_MASK; //set to input mode |
} |
|
return GetData; |
|
} |
/*---------------------------------------------------------------------- |
* |
* FUNCTION NAME: |
* |
* DESCRIPTION: Shift out bits of data |
* |
* EXTERNAL EFFECT: |
* |
* PARAMETERS: |
* |
* RETURNS: None |
* |
* ASSUMPTIONS: |
* |
*----------------------------------------------------------------------*/ |
void |
MdioSend(UINT32 txF, UINT16 size) { |
|
UINT32 dmask; |
INT_NATIVE i, j; |
|
dmask = 1 << (size-1); // msbit out first |
|
for (i = 0; i < size; i++) { // for "size" bits |
|
if ( txF & dmask ) //output data bit high |
*pPortData |= MDIO_PIN_MASK; |
else //output data bit low > 400ns |
*pPortData &= ~MDIO_PIN_MASK; |
// >10ns |
*pPortData |= MDC_PIN_MASK; // clock rise |
|
txF = (UINT32)(txF << 1); // >160ns |
|
for (j=0; j<MDC_HOLD_TIME; j++); |
|
*pPortData &= ~MDC_PIN_MASK; // clock fall |
|
for (j=0; j<MDC_HOLD_TIME; j++); |
|
} |
|
return; |
} |
|
|
/*--------------------------------------------------------------------- |
* |
* FUNCTION NAME: |
* |
* DESCRIPTION: Shifts in bits of data |
* |
* EXTERNAL EFFECT: |
* |
* PARAMETERS: |
* |
* RETURNS: |
* |
* ASSUMPTIONS: |
* |
*---------------------------------------------------------------------*/ |
UINT16 |
MdioReceive(UINT16 size) { |
|
UINT16 i,j, rxF = 0; |
|
for (i = 0; i < size; i++) { // 16 bits |
|
*pPortData |= MDC_PIN_MASK; // clock rise |
|
if ( *pPortData & MDIO_PIN_MASK ) // if read in a high bit |
rxF = ( (UINT16)(rxF << 1) | 1 ); // shift in a one |
else // if read in a low bit |
rxF = ( (UINT16)(rxF << 1) & ~(UINT16)1 ); // shift in a zero |
|
|
for (j=0; j<MDC_HOLD_TIME; j++); |
|
*pPortData &= ~MDC_PIN_MASK; // clock fall |
|
for (j=0; j<MDC_HOLD_TIME; j++); |
|
} |
|
return rxF; |
} |
|