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Rev 1254 → Rev 1765

/hal_io.h
0,0 → 1,158
#ifndef CYGONCE_HAL_HAL_IO_H
#define CYGONCE_HAL_HAL_IO_H
 
//=============================================================================
//
// hal_io.h
//
// HAL device IO register support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg
// Date: 1998-02-17
// Purpose: Define IO register support
// Description: The macros defined here provide the HAL APIs for handling
// device IO control registers.
//
// Usage:
// #include <cyg/hal/hal_io.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/plf_io.h>
 
//-----------------------------------------------------------------------------
// IO Register address.
// This type is for recording the address of an IO register.
 
typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
 
//-----------------------------------------------------------------------------
// HAL IO macros.
#ifndef HAL_IO_MACROS_DEFINED
 
//-----------------------------------------------------------------------------
// BYTE Register access.
// Individual and vectorized access to 8 bit registers.
 
#define HAL_READ_UINT8( _register_, _value_ ) \
((_value_) = *((volatile CYG_BYTE *)(_register_)))
 
#define HAL_WRITE_UINT8( _register_, _value_ ) \
(*((volatile CYG_BYTE *)(_register_)) = (_value_))
 
#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
{ \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
(_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \
}
 
#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
{ \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \
}
 
 
//-----------------------------------------------------------------------------
// 16 bit access.
// Individual and vectorized access to 16 bit registers.
#define HAL_READ_UINT16( _register_, _value_ ) \
((_value_) = *((volatile CYG_WORD16 *)(_register_)))
 
#define HAL_WRITE_UINT16( _register_, _value_ ) \
(*((volatile CYG_WORD16 *)(_register_)) = (_value_))
 
#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
{ \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
(_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \
}
 
#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
{ \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \
}
 
//-----------------------------------------------------------------------------
// 32 bit access.
// Individual and vectorized access to 32 bit registers.
#define HAL_READ_UINT32( _register_, _value_ ) \
((_value_) = *((volatile CYG_WORD32 *)(_register_)))
 
#define HAL_WRITE_UINT32( _register_, _value_ ) \
(*((volatile CYG_WORD32 *)(_register_)) = (_value_))
 
#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
{ \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
(_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \
}
 
#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
{ \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \
}
 
#define HAL_IO_MACROS_DEFINED
 
#endif
 
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_HAL_IO_H
// End of hal_io.h
/basetype.h
0,0 → 1,78
#ifndef CYGONCE_HAL_BASETYPE_H
#define CYGONCE_HAL_BASETYPE_H
 
//=============================================================================
//
// basetype.h
//
// Standard types for this architecture.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, msalter
// Date: 1998-02-05
// Purpose: Define architecture base types.
// Usage: Included by <cyg/infra/cyg_types.h>, do not use directly
//
//####DESCRIPTIONEND####
//
 
#include <pkgconf/hal.h>
 
//-----------------------------------------------------------------------------
// Characterize the architecture
 
#define CYG_BYTEORDER CYG_MSBFIRST // Big endian
 
 
 
//-----------------------------------------------------------------------------
// CalmRISC16 toolchain uses labels with undersores.
 
#define CYG_LABEL_DEFN(_name_) _##_name_
 
//-----------------------------------------------------------------------------
// Define the standard variable sizes
 
#define cyg_halint16 int
#define cyg_halint32 long
#define cyg_halcount32 long
 
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_BASETYPE_H
// End of basetype.h
/calm16-stub.h
0,0 → 1,156
#ifndef CYGONCE_HAL_MIPS_STUB_H
#define CYGONCE_HAL_MIPS_STUB_H
//========================================================================
//
// mips-stub.h
//
// CalmRISC16-specific definitions for generic stub
//
//========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Red Hat, msalter
// Contributors: Red Hat, msalter
// Date: 2001-02-12
// Purpose:
// Description: CalmRISC16-specific definitions for generic stub
// Usage:
//
//####DESCRIPTIONEND####
//
//========================================================================
 
 
#include <pkgconf/system.h>
 
#include <cyg/hal/hal_io.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define TARGET_HAS_HARVARD_MEMORY 1
typedef unsigned long target_addr_t;
#define TARGET_ADDR_IS_PROGMEM(x) (((unsigned long)(x)) >= 0x400000UL)
#define TARGET_ADDR_TO_PTR(x) ((char *) (((unsigned long)(x)) & 0x3fffff))
 
#define NUMREGS 39
 
typedef unsigned long target_register_t;
 
enum regnames {
REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15,
REG_E8, REG_E9, REG_E10, REG_E11, REG_E12, REG_E13, REG_E14, REG_E15,
REG_A8, REG_A9, REG_A10, REG_A11, REG_A12, REG_A13, REG_A14, REG_A15,
REG_PC, REG_SPC_FIQ, REG_SPC_IRQ,
REG_SR, REG_SSR_FIQ, REG_SSR_IRQ, REG_SSR_SWI
};
 
#define REG_LR REG_A14
#define REG_SP REG_A15
 
#define PC REG_PC
#define SP REG_A15
 
#define REGSIZE(X) 4
#define REGBYTE(X) ((X)*4)
 
typedef enum regnames regnames_t;
 
/* Given a trap value TRAP, return the corresponding signal. */
extern int __computeSignal (unsigned int trap_number);
 
/* Return the SPARC trap number corresponding to the last-taken trap. */
extern int __get_trap_number (void);
 
/* Return the currently-saved value corresponding to register REG. */
extern target_register_t get_register (regnames_t reg);
 
/* Store VALUE in the register corresponding to WHICH. */
extern void put_register (regnames_t which, target_register_t value);
 
/* Set the currently-saved pc register value to PC. This also updates NPC
as needed. */
#if !defined(SET_PC_PROTOTYPE_EXISTS) && !defined(set_pc)
#define SET_PC_PROTOTYPE_EXISTS
extern void set_pc (target_register_t pc);
#endif
 
/* Set things up so that the next user resume will execute one instruction.
This may be done by setting breakpoints or setting a single step flag
in the saved user registers, for example. */
#ifndef __single_step
void __single_step (void);
#endif
 
/* Clear the single-step state. */
void __clear_single_step (void);
 
extern int __is_bsp_syscall(void);
 
extern int hal_syscall_handler(void);
/* If the breakpoint we hit is in the breakpoint() instruction, return a
non-zero value. */
#ifndef __is_breakpoint_function
extern int __is_breakpoint_function (void);
#endif
 
/* Skip the current instruction. */
extern void __skipinst (void);
 
extern void __install_breakpoints (void);
 
extern void __clear_breakpoints (void);
 
extern void __install_breakpoint_list (void);
 
extern void __clear_breakpoint_list (void);
 
extern unsigned char __read_prog_uint8(void *addr);
extern unsigned short __read_prog_uint16(void *addr);
extern unsigned long __read_prog_uint32(void *addr);
 
extern void __write_prog_uint8(void *addr, unsigned char val);
extern void __write_prog_uint16(void *addr, unsigned short val);
extern void __write_prog_uint32(void *addr, unsigned long val);
 
#ifdef __cplusplus
} /* extern "C" */
#endif
 
#endif // ifndef CYGONCE_HAL_MIPS_STUB_H
/arch.inc
0,0 → 1,157
#ifndef CYGONCE_HAL_ARCH_INC
#define CYGONCE_HAL_ARCH_INC
##=============================================================================
##
## arch.inc
##
## CalmRISC16 assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): msalter
## Contributors: nickg, dmoseley
## Date: 1997-10-16
## Purpose: Architecture definitions.
## Description: This file contains various definitions and macros that are
## useful for writing assembly code for the CalmRISC16 CPU family.
## Usage:
## #include <cyg/hal/arch.inc>
## ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <cyg/hal/calm16.inc>
#include <cyg/hal/variant.inc>
 
##-----------------------------------------------------------------------------
## CalmRISC16 thread and interrupt saved state. This must match the layout of
## the HAL_SavedRegisters in hal_arch.h. Do not change this without changing
## the layout there, or viceversa.
 
 
##-----------------------------------------------------------------------------
## CPU specific macros. These provide a common assembler interface to
## operations that may have CPU specific implementations on different
## variants of the architecture.
# Initialize CPU
.macro hal_cpu_init
.endm
 
# Enable interrupts
.macro hal_cpu_int_enable
.endm
 
# Disable interrupts
.macro hal_cpu_int_disable
.endm
 
#------------------------------------------------------------------------------
# MMU macros.
#ifndef CYGPKG_HAL_CALM16_MMU_DEFINED
 
.macro hal_mmu_init
.endm
 
#endif
 
#------------------------------------------------------------------------------
# MEMC macros.
#ifndef CYGPKG_HAL_CALM16_MEMC_DEFINED
 
.macro hal_memc_init
.endm
 
#endif
#------------------------------------------------------------------------------
# Cache macros.
#ifndef CYGPKG_HAL_CALM16_CACHE_DEFINED
 
.macro hal_cache_init
.endm
#endif
 
 
#------------------------------------------------------------------------------
# Diagnostics macros.
#ifndef CYGPKG_HAL_CALM16_DIAG_DEFINED
 
.macro hal_diag_init
.endm
 
.macro hal_diag_excpt_start
.endm
 
.macro hal_diag_intr_start
.endm
 
.macro hal_diag_restore
.endm
#endif
 
#------------------------------------------------------------------------------
# Timer initialization.
#ifndef CYGPKG_HAL_CALM16_TIMER_DEFINED
 
.macro hal_timer_init
.endm
 
#endif
 
#------------------------------------------------------------------------------
# Monitor initialization.
#ifndef CYGPKG_HAL_CALM16_MON_DEFINED
 
.macro hal_mon_init
.endm
 
#endif
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_ARCH_INC
# end of arch.inc
/hal_intr.h
0,0 → 1,299
#ifndef CYGONCE_HAL_HAL_INTR_H
#define CYGONCE_HAL_HAL_INTR_H
 
//==========================================================================
//
// hal_intr.h
//
// HAL Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jskov,
// gthomas, jlarmour, msalter
// Date: 1999-02-16
// Purpose: Define Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock.
//
// Usage:
// #include <cyg/hal/hal_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_io.h>
 
#include <cyg/hal/var_intr.h>
 
//--------------------------------------------------------------------------
// MIPS vectors.
 
// These are the exception codes presented in the Cause register and
// correspond to VSRs. These values are the ones to use for HAL_VSR_GET/SET
 
 
#define CYGNUM_HAL_VECTOR_RESET 0 // Reset
#define CYGNUM_HAL_VECTOR_FIQ 1 // External Fast Interrupt
#define CYGNUM_HAL_VECTOR_IRQ 2 // External Interrupt
#define CYGNUM_HAL_VECTOR_TRACE 3 // Trace Request
#define CYGNUM_HAL_VECTOR_SWI 4 // SWI
 
#define CYGNUM_HAL_VSR_MIN 0
#define CYGNUM_HAL_VSR_MAX 4
#define CYGNUM_HAL_VSR_COUNT 5
 
// Min/Max exception numbers and how many there are
#define CYGNUM_HAL_EXCEPTION_MIN 0
#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX
 
#define CYGNUM_HAL_EXCEPTION_COUNT \
( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 )
 
 
#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
#define CYGNUM_HAL_FAST_INTERRUPT 0
#define CYGNUM_HAL_INTERRUPT 1
 
// Min/Max ISR numbers and how many there are
#define CYGNUM_HAL_ISR_MIN 0
#define CYGNUM_HAL_ISR_MAX 1
#define CYGNUM_HAL_ISR_COUNT 2
 
#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
#endif
 
//--------------------------------------------------------------------------
// Static data used by HAL
 
// ISR tables
externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
 
// VSR table
externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_MAX+1];
 
//--------------------------------------------------------------------------
// Default ISR
// The #define is used to test whether this routine exists, and to allow
// us to call it.
 
externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
 
#define HAL_DEFAULT_ISR hal_default_isr
 
//--------------------------------------------------------------------------
// Interrupt state storage
 
typedef cyg_uint32 CYG_INTERRUPT_STATE;
 
//--------------------------------------------------------------------------
// Interrupt control macros
// Beware of nops in this code. They fill delay slots and avoid CP0 hazards
// that might otherwise cause following code to run in the wrong state or
// cause a resource conflict.
 
#define HAL_DISABLE_INTERRUPTS(_old_)
#define HAL_ENABLE_INTERRUPTS()
#define HAL_RESTORE_INTERRUPTS(_old_)
#define HAL_QUERY_INTERRUPTS( _state_ )
 
//--------------------------------------------------------------------------
// Routine to execute DSRs using separate interrupt stack
 
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
externC void hal_interrupt_stack_call_pending_DSRs(void);
#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
hal_interrupt_stack_call_pending_DSRs()
 
// these are offered solely for stack usage testing
// if they are not defined, then there is no interrupt stack.
#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
// use them to declare these extern however you want:
// extern char HAL_INTERRUPT_STACK_BASE[];
// extern char HAL_INTERRUPT_STACK_TOP[];
// is recommended
#endif
 
//--------------------------------------------------------------------------
// Vector translation.
// For chained interrupts we only have a single vector though which all
// are passed. For unchained interrupts we have a vector per interrupt.
 
#ifndef HAL_TRANSLATE_VECTOR
 
#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
 
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0
 
#else
 
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_)
 
#endif
 
#endif
 
//--------------------------------------------------------------------------
// Interrupt and VSR attachment macros
 
#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
CYG_MACRO_START \
cyg_uint32 _index_; \
HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
\
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
(_state_) = 0; \
else \
(_state_) = 1; \
CYG_MACRO_END
 
#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
{ \
cyg_uint32 _index_; \
HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \
\
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
{ \
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \
hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
} \
}
 
#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
{ \
cyg_uint32 _index_; \
HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \
\
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
{ \
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \
hal_interrupt_data[_index_] = 0; \
hal_interrupt_objects[_index_] = 0; \
} \
}
 
#define HAL_VSR_GET( _vector_, _pvsr_ ) \
*(_pvsr_) = (void (*)())hal_vsr_table[_vector_];
 
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) CYG_MACRO_START \
if( (void*)_poldvsr_ != NULL) \
*(CYG_ADDRESS *)_poldvsr_ = (CYG_ADDRESS)hal_vsr_table[_vector_]; \
hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
CYG_MACRO_END
 
// This is an ugly name, but what it means is: grab the VSR back to eCos
// internal handling, or if you like, the default handler. But if
// cooperating with GDB and CygMon, the default behaviour is to pass most
// exceptions to CygMon. This macro undoes that so that eCos handles the
// exception. So use it with care.
 
externC void __default_exception_vsr(void);
externC void __default_interrupt_vsr(void);
externC void __break_vsr_springboard(void);
 
#define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START \
HAL_VSR_SET( _vector_, _vector_ == CYGNUM_HAL_VECTOR_INTERRUPT \
? (CYG_ADDRESS)__default_interrupt_vsr \
: _vector_ == CYGNUM_HAL_VECTOR_BREAKPOINT \
? (CYG_ADDRESS)__break_vsr_springboard \
: (CYG_ADDRESS)__default_exception_vsr, \
_poldvsr_ ); \
CYG_MACRO_END
 
//--------------------------------------------------------------------------
// Interrupt controller access
// The default code here simply uses the fields present in the CP0 status
// and cause registers to implement this functionality.
// Beware of nops in this code. They fill delay slots and avoid CP0 hazards
// that might otherwise cause following code to run in the wrong state or
// cause a resource conflict.
 
#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 
#define HAL_INTERRUPT_MASK( _vector_ )
 
#define HAL_INTERRUPT_UNMASK( _vector_ )
 
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )
 
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
 
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
 
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 
#endif
 
//--------------------------------------------------------------------------
// Clock control.
// This code uses the count and compare registers that are present in many
// MIPS variants.
// Beware of nops in this code. They fill delay slots and avoid CP0 hazards
// that might otherwise cause following code to run in the wrong state or
// cause a resource conflict.
 
#ifndef CYGHWR_HAL_CLOCK_CONTROL_DEFINED
 
externC CYG_WORD32 cyg_hal_clock_period;
#define CYGHWR_HAL_CLOCK_PERIOD_DEFINED
 
#define HAL_CLOCK_INITIALIZE( _period_ )
 
#define HAL_CLOCK_RESET( _vector_, _period_ )
 
#define HAL_CLOCK_READ( _pvalue_ )
 
#define CYGHWR_HAL_CLOCK_CONTROL_DEFINED
 
#endif
 
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_HAL_INTR_H
// End of hal_intr.h
/calm16-regs.h
0,0 → 1,78
#ifndef CYGONCE_HAL_CALM16_REGS_H
#define CYGONCE_HAL_CALM16_REGS_H
//========================================================================
//
// calm16-regs.h
//
// Register defines for CalmRISC 16 processors
//
//========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Red Hat, msalter
// Contributors: Red Hat, msalter
// Date: 2001-02-12
// Purpose:
// Description: Register defines for CalmRISC 16 processors
// Usage:
//
//####DESCRIPTIONEND####
//
//========================================================================
 
#include <pkgconf/hal.h>
 
#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
 
// This value must agree with NUMREGS in calm16-stub.h.
 
#define NUM_REGS 23
 
#define REG_SIZE 4
 
// Status register fields
#define SR_T 0x8000 // TRUE flag
#define SR_PM 0x0040 // Privilege Mode
#define SR_Z1 0x0020 // R7 Zero flag.
#define SR_Z0 0x0010 // R6 Zero flag
#define SR_V 0x0008 // Overflow flag
#define SR_TE 0x0004 // Trace Enable
#define SR_IE 0x0002 // IRQ Enable
#define SR_FE 0x0001 // FIQ Enable
 
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
 
#endif // ifndef CYGONCE_HAL_CALM16_REGS_H
/hal_arch.h
0,0 → 1,345
#ifndef CYGONCE_HAL_HAL_ARCH_H
#define CYGONCE_HAL_HAL_ARCH_H
 
//==========================================================================
//
// hal_arch.h
//
// Architecture specific abstractions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): msalter
// Contributors: msalter
// Date: 2001-02-17
// Purpose: Define architecture abstractions
// Usage: #include <cyg/hal/hal_arch.h>
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#ifndef __ASSEMBLER__
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/var_arch.h>
 
//--------------------------------------------------------------------------
// Processor saved states:
// The layout of this structure is also defined in "arch.inc", for assembly
// code. Do not change this without changing that (or vice versa).
// Notes: This structure is carefully laid out. It is a multiple of 8
// bytes and the pc and badvr fields are positioned to ensure that
// they are on 8 byte boundaries.
 
 
typedef struct
{
CYG_WORD16 vector;
CYG_WORD32 spc_fiq;
CYG_WORD32 spc_irq;
CYG_WORD16 ssr_fiq;
CYG_WORD16 ssr_irq;
CYG_WORD16 ssr_swi;
CYG_WORD16 r[8];
CYG_WORD32 a[8];
} HAL_SavedRegisters;
 
//--------------------------------------------------------------------------
// Exception handling function.
// This function is defined by the kernel according to this prototype. It is
// invoked from the HAL to deal with any CPU exceptions that the HAL does
// not want to deal with itself. It usually invokes the kernel's exception
// delivery mechanism.
 
externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
 
//--------------------------------------------------------------------------
// Bit manipulation macros
 
externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);
 
#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);
 
#define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);
 
//--------------------------------------------------------------------------
// Context Initialization
 
// Optional FPU context initialization
#define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ )
 
// Initialize the context of a thread.
// Arguments:
// _sparg_ name of variable containing current sp, will be written with new sp
// _thread_ thread object address, passed as argument to entry point
// _entry_ entry point address.
// _id_ bit pattern used in initializing registers, for debugging.
#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
{ \
}
 
//--------------------------------------------------------------------------
// Context switch macros.
// The arguments are pointers to locations where the stack pointer
// of the current thread is to be stored, and from where the sp of the
// next thread is to be fetched.
 
externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
externC void hal_thread_load_context( CYG_ADDRESS to )
__attribute__ ((noreturn));
 
#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
hal_thread_switch_context( (CYG_ADDRESS)_tspptr_, \
(CYG_ADDRESS)_fspptr_);
 
#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
 
//--------------------------------------------------------------------------
// Execution reorder barrier.
// When optimizing the compiler can reorder code. In multithreaded systems
// where the order of actions is vital, this can sometimes cause problems.
// This macro may be inserted into places where reordering should not happen.
// The "memory" keyword is potentially unnecessary, but it is harmless to
// keep it.
 
#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
 
//--------------------------------------------------------------------------
// Breakpoint support
// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to
// happen if executed.
// HAL_BREAKINST is the value of the breakpoint instruction and
// HAL_BREAKINST_SIZE is its size in bytes.
// HAL_BREAKINST_TYPE is the type.
 
#define HAL_BREAKPOINT(_label_) \
asm volatile (" .globl _" #_label_ "\n" \
"_" #_label_":" \
" break\n" \
);
 
#define HAL_BREAKINST 0x9e99
#define HAL_BREAKINST_SIZE 2
#define HAL_BREAKINST_TYPE cyg_uint16
 
//--------------------------------------------------------------------------
// Thread register state manipulation for GDB support.
 
// Default to a 32 bit register size for GDB register dumps.
#ifndef CYG_HAL_GDB_REG
#define CYG_HAL_GDB_REG CYG_WORD32
#endif
 
// Translate a stack pointer as saved by the thread context macros above into
// a pointer to a HAL_SavedRegisters structure.
#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
(_regs_) = (HAL_SavedRegisters *)(_sp_)
 
// Copy a set of registers from a HAL_SavedRegisters structure into a
// GDB ordered array.
#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \
{ \
CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \
int _i_; \
\
for( _i_ = 0; _i_ < 8; _i_++ ) \
_regval_[_i_] = ((CYG_WORD32)((_regs_)->r[_i_])) << 16; \
\
for( _i_ = 0; _i_ < 8; _i_++ ) \
_regval_[_i_+8] = ((_regs_)->a[_i_]) << 16; \
\
for( _i_ = 0; _i_ < 8; _i_++ ) \
_regval_[_i_+16] = ((_regs_)->a[_i_]) & 0xffff0000UL; \
\
for( _i_ = 0; _i_ < 8; _i_++ ) \
_regval_[_i_+24] = (_regs_)->a[_i_]; \
\
_regval_[REG_SSR_FIQ] = ((CYG_WORD32)((_regs_)->ssr_fiq)) << 16; \
_regval_[REG_SSR_IRQ] = ((CYG_WORD32)((_regs_)->ssr_irq)) << 16; \
_regval_[REG_SSR_SWI] = ((CYG_WORD32)((_regs_)->ssr_swi)) << 16; \
_regval_[REG_SPC_FIQ] = (_regs_)->spc_fiq; \
_regval_[REG_SPC_IRQ] = (_regs_)->spc_irq; \
switch ((_regs_)->vector) { \
case CYGNUM_HAL_VECTOR_SWI: \
_regval_[REG_SR] = _regval_[REG_SSR_SWI]; \
_regval_[REG_PC] = (_regs_)->a[6]; break; \
case CYGNUM_HAL_VECTOR_FIQ: \
_regval_[REG_SR] = _regval_[REG_SSR_FIQ]; \
_regval_[REG_PC] = (_regs_)->spc_fiq; break; \
default: \
_regval_[REG_SR] = _regval_[REG_SSR_IRQ]; \
_regval_[REG_PC] = (_regs_)->spc_irq; break; \
} \
}
 
// Copy a GDB ordered array into a HAL_SavedRegisters structure.
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
{ \
CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \
int _i_; \
\
for( _i_ = 0; _i_ < 8; _i_++ ) \
(_regs_)->r[_i_] = _regval_[_i_] >> 16; \
\
for( _i_ = 0; _i_ < 8; _i_++ ) \
(_regs_)->a[_i_] = _regval_[_i_+24]; \
\
(_regs_)->ssr_fiq = _regval_[REG_SSR_FIQ] >> 16; \
(_regs_)->ssr_irq = _regval_[REG_SSR_IRQ] >> 16; \
(_regs_)->ssr_swi = _regval_[REG_SSR_SWI] >> 16; \
(_regs_)->spc_fiq = _regval_[REG_SPC_FIQ]; \
(_regs_)->spc_irq = _regval_[REG_SPC_IRQ]; \
switch (__get_trap_number()) { \
case CYGNUM_HAL_VECTOR_SWI: \
(_regs_)->ssr_swi = _regval_[REG_SR] >> 16; \
(_regs_)->a[6] = _regval_[REG_PC]; break; \
case CYGNUM_HAL_VECTOR_FIQ: \
(_regs_)->ssr_fiq = _regval_[REG_SR] >> 16; \
(_regs_)->spc_fiq = _regval_[REG_PC]; break; \
default: \
(_regs_)->ssr_irq = _regval_[REG_SR] >> 16; \
(_regs_)->spc_irq = _regval_[REG_PC]; break; \
} \
}
 
#define CYGARC_HAL_GET_PC_REG(_regs_, _val_) \
{ \
switch ((_regs_)->vector) { \
case CYGNUM_HAL_VECTOR_SWI: \
(_val_) = (_regs_)->a[6]; break; \
case CYGNUM_HAL_VECTOR_FIQ: \
(_val_) = (_regs_)->spc_fiq; break; \
default: \
(_val_) = (_regs_)->spc_irq; break; \
} \
}
 
//--------------------------------------------------------------------------
// HAL setjmp
// Note: These definitions are repeated in context.S. If changes are
// required remember to update both sets.
 
#define CYGARC_JMP_BUF_R4 0
#define CYGARC_JMP_BUF_R5 2
#define CYGARC_JMP_BUF_A12 4
#define CYGARC_JMP_BUF_A13 8
#define CYGARC_JMP_BUF_A14 12
#define CYGARC_JMP_BUF_A15 16
 
#define CYGARC_JMP_BUF_SIZE 20
 
typedef cyg_uint16 hal_jmp_buf[CYGARC_JMP_BUF_SIZE/sizeof(cyg_uint16)];
 
externC int hal_setjmp(hal_jmp_buf env);
externC void hal_longjmp(hal_jmp_buf env, int val);
 
//-------------------------------------------------------------------------
// Idle thread code.
// This macro is called in the idle thread loop, and gives the HAL the
// chance to insert code. Typical idle thread behaviour might be to halt the
// processor.
 
externC void hal_idle_thread_action(cyg_uint32 loop_count);
 
#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
 
//--------------------------------------------------------------------------
// Minimal and sensible stack sizes: the intention is that applications
// will use these to provide a stack size in the first instance prior to
// proper analysis. Idle thread stack should be this big.
 
// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
 
// This is not a config option because it should not be adjusted except
// under "enough rope" sort of disclaimers.
 
// Typical case stack frame size: return link + 4 pushed registers + some locals.
#define CYGNUM_HAL_STACK_FRAME_SIZE (48)
 
// Stack needed for a context switch:
#define CYGNUM_HAL_STACK_CONTEXT_SIZE ((32+10)*CYG_HAL_MIPS_REG_SIZE)
 
// Interrupt + call to ISR, interrupt_end() and the DSR
#define CYGNUM_HAL_STACK_INTERRUPT_SIZE (4+2*CYGNUM_HAL_STACK_CONTEXT_SIZE)
 
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
 
// An interrupt stack which is large enough for all possible interrupt
// conditions (and only used for that purpose) exists. "User" stacks
// can be much smaller
 
#define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+ \
CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+ \
CYGNUM_HAL_STACK_FRAME_SIZE*8)
#define CYGNUM_HAL_STACK_SIZE_TYPICAL (CYGNUM_HAL_STACK_SIZE_MINIMUM+1024)
 
#else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
 
// No separate interrupt stack exists. Make sure all threads contain
// a stack sufficiently large.
 
#define CYGNUM_HAL_STACK_SIZE_MINIMUM (4096)
#define CYGNUM_HAL_STACK_SIZE_TYPICAL (4096)
 
#endif
 
#endif /* __ASSEMBLER__ */
 
 
//--------------------------------------------------------------------------
// Macros for switching context between two eCos instances (jump from
// code in ROM to code in RAM or vice versa).
#define CYGARC_HAL_SAVE_GP()
#define CYGARC_HAL_RESTORE_GP()
 
//--------------------------------------------------------------------------
// Defines for status register bit access
 
#define CYGARC_SR_PM (1<<6)
#define CYGARC_SR_TE (1<<2)
#define CYGARC_SR_IE (1<<1)
#define CYGARC_SR_FE (1<<0)
 
//--------------------------------------------------------------------------
#endif // CYGONCE_HAL_HAL_ARCH_H
// End of hal_arch.h
/calm16.inc
0,0 → 1,94
#ifndef CYGONCE_HAL_CALM16_INC
#define CYGONCE_HAL_CALM16_INC
 
##=============================================================================
##
## calm16.inc
##
## CalmRISC16 assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): msalter
## Contributors: msalter
## Date: 2001-02-12
## Purpose: CalmRISC16 definitions.
## Description: This file contains various definitions and macros that are
## useful for writing assembly code for the MIPS CPU family.
## Usage:
## #include <cyg/hal/calm16.inc>
## ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
 
#------------------------------------------------------------------------------
 
#ifdef __USER_LABEL_PREFIX__
#define __GLUE(a,b) a##b
#define _GLUE(a,b) __GLUE(a,b)
#define SYM_NAME(x) _GLUE(_,x)
 
.macro FUNC_START name
.type _\name,@function
.globl _\name
_\name:
.endm
 
.macro FUNC_END name
_\name\(_end):
.endm
#else
#define SYM_NAME(x) x
.macro FUNC_START name
.type \name,@function
.globl \name
\name:
.endm
 
.macro FUNC_END name
\name\(_end):
.endm
#endif
 
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_CALM16_INC
# end of calm16.inc
/hal_cache.h
0,0 → 1,265
#ifndef CYGONCE_HAL_CACHE_H
#define CYGONCE_HAL_CACHE_H
 
//=============================================================================
//
// hal_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg
// Date: 1998-02-17
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/hal_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/var_cache.h>
 
 
//-----------------------------------------------------------------------------
// Cache dimensions.
// These really should be defined in var_cache.h. If they are not, then provide
// a set of numbers that are typical of many variants.
 
#ifndef HAL_DCACHE_SIZE
 
// Data cache
//#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes
//#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line
//#define HAL_DCACHE_WAYS 0 // Associativity of the cache
 
// Instruction cache
//#define HAL_ICACHE_SIZE 0 // Size of cache in bytes
//#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line
//#define HAL_ICACHE_WAYS 0 // Associativity of the cache
 
//#define HAL_DCACHE_SETS 0
//#define HAL_ICACHE_SETS 0
 
#endif
 
//-----------------------------------------------------------------------------
// Global control of data cache
 
// Enable the data cache
// There is no default mechanism for enabling or disabling the caches.
#ifndef HAL_DCACHE_ENABLE_DEFINED
#define HAL_DCACHE_ENABLE()
#endif
 
// Disable the data cache
#ifndef HAL_DCACHE_DISABLE_DEFINED
#define HAL_DCACHE_DISABLE()
#endif
 
#ifndef HAL_DCACHE_IS_ENABLED_DEFINED
#define HAL_DCACHE_IS_ENABLED(_state_) (_state_) = 1;
#endif
 
// Invalidate the entire cache
// We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this
// is not quite what we want, but there is no index-invalidate operation
// available.
#ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED
#define HAL_DCACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC()
#endif
 
// Synchronize the contents of the cache with memory.
// This uses the index-writeback-invalidate operation.
#ifndef HAL_DCACHE_SYNC_DEFINED
#define HAL_DCACHE_SYNC() \
CYG_MACRO_START \
CYG_MACRO_END
#endif
 
// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)
 
// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
 
//#define HAL_DCACHE_WRITETHRU_MODE 0
//#define HAL_DCACHE_WRITEBACK_MODE 1
 
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
// This uses the fetch-and-lock cache operation.
#ifndef HAL_DCACHE_LOCK_DEFINED
#define HAL_DCACHE_LOCK(_base_, _asize_) \
CYG_MACRO_START \
CYG_MACRO_END
#endif
 
// Undo a previous lock operation.
// Do this by flushing the cache, which is defined to clear the lock bit.
#ifndef HAL_DCACHE_UNLOCK_DEFINED
#define HAL_DCACHE_UNLOCK(_base_, _size_) \
HAL_DCACHE_FLUSH( _base_, _size_ )
#endif
 
// Unlock entire cache
#ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED
#define HAL_DCACHE_UNLOCK_ALL() \
HAL_DCACHE_INVALIDATE_ALL()
#endif
 
//-----------------------------------------------------------------------------
// Data cache line control
 
// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
// This uses the hit-writeback-invalidate cache operation.
#ifndef HAL_DCACHE_FLUSH_DEFINED
#define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
CYG_MACRO_START \
CYG_MACRO_END
#endif
 
// Invalidate cache lines in the given range without writing to memory.
// This uses the hit-invalidate cache operation.
#ifndef HAL_DCACHE_INVALIDATE_DEFINED
#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
CYG_MACRO_START \
CYG_MACRO_END
#endif
 
// Write dirty cache lines to memory for the given address range.
// This uses the hit-writeback cache operation.
#ifndef HAL_DCACHE_STORE_DEFINED
#define HAL_DCACHE_STORE( _base_ , _asize_ ) \
CYG_MACRO_START \
CYG_MACRO_END
#endif
 
// Preread the given range into the cache with the intention of reading
// from it later.
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of writing
// to it later.
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
 
// Allocate and zero the cache lines associated with the given range.
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
// Global control of Instruction cache
 
// Enable the instruction cache
// There is no default mechanism for enabling or disabling the caches.
#ifndef HAL_ICACHE_ENABLE_DEFINED
#define HAL_ICACHE_ENABLE()
#endif
 
// Disable the instruction cache
#ifndef HAL_ICACHE_DISABLE_DEFINED
#define HAL_ICACHE_DISABLE()
#endif
 
#ifndef HAL_ICACHE_IS_ENABLED_DEFINED
#define HAL_ICACHE_IS_ENABLED(_state_) (_state_) = 1;
#endif
 
// Invalidate the entire cache
// This uses the index-invalidate cache operation.
#ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
#define HAL_ICACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
CYG_MACRO_END
#endif
 
// Synchronize the contents of the cache with memory.
// Simply force the cache to reload.
#ifndef HAL_ICACHE_SYNC_DEFINED
#define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
#endif
 
// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)
 
// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
// This uses the fetch-and-lock cache operation.
#ifndef HAL_ICACHE_LOCK_DEFINED
#define HAL_ICACHE_LOCK(_base_, _asize_) \
CYG_MACRO_START \
CYG_MACRO_END
#endif
 
// Undo a previous lock operation.
// Do this by invalidating the cache, which is defined to clear the lock bit.
#ifndef HAL_ICACHE_UNLOCK_DEFINED
#define HAL_ICACHE_UNLOCK(_base_, _size_) \
HAL_ICACHE_INVALIDATE( _base_, _size_ )
#endif
 
// Unlock entire cache
//#define HAL_ICACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Instruction cache line control
 
// Invalidate cache lines in the given range without writing to memory.
// This uses the hit-invalidate cache operation.
#ifndef HAL_ICACHE_INVALIDATE_DEFINED
#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
CYG_MACRO_START \
CYG_MACRO_END
#endif
 
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_CACHE_H
// End of hal_cache.h

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