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/v2_0/cdl/hal_mips_idt32334_refidt334.cdl
0,0 → 1,340
# ====================================================================
#
# hal_mips_idt32334_refIDT334.cdl
#
# IDT32334 board HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): tmichals
# Original data: tmichals
# Contributors:
# Date: 2002-10-03
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_MIPS_IDT32334_REFIDT334 {
display "MIPS IDT79S334A reference platform"
parent CYGPKG_HAL_MIPS
requires CYGPKG_HAL_MIPS_IDT32334
define_header hal_mips_idt32334_ref.h
include_dir cyg/hal
description "
The REFIDT334 HAL package should be used when targetting the
actual hardware."
 
compile hal_diag.c platform.S plf_misc.c plf_stub.c ser16c550c.c
 
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
 
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_mips_idt32334.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_mips_idt32334_ref.h>"
puts $::cdl_header "#define CYGHWR_HAL_MIPS_WARMSTART_COLDSTART"
 
}
 
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
legal_values {"RAM" "ROM" "ROMRAM"}
default_value {"ROM"}
no_define
define -file system.h CYG_HAL_STARTUP
description "
When targetting the REFIDT334 board it is possible to build
the system for either RAM bootstrap, ROM bootstrap, or ROMRAM
bootstrap. RAM bootstrap generally requires that the board
is equipped with ROMs containing a suitable ROM monitor or
equivalent software that allows GDB to download the eCos
application on to the board, for example RedBoot. The ROM
bootstrap is intended for stand-alone applications and typically
requires that the eCos application be blown into EPROMs,
programmed into flash or equivalent technology. Using ROMRAM
will allow the program to exist in ROM, but be copied to RAM
during startup."
}
 
 
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
display "Diagnostic serial port baud rate"
flavor data
legal_values 9600 19200 38400 57600 115200
default_value 115200
description "
This option selects the baud rate used for the diagnostic port.
Note: this should match the value chosen for the GDB port if the
diagnostic and GDB port are the same."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
display "GDB serial port baud rate"
flavor data
legal_values 9600 19200 38400 57600 115200
default_value 115200
description "
This option controls the baud rate used for the GDB connection."
}
 
# Real-time clock/counter specifics
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants."
flavor none
cdl_option CYGNUM_HAL_RTC_NUMERATOR {
display "Real-time clock numerator"
flavor data
calculated 10000000
 
}
 
cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
display "Real-time clock denominator"
flavor data
calculated 100
}
# Isn't a nice way to handle freq requirement!
cdl_option CYGNUM_HAL_RTC_PERIOD {
display "Real-time clock period"
flavor data
calculated { (CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL / 2) / CYGNUM_HAL_RTC_DENOMINATOR }
description "
The count and compare registers of the MIPS core are used
to drive the eCos kernel RTC. The count register
increments at half the CPU clock speed."
}
}
 
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
parent CYGPKG_NONE
description "
Global build options including control over
compiler flags, linker flags and choice of toolchain."
 
 
cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
display "Global command prefix"
flavor data
no_define
default_value { "mipsisa32-elf" }
description "
This option specifies the command prefix used when
invoking the build tools."
}
 
cdl_option CYGBLD_GLOBAL_CFLAGS {
display "Global compiler flags"
flavor data
no_define
default_value { "-mips32 -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority -fno-builtin -G0" }
description "
This option controls the global compiler flags which
are used to compile all packages by
default. Individual packages may define
options which override these global flags."
}
 
cdl_option CYGBLD_GLOBAL_LDFLAGS {
display "Global linker flags"
flavor data
no_define
default_value { "-mips32 -g -nostdlib -Wl,--gc-sections -Wl,-static" }
description "
This option controls the global linker flags. Individual
packages may define options which override these global flags."
}
 
cdl_option CYGBLD_BUILD_GDB_STUBS {
display "Build GDB stub ROM image"
default_value 0
requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"}
requires CYGSEM_HAL_ROM_MONITOR
requires CYGBLD_BUILD_COMMON_GDB_STUBS
requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
no_define
description "
This option enables the building of the GDB stubs for the
board. The common HAL controls takes care of most of the
build process, but the final conversion from ELF image to
binary data is handled by the platform CDL, allowing
relocation of the data if necessary."
 
make -priority 320 {
<PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
$(OBJCOPY) -O binary $< $@
}
}
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
display "Number of communication channels on the board"
flavor data
calculated 1
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "
The IDT board has only one serial port. This option
chooses which port will be used to connect to a host
running GDB."
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
display "Diagnostic serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "
The IDT board has only one serial port. This option
chooses which port will be used for diagnostic output."
}
 
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define
calculated { CYG_HAL_STARTUP == "RAM" ? "mips_idt32334_refidt334_ram" : \
CYG_HAL_STARTUP == "ROM" ? "mips_idt32334_refidt334_rom" : \
"mips_idt32334_refidt334_romram" }
 
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
display "Memory layout linker script fragment"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_mips_idt32334_refidt334_ram.ldi>" : \
CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_mips_idt32334_refidt334_rom.ldi>" : \
"<pkgconf/mlt_mips_idt32334_refidt334_romram.ldi>" }
}
 
cdl_option CYGHWR_MEMORY_LAYOUT_H {
display "Memory layout header file"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_mips_idt32334_refidt334_ram.h>" : \
CYG_HAL_STARTUP == "ROM" ? "<pkgconf/mlt_mips_idt32334_refidt334_rom.h>" : \
"<pkgconf/mlt_mips_idt32334_refidt334_romram.h>" }
}
}
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
display "Work with a ROM monitor"
flavor booldata
legal_values { "Generic" "CygMon" "GDB_stubs" }
default_value { CYG_HAL_STARTUP == "RAM" ? "CygMon" : 0 }
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "RAM" }
description "
Support can be enabled for three different varieties of ROM monitor.
This support changes various eCos semantics such as the encoding
of diagnostic output, or the overriding of hardware interrupt
vectors.
Firstly there is \"Generic\" support which prevents the HAL
from overriding the hardware vectors that it does not use, to
instead allow an installed ROM monitor to handle them. This is
the most basic support which is likely to be common to most
implementations of ROM monitor.
\"CygMon\" provides support for the Cygnus ROM Monitor.
And finally, \"GDB_stubs\" provides support when GDB stubs are
included in the ROM monitor or boot ROM."
}
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
display "Behave as a ROM monitor"
flavor bool
default_value 0
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM"}
description "
Enable this option if this program is to be used as a ROM monitor,
i.e. applications will be loaded into RAM on the board, and this
ROM monitor may process exceptions or interrupts generated from the
application. This enables features such as utilizing a separate
interrupt stack when exceptions are generated."
}
 
cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
display "Redboot HAL options"
flavor none
no_define
parent CYGPKG_REDBOOT
active_if CYGPKG_REDBOOT
description "
This option lists the target's requirements for a valid Redboot
configuration."
 
cdl_option CYGBLD_BUILD_REDBOOT_BIN {
display "Build Redboot ROM binary image"
active_if CYGBLD_BUILD_REDBOOT
default_value 1
no_define
description "This option enables the conversion of the Redboot ELF
image to a binary image suitable for ROM programming."
compile -library=libextras.a
make -priority 325 {
<PREFIX>/bin/redboot.srec : <PREFIX>/bin/redboot.elf
$(OBJCOPY) --strip-all $< $(@:.srec=.img)
$(OBJCOPY) -O srec $< $@
}
}
}
}
 
# EOF hal_mips_idt32334_refidt334.cdl
/v2_0/include/idt32334sio.h
0,0 → 1,224
#ifndef CYGONCE_HAL_IDT32334SIO_H
#define CYGONCE_HAL_IDT32334SIO_H
 
/*=============================================================================
//
// idt32334sio.h
//
// IDT 32334 serial I/O definitions
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Tim Michals
// Contributors: nickg
// Date: 2003-02-13
// Purpose: IDT 32334 serial I/O definitions
// Description:
// Usage:
//####DESCRIPTIONEND####
//========================================================================*/
 
// Interrupt Enable Register
#define IER_RCV 0x01
#define IER_XMT 0x02
#define IER_LS 0x04
#define IER_MS 0x08
 
// Line Control Register
#define LCR_WL5 0x00 // Word length
#define LCR_WL6 0x01
#define LCR_WL7 0x02
#define LCR_WL8 0x03
#define LCR_SB1 0x00 // Number of stop bits
#define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words
#define LCR_SB2 0x04
#define LCR_PN 0x00 // Parity mode - none
#define LCR_PE 0x0C // Parity mode - even
#define LCR_PO 0x08 // Parity mode - odd
#define LCR_PM 0x28 // Forced "mark" parity
#define LCR_PS 0x38 // Forced "space" parity
#define LCR_DL 0x80 // Enable baud rate latch
 
// Line Status Register
#define LSR_RSR 0x01
#define LSR_THE 0x20
 
// Modem Control Register
#define MCR_DTR 0x01
#define MCR_RTS 0x02
#define MCR_INT 0x08 // Enable interrupts
 
// Interrupt status register
#define ISR_Tx 0x02
#define ISR_Rx 0x04
 
// FIFO control register
#define FCR_ENABLE 0x01
#define FCR_CLEAR_RCVR 0x02
#define FCR_CLEAR_XMIT 0x04
 
 
 
////////////////////////////////////////////////////////////
// Clean this up.
 
//-----------------------------------------------------------------------------
// There are two serial ports.
#define CMA_SER_16550_BASE_A 0xb8000803 // port A
#define CMA_SER_16550_BASE_B 0xb8000823 // port B
#define SER_16550_BASE CMA_SER_16550_BASE_A
 
//-----------------------------------------------------------------------------
// Define the serial registers. The Cogent board is equipped with a 16552
// serial chip.
#define SER_16550_RBR 0x00 // receiver buffer register, read, dlab = 0
#define SER_16550_THR 0x00 // transmitter holding register, write, dlab = 0
#define SER_16550_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
#define SER_16550_IER 0x04 // interrupt enable register, read/write, dlab = 0
#define SER_16550_DLM 0x04 // divisor latch (MS), read/write, dlab = 1
#define SER_16550_IIR 0x08 // interrupt identification reg, read, dlab = 0
#define SER_16550_FCR 0x08 // fifo control register, write, dlab = 0
#define SER_16550_AFR 0x10 // alternate function reg, read/write, dlab = 1
#define SER_16550_LCR 0x0c // line control register, read/write
#define SER_16550_MCR 0x10 // modem control register, read/write
#define SER_16550_LSR 0x14 // line status register, read
#define SER_16550_MSR 0x18 // modem status register, read
#define SER_16550_SCR 0x1C // scratch pad register
 
// The interrupt enable register bits.
#define SIO_IER_ERDAI 0x01 // enable received data available irq
#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
#define SIO_IER_ELSI 0x04 // enable receiver line status irq
#define SIO_IER_EMSI 0x08 // enable modem status interrupt
 
// The interrupt identification register bits.
#define SIO_IIR_IP 0x01 // 0 if interrupt pending
#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
 
// The line status register bits.
#define SIO_LSR_DR 0x01 // data ready
#define SIO_LSR_OE 0x02 // overrun error
#define SIO_LSR_PE 0x04 // parity error
#define SIO_LSR_FE 0x08 // framing error
#define SIO_LSR_BI 0x10 // break interrupt
#define SIO_LSR_THRE 0x20 // transmitter holding register empty
#define SIO_LSR_TEMT 0x40 // transmitter register empty
#define SIO_LSR_ERR 0x80 // any error condition
 
// The modem status register bits.
#define SIO_MSR_DCTS 0x01 // delta clear to send
#define SIO_MSR_DDSR 0x02 // delta data set ready
#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
#define SIO_MSR_DDCD 0x08 // delta data carrier detect
#define SIO_MSR_CTS 0x10 // clear to send
#define SIO_MSR_DSR 0x20 // data set ready
#define SIO_MSR_RI 0x40 // ring indicator
#define SIO_MSR_DCD 0x80 // data carrier detect
 
// The line control register bits.
#define SIO_LCR_WLS0 0x01 // word length select bit 0
#define SIO_LCR_WLS1 0x02 // word length select bit 1
#define SIO_LCR_STB 0x04 // number of stop bits
#define SIO_LCR_PEN 0x08 // parity enable
#define SIO_LCR_EPS 0x10 // even parity select
#define SIO_LCR_SP 0x20 // stick parity
#define SIO_LCR_SB 0x40 // set break
#define SIO_LCR_DLAB 0x80 // divisor latch access bit
 
// The FIFO control register
#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
/////////////////////////////////////////
 
 
static unsigned char select_word_length[] = {
LCR_WL5, // 5 bits / word (char)
LCR_WL6,
LCR_WL7,
LCR_WL8
};
 
static unsigned char select_stop_bits[] = {
0,
LCR_SB1, // 1 stop bit
LCR_SB1_5, // 1.5 stop bit
LCR_SB2 // 2 stop bits
};
 
static unsigned char select_parity[] = {
LCR_PN, // No parity
LCR_PE, // Even parity
LCR_PO, // Odd parity
LCR_PM, // Mark parity
LCR_PS, // Space parity
};
 
// FIXME: calc all properly
// The Cogent board has a 3.6864 MHz crystal
static unsigned short select_baud[] = {
0, // Unused
4608, // 50
0, // 75
2094, // 110
0, // 134.5
1536, // 150
0, // 200
768, // 300
384, // 600
182, // 1200
0, // 1800
96, // 2400
0, // 3600
48, // 4800
32, // 7200
24, // 9600
16, // 14400
12, // 19200
6, // 38400
4, // 57600
2, // 115200
0, // 230400
};
 
 
#define NS16550_XTAL_FREQ (75 * 1000000)
#define IDT_BAUD_RATE 115200
 
#endif /* CYGONCE_HAL_IDT32334SIO_H */
/*---------------------------------------------------------------------------*/
/* end of idt32334sio.h */
v2_0/include/idt32334sio.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/include/plf_intr.h =================================================================== --- v2_0/include/plf_intr.h (nonexistent) +++ v2_0/include/plf_intr.h (revision 1765) @@ -0,0 +1,211 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// RefIDT 79S344A Interrupt and clock support +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tmichals +// Contributors: +// +// Date: 2002-09-20 +// Purpose: Define Interrupt support +// Description: The macros defined here provide the HAL APIs for handling +// interrupts and the clock for the IDT79S334A board. +// +// Usage: +// #include +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include +#include +#include + +#define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT + +#define HAL_PLATFORM_RESET_ENTRY 0xbfc00000 + + +//-------------------------------------------------------------------------- +// Interrupt vectors. + +#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED +// the default for all MIPS variants is to use the 6 bits +// in the cause register. + +#define CYGNUM_HAL_INTERRUPT_0 0 +#define CYGNUM_HAL_INTERRUPT_1 1 +#define CYGNUM_HAL_INTERRUPT_2 2 +#define CYGNUM_HAL_INTERRUPT_3 3 +#define CYGNUM_HAL_INTERRUPT_4 4 +#define CYGNUM_HAL_INTERRUPT_5 5 + +// Min/Max ISR numbers and how many there are +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX 30 +#define CYGNUM_HAL_ISR_COUNT 31 + +// The vector used by the Real time clock. The default here is to use +// interrupt 5, which is connected to the counter/comparator registers +// in many MIPS variants. + +#define CYGNUM_HAL_PCI_A CYGNUM_HAL_INTERRUPT_1 +#define CYGNUM_HAL_PCI_B CYGNUM_HAL_INTERRUPT_2 +#define CYGNUM_HAL_PCI_C CYGNUM_HAL_INTERRUPT_4 +#define CYGNUM_EXPANSION CYGNUM_HAL_INTERRUPT_3 + + +#ifndef CYGNUM_HAL_INTERRUPT_RTC +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_5 +#endif + +/* please NOTE that slot D is taken for RTC */ +#define CYGNUM_LAST_IDT_INTERRUPT 20 + +#define CYGNUM_HAL_INTERRUPT_SIO_0 25 +#define CYGNUM_HAL_INTERRUPT_SIO_1 26 + +#define CYGNUM_HAL_PCI_A CYGNUM_HAL_INTERRUPT_1 +#define CYGNUM_HAL_PCI_B CYGNUM_HAL_INTERRUPT_2 +#define CYGNUM_HAL_PCI_C CYGNUM_HAL_INTERRUPT_4 +#define CYGNUM_EXPANSION CYGNUM_HAL_INTERRUPT_3 + + +#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED + +#endif + + + +//-------------------------------------------------------------------------- +// Interrupt controller access +// The default code here simply uses the fields present in the CP0 status +// and cause registers to implement this functionality. +// Beware of nops in this code. They fill delay slots and avoid CP0 hazards +// that might otherwise cause following code to run in the wrong state or +// cause a resource conflict. + +#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED + +#define HAL_INTERRUPT_MASK_CPU( _vector_ ) \ +CYG_MACRO_START \ + asm volatile ( \ + "mfc0 $3,$12\n" \ + "la $2,0x00000400\n" \ + "sllv $2,$2,%0\n" \ + "nor $2,$2,$0\n" \ + "and $3,$3,$2\n" \ + "mtc0 $3,$12\n" \ + "nop; nop; nop\n" \ + : \ + : "r"(_vector_) \ + : "$2", "$3" \ + ); \ +CYG_MACRO_END + +#define HAL_INTERRUPT_UNMASK_CPU( _vector_ ) \ +CYG_MACRO_START \ + asm volatile ( \ + "mfc0 $3,$12\n" \ + "la $2,0x00000400\n" \ + "sllv $2,$2,%0\n" \ + "or $3,$3,$2\n" \ + "mtc0 $3,$12\n" \ + "nop; nop; nop\n" \ + : \ + : "r"(_vector_) \ + : "$2", "$3" \ + ); \ +CYG_MACRO_END + +#define HAL_INTERRUPT_ACKNOWLEDGE_CPU( _vector_ ) \ +CYG_MACRO_START \ + asm volatile ( \ + "mfc0 $3,$13\n" \ + "la $2,0x00000400\n" \ + "sllv $2,$2,%0\n" \ + "nor $2,$2,$0\n" \ + "and $3,$3,$2\n" \ + "mtc0 $3,$13\n" \ + "nop; nop; nop\n" \ + : \ + : "r"(_vector_) \ + : "$2", "$3" \ + ); \ +CYG_MACRO_END + +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) + +#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) + + +externC void cyg_hal_interrupt_mask(cyg_uint32 vector); +externC void cyg_hal_interrupt_unmask(cyg_uint32 vector); +externC void cyg_hal_interrupt_acknowledge(cyg_uint32 vector); + +#define HAL_INTERRUPT_MASK( _vector_ ) \ +CYG_MACRO_START \ + cyg_hal_interrupt_mask ( (_vector_) ); \ +CYG_MACRO_END + +#define HAL_INTERRUPT_UNMASK( _vector_ ) \ + CYG_MACRO_START \ + cyg_hal_interrupt_unmask ( (_vector_) ); \ + CYG_MACRO_END + +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ + CYG_MACRO_START \ + cyg_hal_interrupt_acknowledge ( (_vector_) ); \ + CYG_MACRO_END + +#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED + +#endif + + +#endif /* ifndef CYGONCE_HAL_PLF_INTR_H */ +//-------------------------------------------------------------------------- +// End of plf_intr.h
v2_0/include/plf_intr.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/include/plf_stub.h =================================================================== --- v2_0/include/plf_stub.h (nonexistent) +++ v2_0/include/plf_stub.h (revision 1765) @@ -0,0 +1,108 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tmichals +// Contributors: hmt, jskov, nickg +// Date: 2003-02-13 +// Purpose: Platform HAL stub support for MIPS/IDT79s334a boards. +// Description: +// Usage: #include +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include +#include +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include // CYG_UNUSED_PARAM + +#include // architecture stub support + + + +externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + + + +//---------------------------------------------------------------------------- +// Define serial stuff. +//extern void hal_IDT32334_init_serial( void ); +//extern int hal_IDT32334_get_char( void ); +//extern void hal_IDT32334_put_char( int c ); + +//#define HAL_STUB_PLATFORM_INIT_SERIAL() hal_IDT32334_init_serial() +//#define HAL_STUB_PLATFORM_GET_CHAR() hal_IDT32334_get_char() +//#define HAL_STUB_PLATFORM_PUT_CHAR(c) hal_IDT32334_put_char((c)) +//#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +//#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +//#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. +//#define HAL_STUB_PLATFORM_STUBS_INIT() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Reset. +//#define HAL_STUB_PLATFORM_RESET() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
v2_0/include/plf_stub.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_ram.h =================================================================== --- v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_ram.h (nonexistent) +++ v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_ram.h (revision 1765) @@ -0,0 +1,17 @@ +// eCos memory layout - Thu Mar 16 16:19:05 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include +#include +#endif + +#define CYGMEM_REGION_ram (0x80308000) +#define CYGMEM_REGION_ram_SIZE (0xf78000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x81280000 - (size_t) CYG_LABEL_NAME (__heap1))
v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_ram.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_ram.ldi =================================================================== --- v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_ram.ldi (nonexistent) +++ v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_ram.ldi (revision 1765) @@ -0,0 +1,39 @@ +// eCos memory layout - Mon Apr 03 21:03:12 2000 + +// This is a generated file - do not edit + +#include + +MEMORY +{ + ram : ORIGIN = 0x80308000, LENGTH = 0xf78000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0x80308000, LMA_EQ_VMA) + SECTION_ROMISC (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_init (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_ctors (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_dtors (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_devtab (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_dynamic (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_sdata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_lit8 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_lit4 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_ram.ldi Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_rom.h =================================================================== --- v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_rom.h (nonexistent) +++ v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_rom.h (revision 1765) @@ -0,0 +1,20 @@ +// eCos memory layout - Thu Mar 16 16:47:52 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include +#include +#endif + +#define CYGMEM_REGION_ram (0x80000200) +#define CYGMEM_REGION_ram_SIZE (0x1000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x80200000) +#define CYGMEM_REGION_rom_SIZE (0x800000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x81000200 - (size_t) CYG_LABEL_NAME (__heap1))
v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_rom.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_romram.h =================================================================== --- v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_romram.h (nonexistent) +++ v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_romram.h (revision 1765) @@ -0,0 +1,18 @@ +// eCos memory layout - Thu Mar 16 16:47:52 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include +#include +#endif + +#define CYGMEM_REGION_ram (0x80000200) +#define CYGMEM_REGION_ram_SIZE (0x1000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x81000200 - (size_t) CYG_LABEL_NAME (__heap1))
v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_romram.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_rom.ldi =================================================================== --- v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_rom.ldi (nonexistent) +++ v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_rom.ldi (revision 1765) @@ -0,0 +1,40 @@ +// eCos memory layout - Wed May 10 18:37:59 2000 + +// This is a generated file - do not edit + +#include + +MEMORY +{ + ram : ORIGIN = 0x80000200, LENGTH = 0x1000000 + rom : ORIGIN = 0x80200000, LENGTH = 0x80000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0x80200000, LMA_EQ_VMA) + SECTION_ROMISC (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_RELOCS (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_init (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, 0x80000200, FOLLOWING (.rodata1)) + SECTION_data1 (ram, ALIGN (0x40), FOLLOWING (.data)) + SECTION_eh_frame (ram, ALIGN (0x40), FOLLOWING (.data1)) + SECTION_gcc_except_table (ram, ALIGN (0x40), FOLLOWING (.eh_frame)) + SECTION_ctors (ram, ALIGN (0x40), FOLLOWING (.gcc_except_table)) + SECTION_dtors (ram, ALIGN (0x40), FOLLOWING (.ctors)) + SECTION_devtab (ram, ALIGN (0x40), FOLLOWING (.dtors)) + SECTION_got (ram, ALIGN (0x40), FOLLOWING (.devtab)) + SECTION_dynamic (ram, ALIGN (0x40), FOLLOWING (.got)) + SECTION_sdata (ram, ALIGN (0x40), FOLLOWING (.dynamic)) + SECTION_lit8 (ram, ALIGN (0x40), FOLLOWING (.sdata)) + SECTION_lit4 (ram, ALIGN (0x40), FOLLOWING (.lit8)) + SECTION_sbss (ram, ALIGN (0x40), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x40), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_rom.ldi Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_romram.ldi =================================================================== --- v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_romram.ldi (nonexistent) +++ v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_romram.ldi (revision 1765) @@ -0,0 +1,39 @@ +// eCos memory layout - Wed May 10 18:37:59 2000 + +// This is a generated file - do not edit + +#include + +MEMORY +{ + ram : ORIGIN = 0x80000000, LENGTH = 0x1000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0x80000000, LMA_EQ_VMA) + SECTION_ROMISC (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_init (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x40), LMA_EQ_VMA) + SECTION_data1 (ram, ALIGN (0x40), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x40), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x40), LMA_EQ_VMA) + SECTION_ctors (ram, ALIGN (0x40), LMA_EQ_VMA) + SECTION_dtors (ram, ALIGN (0x40), LMA_EQ_VMA) + SECTION_devtab (ram, ALIGN (0x40), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x40), LMA_EQ_VMA) + SECTION_dynamic (ram, ALIGN (0x40), LMA_EQ_VMA) + SECTION_sdata (ram, ALIGN (0x40), LMA_EQ_VMA) + SECTION_lit8 (ram, ALIGN (0x40), LMA_EQ_VMA) + SECTION_lit4 (ram, ALIGN (0x40), LMA_EQ_VMA) + SECTION_sbss (ram, ALIGN (0x40), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x40), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
v2_0/include/pkgconf/mlt_mips_idt32334_refidt334_romram.ldi Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/include/plf_cache.h =================================================================== --- v2_0/include/plf_cache.h (nonexistent) +++ v2_0/include/plf_cache.h (revision 1765) @@ -0,0 +1,66 @@ +#ifndef CYGONCE_PLF_CACHE_H +#define CYGONCE_PLF_CACHE_H + +//============================================================================= +// +// plf_cache.h +// +// HAL cache control API +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tmichals +// Contributors: +// Date: 2003-02-13 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + + +// Nothing here at present. + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PLF_CACHE_H +// End of plf_cache.h
v2_0/include/plf_cache.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/include/idt79rc233x.h =================================================================== --- v2_0/include/idt79rc233x.h (nonexistent) +++ v2_0/include/idt79rc233x.h (revision 1765) @@ -0,0 +1,573 @@ +#ifndef CYGONCE_HAL_IDT79RC233X_H +#define CYGONCE_HAL_IDT79RC233X_H +//========================================================================== +// +// idt79rc233x.h +// +// IDT 79RC233x platform definitions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Tim Michals +// Contributors: nickg +// Date: 2003-02-13 +// Purpose: IDT 79RC233x platform definitions +// Description: +// Usage: +//####DESCRIPTIONEND#### +//========================================================================== + +#define K0BASE 0x80000000 +#define K0SIZE 0x20000000 +#define K1BASE 0xA0000000 +#define K1SIZE 0x20000000 +#define K2BASE 0xC0000000 +#define K2SIZE 0x40000000 + +/* +* Exception vectors +*/ + +#define T_VEC K0BASE /* tlbmiss vector */ +#define C_VEC (K1BASE+0x100) /* cache exception vector */ +#define E_VEC (K0BASE+0x180) /* exception vector */ +#define R_VEC (K1BASE+0x1fc00000) /* reset vector */ + +/* + * Address conversion macros + */ + +#define K0_TO_K1(x) ((unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */ +#define K1_TO_K0(x) ((unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */ +#define K0_TO_PHYS(x) ((unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */ +#define K1_TO_PHYS(x) ((unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */ +#define PHYS_TO_K0(x) ((unsigned)(x)|0x80000000) /* physical to kseg0 */ +#define PHYS_TO_K1(x) ((unsigned)(x)|0xA0000000) /* physical to kseg1 */ + +/* +* Address predicates +*/ + +#define IS_KSEG0(x) ((unsigned)(x) >= K0BASE && (unsigned)(x) < K1BASE) +#define IS_KSEG1(x) ((unsigned)(x) >= K1BASE && (unsigned)(x) < K2BASE) +#define IS_KUSEG(x) ((unsigned)(x) < K0BASE) + +/* +* Cache size constants +*/ + +#define MINCACHE +(1*1024) /* leading plus for mas's benefit */ +#define MAXCACHE +(256*1024) /* leading plus for mas's benefit */ + +/* +* Cache alignment macros +* +* NOTE: These definitions may migrate to vxWorks.h in a future release. +*/ + +#define CACHE_ROUND_UP(x) ROUND_UP(x, _CACHE_ALIGN_SIZE) +#define CACHE_ROUND_DOWN(x) ROUND_DOWN(x, _CACHE_ALIGN_SIZE) + +/* +* Cause bit definitions +*/ + +#define CAUSE_BD 0x80000000 /* Branch delay slot */ +#define CAUSE_CEMASK 0x30000000 /* coprocessor error */ +#define CAUSE_CESHIFT 28 + +#define CAUSE_IP8 0x00008000 /* External level 8 pending */ +#define CAUSE_IP7 0x00004000 /* External level 7 pending */ +#define CAUSE_IP6 0x00002000 /* External level 6 pending */ +#define CAUSE_IP5 0x00001000 /* External level 5 pending */ +#define CAUSE_IP4 0x00000800 /* External level 4 pending */ +#define CAUSE_IP3 0x00000400 /* External level 3 pending */ +#define CAUSE_SW2 0x00000200 /* Software level 2 pending */ +#define CAUSE_SW1 0x00000100 /* Software level 1 pending */ + +#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */ +#define CAUSE_IPSHIFT 8 + +#define CAUSE_EXCMASK 0x0000007C /* Cause code bits */ +#define CAUSE_EXCSHIFT 2 + +/* +* Status definition bits +*/ + +#define SR_CUMASK 0xf0000000 /* coproc usable bits */ +#define SR_CU3 0x80000000 /* Coprocessor 3 usable */ +#define SR_CU2 0x40000000 /* Coprocessor 2 usable */ +#define SR_CU1 0x20000000 /* Coprocessor 1 usable */ +#define SR_CU0 0x10000000 /* Coprocessor 0 usable */ +#define SR_NBL 0x08000000 /* Enables Non Blocking Load */ +#define SR_RE 0x02000000 /* Reverse endian in user mode */ +#define SR_DL 0x01000000 /* Data Cache Lock Enable */ +#define SR_IL 0x00800000 /* Instruction Cache Lock Enable */ + +#define SR_BEV 0x00400000 /* use boot exception vectors */ +#define SR_SR 0x00100000 /* soft reset occurred */ +#define SR_CE 0x00020000 /* use ECC reg */ +#define SR_DE 0x00010000 /* disable cache errors */ +#define SR_IMASK 0x0000ff00 /* Interrupt mask */ +#define SR_IMASK8 0x00000000 /* mask level 8 */ +#define SR_IMASK7 0x00008000 /* mask level 7 */ +#define SR_IMASK6 0x0000c000 /* mask level 6 */ +#define SR_IMASK5 0x0000e000 /* mask level 5 */ +#define SR_IMASK4 0x0000f000 /* mask level 4 */ +#define SR_IMASK3 0x0000f800 /* mask level 3 */ +#define SR_IMASK2 0x0000fc00 /* mask level 2 */ +#define SR_IMASK1 0x0000fe00 /* mask level 1 */ +#define SR_IMASK0 0x0000ff00 /* mask level 0 */ + +#define SR_IBIT8 0x00008000 /* bit level 8 */ +#define SR_IBIT7 0x00004000 /* bit level 7 */ +#define SR_IBIT6 0x00002000 /* bit level 6 */ +#define SR_IBIT5 0x00001000 /* bit level 5 */ +#define SR_IBIT4 0x00000800 /* bit level 4 */ +#define SR_IBIT3 0x00000400 /* bit level 3 */ +#define SR_IBIT2 0x00000200 /* bit level 2 */ +#define SR_IBIT1 0x00000100 /* bit level 1 */ + +#define SR_KSU_K 0x00000000 /* kernel mode */ +#define SR_KSU_U 0x00000010 /* user mode */ +#define SR_ERL 0x00000004 /* Error Level */ +#define SR_EXL 0x00000002 /* Exception Level */ +#define SR_IE 0x00000001 /* interrupt enable, 1 => enable */ + +#define SR_IMASKSHIFT 8 + +/* +* tlb definitions +*/ + +#define TLB_ENTRIES 16 +#define TLBLO_PFNMASK 0x03ffffc0 +#define TLBLO_PFNSHIFT 6 +#define TLBLO_CMASK 0x00000038 +#define TLBLO_NC 0x00000010 /* uncached */ +#define TLBLO_NONC 0x00000018 /* cacheable non-coherent */ +#define TLBLO_D 0x4 /* writeable */ +#define TLBLO_V 0x2 /* valid bit */ +#define TLBLO_G 0x1 /* global bit */ + +#define TLBHI_VPN2MASK 0xffffe000 +#define TLBHI_VPN2SHIFT 13 +#define TLBHI_PIDMASK 0xff +#define TLBHI_PIDSHIFT 0 +#define TLBHI_NPID 256 +#define TLBINX_PROBE 0x80000000 +#define TLBINX_INXMASK 0x0000003f +#define TLBINX_INXSHIFT 0 +#define TLBRAND_RANDMASK 0x0000000f +#define TLBRAND_RANDSHIFT 0 +#define TLBCTXT_BASEMASK 0xff800000 +#define TLBCTXT_BASESHIFT 23 +#define TLBCTXT_VPN2MASK 0x007ffff0 +#define TLBCTXT_VPN2SHIFT 4 + +/* + * RC32364 Config Register + */ +#define CFG_ICE 0x80000000 /* In Circuit Emulator existence */ +#define CFG_ECMASK 0x70000000 /* System Clock Ratio */ +#define CFG_ECBY2 0x00000000 /* divide by 2 */ +#define CFG_ECBY3 0x10000000 /* divide by 3 */ +#define CFG_ECBY4 0x20000000 /* divide by 4 */ +#define CFG_NBL 0x00800000 /* Non Blocking load */ +#define CFG_BE 0x00008000 /* Big Endian */ +#define CFG_ICMASK 0x00000e00 /* Instruction cache size */ +#define CFG_ICSHIFT 9 +#define CFG_DCMASK 0x000001c0 /* Data cache size */ +#define CFG_DCSHIFT 6 +#define CFG_IB 0x00000020 /* Instruction cache block size */ +#define CFG_DB 0x00000010 /* Data cache block size */ +#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */ + +/* + * Primary cache mode + */ +#define CFG_C_UNCACHED 2 +#define CFG_C_NONCOHERENT 3 + +/* + * Primary Cache TagLo + */ +#define TAG_PTAG_MASK 0x7fffff00 /* Primary Tag */ +#define TAG_PTAG_SHIFT 0x00000008 +#define TAG_PSTATE_MASK 0x000000c0 /* Primary Cache State */ +#define TAG_PSTATE_SHIFT 0x00000006 +#define TAG_LOCK_BIT 0x00000004 /* Cache line lock bit */ +#define TAG_LOCK_BIT_SHIFT 0x00000002 +#define TAG_FIFO_REFILL 0x00000002 /* Fifo refill */ +#define TAG_FIFO_REFILL_SHIFT 0x00000001 +#define TAG_PARITY_MASK 0x00000001 /* Primary Tag Parity */ +#define TAG_PARITY_SHIFT 0x00000000 + + + +/* + * CacheErr register + */ +#define CACHEERR_TYPE 0x80000000 /* reference type: + 0=Instr, 1=Data */ +#define CACHEERR_LEVEL 0x40000000 /* cache level: + 0=Primary, 1=reserved */ +#define CACHEERR_DATA 0x20000000 /* data field: + 0=No error, 1=Error */ +#define CACHEERR_TAG 0x10000000 /* tag field: + 0=No error, 1=Error */ +#define CACHEERR_BOTH 0x02000000 /* Data & Instruction error: + 0=No, 1=Yes */ +#define CACHEERR_SIDX_MASK 0x003ffff8 /* PADDR(21..3) */ +#define CACHEERR_SIDX_SHIFT 3 +#define CACHEERR_PIDX_MASK 0x00000003 /* VADDR(13..12) */ +#define CACHEERR_PIDX_SHIFT 12 + + +/* + * Cache operations + */ +#define Index_Invalidate_I 0x0 /* 0 0 */ +#define Index_Writeback_Inv_D 0x1 /* 0 1 */ +#define Index_Load_Tag_I 0x4 /* 1 0 */ +#define Index_Load_Tag_D 0x5 /* 1 1 */ +#define Index_Store_Tag_I 0x8 /* 2 0 */ +#define Index_Store_Tag_D 0x9 /* 2 1 */ +#define Create_Dirty_Exc_D 0xD /* 3 1 */ +#define Hit_Invalidate_I 0x10 /* 4 0 */ +#define Hit_Invalidate_D 0x11 /* 4 1 */ +#define Hit_Writeback_Inv_D 0x15 /* 5 1 */ +#define Fill_I 0x14 /* 5 0 */ +#define Hit_Writeback_D 0x19 /* 6 1 */ +#define Hit_Writeback_I 0x18 /* 6 0 */ + +/* +* Coprocessor 0 operations +*/ + +#define C0_READI 0x1 /* read ITLB entry addressed by C0_INDEX */ +#define C0_WRITEI 0x2 /* write ITLB entry addressed by C0_INDEX */ +#define C0_WRITER 0x6 /* write ITLB entry addressed by C0_RAND */ +#define C0_PROBE 0x8 /* probe for ITLB entry addressed by TLBHI */ +#define C0_ERET 0x18 /* restore for exception */ +#define FP_EXC_MASK (FP_EXC_I|FP_EXC_U|FP_EXC_O|FP_EXC_Z|FP_EXC_V|FP_EXC_E) +#define FP_EXC_I 0x1000 /* inexact operation */ +#define FP_EXC_U 0x2000 /* underflow */ +#define FP_EXC_O 0x4000 /* overflow */ +#define FP_EXC_Z 0x8000 /* divide by zero */ +#define FP_EXC_V 0x10000 /* invalid operation */ +#define FP_EXC_E 0x20000 /* unimplemented operation */ + + +#define C0_INX $0 /* Index into TLB Array - 4Kc core */ +#define C0_RANDOM $1 /* Randomly generated index into TLB Array - 4Kc core */ +#define C0_TLBLO0 $2 /* Low-order portion of the TLB entry for even-numbered virtual pages - 4Kc core */ +#define C0_TLBLO1 $3 /* Low-order portion of the TLB entry for odd-numbered virtual pages - 4Kc core */ +#define C0_PAGEMASK $5 /* Pointer to page table entry in memory - 4Kc core */ +#define C0_WIRED $6 /* Number of fixed TLB entries - 4Kc core */ +#define C0_TLBHI $10 /* High-order portion of the TLB entry - 4Kc core */ +#define C0_PRId $15 /* Processor Identification and Revision */ +#define C0_CONFIG $16 /* Configuration Register */ +#define C0_LLADDR $17 /* Load linked address */ +#define C0_LLADDR $17 /* Load linked address */ +#define C0_DEBUG $23 /* Debug control and exception status */ +#define C0_DEPC $24 /* Program counter at last debug exception */ +#define C0_TAGLO $28 /* Low-order portion of cache tag interface */ +#define C0_TAGHI $29 /* High-order portion of cache tag interface (not implemented in 4K cores */ +#define C0_DESAVE $31 /* Debug handler scratch pad register */ + + + + +#define TARGET_S334 +#define BUS 0 + +#define PORT_WIDTH_CNTL_REG 0xffffe200 +#define BUS_TURN_AROUND_REG 0xffffe204 +#define BUS_TURN_AROUND_CNTRL_REG 0xb8000000 +#define BUS_TURN_AROUND_VAL 0x00000000 + +#define ADDRESS_LATCH_TIMING_REG 0xB8000004 +#define ADDRESS_LATCH_TIMING_VAL 0x00000007 + +#define PORT_WIDTH_CNTL_VAL 0xaa822aaa +#define SDRAM_TEST_PATTERN 0xaa55aa55 + +/* RC32134 Register Settings */ +#define MEM_BASE_BASE 0xb8000080 +#define MBA_REG0 0x1fc00000 +#define MBM_REG0 0xffC00000 + + +#define MEM_CTL_BASE 0xb8000200 +#define MCR_CS0_BS 0x23ef23ef +#define MCR_CS1_BS 0x28632863 +#define MCR_CS2_BS 0x60e760e7 +#define MCR_CS3_BS 0x60e760e7 /* NVRAM */ +#define MCR_CS4_BS 0x60e760e7 /* S334 LED */ +#define MCR_CS5_BS 0x60e760e7 + + +#define RHEA_IREG_BASE 0xb8000000 +#define SODIMM 1 + +#define DRAM_BNK0_BASE 0x00000000 +#define DRAM_BNK1_BASE 0x01000000 +#define DRAM_BNK2_BASE 0x02000000 +#define DRAM_BNK3_BASE 0x03000000 +#define DRAM_BNK0_MASK 0xff000000 +#define DRAM_BNK1_MASK 0xff000000 +#define DRAM_BNK2_MASK 0xff000000 +#define DRAM_BNK3_MASK 0xff000000 +#define MBA_REG1 0x04000000 +#define MBM_REG1 0xffff0000 +#define SDRAM_CR_BS 0x8955c0ff +#define SDRAM_PC_VAL 0x8955c0a0 +#define SDRAM_RFRSH_CMD 0x8955c090 +#define SDRAM_MODE_REG 0x8955c080 +#define SDRAM_CSEL_PARK 0x8955c0ff +#define TIMER_BASE 0xb8000700 +#define DRAM_RF_CMPR_BS 0x00000040 +#define DRAM_RF_CMPR_SE_BS 0x00000200 +#define CPU_BERR_BS 0xff +#define IP_BERR_BS 0xff +#define DISABLE_TIMER 0x0 +#define ENABLE_TIMER 0x1 + +#define CPU_CLOCK_RATE 75000000 + + +/* define macro so drivers will call sysWbFlush() */ + +#define SYS_WB_FLUSH + +/* task default status register */ + +#define INT_LVL_PCI INT_LVL_IORQ1 +#define INT_LVL_SR_IMASK (INT_LVL_PCI | INT_LVL_IORQ3 |\ + INT_LVL_SW0 | INT_LVL_SW1 ) + +#define RC32364_SR (SR_CU0| INT_LVL_SR_IMASK |\ + INT_LVL_TIMER | SR_IE) + +/* interrupt priority */ + +#define INT_PRIO_MSB TRUE /* interrupt priority msb highest */ + + + + +/* Miscellaneous */ + +#define PIO_DATA_REG0 0xb8000600 +#define PIO_FUNC_SELECT_REG0 0xb8000608 +#define PIO_DATA_REG1 0xb8000610 +#define PIO_DIRCNTL_REG1 0xb8000614 +#define PIO_FUNC_SELECT_REG1 0xb8000618 +#define CYG_MGMT_LED_MASK 0x00000008 +#define CYG_STATUS_LED_MASK 0x00000003 +#define CYG_TEST_LED1_MASK 0x00000002 +#define CYG_TEST_LED2_MASK 0x00000004 +#define CYG_STATUS_LED_GREEN 0x00000001 +#define CYG_STATUS_LED_ORANGE 0x00000002 + + + + +/* PIO definition for Internal Uart */ + +#define PIO_DIRCNTL_REG 0xb8000604 +#define PIO_FUNCSEL_MASK 0xf0 +#define PIO_DIRCNTL_MASK 0xffffff0f +#define PIO_DIRCNTL_VAL 0x50 + + +/* Serial grouping */ + +#define SERIAL_PORT0_GROUP 5 +#define SERIAL_PORT1_GROUP 6 + +/* Rc32134 Interrupt controller settings for Uart */ +#define INTR_STATUS_PTR 0xb8000500 +#define INTR_MASK_REG 0xb8000504 + +#define INTR_COM0_REG 0xb8000554 +#define INTR_COM1_REG 0xb8000564 + +#define INTR_CLEAR_COM0 0xb8000558 +#define INTR_PEND_COM0 0xb8000550 +#define INTR_CLEAR_COM1 0xb8000568 +#define INTR_PEND_COM1 0xb8000560 + +#define INTR_CLEAR_MASTER 0xb8000508 +#define INTR_PEND_MASTER 0xb8000500 + +#define INTR_MASTERMASK_COM1 0x0020 +#define INTR_MASTERMASK_COM2 0x0040 +#define INTR_MASTERMASK_UART ( INTR_MASTERMASK_COM1 | INTR_MASTERMASK_COM2 ) + +/* Rc32134 Timer0(used as Auxiliary clock)interrupts */ +#define AUX_TIMER_INTR_PEND 0xb8000540 +#define AUX_TIMER_INTR_MASK 0xb8000544 +#define AUX_TIMER_INTR_CLEAR 0xb8000548 +#define INTR_MASTERMASK_TIMER0 0x0010 +#define AUX_TIMER_CNTL_REG 0xb8000700 +#define AUX_TIMER_CNT_REG 0xb8000704 +#define AUX_TIMER_CMP_REG 0xb8000708 + +#define AUX_CLOCK_FREQ (2 * NS16550_XTAL_FREQ) + +/* Rc32364 Tlb attributes for PCI transactions */ +#define PCI_MMU_PAGEMASK 0x00000fff +#define MMU_PAGE_UNCACHED 0x00000010 +#define MMU_PAGE_DIRTY 0x00000004 +#define MMU_PAGE_VALID 0x00000002 +#define MMU_PAGE_GLOBAL 0x00000001 +#define PCI_MMU_PAGEATTRIB (MMU_PAGE_UNCACHED|MMU_PAGE_DIRTY|\ + MMU_PAGE_VALID|MMU_PAGE_GLOBAL) +#define PCI_MEMORY_SPACE1 0x40000000 +#define PCI_MEMORY_SPACE2 0x60000000 +#define PCI_IO_SPACE 0x18000000 +#define PCI_PAGE_SIZE 0x01000000 +#define TLB_HI_MASK 0xffffe000 +#define TLB_LO_MASK 0x3fffffff +#define PAGEMASK_SHIFT 13 +#define TLB_LO_SHIFT 6 + + +/* RC32134 PCI definitions */ +#define PCI_CONFIG_ADDR_REG 0xb8002cf8 +#define PCI_CONFIG_DATA_REG 0xb8002cfc + +/* Rhea's Configuration Address*/ + +#define RHEA_CONFIG0_ADDR 0x80000000 +#define RHEA_CONFIG1_ADDR 0x80000004 +#define RHEA_CONFIG2_ADDR 0x80000008 +#define RHEA_CONFIG3_ADDR 0x8000000c +#define RHEA_CONFIG4_ADDR 0x80000010 +#define RHEA_CONFIG5_ADDR 0x80000014 +#define RHEA_CONFIG6_ADDR 0x80000018 +#define RHEA_CONFIG7_ADDR 0x8000001c +#define RHEA_CONFIG8_ADDR 0x80000020 +#define RHEA_CONFIG9_ADDR 0x80000024 +#define RHEA_CONFIG10_ADDR 0x80000028 +#define RHEA_CONFIG11_ADDR 0x8000002c +#define RHEA_CONFIG12_ADDR 0x80000030 +#define RHEA_CONFIG13_ADDR 0x80000034 +#define RHEA_CONFIG14_ADDR 0x80000038 +#define RHEA_CONFIG15_ADDR 0x8000003c +#define RHEA_CONFIG16_ADDR 0x80000040 + +/* Rhea's configuration Header */ + +#define RHEA_PCI_CONFIG0 0x032410b5 /* Device ID & Vendor ID */ +#define RHEA_PCI_CONFIG1 0x02a00157 /* Status & Command */ +#define RHEA_PCI_CONFIG2 0x06800001 /* Class Code & Revision ID */ +#define RHEA_PCI_CONFIG3 0x0000ff04 /* BIST, Header Type, Latency, & Cacheline Size */ +#define RHEA_PCI_CONFIG4 0xa0000000 /* PCI Memory Address that Rhea responds to. */ +#define RHEA_PCI_CONFIG5 0x60000000 /* PCI Dual Cycle Address that Rhea responds to.*/ +#define RHEA_PCI_CONFIG6 0x00800001 /* PCI I/O Address that Rhea responds to. */ +#define RHEA_PCI_CONFIG7 0x00000000 +#define RHEA_PCI_CONFIG8 0x00000000 +#define RHEA_PCI_CONFIG9 0x00000000 +#define RHEA_PCI_CONFIG10 0x00000000 +#define RHEA_PCI_CONFIG11 0x013410b5 +#define RHEA_PCI_CONFIG12 0x00000000 +#define RHEA_PCI_CONFIG13 0x00000000 +#define RHEA_PCI_CONFIG14 0x00000000 +#define RHEA_PCI_CONFIG15 0x38080101 + +/* Because of an errata in Rc32134 Pci Bridge, Scanning does not work properly. + The device number is selected based on which pci slot on S134 board is being + used */ + +#define PCI_BUS 0 +#define PCI_DEVICE_U28 2 /* PCI Slot U28 */ +#define PCI_DEVICE_U29 3 /* PCI Slot U29 */ +#define PCI_DEVICE_U20 4 /* PCI Slot U20 */ +#define PCI_FUNC 0 + +/* Latency for the Pci/Ethernet Card */ + +#define PCI_DEVICE_MAX_LATENCY 0x0000ff00 +/* BusErrCntReg is used to disable/Enable BusError thrown on PCI + bus on scanning */ +#define BUS_ERR_CNTL_REG_ADDR 0xb8000010 + + + + +/* FEI PCI bus resources */ + +#define FEI_IO_MAP_USE +#define FEI_OFFSET_ADD +#define FEI0_MEMBASE0 0x40800000 /* memory base for CSR */ +#define FEI0_MEMSIZE0 0x00001000 /* memory size for CSR, 4KB */ +#define FEI0_MEMBASE1 0x40a00000 /* memory base for Flash */ +#define FEI0_MEMSIZE1 0x00100000 /* memory size for Flash, 1MB */ +#define FEI0_IOBASE0 0x18800000 /* IO base for CSR, 32Bytes */ +#define FEI0_INT_LVL 0x1 /* IRQ 1 */ + +#define PCI_CFG_TYPE PCI_CFG_FORCE + +/* Redefine PCI_CONFIG_ADDR & PCI_CONFIG_DATA */ + +#define CPU_TO_PCI_MEM_BASE 0x40000001 +#define CPU_TO_PCI_IO_BASE 0x18800001 +#define PCI_TO_CPU_MEM_BASE 0x00000000 +#define PCI_TO_CPU_IO_BASE 0x00800001 + +#define IDT134_PCI_BASE 0xb8000000 + +#define IDT134_PCI_MEM_BAR1 (IDT134_PCI_BASE + 0x20B0) +#define IDT134_PCI_MEM_BAR2 (IDT134_PCI_BASE + 0x20B8) +#define IDT134_PCI_MEM_BAR3 (IDT134_PCI_BASE + 0x20C0) +#define IDT134_PCI_IO_BAR (IDT134_PCI_BASE + 0x20C8) +#define IDT134_PCI_ARB_REG (IDT134_PCI_BASE + 0x20E0) +#define IDT134_PCI_CPU_BAR1 (IDT134_PCI_BASE + 0x20E8) +#define IDT134_PCI_CPU_IO_BAR (IDT134_PCI_BASE + 0x2100) +#define IDT134_PCI_CONFIG_ADDR (IDT134_PCI_BASE + 0x2CF8) +#define IDT134_PCI_CONFIG_DATA (IDT134_PCI_BASE + 0x2CFC) + +#define IDT134_BAR_MEM_SWAP 0x00000001 + + +#endif /* CYGONCE_HAL_IDT79RC233X_H */ +/*---------------------------------------------------------------------------*/ +/* end of idt79rc233x.h */
v2_0/include/idt79rc233x.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/include/platform.inc =================================================================== --- v2_0/include/platform.inc (nonexistent) +++ v2_0/include/platform.inc (revision 1765) @@ -0,0 +1,181 @@ +#ifndef CYGONCE_HAL_PLATFORM_INC +#define CYGONCE_HAL_PLATFORM_INC +##============================================================================= +## +## platform.inc +## +## REFIDT334 board assembler header file +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): tmichals +## Contributors: nickg +## Date: 2003-02-13 +## Purpose: CT1608-IDT32334 board definitions. +## Description: This file contains various definitions and macros that are +## useful for writing assembly code for the IDT32334 reference +## board. +## Usage: +## #include +## ... +## +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include + +#------------------------------------------------------------------------------ +# Monitor initialization. + +#ifndef CYGPKG_HAL_MIPS_MON_DEFINED + +#if defined(CYG_HAL_STARTUP_ROM) || \ + ( defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR)) + + # If we are starting up from ROM, or we are starting in + # RAM and NOT using a ROM monitor, initialize the VSR table. + + .macro hal_mon_init + la a0,__default_interrupt_vsr + la a1,__default_exception_vsr + la a3,hal_vsr_table + sw a0,0(a3) + sw a1,1*4(a3) + sw a1,2*4(a3) + sw a1,3*4(a3) + sw a1,4*4(a3) + sw a1,5*4(a3) + sw a1,6*4(a3) + sw a1,7*4(a3) + sw a1,8*4(a3) + sw a1,9*4(a3) + sw a1,10*4(a3) + sw a1,11*4(a3) + sw a1,12*4(a3) + sw a1,13*4(a3) + sw a1,14*4(a3) + sw a1,15*4(a3) + + sw a1,32*4(a3) + sw a1,33*4(a3) + .endm + +#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR) + + # Initialize the VSR table entries + # We only take control of the interrupt vector, + # the rest are left to the ROM for now... + + .macro hal_mon_init + la a0,__default_interrupt_vsr + la a3,hal_vsr_table + sw a0,0(a3) + .endm + +#else + + .macro hal_mon_init + .endm + +#endif + + +#define CYGPKG_HAL_MIPS_MON_DEFINED + +#endif + +#------------------------------------------------------------------------------ +# Decide whether the VSR table is defined externally, or is to be defined +# here. + +#if defined(CYGPKG_HAL_MIPS_SIM) || \ + ( defined(CYGPKG_HAL_MIPS_TX3904) && \ + defined(CYG_HAL_STARTUP_RAM) && \ + !defined(CYGSEM_HAL_USE_ROM_MONITOR) \ + ) + +## VSR table defined in linker script + +#else + +#define CYG_HAL_MIPS_VSR_TABLE_DEFINED + +#endif + +#if defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_ROM) +#ifndef CYGPKG_HAL_MIPS_MEMC_DEFINED + +.macro hal_memc_init + .extern hal_memc_setup + lar t0,hal_memc_setup + jalr t0 + nop +#if defined(CYG_HAL_STARTUP_ROMRAM) + + + # Having got the RAM working, we must now relocate the Entire + # ROM into it and then continue execution from RAM. + + la t0,0x80000000 # dest addr + la t1,0xbfc00000 # source addr + la t3,__ram_data_end # end dest addr +1: + lw v0,0(t1) # get word + addi t1,t1,4 + sw v0,0(t0) # write word + addi t0,t0,4 + bne t0,t3,1b + nop + + + la v0,2f # RAM address to go to + jr v0 + nop +2: + # We are now executing out of RAM! +#endif + +.endm +#define CYGPKG_HAL_MIPS_MEMC_DEFINED +#endif +#endif +#------------------------------------------------------------------------------ +#endif // ifndef CYGONCE_HAL_PLATFORM_INC +# end of platform.inc
v2_0/include/platform.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/include/hal_diag.h =================================================================== --- v2_0/include/hal_diag.h (nonexistent) +++ v2_0/include/hal_diag.h (revision 1765) @@ -0,0 +1,88 @@ +#ifndef CYGONCE_HAL_HAL_DIAG_H +#define CYGONCE_HAL_HAL_DIAG_H + +/*============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Tim Michals +// Contributors: nickg +// Date: 2003-02-13 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include +//####DESCRIPTIONEND#### +//========================================================================*/ + +#include + +#include + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#include + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#else // everything by steam + +/*---------------------------------------------------------------------------*/ +/* functions implemented in hal_diag.c */ + +externC void hal_diag_init(void); +externC void hal_diag_write_char(char c); +externC void hal_diag_read_char(char *c); + +/*---------------------------------------------------------------------------*/ + +#define HAL_DIAG_INIT() hal_diag_init() + +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) + +#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +#endif /* CYGONCE_HAL_DIAG_H */ +/*---------------------------------------------------------------------------*/ +/* end of hal_diag.h */
v2_0/include/hal_diag.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/include/plf_io.h =================================================================== --- v2_0/include/plf_io.h (nonexistent) +++ v2_0/include/plf_io.h (revision 1765) @@ -0,0 +1,136 @@ +#ifndef CYGONCE_PLF_IO_H +#define CYGONCE_PLF_IO_H + +//============================================================================= +// +// plf_io.h +// +// Platform specific IO support +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tmichals +// Contributors: hmt, jskov, nickg +// Date: 2003-02-13 +// Purpose: IDT79s334a platform IO support +// Description: +// Usage: #include +// +//####DESCRIPTIONEND#### +// +//============================================================================= +#include +#include +#include +#include + +//----------------------------------------------------------------------------- + +__externC void cyg_plf_pci_init(void); + +// Initialization of the PCI bus. +#define HAL_PCI_INIT() hal_rc334PciInit() + + +// Map PCI device resources starting from these addresses in PCI space. +#define HAL_PCI_ALLOC_BASE_MEMORY 0x00100000 +#define HAL_PCI_ALLOC_BASE_IO 0x18800000 + +// This is where the PCI spaces are mapped in the CPU's address space. +#define HAL_PCI_PHYSICAL_MEMORY_BASE 0xA0000000 +#define HAL_PCI_PHYSICAL_IO_BASE 0xA0000000 + + + +#define PCI_MEM_BASE 0x40000000 // 512M to xxx +#define PCI_IO_BASE 0x18000000 // 16M to xxx +#define PCI_CONFIG_BASE 0x60000000 // 16M to xxx + + + +// Read a value from the PCI configuration space of the appropriate +// size at an address composed from the bus, devfn and offset. +#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \ + __val = ecosPciConfigInByte(__bus, __devfn, __offset) + + + +#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \ + __val = ecosPciConfigInHalfWord(__bus, __devfn, __offset) + +#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \ + __val = ecosPciConfigInWord(__bus, __devfn, __offset) + +// Write a value to the PCI configuration space of the appropriate +// size at an address composed from the bus, devfn and offset. +#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \ + __val =ecosPciConfigOutChar(__bus, __devfn, __offset) + +#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \ + ecosPciConfigOutHalfWord(__bus, __devfn, __offset, __val) + +#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \ + ecosPciConfigOutWord(__bus, __devfn, __offset, __val) + + + +// Translate the PCI interrupt requested by the device (INTA#, INTB#, +// INTC# ) to the associated CPU interrupt (i.e., HAL vector). +#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \ + CYG_MACRO_START \ + cyg_uint8 __req; \ + HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \ + if (0 != __req) { \ + /* Slot D is not used, assigned the RTC to INT 5 Sorry! */\ + CYG_ADDRWORD __translation[4] = { \ + 0 , \ + CYGNUM_HAL_PCI_A , /* INTB# */ \ + CYGNUM_HAL_PCI_B , /* INTA# */ \ + CYGNUM_HAL_PCI_C , /* INTA# */ \ + }; /* D is NOT used */ \ + \ + __vec = __translation[((__req+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \ + __valid = true; \ + } else { \ + /* Device will not generate interrupt requests. */ \ + __valid = false; \ + } \ + CYG_MACRO_END + + +// end of plf_io.h +#endif // CYGONCE_PLF_IO_H
v2_0/include/plf_io.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/ChangeLog =================================================================== --- v2_0/ChangeLog (nonexistent) +++ v2_0/ChangeLog (revision 1765) @@ -0,0 +1,39 @@ +2003-02-13 Tim Michals +2003-02-13 Jonathan Larmour + + * New package - support for MIPS IDT 79s334a board. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== Index: v2_0/src/plf_stub.c =================================================================== --- v2_0/src/plf_stub.c (nonexistent) +++ v2_0/src/plf_stub.c (revision 1765) @@ -0,0 +1,170 @@ +//============================================================================= +// +// plf_stub.c +// +// Platform specific code for GDB stub support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, jskov (based on the old tx39 hal_stub.c) +// Contributors:tmichals +// Date: 1999-02-12 +// Purpose: Platform specific code for GDB stub support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= +#include +#include + +#include CYGBLD_HAL_PLATFORM_H +#include // Cache handling +#include // Base types +#include // tracing macros +#include // assertion macros +#include // architectural definitions +#include // Interrupt handling +#include // Cache handling + +#include // HAL IO macros +#include // diag output. FIXME +#include +#include +#include + + + +#define PIO_DIRCNTL_REG 0xb8000604 + +void hal_IDT32334_init_serial_baud( int baud ) +{ + cyg_uint16 baud_divisor; + cyg_uint8 _lcr, _ier; + cyg_addrword_t port = CMA_SER_16550_BASE_A; + cyg_uint32 status; + + + HAL_READ_UINT32 ( PIO_DIRCNTL_REG+4, status); + status |= 0xf0; + HAL_WRITE_UINT32 ( PIO_DIRCNTL_REG+4, status); + + + HAL_READ_UINT32 (PIO_DIRCNTL_REG, status); + status &= 0xffffff0f; + status |= 0x50; + HAL_WRITE_UINT32(PIO_DIRCNTL_REG, status); + + baud_divisor = (CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL) / (16 * baud); + + + // Set databits, stopbits and parity. + _lcr = LCR_WL8 | LCR_SB1 | LCR_PN; + + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + + // Set baud rate. + _lcr |= LCR_DL; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + HAL_WRITE_UINT8(port+SER_16550_DLM, baud_divisor >> 8); + HAL_WRITE_UINT8(port+SER_16550_DLL, baud_divisor & 0xff); + _lcr &= ~LCR_DL; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + + HAL_WRITE_UINT8(port+SER_16550_FCR, 0x1); + + HAL_WRITE_UINT8(port+SER_16550_MSR, 0x30); + + + +} + + +#ifndef CYGNUM_IO_SERIAL_IDT32334_SERIAL0_BAUD +# define CYGNUM_IO_SERIAL_IDT32334_SERIAL0_BAUD 115200 +#endif + +// Initialize the current serial port. +void hal_IDT32334_init_serial( void ) +{ + hal_IDT32334_init_serial_baud( CYGNUM_IO_SERIAL_IDT32334_SERIAL0_BAUD); +} + +// Write C to the current serial port. +void hal_IDT32334_put_char( int c ) +{ + cyg_uint8 _lsr; + cyg_addrword_t port =CMA_SER_16550_BASE_A; + + do + { + HAL_READ_UINT8(port+SER_16550_LSR, _lsr); + }while ( !(_lsr & SIO_LSR_THRE) && (_lsr)); + + if ((_lsr & SIO_LSR_THRE) || (!_lsr)) + HAL_WRITE_UINT8(port+SER_16550_THR, c); +} + +// Read one character from the current serial port. +int hal_IDT32334_get_char( void ) +{ + unsigned char c; + cyg_uint8 _lsr; + cyg_addrword_t port = CMA_SER_16550_BASE_A; + + do { + HAL_READ_UINT8(port+SER_16550_LSR, _lsr); + } while ((_lsr & SIO_LSR_DR) == 0); + + HAL_READ_UINT8(port+SER_16550_RBR, c); + return c; + +} + + +int hal_IDT32334_chk_char() +{ + unsigned char c; + cyg_uint8 _lsr; + cyg_addrword_t port = CMA_SER_16550_BASE_A; + + HAL_READ_UINT8(port+SER_16550_LSR, _lsr); + return (_lsr & SIO_LSR_DR)?1:0; + +} +//#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +//----------------------------------------------------------------------------- +// End of plf_stub.c
v2_0/src/plf_stub.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/src/ser16c550c.c =================================================================== --- v2_0/src/ser16c550c.c (nonexistent) +++ v2_0/src/ser16c550c.c (revision 1765) @@ -0,0 +1,546 @@ +//============================================================================= +// +// ser16c550c.c +// +// Simple driver for the 16c550c serial controllers on the IDT board +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tmichals +// Contributors: +// Date: 2003-02-13 +// Purpose: Platform specific code for virtual vector serial support +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include +#include +#include CYGBLD_HAL_PLATFORM_H + +#include // SAVE/RESTORE GP macros +#include // IO macros +#include // interface API +#include // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include // Helper functions +#include // CYG_ISR_HANDLED +#include +#include +//----------------------------------------------------------------------------- +// There is only one port. +#define CMA_SER_16550_BASE_A 0xb8000803 // port A +#define CMA_SER_16550_BASE_B 0xb8000823 // port B + +//----------------------------------------------------------------------------- +// Define the serial registers. The IDT board is equipped with a 16550C +// serial chip. +#define SER_16550_RBR 0x00 // receiver buffer register, read, dlab = 0 +#define SER_16550_THR 0x00 // transmitter holding register, write, dlab = 0 +#define SER_16550_DLL 0x00 // divisor latch (LS), read/write, dlab = 1 +#define SER_16550_IER 0x04 // interrupt enable register, read/write, dlab = 0 +#define SER_16550_DLM 0x04 // divisor latch (MS), read/write, dlab = 1 +#define SER_16550_IIR 0x08 // interrupt identification reg, read, dlab = 0 +#define SER_16550_FCR 0x08 // fifo control register, write, dlab = 0 +#define SER_16550_AFR 0x10 // alternate function reg, read/write, dlab = 1 +#define SER_16550_LCR 0x0c // line control register, read/write +#define SER_16550_MCR 0x10 // modem control register, read/write +#define SER_16550_LSR 0x14 // line status register, read +#define SER_16550_MSR 0x18 // modem status register, read +#define SER_16550_SCR 0x1c // scratch pad register + +// The interrupt enable register bits. +#define SIO_IER_ERDAI 0x01 // enable received data available irq +#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt +#define SIO_IER_ELSI 0x04 // enable receiver line status irq +#define SIO_IER_EMSI 0x08 // enable modem status interrupt + +// The interrupt identification register bits. +#define SIO_IIR_IP 0x01 // 0 if interrupt pending +#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits + +// The line status register bits. +#define SIO_LSR_DR 0x01 // data ready +#define SIO_LSR_OE 0x02 // overrun error +#define SIO_LSR_PE 0x04 // parity error +#define SIO_LSR_FE 0x08 // framing error +#define SIO_LSR_BI 0x10 // break interrupt +#define SIO_LSR_THRE 0x20 // transmitter holding register empty +#define SIO_LSR_TEMT 0x40 // transmitter register empty +#define SIO_LSR_ERR 0x80 // any error condition + +// The modem status register bits. +#define SIO_MSR_DCTS 0x01 // delta clear to send +#define SIO_MSR_DDSR 0x02 // delta data set ready +#define SIO_MSR_TERI 0x04 // trailing edge ring indicator +#define SIO_MSR_DDCD 0x08 // delta data carrier detect +#define SIO_MSR_CTS 0x10 // clear to send +#define SIO_MSR_DSR 0x20 // data set ready +#define SIO_MSR_RI 0x40 // ring indicator +#define SIO_MSR_DCD 0x80 // data carrier detect + +// The line control register bits. +#define SIO_LCR_WLS0 0x01 // word length select bit 0 +#define SIO_LCR_WLS1 0x02 // word length select bit 1 +#define SIO_LCR_STB 0x04 // number of stop bits +#define SIO_LCR_PEN 0x08 // parity enable +#define SIO_LCR_EPS 0x10 // even parity select +#define SIO_LCR_SP 0x20 // stick parity +#define SIO_LCR_SB 0x40 // set break +#define SIO_LCR_DLAB 0x80 // divisor latch access bit + +// The FIFO control register +#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos +#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO +#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO + +///////////////////////////////////////// +// Interrupt Enable Register +#define IER_RCV 0x01 +#define IER_XMT 0x02 +#define IER_LS 0x04 +#define IER_MS 0x08 + +// Line Control Register +#define LCR_WL5 0x00 // Word length +#define LCR_WL6 0x01 +#define LCR_WL7 0x02 +#define LCR_WL8 0x03 +#define LCR_SB1 0x00 // Number of stop bits +#define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words +#define LCR_SB2 0x04 +#define LCR_PN 0x00 // Parity mode - none +#define LCR_PE 0x0C // Parity mode - even +#define LCR_PO 0x08 // Parity mode - odd +#define LCR_PM 0x28 // Forced "mark" parity +#define LCR_PS 0x38 // Forced "space" parity +#define LCR_DL 0x80 // Enable baud rate latch + +// Line Status Register +#define LSR_RSR 0x01 +#define LSR_THE 0x20 + +// Modem Control Register +#define MCR_DTR 0x01 +#define MCR_RTS 0x02 +#define MCR_INT 0x08 // Enable interrupts + +// Interrupt status register +#define ISR_None 0x01 +#define ISR_Rx_Line_Status 0x06 +#define ISR_Rx_Avail 0x04 +#define ISR_Rx_Char_Timeout 0x0C +#define ISR_Tx_Empty 0x02 +#define IRS_Modem_Status 0x00 + +// FIFO control register +#define FCR_ENABLE 0x01 +#define FCR_CLEAR_RCVR 0x02 +#define FCR_CLEAR_XMIT 0x04 + + +//----------------------------------------------------------------------------- +typedef struct { + cyg_uint8* base; + cyg_int32 msec_timeout; + int isr_vector; +} channel_data_t; + +static channel_data_t channels[1] = { + { (cyg_uint8*)CMA_SER_16550_BASE_A, 1000, CYGNUM_HAL_INTERRUPT_SIO_0} +}; + +//----------------------------------------------------------------------------- +// Set the baud rate + +static void +cyg_hal_plf_serial_set_baud(cyg_uint8* port, cyg_uint32 baud) +{ + cyg_uint8 _lcr; + cyg_uint32 baud_divisor; + + baud_divisor = (CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL * 10) / (16 * baud); + + baud_divisor +=5; + baud_divisor = ((cyg_int32)baud_divisor) / 10; + + HAL_READ_UINT8(port+SER_16550_LCR, _lcr); + _lcr |= LCR_DL; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + + HAL_WRITE_UINT8(port+SER_16550_DLM, baud_divisor >> 8); + HAL_WRITE_UINT8(port+SER_16550_DLL, baud_divisor & 0xff); + + _lcr &= ~LCR_DL; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); +} + +//----------------------------------------------------------------------------- +// The minimal init, get and put functions. All by polling. + +void +cyg_hal_plf_serial_init_channel(void* __ch_data) +{ + cyg_uint8* port; + cyg_uint8 _lcr; + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + port = ((channel_data_t*)__ch_data)->base; + + // Disable port interrupts while changing hardware + HAL_WRITE_UINT8(port+SER_16550_IER, 0); + + // Set databits, stopbits and parity. + _lcr = LCR_WL8 | LCR_SB1 | LCR_PN; + HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); + + // Set baud rate. + cyg_hal_plf_serial_set_baud(port, CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD); + + // Enable and clear FIFO + HAL_WRITE_UINT8(port+SER_16550_FCR, (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT)); + + // enable RTS to keep host side happy + HAL_WRITE_UINT8( port+SER_16550_MCR, MCR_RTS ); + + // Don't allow interrupts. + HAL_WRITE_UINT8(port+SER_16550_IER, 0); +} + +void +cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch) +{ + cyg_uint8* port; + cyg_uint8 _lsr; + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + port = ((channel_data_t*)__ch_data)->base; + + CYGARC_HAL_SAVE_GP(); + + do { + HAL_READ_UINT8(port+SER_16550_LSR, _lsr); + } while ( !((_lsr & (SIO_LSR_THRE | SIO_LSR_TEMT)) == 0x60) ); + + // Now, the transmit buffer is empty + HAL_WRITE_UINT8(port+SER_16550_THR, __ch); + + // Hang around until the character has been safely sent. +// do { +// HAL_READ_UINT8(port+SER_16550_LSR, _lsr); +// } while ((_lsr & SIO_LSR_THRE) == 0); + + CYGARC_HAL_RESTORE_GP(); +} + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + cyg_uint8* port; + cyg_uint8 _lsr; + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + port = ((channel_data_t*)__ch_data)->base; + + HAL_READ_UINT8(port+SER_16550_LSR, _lsr); + if ((_lsr & SIO_LSR_DR) == 0) + return false; + + HAL_READ_UINT8(port+SER_16550_RBR, *ch); + + return true; +} + +cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + + +cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count; + channel_data_t* chan; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + chan = (channel_data_t*)__ch_data; + + delay_count = chan->msec_timeout * 10; // delay in .1 ms steps + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t* chan; + cyg_uint8 ier; + int ret = 0; + CYGARC_HAL_SAVE_GP(); + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + chan = (channel_data_t*)__ch_data; + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + irq_state = 1; + + HAL_READ_UINT8(chan->base + SER_16550_IER, ier); + ier |= SIO_IER_ERDAI; + HAL_WRITE_UINT8(chan->base + SER_16550_IER, ier); + + HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1); + HAL_INTERRUPT_UNMASK(chan->isr_vector); + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + + HAL_READ_UINT8(chan->base + SER_16550_IER, ier); + ier &= ~SIO_IER_ERDAI; + HAL_WRITE_UINT8(chan->base + SER_16550_IER, ier); + + HAL_INTERRUPT_MASK(chan->isr_vector); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + break; + case __COMMCTL_SETBAUD: + { + cyg_uint32 baud_rate; + cyg_uint32 baud_divisor; + cyg_uint8* port = chan->base; + va_list ap; + + va_start(ap, __func); + baud_rate = va_arg(ap, cyg_uint32); + va_end(ap); + + + // Disable port interrupts while changing hardware + HAL_READ_UINT8(port+SER_16550_IER, ier); + HAL_WRITE_UINT8(port+SER_16550_IER, 0); + + // Set baud rate. + cyg_hal_plf_serial_set_baud(port, baud_rate); + + // Reenable interrupts if necessary + HAL_WRITE_UINT8(port+SER_16550_IER, ier); + } + break; + + case __COMMCTL_GETBAUD: + break; + default: + break; + } + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + int res = 0; + cyg_uint8 _iir, c; + channel_data_t* chan; + CYGARC_HAL_SAVE_GP(); + + // Some of the diagnostic print code calls through here with no idea what the ch_data is. + // Go ahead and assume it is channels[0]. + if (__ch_data == 0) + __ch_data = (void*)&channels[0]; + + chan = (channel_data_t*)__ch_data; + + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + + HAL_READ_UINT8(chan->base + SER_16550_IIR, _iir); + _iir &= SIO_IIR_ID_MASK; + + *__ctrlc = 0; + if ((_iir == ISR_Rx_Avail) || (_iir == ISR_Rx_Char_Timeout)) { + + HAL_READ_UINT8(chan->base + SER_16550_RBR, c); + + if( cyg_hal_is_break( &c , 1 ) ) + *__ctrlc = 1; + + res = CYG_ISR_HANDLED; + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static void +cyg_hal_plf_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + // Disable interrupts. + HAL_INTERRUPT_MASK(channels[0].isr_vector); + + // Init channels + cyg_hal_plf_serial_init_channel((void*)&channels[0]); + + // Setup procs in the vector table + + // Set channel 0 + CYGACC_CALL_IF_SET_CONSOLE_COMM(0); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + + cyg_hal_plf_serial_init(); +} + +//----------------------------------------------------------------------------- +// end of ser16c550c.c +
v2_0/src/ser16c550c.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/src/platform.S =================================================================== --- v2_0/src/platform.S (nonexistent) +++ v2_0/src/platform.S (revision 1765) @@ -0,0 +1,445 @@ +##============================================================================= +## +## platform.S +## +## MIPS IDT platform code +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): tmichals +## Contributors: nickg +## Date: 2002-10-02 +## Purpose: +## Description: MIPS IDT platform code +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include +#include + +#ifdef CYGPKG_KERNEL +# include +#endif + +#include +#include + + +FUNC_START(hal_memc_setup) +#define PIO_BASE_ADDR 0xb8000600 +#define PIO_DC_SET 0x00500050 +#define PIO_DC_MASK 0xff0fff0f + + li t0,PIO_BASE_ADDR + lw t1,0x4(t0) + nop + li t2,PIO_DC_MASK #mask the UART bits + and t1,t1,t2 + nop + li t2,PIO_DC_SET #rx0=rx1=input, tx0=tx1=output + or t1,t1,t2 + nop + sw t1,0x4(t0) + + + li t0,PORT_WIDTH_CNTL_REG /* Set PortWidth and Bus parameters */ + li t1,PORT_WIDTH_CNTL_VAL + sw t1,0(t0) + + li t0,BUS_TURN_AROUND_CNTRL_REG + li t1,BUS_TURN_AROUND_VAL /* Sets all turnarounds to 3 cycles. 0x18000000*/ + sw t1,0(t0) + + li t0,BUS_TURN_AROUND_REG + li t1,BUS_TURN_AROUND_VAL /* Sets all turnarounds to 3 cycles. 0xffffe204*/ + sw t1,0(t0) + + + li t0,ADDRESS_LATCH_TIMING_REG + li t1,ADDRESS_LATCH_TIMING_VAL + sw t1,0(t0) + + + +/* CHIP SELECT 0 for FLASH */ + li t0,MEM_BASE_BASE + li t1,MBA_REG0 + sw t1,0(t0) /* 0x18000080 */ + li t1,MBM_REG0 + sw t1,0x4(t0) /* 0x18000084 */ + li t0,MEM_CTL_BASE + li t1,MCR_CS0_BS + sw t1,0(t0) /* 0x18000200 */ + +/* CHIP SELECT 1 for FLASH */ + + li t0,MEM_BASE_BASE + li t1,MBA_REG1 + sw t1,8(t0) /* 0x18000088 */ + li t1,MBM_REG1 /* 0x1800008C */ + sw t1,0xc(t0) + li t0,MEM_CTL_BASE + li t1,MCR_CS1_BS /* chip select 2 for other flash */ + sw t1,0x4(t0) /* 0x18000204 */ + +/* CHIP SELECT 2*/ + li t1,MCR_CS2_BS + sw t1,0x8(t0) + +/* CHIP SELECT 3*/ + li t1,MCR_CS3_BS + sw t1,0xc(t0) + + +/* CHIP SELECT 4*/ + li t1,MCR_CS4_BS + sw t1,0x10(t0) + + +/* CHIP SELECT 5*/ + li t1,MCR_CS5_BS + sw t1,0x14(t0) + + + + li t0,RHEA_IREG_BASE + li t1,DISABLE_TIMER + sw t1,0x730(t0) + + li t1,0 + sw t1,0x310(t0) + + +/* SDRAM Initialization:- Start Here! */ + li t1,DRAM_BNK0_BASE + sw t1,0xc0(t0) + li t1,DRAM_BNK1_BASE + sw t1,0xc8(t0) + li t1,DRAM_BNK2_BASE + sw t1,0xd0(t0) + li t1,DRAM_BNK3_BASE + sw t1,0xd8(t0) + + li t1,DRAM_BNK0_MASK + sw t1,0xc4(t0) + li t1,DRAM_BNK1_MASK + sw t1,0xcc(t0) + li t1,DRAM_BNK2_MASK + sw t1,0xd4(t0) + li t1,DRAM_BNK3_MASK + sw t1,0xdc(t0) + + li t0,MEM_BASE_BASE + li t1,MBA_REG1 + sw t1,0x8(t0) + li t1,MBM_REG1 + sw t1,0xc(t0) + + li t0,TIMER_BASE + li t1,DISABLE_TIMER + sw t1,0x60(t0) + nop + li t1,0x0 + sw t1,0x64(t0) + li t1,CPU_BERR_BS + sw t1,0x48(t0) + li t1,IP_BERR_BS + sw t1,0x58(t0) + + + li t0,RHEA_IREG_BASE + li t1,SDRAM_CR_BS + sw t1,0x300(t0) + + li t2,2 + li t3,0 +1: + li t1,SDRAM_PC_VAL + sw t1,0x300(t0) + nop + li t4,SDRAM_TEST_PATTERN + li t5,K1BASE | DRAM_BNK0_BASE + sw t4,0x1000(t5) + addu t3,1 + bne t3,t2,1b + nop + + li t2,2 + li t3,0 +1: + li t1,SDRAM_RFRSH_CMD + sw t1,0x300(t0) + sw t4,0x0(t5) + addu t3,1 + bne t3,t2,1b + nop + + + li t1,SDRAM_MODE_REG + sw t1,0x300(t0) + sw t4,0x80(t5) + + li t0,TIMER_BASE + li t1,DRAM_RF_CMPR_BS + sw t1,0x68(t0) + li t1,ENABLE_TIMER + sw t1,0x60(t0) + + + /* Delay for Sdram to stabilise with fast refresh */ + li t2, 0x2FF00 +1: + subu t2, 1 + bne t2, zero,1b + nop + + /* Change the Sdram refresh to a standard refresh */ + li t0,TIMER_BASE + li t1,DRAM_RF_CMPR_SE_BS + sw t1,0x68(t0) + +/* SDRAM Initialization : End Here ! */ + + + jr ra + nop + +FUNC_END(hal_memc_setup) + + +FUNC_START(hal_setTlbEntry) + .set noreorder + mtc0 a0,C0_INX + mtc0 a1,C0_TLBHI + mtc0 a2,C0_TLBLO0 + mtc0 a3,C0_TLBLO1 + nop + nop + tlbwi + nop +.set reorder + + j ra + nop +FUNC_END(hal_setTlbEntry) + +FUNC_START(hal_setPageSize) + .set noreorder + mtc0 a0,C0_PAGEMASK + nop + nop + .set reorder + j ra + nop +FUNC_END(hal_setPageSize) + + + + +FUNC_START (hal_sysConfigOutByte) + .set noreorder + li t0,0xb8002cf8 + li t1,0xb8002cfc + li t2,0x3 + and a2,t2 + sw a0,0x0(t0) + xori a2,0x3 + or t1,a2 + sb a1,0x0(t1) + j ra + nop + .set reorder +FUNC_END(hal_sysConfigOutByte) + + + +FUNC_START(hal_sysConfigOutHalfWord) + .set noreorder + li t0,0xb8002cf8 + li t1,0xb8002cfc + li t2,0x3 + and a2,t2 + sw a0,0x0(t0) + xori a2,0x2 + or t1,a2 + sh a1,0x0(t1) + j ra + nop + .set reorder +FUNC_END (hal_sysConfigOutHalfWord) + +FUNC_START (hal_sysConfigOutWord) + .set noreorder + li t0,0xb8002cf8 + li t1,0xb8002cfc + sw a0,0x0(t0) + sw a1,0x0(t1) + j ra + nop + .set reorder +FUNC_END (hal_sysConfigOutWord) + + +/* + * Function: + * unsigned char sysConfigInByte (int pciConfigAddress) ; + * Inputs: + * a0 - pciConfigAddress + * Outputs: + * v0 - byte read from PCI Configuration space. + */ + FUNC_START (hal_sysConfigInByte) +sysConfigInByte: + li t0, 0xb8000000 /* t0 = Upper 16 bits of PCI config */ + /* space address register */ + andi t1, a0, 0x00000003 /* t1 = PCI config space byte offset. */ + xor t2, t1, a0 /* t2 = PCI config address of */ + /* longword containing byte. */ + xori t1, 0x00000003 /* t1 = big endian byte offset. */ + /* offset 0 -> 3 */ + /* offset 1 -> 2 */ + /* offset 2 -> 1 */ + /* offset 3 -> 0 */ + or t1, t0 /* t1 = byte corrected PCI config */ + /* data address. */ + .set noreorder /* Instructions must not be moved ! */ + sw t2, 0x2cf8 (t0) /* Write PCI config space address reg */ + lw $0, 0x2cf8 (t0) /* wbflush() insures write-then-read */ + + lbu v0, 0x2cfc (t1) /* v0 = PCI config space byte read */ + + j ra /* Return to caller. */ + sw $0, 0x2cf8 (t0) /* BDSLOT - Park PCI bus */ + + .set reorder +FUNC_END (hal_sysConfigInByte) + +/* + * Function: + * unsigned short sysConfigInHalfWord (int pciConfigAddress) ; + * + * Inputs: + * a0 - pciConfigAddress + * + * Outputs: + * v0 - half word read from PCI Configuration space. + */ + +FUNC_START (hal_sysConfigInHalfWord) +sysConfigInHalfWord: + li t0, 0xb8000000 /* t0 = Upper 16 bits of PCI config */ + /* space address register */ + andi t1, a0, 0x00000003 /* t1 = Config space halfword offset. */ + xor t2, t1, a0 /* t2 = PCI config address of */ + /* longword containing halfword. */ + + xori t1, 0x00000002 /* t1 = big endian halfword offset. */ + /* offset 0 -> 2 */ + /* offset 2 -> 0 */ + + or t1, t0 /* t1 = halfword corrected PCI config */ + /* data address. */ + .set noreorder /* Instructions must not be moved ! */ + sw t2, 0x2cf8 (t0) /* Write PCI config space address reg */ + lw $0, 0x2cf8 (t0) /* wbflush() insures write-then-read */ + + lhu v0, 0x2cfc (t1) /* v0 = config space halfword read */ + + j ra /* Return to caller. */ + sw $0, 0x2cf8 (t0) /* BDSLOT - Park PCI bus */ + + .set reorder +FUNC_END (hal_sysConfigInHalfWord) + +/* + * Function: + * unsigned short sysConfigInWord (int pciConfigAddress) ; + * + * Inputs: + * a0 - pciConfigAddress + * + * Outputs: + * v0 - word read from PCI Configuration space. + */ + +FUNC_START (hal_sysConfigInWord) + li t0, 0xb8000000 /* t0 = Upper 16 bits of PCI config */ + /* space address register */ + .set noreorder /* Instructions must not be moved ! */ + sw a0, 0x2cf8 (t0) /* Write PCI config space address reg */ + lw $0, 0x2cf8 (t0) /* wbflush() insures write-then-read */ + + lw v0, 0x2cfc (t0) /* v0 = config space word read */ + + j ra /* Return to caller. */ + sw $0, 0x2cf8 (t0) /* BDSLOT - Park PCI bus */ + + .set reorder +FUNC_END(hal_sysConfigInWord) + + +##----------------------------------------------------------------------------- +# Interrupt vector tables. +# These tables contain the isr, data and object pointers used to deliver +# interrupts to user code. + + .extern hal_default_isr + .data + + .globl hal_interrupt_handlers +hal_interrupt_handlers: + .rept 30 + .long hal_default_isr + .endr + + .globl hal_interrupt_data +hal_interrupt_data: + .rept 30 + .long 0 + .endr + + .globl hal_interrupt_objects +hal_interrupt_objects: + .rept 30 + .long 0 + .endr + +##----------------------------------------------------------------------------- +## end of platform.S +
v2_0/src/platform.S Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/src/hal_diag.c =================================================================== --- v2_0/src/hal_diag.c (nonexistent) +++ v2_0/src/hal_diag.c (revision 1765) @@ -0,0 +1,183 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tmichals +// Contributors: nickg, dmoseley +// Date: 2003-02-13 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include + +#include // base types + +#include +#include + +#include + +#include + +//----------------------------------------------------------------------------- +// Select which diag channels to use + +//#define CYG_KERNEL_DIAG_LCD +#define CYG_KERNEL_DIAG_SERIAL + +/*---------------------------------------------------------------------------*/ + +void hal_diag_led(int x) +{ +// HAL_WRITE_UINT32(HAL_DISPLAY_LEDBAR, x); +#if !defined(CYG_KERNEL_DIAG_LCD) +// HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIWORD, x); +#endif +} + +externC void diag_write_string (const char*); + +#ifdef CYG_KERNEL_DIAG_SERIAL +extern void cyg_hal_plf_comms_init(void); +extern void cyg_hal_plf_serial_putc(void*, cyg_uint8); +extern cyg_uint8 cyg_hal_plf_serial_getc(void*); +#endif + +void hal_diag_init(void) +{ +#if defined(CYGSEM_HAL_ROM_MONITOR) && !defined(CYG_KERNEL_DIAG_SERIAL) + // It's handy to have the LCD initialized at reset when using it + // for debugging output. + // The serial port likely doesn't work yet. Let's wait. + diag_write_string ("eCos ROM " __TIME__ "\n"); + diag_write_string (__DATE__ "\n"); +#endif + + cyg_hal_plf_comms_init(); +} + +#if defined(CYG_KERNEL_DIAG_LCD) +static void hal_diag_clear_lcd(void) +{ + volatile int i = 0x20000; + while (--i) ; + + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, ' '); + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, ' '); + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, ' '); + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, ' '); + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, ' '); + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, ' '); + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, ' '); + HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' '); +} +#endif /* defined(CYG_KERNEL_DIAG_LCD) */ + +void hal_diag_write_char(char c) +{ +#if defined(CYG_KERNEL_DIAG_LCD) + static volatile CYG_WORD* reg = HAL_DISPLAY_ASCIIPOS0; +#endif + + unsigned long __state; + + HAL_DISABLE_INTERRUPTS(__state); + + if(c == '\n') + { +#if defined(CYG_KERNEL_DIAG_LCD) + reg = HAL_DISPLAY_ASCIIPOS0; + hal_diag_clear_lcd(); +#endif +#if defined (CYG_KERNEL_DIAG_SERIAL) + cyg_hal_plf_serial_putc(NULL, '\r'); + cyg_hal_plf_serial_putc(NULL, '\n'); +#endif + } + else if (c == '\r') + { + // Ignore '\r' + } + else + { +#if defined(CYG_KERNEL_DIAG_LCD) + if (reg == HAL_DISPLAY_ASCIIPOS0) + hal_diag_clear_lcd(); + + HAL_WRITE_UINT32(reg, c); + + // Advance to next LED position. + if (reg == HAL_DISPLAY_ASCIIPOS0) + reg = HAL_DISPLAY_ASCIIPOS1; + else if (reg == HAL_DISPLAY_ASCIIPOS1) + reg = HAL_DISPLAY_ASCIIPOS2; + else if (reg == HAL_DISPLAY_ASCIIPOS2) + reg = HAL_DISPLAY_ASCIIPOS3; + else if (reg == HAL_DISPLAY_ASCIIPOS3) + reg = HAL_DISPLAY_ASCIIPOS4; + else if (reg == HAL_DISPLAY_ASCIIPOS4) + reg = HAL_DISPLAY_ASCIIPOS5; + else if (reg == HAL_DISPLAY_ASCIIPOS5) + reg = HAL_DISPLAY_ASCIIPOS6; + else if (reg == HAL_DISPLAY_ASCIIPOS6) + reg = HAL_DISPLAY_ASCIIPOS7; + else // reg == HAL_DISPLAY_ASCIIPOS7 or UNKNOWN + reg = HAL_DISPLAY_ASCIIPOS0; +#endif +#if defined(CYG_KERNEL_DIAG_SERIAL) + cyg_hal_plf_serial_putc(NULL, c); +#endif + } + + HAL_RESTORE_INTERRUPTS(__state); +} + +void hal_diag_read_char(char* c) +{ + *c = cyg_hal_plf_serial_getc(NULL); +} + +/*---------------------------------------------------------------------------*/ +/* End of hal_diag.c */
v2_0/src/hal_diag.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/src/plf_misc.c =================================================================== --- v2_0/src/plf_misc.c (nonexistent) +++ v2_0/src/plf_misc.c (revision 1765) @@ -0,0 +1,659 @@ +//========================================================================== +// +// plf_misc.c +// +// HAL platform miscellaneous functions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): tmichals +// Contributors: +// Date: 2002-09-01 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous functions provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include +#include + +#include CYGBLD_HAL_PLATFORM_H + +#include // Base types +#include // tracing macros +#include // assertion macros +#include // architectural definitions +#include // Interrupt handling +#include // Cache handling + +/* This is the Reference board configuration */ +#include + +#include +#include + +void hal_rc334PciInit (void); +static void mmuInit (void); +static void sysDisableBusError (void) ; +static void sysEnableBusError(void); +void ecosPciConfigOutByte( int busNo, int devFnNo,int regOffset,unsigned char data ); +void ecosPciConfigOutHalfWord( int busNo,int devFnNo,int regOffset,unsigned short data ); +void ecosPciConfigOutWord( int busNo,int devFnNo,int regOffset,unsigned int data ); +unsigned char ecosPciConfigInByte(int busNo, int devFnNo,int regOffset); +unsigned short ecosPciConfigInHalfWord( int busNo,int devFnNo,int regOffset); +unsigned int ecosPciConfigInWord( int busNo, int devFnNo,int regOffset); +void displayLED(char *str, int count); + +/*------------------------------------------------------------------------*/ + + /* this is called from the kernel */ +void hal_platform_init(void) +{ + + HAL_ICACHE_INVALIDATE_ALL(); + HAL_ICACHE_ENABLE(); + HAL_DCACHE_INVALIDATE_ALL(); + HAL_DCACHE_ENABLE(); + + displayLED("eCOS", 4); + hal_if_init(); + mmuInit(); + hal_rc334PciInit(); +} + + + +/* PCI Configuration Registers */ +#define PCI_CFG_VENDORID 0x00 +#define PCI_CFG_DEVICEID 0x02 +#define PCI_CFG_COMMAND 0x04 +#define PCI_CFG_STATUS 0x06 +#define PCI_CFG_REVID 0x08 +#define PCI_CFG_CLASS_CODE 0x09 +#define PCI_CFG_CACHELINE 0x0c +#define PCI_CFG_LATENCY_TIMER 0x0d +#define PCI_CFG_HEADER_TYPE 0x0e +#define PCI_CFG_BIST 0x0f +#define PCI_CFG_BAR0 0x10 +#define PCI_CFG_BAR1 0x14 +#define PCI_CFG_BAR2 0x18 +#define PCI_CFG_BAR3 0x1c +#define PCI_CFG_BAR4 0x20 +#define PCI_CFG_BAR5 0x24 +#define PCI_CFG_CIS_POINTER 0x28 +#define PCI_CFG_SUB_VENDORID 0x2c +#define PCI_CFG_SUB_SYSTEMID 0x2e +#define PCI_CFG_EXP_ROM 0x30 +#define PCI_CFG_CAPABILITIES 0x34 +#define PCI_CFG_RESERVED1 0x35 +#define PCI_CFG_RESERVED2 0x38 +#define PCI_CFG_INT_LINE 0x3c +#define PCI_CFG_INT_PIN 0x3d +#define PCI_CFG_MIN_GRANT 0x3e +#define PCI_CFG_MAX_LATENCY 0x3f +#define PCI_CFG_TRDY_TIMEOUT 0x40 +#define PCI_CFG_RETRY_TIMEOUT 0x41 + +#define RC334_CONFIG0 0x80000000 +/* Typical values used in this example */ +#define RC334_PCI_CONFIG0 0x0204111D /* Device ID & Vendor ID */ +#define RC334_PCI_CONFIG1 0x00200157 /* Command : MWINV, Enable bus master, + memory I/O access */ +#define RC334_PCI_CONFIG2 0x06800001 /* Class Code & Revision ID */ +#define RC334_PCI_CONFIG3 0x0000ff04 /* BIST, Header Type, Master Latency, + Cache line size */ +#define RC334_PCI_CONFIG4 0xA0000008 /* Memory Base Address Reg, prefetchable */ +#define RC334_PCI_CONFIG5 0x60000000 /* Integrated Controller Reg, non-prefetchable */ +#define RC334_PCI_CONFIG6 0x00800001 /* IO Base Address Reg */ +#define RC334_PCI_CONFIG7 0x00000000 /* Unused BAR space, assign some address + that never gets generated on PCI Bus */ + +/* Reserved registers */ +#define RC334_PCI_CONFIG8 0x00000000 +#define RC334_PCI_CONFIG9 0x00000000 +#define RC334_PCI_CONFIG10 0x00000000 + +/* Subsystem ID and the subsystem Vendor ID */ +#define RC334_PCI_CONFIG11 0x00000000 + +/* Reserved registers */ +#define RC334_PCI_CONFIG12 0x00000000 +#define RC334_PCI_CONFIG13 0x00000000 +#define RC334_PCI_CONFIG14 0x00000000 + +/* Max latency, Min Grant, Interrupt pin and interrupt line */ +#define RC334_PCI_CONFIG15 0x38080101 + +/* Retry timeout value, TRDY timeout value. Set to default 0x80 */ +#define RC334_PCI_CONFIG16 0x00008080 + +/* Rc32334 specific PCI registers */ +#define RC334_PCI_REG_BASE 0xb8000000 +#define RC334_CPUTOPCI_BASE_REG1 (RC334_PCI_REG_BASE + 0x20B0) +#define RC334_CPUTOPCI_BASE_REG2 (RC334_PCI_REG_BASE + 0x20B8) +#define RC334_CPUTOPCI_BASE_REG3 (RC334_PCI_REG_BASE + 0x20C0) +#define RC334_CPUTOPCI_BASE_REG4 (RC334_PCI_REG_BASE + 0x20C8) + +#define RC334_PCI_ARB_REG (RC334_PCI_REG_BASE + 0x20E0) +#define RC334_PCITOCPU__BASE_REG1 (RC334_PCI_REG_BASE + 0x20E8) +#define RC334_PCITOCPU__BASE_REG2 (RC334_PCI_REG_BASE + 0x20F4) +#define RC334_PCITOCPU__BASE_REG3 (RC334_PCI_REG_BASE + 0x2100) +#define RC334_PCITOCPU__BASE_REG4 (RC334_PCI_REG_BASE + 0x210C) + +/* Considering a typical case */ +#define CPUTOPCI_BASE_REG1_VAL 0x40000001 +#define CPUTOPCI_BASE_REG2_VAL 0x00000000 +#define CPUTOPCI_BASE_REG3_VAL 0x00000000 +#define CPUTOPCI_BASE_REG4_VAL 0x18800001 + +//TCM#define PCITOCPU_BASE_REG3_VAL 0x00000000 +//TCM#define PCITOCPU_BASE_REG4_VAL 0x18000051 /* Size field set to 0x14 : 1MB size */ + +#define RC334_PCITOCPU_BASE_REG1 (RC334_PCI_REG_BASE+0x20E8) +#define RC334_PCITOCPU_BASE_REG2 (RC334_PCI_REG_BASE+0x20F4) +#define RC334_PCITOCPU_BASE_REG3 (RC334_PCI_REG_BASE+0x2100) +#define RC334_PCITOCPU_BASE_REG4 (RC334_PCI_REG_BASE+0x210C) + +#define PCITOCPU_MEM_BASE(addr) ( (addr & 0xFFFFFF)<<8) +#define PCITOCPU_SIZE(i) ( ( i & 0x1F) << 2 ) +#define PCITOCPU_EN_SWAP 1 + +#define SIZE_1MB 0x14 +#define SIZE_64MB 0x1A + +#define SYS_MEM_BASE 0x0 /* local sdram starting address */ +#define RC32334_INT_REG_BASE 0x18000000 /* Integrated controller's internal registers */ + +/* PCI Target Control Register is provided in the RC32334 to utilize +eager prefetches and reduce target disconnects and retries. In the +following example, an optimized value is picked that enables eager +prefetch for all BAR's, enables Memory Write and Memory Write and +Invalidate (MWMWI), uses threshold for target write FIFO of 8 words, +and sets disconnect and retry timer to 40 PCI clocks */ + +#define PCI_TARGET_CONTROL_REG 0xB80020A4 +#define PCI_TARGET_CONTROL_REG_VAL 0x7EF02828 + +/* BAR1 is selected as memory base register with 64 Mbyte address +range starting at physical address 0x0000_0000, allowing external PCI +masters to access the local SDRAM for data read and write. This +register setting works with the BAR1 register in the PCI configuration +register in the PCI bridge of the RC32334 which, in this example, has +been set to 0xA000_0000. With the given settings, the external PCI +masters can access addresses in the range 0xA000_0000 through +0xA3FF_FFFF using BAR1 which gets translated to address range +0x0000_0000 through 0x03FF_FFFF on the local CPU bus owing to the +PCITOCPU_BASE_REG1 settings. */ + +#define PCITOCPU_BASE_REG1_VAL ((PCITOCPU_MEM_BASE(SYS_MEM_BASE)) | \ + (PCITOCPU_SIZE(SIZE_64MB) ) | \ + (PCITOCPU_EN_SWAP) ) + +/* BAR2 is selected as memory base register with 1 Mbyte range +starting at the physical address 0x1800_0000. This maps to the RC32334 +internal registers allowing external PCI masters to read/modify the +RC32334 registers. In this example, the BAR2 register in the PCI +configuration register of the RC32334 PCI bridge has been set to +0xB800_0000 (note that this address is in the PCI space and should not +be confused with the CPU address map). External PCI masters can access +memory range 0xB800_0000 through 0xB80F_FFFF, sufficient enough to +access all the RC32334 internal registers. The PCITOCPU_BASE_REG2 +settings map all PCI cycles falling in the above range to physical +address range 0x1800_0000 — 0x180F_FFFF on the local CPU bus. */ + +#define PCITOCPU_BASE_REG2_VAL ((PCITOCPU_MEM_BASE(RC32334_INT_REG_BASE)) | \ + (PCITOCPU_SIZE(SIZE_1MB) ) | \ + (PCITOCPU_EN_SWAP) ) + +/* BAR3 is selected as IO base register with 1 Mbyte range mapped to +address 0x1800_0000, providing another window for accessing the +Integrated controller registers. In this example, the value for the +BAR3 has been picked as 0x0000_0000 (address range 0x0000_00000 +through 0x000F_FFFF). Any PCI IO cycles to this address range would +get translated to local CPU address range of 0x1800_0000 through +0x180F_FFFF using this register settings. */ + +#define PCITOCPU_BASE_REG3_VAL ( \ + (PCITOCPU_MEM_BASE(RC32334_INT_REG_BASE)) | \ + (PCITOCPU_SIZE(SIZE_1MB) ) | \ + (PCITOCPU_EN_SWAP) ) + +/* BAR4 register is not used. Therefore, it can be disabled by selecting the SIZE value 1-7 */ +#define PCITOCPU_BASE_REG4_VAL ( PCITOCPU_SIZE( 1 ) ) + +/* Arbitration register value: + Target Ready, internal arbiter, fixed priority +*/ +#define PCI_ARB_REG_VAL 0x00000001 + +/* Rc32334 config address/data definitions */ +#define PCI_CONFIG_ADDR_REG 0xb8002cf8 +#define PCI_CONFIG_DATA_REG 0xb8002cfc + +/* BYTE SWAP macros */ +#define HALF_WORD_SWAP(x) \ + ( ( ( x << 8 ) & 0xff00) | \ + ( (x >> 8 ) & 0x00ff ) ) + +#define WORD_SWAP(x)\ + ( ( ( x << 24 ) & 0xff000000 ) | \ + ( (x << 8 ) & 0x00ff0000 ) | \ + ( (x >> 8 ) & 0x0000ff00 ) | \ + ( (x >> 24 ) & 0x000000ff ) ) + +/* PCI Functions */ +unsigned int pciConfigInWord( int busNo, int devNo, int funcNo, int regOffset); +unsigned short pciConfigInHalfWord( int busNo, int devNo, int funcNo, int regOffset); +unsigned char pciConfigInByte( int busNo, int devNo, int funcNo, int regOffset); +void pciConfigOutWord ( int busNo, int devNo, int funcNo, int regOffset, unsigned int data ); +void pciConfigOutHalfWord ( int busNo, int devNo, int funcNo, int regOffset, unsigned short data ); +void pciConfigOutChar ( int busNo, int devNo, int funcNo, int regOffset, unsigned char data ); + +/* Rc32334 Bus error register. The bit7 of this register can be used +to enable or disable the BusError. The bus error is disabled briefly +at the time of pci Scanning and enabled thereafter. */ + +#define RC334_BUS_ERR_CNTL_REG 0xb8000010 + +/* + Function name : hal_rc334PciInit + Parameters passed : none + return value : none + The function initialises the configuration registers of Rc32334 PCI interface controller. +*/ +void hal_rc334PciInit ( ) +{ + + unsigned int pciConfigData[17]; + int index ; + volatile unsigned int *configAddrReg ; + volatile unsigned int *configDataReg ; + volatile unsigned int *regPointer ; + + configAddrReg = (volatile unsigned int*) PCI_CONFIG_ADDR_REG; + configDataReg = (volatile unsigned int*) PCI_CONFIG_DATA_REG; + + pciConfigData[0] = RC334_PCI_CONFIG0; + pciConfigData[1] = RC334_PCI_CONFIG1; + pciConfigData[2] = RC334_PCI_CONFIG2; + pciConfigData[3] = RC334_PCI_CONFIG3; + pciConfigData[4] = RC334_PCI_CONFIG4; + pciConfigData[5] = RC334_PCI_CONFIG5; + pciConfigData[6] = RC334_PCI_CONFIG6; + pciConfigData[7] = RC334_PCI_CONFIG7; + pciConfigData[8] = RC334_PCI_CONFIG8; + pciConfigData[9] = RC334_PCI_CONFIG9; + pciConfigData[10] = RC334_PCI_CONFIG10; + pciConfigData[11] = RC334_PCI_CONFIG11; + pciConfigData[12] = RC334_PCI_CONFIG12; + pciConfigData[13] = RC334_PCI_CONFIG13; + pciConfigData[14] = RC334_PCI_CONFIG14; + pciConfigData[15] = RC334_PCI_CONFIG15; + pciConfigData[16] = RC334_PCI_CONFIG16; + + *configAddrReg = (unsigned int)RC334_CONFIG0 ; +/* This example writes to all the configuration registers. Some of +the PCI configuration registers (such as Device ID, Vendor ID, Class +Code, Revision ID, BIST, Header Type, Subsystem Vendor ID, Maximum +Latency, Minimum Grant, Interrupt Pin) need not be initialized */ + + for (index =0; index <17; index++ ) + { + *configDataReg = pciConfigData[index]; + *configAddrReg = *configAddrReg + 4; + } + + /* Park the Address Register */ + configAddrReg = ( volatile unsigned int*)0x0 ; + +/* Set Rc32334 specific registers */ + +regPointer = ( volatile unsigned int*)(RC334_CPUTOPCI_BASE_REG1) ; +*regPointer = (unsigned int)(CPUTOPCI_BASE_REG1_VAL ); + +regPointer = (volatile unsigned int*)(RC334_CPUTOPCI_BASE_REG2) ; +*regPointer = (unsigned int)(CPUTOPCI_BASE_REG2_VAL ); + +regPointer = (volatile unsigned int*)(RC334_CPUTOPCI_BASE_REG3) ; +*regPointer = (unsigned int)(CPUTOPCI_BASE_REG3_VAL ); + +regPointer = (volatile unsigned int*)(RC334_CPUTOPCI_BASE_REG4) ; +*regPointer = (unsigned int)(CPUTOPCI_BASE_REG4_VAL ); + +regPointer = (volatile unsigned int*)(RC334_PCITOCPU_BASE_REG1) ; +*regPointer = (unsigned int)(PCITOCPU_BASE_REG1_VAL ); + +regPointer = ( volatile unsigned int*)(RC334_PCITOCPU_BASE_REG2) ; +*regPointer = (unsigned int)(PCITOCPU_BASE_REG2_VAL ); + +regPointer = (volatile unsigned int*)(RC334_PCITOCPU_BASE_REG3) ; +*regPointer = (unsigned int)(PCITOCPU_BASE_REG3_VAL ); + +regPointer = (volatile unsigned int*)(RC334_PCITOCPU_BASE_REG4) ; +*regPointer = (unsigned int)(PCITOCPU_BASE_REG4_VAL ); + +regPointer = (volatile unsigned int*)PCI_TARGET_CONTROL_REG ; +*regPointer = (unsigned int)PCI_TARGET_CONTROL_REG_VAL ; + +regPointer = (volatile unsigned int*)(RC334_PCI_ARB_REG); +*regPointer = (unsigned int)(PCI_ARB_REG_VAL); + +} + +/* Function name : sysDisableBusError + Disables the Bus Error prior to pciScan. +*/ +static void sysDisableBusError ( ) { + unsigned int* regPointer ; + unsigned int data ; + regPointer = (unsigned int*) ( RC334_BUS_ERR_CNTL_REG); + data = *regPointer ; + /* Set bit7 to disable busError */ + data = data | 0x00000080 ; + *regPointer = data ; +} + +/* Function name : sysEnableBusError + Enables the Bus Error after pciScan +*/ +static void sysEnableBusError ( ) { + unsigned int* regPointer ; + unsigned int data ; + regPointer = (unsigned int*) ( RC334_BUS_ERR_CNTL_REG); + data = *regPointer ; + /* Reset bit7 to enable busError */ + data = data & 0xffffff7f; + *regPointer = data ; +} + + + + +#define TLB_HI_MASK 0xffffe000 +#define TLB_LO_MASK 0x3fffffff +#define PAGEMASK_SHIFT 13 +#define TLB_LO_SHIFT 6 +#define PCI_PAGE_SIZE 0x01000000 /* 16 Mbyte */ +#define MMU_PAGE_UNCACHED 0x00000010 +#define MMU_PAGE_DIRTY 0x00000004 +#define MMU_PAGE_VALID 0x00000002 +#define MMU_PAGE_GLOBAL 0x00000001 +#define PCI_MMU_PAGEMASK 0x00000fff +#define PCI_MMU_PAGEATTRIB (MMU_PAGE_UNCACHED|MMU_PAGE_DIRTY| MMU_PAGE_VALID|MMU_PAGE_GLOBAL) +#define PCI_MEMORY_SPACE1 0x40000000 +#define PCI_MEMORY_SPACE2 0x60000000 +#define PCI_IO_SPACE 0x18000000 +/* + Function name : mmuInit + Tlb Initialisation for the PCI memory/IO windows. +*/ +static void mmuInit ( ) { + unsigned int Tlb_Attrib ; + unsigned int Tlb_Hi ; + unsigned int Tlb_Lo0 ; + unsigned int Tlb_Lo1 ; + unsigned int Page_Size ; + unsigned int pageFrame ; + unsigned int Tlb_Inx ; + + /* Uncached, dirty, global and valid MMU page */ + Tlb_Attrib = PCI_MMU_PAGEATTRIB ; + + Page_Size = PCI_MMU_PAGEMASK ; + Page_Size = (Page_Size << (PAGEMASK_SHIFT)); + hal_setPageSize(Page_Size); + +/* + * MMU mapping for PCI_MEMORY_SPACE1 + * Map 16MB pages + * Virtual 0x40000000-0x40ffffff to Physical 0x40000000 - 0x40ffffff + * Virtual 0x41000000-0x41ffffff to Physical 0x41000000 - 0x41ffffff + */ + + Tlb_Hi = PCI_MEMORY_SPACE1 ; /* VPN2:VirtualPageframeNumber%2 */ + Tlb_Hi = (Tlb_Hi & TLB_HI_MASK) ; + + pageFrame = PCI_MEMORY_SPACE1 ; + /* Even PFN:Page Frame Number */ + pageFrame = pageFrame >> TLB_LO_SHIFT; + Tlb_Lo0 = pageFrame ; + Tlb_Lo0 = ( Tlb_Lo0 | Tlb_Attrib) ; + Tlb_Lo0 = ( Tlb_Lo0 & TLB_LO_MASK); + + pageFrame = (PCI_MEMORY_SPACE1 | PCI_PAGE_SIZE) ; + /* Odd PFN:Page Frame Number*/ + pageFrame = pageFrame >> TLB_LO_SHIFT ; + Tlb_Lo1 = pageFrame ; + Tlb_Lo1 = ( Tlb_Lo1 | Tlb_Attrib) ; + Tlb_Lo1 = ( Tlb_Lo1 & TLB_LO_MASK); + Tlb_Inx = 0 ; + hal_setTlbEntry(Tlb_Inx, Tlb_Hi, Tlb_Lo0, Tlb_Lo1); + +/* + * MMU mapping for PCI_MEMORY_SPACE2 + * Virtual 0x60000000-0x60ffffff to Physical 0x60000000 - 0x60ffffff + * Virtual 0x61000000-0x61ffffff to Physical 0x61000000 - 0x61ffffff + */ + Tlb_Hi = PCI_MEMORY_SPACE2 ; /* VPN2 */ + Tlb_Hi = ( Tlb_Hi & TLB_HI_MASK ); + + pageFrame = PCI_MEMORY_SPACE2 ; + pageFrame = pageFrame >> TLB_LO_SHIFT ; /*Even PFN */ + Tlb_Lo0 = pageFrame ; + + Tlb_Lo0 = ( Tlb_Lo0 | Tlb_Attrib) ; + Tlb_Lo0 = ( Tlb_Lo0 & TLB_LO_MASK); + + pageFrame = ( PCI_MEMORY_SPACE2 | PCI_PAGE_SIZE ) ; + pageFrame = pageFrame >> TLB_LO_SHIFT ; /* Odd PFN */ + Tlb_Lo1 = pageFrame ; + Tlb_Lo1 = ( Tlb_Lo1 | Tlb_Attrib) ; + Tlb_Lo1 = ( Tlb_Lo1 & TLB_LO_MASK); + Tlb_Inx = 1 ; + hal_setTlbEntry(Tlb_Inx, Tlb_Hi, Tlb_Lo0, Tlb_Lo1); + +/* + * MMU mapping PCI IO space + * Virtual 0x18000000-0x18ffffff to Physical 0x18000000 - 0x18ffffff + * Virtual 0x19000000-0x19ffffff to Physical 0x19000000 - 0x19ffffff + */ + Tlb_Hi = PCI_IO_SPACE ; /* VPN2 */ + Tlb_Hi = ( Tlb_Hi & TLB_HI_MASK ); + + pageFrame = PCI_IO_SPACE ; + + pageFrame = pageFrame >> TLB_LO_SHIFT ; /* Even PFN */ + Tlb_Lo0 = pageFrame ; + Tlb_Lo0 = ( Tlb_Lo0 | Tlb_Attrib) ; + Tlb_Lo0 = ( Tlb_Lo0 & TLB_LO_MASK); + + pageFrame = (PCI_IO_SPACE | PCI_PAGE_SIZE) ; + pageFrame = pageFrame >> TLB_LO_SHIFT ; /* Odd PFN */ + Tlb_Lo1 = pageFrame ; + Tlb_Lo1 = ( Tlb_Lo1 | Tlb_Attrib) ; + Tlb_Lo1 = ( Tlb_Lo1 & TLB_LO_MASK); + Tlb_Inx = 2 ; + hal_setTlbEntry(Tlb_Inx, Tlb_Hi, Tlb_Lo0, Tlb_Lo1); + } + + + + +/* ecos PCI functions */ + + + void ecosPciConfigOutByte + ( int busNo, + int devFnNo, + int regOffset, + unsigned char data ){ + + unsigned int address ; + + address = ( ( (busNo << 16) & 0x00ff0000 ) | + ( ( devFnNo << 8 ) & 0x0000ff00 ) + ); + address = ( address | 0x80000000 | (regOffset ) ); + hal_sysConfigOutByte(address, data, (regOffset & 0x3) ); +} + +void ecosPciConfigOutHalfWord + ( int busNo, + int devFnNo, + int regOffset, + unsigned short data ){ + + unsigned int address ; + + address = ( ( (busNo << 16) & 0x00ff0000 ) | + ( ( devFnNo << 8 ) & 0x0000ff00) + ); + address = ( address | 0x80000000 | (regOffset ) ); + hal_sysConfigOutHalfWord(address, data, (regOffset & 0x3) ); +} + + +void ecosPciConfigOutWord + ( int busNo, + int devFnNo, + int regOffset, + unsigned int data ){ + + unsigned int address ; + address = ( ( (busNo << 16) & 0x00ff0000 ) | + ( ( devFnNo << 8 ) & 0x0000ff00) + ); + address = ( address | 0x80000000 | (regOffset ) ); + + hal_sysConfigOutWord(address, data); +} + +unsigned char ecosPciConfigInByte + (int busNo, + int devFnNo, + int regOffset + ){ + + unsigned int address ; + unsigned char retVal ; + + address = ( ( (busNo << 16) & 0x00ff0000 ) | + ( ( devFnNo << 8 ) & 0x0000ff00) + ); + address = ( address | 0x80000000 | (regOffset ) ); + sysDisableBusError( ); + retVal = (unsigned char)(hal_sysConfigInByte(address)); + sysEnableBusError( ); + return ( retVal ); +} + +unsigned short ecosPciConfigInHalfWord + ( int busNo, + int devFnNo, + int regOffset + ){ + + unsigned int address; + unsigned short retVal; + + address = ( ( (busNo << 16) & 0x00ff0000 ) | + ( ( devFnNo << 8 ) & 0x0000ff00) + ); + address = ( address | 0x80000000 | (regOffset ) ); + sysDisableBusError( ); + retVal = (unsigned short)hal_sysConfigInHalfWord(address); + sysEnableBusError( ); + return retVal; + +} +unsigned int ecosPciConfigInWord + ( int busNo, + int devFnNo, + int regOffset + ){ + + unsigned int address; + unsigned int retVal; + + address = ( ( (busNo << 16) & 0x00ff0000 ) | + ( ( devFnNo << 8 ) & 0x0000ff00) + ); + address = ( address | 0x80000000 | regOffset ); + sysDisableBusError( ); + retVal = hal_sysConfigInWord(address); + sysEnableBusError( ); + return retVal; +} + + +void displayLED(char *str, int count) +{ + char *pChar = (char *)0xB4000000; + + char temp; + + /* clear */ + temp = pChar[0x400]; + + if (count) + pChar[0xf]= str[0]; + else + return; + + if (--count) + pChar[0xb]= str[1]; + else + return; + + if (--count) + pChar[0x7]= str[2]; + else + return; + + if (--count) + pChar[0x3]= str[3]; + else + return; + +} + +/*------------------------------------------------------------------------*/ +/* End of plf_misc.c */ +
v2_0/src/plf_misc.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: v2_0/misc/redboot_RAM.ecm =================================================================== --- v2_0/misc/redboot_RAM.ecm (nonexistent) +++ v2_0/misc/redboot_RAM.ecm (revision 1765) @@ -0,0 +1,104 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware refidt334 ; + template redboot ; + package -hardware CYGPKG_HAL_MIPS v2_0 ; + package -hardware CYGPKG_HAL_MIPS_IDT32334 v2_0 ; + package -hardware CYGPKG_HAL_MIPS_IDT32334_REFIDT334 v2_0 ; + package -hardware CYGPKG_IO_PCI v2_0 ; + package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 v2_0 ; + package -hardware CYGPKG_DEVS_ETH_MIPS_REFIDT334 v2_0 ; + package -hardware CYGPKG_DEVS_FLASH_MIPS_REFIDT334 v2_0 ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX v2_0 ; + package -hardware CYGPKG_IO_SERIAL_MIPS_IDT79S334A v2_0 ; + package -template CYGPKG_HAL v2_0 ; + package -template CYGPKG_INFRA v2_0 ; + package -template CYGPKG_REDBOOT v2_0 ; + package -template CYGPKG_ISOINFRA v2_0 ; + package -template CYGPKG_LIBC_STRING v2_0 ; + package -template CYGPKG_NS_DNS v2_0 ; + package -template CYGPKG_CRC v2_0 ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 0 +}; + +cdl_option CYGHWR_HAL_MIPS_CPU_FREQ { + user_value 75 +}; + +cdl_component CYG_HAL_STARTUP { + user_value RAM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + user_value 0x00040000 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +}; + + Index: v2_0/misc/RAMNetwork.ecm =================================================================== --- v2_0/misc/RAMNetwork.ecm (nonexistent) +++ v2_0/misc/RAMNetwork.ecm (revision 1765) @@ -0,0 +1,193 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware refIDT334 ; + template default ; + package -template CYGPKG_HAL v2_0 ; + package -template CYGPKG_IO v2_0 ; + package -template CYGPKG_IO_SERIAL v2_0 ; + package -template CYGPKG_INFRA v2_0 ; + package -template CYGPKG_KERNEL v2_0 ; + package -template CYGPKG_MEMALLOC v2_0 ; + package -template CYGPKG_ISOINFRA v2_0 ; + package -template CYGPKG_LIBC v2_0 ; + package -template CYGPKG_LIBC_I18N v2_0 ; + package -template CYGPKG_LIBC_SETJMP v2_0 ; + package -template CYGPKG_LIBC_SIGNALS v2_0 ; + package -template CYGPKG_LIBC_STARTUP v2_0 ; + package -template CYGPKG_LIBC_STDIO v2_0 ; + package -template CYGPKG_LIBC_STDLIB v2_0 ; + package -template CYGPKG_LIBC_STRING v2_0 ; + package -template CYGPKG_LIBC_TIME v2_0 ; + package -template CYGPKG_LIBM v2_0 ; + package -template CYGPKG_IO_WALLCLOCK v2_0 ; + package -template CYGPKG_ERROR v2_0 ; + package -hardware CYGPKG_HAL_MIPS v2_0 ; + package -hardware CYGPKG_HAL_MIPS_IDT32334 v2_0 ; + package -hardware CYGPKG_HAL_MIPS_IDT32334_REFIDT334 v2_0 ; + package -hardware CYGPKG_IO_PCI v2_0 ; + package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 v2_0 ; + package -hardware CYGPKG_DEVS_ETH_MIPS_REFIDT334 v2_0 ; + package -hardware CYGPKG_DEVS_FLASH_MIPS_REFIDT334 v2_0 ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX v2_0 ; + package -hardware CYGPKG_IO_SERIAL_MIPS_IDT79S334A v2_0 ; + package CYGPKG_IO_FLASH v2_0 ; + package CYGPKG_IO_FILEIO v2_0 ; + package CYGPKG_IO_ETH_DRIVERS v2_0 ; + package CYGPKG_NET v2_0 ; + package CYGPKG_NET_FREEBSD_STACK v2_0 ; +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + user_value 1 GDB_stubs +}; + +cdl_option CYGHWR_HAL_MIPS_CPU_FREQ { + user_value 75 +}; + +cdl_component CYG_HAL_STARTUP { + user_value RAM +}; + +cdl_option CYGBLD_ISO_CTYPE_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_ERRNO_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_FILETYPES_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_STREAMS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_FILEACCESS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_FORMATTED_IO_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_CHAR_IO_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_DIRECT_IO_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDIO_ERROR_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRERROR_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_C_TIME_TYPES_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_C_CLOCK_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_SIGNAL_NUMBERS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_SIGNAL_IMPL_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_SETJMP_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_DIRENT_HEADER { + user_value 1 +}; + +cdl_option CYGBLD_ISO_BSDTYPES_HEADER { + user_value 1 +}; + +cdl_option CYGBLD_ISO_OPEN_MAX_HEADER { + user_value 1 +}; + +cdl_option CYGBLD_ISO_NAME_MAX_HEADER { + user_value 1 +}; + +cdl_option CYGBLD_ISO_NETDB_PROTO_HEADER { + user_value 1 +}; + +cdl_option CYGBLD_ISO_NETDB_SERV_HEADER { + user_value 1 +}; + +cdl_option CYGHWR_DEVS_FLASH_AMD_AM29F040B { + user_value 1 +}; + +cdl_component CYGPKG_NET_TFTP { + user_value 0 +}; + +cdl_component CYGPKG_NET_DHCP { + user_value 0 +}; + + Index: v2_0/misc/redboot_ROMRAM.ecm =================================================================== --- v2_0/misc/redboot_ROMRAM.ecm (nonexistent) +++ v2_0/misc/redboot_ROMRAM.ecm (revision 1765) @@ -0,0 +1,102 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware refidt334 ; + template redboot ; + package -hardware CYGPKG_HAL_MIPS v2_0 ; + package -hardware CYGPKG_HAL_MIPS_IDT32334 v2_0 ; + package -hardware CYGPKG_HAL_MIPS_IDT32334_REFIDT334 v2_0 ; + package -hardware CYGPKG_IO_PCI v2_0 ; + package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 v2_0 ; + package -hardware CYGPKG_DEVS_ETH_MIPS_REFIDT334 v2_0 ; + package -hardware CYGPKG_DEVS_FLASH_MIPS_REFIDT334 v2_0 ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX v2_0 ; + package -hardware CYGPKG_IO_SERIAL_MIPS_IDT79S334A v2_0 ; + package -template CYGPKG_HAL v2_0 ; + package -template CYGPKG_INFRA v2_0 ; + package -template CYGPKG_REDBOOT v2_0 ; + package -template CYGPKG_ISOINFRA v2_0 ; + package -template CYGPKG_LIBC_STRING v2_0 ; + package -template CYGPKG_NS_DNS v2_0 ; + package -template CYGPKG_CRC v2_0 ; + package CYGPKG_IO_ETH_DRIVERS v2_0 ; + package CYGPKG_IO_FLASH v2_0 ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGHWR_HAL_MIPS_CPU_FREQ { + user_value 75 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROMRAM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_DNS_HEADER { + inferred_value 1 +}; + +cdl_option CYGPKG_NS_DNS_BUILD { + inferred_value 0 +}; + +cdl_option CYGHWR_DEVS_FLASH_AMD_AM29F040B { + inferred_value 1 +}; + +

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