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Rev 1254 → Rev 1765

/v2_0/cdl/hal_mips_malta.cdl
0,0 → 1,358
# ====================================================================
#
# hal_mips_malta.cdl
#
# MIPS Malta board HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): dmoseley
# Original data: bartv
# Contributors: dmoseley, jskov
# Date: 2000-06-06
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_MIPS_MALTA {
display "Malta evaluation board"
parent CYGPKG_HAL_MIPS
requires { ((((CYGHWR_HAL_MIPS_MIPS32_CORE == "4Kc") || \
(CYGHWR_HAL_MIPS_MIPS32_CORE == "4Kp") || \
(CYGHWR_HAL_MIPS_MIPS32_CORE == "4Km")) && CYGPKG_HAL_MIPS_MIPS32) || \
(((CYGHWR_HAL_MIPS_MIPS64_CORE == "5K") || \
(CYGHWR_HAL_MIPS_MIPS64_CORE == "20K")) && CYGPKG_HAL_MIPS_MIPS64)) \
}
requires CYGPKG_IO_PCI
include_dir cyg/hal
description "
The Malta HAL package should be used when targetting the
actual hardware."
 
compile hal_diag.c platform.S plf_misc.c ser16c550c.c smsc37m81x.c
 
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
implements CYGINT_HAL_PLF_IF_IDE
 
cdl_option CYGBLD_HAL_TARGET_H {
display "Variant header"
flavor data
no_define
calculated { CYGPKG_HAL_MIPS_MIPS32 ? "<pkgconf/hal_mips_mips32.h>" : \
"<pkgconf/hal_mips_mips64.h>" }
define -file system.h CYGBLD_HAL_TARGET_H
description "Variant header."
 
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_mips_malta.h>"
puts $::cdl_system_header ""
puts $::cdl_system_header "/* Make sure we get the CORE type definitions for HAL_PLATFORM_CPU */"
puts $::cdl_system_header "#include CYGBLD_HAL_TARGET_H"
puts $::cdl_system_header "#define HAL_PLATFORM_BOARD \"Malta\""
puts $::cdl_system_header "#define HAL_PLATFORM_EXTRA \"\""
puts $::cdl_system_header ""
puts $::cdl_system_header "#if defined(CYGHWR_HAL_MIPS_MIPS32_CORE_4Kc)"
puts $::cdl_system_header "# define HAL_PLATFORM_CPU \"MIPS32 4Kc\""
puts $::cdl_system_header "#elif defined(CYGHWR_HAL_MIPS_MIPS32_CORE_4Kp)"
puts $::cdl_system_header "# define HAL_PLATFORM_CPU \"MIPS32 4Kp\""
puts $::cdl_system_header "#elif defined(CYGHWR_HAL_MIPS_MIPS32_CORE_4Km)"
puts $::cdl_system_header "# define HAL_PLATFORM_CPU \"MIPS32 4Km\""
puts $::cdl_system_header "#elif defined(CYGHWR_HAL_MIPS_MIPS64_CORE_5K)"
puts $::cdl_system_header "# define HAL_PLATFORM_CPU \"MIPS64 5K\""
puts $::cdl_system_header "#elif defined(CYGHWR_HAL_MIPS_MIPS64_CORE_20K)"
puts $::cdl_system_header "# define HAL_PLATFORM_CPU \"MIPS64 20K\""
puts $::cdl_system_header "#else"
puts $::cdl_system_header "# error Unknown Core"
puts $::cdl_system_header "#endif"
puts $::cdl_system_header ""
}
}
 
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
legal_values {"RAM" "ROM"}
default_value {"RAM"}
no_define
define -file system.h CYG_HAL_STARTUP
description "
Currently only ROM startup type is supported."
}
 
# The "-o file" is a workaround for CR100958 - without it the
# output file would end up in the source directory under CygWin.
# n.b. grep does not behave itself under win32
make -priority 1 {
<PREFIX>/include/cyg/hal/plf_defs.inc : <PACKAGE>/src/plf_mk_defs.c
$(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,plf_defs.tmp -o plf_mk_defs.tmp -S $<
fgrep .equ plf_mk_defs.tmp | sed s/#// > $@
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 plf_defs.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm plf_defs.tmp plf_mk_defs.tmp
}
 
cdl_option CYGHWR_HAL_MIPS_MALTA_CPU_CLOCK {
display "CPU clock speed"
flavor data
calculated 80000000
description "
This option specifies the CPU clock."
}
 
# Real-time clock/counter specifics
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants."
flavor none
cdl_option CYGNUM_HAL_RTC_NUMERATOR {
display "Real-time clock numerator"
flavor data
calculated 1000000000
}
cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
display "Real-time clock denominator"
flavor data
calculated 100
}
cdl_option CYGNUM_HAL_RTC_PERIOD {
display "Real-time clock period"
flavor data
calculated { (CYGHWR_HAL_MIPS_MALTA_CPU_CLOCK / 2) / CYGNUM_HAL_RTC_DENOMINATOR }
description "
The count and compare registers of the Malta are used
to drive the eCos kernel RTC. The count register
increments at half the CPU clock speed."
}
}
 
cdl_option CYGBLD_BUILD_GDB_STUBS {
display "Build GDB stub ROM image"
default_value 0
parent CYGBLD_GLOBAL_OPTIONS
requires { CYG_HAL_STARTUP == "ROM" }
requires CYGSEM_HAL_ROM_MONITOR
requires CYGBLD_BUILD_COMMON_GDB_STUBS
requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
no_define
description "
This option enables the building of the GDB stubs for the
board. The common HAL controls takes care of most of the
build process, but the final conversion from ELF image to
binary data is handled by the platform CDL, allowing
relocation of the data if necessary."
 
make -priority 320 {
<PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
$(OBJCOPY) -O binary $< $@
}
}
 
 
cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE {
display "Number of breakpoints supported by the HAL."
flavor data
default_value 25
description "
This option determines the number of breakpoints supported by the HAL."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
display "Number of communication channels on the board"
flavor data
calculated 2
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "
The Malta board has only one serial port. This option
chooses which port will be used to connect to a host
running GDB."
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
display "Diagnostic serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "
The Malta board has only one serial port. This option
chooses which port will be used for diagnostic output."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD {
display "Console/GDB serial port baud rate"
flavor data
legal_values 9600 19200 38400 57600 115200
default_value 38400
define CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
description "
This option controls the default baud rate used for the
Console/GDB connection."
}
 
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define
calculated { CYG_HAL_STARTUP == "RAM" ? "mips_malta_ram" : \
"mips_malta_rom" }
 
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
display "Memory layout linker script fragment"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_mips_malta_ram.ldi>" : \
"<pkgconf/mlt_mips_malta_rom.ldi>" }
}
 
cdl_option CYGHWR_MEMORY_LAYOUT_H {
display "Memory layout header file"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_mips_malta_ram.h>" : \
"<pkgconf/mlt_mips_malta_rom.h>" }
}
}
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
display "Work with a ROM monitor"
flavor booldata
legal_values { "Generic" "GDB_stubs" }
default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "RAM" }
description "
Support can be enabled for three different varieties of ROM monitor.
This support changes various eCos semantics such as the encoding
of diagnostic output, or the overriding of hardware interrupt
vectors.
Firstly there is \"Generic\" support which prevents the HAL
from overriding the hardware vectors that it does not use, to
instead allow an installed ROM monitor to handle them. This is
the most basic support which is likely to be common to most
implementations of ROM monitor.
\"GDB_stubs\" provides support when GDB stubs are
included in the ROM monitor or boot ROM."
}
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
display "Behave as a ROM monitor"
flavor bool
default_value 0
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "ROM" }
description "
Enable this option if this program is to be used as a ROM monitor,
i.e. applications will be loaded into RAM on the board, and this
ROM monitor may process exceptions or interrupts generated from the
application. This enables features such as utilizing a separate
interrupt stack when exceptions are generated."
}
 
cdl_component CYGPKG_CYGMON_HAL_OPTIONS {
display "CygMon HAL options"
flavor none
no_define
parent CYGPKG_CYGMON
active_if CYGPKG_CYGMON
description "
This option also lists the target's requirements for a valid CygMon
configuration."
 
cdl_option CYGBLD_BUILD_CYGMON_BIN {
display "Build CygMon ROM binary image"
active_if CYGBLD_BUILD_CYGMON
default_value 1
no_define
description "This option enables the conversion of the CygMon ELF
image to a binary image suitable for ROM programming."
make -priority 325 {
<PREFIX>/bin/cygmon.srec : <PREFIX>/bin/cygmon.elf
$(OBJCOPY) --strip-debug $< $(@:.bin=.img)
$(OBJCOPY) -O srec $< $@
}
}
}
 
cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
display "Redboot HAL options"
flavor none
no_define
parent CYGPKG_REDBOOT
active_if CYGPKG_REDBOOT
description "
This option lists the target's requirements for a valid Redboot
configuration."
 
cdl_option CYGBLD_BUILD_REDBOOT_BIN {
display "Build Redboot ROM binary image"
active_if CYGBLD_BUILD_REDBOOT
default_value 1
no_define
description "This option enables the conversion of the Redboot ELF
image to a binary image suitable for ROM programming."
compile -library=libextras.a
make -priority 325 {
<PREFIX>/bin/redboot.srec : <PREFIX>/bin/redboot.elf
$(OBJCOPY) --strip-all $< $(@:.srec=.img)
$(OBJCOPY) -O srec $< $@
}
}
}
 
}
/v2_0/include/plf_intr.h
0,0 → 1,303
#ifndef CYGONCE_HAL_PLF_INTR_H
#define CYGONCE_HAL_PLF_INTR_H
 
//==========================================================================
//
// plf_intr.h
//
// Malta Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jskov,
// gthomas, jlarmour, dmoseley
// Date: 2001-03-20
// Purpose: Define Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock for the Malta board.
//
// Usage:
// #include <cyg/hal/plf_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
// First an assembly safe part
 
//--------------------------------------------------------------------------
// Interrupt vectors.
 
#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
 
// These are decoded via the IP bits of the cause
// register when an external interrupt is delivered.
 
#define CYGNUM_HAL_INTERRUPT_SOUTH_BRIDGE_INTR 0
#define CYGNUM_HAL_INTERRUPT_SOUTH_BRIDGE_SMI 1
#define CYGNUM_HAL_INTERRUPT_CBUS_UART 2
#define CYGNUM_HAL_INTERRUPT_COREHI 3
#define CYGNUM_HAL_INTERRUPT_CORELO 4
#define CYGNUM_HAL_INTERRUPT_COMPARE 5
 
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE 6
 
#define CYGNUM_HAL_INTERRUPT_CTRL1_BASE 6
#define CYGNUM_HAL_INTERRUPT_TIMER 6
#define CYGNUM_HAL_INTERRUPT_KEYBOARD 7
#define CYGNUM_HAL_INTERRUPT_CASCADE 8 // this is where int ctrl2 is cascaded
#define CYGNUM_HAL_INTERRUPT_TTY1 9
#define CYGNUM_HAL_INTERRUPT_TTY0 10
#define CYGNUM_HAL_INTERRUPT_11 11
#define CYGNUM_HAL_INTERRUPT_FLOPPY 12
#define CYGNUM_HAL_INTERRUPT_PARALLEL 13
 
#define CYGNUM_HAL_INTERRUPT_CTRL2_BASE 14
#define CYGNUM_HAL_INTERRUPT_REAL_TIME_CLOCK 14
#define CYGNUM_HAL_INTERRUPT_I2C 15
#define CYGNUM_HAL_INTERRUPT_PCI_AB 16
#define CYGNUM_HAL_INTERRUPT_PCI_CD 17
#define CYGNUM_HAL_INTERRUPT_MOUSE 18
#define CYGNUM_HAL_INTERRUPT_19 19
#define CYGNUM_HAL_INTERRUPT_IDE_PRIMARY 20
#define CYGNUM_HAL_INTERRUPT_IDE_SECONDARY 21
 
#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
 
// This overlaps with CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE above but it
// doesn't matter. It's only used by the HAL to access the special
// chaining entry in the ISR tables. All other attempted access to
// the ISR table will be redirected to this entry (courtesy of
// HAL_TRANSLATE_VECTOR). The other vector definitions are still
// valid, but only for enable/disable/config etc. (i.e., in chaining
// mode they have associated entries in the ISR tables).
#define CYGNUM_HAL_INTERRUPT_CHAINING 6
 
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
(_index_) = CYGNUM_HAL_INTERRUPT_CHAINING
 
// Min/Max ISR numbers
#define CYGNUM_HAL_ISR_MIN 0
#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_CHAINING
 
#else
 
// Min/Max ISR numbers
#define CYGNUM_HAL_ISR_MIN 0
#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_IDE_SECONDARY
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
 
#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1)
 
// The vector used by the Real time clock
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE
 
#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
 
#endif
 
 
//--------------------------------------------------------------------------
#ifndef __ASSEMBLER__
 
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/plf_io.h>
 
//--------------------------------------------------------------------------
// Interrupt controller access.
 
#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 
// Array which stores the configured priority levels for the configured
// interrupts.
externC volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
 
#define HAL_INTERRUPT_MASK( _vector_ ) \
CYG_MACRO_START \
if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
{ \
asm volatile ( \
"mfc0 $3,$12\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$12\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
} \
else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_CTRL2_BASE) \
{ \
cyg_uint8 _mask_; \
cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_CTRL2_BASE; \
HAL_READ_UINT8(HAL_PIIX4_SLAVE_OCW1, _mask_ ); \
_mask_ |= (1<<_shift_); \
HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_OCW1, _mask_ ); \
} \
else /* CTRL1 */ \
{ \
cyg_uint8 _mask_; \
cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_CTRL1_BASE; \
HAL_READ_UINT8(HAL_PIIX4_MASTER_OCW1, _mask_ ); \
_mask_ |= (1<<_shift_); \
HAL_WRITE_UINT8(HAL_PIIX4_MASTER_OCW1, _mask_ ); \
} \
CYG_MACRO_END
 
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
CYG_MACRO_START \
if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
{ \
asm volatile ( \
"mfc0 $3,$12\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"or $3,$3,$2\n" \
"mtc0 $3,$12\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
} \
else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_CTRL2_BASE) \
{ \
cyg_uint8 _mask_; \
cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_CTRL2_BASE; \
HAL_READ_UINT8(HAL_PIIX4_SLAVE_OCW1, _mask_ ); \
_mask_ &= ~(1<<_shift_); \
HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_OCW1, _mask_ ); \
} \
else /* CTRL1 */ \
{ \
cyg_uint8 _mask_; \
cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_CTRL1_BASE; \
HAL_READ_UINT8(HAL_PIIX4_MASTER_OCW1, _mask_ ); \
_mask_ &= ~(1<<_shift_); \
HAL_WRITE_UINT8(HAL_PIIX4_MASTER_OCW1, _mask_ ); \
} \
CYG_MACRO_END
 
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
CYG_MACRO_START \
cyg_uint32 _srvector_ = _vector_; \
if ((_vector_) >= CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) { \
_srvector_ = CYGNUM_HAL_INTERRUPT_SOUTH_BRIDGE_INTR; \
} \
asm volatile ( \
"mfc0 $3,$13\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$13\n" \
"nop; nop; nop\n" \
: \
: "r"(_srvector_) \
: "$2", "$3" \
); \
CYG_MACRO_END
 
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
CYG_MACRO_START \
if ((_vector_) >= CYGNUM_HAL_INTERRUPT_CTRL2_BASE) \
{ \
cyg_uint8 _mask_; \
cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_CTRL2_BASE; \
HAL_READ_UINT8(HAL_PIIX4_ELCR2, _mask_ ); \
_mask_ &= ~(1<<_shift_); \
if (_level_) _mask_ |= (1<<_shift_); \
_mask_ &= HAL_PIIX4_ELCR2_MASK; \
HAL_WRITE_UINT8(HAL_PIIX4_ELCR2, _mask_ ); \
} \
else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_CTRL1_BASE) \
{ \
cyg_uint8 _mask_; \
cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_CTRL1_BASE; \
HAL_READ_UINT8(HAL_PIIX4_ELCR1, _mask_ ); \
_mask_ &= ~(1<<_shift_); \
if (_level_) _mask_ |= (1<<_shift_); \
_mask_ &= HAL_PIIX4_ELCR1_MASK; \
HAL_WRITE_UINT8(HAL_PIIX4_ELCR1, _mask_ ); \
} \
CYG_MACRO_END
 
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
 
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 
#endif
 
 
//--------------------------------------------------------------------------
// Control-C support.
 
#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT)
 
# define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_SER
 
externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
 
# define HAL_CTRLC_ISR hal_ctrlc_isr
 
#endif
 
 
//----------------------------------------------------------------------------
// Reset.
#ifndef CYGHWR_HAL_RESET_DEFINED
extern void hal_malta_reset( void );
#define CYGHWR_HAL_RESET_DEFINED
#define HAL_PLATFORM_RESET() hal_malta_reset()
 
#define HAL_PLATFORM_RESET_ENTRY 0xbfc00000
 
#endif // CYGHWR_HAL_RESET_DEFINED
 
#endif // __ASSEMBLER__
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLF_INTR_H
// End of plf_intr.h
/v2_0/include/plf_stub.h
0,0 → 1,84
#ifndef CYGONCE_HAL_PLF_STUB_H
#define CYGONCE_HAL_PLF_STUB_H
 
//=============================================================================
//
// plf_stub.h
//
// Platform header for GDB stub support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov, dmoseley
// Date: 2001-03-20
// Purpose: Platform HAL stub support for MIPS Malta boards.
// Usage: #include <cyg/hal/plf_stub.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
#include <pkgconf/hal.h>
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
 
#include <cyg/hal/mips-stub.h> // architecture stub support
 
//----------------------------------------------------------------------------
// Define some platform specific communication details. This is mostly
// handled by hal_if now, but we need to make sure the comms tables are
// properly initialized.
 
externC void cyg_hal_plf_comms_init(void);
 
#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
 
#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
 
//----------------------------------------------------------------------------
// Stub initializer.
#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT
 
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_PLF_STUB_H
// End of plf_stub.h
/v2_0/include/pkgconf/mlt_mips_malta_rom.h
0,0 → 1,25
// eCos memory layout - Mon Apr 09 14:21:03 2001
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0x80000400)
#define CYGMEM_REGION_ram_SIZE (0x1fffc00)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#define CYGMEM_REGION_rom (0x9fc00000)
#define CYGMEM_REGION_rom_SIZE (0x400000)
#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x81f00000 - (size_t) CYG_LABEL_NAME (__heap1))
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__pci_window) [];
#endif
#define CYGMEM_SECTION_pci_window (CYG_LABEL_NAME (__pci_window))
#define CYGMEM_SECTION_pci_window_SIZE (0x100000)
/v2_0/include/pkgconf/mlt_mips_malta_rom.ldi
0,0 → 1,41
// eCos memory layout - Mon Apr 09 14:21:03 2001
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0x80000400, LENGTH = 0x1fffc00
rom : ORIGIN = 0x9fc00000, LENGTH = 0x400000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (rom, 0x9fc00000, LMA_EQ_VMA)
SECTION_ROMISC (rom, ALIGN (0x40), LMA_EQ_VMA)
SECTION_RELOCS (rom, ALIGN (0x40), LMA_EQ_VMA)
SECTION_init (rom, ALIGN (0x40), LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x40), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x40), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x40), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x40), LMA_EQ_VMA)
SECTION_data (ram, 0x80000400, FOLLOWING (.rodata1))
SECTION_data1 (ram, ALIGN (0x40), FOLLOWING (.data))
SECTION_eh_frame (ram, ALIGN (0x40), FOLLOWING (.data1))
SECTION_gcc_except_table (ram, ALIGN (0x40), FOLLOWING (.eh_frame))
SECTION_ctors (ram, ALIGN (0x40), FOLLOWING (.gcc_except_table))
SECTION_dtors (ram, ALIGN (0x40), FOLLOWING (.ctors))
SECTION_devtab (ram, ALIGN (0x40), FOLLOWING (.dtors))
SECTION_got (ram, ALIGN (0x40), FOLLOWING (.devtab))
SECTION_dynamic (ram, ALIGN (0x40), FOLLOWING (.got))
SECTION_sdata (ram, ALIGN (0x40), FOLLOWING (.dynamic))
SECTION_lit8 (ram, ALIGN (0x40), FOLLOWING (.sdata))
SECTION_lit4 (ram, ALIGN (0x40), FOLLOWING (.lit8))
SECTION_sbss (ram, ALIGN (0x40), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x40), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
CYG_LABEL_DEFN(__pci_window) = 0x81f00000; . = CYG_LABEL_DEFN(__pci_window) + 0x100000;
SECTIONS_END
}
/v2_0/include/pkgconf/mlt_mips_malta_ram.h
0,0 → 1,22
// eCos memory layout - Mon Apr 09 14:17:14 2001
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0x80020000)
#define CYGMEM_REGION_ram_SIZE (0x1fe0000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x81f00000 - (size_t) CYG_LABEL_NAME (__heap1))
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__pci_window) [];
#endif
#define CYGMEM_SECTION_pci_window (CYG_LABEL_NAME (__pci_window))
#define CYGMEM_SECTION_pci_window_SIZE (0x100000)
/v2_0/include/pkgconf/mlt_mips_malta_ram.ldi
0,0 → 1,40
// eCos memory layout - Mon Apr 09 14:17:14 2001
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0x80020000, LENGTH = 0x1fe0000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (ram, 0x80020000, LMA_EQ_VMA)
SECTION_ROMISC (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_RELOCS (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_init (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_data1 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_eh_frame (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_ctors (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_dtors (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_devtab (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_got (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_dynamic (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_sdata (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_lit8 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_lit4 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
CYG_LABEL_DEFN(__pci_window) = 0x81f00000; . = CYG_LABEL_DEFN(__pci_window) + 0x100000;
SECTIONS_END
}
/v2_0/include/pkgconf/mlt_mips_malta_rom.mlt
0,0 → 1,27
version 0
region ram 80000400 1fffc00 0 !
region rom 9fc00000 400000 1 !
section data 0 40 1 1 1 1 0 1 80000400 data1 data1 !
section data1 0 40 1 1 0 1 0 1 eh_frame eh_frame !
section eh_frame 0 40 1 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 40 1 1 0 1 0 1 ctors ctors !
section ctors 0 40 1 1 0 1 0 1 dtors dtors !
section dtors 0 40 1 1 0 1 0 1 devtab devtab !
section devtab 0 40 1 1 0 1 0 1 got got !
section got 0 40 1 1 0 1 0 1 dynamic dynamic !
section dynamic 0 40 1 1 0 1 0 1 sdata sdata !
section sdata 0 40 1 1 0 1 0 1 lit8 lit8 !
section lit8 0 40 1 1 0 1 0 1 lit4 lit4 !
section lit4 0 40 1 1 0 1 0 0 sbss !
section sbss 0 40 0 1 0 1 0 1 bss bss !
section bss 0 40 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
section pci_window 100000 1 0 0 1 0 1 0 81f00000 81f00000 !
section rom_vectors 0 1 0 1 1 1 1 1 9fc00000 9fc00000 ROMISC ROMISC !
section ROMISC 0 40 0 1 0 1 0 1 RELOCS RELOCS !
section RELOCS 0 40 0 1 0 1 0 1 init init !
section init 0 40 0 1 0 1 0 1 text text !
section text 0 40 0 1 0 1 0 1 fini fini !
section fini 0 40 0 1 0 1 0 1 rodata rodata !
section rodata 0 40 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 40 0 1 0 0 0 1 data !
/v2_0/include/pkgconf/mlt_mips_malta_ram.mlt
0,0 → 1,26
version 0
region ram 80020000 1fe0000 0 !
section rom_vectors 0 1 0 1 1 1 1 1 80020000 80020000 ROMISC ROMISC !
section ROMISC 0 4 0 1 0 1 0 1 RELOCS RELOCS !
section RELOCS 0 4 0 1 0 1 0 1 init init !
section init 0 4 0 1 0 1 0 1 text text !
section text 0 4 0 1 0 1 0 1 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata rodata !
section rodata 0 8 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 8 0 1 0 1 0 1 data data !
section data 0 8 0 1 0 1 0 1 data1 data1 !
section data1 0 8 0 1 0 1 0 1 eh_frame eh_frame !
section eh_frame 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 4 0 1 0 1 0 1 ctors ctors !
section ctors 0 4 0 1 0 1 0 1 dtors dtors !
section dtors 0 4 0 1 0 1 0 1 devtab devtab !
section devtab 0 4 0 1 0 1 0 1 got got !
section got 0 4 0 1 0 1 0 1 dynamic dynamic !
section dynamic 0 4 0 1 0 1 0 1 sdata sdata !
section sdata 0 4 0 1 0 1 0 1 lit8 lit8 !
section lit8 0 8 0 1 0 1 0 1 lit4 lit4 !
section lit4 0 8 0 1 0 1 0 1 sbss sbss !
section sbss 0 8 0 1 0 1 0 1 bss bss !
section bss 0 8 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
section pci_window 100000 1 0 0 1 0 1 0 81f00000 81f00000 !
/v2_0/include/plf_cache.h
0,0 → 1,73
#ifndef CYGONCE_PLF_CACHE_H
#define CYGONCE_PLF_CACHE_H
 
//=============================================================================
//
// plf_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors:nickg
// Date: 2001-03-20
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/plf_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/plf_cache.h>
 
//=============================================================================
 
// Nothing here at present.
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_PLF_CACHE_H
// End of plf_cache.h
 
/v2_0/include/platform.inc
0,0 → 1,240
#ifndef CYGONCE_HAL_PLATFORM_INC
#define CYGONCE_HAL_PLATFORM_INC
##=============================================================================
##
## platform.inc
##
## Malta board assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): dmoseley
## Contributors:dmoseley, jskov
## Date: 2001-03-20
## Purpose: Malta board definitions.
## Description: This file contains various definitions and macros that are
## useful for writing assembly code for the Malta board.
## Usage:
## #include <cyg/hal/platform.inc>
## ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <cyg/hal/mips.inc>
 
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/plf_io.h>
 
#------------------------------------------------------------------------------
# Additional bits for status register.
# We set the IM[0] bit to accept all interrupts.
 
#define INITIAL_SR_PLF 0x00000400
 
#------------------------------------------------------------------------------
 
#define CYGPKG_HAL_RESET_VECTOR_FIRST_CODE
.macro hal_reset_vector_first_code
# Branch forward past the board ID register.
b 1f
nop
nop
nop
nop
nop
1:
.endm
 
#define CYGPKG_HAL_EARLY_INIT
.macro hal_early_init
# Do these initializations early (rather than in hal_memc_init) so
# we have access to the LEDs on the board for debugging purposes.
 
#
# WARNING: THESE WRITES NEED TO HANDLE BYTE-SWAPPING PROPERLY WHEN DOING BIG-ENDIAN
#
 
#
# Setup Galileo CPU Interface Register
#
# Set the WriteRate bit - ie Accept 'DDD' back-to-back transfers (see CoreLV "Users Manual")
# All other bits stay the same
#
li k0, CYGARC_UNCACHED_ADDRESS(HAL_GALILEO_REGISTER_BASE)
lw k1, HAL_GALILEO_CPU_INTERFACE_CONFIG_OFFSET(k0)
li k0, HAL_GALILEO_CPU_WRITERATE_MASK
or k1, k1, k0
li k0, CYGARC_UNCACHED_ADDRESS(HAL_GALILEO_REGISTER_BASE)
sw k1, HAL_GALILEO_CPU_INTERFACE_CONFIG_OFFSET(k0)
 
#
# Use BootCS chip-select for the entire device bus region
#
li k1, 0
sw k1, HAL_GALILEO_CS3_HIGH_DECODE_OFFSET(k0)
li k1, 0xf0
sw k1, HAL_GALILEO_CSBOOT_LOW_DECODE_OFFSET(k0)
li k1, 0xff
sw k1, HAL_GALILEO_CSBOOT_HIGH_DECODE_OFFSET(k0)
.endm
 
#------------------------------------------------------------------------------
# Interrupt decode macros
 
# Only INTN[0] is connected on the Malta board. We need to access the
# interrupt controller to get the actual vector number.
 
#ifndef CYGPKG_HAL_MIPS_INTC_INIT_DEFINED
 
.macro hal_intc_init
mfc0 v0,status
nop
lui v1,0xFFFF
ori v1,v1,0x04FF
and v0,v0,v1 # Clear the IntMask bits except IM[0]
mtc0 v0,status
nop
nop
nop
.endm
 
#define CYGPKG_HAL_MIPS_INTC_INIT_DEFINED
 
#endif
 
#ifndef CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
# When chaining, go through trampoline for external
# interrupts (we need to query the intc for the source)
# but let other internal vectors go directly to the
# chaining ISR.
.macro hal_intc_translate inum,vnum
beqz \inum,1f
move \vnum,\inum
ori \vnum,zero,CYGNUM_HAL_INTERRUPT_CHAINING
1:
.endm
#else
.macro hal_intc_translate inum,vnum
move \vnum,\inum # Vector == interrupt number
.endm
#endif
 
#define CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
#endif
 
// We also define our own interrupt tables in platform.S...
#define CYG_HAL_MIPS_ISR_TABLES_DEFINED
 
#------------------------------------------------------------------------------
# Diagnostic macros
 
#ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED
 
.macro hal_diag_init
.endm
 
.macro hal_diag_excpt_start
.endm
 
.macro hal_diag_intr_start
.endm
 
.macro hal_diag_restore
.endm
 
#define CYGPKG_HAL_MIPS_DIAG_DEFINED
 
#endif // ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED
#------------------------------------------------------------------------------
# MEMC macros.
#
#if defined(CYG_HAL_STARTUP_ROM)
 
#------------------------------------------------------------------------------
# Make sure the jump to _start in vectors.S is done uncached
#
 
#define CYGARC_START_FUNC_UNCACHED
 
.macro hal_memc_init
.extern hal_malta_init_sdram
 
lar k0,hal_malta_init_sdram
CYGARC_ADDRESS_REG_UNCACHED(k0)
jalr k0
nop
 
beqz v0, 2f
nop
 
# Error in sizing memory
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS0, 'M')
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS1, 'E')
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS2, 'M')
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS3, 'E')
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS4, 'R')
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS5, 'R')
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS6, 'O')
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS7, 'R')
1: b 1b
nop
 
2: # No error in sizing memory
 
# Store the memory size at the base of RAM for later
la k0, 0x80000000
move k1, k0
CYGARC_ADDRESS_REG_UNCACHED(k1)
sw v1, 0(k1)
nop
nop
nop
.endm
 
#define CYGPKG_HAL_MIPS_MEMC_DEFINED
 
#endif
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLATFORM_INC
# end of platform.inc
/v2_0/include/hal_diag.h
0,0 → 1,74
#ifndef CYGONCE_HAL_DIAG_H
#define CYGONCE_HAL_DIAG_H
 
/*=============================================================================
//
// hal_diag.h
//
// HAL Support for Kernel Diagnostic Routines
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas
// Contributors:nickg, gthomas
// Date: 2001-03-20
// Purpose: HAL Support for Kernel Diagnostic Routines
// Description: Diagnostic routines for use during kernel development.
// Usage: #include <cyg/hal/hal_diag.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/hal_if.h>
 
#define HAL_DIAG_INIT() hal_if_diag_init()
#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
 
//-----------------------------------------------------------------------------
// LED
 
externC void hal_diag_led(int n);
 
//-----------------------------------------------------------------------------
// end of hal_diag.h
#endif // CYGONCE_HAL_DIAG_H
/v2_0/include/plf_io.h
0,0 → 1,644
#ifndef CYGONCE_PLF_IO_H
#define CYGONCE_PLF_IO_H
 
//=============================================================================
//
// plf_io.h
//
// Platform specific IO support
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): dmoseley
// Contributors: dmoseley, jskov
// Date: 2001-03-20
// Purpose: Malta platform IO support
// Description:
// Usage: #include <cyg/hal/plf_io.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/hal/hal_misc.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/plf_intr.h>
 
#ifdef __ASSEMBLER__
#define HAL_REG(x) x
#define HAL_REG8(x) x
#define HAL_REG16(x) x
#else
#define HAL_REG(x) (volatile CYG_WORD *)(x)
#define HAL_REG8(x) (volatile CYG_BYTE *)(x)
#define HAL_REG16(x) (volatile CYG_WORD16 *)(x)
#endif
 
//-----------------------------------------------------------------------------
 
/* Malta Memory Definitions */
#define HAL_MALTA_RAM_BASE 0x00000000
#define HAL_MALTA_PCI_MEM0_BASE 0x08000000
#define HAL_MALTA_PCI_MEM0_SIZE 0x08000000 // 128 MB
#define HAL_MALTA_PCI_MEM1_BASE 0x10000000
#define HAL_MALTA_PCI_MEM1_SIZE 0x08000000 // 128 MB
 
#define HAL_MALTA_PCI_IO_BASE 0x18000000
#define HAL_MALTA_PCI_IO_SIZE 0x03d00000 // 62 MB
#define HAL_MALTA_CONTROLLER_BASE 0x1BE00000
#define HAL_MALTA_CONTROLLER_BASE_ISD_CONFIG (HAL_MALTA_CONTROLLER_BASE >> 21)
#define HAL_MALTA_FLASH_BASE 0x1E000000
#define HAL_MALTA_FLASH_SIZE SZ_4M
#define HAL_MALTA_MAX_BANKSIZE SZ_128M
 
#define HAL_MALTA_NULL_DEVNUM 0x0
#define HAL_MALTA_MEMERROR 1
 
// PCI registers
#define _PIIX4_PCI_ID 10
#define _PIIX4_BRIDGE 0
#define _PIIX4_IDE 1
#define _PIIX4_USB 2
#define _PIIX4_POWER 3
 
#define CYG_PCI_CFG_PIIX4_PIRQR 0x60
#define CYG_PCI_CFG_PIIX4_SERIRQC 0x64
#define CYG_PCI_CFG_PIIX4_TOM 0x69
#define CYG_PCI_CFG_PIIX4_GENCFG 0xb0
 
#define CYG_PCI_CFG_PIIX4_IDETIM 0x40
#define CYG_PCI_CFG_PIIX4_IDETIM_IDE 0x8000
#define CYG_PCI_CFG_PIIX4_IDETIM_SITRE 0x4000
#define CYG_PCI_CFG_PIIX4_IDETIM_DTE1 0x0080
#define CYG_PCI_CFG_PIIX4_IDETIM_PPE1 0x0040
#define CYG_PCI_CFG_PIIX4_IDETIM_IE1 0x0020
#define CYG_PCI_CFG_PIIX4_IDETIM_TIME1 0x0010
#define CYG_PCI_CFG_PIIX4_IDETIM_DTE0 0x0008
#define CYG_PCI_CFG_PIIX4_IDETIM_PPE0 0x0004
#define CYG_PCI_CFG_PIIX4_IDETIM_IE0 0x0002
#define CYG_PCI_CFG_PIIX4_IDETIM_TIME0 0x0001
 
#define CYG_PCI_CFG_PIIX4_SERIRQC_ENABLE 0x80
#define CYG_PCI_CFG_PIIX4_SERIRQC_CONT 0x40
 
#define CYG_PCI_CFG_PIIX4_TOM_TOM_MASK 0xf0
#define CYG_PCI_CFG_PIIX4_TOM_TOM_16M 0xf0
 
#define CYG_PCI_CFG_PIIX4_GENCFG_ISA 0x00000001
#define CYG_PCI_CFG_PIIX4_GENCFG_SERIRQ 0x00010000
 
 
 
/* Malta Registers */
#define HAL_MALTA_REGISTER_BASE 0xBF000000
 
#define HAL_MALTA_NMISTATUS_OFFSET 0x00000024
#define HAL_MALTA_NMIACK_OFFSET 0x00000104
#define HAL_MALTA_SOFTRES_OFFSET 0x00000500
#define HAL_MALTA_BRKRES_OFFSET 0x00000508
#define HAL_MALTA_REVISION_OFFSET 0x00C00010
 
#define HAL_MALTA_NMISTATUS HAL_REG(HAL_MALTA_REGISTER_BASE + HAL_MALTA_NMISTATUS_OFFSET)
#define HAL_MALTA_NMIACK HAL_REG(HAL_MALTA_REGISTER_BASE + HAL_MALTA_NMIACK_OFFSET)
#define HAL_MALTA_SOFTRES HAL_REG(HAL_MALTA_REGISTER_BASE + HAL_MALTA_SOFTRES_OFFSET)
#define HAL_MALTA_BRKRES HAL_REG(HAL_MALTA_REGISTER_BASE + HAL_MALTA_BRKRES_OFFSET)
#define HAL_MALTA_REVISION HAL_REG(HAL_MALTA_REGISTER_BASE + HAL_MALTA_REVISION_OFFSET)
 
/* Malta NMI controller fields */
#define HAL_MALTA_NMISTATUS_FLAG 0x00000001
#define HAL_MALTA_NMIACK_FLAG 0x00000001
 
/* Malta softreset fields */
#define HAL_MALTA_GORESET 0x42
 
/* Malta brkreset fields */
#define HAL_MALTA_BRKRES_DEFAULT_VALUE 0xA
 
// PIIX4 registers
#define HAL_PIIX4_REGISTER_BASE 0xb8000000
 
// PIIX4 interrupt controller stuff
#define HAL_PIIX4_MASTER_ICW1 HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x0020)
#define HAL_PIIX4_MASTER_ICW2 HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x0021)
#define HAL_PIIX4_MASTER_ICW3 HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x0021)
#define HAL_PIIX4_MASTER_ICW4 HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x0021)
#define HAL_PIIX4_MASTER_OCW3 HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x0020)
#define HAL_PIIX4_MASTER_OCW1 HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x0021)
 
#define HAL_PIIX4_SLAVE_ICW1 HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x00a0)
#define HAL_PIIX4_SLAVE_OCW3 HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x00a0)
#define HAL_PIIX4_SLAVE_ICW2 HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x00a1)
#define HAL_PIIX4_SLAVE_ICW3 HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x00a1)
#define HAL_PIIX4_SLAVE_ICW4 HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x00a1)
#define HAL_PIIX4_SLAVE_OCW1 HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x00a1)
 
#define HAL_PIIX4_MASTER_SLAVE_OFFSET 0x80
 
#define HAL_PIIX4_ELCR1 HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x04d0)
#define HAL_PIIX4_ELCR2 HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x04d1)
 
#define HAL_PIIX4_ICW1_SEL 0x10
#define HAL_PIIX4_ICW1_WR 0x01
#define HAL_PIIX4_ICW3_CASCADE 0x04
#define HAL_PIIX4_ICW3_SLAVE 0x02
#define HAL_PIIX4_ICW4_UPMODE 0x01
 
#define HAL_PIIX4_OCW3_ESSM 0x40
#define HAL_PIIX4_OCW3_SEL 0x08
#define HAL_PIIX4_OCW3_REQ 0x02
#define HAL_PIIX4_OCW3_IS 0x03
 
#define HAL_PIIX4_ELCR1_MASK 0xf8
#define HAL_PIIX4_ELCR2_MASK 0xde
 
// PIIX4 IDE interface
#define HAL_PIIX4_IDE_PRI_CMD (HAL_PIIX4_REGISTER_BASE + 0x01f0)
#define HAL_PIIX4_IDE_PRI_CTL (HAL_PIIX4_REGISTER_BASE + 0x03f4)
#define HAL_PIIX4_IDE_SEC_CMD (HAL_PIIX4_REGISTER_BASE + 0x0170)
#define HAL_PIIX4_IDE_SEC_CTL (HAL_PIIX4_REGISTER_BASE + 0x0374)
 
/* Galileo Registers */
#define HAL_GALILEO_REGISTER_BASE 0xB4000000
#define HAL_GALILEO_PCI0_MEM0_BASE 0xB2000000
 
#define HAL_GALILEO_CPU_INTERFACE_CONFIG_OFFSET 0x0
#define HAL_GALILEO_INT_SPACE_DECODE_OFFSET 0x68
#define HAL_GALILEO_CS3_HIGH_DECODE_OFFSET 0x43c
#define HAL_GALILEO_CSBOOT_LOW_DECODE_OFFSET 0x440
#define HAL_GALILEO_CSBOOT_HIGH_DECODE_OFFSET 0x444
 
/* Galileo CPU Interface config fields */
#define HAL_GALILEO_BYTE_SWAP (BIT16 | BIT0)
 
#define HAL_GALILEO_CACHEOPMAP_MASK 0x000001FF
#define HAL_GALILEO_CACHEPRES_MASK 0x00000200
#define HAL_GALILEO_WRITEMODE_MASK 0x00000800
#define HAL_GALILEO_ENDIAN_MASK 0x00001000
#define HAL_GALILEO_R5KL2_MASK 0x00004000
#define HAL_GALILEO_EXT_HIT_DELAY_MASK 0x00008000
#define HAL_GALILEO_CPU_WRITERATE_MASK 0x00010000
#define HAL_GALILEO_STOP_RETRY_MASK 0x00020000
#define HAL_GALILEO_MULTI_GT_MASK 0x00040000
#define HAL_GALILEO_SYSADCVALID_MASK 0x00080000
 
/* Galileo Memory Controller registers */
#define HAL_GALILEO_SDRAM_DUPLICATE_BANK_ADDR BIT20
#define HAL_GALILEO_SDRAM_BANK_INTERLEAVE_DIS BIT14
#define HAL_GALILEO_CPU_DECODE_SHIFT 21
#define HAL_GALILEO_DEV_DECODE_SHIFT 20
#define HAL_GALILEO_SDRAM_SRAS_TO_SCAS_DELAY_3C BIT10
#define HAL_GALILEO_SDRAM_WIDTH_64BIT BIT6
#define HAL_GALILEO_SDRAM_SRAS_PRECHARGE_3C BIT3
#define HAL_GALILEO_SDRAM_BANK0_CASLAT_2 BIT0
#define HAL_GALILEO_SDRAM_BANK0_SZ_64M BIT11
#define HAL_GALILEO_SDRAM_NUM_BANKS_4 BIT5
#define HAL_GALILEO_SDRAM_BANK0_PARITY BIT8
#define HAL_GALILEO_SDRAM_CFG_RAM_WIDTH BIT15
#define HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn BIT31
#define HAL_GALILEO_PCI0_STATUS_COMMAND_REGNUM 0x04
#define HAL_GALILEO_PCI0_BIST_REGNUM 0x0C
#define HAL_GALILEO_PCI0_SCS32_BASE_REGNUM 0x14
#define HAL_GALILEO_PCI0_CONFIG_IOEn 0x1
#define HAL_GALILEO_PCI0_CONFIG_MEMEn 0x2
#define HAL_GALILEO_PCI0_CONFIG_MasEn 0x4
#define HAL_GALILEO_PCI0_CONFIG_SErrEn 0x100
#define HAL_GALILEO_PCI0_LAT_TIMER_VAL 0x800
#define HAL_GALILEO_PCI0_TIMEOUT_RETRY_VALUE 0x00ffffff
 
#define HAL_GALILEO_SDRAM_BANK0_OFFSET 0x44c
#define HAL_GALILEO_SDRAM_BANK2_OFFSET 0x454
#define HAL_GALILEO_SDRAM_CONFIG_OFFSET 0x448
 
#define HAL_GALILEO_SCS10_LD_OFFSET 0x008
#define HAL_GALILEO_SCS10_HD_OFFSET 0x010
#define HAL_GALILEO_SCS32_LD_OFFSET 0x018
#define HAL_GALILEO_SCS32_HD_OFFSET 0x020
#define HAL_GALILEO_CS20_LD_OFFSET 0x028
#define HAL_GALILEO_CS20_HD_OFFSET 0x030
#define HAL_GALILEO_PCIIO_LD_OFFSET 0x048
#define HAL_GALILEO_PCIIO_HD_OFFSET 0x050
#define HAL_GALILEO_PCIMEM0_LD_OFFSET 0x058
#define HAL_GALILEO_PCIMEM0_HD_OFFSET 0x060
#define HAL_GALILEO_PCIMEM1_LD_OFFSET 0x080
#define HAL_GALILEO_PCIMEM1_HD_OFFSET 0x088
#define HAL_GALILEO_PCI1IO_LD_OFFSET 0x090
#define HAL_GALILEO_PCI1IO_HD_OFFSET 0x098
#define HAL_GALILEO_PCI1MEM0_LD_OFFSET 0x0a0
#define HAL_GALILEO_PCI1MEM0_HD_OFFSET 0x0a8
#define HAL_GALILEO_PCI1MEM1_LD_OFFSET 0x0b0
#define HAL_GALILEO_PCI1MEM1_HD_OFFSET 0x0b8
#define HAL_GALILEO_PCI_IO_REMAP 0x0f0
 
#define HAL_GALILEO_SCS0_LD_OFFSET 0x400
#define HAL_GALILEO_SCS0_HD_OFFSET 0x404
#define HAL_GALILEO_SCS1_LD_OFFSET 0x408
#define HAL_GALILEO_SCS1_HD_OFFSET 0x40c
#define HAL_GALILEO_SCS2_LD_OFFSET 0x410
#define HAL_GALILEO_SCS2_HD_OFFSET 0x414
#define HAL_GALILEO_SCS3_LD_OFFSET 0x418
#define HAL_GALILEO_SCS3_HD_OFFSET 0x41c
#define HAL_GALILEO_CS0_LD_OFFSET 0x420
#define HAL_GALILEO_CS0_HD_OFFSET 0x424
#define HAL_GALILEO_CS1_LD_OFFSET 0x428
#define HAL_GALILEO_CS1_HD_OFFSET 0x42c
#define HAL_GALILEO_CS2_LD_OFFSET 0x430
#define HAL_GALILEO_CS2_HD_OFFSET 0x434
 
// GALILEO PCI Internal
#define HAL_GALILEO_PCI_INTERNAL_COMMAND_OFFSET 0xC00
#define HAL_GALILEO_PCI0_TIMEOUT_RETRY_OFFSET 0xc04
#define HAL_GALILEO_PCI0_SCS10_SIZE_OFFSET 0xc08
#define HAL_GALILEO_PCI0_SCS32_SIZE_OFFSET 0xc0c
#define HAL_GALILEO_PCI0_SCS20_SIZE_OFFSET 0xc10
#define HAL_GALILEO_PCI0_CS3_SIZE_OFFSET 0xc14
#define HAL_GALILEO_BAR_ENA_OFFSET 0xc3c
# define HAL_GALILEO_BAR_ENA_SWCS3 (1 << 0)
# define HAL_GALILEO_BAR_ENA_SWCS32 (1 << 1)
# define HAL_GALILEO_BAR_ENA_SWCS10 (1 << 2)
# define HAL_GALILEO_BAR_ENA_IO (1 << 3)
# define HAL_GALILEO_BAR_ENA_MEM (1 << 4)
# define HAL_GALILEO_BAR_ENA_CS3 (1 << 5)
# define HAL_GALILEO_BAR_ENA_CS20 (1 << 6)
# define HAL_GALILEO_BAR_ENA_SCS32 (1 << 7)
# define HAL_GALILEO_BAR_ENA_SCS10 (1 << 8)
#define HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET 0xcf8
# define HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE (1 << 31)
#define HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET 0xcfc
 
// GALILEO Interrupts
#define HAL_GALILEO_IRQ_CAUSE_OFFSET 0xc18
# define HAL_GALILEO_IRQCAUSE_INTSUM (1 << 0)
# define HAL_GALILEO_IRQCAUSE_MEMOUT (1 << 1)
# define HAL_GALILEO_IRQCAUSE_DMAOUT (1 << 2)
# define HAL_GALILEO_IRQCAUSE_CPUOUT (1 << 3)
# define HAL_GALILEO_IRQCAUSE_DMA0 (1 << 4)
# define HAL_GALILEO_IRQCAUSE_DMA1 (1 << 5)
# define HAL_GALILEO_IRQCAUSE_DMA2 (1 << 6)
# define HAL_GALILEO_IRQCAUSE_DMA3 (1 << 7)
# define HAL_GALILEO_IRQCAUSE_T0 (1 << 8)
# define HAL_GALILEO_IRQCAUSE_T1 (1 << 9)
# define HAL_GALILEO_IRQCAUSE_T2 (1 << 10)
# define HAL_GALILEO_IRQCAUSE_T3 (1 << 11)
# define HAL_GALILEO_IRQCAUSE_MASRD (1 << 12)
# define HAL_GALILEO_IRQCAUSE_SLVWR (1 << 13)
# define HAL_GALILEO_IRQCAUSE_MASWR (1 << 14)
# define HAL_GALILEO_IRQCAUSE_SLVRD (1 << 15)
# define HAL_GALILEO_IRQCAUSE_AERR (1 << 16)
# define HAL_GALILEO_IRQCAUSE_MERR (1 << 17)
# define HAL_GALILEO_IRQCAUSE_MASABT (1 << 18)
# define HAL_GALILEO_IRQCAUSE_TARABT (1 << 19)
# define HAL_GALILEO_IRQCAUSE_RETRY (1 << 20)
# define HAL_GALILEO_IRQCAUSE_CPUSUM (1 << 30)
# define HAL_GALILEO_IRQCAUSE_PCISUM (1 << 31)
#define HAL_GALILEO_HIRQ_CAUSE_OFFSET 0xc98
#define HAL_GALILEO_CPUIRQ_MASK_OFFSET 0xc1c
#define HAL_GALILEO_CPUHIRQ_MASK_OFFSET 0xc9c
 
 
#define HAL_I2CFPGA_BASE 0x1f000b00
#define HAL_I2CFPGA_INP 0x00
#define HAL_I2CFPGA_OE 0x08
#define HAL_I2CFPGA_OUT 0x10
#define HAL_I2CFPGA_SEL 0x18
 
#define HAL_I2CFPGA_SEL_FPGA 0x00000001
#define HAL_I2CFPGA_SEL_SB 0x00000000
 
#define HAL_I2CFPGA_OE_SCL_OUT 0x00000002
#define HAL_I2CFPGA_OE_SCL_TRI 0x00000000
#define HAL_I2CFPGA_OE_SDA_OUT 0x00000001
#define HAL_I2CFPGA_OE_SDA_TRI 0x00000000
 
#define HAL_I2CFPGA_OUT_SCL_HIGH 0x00000002
#define HAL_I2CFPGA_OUT_SCL_LOW 0x00000000
#define HAL_I2CFPGA_OUT_SDA_HIGH 0x00000001
#define HAL_I2CFPGA_OUT_SDA_LOW 0x00000000
 
 
#define HAL_I2CFPGA_IN_SDA_MASK 0x00000001
 
#define HAL_I2CFPGA_OUT_SDA_ACK 0x00000000
#define HAL_I2CFPGA_OUT_SDA_NACK 0x00000001
#define HAL_I2CFPGA_OUT_SDA_WAIT_ACK 0x00000001
 
 
#define HAL_I2C_WRITE 0x00
#define HAL_I2C_READ 0x01
 
#define HAL_I2C_SPD_ADDRESS 0xa0
 
#define HAL_I2C_COUT_DOUT (HAL_I2CFPGA_OE_SCL_OUT|HAL_I2CFPGA_OE_SDA_OUT)
#define HAL_I2C_COUT_DIN (HAL_I2CFPGA_OE_SCL_OUT|HAL_I2CFPGA_OE_SDA_TRI)
#define HAL_I2C_CIN_DIN (HAL_I2CFPGA_OE_SCL_TRI|HAL_I2CFPGA_OE_SDA_TRI)
#define HAL_I2C_CHIGH_DHIGH (HAL_I2CFPGA_OUT_SCL_HIGH|HAL_I2CFPGA_OUT_SDA_HIGH)
#define HAL_I2C_CHIGH_DLOW (HAL_I2CFPGA_OUT_SCL_HIGH|HAL_I2CFPGA_OUT_SDA_LOW)
#define HAL_I2C_CLOW_DLOW (HAL_I2CFPGA_OUT_SCL_LOW|HAL_I2CFPGA_OUT_SDA_LOW)
#define HAL_I2C_CLOW_DHIGH (HAL_I2CFPGA_OUT_SCL_LOW|HAL_I2CFPGA_OUT_SDA_HIGH)
 
 
#define HAL_SPD_GET_NUM_ROW_BITS 3
#define HAL_SPD_GET_NUM_COL_BITS 4
#define HAL_SPD_GET_NUM_MODULE_BANKS 5
#define HAL_SPD_GET_SDRAM_WIDTH 6
#define HAL_SPD_GET_CONFIG_TYPE 11
#define HAL_SPD_GET_REFRESH_RATE 12
#define HAL_SPD_GET_ERROR_CHECK_WIDTH 14
#define HAL_SPD_GET_BURST_LENGTH 16
#define HAL_SPD_GET_NUM_DEVICE_BANKS 17
#define HAL_SPD_GET_CAS_LAT 18
#define HAL_SPD_GET_ROW_DENSITY 31
#define HAL_SPD_CONFIG_TYPE_PARITY BIT0
#define HAL_SPD_CONFIG_TYPE_ECC BIT1
#define HAL_SPD_REFRESH_RATE_125 5
#define HAL_SPD_REFRESH_RATE_62_5 4
#define HAL_SPD_REFRESH_RATE_31_3 3
#define HAL_SPD_REFRESH_RATE_15_625 0
#define HAL_SPD_REFRESH_RATE_7_8 2
#define HAL_SPD_REFRESH_RATE_3_9 1
 
#define HAL_SPD_REFRESH_COUNTER_125 (125*2)
#define HAL_SPD_REFRESH_COUNTER_62_5 (62*2)
#define HAL_SPD_REFRESH_COUNTER_31_3 (31*2)
#define HAL_SPD_REFRESH_COUNTER_15_625 (15*2)
#define HAL_SPD_REFRESH_COUNTER_7_8 (7*2)
#define HAL_SPD_REFRESH_COUNTER_3_9 (3*2)
 
/* Malta Display Registers */
#define HAL_DISPLAY_BASE (HAL_MALTA_REGISTER_BASE + 0x400)
 
#define HAL_DISPLAY_LEDGREEN_OFFSET 0x00
#define HAL_DISPLAY_LEDBAR_OFFSET 0x08
#define HAL_DISPLAY_ASCIIWORD_OFFSET 0x10
#define HAL_DISPLAY_ASCIIPOS0_OFFSET 0x18
#define HAL_DISPLAY_ASCIIPOS1_OFFSET 0x20
#define HAL_DISPLAY_ASCIIPOS2_OFFSET 0x28
#define HAL_DISPLAY_ASCIIPOS3_OFFSET 0x30
#define HAL_DISPLAY_ASCIIPOS4_OFFSET 0x38
#define HAL_DISPLAY_ASCIIPOS5_OFFSET 0x40
#define HAL_DISPLAY_ASCIIPOS6_OFFSET 0x48
#define HAL_DISPLAY_ASCIIPOS7_OFFSET 0x50
 
#define HAL_DISPLAY_LEDGREEN HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_LEDGREEN_OFFSET)
#define HAL_DISPLAY_LEDBAR HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_LEDBAR_OFFSET)
#define HAL_DISPLAY_ASCIIWORD HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIWORD_OFFSET)
#define HAL_DISPLAY_ASCIIPOS0 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS0_OFFSET)
#define HAL_DISPLAY_ASCIIPOS1 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS1_OFFSET)
#define HAL_DISPLAY_ASCIIPOS2 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS2_OFFSET)
#define HAL_DISPLAY_ASCIIPOS3 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS3_OFFSET)
#define HAL_DISPLAY_ASCIIPOS4 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS4_OFFSET)
#define HAL_DISPLAY_ASCIIPOS5 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS5_OFFSET)
#define HAL_DISPLAY_ASCIIPOS6 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS6_OFFSET)
#define HAL_DISPLAY_ASCIIPOS7 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS7_OFFSET)
 
#ifdef __ASSEMBLER__
 
# define DEBUG_ASCII_DISPLAY(register, character) \
li k0, CYGARC_UNCACHED_ADDRESS(register); \
li k1, character; \
sw k1, 0(k0); \
nop; \
nop; \
nop
 
# define DEBUG_LED_IMM(val) \
li k0, HAL_DISPLAY_LEDBAR; \
li k1, val; \
sw k1, 0(k0)
 
# define DEBUG_LED_REG(reg) \
li k0, HAL_DISPLAY_LEDBAR; \
sw reg, 0(k0)
 
# define DEBUG_HEX_DISPLAY_IMM(val) \
li k0, HAL_DISPLAY_ASCIIWORD; \
li k1, val; \
sw k1, 0(k0)
 
# define DEBUG_HEX_DISPLAY_REG(reg) \
li k0, HAL_DISPLAY_ASCIIWORD; \
sw reg, 0(k0)
 
# define DEBUG_DELAY() \
li k0, 0x20000; \
0: sub k0, k0, 1; \
bnez k0, 0b; \
nop
 
#else
 
# define DEBUG_ASCII_DISPLAY(register, character) \
*(register) = character
 
# define DEBUG_LED_IMM(val) \
*HAL_DISPLAY_LEDBAR = val
 
# define DEBUG_HEX_DISPLAY_IMM(val) \
*HAL_DISPLAY_ASCIIWORD = val
 
# define DEBUG_DELAY() \
{ \
volatile int i = 0x20000; \
while (--i) ; \
}
 
# define DEBUG_DISPLAY(str) \
{ \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS0, str[0]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS1, str[1]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS2, str[2]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS3, str[3]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS4, str[4]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS5, str[5]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS6, str[6]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS7, str[7]); \
}
 
 
#define HAL_GALILEO_PUTREG(x,y) \
(*((volatile unsigned *)(CYGARC_UNCACHED_ADDRESS(HAL_MALTA_CONTROLLER_BASE) + (x))) = (y))
#define HAL_GALILEO_GETREG(x) \
(*((volatile unsigned *)(CYGARC_UNCACHED_ADDRESS(HAL_MALTA_CONTROLLER_BASE) + (x))))
 
 
extern cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset);
extern cyg_uint16 cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset);
extern cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset);
extern void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint32 val);
extern void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint16 val);
extern void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint8 val);
 
// Initialize the PCI bus.
externC void cyg_hal_plf_pci_init(void);
#define HAL_PCI_INIT() cyg_hal_plf_pci_init()
 
// leave gap at start of IO and mem for southbridge which is beyond standards
// and not only ignores writes to the BAR, but also does not advertise use of
// any IO/memory space. That is, southbridge is hardwired at 0x18000000
 
// Map PCI device resources starting from these addresses in PCI space.
#define HAL_PCI_ALLOC_BASE_MEMORY (HAL_MALTA_PCI_MEM0_BASE + 0x20000)
#define HAL_PCI_ALLOC_BASE_IO 0x10000
 
// This is where the PCI spaces are mapped in the CPU's address space.
//
#define HAL_PCI_PHYSICAL_MEMORY_BASE CYGARC_UNCACHED_ADDRESS(0)
#define HAL_PCI_PHYSICAL_IO_BASE CYGARC_UNCACHED_ADDRESS(HAL_MALTA_PCI_IO_BASE)
 
// Read a value from the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
__val = cyg_hal_plf_pci_cfg_read_byte((__bus), (__devfn), (__offset))
#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
__val = cyg_hal_plf_pci_cfg_read_word((__bus), (__devfn), (__offset))
 
#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
__val = cyg_hal_plf_pci_cfg_read_dword((__bus), (__devfn), (__offset))
 
// Write a value to the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
cyg_hal_plf_pci_cfg_write_byte((__bus), (__devfn), (__offset), (__val))
 
#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
cyg_hal_plf_pci_cfg_write_word((__bus), (__devfn), (__offset), (__val))
 
#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
cyg_hal_plf_pci_cfg_write_dword((__bus), (__devfn), (__offset), (__val))
 
 
// Translate the PCI interrupt requested by the device (INTA#, INTB#,
// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
CYG_MACRO_START \
cyg_uint8 __req; \
HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
if (0 != __req) { \
/* Interrupt assignment as Galileo sees them. */ \
/* (From Malta User's Manual, 6.1 PCI Bus) */ \
CYG_ADDRWORD __translation[4] = { \
CYGNUM_HAL_INTERRUPT_PCI_AB, /* INTB# */ \
CYGNUM_HAL_INTERRUPT_PCI_CD, /* INTC# */ \
CYGNUM_HAL_INTERRUPT_PCI_CD, /* INTD# */ \
CYGNUM_HAL_INTERRUPT_PCI_AB}; /* INTA# */ \
\
/* The PCI lines from the different slots are wired like this */ \
/* on the PCI backplane: */ \
/* PCI_AB PCI_AB PCI_CD PCI_CD */ \
/* AMD PCnet INTA# */ \
/* I/O Slot 1 INTA# INTB# INTC# INTD# */ \
/* I/O Slot 2 INTD# INTA# INTB# INTC# */ \
/* I/O Slot 3 INTC# INTD# INTA# INTB# */ \
/* I/O Slot 4 INTB# INTC# INTD# INTA# */ \
/* */ \
/* Devsel signals are wired to, resulting in device IDs: */ \
/* AMD PCnet AD21 / dev 11 [(11+1)&3 = 0] */ \
/* I/O Slot 1 AD28 / dev 18 [(18+1)&3 = 3] */ \
/* I/O Slot 2 AD29 / dev 19 [(19+1)&3 = 0] */ \
/* I/O Slot 3 AD30 / dev 20 [(20+1)&3 = 1] */ \
/* I/O Slot 4 AD31 / dev 21 [(21+1)&3 = 2] */ \
\
__vec = __translation[((__req+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \
__valid = true; \
} else { \
/* Device will not generate interrupt requests. */ \
__valid = false; \
} \
CYG_MACRO_END
 
// Galileo GT64120 on MIPS MALTA requires special processing.
// First, it will hang when accessing device 31 on the local bus.
// Second, we need to ignore the GT64120 so we can set it up
// outside the generic PCI library.
#define HAL_PCI_IGNORE_DEVICE(__bus, __dev, __fn) \
((__bus) == 0 && ((__dev) == 0 || (__dev) == 31))
 
// Bus address translation macros
#define HAL_PCI_CPU_TO_BUS(__cpu_addr, __bus_addr) \
CYG_MACRO_START \
(__bus_addr) = CYGARC_PHYSICAL_ADDRESS((cyg_uint32)__cpu_addr); \
CYG_MACRO_END
 
#define HAL_PCI_BUS_TO_CPU(__bus_addr, __cpu_addr) \
CYG_MACRO_START \
(__cpu_addr) = CYGARC_UNCACHED_ADDRESS(__bus_addr); \
CYG_MACRO_END
 
 
// IDE interface macros
//
#define HAL_IDE_NUM_CONTROLLERS 2
 
// Initialize the IDE controller(s).
externC void cyg_hal_plf_ide_init(void);
#define HAL_IDE_INIT() cyg_hal_plf_ide_init()
 
#define HAL_IDE_READ_UINT8( __ctlr, __regno, __val ) \
__val = *HAL_REG8(((__ctlr) ? HAL_PIIX4_IDE_SEC_CMD : HAL_PIIX4_IDE_PRI_CMD) + (__regno))
#define HAL_IDE_READ_UINT16( __ctlr, __regno, __val ) \
__val = *HAL_REG16(((__ctlr) ? HAL_PIIX4_IDE_SEC_CMD : HAL_PIIX4_IDE_PRI_CMD) + (__regno))
#define HAL_IDE_READ_ALTSTATUS( __ctlr, __val ) \
__val = *HAL_REG16(((__ctlr) ? HAL_PIIX4_IDE_SEC_CTL : HAL_PIIX4_IDE_PRI_CTL) + 2)
 
#define HAL_IDE_WRITE_UINT8( __ctlr, __regno, __val ) \
*HAL_REG8( ((__ctlr) ? HAL_PIIX4_IDE_SEC_CMD : HAL_PIIX4_IDE_PRI_CMD) + (__regno)) = (__val)
#define HAL_IDE_WRITE_UINT16( __ctlr, __regno, __val ) \
*HAL_REG16( ((__ctlr) ? HAL_PIIX4_IDE_SEC_CMD : HAL_PIIX4_IDE_PRI_CMD) + (__regno)) = (__val)
#define HAL_IDE_WRITE_CONTROL( __ctlr, __val ) \
*HAL_REG8( ((__ctlr) ? HAL_PIIX4_IDE_SEC_CTL : HAL_PIIX4_IDE_PRI_CTL) + 2) = (__val)
 
#endif
 
//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_PLF_IO_H
/v2_0/ChangeLog
0,0 → 1,323
2002-08-06 Gary Thomas <gary@chez-thomas.org>
2002-08-06 Motoya Kurotsu <kurotsu@allied-telesis.co.jp>
 
* src/ser16c550c.c: I/O channel data can't be constant - contains
timeout information which can be changed.
 
2002-02-11 Jesper Skov <jskov@redhat.com>
 
* include/platform.inc: Added hal_intc_translate that knows about
the special trampoline code.
 
* include/plf_intr.h: Updated comment.
 
2002-02-05 Jesper Skov <jskov@redhat.com>
 
* include/plf_intr.h: Always define the vectors, regardless of
chaining configuration.
 
2002-01-31 Jesper Skov <jskov@redhat.com>
 
* src/platform.S (hal_isr_springboard_southbridge): Apply mask to
interrupt flags - I've seen requests set for masked
interrupts. Also don't check the slave controller unless the
cascade request is set.
 
2001-12-06 Nick Garnett <nickg@redhat.com>
 
* images/redboot_RAM_5kc.elf
* images/redboot_RAM_5kc.srec
* images/redboot_ROM_5kc.elf
* images/redboot_ROM_5kc.fl
* images/redboot_ROM_5kc.srec
Added these images for 5kc target.
 
* images/redboot_RAM.elf
* images/redboot_RAM.srec
* images/redboot_ROM.elf
* images/redboot_ROM.fl
* images/redboot_ROM.srec
Updated these images to match the 5kc ones. These images are for
Malta boards with the 4kc processor. These will actually run in a
5kc, but will treat it as a 32bit CPU, and will not provide 64bit
state to GDB.
2001-12-04 Nick Garnett <nickg@redhat.com>
 
* misc/redboot_ROM.ecm: Commented out CYGSEM_REDBOOT_DISK_ISO9660
since its presence causes CDL and compilation errors.
 
2001-11-06 Mark Salter <msalter@redhat.com>
 
* misc/redboot_ROM.ecm: Cleanup to support both mips32 and mips64.
* misc/redboot_RAM.ecm: Ditto.
 
2001-10-31 Jonathan Larmour <jlarmour@redhat.com>
 
* cdl/hal_mips_malta.cdl: Indicate support of variable baud rates.
 
2001-07-24 Mark Salter <msalter@redhat.com>
 
* src/plf_misc.c (cyg_hal_plf_ide_init): New function to enable IDE
controllers.
(cyg_hal_plf_pci_init): Move ISA bridge setup from cyg_hal_plf_pci_init
* include/plf_io.h: Add IDE i/f macros.
* cdl/hal_mips_malta.cdl: Now implements CYGINT_HAL_PLF_IF_IDE.
 
2001-07-17 David Woodhouse <dwmw2@redhat.com>
 
* src/redboot_cmds.c: Remove. Superseded by generic MIPS exec.
* cdl/hal_mips_malta.cdl: Remove reference to $1
 
2001-07-13 Jesper Skov <jskov@redhat.com>
 
* include/plf_io.h (HAL_PCI_ALLOC_BASE_IO): Reserve 64kB for
southbridge instead of 8kB.
 
2001-07-12 Jesper Skov <jskov@redhat.com>
 
* include/plf_io.h: Fix errors.
 
2001-07-05 Jesper Skov <jskov@redhat.com>
 
* include/plf_io.h: Added PCI/CPU address translation macros.
 
2001-06-27 Mark Salter <msalter@redhat.com>
 
* misc/redboot_RAM.ecm (CYGSEM_REDBOOT_BSP_SYSCALLS): Enable GNUPro
syscalls.
* misc/redboot_ROM.ecm (CYGSEM_REDBOOT_BSP_SYSCALLS): Ditto.
 
2001-06-06 Jesper Skov <jskov@redhat.com>
 
* include/plf_io.h (HAL_PCI_TRANSLATE_INTERRUPT): Defined.
 
* include/plf_intr.h: Made safe to include from assembly files.
* src/plf_mk_defs.c (main): Deleted interrupt vector definitions.
 
* src/ser16c550c.c: Fix warning.
 
* src/platform.S: Add .noreorder statements.
 
2001-06-05 Jesper Skov <jskov@redhat.com>
 
* src/platform.S (hal_isr_springboard_southbridge): Use delay
slots, return 0 for spurious interrupts.
 
2001-06-01 Jesper Skov <jskov@redhat.com>
 
* src/plf_mk_defs.c: Added CYGNUM_HAL_INTERRUPT_CASCADE.
 
* src/plf_misc.c (hal_init_irq): Fix enabling of cascading
interrupts from secondary controller.
 
* src/platform.S (hal_isr_springboard_southbridge): Fixed decoding
of secondary sources. Bail out on spurious interrups.
 
2001-04-26 Mark Salter <msalter@redhat.com>
 
* include/plf_io.h (HAL_PCI_ALLOC_BASE_MEMORY): Fix typo.
 
* cdl/hal_mips_malta.cdl (CYGNUM_HAL_RTC_PERIOD): Fix calculation to
be based on one half of the CPU clock frequency.
2001-04-23 Mark Salter <msalter@redhat.com>
 
* include/plf_io.h: Adjust PCI memory and io base constants so that
CPU/PCI addresses match the GT64120 setup. Change PCI memory alloc
base to allow for memory used by south bridge.
 
2001-04-11 Jesper Skov <jskov@redhat.com>
 
* src/plf_mk_defs.c: Added a few more defs.
 
* src/platform.S: Added southbridge springboard for interrupt
decoding.
 
* include/plf_io.h: Carve out a bit of memory at 0 in the PCI IO
space. Otherwise PCI devices get assigned space which the lana
southbridge is hardwired to. Also moved PCI register defs to this
file.
* src/plf_misc.c: Added PCI interrupt routing setup.
 
2001-04-10 Jesper Skov <jskov@redhat.com>
 
* src/ser16c550c.c (cyg_hal_plf_serial_init_channel): Allow
interrupts.
 
* include/plf_io.h (HAL_PIIX4_ELCR2): Fix typo.
 
* src/plf_misc.c (hal_init_irq): Added.
(hal_init_irq): Use byte access to SERIRQ.
 
* include/plf_io.h: Replaced interrupt definitions.
 
* include/plf_intr.h: Proper interrupt handling.
 
* include/platform.inc: Removed hal_intc_decode.
 
* misc/redboot_RAM.ecm: Added decompression support.
* misc/redboot_ROM.ecm: Same.
 
* include/pkgconf/mlt_mips_malta_ram.mlt: Give RedBoot even more
space.
* include/pkgconf/mlt_mips_malta_ram.ldi: Same.
* include/pkgconf/mlt_mips_malta_ram.h: Same.
 
2001-04-09 Jesper Skov <jskov@redhat.com>
 
* include/pkgconf/mlt_mips_malta_ram.h: Changed base address.
* include/pkgconf/mlt_mips_malta_ram.mlt: Same.
* include/pkgconf/mlt_mips_malta_ram.ldi: Same.
 
* misc/redboot_ROM.ecm: Updated.
 
* include/pkgconf/mlt_mips_malta_rom.h: Updated.
* include/pkgconf/mlt_mips_malta_rom.ldi: Same.
* include/pkgconf/mlt_mips_malta_rom.mlt: Same.
* include/pkgconf/mlt_mips_malta_ram.h: Updated.
* include/pkgconf/mlt_mips_malta_ram.ldi: Same.
* include/pkgconf/mlt_mips_malta_ram.mlt: Same.
 
* src/plf_mk_defs.c: Added.
* cdl/hal_mips_malta.cdl: Build mk_defs file.
* src/platform.S: Get table size def from header.
 
2001-04-03 Jesper Skov <jskov@redhat.com>
 
* misc/redboot_RAM.ecm: Added net packages.
 
* include/pkgconf/mlt_mips_malta_ram.h: Hacked in some PCI memory.
* include/pkgconf/mlt_mips_malta_ram.ldi: Same.
 
2001-04-02 Jesper Skov <jskov@redhat.com>
 
* src/ser16c550c.c: Removed debug channel definitions, added
second port.
 
* include/plf_intr.h: Removed UART vector.
 
* src/plf_misc.c: Moved SMSC superIO init code...
* src/smsc37m81x.c (cyg_hal_init_superIO): to here.
* cdl/hal_mips_malta.cdl: Compile new file.
 
2001-03-23 Jesper Skov <jskov@redhat.com>
 
* src/plf_misc.c (hal_platform_init): Initialize PIIX4 and set up
COM1 for the SMSC SuperIO part. Now we have serial output. Wohoo!
 
* include/plf_io.h: Added a few new definitions.
 
* src/platform.S: Enable Galileo as PCI master. Make all PCI IO be
offset from zero to make PIIX4 happy.
 
* include/plf_intr.h (CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE): Added.
 
* misc/redboot_ROM.ecm: Updated.
 
* src/platform.S: Use correct ISR count (hack).
 
* include/platform.inc: Remove RAM SDRAM init hack.
 
* src/platform.S: SDP: Fix sizing logic.
 
* include/plf_io.h (HAL_SPD_GET_SDRAM_WIDTH): Changed to width of
DIMM instead of width of individual SDRAM devices.
 
2001-03-22 Jesper Skov <jskov@redhat.com>
 
* src/platform.S: Remove some of the hacks.
 
* include/plf_io.h (HAL_I2C_READ, HAL_I2C_WRITE): Get these right,
and the code works. Sheesh!
 
* src/platform.S: Minor tweaks to make I2C code match that in
YAMON. Still doesn't work though.
 
* include/platform.inc: Hacked to enable SDRAM init.
 
* src/platform.S: Rewrote to use simpler macros.
 
* src/plf_misc.c: Removed some CYGMON stuff.
 
* include/plf_io.h: Added simpler definitions for I2C access.
 
* src/plf_misc.c (hal_platform_init): Fix warning.
 
* src/platform.S: Rewrote I2C code for FPGA controller.
 
* include/pkgconf/mlt_mips_malta_rom.h: Updated.
* include/pkgconf/mlt_mips_malta_rom.mlt: Same.
* include/pkgconf/mlt_mips_malta_rom.ldi: Same.
 
* include/plf_io.h: Added I2C definitions for FPGA I2C
controller.
 
* cdl/hal_mips_malta.cdl: Added clock option.
 
2001-03-21 Jesper Skov <jskov@redhat.com>
 
* misc/redboot_RAM.ecm: Updated.
 
* src/plf_misc.c: Always init PCI. Wait for reset.
 
2001-03-20 Jesper Skov <jskov@redhat.com>
 
* src/ser16c550c.c: Work with either the debug UART (untested) or
the SuperIO controllers. Clean up baud rate stuff.
 
* src/plf_misc.c (cyg_hal_plf_pci_init): Disable init code for
now.
 
* include/platform.inc: Removed ROMRAM startup stuff.
 
* cdl/hal_mips_malta.cdl: Changed some default settings.
 
* src/plf_misc.c: Removed test code and CYGMON init code.
 
* misc/redboot_RAM.ecm: Updated with new options.
 
* src/ser16c550c.c: Changes to use SuperIO in PCI space.
 
* cdl/hal_mips_malta.cdl: Replace old baud rate options with
CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD.
* src/redboot_cmds.c (do_exec): Use
CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD.
 
* Package cloned from Atlas package.
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/v2_0/src/ser16c550c.c
0,0 → 1,571
//=============================================================================
//
// ser16c550c.c
//
// Simple driver for the 16c550c serial controllers on the Malta board
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): dmoseley
// Contributors:dmoseley, jskov
// Date: 2001-03-20
// Description: Simple driver for the 16c550c serial controller
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H
 
#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_if.h> // interface API
#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
#include <cyg/hal/hal_misc.h> // Helper functions
#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
 
//-----------------------------------------------------------------------------
// Define the serial registers. The Malta board is equipped with a 16550C
// serial chip.
#define MALTA_SER_CLOCK 1843200
#define MALTA_SER_16550_BASE_A 0xb80003f8
#define MALTA_SER_16550_BASE_B 0xb80002f8
#define SER_16550_RBR 0x00 // receiver buffer register, read, dlab = 0
#define SER_16550_THR 0x00 // transmitter holding register, write, dlab = 0
#define SER_16550_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
#define SER_16550_IER 0x01 // interrupt enable register, read/write, dlab = 0
#define SER_16550_DLM 0x01 // divisor latch (MS), read/write, dlab = 1
#define SER_16550_IIR 0x02 // interrupt identification reg, read, dlab = 0
#define SER_16550_FCR 0x02 // fifo control register, write, dlab = 0
#define SER_16550_AFR 0x02 // alternate function reg, read/write, dlab = 1
#define SER_16550_LCR 0x03 // line control register, read/write
#define SER_16550_MCR 0x04 // modem control register, read/write
#define SER_16550_LSR 0x05 // line status register, read
#define SER_16550_MSR 0x06 // modem status register, read
#define SER_16550_SCR 0x07 // scratch pad register
 
// The interrupt enable register bits.
#define SIO_IER_ERDAI 0x01 // enable received data available irq
#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
#define SIO_IER_ELSI 0x04 // enable receiver line status irq
#define SIO_IER_EMSI 0x08 // enable modem status interrupt
 
// The interrupt identification register bits.
#define SIO_IIR_IP 0x01 // 0 if interrupt pending
#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
 
// The line status register bits.
#define SIO_LSR_DR 0x01 // data ready
#define SIO_LSR_OE 0x02 // overrun error
#define SIO_LSR_PE 0x04 // parity error
#define SIO_LSR_FE 0x08 // framing error
#define SIO_LSR_BI 0x10 // break interrupt
#define SIO_LSR_THRE 0x20 // transmitter holding register empty
#define SIO_LSR_TEMT 0x40 // transmitter register empty
#define SIO_LSR_ERR 0x80 // any error condition
 
// The modem status register bits.
#define SIO_MSR_DCTS 0x01 // delta clear to send
#define SIO_MSR_DDSR 0x02 // delta data set ready
#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
#define SIO_MSR_DDCD 0x08 // delta data carrier detect
#define SIO_MSR_CTS 0x10 // clear to send
#define SIO_MSR_DSR 0x20 // data set ready
#define SIO_MSR_RI 0x40 // ring indicator
#define SIO_MSR_DCD 0x80 // data carrier detect
 
// The line control register bits.
#define SIO_LCR_WLS0 0x01 // word length select bit 0
#define SIO_LCR_WLS1 0x02 // word length select bit 1
#define SIO_LCR_STB 0x04 // number of stop bits
#define SIO_LCR_PEN 0x08 // parity enable
#define SIO_LCR_EPS 0x10 // even parity select
#define SIO_LCR_SP 0x20 // stick parity
#define SIO_LCR_SB 0x40 // set break
#define SIO_LCR_DLAB 0x80 // divisor latch access bit
 
// The FIFO control register
#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
 
/////////////////////////////////////////
// Interrupt Enable Register
#define IER_RCV 0x01
#define IER_XMT 0x02
#define IER_LS 0x04
#define IER_MS 0x08
 
// Line Control Register
#define LCR_WL5 0x00 // Word length
#define LCR_WL6 0x01
#define LCR_WL7 0x02
#define LCR_WL8 0x03
#define LCR_SB1 0x00 // Number of stop bits
#define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words
#define LCR_SB2 0x04
#define LCR_PN 0x00 // Parity mode - none
#define LCR_PE 0x0C // Parity mode - even
#define LCR_PO 0x08 // Parity mode - odd
#define LCR_PM 0x28 // Forced "mark" parity
#define LCR_PS 0x38 // Forced "space" parity
#define LCR_DL 0x80 // Enable baud rate latch
 
// Line Status Register
#define LSR_RSR 0x01
#define LSR_THE 0x20
 
// Modem Control Register
#define MCR_DTR 0x01
#define MCR_RTS 0x02
#define MCR_INT 0x08 // Enable interrupts
#define MCR_AFE 0x20
 
// Interrupt status register
#define ISR_None 0x01
#define ISR_Rx_Line_Status 0x06
#define ISR_Rx_Avail 0x04
#define ISR_Rx_Char_Timeout 0x0C
#define ISR_Tx_Empty 0x02
#define IRS_Modem_Status 0x00
 
// FIFO control register
#define FCR_ENABLE 0x01
#define FCR_CLEAR_RCVR 0x02
#define FCR_CLEAR_XMIT 0x04
 
#define CYG_DEV_SERIAL_BAUD_DIVISOR (MALTA_SER_CLOCK/16/CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD)
 
//-----------------------------------------------------------------------------
typedef struct {
cyg_uint8* base;
cyg_int32 msec_timeout;
int isr_vector;
} channel_data_t;
 
static channel_data_t channels[2] = {
{ (cyg_uint8*)MALTA_SER_16550_BASE_A, 1000, CYGNUM_HAL_INTERRUPT_TTY0},
{ (cyg_uint8*)MALTA_SER_16550_BASE_B, 1000, CYGNUM_HAL_INTERRUPT_TTY1}
};
 
//-----------------------------------------------------------------------------
// Set the baud rate
 
static void
cyg_hal_plf_serial_set_baud(cyg_uint8* port, cyg_uint16 baud_divisor)
{
cyg_uint8 _lcr;
 
HAL_READ_UINT8(port+SER_16550_LCR, _lcr);
_lcr |= LCR_DL;
HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);
 
HAL_WRITE_UINT8(port+SER_16550_DLM, baud_divisor >> 8);
HAL_WRITE_UINT8(port+SER_16550_DLL, baud_divisor & 0xff);
 
_lcr &= ~LCR_DL;
HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);
}
 
//-----------------------------------------------------------------------------
// The minimal init, get and put functions. All by polling.
 
void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
cyg_uint8* port;
cyg_uint8 _lcr;
 
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
 
port = ((channel_data_t*)__ch_data)->base;
 
// Disable port interrupts while changing hardware
HAL_WRITE_UINT8(port+SER_16550_IER, 0);
 
// Set databits, stopbits and parity.
_lcr = LCR_WL8 | LCR_SB1 | LCR_PN;
HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr);
 
// Set baud rate.
cyg_hal_plf_serial_set_baud(port, CYG_DEV_SERIAL_BAUD_DIVISOR);
 
// Enable and clear FIFO
HAL_WRITE_UINT8(port+SER_16550_FCR, (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT));
 
// enable RTS to keep host side happy. Also allow interrupts
HAL_WRITE_UINT8( port+SER_16550_MCR, MCR_DTR | MCR_RTS | MCR_INT);
// Don't allow interrupts.
HAL_WRITE_UINT8(port+SER_16550_IER, 0);
}
 
void
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch)
{
cyg_uint8* port;
cyg_uint8 _lsr;
 
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
 
port = ((channel_data_t*)__ch_data)->base;
 
CYGARC_HAL_SAVE_GP();
 
do {
HAL_READ_UINT8(port+SER_16550_LSR, _lsr);
} while ((_lsr & SIO_LSR_THRE) == 0);
 
// Now, the transmit buffer is empty
HAL_WRITE_UINT8(port+SER_16550_THR, __ch);
 
// Hang around until the character has been safely sent.
do {
HAL_READ_UINT8(port+SER_16550_LSR, _lsr);
} while ((_lsr & SIO_LSR_THRE) == 0);
 
CYGARC_HAL_RESTORE_GP();
}
 
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
cyg_uint8* port;
cyg_uint8 _lsr;
 
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
 
port = ((channel_data_t*)__ch_data)->base;
 
HAL_READ_UINT8(port+SER_16550_LSR, _lsr);
if ((_lsr & SIO_LSR_DR) == 0)
return false;
 
HAL_READ_UINT8(port+SER_16550_RBR, *ch);
 
return true;
}
 
cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
cyg_uint8 ch;
CYGARC_HAL_SAVE_GP();
 
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
 
while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
 
CYGARC_HAL_RESTORE_GP();
return ch;
}
 
static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
 
while(__len-- > 0)
cyg_hal_plf_serial_putc(__ch_data, *__buf++);
 
CYGARC_HAL_RESTORE_GP();
}
 
static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
 
while(__len-- > 0)
*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
 
CYGARC_HAL_RESTORE_GP();
}
 
 
cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
int delay_count;
channel_data_t* chan;
cyg_bool res;
CYGARC_HAL_SAVE_GP();
 
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
 
chan = (channel_data_t*)__ch_data;
 
delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
 
for(;;) {
res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
if (res || 0 == delay_count--)
break;
CYGACC_CALL_IF_DELAY_US(100);
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan;
cyg_uint8 ier;
int ret = 0;
CYGARC_HAL_SAVE_GP();
 
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
 
chan = (channel_data_t*)__ch_data;
 
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
 
HAL_READ_UINT8(chan->base + SER_16550_IER, ier);
ier |= SIO_IER_ERDAI;
HAL_WRITE_UINT8(chan->base + SER_16550_IER, ier);
 
HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
 
HAL_READ_UINT8(chan->base + SER_16550_IER, ier);
ier &= ~SIO_IER_ERDAI;
HAL_WRITE_UINT8(chan->base + SER_16550_IER, ier);
 
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
 
va_start(ap, __func);
 
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
 
va_end(ap);
}
break;
case __COMMCTL_SETBAUD:
{
cyg_uint32 baud_rate;
cyg_uint16 baud_divisor;
cyg_uint8* port = chan->base;
va_list ap;
 
va_start(ap, __func);
baud_rate = va_arg(ap, cyg_uint32);
va_end(ap);
 
baud_divisor = (MALTA_SER_CLOCK / 16 / baud_rate);
 
HAL_WRITE_UINT32(HAL_MALTA_BRKRES, 0);
#if 0
//
// We may need to increase the timeout before causing a break reset.
// According to the Malta Users Manual (Document MD00005) The BRKRES
// register will need to be programmed with a value larger that 0xA (the default)
// if we are going to use a baud rate lower than 2400.
//
if (baud_rate <= 2400)
{
// For now, just disable the break reset entirely.
HAL_WRITE_UINT32(HAL_MALTA_BRKRES, 0);
} else {
// Put the break reset state back to the default
HAL_WRITE_UINT32(HAL_MALTA_BRKRES, HAL_MALTA_BRKRES_DEFAULT_VALUE);
}
#endif
// Disable port interrupts while changing hardware
HAL_READ_UINT8(port+SER_16550_IER, ier);
HAL_WRITE_UINT8(port+SER_16550_IER, 0);
 
// Set baud rate.
cyg_hal_plf_serial_set_baud(port, baud_divisor);
 
// Reenable interrupts if necessary
HAL_WRITE_UINT8(port+SER_16550_IER, ier);
}
break;
 
case __COMMCTL_GETBAUD:
break;
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
 
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
cyg_uint8 _iir, c;
channel_data_t* chan;
CYGARC_HAL_SAVE_GP();
 
// Some of the diagnostic print code calls through here with no idea what the ch_data is.
// Go ahead and assume it is channels[0].
if (__ch_data == 0)
__ch_data = (void*)&channels[0];
 
chan = (channel_data_t*)__ch_data;
 
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
 
HAL_READ_UINT8(chan->base + SER_16550_IIR, _iir);
_iir &= SIO_IIR_ID_MASK;
 
*__ctrlc = 0;
if ((_iir == ISR_Rx_Avail) || (_iir == ISR_Rx_Char_Timeout)) {
 
HAL_READ_UINT8(chan->base + SER_16550_RBR, c);
if( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
 
res = CYG_ISR_HANDLED;
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 
// Disable interrupts.
HAL_INTERRUPT_MASK(channels[0].isr_vector);
HAL_INTERRUPT_MASK(channels[1].isr_vector);
 
// Init channels
cyg_hal_plf_serial_init_channel((void*)&channels[0]);
cyg_hal_plf_serial_init_channel((void*)&channels[1]);
// Setup procs in the vector table
 
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 
// Set channel 1
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
 
void
cyg_hal_plf_comms_init(void)
{
static int initialized = 0;
 
if (initialized)
return;
 
initialized = 1;
 
cyg_hal_plf_serial_init();
}
 
//-----------------------------------------------------------------------------
// end of ser16c550c.c
 
/v2_0/src/platform.S
0,0 → 1,792
##
#=============================================================================
## platform.S
##
## MIPS Malta platform code
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): dmoseley
## Contributors:dmoseley, jskov
## Date: 2001-03-20
## Purpose: MIPS Malta platform code
## Description: Platform specific code for Malta board.
##
##
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <pkgconf/system.h>
#include <pkgconf/hal.h>
 
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
#endif
 
#include <cyg/hal/arch.inc>
#include <cyg/hal/plf_io.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/plf_defs.inc>
#include CYGBLD_HAL_PLATFORM_H
 
##-----------------------------------------------------------------------------
 
##-----------------------------------------------------------------------------
# Platform Initialization.
# This code performs platform specific initialization.
 
##-----------------------------------------------------------------------------
## I2C accessors - these need to delay after accessing the controller.
// Need to delay between clocking the serial bits since the CPU is way too
// fast for the I2C interface. CPU runs at CYGHWR_HAL_MIPS_MALTA_CPU_CLOCK
// and the I2C no fasten than 1.7MHz. We want to delay the CPU for half
// an I2C cycle and two instructions are executed per loop, hence:
 
#define PAUSE \
li t0, (20*(CYGHWR_HAL_MIPS_MALTA_CPU_CLOCK/1700000/2/2)); \
99: bne t0, zero, 99b; \
addiu t0, -1
 
 
#define I2C_OE(v) \
li t0,v; \
sw t0,HAL_I2CFPGA_OE(a1); \
PAUSE
 
#define I2C_OUT(v) \
li t0,v; \
sw t0,HAL_I2CFPGA_OUT(a1); \
PAUSE
 
#define I2C_IN(v) \
lw v,HAL_I2CFPGA_INP(a1); \
andi v,v,HAL_I2CFPGA_IN_SDA_MASK; \
PAUSE
 
#define I2C_ENABLE \
I2C_OE(HAL_I2C_CIN_DIN); \
I2C_OUT(HAL_I2C_CHIGH_DHIGH); \
li t0,HAL_I2CFPGA_SEL_FPGA; \
sw t0,HAL_I2CFPGA_SEL(a1); \
PAUSE
 
##-----------------------------------------------------------------------------
## MEMC initialization.
##
 
#if defined(CYG_HAL_STARTUP_ROM)
 
.text
.set noreorder
 
.macro MASK_WRITE_PCI_REG regnum, devnum, mask
.set noreorder
# First, read the appropriate register
li t0, HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn | \regnum | \devnum
sw t0, HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET(s7)
lw t1, HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET(s7)
 
# Now, mask in the appropriate bits
li t2, \mask
or t1, t2
 
# Write the updated value
li t0, HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn | \regnum | \devnum
sw t0, HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET(s7)
sw t1, HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET(s7)
.endm
 
.macro WRITE_PCI_REG regnum, devnum, base
.set noreorder
li t0, HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn | \regnum | \devnum
li t1, \base
sw t0, HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET(s7)
sw t1, HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET(s7)
.endm
 
#define NO_MASK 0
#define NO_ERROR_CHECK 0
#define ERROR_CHECK 1
.macro READ_SPD_VALUE func, mask, ret_reg, err_check
.set noreorder
jal read_spd_value
li a0, \func # delay slot
.if \err_check
beq v0, zero, error
nop
.endif
move \ret_reg, v0
.if \mask
and \ret_reg, \mask
.endif
.endm
 
##-----------------------------------------------------------------------------
##
## Initialize the RAM.
##
## To do that, we need to first initialize the Galileo PCI stuff to gain access
## to the SAA9730.
## From there, use the I2C bus of the SAA9730 to read the SPD SDRAM
## config data. We then setup the Galileo SDRAM configuration
##
## Returns
## v0 = Error Code
## v1 = SDRAM size
##
FUNC_START(hal_malta_init_sdram)
 
.set noreorder
 
# Save the return address
move s8, ra
 
# Setup the base address registers
li s7, CYGARC_UNCACHED_ADDRESS(HAL_GALILEO_REGISTER_BASE)
#
# Change the Galileo Base address to HAL_MALTA_CONTROLLER_BASE
#
li t0, HAL_MALTA_CONTROLLER_BASE_ISD_CONFIG
sw t0, HAL_GALILEO_INT_SPACE_DECODE_OFFSET(s7)
li s7, CYGARC_UNCACHED_ADDRESS(HAL_MALTA_CONTROLLER_BASE)
 
# Setup the Galileo controller Endian configuration
li t0, (HAL_GALILEO_BYTE_SWAP)
sw t0, HAL_GALILEO_PCI_INTERNAL_COMMAND_OFFSET(s7)
 
# Setup the PCI_0 Timeout and retry configuration
li t0, HAL_GALILEO_PCI0_TIMEOUT_RETRY_VALUE
sw t0, HAL_GALILEO_PCI0_TIMEOUT_RETRY_OFFSET(s7)
 
# Setup Galileo as PCI Master
MASK_WRITE_PCI_REG HAL_GALILEO_PCI0_STATUS_COMMAND_REGNUM, HAL_MALTA_NULL_DEVNUM, \
(HAL_GALILEO_PCI0_CONFIG_MEMEn | HAL_GALILEO_PCI0_CONFIG_MasEn | HAL_GALILEO_PCI0_CONFIG_SErrEn)
 
# Setup Galileo PCI latency timer
MASK_WRITE_PCI_REG HAL_GALILEO_PCI0_BIST_REGNUM, HAL_MALTA_NULL_DEVNUM, \
HAL_GALILEO_PCI0_LAT_TIMER_VAL
 
# Enable FPGA I2C
li a1, CYGARC_UNCACHED_ADDRESS(HAL_I2CFPGA_BASE)
I2C_ENABLE
 
##=====================================================================================
##
## Read the SPD device parameters and determine memory size
##
 
READ_SPD_VALUE HAL_SPD_GET_NUM_ROW_BITS, 0xf, s0, ERROR_CHECK
READ_SPD_VALUE HAL_SPD_GET_NUM_COL_BITS, 0xf, s1, ERROR_CHECK
 
READ_SPD_VALUE HAL_SPD_GET_NUM_DEVICE_BANKS, NO_MASK, s2, ERROR_CHECK
 
READ_SPD_VALUE HAL_SPD_GET_SDRAM_WIDTH, 0x7f, s3, ERROR_CHECK
READ_SPD_VALUE HAL_SPD_GET_NUM_MODULE_BANKS, NO_MASK, s4, ERROR_CHECK
READ_SPD_VALUE HAL_SPD_GET_ROW_DENSITY, NO_MASK, s5, ERROR_CHECK
 
READ_SPD_VALUE HAL_SPD_GET_BURST_LENGTH, NO_MASK, s6, ERROR_CHECK
 
#
# Determine Size in Mbit
# SIZE = SDRAM_WIDTH * NUM_DEVICE_BANKS * 2 ^ (NUM_ROW_BITS + NUM_COL_BITS)
#
addu t0, s0, s1 # t0 = (NUM_ROW_BITS + NUM_COL_BITS)
li t1, 1 # t1 = 2 ^ 0
sll t1, t0 # t1 = 2 ^ (NUM_ROW_BITS + NUM_COL_BITS)
multu s2, t1
mflo s6 # s6 = NUM_DEVICE_BANKS * 2 ^ (NUM_ROW_BITS + NUM_COL_BITS)
nop
nop
nop
multu s6, s3
mflo s6 # s6 = SDRAM_WIDTH * NUM_DEVICE_BANKS * 2 ^ (NUM_ROW_BITS + NUM_COL_BITS)
nop
nop
nop
 
#
# Determine size of Bank 0
# SPD Density of Each Row on Module value is used. Bit 7 represents
# 512MB, bit 6 256MB, etc. Highest set bit is size of bank 0.
# If there are two banks and these have different sizes, an extra
# bit will be set. If the sizes are the same, only the one bit is set.
# Note, at the exit of this loop, the size-bit of bank 0 will have been
# shifted out, allowing an easy check for multiple sizes below
#
li s0, SZ_512M
0:
and t1, s5, BIT7
bnez t1, 8f
sll s5, 1
b 0b
srl s0, 1
8:
 
#
# Determine if Bank 1 exists
#
li t0, 1
beq s4, t0, 8f
move s1, zero
#
# Determine if Bank 1 is different than Bank 0. If no additional bits
# set, size is the same.
#
and t1, s5, 0xFF
beq t1, zero, 8f
move s1, s0
#
# Determine size of Bank 1. It will be at least one factor smaller
# than that of bank 0.
#
sll s1,1
0:
and t1, s5, BIT7
bnez t1, 8f
sll s5, 1
b 0b
srl s1, 1
8:
 
#
# FIXME: We should probably do some validation on the various
# memory parameters here at some point.
#
 
#
# Set the base SDRAM bank configuration value.
# All other fields are zero, and the proper value is masked
# in when they are known
#
li s5, HAL_GALILEO_SDRAM_SRAS_TO_SCAS_DELAY_3C | \
HAL_GALILEO_SDRAM_WIDTH_64BIT | \
HAL_GALILEO_SDRAM_SRAS_PRECHARGE_3C
 
#
# Setup the CASLAT value.
# Support only CASLAT = 2
#
READ_SPD_VALUE HAL_SPD_GET_CAS_LAT, NO_MASK, v0, NO_ERROR_CHECK
and t0, v0, 2
beqz t0, error
nop
ori s5, HAL_GALILEO_SDRAM_BANK0_CASLAT_2
 
#
# Setup SDRAM device size
#
li t0, SZ_16M
beq s6, t0, 8f
nop
ori s5, HAL_GALILEO_SDRAM_BANK0_SZ_64M
8:
 
#
# Setup burst length: Support only 8
#
READ_SPD_VALUE HAL_SPD_GET_BURST_LENGTH, NO_MASK, v0, NO_ERROR_CHECK
and t0, v0, 8
beqz t0, error
nop
 
#
# Setup Parity.
# Only support Parity/Noparity. Don't support ECC.
#
READ_SPD_VALUE HAL_SPD_GET_CONFIG_TYPE, NO_MASK, v0, NO_ERROR_CHECK
li t0, HAL_SPD_CONFIG_TYPE_PARITY
beq t0, v0, 0f
nop
li t0, HAL_SPD_CONFIG_TYPE_ECC
beq t0, v0, error
nop
b 8f
li v1, 0
0:
ori s5, HAL_GALILEO_SDRAM_BANK0_PARITY
li v1, 1
8:
 
#
# Setup number of device banks
# Only support 2 or 4 banks
#
li t0, 2
beq s2, t0, 8f
nop
li t0, 4
beq s2, t0, 0f
nop
b error
nop
0:
ori s5, HAL_GALILEO_SDRAM_NUM_BANKS_4
8:
 
#
# Now actually store the bank config register
#
sw s5, HAL_GALILEO_SDRAM_BANK0_OFFSET(s7)
sw s5, HAL_GALILEO_SDRAM_BANK2_OFFSET(s7)
 
#
# Setup the SDRAM configuration register
# All other fields are zero, and the proper value is masked
# in when they are known
#
li s5, HAL_GALILEO_SDRAM_DUPLICATE_BANK_ADDR | HAL_GALILEO_SDRAM_BANK_INTERLEAVE_DIS
 
#
# Setup the Refresh Rate
#
READ_SPD_VALUE HAL_SPD_GET_REFRESH_RATE, 0x7f, v0, NO_ERROR_CHECK
 
li t0, HAL_SPD_REFRESH_RATE_125
beq t0, v0, 8f
li t0, HAL_SPD_REFRESH_COUNTER_125
 
li t0, HAL_SPD_REFRESH_RATE_62_5
beq t0, v0, 8f
li t0, HAL_SPD_REFRESH_COUNTER_62_5
 
li t0, HAL_SPD_REFRESH_RATE_31_3
beq t0, v0, 8f
li t0, HAL_SPD_REFRESH_COUNTER_31_3
 
li t0, HAL_SPD_REFRESH_RATE_15_625
beq t0, v0, 8f
li t0, HAL_SPD_REFRESH_COUNTER_15_625
 
li t0, HAL_SPD_REFRESH_RATE_7_8
beq t0, v0, 8f
li t0, HAL_SPD_REFRESH_COUNTER_7_8
 
# Unknown: assume 3.9 microseconds
li t0, HAL_SPD_REFRESH_COUNTER_3_9
8:
 
or s5, t0
 
#if 0 // FIXME: Dunno what this is supposed to do, but it changes the RMW flag,
// not anything related to RAM width.
#
# Setup RAM_WIDTH
#
beqz v1, 8f
nop
READ_SPD_VALUE HAL_SPD_GET_ERROR_CHECK_WIDTH, 0x7f, v0, NO_ERROR_CHECK
beq v0, zero, 8f
nop
ori s5, HAL_GALILEO_SDRAM_CFG_RAM_WIDTH
8:
#endif
 
#
# Store the SDRAM configuration register
#
sw s5, HAL_GALILEO_SDRAM_CONFIG_OFFSET(s7)
#
# Setup SDRAM Bank 0 Address Decoding
#
li a0, CYGARC_PHYSICAL_ADDRESS(HAL_MALTA_RAM_BASE) # Physical bottom of Bank 0
add a1, s0, a0
subu a1, 1 # Physical top of Bank 0
 
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT # Setup SCS[1:0]
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT # First level decoding
sw t0, HAL_GALILEO_SCS10_LD_OFFSET(s7) # (ie Processor Decode Region)
sw t1, HAL_GALILEO_SCS10_HD_OFFSET(s7) #
 
srl t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT # Setup SCS0
srl t1, a1, HAL_GALILEO_DEV_DECODE_SHIFT # Second level decoding
sw t0, HAL_GALILEO_SCS0_LD_OFFSET(s7) # (ie Device Sub-decode Region)
sw t1, HAL_GALILEO_SCS0_HD_OFFSET(s7) #
 
#
# Setup SDRAM Bank 1 Address Decoding
#
add a0, s0, CYGARC_PHYSICAL_ADDRESS(HAL_MALTA_RAM_BASE) # Physical bottom of Bank 1
add a1, a0, s1
subu a1, 1 # Physical top of Bank 1
 
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT # Setup SCS[3:2]
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT # First level decoding
sw t0, HAL_GALILEO_SCS32_LD_OFFSET(s7) # (ie Processor Decode Region)
sw t1, HAL_GALILEO_SCS32_HD_OFFSET(s7) #
 
srl t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT # Setup SCS2
srl t1, a1, HAL_GALILEO_DEV_DECODE_SHIFT # Second level decoding
sw t0, HAL_GALILEO_SCS2_LD_OFFSET(s7) # (ie Device Sub-decode Region)
sw t1, HAL_GALILEO_SCS2_HD_OFFSET(s7) #
 
#
# Setup PCI windows
#
li a0, CYGARC_PHYSICAL_ADDRESS(HAL_MALTA_PCI_MEM0_BASE)
add a1, a0, HAL_MALTA_PCI_MEM0_SIZE
subu a1, 1 # Physical top of Mem Bank 0
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT
sw t0, HAL_GALILEO_PCIMEM0_LD_OFFSET(s7)
sw t1, HAL_GALILEO_PCIMEM0_HD_OFFSET(s7)
 
li a0, CYGARC_PHYSICAL_ADDRESS(HAL_MALTA_PCI_MEM1_BASE)
add a1, a0, HAL_MALTA_PCI_MEM1_SIZE
subu a1, 1 # Physical top of Mem Bank 1
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT
sw t0, HAL_GALILEO_PCIMEM1_LD_OFFSET(s7)
sw t1, HAL_GALILEO_PCIMEM1_HD_OFFSET(s7)
 
li a0, CYGARC_PHYSICAL_ADDRESS(HAL_MALTA_PCI_IO_BASE)
add a1, a0, HAL_MALTA_PCI_IO_SIZE
subu a1, 1 # Physical top of IO Bank
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT
sw t0, HAL_GALILEO_PCIIO_LD_OFFSET(s7)
sw t1, HAL_GALILEO_PCIIO_HD_OFFSET(s7)
 
# Here's a nice gotcha. The Intel southbridge *must* see IO
# starting from 0.
sw zero,HAL_GALILEO_PCI_IO_REMAP(s7)
 
#
# Setup FLASH Address Decoding
#
li a0, CYGARC_PHYSICAL_ADDRESS(HAL_MALTA_FLASH_BASE) # Physical bottom of Flash Bank
add a1, a0, HAL_MALTA_FLASH_SIZE
subu a1, 1 # Physical top of Flash Bank
 
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT # Setup CS[2:0]
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT # First level decoding
sw t0, HAL_GALILEO_CS20_LD_OFFSET(s7) # (ie Processor Decode Region)
sw t1, HAL_GALILEO_CS20_HD_OFFSET(s7) #
 
srl t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT # Setup CS0
srl t1, a1, HAL_GALILEO_DEV_DECODE_SHIFT # Second level decoding
sw t0, HAL_GALILEO_CS0_LD_OFFSET(s7) # (ie Device Sub-decode Region)
sw t1, HAL_GALILEO_CS0_HD_OFFSET(s7) #
 
#
# Now disable all unused decodes
# (SCS1, SCS3, PCI1xx, CS1, CS2)
#
li t0, 0xffff
move t1, zero
sw t0, HAL_GALILEO_SCS1_LD_OFFSET(s7)
sw t1, HAL_GALILEO_SCS1_HD_OFFSET(s7)
sw t0, HAL_GALILEO_SCS3_LD_OFFSET(s7)
sw t1, HAL_GALILEO_SCS3_HD_OFFSET(s7)
sw t0, HAL_GALILEO_PCI1IO_LD_OFFSET(s7)
sw t1, HAL_GALILEO_PCI1IO_HD_OFFSET(s7)
sw t0, HAL_GALILEO_PCI1MEM0_LD_OFFSET(s7)
sw t1, HAL_GALILEO_PCI1MEM0_HD_OFFSET(s7)
sw t0, HAL_GALILEO_PCI1MEM1_LD_OFFSET(s7)
sw t1, HAL_GALILEO_PCI1MEM1_HD_OFFSET(s7)
sw t0, HAL_GALILEO_CS1_LD_OFFSET(s7)
sw t1, HAL_GALILEO_CS1_HD_OFFSET(s7)
sw t0, HAL_GALILEO_CS2_LD_OFFSET(s7)
sw t1, HAL_GALILEO_CS2_HD_OFFSET(s7)
 
noerror:
move v0, zero
add v1, s0, s1
move ra, s8
jr ra
nop
 
error:
li v0, HAL_MALTA_MEMERROR
move ra, s8
jr ra
nop
 
FUNC_END(hal_malta_init_sdram)
 
.macro i2c_start
# Start: SDA low -> high with SLC high
I2C_OE(HAL_I2C_COUT_DOUT)
I2C_OUT(HAL_I2C_CHIGH_DHIGH)
I2C_OUT(HAL_I2C_CHIGH_DLOW)
I2C_OUT(HAL_I2C_CLOW_DLOW)
.endm
.macro i2c_stop
# Stop: SDA high -> low with SLC high
I2C_OE(HAL_I2C_COUT_DOUT)
I2C_OUT(HAL_I2C_CLOW_DLOW)
I2C_OUT(HAL_I2C_CHIGH_DLOW)
I2C_OUT(HAL_I2C_CHIGH_DHIGH)
I2C_OUT(HAL_I2C_CLOW_DHIGH)
.endm
 
.macro i2c_write
# Value to write in t1.
# Writes happen by clocking SCL low->high->low while SDA defines
# the bit to be sent (MSB first).
I2C_OE(HAL_I2C_COUT_DOUT)
li t2, 7
1: srlv t3, t1, t2
andi t3, 1
beq t3, zero, 2f
nop
# Send 1
I2C_OUT(HAL_I2C_CLOW_DHIGH)
I2C_OUT(HAL_I2C_CHIGH_DHIGH)
I2C_OUT(HAL_I2C_CLOW_DHIGH)
b 3f
nop
2: # Send 0
I2C_OUT(HAL_I2C_CLOW_DLOW)
I2C_OUT(HAL_I2C_CHIGH_DLOW)
I2C_OUT(HAL_I2C_CLOW_DLOW)
3: bne t2, zero, 1b
addiu t2, -1
# Now tristate the SDA and pulse the clock. Receiver will
# ack the transfer by pulling SDA low.
# Read by pulsing clock. Leave result in t1
I2C_OE(HAL_I2C_COUT_DIN)
I2C_OUT(HAL_I2C_CHIGH_DHIGH)
I2C_IN(t1)
I2C_OUT(HAL_I2C_CLOW_DHIGH)
.endm
 
.macro i2c_read
# Value read is returned in t1
# Reads happen by clocking SCL high->low while reading SDA
I2C_OE(HAL_I2C_COUT_DIN)
move t1,zero
li t2, 7
1: I2C_OUT(HAL_I2C_CHIGH_DHIGH)
I2C_IN(t3)
sll t1,1
or t1,t1,t3
I2C_OUT(HAL_I2C_CLOW_DHIGH)
 
bne t2, zero, 1b
addiu t2, -1
 
// Send ack by clocking with SDA low.
I2C_OUT(HAL_I2C_CLOW_DHIGH)
I2C_OE(HAL_I2C_COUT_DOUT)
I2C_OUT(HAL_I2C_CHIGH_DHIGH)
I2C_OUT(HAL_I2C_CLOW_DHIGH)
.endm
##
## Read a value from the SDRAM SPD device.
##
## Parameters: a0 = subaddress
## Returns: v0 = SPD value read
##
FUNC_START(read_spd_value)
.set noreorder
# Setup a base address register
li a1, CYGARC_UNCACHED_ADDRESS(HAL_I2CFPGA_BASE)
 
i2c_start
 
# Write address of SDRAM sense controller
li t1,( HAL_I2C_SPD_ADDRESS | HAL_I2C_WRITE )
i2c_write
li t0,HAL_I2CFPGA_OUT_SDA_NACK
beq t0,t1,i2c_error
move v0,zero
 
# Write address of data wanted
move t1,a0
i2c_write
li t0,HAL_I2CFPGA_OUT_SDA_NACK
beq t0,t1,i2c_error
move v0,zero
i2c_start
 
# Write address of SDRAM sense controller
li t1,( HAL_I2C_SPD_ADDRESS | HAL_I2C_READ )
i2c_write
li t0,HAL_I2CFPGA_OUT_SDA_NACK
beq t0,t1,i2c_error
move v0,zero
 
# Read data
i2c_read
move v0,t1
 
i2c_stop
i2c_error:
jr ra
nop
 
FUNC_END(read_spd_value)
#endif // defined(CYG_HAL_STARTUP_ROM)
 
##-----------------------------------------------------------------------------
## ISR springboard.
## This routine decodes the interrupt from the southbridge and vectors to it.
 
# On entry:
# a0 = MIPS status register interrupt number (1,2 or 3)
# a1 = ISR data value (= interrupt controller reg address)
# a2 = saved reg dump ptr
# s0 = saved reg dump ptr
# s1 = vector table offset
# s2 = interrupt number
# a3,v0,v1 etc available for use
 
.text
 
FUNC_START(hal_isr_springboard_southbridge)
.set noreorder
# Get req bits of controller 1
lb v0,0(a1)
lb v1,1(a1) # apply mask
xori v1,v1,0xffff
and v0,v0,v1
andi v1,v0,0xffff&~(1<<(CYGNUM_HAL_INTERRUPT_CASCADE-CYGNUM_HAL_INTERRUPT_CTRL1_BASE))
bne v1,zero,1f
ori a2,zero,CYGNUM_HAL_INTERRUPT_CTRL1_BASE
# If cascade is set, check controller 2
andi v0,v0,(1<<(CYGNUM_HAL_INTERRUPT_CASCADE-CYGNUM_HAL_INTERRUPT_CTRL1_BASE))
beq v0,zero,2f
lb v0,HAL_PIIX4_MASTER_SLAVE_OFFSET(a1)
lb v1,HAL_PIIX4_MASTER_SLAVE_OFFSET+1(a1) # apply mask
xori v1,v1,0xffff
and v0,v0,v1
bne v0,zero,1f
ori a2,zero,CYGNUM_HAL_INTERRUPT_CTRL2_BASE
# Spurious interrupt, return to VSR
2: jr ra
move v0,zero
1:
 
# FIXME: May want to rewrite this to do ls bit on byte
# to save a few cycles.
# The following code implements an ls bit index algorithm similar
# to that in hal_lsbit_index() in hal_misc.c.
negu v1,v0 # v1 = -v0
and v1,v1,v0 # v1 &= v0 [isolate ls bit]
sll v0,v1,16 # v0 = v1<<16
subu v1,v0,v1 # v1 = v0 - v1
sll a0,v1,6 # a0 = v1<<6
addu v1,v1,a0 # v1 += a0
sll a1,v1,4 # a1 = v1<<4
addu v1,v1,a1 # v1 += a1
la v0,hal_isr_springboard_table # v0 = table address
srl v1,v1,26 # v1 = v1>>26
addu v1,v1,v0 # v1 = table entry address
lb a0,0(v1) # a0 = intc isr number
 
add s2,a0,a2 # s2 = eCos isr number
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
hal_isr_springboard_chaining:
# This serves as the __default_interrupt_isr entry-point in
# chaning mode, thus ensuring that all interrupts from
# vectors 0-5 eventually end up on the special CHAINING vector.
# (See the hal_interrupt_handlers table)
ori s1,zero,CYGNUM_HAL_INTERRUPT_CHAINING*4 # s1 = chaining isr ix
#else
sll s1,s2,2 # s1 = isr table index
#endif
 
la v1,hal_interrupt_handlers
add v1,v1,s1 # v1 = isr handler address
lw v1,0(v1) # v1 = isr handler
 
la a1,hal_interrupt_data
add a1,a1,s1 # a1 = address of data ptr
lw a1,0(a1) # a1 = data pointer
 
move a0,s2 # pass interrupt number
 
jr v1 # jump to handler, return is to
nop # default vsr already in ra
 
FUNC_END(hal_isr_springboard_southbridge)
 
hal_isr_springboard_table:
.byte -1, 0, 1, 12, 2, 6, 0, 13
.byte 3, 0, 7, 0, 0, 0, 0, 14
.byte 10, 4, 0, 0, 8, 0, 0, 25
.byte 0, 0, 0, 0, 0, 21, 27, 15
.byte 31, 11, 5, 0, 0, 0, 0, 0
.byte 9, 0, 0, 24, 0, 0, 20, 26
.byte 30, 0, 0, 0, 0, 23, 0, 19
.byte 29, 0, 22, 18, 28, 17, 16, 0
 
##-----------------------------------------------------------------------------
# Interrupt vector tables.
# These tables contain the isr, data and object pointers used to deliver
# interrupts to user code.
 
.extern hal_default_isr
 
.data
 
.globl hal_interrupt_handlers
hal_interrupt_handlers:
.long hal_isr_springboard_southbridge
.rept CYGNUM_HAL_ISR_COUNT-1
.long hal_default_isr
.endr
 
.globl hal_interrupt_data
hal_interrupt_data:
.long HAL_PIIX4_MASTER_OCW3
.rept CYGNUM_HAL_ISR_COUNT-1
.long 0
.endr
 
.globl hal_interrupt_objects
hal_interrupt_objects:
.rept CYGNUM_HAL_ISR_COUNT
.long 0
.endr
 
##-----------------------------------------------------------------------------
## end of platform.S
/v2_0/src/hal_diag.c
0,0 → 1,187
/*=============================================================================
//
// hal_diag.c
//
// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors:nickg, dmoseley
// Date: 2001-03-20
// Purpose: HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_diag.h>
 
#include <cyg/hal/hal_intr.h>
 
#include <cyg/hal/hal_io.h>
 
//-----------------------------------------------------------------------------
// Select which diag channels to use
 
//#define CYG_KERNEL_DIAG_LCD
#define CYG_KERNEL_DIAG_SERIAL
 
/*---------------------------------------------------------------------------*/
 
void hal_diag_led(int x)
{
HAL_WRITE_UINT32(HAL_DISPLAY_LEDBAR, x);
#if !defined(CYG_KERNEL_DIAG_LCD)
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIWORD, x);
#endif
}
 
externC void diag_write_string (const char*);
 
#ifdef CYG_KERNEL_DIAG_SERIAL
extern void cyg_hal_plf_comms_init(void);
extern void cyg_hal_plf_serial_putc(void*, cyg_uint8);
extern cyg_uint8 cyg_hal_plf_serial_getc(void*);
#endif
 
void hal_diag_init(void)
{
#if defined(CYGSEM_HAL_ROM_MONITOR) && !defined(CYG_KERNEL_DIAG_SERIAL)
// It's handy to have the LCD initialized at reset when using it
// for debugging output.
// The serial port likely doesn't work yet. Let's wait.
diag_write_string ("eCos ROM " __TIME__ "\n");
diag_write_string (__DATE__ "\n");
#endif
 
#if defined(CYG_KERNEL_DIAG_SERIAL)
cyg_hal_plf_comms_init();
#endif
}
 
#if defined(CYG_KERNEL_DIAG_LCD)
static void hal_diag_clear_lcd(void)
{
volatile int i = 0x20000;
while (--i) ;
 
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, ' ');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, ' ');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, ' ');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, ' ');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, ' ');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, ' ');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, ' ');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' ');
}
#endif /* defined(CYG_KERNEL_DIAG_LCD) */
 
void hal_diag_write_char(char c)
{
#if defined(CYG_KERNEL_DIAG_LCD)
static volatile CYG_WORD* reg = HAL_DISPLAY_ASCIIPOS0;
#endif
 
unsigned long __state;
 
HAL_DISABLE_INTERRUPTS(__state);
 
if(c == '\n')
{
#if defined(CYG_KERNEL_DIAG_LCD)
reg = HAL_DISPLAY_ASCIIPOS0;
hal_diag_clear_lcd();
#endif
#if defined (CYG_KERNEL_DIAG_SERIAL)
cyg_hal_plf_serial_putc(NULL, '\r');
cyg_hal_plf_serial_putc(NULL, '\n');
#endif
}
else if (c == '\r')
{
// Ignore '\r'
}
else
{
#if defined(CYG_KERNEL_DIAG_LCD)
if (reg == HAL_DISPLAY_ASCIIPOS0)
hal_diag_clear_lcd();
 
HAL_WRITE_UINT32(reg, c);
 
// Advance to next LED position.
if (reg == HAL_DISPLAY_ASCIIPOS0)
reg = HAL_DISPLAY_ASCIIPOS1;
else if (reg == HAL_DISPLAY_ASCIIPOS1)
reg = HAL_DISPLAY_ASCIIPOS2;
else if (reg == HAL_DISPLAY_ASCIIPOS2)
reg = HAL_DISPLAY_ASCIIPOS3;
else if (reg == HAL_DISPLAY_ASCIIPOS3)
reg = HAL_DISPLAY_ASCIIPOS4;
else if (reg == HAL_DISPLAY_ASCIIPOS4)
reg = HAL_DISPLAY_ASCIIPOS5;
else if (reg == HAL_DISPLAY_ASCIIPOS5)
reg = HAL_DISPLAY_ASCIIPOS6;
else if (reg == HAL_DISPLAY_ASCIIPOS6)
reg = HAL_DISPLAY_ASCIIPOS7;
else // reg == HAL_DISPLAY_ASCIIPOS7 or UNKNOWN
reg = HAL_DISPLAY_ASCIIPOS0;
#endif
#if defined(CYG_KERNEL_DIAG_SERIAL)
cyg_hal_plf_serial_putc(NULL, c);
#endif
}
 
HAL_RESTORE_INTERRUPTS(__state);
}
 
void hal_diag_read_char(char* c)
{
*c = cyg_hal_plf_serial_getc(NULL);
}
 
/*---------------------------------------------------------------------------*/
/* End of hal_diag.c */
/v2_0/src/plf_mk_defs.c
0,0 → 1,86
//==========================================================================
//
// plf_mk_defs.c
//
// HAL (platform) "make defs" program
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov
// Date: 2001-04-09
// Purpose: Platform dependent definition generator
// Description: This file contains code that can be compiled by the target
// compiler and used to generate machine specific definitions
// suitable for use in assembly code.
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_arch.h> // HAL header
#include <cyg/hal/hal_intr.h> // HAL header
#include <cyg/hal/hal_cache.h> // HAL header
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
# include <cyg/kernel/instrmnt.h>
#endif
 
/*
* This program is used to generate definitions needed by
* assembly language modules.
*
* This technique was first used in the OSF Mach kernel code:
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
*/
 
#define DEFINE(sym, val) \
asm volatile("\n\t.equ\t" #sym ",%0" : : "i" (val))
 
int
main(void)
{
// DEFINE(CYGNUM_HAL_ISR_COUNT, CYGNUM_HAL_ISR_COUNT);
return 0;
}
 
//--------------------------------------------------------------------------
// EOF plf_mk_defs.c
/v2_0/src/plf_misc.c
0,0 → 1,467
//==========================================================================
//
// plf_misc.c
//
// HAL platform miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jlarmour, dmoseley, jskov
// Date: 2001-03-20
// Purpose: HAL miscellaneous functions
// Description: This file contains miscellaneous functions provided by the
// HAL.
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // Base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_arch.h> // architectural definitions
 
#include <cyg/hal/hal_intr.h> // Interrupt handling
 
#include <cyg/hal/hal_cache.h> // Cache handling
 
#include <cyg/hal/hal_if.h>
#include <cyg/io/pci_hw.h>
#include <cyg/io/pci.h>
 
//--------------------------------------------------------------------------
 
externC void cyg_hal_init_superIO(void);
static void hal_init_irq(void);
 
//--------------------------------------------------------------------------
 
void hal_platform_init(void)
{
HAL_WRITE_UINT32(HAL_DISPLAY_LEDBAR, 0xff);
#if defined(CYGPKG_CYGMON)
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, ' ');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, 'C');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'Y');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'G');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'M');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 'O');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, 'N');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' ');
#elif defined(CYGPKG_REDBOOT)
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, 'R');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, 'e');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'd');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'B');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'o');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 'o');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, 't');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' ');
#else
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, ' ');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, ' ');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'e');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'C');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'O');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 'S');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, ' ');
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' ');
#endif
 
// Initialize PCI before VV since serial registers need to be in
// place before that time.
cyg_hal_plf_pci_init();
 
// Init interrupt controller on PIIX4
hal_init_irq();
 
// Initialize super IO controller
cyg_hal_init_superIO();
 
// Set up eCos/ROM interfaces
hal_if_init();
 
HAL_ICACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_INVALIDATE_ALL();
HAL_DCACHE_ENABLE();
}
 
 
/*------------------------------------------------------------------------*/
/* Reset support */
 
void hal_malta_reset(void)
{
*HAL_MALTA_SOFTRES = HAL_MALTA_GORESET;
for(;;); // wait for it
}
 
 
//--------------------------------------------------------------------------
// IRQ init
static void
hal_init_irq(void)
{
cyg_uint32 v;
 
// Enable SERIRQ on PIIX4
v = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,0),
CYG_PCI_CFG_PIIX4_GENCFG);
v |= CYG_PCI_CFG_PIIX4_GENCFG_SERIRQ;
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,0),
CYG_PCI_CFG_PIIX4_GENCFG, v);
 
// Enable SERIRQ and set to continous mode.
v = cyg_hal_plf_pci_cfg_read_byte(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,0),
CYG_PCI_CFG_PIIX4_SERIRQC);
v |= CYG_PCI_CFG_PIIX4_SERIRQC_ENABLE | CYG_PCI_CFG_PIIX4_SERIRQC_CONT;
cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,0),
CYG_PCI_CFG_PIIX4_SERIRQC, v);
 
// Init master interrupt controller (4.2.2, pp 74-78)
HAL_WRITE_UINT8(HAL_PIIX4_MASTER_ICW1, HAL_PIIX4_ICW1_SEL | HAL_PIIX4_ICW1_WR);
HAL_WRITE_UINT8(HAL_PIIX4_MASTER_ICW2, CYGNUM_HAL_INTERRUPT_CTRL1_BASE - CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE);
HAL_WRITE_UINT8(HAL_PIIX4_MASTER_ICW3, HAL_PIIX4_ICW3_CASCADE);
HAL_WRITE_UINT8(HAL_PIIX4_MASTER_ICW4, HAL_PIIX4_ICW4_UPMODE);
HAL_WRITE_UINT8(HAL_PIIX4_MASTER_OCW3, HAL_PIIX4_OCW3_SEL | HAL_PIIX4_OCW3_ESSM | HAL_PIIX4_OCW3_REQ);
 
// Init slave interrupt controller
HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_ICW1, HAL_PIIX4_ICW1_SEL | HAL_PIIX4_ICW1_WR);
HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_ICW2, CYGNUM_HAL_INTERRUPT_CTRL2_BASE - CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE);
HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_ICW3, HAL_PIIX4_ICW3_SLAVE);
HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_ICW4, HAL_PIIX4_ICW4_UPMODE);
 
// Mask all sources
HAL_WRITE_UINT8(HAL_PIIX4_MASTER_OCW1,
0xff & ~(1<<(CYGNUM_HAL_INTERRUPT_CASCADE-CYGNUM_HAL_INTERRUPT_CTRL1_BASE)));
HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_OCW1, 0xff);
 
// Set PCI interrupt routing and set those interrupts to level
// sense as per 4.1.10 page 59 in 82371AB doc.
v = ( (CYGNUM_HAL_INTERRUPT_PCI_AB-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 0
|(CYGNUM_HAL_INTERRUPT_PCI_AB-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 8
|(CYGNUM_HAL_INTERRUPT_PCI_CD-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 16
|(CYGNUM_HAL_INTERRUPT_PCI_CD-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 24);
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,0),
CYG_PCI_CFG_PIIX4_PIRQR, v);
HAL_READ_UINT8(HAL_PIIX4_ELCR2, v);
v |= (1 << (CYGNUM_HAL_INTERRUPT_PCI_AB-CYGNUM_HAL_INTERRUPT_CTRL2_BASE))
|(1 << (CYGNUM_HAL_INTERRUPT_PCI_CD-CYGNUM_HAL_INTERRUPT_CTRL2_BASE));
HAL_WRITE_UINT8(HAL_PIIX4_ELCR2, v);
 
// Let south bridge interrupt
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SOUTH_BRIDGE_INTR);
}
 
/*------------------------------------------------------------------------*/
/* PCI support */
#if defined(CYGPKG_IO_PCI)
 
#define PCIMEM_START 0x08000000 // PCI memory address
#define PCIMEM_SIZE 0x10000000 // 256 MByte
#define PCIIO_START 0x18000000 // PCI io address
#define PCIIO_SIZE 0x03E00000 // 62 MByte
 
static int __check_bar(cyg_uint32 addr, cyg_uint32 size)
{
int n;
 
for (n = 0; n <= 31; n++)
if (size == (1 << n)) {
/* Check that address is naturally aligned */
if (addr != (addr & ~(size-1)))
return 0;
return size - 1;
}
return 0;
}
 
 
// One-time PCI initialization.
 
void cyg_hal_plf_pci_init(void)
{
cyg_uint32 bar_ena, start10, start32, end, size;
cyg_uint8 next_bus;
cyg_uint32 v;
 
 
static int initialized = 0;
if (initialized) return;
initialized = 1;
 
// Setup for bus mastering
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_IO |
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
 
// Setup latency timer field
cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 6);
 
// Disable all BARs
bar_ena = 0x1ff;
 
// Check for active SCS10
start10 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_LD_OFFSET) << 21;
end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_HD_OFFSET) & 0x7f) + 1) << 21;
if (end > start10) {
if ((size = __check_bar(start10, end - start10)) != 0) {
// Enable BAR
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS10_SIZE_OFFSET, size);
bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10;
}
}
 
// Check for active SCS32
start32 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_LD_OFFSET) << 21;
end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_HD_OFFSET) & 0x7f) + 1) << 21;
if (end > start32) {
if ((size = __check_bar(start32, end - start32)) != 0) {
// Enable BAR
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS32_SIZE_OFFSET, size);
bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS32;
}
}
 
bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10;
HAL_GALILEO_PUTREG(HAL_GALILEO_BAR_ENA_OFFSET, bar_ena);
 
 
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0, 0xffffffff);
 
end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0);
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0, start10);
 
 
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_1, 0xffffffff);
 
end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_1);
 
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_1, start32);
 
 
// enable ISA bridge on PIIX4
v = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,_PIIX4_BRIDGE),
CYG_PCI_CFG_PIIX4_GENCFG);
v |= CYG_PCI_CFG_PIIX4_GENCFG_ISA;
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,_PIIX4_BRIDGE),
CYG_PCI_CFG_PIIX4_GENCFG, v);
 
v = cyg_hal_plf_pci_cfg_read_byte(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,_PIIX4_BRIDGE),
CYG_PCI_CFG_PIIX4_TOM);
v &= ~CYG_PCI_CFG_PIIX4_TOM_TOM_MASK;
v |= CYG_PCI_CFG_PIIX4_TOM_TOM_16M;
cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,_PIIX4_BRIDGE),
CYG_PCI_CFG_PIIX4_TOM, v);
 
 
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
 
 
// Check for configuration error.
static int pci_config_errcheck(void)
{
cyg_uint32 irq;
 
// Check for master or target abort
irq = HAL_GALILEO_GETREG(HAL_GALILEO_IRQ_CAUSE_OFFSET);
 
if (irq & (HAL_GALILEO_IRQCAUSE_MASABT | HAL_GALILEO_IRQCAUSE_TARABT)) {
// Error. Clear bits.
HAL_GALILEO_PUTREG(HAL_GALILEO_IRQ_CAUSE_OFFSET,
~(HAL_GALILEO_IRQCAUSE_MASABT | HAL_GALILEO_IRQCAUSE_TARABT));
return 1;
}
return 0;
}
 
cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset)
{
cyg_uint32 config_data;
 
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
(bus << 16) | (devfn << 8) | offset);
 
config_data = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
 
if (pci_config_errcheck())
return 0xffffffff;
return config_data;
}
 
cyg_uint16 cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset)
{
cyg_uint32 config_dword;
 
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
(bus << 16) | (devfn << 8) | (offset & ~3));
 
config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
 
if (pci_config_errcheck())
return 0xffff;
return (cyg_uint16)((config_dword >> ((offset & 3) * 8)) & 0xffff);
}
 
cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset)
{
cyg_uint32 config_dword;
 
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
(bus << 16) | (devfn << 8) | (offset & ~3));
 
config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
 
if (pci_config_errcheck())
return 0xff;
return (cyg_uint8)((config_dword >> ((offset & 3) * 8)) & 0xff);
}
 
void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint32 data)
{
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
(bus << 16) | (devfn << 8) | offset);
 
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, data);
 
(void)pci_config_errcheck();
}
 
void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint16 data)
{
cyg_uint32 config_dword, shift;
 
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
(bus << 16) | (devfn << 8) | (offset & ~3));
 
config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
if (pci_config_errcheck())
return;
 
shift = (offset & 3) * 8;
config_dword &= ~(0xffff << shift);
config_dword |= (data << shift);
 
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword);
 
(void)pci_config_errcheck();
}
 
void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint8 data)
{
cyg_uint32 config_dword, shift;
 
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
(bus << 16) | (devfn << 8) | (offset & ~3));
 
config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET);
if (pci_config_errcheck())
return;
 
shift = (offset & 3) * 8;
config_dword &= ~(0xff << shift);
config_dword |= (data << shift);
 
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword);
 
(void)pci_config_errcheck();
}
#endif // defined(CYGPKG_IO_PCI)
 
 
/*------------------------------------------------------------------------*/
/* IDE support */
 
void cyg_hal_plf_ide_init(void)
{
cyg_uint32 v;
 
// enable IDE
v = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,_PIIX4_IDE),
CYG_PCI_CFG_PIIX4_IDETIM);
v |= (CYG_PCI_CFG_PIIX4_IDETIM_IDE << 16) | CYG_PCI_CFG_PIIX4_IDETIM_IDE;
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,_PIIX4_IDE),
CYG_PCI_CFG_PIIX4_IDETIM, v);
}
 
 
/*------------------------------------------------------------------------*/
/* End of plf_misc.c */
/v2_0/src/smsc37m81x.c
0,0 → 1,130
//=============================================================================
//
// smsc37m81x.c
//
// Init code for SMSC 37m81x super IO controller
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2001-04-02
// Description: Init code for SMSC 37m81x super IO controller
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include CYGBLD_HAL_PLATFORM_H
 
#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_intr.h> // interrupt vectors
 
 
// From page 137+ in SMSC-37m81x.pdf
#define SMSC_CONFIG 0xb80003f0
#define SMSC_CONFIG_DATA 0xb80003f1
 
#define SMSC_CONFIG_DEV 0x07
#define SMSC_CONFIG_ACTIVATE 0x30
#define SMSC_CONFIG_ENTER 0x55
#define SMSC_CONFIG_BASE_HIGH 0x60
#define SMSC_CONFIG_BASE_LOW 0x61
#define SMSC_CONFIG_IRQ 0x70
#define SMSC_CONFIG_EXIT 0xaa
#define SMSC_CONFIG_MODE 0xf0
 
#define SMSC_CONFIG_DEV_COM1 0x04
#define SMSC_CONFIG_DEV_COM2 0x05
 
#define SMSC_CONFIG_MODE_HIGH 0x02
 
#define SMSC_CONFIG_ACTIVATE_ENABLE 0x01
 
 
void
cyg_hal_init_superIO(void)
{
HAL_WRITE_UINT8(SMSC_CONFIG, SMSC_CONFIG_ENTER);
 
// Configure and enable COM1
HAL_WRITE_UINT8(SMSC_CONFIG, SMSC_CONFIG_DEV);
HAL_WRITE_UINT8(SMSC_CONFIG_DATA, SMSC_CONFIG_DEV_COM1);
 
HAL_WRITE_UINT8(SMSC_CONFIG, SMSC_CONFIG_BASE_HIGH);
HAL_WRITE_UINT8(SMSC_CONFIG_DATA, 0x03);
HAL_WRITE_UINT8(SMSC_CONFIG, SMSC_CONFIG_BASE_LOW);
HAL_WRITE_UINT8(SMSC_CONFIG_DATA, 0xf8);
 
HAL_WRITE_UINT8(SMSC_CONFIG, SMSC_CONFIG_IRQ);
HAL_WRITE_UINT8(SMSC_CONFIG_DATA,
(CYGNUM_HAL_INTERRUPT_TTY0-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE));
 
HAL_WRITE_UINT8(SMSC_CONFIG, SMSC_CONFIG_MODE);
HAL_WRITE_UINT8(SMSC_CONFIG_DATA, SMSC_CONFIG_MODE_HIGH);
 
HAL_WRITE_UINT8(SMSC_CONFIG, SMSC_CONFIG_ACTIVATE);
HAL_WRITE_UINT8(SMSC_CONFIG_DATA, SMSC_CONFIG_ACTIVATE_ENABLE);
 
// Configure and enable COM2
HAL_WRITE_UINT8(SMSC_CONFIG, SMSC_CONFIG_DEV);
HAL_WRITE_UINT8(SMSC_CONFIG_DATA, SMSC_CONFIG_DEV_COM2);
 
HAL_WRITE_UINT8(SMSC_CONFIG, SMSC_CONFIG_BASE_HIGH);
HAL_WRITE_UINT8(SMSC_CONFIG_DATA, 0x02);
HAL_WRITE_UINT8(SMSC_CONFIG, SMSC_CONFIG_BASE_LOW);
HAL_WRITE_UINT8(SMSC_CONFIG_DATA, 0xf8);
 
HAL_WRITE_UINT8(SMSC_CONFIG, SMSC_CONFIG_IRQ);
HAL_WRITE_UINT8(SMSC_CONFIG_DATA,
(CYGNUM_HAL_INTERRUPT_TTY1-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE));
 
HAL_WRITE_UINT8(SMSC_CONFIG, SMSC_CONFIG_MODE);
HAL_WRITE_UINT8(SMSC_CONFIG_DATA, SMSC_CONFIG_MODE_HIGH);
 
HAL_WRITE_UINT8(SMSC_CONFIG, SMSC_CONFIG_ACTIVATE);
HAL_WRITE_UINT8(SMSC_CONFIG_DATA, SMSC_CONFIG_ACTIVATE_ENABLE);
 
HAL_WRITE_UINT8(SMSC_CONFIG, SMSC_CONFIG_EXIT);
 
}
 
//-----------------------------------------------------------------------------
// end of smsc37m81x.c
 
/v2_0/misc/redboot_RAM.ecm
0,0 → 1,106
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware malta ;
template redboot ;
package -hardware CYGPKG_HAL_MIPS v2_0 ;
package -hardware CYGPKG_HAL_MIPS_MIPS32 v2_0 ;
package -hardware CYGPKG_HAL_MIPS_MALTA v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_INTEL_28FXXX v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_MALTA v2_0 ;
package -hardware CYGPKG_IO_PCI v2_0 ;
package -hardware CYGPKG_DEVS_ETH_AMD_PCNET v2_0 ;
package -hardware CYGPKG_DEVS_ETH_MIPS_MIPS32_MALTA v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package -template CYGPKG_ISOINFRA v2_0 ;
package -template CYGPKG_LIBC_STRING v2_0 ;
package -template CYGPKG_NS_DNS v2_0 ;
package CYGPKG_IO_FLASH v2_0 ;
package CYGPKG_IO_ETH_DRIVERS v2_0 ;
package CYGPKG_MEMALLOC v2_0 ;
package CYGPKG_COMPRESS_ZLIB v2_0 ;
};
 
cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
inferred_value 0
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 4096
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_option CYGHWR_HAL_MIPS_MIPS32_CORE {
user_value 4Kc
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
inferred_value 0x40000
};
 
cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS {
user_value 1
};
 
cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/bsdstring.h>
};
 
cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_DNS_HEADER {
inferred_value 1 <cyg/ns/dns/dns.h>
};
 
cdl_option CYGPKG_NS_DNS_BUILD {
inferred_value 0
};
 
cdl_option CYGHWR_DEVS_FLASH_INTEL_28F160S5 {
inferred_value 1
};
 
 
/v2_0/misc/redboot_ROM_5kc.ecm
0,0 → 1,114
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware malta ;
template redboot ;
package -hardware CYGPKG_HAL_MIPS v2_0 ;
package -hardware CYGPKG_HAL_MIPS_MIPS64 v2_0 ;
package -hardware CYGPKG_HAL_MIPS_MALTA v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_INTEL_28FXXX v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_MALTA v2_0 ;
package -hardware CYGPKG_IO_PCI v2_0 ;
package -hardware CYGPKG_DEVS_ETH_AMD_PCNET v2_0 ;
package -hardware CYGPKG_DEVS_ETH_MIPS_MIPS32_MALTA v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package -template CYGPKG_ISOINFRA v2_0 ;
package -template CYGPKG_LIBC_STRING v2_0 ;
package -template CYGPKG_NS_DNS v2_0 ;
package CYGPKG_IO_FLASH v2_0 ;
package CYGPKG_IO_ETH_DRIVERS v2_0 ;
package CYGPKG_COMPRESS_ZLIB v2_0 ;
package CYGPKG_MEMALLOC v2_0 ;
};
 
cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
inferred_value 0
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 4096
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
};
 
cdl_option CYGHWR_HAL_MIPS_MIPS64_CORE {
user_value 5K
};
 
cdl_component CYG_HAL_STARTUP {
user_value ROM
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
inferred_value 0x40000
};
 
cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS {
user_value 1
};
 
cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/bsdstring.h>
};
 
cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_DNS_HEADER {
inferred_value 1 <cyg/ns/dns/dns.h>
};
 
cdl_option CYGPKG_NS_DNS_BUILD {
inferred_value 0
};
 
cdl_option CYGHWR_DEVS_FLASH_INTEL_28F160S5 {
inferred_value 1
};
 
 
/v2_0/misc/redboot_RAM_5kc.ecm
0,0 → 1,110
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware malta ;
template redboot ;
package -hardware CYGPKG_HAL_MIPS v2_0 ;
package -hardware CYGPKG_HAL_MIPS_MIPS64 v2_0 ;
package -hardware CYGPKG_HAL_MIPS_MALTA v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_INTEL_28FXXX v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_MALTA v2_0 ;
package -hardware CYGPKG_IO_PCI v2_0 ;
package -hardware CYGPKG_DEVS_ETH_AMD_PCNET v2_0 ;
package -hardware CYGPKG_DEVS_ETH_MIPS_MIPS32_MALTA v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package -template CYGPKG_ISOINFRA v2_0 ;
package -template CYGPKG_LIBC_STRING v2_0 ;
package -template CYGPKG_NS_DNS v2_0 ;
package CYGPKG_IO_FLASH v2_0 ;
package CYGPKG_IO_ETH_DRIVERS v2_0 ;
package CYGPKG_COMPRESS_ZLIB v2_0 ;
package CYGPKG_MEMALLOC v2_0 ;
};
 
cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
inferred_value 0
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 4096
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_option CYGHWR_HAL_MIPS_MIPS64_CORE {
user_value 5K
};
 
cdl_component CYG_HAL_STARTUP {
user_value RAM
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
inferred_value 0x40000
};
 
cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS {
user_value 1
};
 
cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/bsdstring.h>
};
 
cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_DNS_HEADER {
inferred_value 1 <cyg/ns/dns/dns.h>
};
 
cdl_option CYGPKG_NS_DNS_BUILD {
inferred_value 0
};
 
cdl_option CYGHWR_DEVS_FLASH_INTEL_28F160S5 {
inferred_value 1
};
 
 
/v2_0/misc/redboot_ROM.ecm
0,0 → 1,114
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware malta ;
template redboot ;
package -hardware CYGPKG_HAL_MIPS v2_0 ;
package -hardware CYGPKG_HAL_MIPS_MIPS32 v2_0 ;
package -hardware CYGPKG_HAL_MIPS_MALTA v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_INTEL_28FXXX v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_MALTA v2_0 ;
package -hardware CYGPKG_IO_PCI v2_0 ;
package -hardware CYGPKG_DEVS_ETH_AMD_PCNET v2_0 ;
package -hardware CYGPKG_DEVS_ETH_MIPS_MIPS32_MALTA v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package -template CYGPKG_ISOINFRA v2_0 ;
package -template CYGPKG_LIBC_STRING v2_0 ;
package -template CYGPKG_NS_DNS v2_0 ;
package CYGPKG_IO_FLASH v2_0 ;
package CYGPKG_IO_ETH_DRIVERS v2_0 ;
package CYGPKG_COMPRESS_ZLIB v2_0 ;
package CYGPKG_MEMALLOC v2_0 ;
};
 
cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
inferred_value 0
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 4096
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
};
 
cdl_option CYGHWR_HAL_MIPS_MIPS32_CORE {
user_value 4Kc
};
 
cdl_component CYG_HAL_STARTUP {
user_value ROM
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
inferred_value 0x40000
};
 
cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS {
user_value 1
};
 
cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/bsdstring.h>
};
 
cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_DNS_HEADER {
inferred_value 1 <cyg/ns/dns/dns.h>
};
 
cdl_option CYGPKG_NS_DNS_BUILD {
inferred_value 0
};
 
cdl_option CYGHWR_DEVS_FLASH_INTEL_28F160S5 {
inferred_value 1
};
 
 

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