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    /or1k/trunk/ecos-2.0/packages/hal/powerpc/ts1000
    from Rev 1254 to Rev 1765
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  •

Rev 1254 → Rev 1765

/v2_0/cdl/hal_powerpc_ts1000.cdl
0,0 → 1,320
# ====================================================================
#
# hal_powerpc_ts1000.cdl
#
# PowerPC/TS1000 board HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
## Copyright (C) 2002 Gary Thomas
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): jskov
# Original data: hmt
# Contributors: gthomas
# Date: 1999-11-02
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_POWERPC_TS1000 {
display "Allied Telesyn TS1000 board"
parent CYGPKG_HAL_POWERPC
requires CYGPKG_HAL_POWERPC_MPC8xx
define_header hal_powerpc_ts1000.h
include_dir cyg/hal
description "
The TS1000 HAL package provides the support needed to run
eCos on a Allied Telesyn TS1000 board."
 
compile hal_diag.c hal_aux.c ts1000.S
 
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
implements CYGNUM_HAL_QUICC_SMC1
 
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc8xx.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_ts1000.h>"
 
puts $::cdl_header "#define HAL_PLATFORM_CPU \"PowerPC 855\""
puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Allied Telesyn TS1000\""
puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
}
 
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
legal_values {"RAM" "ROM" "ROMRAM"}
default_value {"RAM"}
no_define
define -file system.h CYG_HAL_STARTUP
description "
This option is used to control where the application program will
run, either from RAM or ROM (flash) memory. ROM based applications
must be self contained, while RAM applications will typically assume
the existence of a debug environment, such as GDB stubs."
}
 
cdl_option CYGHWR_HAL_POWERPC_BOARD_SPEED {
display "Development board clock speed (MHz)"
flavor data
legal_values { 25 50 }
default_value 50
description "
TS1000 Development Boards have various system clock speeds
depending on the processor fitted. Select the clock speed
appropriate for your board so that the system can set the serial
baud rate correctly, amongst other things."
}
 
# Real-time clock/counter specifics
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants."
description "
Period is busclock/16/100."
flavor none
cdl_option CYGNUM_HAL_RTC_NUMERATOR {
display "Real-time clock numerator"
flavor data
calculated 1000000000
}
cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
display "Real-time clock denominator"
flavor data
calculated 100
}
cdl_option CYGNUM_HAL_RTC_PERIOD {
display "Real-time clock period"
flavor data
calculated { (((CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/16)/100) }
}
}
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
description "
Global build options including control over
compiler flags, linker flags and choice of toolchain."
 
 
parent CYGPKG_NONE
 
cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
display "Global command prefix"
flavor data
no_define
default_value { "powerpc-eabi" }
description "
This option specifies the command prefix used when
invoking the build tools."
}
 
cdl_option CYGBLD_GLOBAL_CFLAGS {
display "Global compiler flags"
flavor data
no_define
default_value { "-msoft-float -mcpu=860 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which
are used to compile all packages by
default. Individual packages may define
options which override these global flags."
}
 
cdl_option CYGBLD_GLOBAL_LDFLAGS {
display "Global linker flags"
flavor data
no_define
default_value { "-msoft-float -mcpu=860 -g -nostdlib -Wl,--gc-sections -Wl,-static" }
description "
This option controls the global linker flags. Individual
packages may define options which override these global flags."
}
 
cdl_option CYGBLD_BUILD_GDB_STUBS {
display "Build GDB stub ROM image"
default_value 0
requires { CYG_HAL_STARTUP == "ROM" }
requires CYGSEM_HAL_ROM_MONITOR
requires CYGBLD_BUILD_COMMON_GDB_STUBS
requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
no_define
description "
This option enables the building of the GDB stubs for the
board. The common HAL controls takes care of most of the
build process, but the platform CDL takes care of creating
an S-Record data file suitable for programming using
the board's EPPC-Bug firmware monitor."
 
make -priority 320 {
<PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
$(OBJCOPY) -O srec --change-address=0x02000000 $< $(@:.bin=.srec)
$(OBJCOPY) -O binary $< $@
}
}
}
 
cdl_component CYGPKG_HAL_POWERPC_TS1000_OPTIONS {
display "TS1000 build options"
flavor none
description "
Package specific build options including control over
compiler flags used only in building this package,
and details of which tests are built."
 
 
cdl_option CYGPKG_HAL_POWERPC_TS1000_CFLAGS_ADD {
display "Additional compiler flags"
flavor data
no_define
default_value { "" }
description "
This option modifies the set of compiler flags for
building the TS1000 HAL. These flags are used in addition
to the set of global flags."
}
 
cdl_option CYGPKG_HAL_POWERPC_TS1000_CFLAGS_REMOVE {
display "Suppressed compiler flags"
flavor data
no_define
default_value { "" }
description "
This option modifies the set of compiler flags for
building the TS1000 HAL. These flags are removed from
the set of global flags if present."
}
 
cdl_option CYGPKG_HAL_POWERPC_TS1000_TESTS {
display "TS1000 tests"
flavor data
no_define
calculated { "tests/ts1000time" }
description "
This option specifies the set of tests for the TS1000 HAL."
}
}
 
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define
calculated { CYG_HAL_STARTUP == "RAM" ? "powerpc_ts1000_ram" : \
CYG_HAL_STARTUP == "ROMRAM" ? "powerpc_ts1000_romram" : \
"powerpc_ts1000_rom" }
 
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
display "Memory layout linker script fragment"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_powerpc_ts1000_ram.ldi>" : \
CYG_HAL_STARTUP == "ROMRAM" ? "<pkgconf/mlt_powerpc_ts1000_romram.ldi>" : \
"<pkgconf/mlt_powerpc_ts1000_rom.ldi>" }
}
 
cdl_option CYGHWR_MEMORY_LAYOUT_H {
display "Memory layout header file"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_powerpc_ts1000_ram.h>" : \
CYG_HAL_STARTUP == "ROMRAM" ? "<pkgconf/mlt_powerpc_ts1000_romram.h>" : \
"<pkgconf/mlt_powerpc_ts1000_rom.h>" }
}
}
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
display "Behave as a ROM monitor"
flavor bool
default_value 0
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
description "
Enable this option if this program is to be used as a ROM monitor,
i.e. applications will be loaded into RAM on the board, and this
ROM monitor may process exceptions or interrupts generated from the
application. This enables features such as utilizing a separate
interrupt stack when exceptions are generated."
}
 
cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
display "Redboot HAL options"
flavor none
no_define
parent CYGPKG_REDBOOT
active_if CYGPKG_REDBOOT
description "
This option lists the target's requirements for a valid Redboot
configuration."
 
cdl_option CYGSEM_REDBOOT_HAL_LINUX_BOOT {
active_if CYGBLD_BUILD_REDBOOT_WITH_EXEC
display "Support booting Linux via RedBoot"
flavor bool
default_value 0
description "
This option enables RedBoot to support booting of a Linux kernel."
 
compile -library=libextras.a redboot_linux_exec.c
}
 
cdl_option CYGBLD_BUILD_REDBOOT_BIN {
display "Build Redboot ROM binary image"
active_if CYGBLD_BUILD_REDBOOT
default_value 1
no_define
description "This option enables the conversion of the Redboot ELF
image to a binary image suitable for ROM programming."
 
# compile -library=libextras.a redboot_cmds.c
make -priority 325 {
<PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
$(OBJCOPY) -O srec $< $(@:.bin=.srec)
$(OBJCOPY) -O binary $< $@
}
}
}
}
/v2_0/include/plf_intr.h
0,0 → 1,82
#ifndef CYGONCE_HAL_PLF_INTR_H
#define CYGONCE_HAL_PLF_INTR_H
 
//==========================================================================
//
// plf_intr.h
//
// Allied Telesyn TS1000 platform specific interrupt definitions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors: jskov, gthomas
// Date: 2000-06-13
// Purpose: Define platform specific interrupt support
//
// Usage:
// #include <cyg/hal/plf_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
//--------------------------------------------------------------------------
// Control-C support.
 
// Defined by the quicc driver
#include <cyg/hal/quicc/quicc_smc1.h>
 
 
//----------------------------------------------------------------------------
// Reset.
 
externC void _mpc8xx_reset(void);
#define HAL_PLATFORM_RESET() _mpc8xx_reset()
 
#define HAL_PLATFORM_RESET_ENTRY 0xfe000100
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLF_INTR_H
// End of plf_intr.h
/v2_0/include/plf_stub.h
0,0 → 1,88
#ifndef CYGONCE_HAL_PLF_STUB_H
#define CYGONCE_HAL_PLF_STUB_H
 
//=============================================================================
//
// plf_stub.h
//
// Platform header for GDB stub support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov, gthomas
// Date: 1999-02-12
// Purpose: Platform HAL stub support for PowerPC/TS1000 board.
// Usage: #include <cyg/hal/plf_stub.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
 
#include <cyg/hal/ppc_stub.h> // architecture stub support
 
//----------------------------------------------------------------------------
// Define some platform specific communication details. This is mostly
// handled by hal_if now, but we need to make sure the comms tables are
// properly initialized.
 
externC void cyg_hal_plf_comms_init(void);
 
#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
 
#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
//----------------------------------------------------------------------------
// Stub initializer.
externC void hal_ts1000_set_led( int val );
#ifdef CYG_HAL_STARTUP_ROM
# define HAL_STUB_PLATFORM_INIT() hal_ts1000_set_led( 4 )
// to distinguish eCos stub ROM ready state from either RedBoot or app.
#endif
 
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_PLF_STUB_H
// End of plf_stub.h
/v2_0/include/plf_regs.h
0,0 → 1,60
#ifndef CYGONCE_HAL_PLF_REGS_H
#define CYGONCE_HAL_PLF_REGS_H
 
//==========================================================================
//
// plf_regs.h
//
// PowerPC 8xx platform CPU definitions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas
// Date: 2002-06-27
// Purpose:
// Description: Possibly override any platform assumptions
//
// Usage: Included via the variant+architecture register headers:
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#endif // CYGONCE_HAL_PLF_REGS_H
/v2_0/include/pkgconf/mlt_powerpc_ts1000_rom.h
0,0 → 1,35
// eCos memory layout - Thu May 30 10:21:41 2002
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0)
#define CYGMEM_REGION_ram_SIZE (0x1000000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#define CYGMEM_REGION_rom (0xfe000000)
#define CYGMEM_REGION_rom_SIZE (0x800000)
#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_vectors) [];
#endif
#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
#define CYGMEM_SECTION_reserved_vectors_SIZE (0x3000)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
#endif
#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
#endif
#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x1000000 - (size_t) CYG_LABEL_NAME (__heap1))
/v2_0/include/pkgconf/mlt_powerpc_ts1000_romram.h
0,0 → 1,17
// eCos memory layout - Thu May 30 10:05:45 2002
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0)
#define CYGMEM_REGION_ram_SIZE (0x1000000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x1000000 - (size_t) CYG_LABEL_NAME (__heap1))
/v2_0/include/pkgconf/mlt_powerpc_ts1000_rom.ldi
0,0 → 1,31
// eCos memory layout - Thu May 30 10:21:41 2002
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0, LENGTH = 0x1000000
rom : ORIGIN = 0xfe000000, LENGTH = 0x800000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_vectors (rom, 0xfe000000, LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA)
CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000;
CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200;
CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x1); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100;
SECTION_data (ram, ALIGN (0x10), FOLLOWING (.gcc_except_table))
SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
/v2_0/include/pkgconf/mlt_powerpc_ts1000_romram.ldi
0,0 → 1,27
// eCos memory layout - Thu May 30 10:05:45 2002
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0, LENGTH = 0x1000000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_vectors (ram, 0, LMA_EQ_VMA)
SECTION_text (ram, 0x3400, LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
/v2_0/include/pkgconf/mlt_powerpc_ts1000_ram.h
0,0 → 1,37
// eCos memory layout - Thu May 30 10:27:39 2002
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0)
#define CYGMEM_REGION_ram_SIZE (0x1000000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_vectors) [];
#endif
#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
#define CYGMEM_SECTION_reserved_vectors_SIZE (0x3000)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
#endif
#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
#endif
#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_for_rom) [];
#endif
#define CYGMEM_SECTION_reserved_for_rom (CYG_LABEL_NAME (__reserved_for_rom))
#define CYGMEM_SECTION_reserved_for_rom_SIZE (0x3cd00)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x1000000 - (size_t) CYG_LABEL_NAME (__heap1))
/v2_0/include/pkgconf/mlt_powerpc_ts1000_ram.ldi
0,0 → 1,31
// eCos memory layout - Thu May 30 10:27:39 2002
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0, LENGTH = 0x1000000
}
 
SECTIONS
{
SECTIONS_BEGIN
CYG_LABEL_DEFN(__reserved_vectors) = 0; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x3000;
CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200;
CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100;
CYG_LABEL_DEFN(__reserved_for_rom) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_for_rom) + 0x3cd00;
SECTION_vectors (ram, ALIGN (0x10), LMA_EQ_VMA)
SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
/v2_0/include/pkgconf/mlt_powerpc_ts1000_rom.mlt
0,0 → 1,17
version 0
region ram 0 1000000 0 !
region rom fe000000 800000 1 !
section reserved_vectors 3000 1 0 0 1 1 1 1 0 0 reserved_vsr_table reserved_vsr_table !
section reserved_vsr_table 200 1 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table !
section reserved_virtual_table 100 1 0 0 0 1 0 0 data !
section data 0 10 1 1 0 1 0 0 sbss !
section sbss 0 4 0 1 0 1 0 1 bss bss !
section bss 0 10 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
section vectors 0 1 0 1 1 1 1 1 fe000000 fe000000 text text !
section text 0 4 0 1 0 1 0 1 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
section rodata 0 8 0 1 0 1 0 1 fixup fixup !
section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 1 0 1 0 0 0 1 data !
/v2_0/include/pkgconf/mlt_powerpc_ts1000_romram.mlt
0,0 → 1,13
version 0
region ram 0 1000000 0 !
section vectors 0 1 0 1 1 0 1 0 0 0 !
section text 0 1 0 1 1 1 1 1 3400 3400 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
section rodata 0 8 0 1 0 1 0 1 fixup fixup !
section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 1 0 1 0 1 0 1 data data !
section data 0 8 0 1 0 1 0 1 sbss sbss !
section sbss 0 4 0 1 0 1 0 1 bss bss !
section bss 0 10 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
/v2_0/include/pkgconf/mlt_powerpc_ts1000_ram.mlt
0,0 → 1,17
version 0
region ram 0 1000000 0 !
section reserved_vectors 3000 1 0 0 1 1 1 1 0 0 reserved_vsr_table reserved_vsr_table !
section reserved_vsr_table 200 10 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table !
section reserved_virtual_table 100 10 0 0 0 1 0 1 reserved_for_rom reserved_for_rom !
section reserved_for_rom 3cd00 10 0 0 0 1 0 1 vectors vectors !
section vectors 0 10 0 1 0 1 0 1 text text !
section text 0 4 0 1 0 1 0 1 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 8 0 1 0 1 0 1 rodata rodata !
section rodata 0 8 0 1 0 1 0 1 fixup fixup !
section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 1 0 1 0 1 0 1 data data !
section data 0 8 0 1 0 1 0 1 sbss sbss !
section sbss 0 4 0 1 0 1 0 1 bss bss !
section bss 0 10 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
/v2_0/include/plf_cache.h
0,0 → 1,65
#ifndef CYGONCE_PLF_CACHE_H
#define CYGONCE_PLF_CACHE_H
 
//=============================================================================
//
// plf_cache.h
//
// Platform HAL cache details
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2000-01-26
// Purpose: Platform cache control API
// Description: The macros defined here provide the platform specific
// cache control operations / behavior.
// Usage: Is included via the architecture cache header:
// #include <cyg/hal/hal_cache.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
//---------------------------------------------------------------------------
// Initial cache enabling - controlled by common CDL
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_PLF_CACHE_H
// End of plf_cache.h
/v2_0/include/hal_diag.h
0,0 → 1,69
#ifndef CYGONCE_HAL_HAL_DIAG_H
#define CYGONCE_HAL_HAL_DIAG_H
 
//=============================================================================
//
// hal_diag.h
//
// HAL Support for Kernel Diagnostic Routines
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors:nickg
// Date: 1998-03-02
// Purpose: HAL Support for Kernel Diagnostic Routines
// Description: Diagnostic routines for use during kernel development.
// Usage: #include <cyg/hal/hal_diag.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_if.h>
 
#define HAL_DIAG_INIT() hal_if_diag_init()
#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
 
//-----------------------------------------------------------------------------
// end of hal_diag.h
#endif // CYGONCE_HAL_HAL_DIAG_H
/v2_0/ChangeLog
0,0 → 1,86
2002-12-02 Gary Thomas <gthomas@ecoscentric.com>
 
* include/plf_intr.h: Use MPC8xx variant RESET support.
 
2002-11-26 Gary Thomas <gthomas@ecoscentric.com>
 
* cdl/hal_powerpc_ts1000.cdl: Move platform define to platform package.
 
2002-11-25 Gary Thomas <gthomas@ecoscentric.com>
 
* src/ts1000.S: Minor include file cleanup.
 
* cdl/hal_powerpc_ts1000.cdl: Update port layout CDL.
 
2002-10-18 Gary Thomas <gthomas@ecoscentric.com>
 
* cdl/hal_powerpc_ts1000.cdl: Fix clock rate calculation.
 
* misc/redboot_ROMRAM.ecm:
* misc/redboot_ROM.ecm:
* misc/redboot_RAM.ecm: FLASH package name change.
 
* include/plf_cache.h: No need for "old" FLASH cache support.
 
* src/hal_diag.c:
* include/hal_diag.h: Remove old !VIRTUAL_VECTORS cruft.
 
2002-10-15 Gary Thomas <gary@mlbassoc.com>
 
* src/ts1000.S: Don't reset PHY on RAM startup.
 
2002-09-03 Gary Thomas <gary@mlbassoc.com>
 
* src/ts1000.S:
* src/hal_diag.c:
* src/hal_aux.c:
* include/pkgconf/mlt_powerpc_ts1000_romram.mlt:
* include/pkgconf/mlt_powerpc_ts1000_romram.ldi:
* include/pkgconf/mlt_powerpc_ts1000_romram.h:
* include/pkgconf/mlt_powerpc_ts1000_rom.mlt:
* include/pkgconf/mlt_powerpc_ts1000_rom.ldi:
* include/pkgconf/mlt_powerpc_ts1000_rom.h:
* include/pkgconf/mlt_powerpc_ts1000_ram.mlt:
* include/pkgconf/mlt_powerpc_ts1000_ram.ldi:
* include/pkgconf/mlt_powerpc_ts1000_ram.h:
* include/plf_stub.h:
* include/plf_regs.h:
* include/plf_intr.h:
* include/plf_cache.h:
* include/hal_diag.h:
* cdl/hal_powerpc_ts1000.cdl: New platform - Allied Telesyn TS1000.
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/v2_0/src/hal_aux.c
0,0 → 1,84
//=============================================================================
//
// hal_aux.c
//
// HAL auxiliary objects and code; per platform
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt
// Contributors:hmt
// Date: 1999-06-08
// Purpose: HAL aux objects: startup tables.
// Description: Tables for per-platform initialization
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <pkgconf/hal_powerpc_quicc.h>
 
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_mem.h> // HAL memory definitions
#include <cyg/hal/quicc/ppc8xx.h>
#include <cyg/hal/hal_if.h> // hal_if_init
#include CYGHWR_MEMORY_LAYOUT_H
 
// The memory map is weakly defined, allowing the application to redefine
// it if necessary. The regions defined below are the minimum requirements.
CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
// Mapping for the TS1000 (PPC855T) board
CYGARC_MEMDESC_CACHE( 0xfe000000, 0x00800000 ), // ROM region
CYGARC_MEMDESC_NOCACHE( 0xfa000000, 0x00400000 ), // Control/Status+LEDs
CYGARC_MEMDESC_CACHE( CYGMEM_REGION_ram, CYGMEM_REGION_ram_SIZE ), // Main memory
 
CYGARC_MEMDESC_TABLE_END
};
 
//--------------------------------------------------------------------------
// Platform init code.
void
hal_platform_init(void)
{
// Basic hardware initialization has already taken place
 
hal_if_init(); // Initialize logical I/O layer (virtual vector support)
}
 
// EOF hal_aux.c
/v2_0/src/ts1000.S
0,0 → 1,609
##=============================================================================
##
## ts1000.S
##
## TS1000 board hardware setup
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
## Copyright (C) 2002 Gary Thomas
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): hmt
## Contributors:hmt, gthomas
## Date: 1999-06-08
## Purpose: TS1000 board hardware setup
## Description: This file contains any code needed to initialize the
## hardware on an Allied Telesyn TS1000 (PPC855T) board.
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/hal/arch.inc> /* register symbols et al */
#include <cyg/hal/ppc_regs.h> /* on-chip resource layout, special */
/* registers, IMM layout... */
#include <cyg/hal/quicc/ppc8xx.h> /* more of the same */
#------------------------------------------------------------------------------
# this is controlled with one define for tidiness:
# (and it is undefined by default)
 
//#define CYGPRI_RAM_START_PROGRAMS_UPMS
 
#if defined(CYG_HAL_STARTUP_ROM) \
|| defined(CYG_HAL_STARTUP_ROMRAM) \
|| defined(CYGPRI_RAM_START_PROGRAMS_UPMS)
# define CYGPRI_DO_PROGRAM_UPMS
#endif
 
/* The intention is that we only set up the UPMs in ROM start, be it actual
* ROM application start or Stub ROMs that we built from the same sources.
*
* The alternative approach - in which we have reliability doubts - is to
* program the UPMs with *old* timing data in StubROM start, then
* *reprogram* them with *new* timing data in RAM start - and of course
* program with *new* timing data in plain ROM application start.
* (Re-programming from new to new timing data fails - hence the suspicion
* of reprogramming _at_all_, hence this private configuration)
*
* With CYGPRI_RAM_START_PROGRAMS_UPMS left undefined, the former behaviour
* - programming the UPMs exactly once - is obtained. Define it to get the
* latter, untrusted behaviour.
*/
#------------------------------------------------------------------------------
 
//
// Macros to build BR/OR registers
//
#define _BR(_reg,_BA,_PS,_MS,_V) \
.long CYGARC_REG_IMM_BASE+_reg, ((_BA&0xFFFF8000)|(_PS<<10)|(_MS<<6)|_V)
// Port size
#define _PS_32 0x00 // 32 bits
#define _PS_8 0x01 // 8 bits
#define _PS_16 0x02 // 16 bits
// Machine select
#define _MS_GPCM 0x00
#define _MS_UPMA 0x02
#define _MS_UPMB 0x03
 
#define _OR_GPCM(_reg,_AM,_CSNT,_ACS,_BIH,_SCY,_SETA,_TRLX,_EHTR) \
.long CYGARC_REG_IMM_BASE+_reg, ((_AM&0xFFFF8000)|(_CSNT<<11)|(_ACS<<9)|(_BIH<<8)|(_SCY<<4)|(_SETA<<3)|(_TRLX<<2)|(_EHTR<<1))
 
// GPCM - Chip select negation time
#define _CSNT_0 0
#define _CSNT_1 1
// GPCM - Address setup time
#define _ACS_0 0x00 // !CS asserted with address lines
#define _ACS_4 0x02 // !CS asserted 1/4 clock after address lines
#define _ACS_2 0x03 // !CS asserted 1/2 clock after address lines
 
// Burst Inhibit
#define _BIH_0 0 // Bursting supported
#define _BIH_1 1 // Bursting disabled
// GPCM - Address setup times
#define _SCY_0 0x0 // No additional wait states
#define _SCY_1 0x1 // 1 additional wait states
#define _SCY_2 0x2 // 2 additional wait states
#define _SCY_3 0x3 // 3 additional wait states
#define _SCY_4 0x4 // 4 additional wait states
#define _SCY_5 0x5 // 5 additional wait states
#define _SCY_6 0x6 // 6 additional wait states
#define _SCY_7 0x7 // 7 additional wait states
#define _SCY_8 0x8 // 8 additional wait states
#define _SCY_9 0x9 // 9 additional wait states
#define _SCY_10 0xA // 10 additional wait states
#define _SCY_11 0xB // 11 additional wait states
#define _SCY_12 0xC // 12 additional wait states
#define _SCY_13 0xD // 13 additional wait states
#define _SCY_14 0xE // 14 additional wait states
#define _SCY_15 0xF // 15 additional wait states
// GPCM - external transfer acknowledge
#define _SETA_0 0 // No external acknowledge
#define _SETA_1 1 // External acknowledge
 
// GPCM - relaxed timing
#define _TRLX_0 0 // Strict timing
#define _TRLX_1 1 // Relaxed timing (wait states doubled)
// GPCM - external hold time
#define _EHTR_0 0 // Strict timing
#define _EHTR_1 1 // One wait state needed when switching banks
#define _OR_UPM(_reg,_AM,_SAM,_G5LA,_G5LS,_BIH)\
.long CYGARC_REG_IMM_BASE+_reg,((_AM&0xFFFF8000)|(_SAM<<11)|(_G5LA<<10)|(_G5LS<<9)|(_BIH<<8))
 
#define _SAM_0 0 // Address lines are not multiplexed
#define _SAM_1 1 // Address lines are multiplexed by controller
#define _G5LA_0 0 // Use GPLB5 for GPL5
#define _G5LA_1 1 // Use GPLA5 for GPL5
#define _G5LS_0 0 // !GPL5 asserted on low edge
#define _G5LS_1 1 // !GPL5 asserted on high edge
#------------------------------------------------------------------------------
 
//
// PTA field is (System Clock in MHz * Refresh rate in us) / Prescale
// e.g. ((14*3.6864)*62.5)/32 => 100.8 => 101
//
// Since the processor is clocked using the EXTCLK signal, the PLL
// should always run 1-1
//
#define PLPRCR_PTX 0x000
#define MAMR_PTA 98
 
//
// Special MPC8xx cache control
//
#define CACHE_UNLOCKALL 0x0a00
#define CACHE_DISABLE 0x0400
#define CACHE_INVALIDATEALL 0x0c00
#define CACHE_ENABLE 0x0200
#define CACHE_ENABLEBIT 0x8000
 
#define CACHE_FORCEWRITETHROUGH 0x0100
#define CACHE_NOWRITETHROUGH 0x0300
#define CACHE_CLEAR_LE_SWAP 0x0700
#------------------------------------------------------------------------------
 
// LED macro uses r23, r25: r4 assumed to point to IMMR
#define LED( x ) \
lhz r25,PADAT(r4) ; \
andi. r25,r25,(~0x3C&0xFFFF) ; \
ori r25,r25,(x<<2) ; \
sth r25,PADAT(r4) ; \
#------------------------------------------------------------------------------
FUNC_START( hal_hardware_init )
 
mflr r30 // Save original return address
# Throughout this routine, r4 is the base address of the control
# registers. r3 and r5 are scratch in general.
lwi r4,CYGARC_REG_IMM_BASE # base address of control registers
mtspr CYGARC_REG_IMMR,r4
 
//
// Set up GPIO port A - used to drive LEDs.
//
lhz r3,PAODR(r4) // paodr &= ~0x803C
andi. r3,r3,(~0x803C&0xFFFF)
sth r3,PAODR(r4)
lhz r3,PADIR(r4) // padir |= 0x803C -- all outputs
ori r3,r3,0x803C
sth r3,PADIR(r4)
lhz r3,PAPAR(r4) // papar &= ~0x803C
andi. r3,r3,(~0x803C&0xFFFF)
sth r3,PAPAR(r4)
#ifdef CYG_HAL_STARTUP_RAM
lhz r3,PADAT(r4) // Turn off all LEDs, preserve PHY state
ori r3,r3,0x003C
#else
lwi r3,0x803C // Turn off all LEDS, reset PHY
#endif
sth r3,PADAT(r4)
LED( 0 ) # turn all LEDs off
 
# DATA CACHE
mfspr r3,CYGARC_REG_DC_CST /* clear error bits */
lis r3,CACHE_UNLOCKALL
sync
mtspr CYGARC_REG_DC_CST,r3 /* unlock all lines */
lis r3,CACHE_INVALIDATEALL
sync
mtspr CYGARC_REG_DC_CST,r3 /* invalidate all lines */
 
lis r3,CACHE_DISABLE
sync
mtspr CYGARC_REG_DC_CST,r3 /* disable */
lis r3,CACHE_FORCEWRITETHROUGH
sync
mtspr CYGARC_REG_DC_CST,r3 /* set force-writethrough mode */
 
lis r3,CACHE_CLEAR_LE_SWAP
sync
mtspr CYGARC_REG_DC_CST,r3 /* clear little-endian swap mode */
# INSTRUCTION CACHE (no writeback modes)
mfspr r3,CYGARC_REG_IC_CST /* clear error bits */
lis r3,CACHE_UNLOCKALL
mtspr CYGARC_REG_IC_CST,r3 /* unlock all lines */
isync
lis r3,CACHE_INVALIDATEALL
mtspr CYGARC_REG_IC_CST,r3 /* invalidate all lines */
isync
lis r3,CACHE_DISABLE
mtspr CYGARC_REG_IC_CST,r3 /* disable */
isync
sync
LED( 0x01 )
#ifdef CYG_HAL_STARTUP_ROMRAM
// Need to set the PC into the FLASH (ROM) before the address map changes
lwi r3,10f
lwi r5,0xFE000000
or r3,r3,r5
mtctr r3
bctr
10:
#endif
/*
* SIU Initialization.
*/
lwi r3,0x00610400
stw r3,SIUMCR(r4)
 
/*
* Enable bus monitor. Disable Watchdog timer.
*/
lwi r3,0xffffff88
stw r3,SYPCR(r4)
 
/*
* Clear REFA & REFB. Enable but freeze timebase.
*/
lwi r3,0x0000 // FIXME: should this be 0x0000 or 0x00C2
sth r3,TBSCR(r4)
 
/*
* Unlock some RTC registers (see section 5.11.2)
*/
lwi r3,0x55ccaa33
stw r3,RTCSCK(r4)
stw r3,RTCK(r4)
stw r3,RTSECK(r4)
stw r3,RTCALK(r4)
 
/*
* Clear SERC & ALR. RTC runs on freeze. Enable RTC.
*/
li r3,0x0000 // FIXME: should this be 0x0000 or 0x00C3
sth r3,RTCSC(r4)
 
/*
* Clear periodic timer interrupt status.
* Enable periodic timer and stop it on freeze.
*/
li r3,0x0001 // FIXME: should this be 0x0001 or 0x0083
sth r3,PISCR(r4)
 
LED( 0x02 )
/*
* Perform UPM programming by writing to its 64 RAM locations.
* Note that UPM initialization must be done before the Bank Register
* initialization. Otherwise, system may hang when writing to Bank
* Registers in certain cases.
*/
#ifdef CYGPRI_DO_PROGRAM_UPMS
lwi r5,__upmtbl_start
lwi r6,__upmtbl_end
sub r7,r6,r5 /* size of table */
srawi r7,r7,2 /* in words */
lwi r6,0x00800000 /* Command - OP=Write, UPMB, MAD=0 */
or r7,r7,r6
1:
lwz r3,0(r5) /* get data from table */
stw r3,MDR(r4) /* store the data to MD register */
stw r6,MCR(r4) /* issue command to MCR register */
addi r5,r5,4 /* next entry in the table */
addi r6,r6,1 /* next MAD address */
cmpw r6,r7 /* done yet ? */
blt 1b
#endif // CYGPRI_DO_PROGRAM_UPMS
LED( 0x03 )
 
/*
* Set refresh timer prescaler to divide by 8.
*/
li r3,PTP_DIV32
sth r3,MPTPR(r4)
 
/*
* See Table 15-16 MPC860 User's Manual.
*
// Set the value of Machine A Mode Register (MAMR) to $5E802114.
// Field PTA (bits 0-7) = 94
// Field PTAE (bit 8) = 1
// Field AMA (bits 9-11) = 0
// Field Reserved (bit 12) = 0
// Field DSA (bits 13-14) = 0
// Field Reserved (bit 15) = 0
// Field G0CLA (bits 16-18) = 1
// Field GPL_A4DIS (bit 19) = 0
// Field RLFA (bits 20-23) = 1
// Field WLFA (bits 24-27) = 1
// Field TLFA (bits 28-31) = 4
*/
lwi r3,0x00802114|(MAMR_PTA<<24)
stw r3,MAMR(r4)
stw r3,MBMR(r4)
 
/*
* Base Register initialization.
*/
 
//
// Memory map (device addressing) layout
//
bl 10f
mc_regs:
// CS0 - FLASH - 0xFE000000..0xFE7FFFFF, 9 wait states, no bursting
_OR_GPCM(OR0, 0xFF800000, _CSNT_1, _ACS_2, \
_BIH_1, _SCY_9, _SETA_0, _TRLX_1, _EHTR_1)
_BR(BR0, 0xFE000000, _PS_16, _MS_GPCM, 1)
 
// CS1 - DRAM - 0x00000000..0x00FFFFFF,
_BR(BR1, 0x00000000, _PS_32, _MS_UPMB, 1)
_OR_UPM(OR1, 0xFF000000, _SAM_1, _G5LA_0, _G5LS_0, _BIH_0)
// CS2 - FPGA Loading - 0x80020000..0x80027FFF, 7 wait states, no bursting
_BR(BR2, 0x80020000, _PS_32, _MS_GPCM, 1)
_OR_GPCM(OR2, 0xFFFF8000, _CSNT_1, _ACS_2, \
_BIH_1, _SCY_7, _SETA_0, _TRLX_1, _EHTR_1)
// CS3 - FPGA - 0x80030000..0x80037FFF, 7 wait states, no bursting
_OR_GPCM(OR3, 0xFFFF8000, _CSNT_1, _ACS_2, \
_BIH_1, _SCY_7, _SETA_0, _TRLX_1, _EHTR_1)
_BR(BR3, 0x80030000, _PS_32, _MS_GPCM, 1)
// CS4 - DS3 - 0x80040000..0x80047FFF, 7 wait states, no bursting
_OR_GPCM(OR4, 0xFFFF8000, _CSNT_1, _ACS_2, \
_BIH_1, _SCY_7, _SETA_0, _TRLX_1, _EHTR_1)
_BR(BR4, 0x80040000, _PS_32, _MS_GPCM, 1)
// CS5 - DS1 - 0x80050000..0x80057FFF, 7 wait states, no bursting
_OR_GPCM(OR5, 0xFFFF8000, _CSNT_1, _ACS_2, \
_BIH_1, _SCY_7, _SETA_0, _TRLX_1, _EHTR_1)
_BR(BR5, 0x80050000, _PS_32, _MS_GPCM, 1)
.long 0 // End of table
 
//
// Program memory controller registers (using table above)
//
10: mflr r3 // Points to table
subi r3,r3,4
20: lwzu r5,4(r3) // Next address
cmpi 0,r5,0
beq 30f // done?
lwzu r6,4(r3) // value
lwzu r7,4(r3) // second part of address/value pair
lwzu r8,4(r3)
stw r6,0(r5) // store pair in order
stw r8,0(r7)
b 20b
30:
/*
* SYSTEM CLOCK CONTROL REGISTER
// Set the value of System Clock and Reset Control Register (SCCR) to $00400000.
// Field Reserved (bit 0) = 0
// Field COM (bits 1-2) = 0
// Field Reserved (bits 3-5) = 0
// Field TBS (bit 6) = 0
// Field RTDIV (bit 7) = 0
// Field RTSEL (bit 8) = 0
// Field CRQEN (bit 9) = 1
// Field PRQEN (bit 10) = 0
// Field Reserved (bits 11-12) = 0
// Field EBDF (bits 13-14) = 0
// Field Reserved (bits 15-16) = 0
// Field DFSYNC (bits 17-18) = 0
// Field DFBRG (bits 19-20) = 0
// Field DFNL (bits 21-23) = 0
// Field DFNH (bits 24-26) = 0
// Field Reserved (bits 27-31) = 0
*/
lwi r3,0x00400000
stw r3,SCCR(r4)
LED( 0x04 )
 
/*
* PLL, LOW POWER, AND RESET CONTROL REGISTER
// Set the value of PLL, Low Power and Reset Control Register (PLPRCR) to $00C04000.
// Field MF (bits 0-11) = 12
// Field Reserved (bits 12-15) = 0
// Field SPLSS (bit 16) = 0
// Field TEXPS (bit 17) = 1
// Field Reserved (bit 18) = 0
// Field TMIST (bit 19) = 0
// Field Reserved (bit 20) = 0
// Field CSRC (bit 21) = 0
// Field LPM (bits 22-23) = 0
// Field CSR (bit 24) = 0
// Field LOLRE (bit 25) = 0
// Field FIOPD (bit 26) = 0
// Field Reserved (bits 27-31) = 0
*/
lwi r3,0x04000|(PLPRCR_PTX<<20)
stw r3,PLPRCR(r4)
 
lwi r3,0x40000
mtctr r3
10: nop
bdnz 10b
 
/* SDRAM Initialization Sequence, UPMB, CS1 */
li r3,0
stw r3,MAR(r4)
 
lwi r3,0x80802115; /* run precharge from loc 21 (0x15) */
stw r3,MCR(r4)
 
lwi r3,0x80802830; /* run refresh 8 times */
stw r3,MCR(r4)
lwi r3,0x22<<2; // Mode register setting
stw r3,MAR(r4)
 
lwi r3,0x80802116; /* run MRS pattern from loc 22 (0x16) */
stw r3,MCR(r4)
 
# mask interrupt sources in the SIU
lis r2,0
lwi r3,CYGARC_REG_IMM_SIMASK
stw r2,0(r3)
 
# set the decrementer to maxint
lwi r2,0
not r2,r2
mtdec r2
# and enable the timebase and decrementer to make sure
li r2,1 # TBEnable and not TBFreeze
lwi r3,CYGARC_REG_IMM_TBSCR
sth r2,0(r3)
 
LED( 0x05 )
 
#ifdef CYG_HAL_STARTUP_ROM
# move return address to where the ROM is
mflr r3
lwi r4,0x00FFFFFF // CAUTION!! Assumes only low 16M for ROM
and r3,r3,r4
oris r3,r3,CYGMEM_REGION_rom>>16
mtlr r3
#endif
 
#ifdef CYG_HAL_STARTUP_ROMRAM
// Copy image from ROM to RAM
LED(0x06)
lwi r4,0xFE000000
lwi r5,0x01FFFFFF // ROM/FLASH base
and r3,r30,r5 // segment relative
lwi r30,_hal_hardware_init_done
sub r6,r3,r30 // Absolute address
add r6,r6,r4 // FLASH address
lwi r7,0 // where to copy to
lwi r8,__ram_data_end
10: lwz r5,0(r6)
stw r5,0(r7)
addi r6,r6,4
addi r7,r7,4
cmplw r7,r8
bne 10b
#endif
 
LED(0x0F)
mtlr r30 // Restore original link address
blr
FUNC_END( hal_hardware_init )
 
 
#ifdef CYGPRI_DO_PROGRAM_UPMS
# -------------------------------------------------------------------------
# this table initializes the User Programmable Machine (UPM) nastiness
# in the QUICC to control DRAM timing.
 
__upmtbl_start:
 
// UPM 0x00: single read
.long 0x0f0dfc04, 0x0ffffc04, 0x00bf7c04, 0x0ff5fc00
.long 0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04
// UPM 0x08: burst read
.long 0x0f0dfc04, 0x0ffffc04, 0x00bf7c04, 0x00fffc00
.long 0x00fffc00, 0x00fffc00, 0x0ff5fc00, 0x1ffffc05
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
.long 0xfffffc04
// UPM 0x15: initial precharge cycles
.long 0x1ff5fc35
// UPM 0x16: program mode register
.long 0xefcabc34, 0x1f357c35 // 0x1fb57c35 or 0xfffffc04
// UPM 0x18: single write
.long 0x0f0dfc04, 0x0ffffc00, 0x00b77c04, 0x0ffffc04
.long 0x0ff5fc04, 0x1ffffc05, 0xfffffc04, 0xfffffc04
// UPM 0x20: burst write
.long 0x0f0dfc04, 0x0ffffc00, 0x00b77c00, 0x00fffc00
.long 0x00fffc00, 0x00fffc04, 0x0ffffc04, 0x0ff5fc04
.long 0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
// UPM 0x30: refresh
.long 0x0ff5fc00, 0x0ffffc00, 0x0ffd7c80, 0x0ffffc00
.long 0x0ffffc00, 0x0ffffc80, 0x3ffffc07, 0xfffffc04
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
// UPM 0x3C: exception
.long 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
 
__upmtbl_end:
#endif // CYGPRI_DO_PROGRAM_UPMS
FUNC_START(hal_ts1000_set_led)
lwi r4,CYGARC_REG_IMM_BASE # base address of control registers
lhz r5,PADAT(r4)
andi. r5,r5,(~0x3C&0xFFFF)
andi. r3,r3,0x0F
slwi r3,r3,2
or r5,r5,r3
sth r5,PADAT(r4)
lwi r5,_hold_led
stw r3,0(r5)
blr
FUNC_END(hal_ts1000_set_led)
.data
_hold_led:
.long 0
.text
FUNC_START(hal_ts1000_get_led)
lwi r5,_hold_led
lwz r3,0(r5)
blr
FUNC_END(hal_ts1000_get_led)
 
 
#------------------------------------------------------------------------------
# end of ts1000.S
/v2_0/src/hal_diag.c
0,0 → 1,83
//=============================================================================
//
// hal_diag.c
//
// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt
// Contributors:hmt, gthomas
// Date: 1999-06-08
// Purpose: HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_intr.h> // Interrupt macros
 
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
#include <cyg/hal/hal_stub.h> // hal_output_gdb_string
#endif
 
#include <cyg/hal/ppc_regs.h>
#include <cyg/hal/quicc/quicc_smc1.h>
 
void
cyg_hal_plf_comms_init(void)
{
static int initialized = 0;
 
if (initialized)
return;
initialized = 1;
 
cyg_hal_plf_serial_init(); // Defined in hal/powerpc/quicc/...
}
 
// EOF hal_diag.c
/v2_0/misc/redboot_RAM.ecm
0,0 → 1,94
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware ts1000 ;
template redboot ;
package -hardware CYGPKG_HAL_POWERPC v2_0 ;
package -hardware CYGPKG_HAL_POWERPC_MPC8xx v2_0 ;
package -hardware CYGPKG_HAL_POWERPC_TS1000 v2_0 ;
package -hardware CYGPKG_HAL_QUICC v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_POWERPC_TS1000 v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX v2_0 ;
package -hardware CYGPKG_DEVS_ETH_POWERPC_FEC v2_0 ;
package -hardware CYGPKG_DEVS_ETH_POWERPC_TS1000 v2_0 ;
package -hardware CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package -template CYGPKG_ISOINFRA v2_0 ;
package -template CYGPKG_LIBC_STRING v2_0 ;
package -template CYGPKG_NS_DNS v2_0 ;
package -template CYGPKG_CRC v2_0 ;
package CYGPKG_IO_FLASH v2_0 ;
package CYGPKG_IO_ETH_DRIVERS v2_0 ;
};
 
cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
inferred_value 0
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 4096
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
user_value 0x00030000
};
 
cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/bsdstring.h>
};
 
cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_DNS_HEADER {
inferred_value 1 <cyg/ns/dns/dns.h>
};
 
cdl_option CYGPKG_NS_DNS_BUILD {
inferred_value 0
};
 
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29DL640D {
inferred_value 1
};
 
 
/v2_0/misc/redboot_ROM.ecm
0,0 → 1,102
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware ts1000 ;
template redboot ;
package -hardware CYGPKG_HAL_POWERPC v2_0 ;
package -hardware CYGPKG_HAL_POWERPC_MPC8xx v2_0 ;
package -hardware CYGPKG_HAL_POWERPC_TS1000 v2_0 ;
package -hardware CYGPKG_HAL_QUICC v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_POWERPC_TS1000 v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX v2_0 ;
package -hardware CYGPKG_DEVS_ETH_POWERPC_FEC v2_0 ;
package -hardware CYGPKG_DEVS_ETH_POWERPC_TS1000 v2_0 ;
package -hardware CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package -template CYGPKG_ISOINFRA v2_0 ;
package -template CYGPKG_LIBC_STRING v2_0 ;
package -template CYGPKG_NS_DNS v2_0 ;
package -template CYGPKG_CRC v2_0 ;
package CYGPKG_IO_FLASH v2_0 ;
package CYGPKG_IO_ETH_DRIVERS v2_0 ;
};
 
cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
inferred_value 0
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 4096
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
};
 
cdl_component CYG_HAL_STARTUP {
user_value ROM
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
user_value 0x00030000
};
 
cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/bsdstring.h>
};
 
cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_DNS_HEADER {
inferred_value 1 <cyg/ns/dns/dns.h>
};
 
cdl_option CYGPKG_NS_DNS_BUILD {
inferred_value 0
};
 
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29DL640D {
inferred_value 1
};
 
 
/v2_0/misc/redboot_ROMRAM.ecm
0,0 → 1,102
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware ts1000 ;
template redboot ;
package -hardware CYGPKG_HAL_POWERPC v2_0 ;
package -hardware CYGPKG_HAL_POWERPC_MPC8xx v2_0 ;
package -hardware CYGPKG_HAL_POWERPC_TS1000 v2_0 ;
package -hardware CYGPKG_HAL_QUICC v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_POWERPC_TS1000 v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX v2_0 ;
package -hardware CYGPKG_DEVS_ETH_POWERPC_FEC v2_0 ;
package -hardware CYGPKG_DEVS_ETH_POWERPC_TS1000 v2_0 ;
package -hardware CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package -template CYGPKG_ISOINFRA v2_0 ;
package -template CYGPKG_LIBC_STRING v2_0 ;
package -template CYGPKG_NS_DNS v2_0 ;
package -template CYGPKG_CRC v2_0 ;
package CYGPKG_IO_FLASH v2_0 ;
package CYGPKG_IO_ETH_DRIVERS v2_0 ;
};
 
cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
inferred_value 0
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 4096
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
};
 
cdl_component CYG_HAL_STARTUP {
user_value ROMRAM
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
user_value 0x00030000
};
 
cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/bsdstring.h>
};
 
cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_DNS_HEADER {
inferred_value 1 <cyg/ns/dns/dns.h>
};
 
cdl_option CYGPKG_NS_DNS_BUILD {
inferred_value 0
};
 
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29DL640D {
inferred_value 1
};
 
 

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