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    from Rev 1254 to Rev 1765
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Rev 1254 → Rev 1765

/cdl/hal_v85x_v850.cdl
0,0 → 1,121
# ====================================================================
#
# hal_v85x_v850.cdl
#
# NEC/V850 variant architectural HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): gthomas
# Contributors: jlarmour
# Date: 2000-03-09
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_V85X_V850 {
display "V850 variant"
parent CYGPKG_HAL_V85X
hardware
include_dir cyg/hal
define_header hal_v85x_v850.h
description "
The V850 variant HAL package provides generic support
for this processor architecture. It is also necessary to
select a specific target platform HAL package."
 
define_proc {
puts $::cdl_header "#include <pkgconf/hal_v85x.h>"
}
 
compile v850_stub.c v850_misc.c context.S hal_diag.c
 
implements CYGINT_HAL_TESTS_NO_CACHES
 
cdl_interface CYGINT_HAL_V850_DIAG_ONCHIP_SERIAL0 {
display "Defined if platform uses standard on-chip serial0"
}
cdl_option CYGBLD_HAL_V850_DIAG_USE_ONCHIP_SERIAL0 {
display "Build diag driver for on-chip V850 serial 0"
active_if { CYGINT_HAL_V850_DIAG_ONCHIP_SERIAL0 != 0 }
compile hal_diag.c
}
 
cdl_interface CYGINT_HAL_V850_VARIANT_SA1 {
display "Defined if CPU is a V850/SA1"
}
 
cdl_interface CYGINT_HAL_V850_VARIANT_SB1 {
display "Defined if CPU is a V850/SB1"
}
 
requires 1 == CYGINT_HAL_V850_VARIANT_SA1 ^ 1 == CYGINT_HAL_V850_VARIANT_SB1
# by virtue of the above requires:
implements CYGINT_HAL_V85X_VARIANT
 
cdl_option CYGDBG_HAL_V850_ICE {
display "Support debugging via ICE"
default_value { (0 != CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT) && \
("RAM" != CYG_HAL_STARTUP) }
requires CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
implements CYGINT_HAL_V85X_ICE_DEBUG
compile -library=libextras.a v850_ice.cxx
description \
"This option enables additional support for debugging via
ICE, chiefly in the form of an interface to gdbserv which
allows it to provide eCos thread data in GDB."
}
 
make {
<PREFIX>/lib/target.ld: <PACKAGE>/src/v85x_v850.ld
$(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 target.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm target.tmp
}
 
cdl_option CYGBLD_LINKER_SCRIPT {
display "Linker script"
flavor data
no_define
calculated { "src/v85x_v850.ld" }
}
 
}
/tests/nmitest.c
0,0 → 1,97
//==========================================================================
//
// nmitest.c
//
// V850 NMI test program
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jlarmour
// Contributors: jlarmour
// Date: 2001-02-01
// Purpose: Test NMI function
// Description: This test allows the NMI functionality to be tested.
// It is not built by default.
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#include <cyg/hal/hal_intr.h>
#include <cyg/infra/diag.h>
 
#include <cyg/kernel/kapi.h>
 
int nmicount;
char stack[4096];
static cyg_handle_t thr0h;
static cyg_thread thr0;
 
void
nmi_handler(cyg_addrword_t data, cyg_code_t exception_number,
cyg_addrword_t info)
{
nmicount++;
}
 
static void
entry0( cyg_addrword_t data )
{
int oldnmicount=0;
 
cyg_exception_set_handler( CYGNUM_HAL_VECTOR_NMI,
&nmi_handler,
0,
NULL,
NULL );
for (;;) {
if ( oldnmicount != nmicount ) {
diag_printf("Caught NMI\n");
oldnmicount = nmicount;
}
}
}
 
void
cyg_user_start(void)
{
cyg_thread_create(4, entry0, (cyg_addrword_t)0, "thread 0",
(void *)&stack[0], sizeof(stack), &thr0h, &thr0 );
cyg_thread_resume(thr0h);
}
 
// EOF nmitest.c
/include/v850_common.h
0,0 → 1,562
#ifndef CYGONCE_V850_COMMON_H
#define CYGONCE_V850_COMMON_H
 
/*=============================================================================
//
// v850_common.h
//
// NEC/V850 common definitions
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas, jlarmour
// Contributors: gthomas, jlarmour
// Date: 2000-03-10
// Purpose: NEC/V850 CPU family hardware description
// Description:
// Usage: #include <cyg/hal/v850_common.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
// Note: these defintions match the documentation, thus no attempt is made
// to sanitise (mangle) the names. Also, care should be taken to keep this
// clean for use in assembly code (no "C" constructs).
 
#include <pkgconf/hal.h>
 
// These definitions are for the NEC V850/SA1 (70301x)
 
#if CYGINT_HAL_V850_VARIANT_SA1
 
#define V850_REGS 0xFFFFF000
 
#define V850_REG_P0 0xFFFFF000
#define V850_REG_P1 0xFFFFF002
#define V850_REG_P2 0xFFFFF004
#define V850_REG_P3 0xFFFFF006
#define V850_REG_P4 0xFFFFF008
#define V850_REG_P5 0xFFFFF00A
#define V850_REG_P6 0xFFFFF00C
#define V850_REG_P7 0xFFFFF00E
#define V850_REG_P8 0xFFFFF010
#define V850_REG_P9 0xFFFFF012
#define V850_REG_P10 0xFFFFF014
#define V850_REG_P11 0xFFFFF016
#define V850_REG_P12 0xFFFFF018
 
#define V850_REG_PM0 0xFFFFF020
#define V850_REG_PM1 0xFFFFF022
#define V850_REG_PM2 0xFFFFF024
#define V850_REG_PM3 0xFFFFF026
#define V850_REG_PM4 0xFFFFF028
#define V850_REG_PM5 0xFFFFF02A
#define V850_REG_PM6 0xFFFFF02C
#define V850_REG_PM9 0xFFFFF032
#define V850_REG_PM10 0xFFFFF034
#define V850_REG_PM11 0xFFFFF036
#define V850_REG_PM12 0xFFFFF038
 
#define V850_REG_MM 0xFFFFF04C
 
#define V850_REG_PMC12 0xFFFFF058
 
#define V850_REG_DWC 0xFFFFF060
#define V850_REG_BCC 0xFFFFF062
#define V850_REG_SYC 0xFFFFF064
#define V850_REG_MAM 0xFFFFF068
 
#define V850_REG_PSC 0xFFFFF070
#define V850_REG_PCC 0xFFFFF074
#define V850_REG_SYS 0xFFFFF078
 
#define V850_REG_PU0 0xFFFFF080
#define V850_REG_PU1 0xFFFFF082
#define V850_REG_PU2 0xFFFFF084
#define V850_REG_PU3 0xFFFFF086
#define V850_REG_PU10 0xFFFFF094
#define V850_REG_PU11 0xFFFFF096
 
#define V850_REG_PF1 0xFFFFF0A2
#define V850_REG_PF2 0xFFFFF0A4
#define V850_REG_PF10 0xFFFFF0B4
 
#define V850_REG_EGP0 0xFFFFF0C0
#define V850_REG_EGN0 0xFFFFF0C2
 
#define V850_REG_WDTIC 0xFFFFF100
#define V850_REG_PIC0 0xFFFFF102
#define V850_REG_PIC1 0xFFFFF104
#define V850_REG_PIC2 0xFFFFF106
#define V850_REG_PIC3 0xFFFFF108
#define V850_REG_PIC4 0xFFFFF10A
#define V850_REG_PIC5 0xFFFFF10C
#define V850_REG_PIC6 0xFFFFF10E
#define V850_REG_WTIIC 0xFFFFF110
#define V850_REG_WTNIIC 0xFFFFF110
#define V850_REG_TMIC00 0xFFFFF112
#define V850_REG_TMIC01 0xFFFFF114
#define V850_REG_TMIC10 0xFFFFF116
#define V850_REG_TMIC11 0xFFFFF118
#define V850_REG_TMIC2 0xFFFFF11A
#define V850_REG_TMIC3 0xFFFFF11C
#define V850_REG_TMIC4 0xFFFFF11E
#define V850_REG_TMIC5 0xFFFFF120
#define V850_REG_CSIC0 0xFFFFF122
#define V850_REG_SERIC0 0xFFFFF124
#define V850_REG_CSIC1 0xFFFFF126
#define V850_REG_SRIC0 0xFFFFF126
#define V850_REG_STIC0 0xFFFFF128
#define V850_REG_CSIC2 0xFFFFF12A
#define V850_REG_SRIC2 0xFFFFF12A
#define V850_REG_SERIC1 0xFFFFF12C
#define V850_REG_SRIC1 0xFFFFF12E
#define V850_REG_STIC1 0xFFFFF130
#define V850_REG_ADIC 0xFFFFF132
#define V850_REG_DMAIC0 0xFFFFF134
#define V850_REG_DMAIC1 0xFFFFF136
#define V850_REG_DMAIC2 0xFFFFF138
#define V850_REG_WTIC 0xFFFFF13A
#define V850_REG_WTNIC 0xFFFFF13A
 
#define V850_REG_ISPR 0xFFFFF166
#define V850_REG_PRCMD 0xFFFFF170
 
#define V850_REG_DIOA0 0xFFFFF180
#define V850_REG_DRA0 0xFFFFF182
#define V850_REG_DBC0 0xFFFFF184
#define V850_REG_DCHC0 0xFFFFF186
 
#define V850_REG_DIOA1 0xFFFFF190
#define V850_REG_DRA1 0xFFFFF192
#define V850_REG_DBC1 0xFFFFF194
#define V850_REG_DCHC1 0xFFFFF196
 
#define V850_REG_DIOA2 0xFFFFF1A0
#define V850_REG_DRA2 0xFFFFF1A2
#define V850_REG_DBC2 0xFFFFF1A4
#define V850_REG_DCHC2 0xFFFFF1A6
 
#define V850_REG_TM0 0xFFFFF200
#define V850_REG_CR00 0xFFFFF202
#define V850_REG_CR01 0xFFFFF204
#define V850_REG_PRM0 0xFFFFF206
#define V850_REG_PRM00 0xFFFFF206
#define V850_REG_TMC0 0xFFFFF208
#define V850_REG_CRC0 0xFFFFF20A
#define V850_REG_TOC0 0xFFFFF20C
#define V850_REG_PRM01 0xFFFFF20E
 
#define V850_REG_TM1 0xFFFFF210
#define V850_REG_CR10 0xFFFFF212
#define V850_REG_CR11 0xFFFFF214
#define V850_REG_PRM1 0xFFFFF216
#define V850_REG_PRM10 0xFFFFF216
#define V850_REG_TMC1 0xFFFFF218
#define V850_REG_CRC1 0xFFFFF21A
#define V850_REG_TOC1 0xFFFFF21C
#define V850_REG_PRM11 0xFFFFF21E
 
#define V850_REG_TM2 0xFFFFF240
#define V850_REG_CR20 0xFFFFF242
#define V850_REG_TCL2 0xFFFFF244
#define V850_REG_TMC2 0xFFFFF246
#define V850_REG_TM23 0xFFFFF24A
#define V850_REG_CR23 0xFFFFF24C
#define V850_REG_TCL21 0xFFFFF24E
 
#define V850_REG_TM3 0xFFFFF250
#define V850_REG_CR30 0xFFFFF252
#define V850_REG_TCL3 0xFFFFF254
#define V850_REG_TMC3 0xFFFFF256
#define V850_REG_TCL31 0xFFFFF25E
 
#define V850_REG_TM4 0xFFFFF260
#define V850_REG_CR40 0xFFFFF262
#define V850_REG_TCL4 0xFFFFF264
#define V850_REG_TMC4 0xFFFFF266
#define V850_REG_TM45 0xFFFFF26A
#define V850_REG_CR45 0xFFFFF26C
#define V850_REG_TCL41 0xFFFFF26E
 
#define V850_REG_TM5 0xFFFFF270
#define V850_REG_CR50 0xFFFFF272
#define V850_REG_TCL5 0xFFFFF274
#define V850_REG_TMC5 0xFFFFF276
#define V850_REG_TCL51 0xFFFFF27E
 
#define V850_REG_SIO0 0xFFFFF2A0
#define V850_REG_CSIM0 0xFFFFF2A2
#define V850_REG_CSIS0 0xFFFFF2A4
 
#define V850_REG_SIO1 0xFFFFF2B0
#define V850_REG_CSIM1 0xFFFFF2B2
#define V850_REG_CSIS1 0xFFFFF2B4
 
#define V850_REG_SIO2 0xFFFFF2C0
#define V850_REG_CSIM2 0xFFFFF2C2
#define V850_REG_CSIS2 0xFFFFF2C4
 
#define V850_REG_ASIM0 0xFFFFF300
#define V850_REG_ASIS0 0xFFFFF302
#define V850_REG_BRGC0 0xFFFFF304
#define V850_REG_TXS0 0xFFFFF306
#define V850_REG_RXB0 0xFFFFF308
#define V850_REG_BRGMC0 0xFFFFF30E
#define V850_REG_BRGMC00 0xFFFFF30E
 
#define V850_REG_ASIM1 0xFFFFF310
#define V850_REG_ASIS1 0xFFFFF312
#define V850_REG_BRGC1 0xFFFFF314
#define V850_REG_TXS1 0xFFFFF316
#define V850_REG_RXB1 0xFFFFF318
#define V850_REG_BRGMC1 0xFFFFF31E
#define V850_REG_BRGMC10 0xFFFFF31E
#define V850_REG_BRGMC01 0xFFFFF320
 
#define V850_REG_IICC0 0xFFFFF340
#define V850_REG_IICS0 0xFFFFF342
#define V850_REG_IICCL0 0xFFFFF344
#define V850_REG_SVA0 0xFFFFF346
#define V850_REG_IIC0 0xFFFFF348
#define V850_REG_IICX0 0xFFFFF34A
 
#define V850_REG_WTM 0xFFFFF360
#define V850_REG_OSTS 0xFFFFF380
#define V850_REG_WDCS 0xFFFFF382
#define V850_REG_WDTM 0xFFFFF384
 
#define V850_REG_RTBL 0xFFFFF3A0
#define V850_REG_RTBH 0xFFFFF3A2
#define V850_REG_RTPM 0xFFFFF3A4
#define V850_REG_RTPC 0xFFFFF3A6
 
#define V850_REG_ADM 0xFFFFF3C0
#define V850_REG_ADS 0xFFFFF3C2
#define V850_REG_ADCR 0xFFFFF3C4
#define V850_REG_ADCRH 0xFFFFF3C6
 
/*---------------------------------------------------------------------------*/
 
// These definitions are for the NEC V850/SB1 (70303x)
 
#elif CYGINT_HAL_V850_VARIANT_SB1
 
#define V850_REGS 0xFFFFF000
 
#define V850_REG_P0 0xFFFFF000
#define V850_REG_P1 0xFFFFF002
#define V850_REG_P2 0xFFFFF004
#define V850_REG_P3 0xFFFFF006
#define V850_REG_P4 0xFFFFF008
#define V850_REG_P5 0xFFFFF00A
#define V850_REG_P6 0xFFFFF00C
#define V850_REG_P7 0xFFFFF00E
#define V850_REG_P8 0xFFFFF010
#define V850_REG_P9 0xFFFFF012
#define V850_REG_P10 0xFFFFF014
#define V850_REG_P11 0xFFFFF016
 
#define V850_REG_PM0 0xFFFFF020
#define V850_REG_PM1 0xFFFFF022
#define V850_REG_PM2 0xFFFFF024
#define V850_REG_PM3 0xFFFFF026
#define V850_REG_PM4 0xFFFFF028
#define V850_REG_PM5 0xFFFFF02A
#define V850_REG_PM6 0xFFFFF02C
#define V850_REG_PM9 0xFFFFF032
#define V850_REG_PM10 0xFFFFF034
#define V850_REG_PM11 0xFFFFF036
 
#define V850_REG_PAC 0xFFFFF040
#define V850_REG_MM 0xFFFFF04C
 
#define V850_REG_DWC 0xFFFFF060
#define V850_REG_BCC 0xFFFFF062
#define V850_REG_SYC 0xFFFFF064
#define V850_REG_MAM 0xFFFFF068
 
#define V850_REG_PSC 0xFFFFF070
#define V850_REG_PCC 0xFFFFF074
#define V850_REG_SYS 0xFFFFF078
 
#define V850_REG_PU0 0xFFFFF080
#define V850_REG_PU1 0xFFFFF082
#define V850_REG_PU2 0xFFFFF084
#define V850_REG_PU3 0xFFFFF086
#define V850_REG_PU10 0xFFFFF094
#define V850_REG_PU11 0xFFFFF096
 
#define V850_REG_PF1 0xFFFFF0A2
#define V850_REG_PF2 0xFFFFF0A4
#define V850_REG_PF3 0xFFFFF0A6
#define V850_REG_PF10 0xFFFFF0B4
 
#define V850_REG_EGP0 0xFFFFF0C0
#define V850_REG_EGN0 0xFFFFF0C2
 
#define V850_REG_WDTIC 0xFFFFF100
#define V850_REG_PIC0 0xFFFFF102
#define V850_REG_PIC1 0xFFFFF104
#define V850_REG_PIC2 0xFFFFF106
#define V850_REG_PIC3 0xFFFFF108
#define V850_REG_PIC4 0xFFFFF10A
#define V850_REG_PIC5 0xFFFFF10C
#define V850_REG_PIC6 0xFFFFF10E
#define V850_REG_WTNIIC 0xFFFFF118
#define V850_REG_TMIC00 0xFFFFF11A
#define V850_REG_TMIC01 0xFFFFF11C
#define V850_REG_TMIC10 0xFFFFF11E
#define V850_REG_TMIC11 0xFFFFF120
#define V850_REG_TMIC2 0xFFFFF122
#define V850_REG_TMIC3 0xFFFFF124
#define V850_REG_TMIC4 0xFFFFF126
#define V850_REG_TMIC5 0xFFFFF128
#define V850_REG_TMIC6 0xFFFFF12A
#define V850_REG_TMIC7 0xFFFFF12C
#define V850_REG_CSIC0 0xFFFFF12E
#define V850_REG_SERIC0 0xFFFFF130
#define V850_REG_CSIC1 0xFFFFF132
#define V850_REG_SRIC0 0xFFFFF132
#define V850_REG_STIC0 0xFFFFF134
#define V850_REG_CSIC2 0xFFFFF136
#define V850_REG_SRIC2 0xFFFFF136
#define V850_REG_IICIC1 0xFFFFF138
#define V850_REG_SERIC1 0xFFFFF13A
#define V850_REG_CSIC3 0xFFFFF13C
#define V850_REG_SRIC3 0xFFFFF13C
#define V850_REG_STIC1 0xFFFFF13E
#define V850_REG_CSIC4 0xFFFFF140
#define V850_REG_SRIC4 0xFFFFF140
#define V850_REG_IEBIC1 0xFFFFF142
#define V850_REG_IEBIC2 0xFFFFF144
#define V850_REG_ADIC 0xFFFFF146
#define V850_REG_DMAIC0 0xFFFFF148
#define V850_REG_DMAIC1 0xFFFFF14A
#define V850_REG_DMAIC2 0xFFFFF14C
#define V850_REG_DMAIC3 0xFFFFF14E
#define V850_REG_DMAIC4 0xFFFFF150
#define V850_REG_DMAIC5 0xFFFFF152
#define V850_REG_WTNIC 0xFFFFF154
#define V850_REG_KRIC 0xFFFFF156
 
#define V850_REG_ISPR 0xFFFFF166
#define V850_REG_PRCMD 0xFFFFF170
 
#define V850_REG_DIOA0 0xFFFFF180
#define V850_REG_DRA0 0xFFFFF182
#define V850_REG_DBC0 0xFFFFF184
#define V850_REG_DCHC0 0xFFFFF186
 
#define V850_REG_DIOA1 0xFFFFF190
#define V850_REG_DRA1 0xFFFFF192
#define V850_REG_DBC1 0xFFFFF194
#define V850_REG_DCHC1 0xFFFFF196
 
#define V850_REG_DIOA2 0xFFFFF1A0
#define V850_REG_DRA2 0xFFFFF1A2
#define V850_REG_DBC2 0xFFFFF1A4
#define V850_REG_DCHC2 0xFFFFF1A6
 
#define V850_REG_DIOA3 0xFFFFF1B0
#define V850_REG_DRA3 0xFFFFF1B2
#define V850_REG_DBC3 0xFFFFF1B4
#define V850_REG_DCHC3 0xFFFFF1B6
 
#define V850_REG_DIOA4 0xFFFFF1C0
#define V850_REG_DRA4 0xFFFFF1C2
#define V850_REG_DBC4 0xFFFFF1C4
#define V850_REG_DCHC4 0xFFFFF1C6
 
#define V850_REG_DIOA5 0xFFFFF1D0
#define V850_REG_DRA5 0xFFFFF1D2
#define V850_REG_DBC5 0xFFFFF1D4
#define V850_REG_DCHC5 0xFFFFF1D6
 
#define V850_REG_TM0 0xFFFFF200
#define V850_REG_CR00 0xFFFFF202
#define V850_REG_CR01 0xFFFFF204
#define V850_REG_PRM00 0xFFFFF206
#define V850_REG_TMC0 0xFFFFF208
#define V850_REG_CRC0 0xFFFFF20A
#define V850_REG_TOC0 0xFFFFF20C
#define V850_REG_PRM01 0xFFFFF20E
 
#define V850_REG_TM1 0xFFFFF210
#define V850_REG_CR10 0xFFFFF212
#define V850_REG_CR11 0xFFFFF214
#define V850_REG_PRM10 0xFFFFF216
#define V850_REG_TMC1 0xFFFFF218
#define V850_REG_CRC1 0xFFFFF21A
#define V850_REG_TOC1 0xFFFFF21C
#define V850_REG_PRM11 0xFFFFF21E
 
#define V850_REG_TM2 0xFFFFF240
#define V850_REG_CR20 0xFFFFF242
#define V850_REG_TCL20 0xFFFFF244
#define V850_REG_TMC2 0xFFFFF246
#define V850_REG_TM23 0xFFFFF24A
#define V850_REG_CR23 0xFFFFF24C
#define V850_REG_TCL21 0xFFFFF24E
 
#define V850_REG_TM3 0xFFFFF250
#define V850_REG_CR30 0xFFFFF252
#define V850_REG_TCL30 0xFFFFF254
#define V850_REG_TMC3 0xFFFFF256
#define V850_REG_TCL31 0xFFFFF25E
 
#define V850_REG_TM4 0xFFFFF260
#define V850_REG_CR40 0xFFFFF262
#define V850_REG_TCL40 0xFFFFF264
#define V850_REG_TMC4 0xFFFFF266
#define V850_REG_TM45 0xFFFFF26A
#define V850_REG_CR45 0xFFFFF26C
#define V850_REG_TCL41 0xFFFFF26E
 
#define V850_REG_TM5 0xFFFFF270
#define V850_REG_CR50 0xFFFFF272
#define V850_REG_TCL50 0xFFFFF274
#define V850_REG_TMC5 0xFFFFF276
#define V850_REG_TCL51 0xFFFFF27E
 
#define V850_REG_TM6 0xFFFFF280
#define V850_REG_CR60 0xFFFFF282
#define V850_REG_TCL60 0xFFFFF284
#define V850_REG_TMC6 0xFFFFF286
#define V850_REG_TM67 0xFFFFF28A
#define V850_REG_CR67 0xFFFFF28C
#define V850_REG_TCL61 0xFFFFF28E
 
#define V850_REG_TM7 0xFFFFF290
#define V850_REG_CR70 0xFFFFF292
#define V850_REG_TCL70 0xFFFFF294
#define V850_REG_TMC7 0xFFFFF296
#define V850_REG_TCL71 0xFFFFF29E
 
#define V850_REG_SIO0 0xFFFFF2A0
#define V850_REG_CSIM0 0xFFFFF2A2
#define V850_REG_CSIS0 0xFFFFF2A4
 
#define V850_REG_SIO1 0xFFFFF2B0
#define V850_REG_CSIM1 0xFFFFF2B2
#define V850_REG_CSIS1 0xFFFFF2B4
 
#define V850_REG_SIO2 0xFFFFF2C0
#define V850_REG_CSIM2 0xFFFFF2C2
#define V850_REG_CSIS2 0xFFFFF2C4
 
#define V850_REG_SIO3 0xFFFFF2D0
#define V850_REG_CSIM3 0xFFFFF2D2
#define V850_REG_CSIS3 0xFFFFF2D4
 
#define V850_REG_SIO4 0xFFFFF2E0
#define V850_REG_CSIM4 0xFFFFF2E2
#define V850_REG_CSIB4 0xFFFFF2E4
#define V850_REG_BRGCN4 0xFFFFF2E6
#define V850_REG_BRGCK4 0xFFFFF2E8
 
#define V850_REG_ASIM0 0xFFFFF300
#define V850_REG_ASIS0 0xFFFFF302
#define V850_REG_BRGC0 0xFFFFF304
#define V850_REG_TXS0 0xFFFFF306
#define V850_REG_RXB0 0xFFFFF308
#define V850_REG_BRGMC00 0xFFFFF30E
 
#define V850_REG_ASIM1 0xFFFFF310
#define V850_REG_ASIS1 0xFFFFF312
#define V850_REG_BRGC1 0xFFFFF314
#define V850_REG_TXS1 0xFFFFF316
#define V850_REG_RXB1 0xFFFFF318
#define V850_REG_BRGMC10 0xFFFFF31E
#define V850_REG_BRGMC01 0xFFFFF320
#define V850_REG_BRGMC11 0xFFFFF322
 
#define V850_REG_IICC0 0xFFFFF340
#define V850_REG_IICS0 0xFFFFF342
#define V850_REG_IICCL0 0xFFFFF344
#define V850_REG_SVA0 0xFFFFF346
#define V850_REG_IIC0 0xFFFFF348
#define V850_REG_IICX0 0xFFFFF34A
#define V850_REG_IICCE0 0xFFFFF34C
 
#define V850_REG_IICC1 0xFFFFF350
#define V850_REG_IICS1 0xFFFFF352
#define V850_REG_IICCL1 0xFFFFF354
#define V850_REG_SVA1 0xFFFFF356
#define V850_REG_IIC1 0xFFFFF358
#define V850_REG_IICX1 0xFFFFF35A
#define V850_REG_IICCE1 0xFFFFF35C
 
#define V850_REG_WTNM 0xFFFFF360
#define V850_REG_WTNCS 0xFFFFF364
 
#define V850_REG_CORCN 0xFFFFF36C
#define V850_REG_CORRQ 0xFFFFF36E
#define V850_REG_CORAD0 0xFFFFF370
#define V850_REG_CORAD1 0xFFFFF374
#define V850_REG_CORAD2 0xFFFFF378
#define V850_REG_CORAD3 0xFFFFF37C
 
#define V850_REG_OSTS 0xFFFFF380
#define V850_REG_WDCS 0xFFFFF382
#define V850_REG_WDTM 0xFFFFF384
#define V850_REG_DMAS 0xFFFFF38E
 
#define V850_REG_RTBL 0xFFFFF3A0
#define V850_REG_RTBH 0xFFFFF3A2
#define V850_REG_RTPM 0xFFFFF3A4
#define V850_REG_RTPC 0xFFFFF3A6
 
#define V850_REG_ADM1 0xFFFFF3C0
#define V850_REG_ADS 0xFFFFF3C2
#define V850_REG_ADCR 0xFFFFF3C4
#define V850_REG_ADCRH 0xFFFFF3C6
#define V850_REG_ADM2 0xFFFFF3C8
 
#define V850_REG_KRM 0xFFFFF3D0
 
#define V850_REG_NCC 0xFFFFF3D4
 
#else // elif CYGINT_HAL_V850_VARIANT_SB1
# error No v850 variant defined
#endif
 
 
/*---------------------------------------------------------------------------*/
/* end of v850_common.h */
#endif /* CYGONCE_V850_COMMON_H */
/include/var_cache.h
0,0 → 1,80
#ifndef CYGONCE_VAR_CACHE_H
#define CYGONCE_VAR_CACHE_H
 
//=============================================================================
//
// var_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg,jlarmour
// Date: 2001-03-21
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/var_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <cyg/hal/plf_cache.h>
 
// No caches defined in this variant by default
#ifndef HAL_ICACHE_ENABLE
# define HAL_ICACHE_ENABLE()
# define HAL_ICACHE_DISABLE()
# define HAL_ICACHE_SYNC()
# define HAL_ICACHE_INVALIDATE_ALL()
#endif
 
#ifndef HAL_DCACHE_ENABLE
# define HAL_DCACHE_ENABLE()
# define HAL_DCACHE_DISABLE()
# define HAL_DCACHE_SYNC()
# define HAL_DCACHE_INVALIDATE_ALL()
#endif
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_VAR_CACHE_H
// End of var_cache.h
/include/var_intr.h
0,0 → 1,272
#ifndef CYGONCE_HAL_VAR_INTR_H
#define CYGONCE_HAL_VAR_INTR_H
 
//==========================================================================
//
// var_intr.h
//
// NEC V850 Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jskov, gthomas, jlarmour
// Date: 2001-03-21
// Purpose: NEC V850 Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock for variants of the NEC V85x
// architecture.
//
// Usage:
// #include <cyg/hal/var_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/plf_intr.h>
 
//--------------------------------------------------------------------------
// NEC V850/SA1 (70301x) and V850/SB1 (70303x) vectors.
 
// These are the exception codes presented in the Cause register and
// correspond to VSRs. These values are the ones to use for HAL_VSR_GET/SET
 
#define CYGNUM_HAL_VECTOR_RESET 0x00
#define CYGNUM_HAL_VECTOR_NMI 0x01
#define CYGNUM_HAL_VECTOR_INTWDT 0x02 // watchdog timer NMI
#define CYGNUM_HAL_VECTOR_TRAP00 0x04
#define CYGNUM_HAL_VECTOR_TRAP10 0x05
#define CYGNUM_HAL_VECTOR_ILGOP 0x06 // illegal opcode
#define CYGNUM_HAL_VECTOR_INTWDTM 0x08 // watchdog timer maskable
#define CYGNUM_HAL_VECTOR_INTP0 0x09
#define CYGNUM_HAL_VECTOR_INTP1 0x0A
#define CYGNUM_HAL_VECTOR_INTP2 0x0B
#define CYGNUM_HAL_VECTOR_INTP3 0x0C
#define CYGNUM_HAL_VECTOR_INTP4 0x0D
#define CYGNUM_HAL_VECTOR_INTP5 0x0E
#define CYGNUM_HAL_VECTOR_INTP6 0x0F
 
#if CYGINT_HAL_V850_VARIANT_SA1
#define CYGNUM_HAL_VECTOR_INTWTNI 0x10
#define CYGNUM_HAL_VECTOR_INTTM00 0x11
#define CYGNUM_HAL_VECTOR_INTTM01 0x12
#define CYGNUM_HAL_VECTOR_INTTM10 0x13
#define CYGNUM_HAL_VECTOR_INTTM11 0x14
#define CYGNUM_HAL_VECTOR_INTTM2 0x15
#define CYGNUM_HAL_VECTOR_INTTM3 0x16
#define CYGNUM_HAL_VECTOR_INTTM4 0x17
#define CYGNUM_HAL_VECTOR_INTTM5 0x18
#define CYGNUM_HAL_VECTOR_INTIIC0 0x19
#define CYGNUM_HAL_VECTOR_INTCSI0 0x19
#define CYGNUM_HAL_VECTOR_INTSER0 0x1A
#define CYGNUM_HAL_VECTOR_INTSR0 0x1B
#define CYGNUM_HAL_VECTOR_INTCSI1 0x1B
#define CYGNUM_HAL_VECTOR_INTST0 0x1C
#define CYGNUM_HAL_VECTOR_INTCSI2 0x1D
#define CYGNUM_HAL_VECTOR_INTSER1 0x1E
#define CYGNUM_HAL_VECTOR_INTSR1 0x1F
#define CYGNUM_HAL_VECTOR_INTST1 0x20
#define CYGNUM_HAL_VECTOR_INTAD 0x21
#define CYGNUM_HAL_VECTOR_INTDMA0 0x22
#define CYGNUM_HAL_VECTOR_INTDMA1 0x23
#define CYGNUM_HAL_VECTOR_INTDMA2 0x24
#define CYGNUM_HAL_VECTOR_INTWTN 0x25
 
#define CYGNUM_HAL_VSR_MIN 0
#define CYGNUM_HAL_VSR_MAX 0x25
#define CYGNUM_HAL_VSR_COUNT 0x26
 
#elif CYGINT_HAL_V850_VARIANT_SB1
 
#define CYGNUM_HAL_VECTOR_INTWTNI 0x14
#define CYGNUM_HAL_VECTOR_INTTM00 0x15
#define CYGNUM_HAL_VECTOR_INTTM01 0x16
#define CYGNUM_HAL_VECTOR_INTTM10 0x17
#define CYGNUM_HAL_VECTOR_INTTM11 0x18
#define CYGNUM_HAL_VECTOR_INTTM2 0x19
#define CYGNUM_HAL_VECTOR_INTTM3 0x1A
#define CYGNUM_HAL_VECTOR_INTTM4 0x1B
#define CYGNUM_HAL_VECTOR_INTTM5 0x1C
#define CYGNUM_HAL_VECTOR_INTTM6 0x1D
#define CYGNUM_HAL_VECTOR_INTTM7 0x1E
#define CYGNUM_HAL_VECTOR_INTIIC0 0x1F
#define CYGNUM_HAL_VECTOR_INTCSI0 0x1F
#define CYGNUM_HAL_VECTOR_INTSER0 0x20
#define CYGNUM_HAL_VECTOR_INTSR0 0x21
#define CYGNUM_HAL_VECTOR_INTCSI1 0x21
#define CYGNUM_HAL_VECTOR_INTST0 0x22
#define CYGNUM_HAL_VECTOR_INTCSI2 0x23
#define CYGNUM_HAL_VECTOR_INTIIC1 0x24
#define CYGNUM_HAL_VECTOR_INTSER1 0x25
#define CYGNUM_HAL_VECTOR_INTSR1 0x26
#define CYGNUM_HAL_VECTOR_INTCSI3 0x26
#define CYGNUM_HAL_VECTOR_INTST1 0x27
#define CYGNUM_HAL_VECTOR_INTCSI4 0x28
#ifdef __SB2
#define CYGNUM_HAL_VECTOR_INTIE1 0x29
#define CYGNUM_HAL_VECTOR_INTIE2 0x2A
#endif
#define CYGNUM_HAL_VECTOR_INTAD 0x2B
#define CYGNUM_HAL_VECTOR_INTDMA0 0x2C
#define CYGNUM_HAL_VECTOR_INTDMA1 0x2D
#define CYGNUM_HAL_VECTOR_INTDMA2 0x2E
#define CYGNUM_HAL_VECTOR_INTDMA3 0x2F
#define CYGNUM_HAL_VECTOR_INTDMA4 0x30
#define CYGNUM_HAL_VECTOR_INTDMA5 0x31
#define CYGNUM_HAL_VECTOR_INTWTN 0x32
#define CYGNUM_HAL_VECTOR_INTKR 0x33
 
 
#define CYGNUM_HAL_VSR_MIN 0
#define CYGNUM_HAL_VSR_MAX 0x33
#define CYGNUM_HAL_VSR_COUNT ((CYGNUM_HAL_VSR_MAX-CYGNUM_HAL_VSR_MIN)+1)
 
#else
# error No v850 variant implemented!
#endif
 
// Min/Max exception numbers and how many there are
#define CYGNUM_HAL_EXCEPTION_MIN 0
#define CYGNUM_HAL_EXCEPTION_MAX 7
#define CYGNUM_HAL_EXCEPTION_COUNT ((CYGNUM_HAL_EXCEPTION_MAX-CYGNUM_HAL_EXCEPTION_MIN)+1)
 
// Min/Max ISR numbers and how many there are
#define CYGNUM_HAL_ISR_MIN 0x08
#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_VSR_MAX
#define CYGNUM_HAL_ISR_COUNT ((CYGNUM_HAL_ISR_MAX-CYGNUM_HAL_ISR_MIN)+1)
 
// The vector used by the Real time clock.
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_VECTOR_INTTM10
 
// Mapping from interrupt numbers to hardware registers
#if CYGINT_HAL_V850_VARIANT_SA1
#define CYG_HAL_V85X_INTERRUPT_CONTROL_REGISTERS \
(volatile unsigned char *)V850_REG_WDTIC, \
(volatile unsigned char *)V850_REG_PIC0, \
(volatile unsigned char *)V850_REG_PIC1, \
(volatile unsigned char *)V850_REG_PIC2, \
(volatile unsigned char *)V850_REG_PIC3, \
(volatile unsigned char *)V850_REG_PIC4, \
(volatile unsigned char *)V850_REG_PIC5, \
(volatile unsigned char *)V850_REG_PIC6, \
(volatile unsigned char *)V850_REG_WTNIIC, \
(volatile unsigned char *)V850_REG_TMIC00, \
(volatile unsigned char *)V850_REG_TMIC01, \
(volatile unsigned char *)V850_REG_TMIC10, \
(volatile unsigned char *)V850_REG_TMIC11, \
(volatile unsigned char *)V850_REG_TMIC2, \
(volatile unsigned char *)V850_REG_TMIC3, \
(volatile unsigned char *)V850_REG_TMIC4, \
(volatile unsigned char *)V850_REG_TMIC5, \
(volatile unsigned char *)V850_REG_CSIC0, \
(volatile unsigned char *)V850_REG_SERIC0, \
(volatile unsigned char *)V850_REG_CSIC1, \
(volatile unsigned char *)V850_REG_STIC0, \
(volatile unsigned char *)V850_REG_CSIC2, \
(volatile unsigned char *)V850_REG_SERIC1, \
(volatile unsigned char *)V850_REG_SRIC1, \
(volatile unsigned char *)V850_REG_STIC1, \
(volatile unsigned char *)V850_REG_ADIC, \
(volatile unsigned char *)V850_REG_DMAIC0, \
(volatile unsigned char *)V850_REG_DMAIC1, \
(volatile unsigned char *)V850_REG_DMAIC2, \
(volatile unsigned char *)V850_REG_WTNIC
 
#elif CYGINT_HAL_V850_VARIANT_SB1
#define CYG_HAL_V85X_INTERRUPT_CONTROL_REGISTERS \
(volatile unsigned char *)V850_REG_WDTIC, \
(volatile unsigned char *)V850_REG_PIC0, \
(volatile unsigned char *)V850_REG_PIC1, \
(volatile unsigned char *)V850_REG_PIC2, \
(volatile unsigned char *)V850_REG_PIC3, \
(volatile unsigned char *)V850_REG_PIC4, \
(volatile unsigned char *)V850_REG_PIC5, \
(volatile unsigned char *)V850_REG_PIC6, \
NULL, \
NULL, \
NULL, \
NULL, \
(volatile unsigned char *)V850_REG_WTNIIC, \
(volatile unsigned char *)V850_REG_TMIC00, \
(volatile unsigned char *)V850_REG_TMIC01, \
(volatile unsigned char *)V850_REG_TMIC10, \
(volatile unsigned char *)V850_REG_TMIC11, \
(volatile unsigned char *)V850_REG_TMIC2, \
(volatile unsigned char *)V850_REG_TMIC3, \
(volatile unsigned char *)V850_REG_TMIC4, \
(volatile unsigned char *)V850_REG_TMIC5, \
(volatile unsigned char *)V850_REG_TMIC6, \
(volatile unsigned char *)V850_REG_TMIC7, \
(volatile unsigned char *)V850_REG_CSIC0, \
(volatile unsigned char *)V850_REG_SERIC0, \
(volatile unsigned char *)V850_REG_CSIC1, \
(volatile unsigned char *)V850_REG_STIC0, \
(volatile unsigned char *)V850_REG_CSIC2, \
(volatile unsigned char *)V850_REG_IICIC1, \
(volatile unsigned char *)V850_REG_SERIC1, \
(volatile unsigned char *)V850_REG_CSIC3, \
(volatile unsigned char *)V850_REG_STIC1, \
(volatile unsigned char *)V850_REG_CSIC4, \
(volatile unsigned char *)V850_REG_IEBIC1, \
(volatile unsigned char *)V850_REG_IEBIC2, \
(volatile unsigned char *)V850_REG_ADIC, \
(volatile unsigned char *)V850_REG_DMAIC0, \
(volatile unsigned char *)V850_REG_DMAIC1, \
(volatile unsigned char *)V850_REG_DMAIC2, \
(volatile unsigned char *)V850_REG_DMAIC3, \
(volatile unsigned char *)V850_REG_DMAIC4, \
(volatile unsigned char *)V850_REG_DMAIC5, \
(volatile unsigned char *)V850_REG_WTNIC, \
(volatile unsigned char *)V850_REG_KRIC
 
#endif // elif CYGINT_HAL_V850_VARIANT_SB1
 
//--------------------------------------------------------------------------
// Clock control
 
// This is handled by the default code
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VAR_INTR_H
// End of var_intr.h
/include/var_arch.h
0,0 → 1,93
#ifndef CYGONCE_HAL_VAR_ARCH_H
#define CYGONCE_HAL_VAR_ARCH_H
 
//==========================================================================
//
// var_arch.h
//
// Architecture specific abstractions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, gthomas
// Date: 1999-02-17
// Purpose: Define architecture abstractions
// Description: This file contains any extra or modified definitions for
// this variant of the architecture.
// Usage: #include <cyg/hal/var_arch.h>
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <cyg/infra/cyg_type.h>
 
#define CYG_HAL_GDB_REG CYG_WORD32
 
// Copy a set of registers from a HAL_SavedRegisters structure into a
// GDB ordered array.
#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \
{ \
CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \
int _i_; \
\
for( _i_ = 0; _i_ < 32; _i_++ ) \
_regval_[_i_] = (_regs_)->d[_i_]; \
\
_regval_[37] = (_regs_)->psw; \
_regval_[36] = (_regs_)->cause; \
_regval_[64] = (_regs_)->pc; \
}
 
// Copy a GDB ordered array into a HAL_SavedRegisters structure.
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
{ \
CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \
int _i_; \
\
for( _i_ = 0; _i_ < 32; _i_++ ) \
(_regs_)->d[_i_] = _regval_[_i_]; \
\
(_regs_)->psw = _regval_[37]; \
(_regs_)->cause = _regval_[36]; \
(_regs_)->pc = _regval_[64]; \
}
 
//--------------------------------------------------------------------------
#endif // CYGONCE_HAL_VAR_ARCH_H
// End of var_arch.h
/ChangeLog
0,0 → 1,175
2003-04-10 Nick Garnett <nickg@balti.calivar.com>
 
* src/v85x_v850.ld:
Added .eh_frame to data section. This is a stopgap fix to allow
C++ programs that define exceptions to link and run. It does not
allow them to actually throw exceptions, since that depends on
compiler changes that have not been made. Further, more
far-reaching, linker script changes will also be needs when that
happens.
Added libsupc++.a to GROUP() directive for GCC versions later than
3.0.
 
2002-05-23 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_v85x_v850.cdl: Don't run cache tests.
 
2001-06-21 Jonathan Larmour <jlarmour@redhat.com>
 
* include/v850_common.h: Add register defns for other V850/SA1 models.
 
2001-04-24 Jonathan Larmour <jlarmour@redhat.com>
 
* cdl/hal_v85x_v850.cdl: Separate v850_ice.cxx into separate file
and only build if CYGDBG_HAL_V850_ICE. Also only build for ROM
or ROMRAM startup.
* src/hal_diag.c: msec_timeout can be static
* src/v850_stub.c: Separate ICE support into new v850_ice.cxx file from
here
* src/v850_ice.cxx: New file
* src/v85x_v850.ld: Enter at reset_vector for ROM or ROMRAM startup.
This is better when loading via ICE.
 
2001-03-29 Jonathan Larmour <jlarmour@redhat.com>
 
* cdl/hal_v85x_v850.cdl: Fix typo.
 
2001-03-28 Jonathan Larmour <jlarmour@redhat.com>
 
* src/hal_diag.c: Move here from platform HALs - on-board serial0
is generic for V850 platforms.
 
* cdl/hal_v85x_v850.cdl: Build hal_diag.c
Add interfaces indicating variant.
Add option for ICE debugging.
 
* include/v850_common.h: Move register definitions here from
platform HAL and define both SA1 and SB1 variants.
Also rename some to match official docs.
 
* include/var_arch.h: No need to include <pkgconf/hal.h>
 
* include/var_cache.h: Provide empty default cache macros here.
 
* include/var_intr.h: Move interrupt definitions here from
platform HAL and define for both SA1 and SB1 variants.
Also rename some to match official docs.
 
* src/v850_misc.c: Doesn't use tracing, so don't include header.
 
* src/v850_stub.c: Reflect CYGNUM_HAL_VECTOR_WATCHDOG_TIMER ->
CYGNUM_HAL_VECTOR_INTWDT renaming.
Add support for debugging via ICE and gdbserv.
 
* src/v85x_v850.ld: Start at "start" not "reset_vector".
Support ram_vectors section (separated out to support ROMRAM startup).
 
* src/nec.ld: Remove - redundant.
 
* tests/nmitest.c: Added. Standalone test for checking if we've
received an NMI.
 
2000-09-06 Gary Thomas <gthomas@redhat.com>
 
* cdl/hal_v85x_v850.cdl: Improve [CPU] variant support.
 
2000-07-24 Jonathan Larmour <jlarmour@redhat.co.uk>
 
* src/v850_stub.c (__is_breakpoint_function): Removed use
of CYG_LABEL_NAME() and added underscore to _breakinst.
 
* src/nec.ld, src/v85x_v850.ld:
Switched to new table definition mechanism.
 
2000-06-12 Gary Thomas <gthomas@redhat.com>
 
* src/v850_misc.c (hal_interrupt_unmask): Remove [extra]
debug message.
 
2000-06-09 Gary Thomas <gthomas@redhat.com>
 
* src/v850_misc.c: Make interrupt handling routines safe.
Also add asserts to verify.
 
2000-05-25 Gary Thomas <gthomas@redhat.com>
 
* src/v85x_v850.ld: Add platform specifics. In particular the
special, hardwired symbol "hal_vsr_table" needs to be platform
specific.
 
2000-05-24 Gary Thomas <gthomas@redhat.com>
 
* include/v850_common.h: Split into platform specific files.
 
2000-04-25 Gary Thomas <gthomas@redhat.com>
 
* src/v85x_v850.ld: Fix linking problem with "_etext".
 
2000-04-14 Gary Thomas <gthomas@redhat.com>
 
* src/v850_stub.c: Use 'br *' with a watchdog to emulate a
breakpoint since the hardware does not support them directly.
 
2000-04-11 Gary Thomas <gthomas@redhat.com>
 
* src/v850_stub.c (next_pc): Instruction "jmp [Rn]" was being
decoded incorrectly, leading to erroneous single step behaviour.
 
2000-03-31 Gary Thomas <gthomas@redhat.com>
 
* src/context.S: Use SLD/SST for smaller, faster code in context
save/restore functions.
 
2000-03-30 Gary Thomas <gthomas@redhat.com>
 
* src/context.S (_hal_longjmp):
(_hal_setjmp): Need to save R1/R2/R4/R5 since GCC seems to use them.
 
2000-03-27 Gary Thomas <gthomas@redhat.com>
 
* include/var_intr.h: Remove extra junk left over from cut&paste.
 
* src/context.S: Add setjmp/longjmp support.
 
2000-03-21 Gary Thomas <gthomas@redhat.com>
 
* src/v850_stub.c (__skipinst): Use single step code properly.
 
2000-03-20 Gary Thomas <gthomas@redhat.com>
 
* src/v850_stub.c: Add single step support.
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/src/v850_stub.c
0,0 → 1,326
//========================================================================
//
// v850_stub.c
//
// Helper functions for stub, generic to all NEC processors
//
//========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Red Hat, gthomas, jlarmour
// Contributors: Red Hat, gthomas, jskov
// Date: 1998-11-26
// Purpose:
// Description: Helper functions for stub, generic to all NEC processors
// Usage:
//
//####DESCRIPTIONEND####
//
//========================================================================
 
#include <stddef.h>
 
#include <pkgconf/hal.h>
#ifdef CYGPKG_CYGMON
#include <pkgconf/cygmon.h>
#endif
 
#ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
#include <cyg/hal/dbg-threads-api.h>
#endif
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/hal/hal_stub.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_intr.h>
 
#ifndef FALSE
#define FALSE 0
#define TRUE 1
#endif
 
/* Given a trap value TRAP, return the corresponding signal. */
 
int __computeSignal (unsigned int trap_number)
{
unsigned short curins, *pc;
switch (trap_number) {
case CYGNUM_HAL_VECTOR_INTWDT: // watchdog timer NMI
pc = (unsigned short *)_hal_registers->pc;
curins = *pc;
if (curins == 0x0585) {
// "br *" - used for breakpoint
return SIGTRAP;
} else {
// Anything else - just ignore it happened
return 0;
}
case CYGNUM_HAL_VECTOR_NMI:
return SIGINT;
default:
return SIGTRAP;
}
}
 
 
/* Return the trap number corresponding to the last-taken trap. */
int __get_trap_number (void)
{
// The vector is not not part of the GDB register set so get it
// directly from the save context.
return _hal_registers->vector;
}
 
/* Set the currently-saved pc register value to PC. */
 
void set_pc (target_register_t pc)
{
put_register (PC, pc);
}
 
 
/*----------------------------------------------------------------------
* Single-step support
*/
 
/* Set things up so that the next user resume will execute one instruction.
This may be done by setting breakpoints or setting a single step flag
in the saved user registers, for example. */
 
static unsigned short *ss_saved_pc = 0;
static unsigned short ss_saved_instr[2];
static int ss_saved_instr_size;
 
#define FIXME() {diag_printf("FIXME - %s\n", __FUNCTION__); }
 
static unsigned short *
next_pc(unsigned short *pc)
{
unsigned short curins = *pc;
unsigned short *newpc = pc;
 
switch ((curins & 0x0780) >> 7) {
case 0x0:
if ((curins & 0x60) == 0x60) {
int Rn = curins & 0x1F;
newpc = (unsigned short *)get_register(Rn);
} else {
newpc = pc+1;
}
break;
case 0x1:
case 0x2:
case 0x3:
case 0x4:
case 0x5:
// Arithmetic - no branch opcodes
newpc = pc+1;
break;
case 0x6:
case 0x7:
case 0x8:
case 0x9:
case 0xA:
// Load and store - no branch opcodes
newpc = pc+2;
break;
case 0xB:
// Conditional branch
if (1) {
unsigned long psw = get_register(PSW);
#define PSW_SAT 0x10
#define PSW_CY 0x08
#define PSW_OV 0x04
#define PSW_S 0x02
#define PSW_Z 0x01
long disp = ((curins & 0xF800) >> 8) | ((curins & 0x70) >> 4);
int cc = curins & 0x0F;
int S = (psw & PSW_S) != 0;
int Z = (psw & PSW_Z) != 0;
int OV = (psw & PSW_OV) != 0;
int CY = (psw & PSW_CY) != 0;
int do_branch = 0;
if (curins & 0x8000) disp |= 0xFFFFFF00;
switch (cc) {
case 0x0: // BV
do_branch = (OV == 1);
break;
case 0x1: // BL
do_branch = (CY == 1);
break;
case 0x2: // BE
do_branch = (Z == 1);
break;
case 0x3: // BNH
do_branch = ((CY | Z) == 1);
break;
case 0x4: // BN
do_branch = (S == 1);
break;
case 0x5: // - always
do_branch = 1;
break;
case 0x6: // BLT
do_branch = ((S ^ OV) == 1);
break;
case 0x7: // BLE
do_branch = (((S ^ OV) | Z) == 1);
break;
case 0x8: // BNV
do_branch = (OV == 0);
break;
case 0x9: // BNL
do_branch = (CY == 0);
break;
case 0xA: // BNE
do_branch = (Z == 0);
break;
case 0xB: // BH
do_branch = ((CY | Z) == 0);
break;
case 0xC: // BP
do_branch = (S == 0);
break;
case 0xD: // BSA
do_branch = ((psw & PSW_SAT) != 0);
break;
case 0xE: // BGE
do_branch = ((S ^ OV) == 0);
break;
case 0xF: // BGT
do_branch = (((S ^ OV) | Z) == 0);
break;
}
if (do_branch) {
newpc = pc + disp;
} else {
newpc = pc + 1;
}
}
break;
case 0xC:
case 0xD:
case 0xE:
// Arithmetic & load/store - no branch opcodes
newpc = pc+2;
break;
case 0xF:
if ((curins & 0x60) >= 0x40) {
// Bitfield and extended instructions - no branch opcodes
newpc = pc+2;
} else {
// JR/JARL
long disp = ((curins & 0x3F) << 16) | *(pc+1);
if (curins & 0x20) disp |= 0xFFC00000;
newpc = pc + (disp>>1);
}
}
return newpc;
}
 
void __single_step (void)
{
unsigned short *pc = (unsigned short *)get_register(PC);
unsigned short *break_pc;
unsigned short _breakpoint[] = {0x07E0, 0x0780};
unsigned short *breakpoint = _breakpoint;
// If the current instruction is a branch, decide if the branch will
// be taken to determine where to set the breakpoint.
break_pc = next_pc(pc);
// Now see what kind of breakpoint can be used.
// Note: since this is a single step, always use the 32 bit version.
ss_saved_pc = break_pc;
ss_saved_instr_size = 2;
ss_saved_instr[0] = *break_pc;
*break_pc++ = *breakpoint++;
ss_saved_instr[1] = *break_pc;
*break_pc++ = *breakpoint++;
}
 
/* Clear the single-step state. */
 
void __clear_single_step (void)
{
unsigned short *pc, *val;
int i;
if (ss_saved_instr_size != 0) {
pc = ss_saved_pc;
val = ss_saved_instr;
for (i = 0; i < ss_saved_instr_size; i++) {
*pc++ = *val++;
}
ss_saved_instr_size = 0;
}
}
 
#if !defined(CYGPKG_CYGMON)
void __install_breakpoints (void)
{
// FIXME();
}
 
void __clear_breakpoints (void)
{
// FIXME();
}
#endif // !CYGPKG_CYGMON
 
/* If the breakpoint we hit is in the breakpoint() instruction, return a
non-zero value. */
 
int
__is_breakpoint_function ()
{
return get_register (PC) == (target_register_t)&_breakinst;
}
 
 
/* Skip the current instruction. Since this is only called by the
stub when the PC points to a breakpoint or trap instruction,
*/
 
void __skipinst (void)
{
unsigned short *pc = (unsigned short *)get_register(PC);
pc = next_pc(pc);
put_register(PC, (unsigned long)pc);
}
 
 
#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
// EOF v850_stub.c
/src/v850_ice.cxx
0,0 → 1,573
//========================================================================
//
// v850_ice.cxx
//
// ICE debugging support for V850 processors
//
//========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jlarmour
// Contributors:
// Date: 2001-03-12
// Purpose:
// Description: ICE debugging support for V850 processors
// Usage:
//
//####DESCRIPTIONEND####
//
//========================================================================
 
#include <pkgconf/hal.h>
 
#ifdef CYGDBG_HAL_V850_ICE
 
#include <stddef.h>
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/dbg-threads-api.h>
#include <cyg/hal/nec-stub.h>
#include <cyg/hal/hal_arch.h>
 
#define ICEDEBUG 0
 
#if ICEDEBUG
#include <cyg/infra/diag.h>
#endif
 
/* ----------------------------------------------------------------------- */
/* Common ICE syscall information */
 
/* Magic area for syscall information, from vectors.S */
__externC char hal_v85x_ice_syscall_info[];
 
/* Syscall operation codes. This is a "contract" with the host. */
 
#define V850ICE_SYSCALL_GET_THREADNEXT 1
#define V850ICE_SYSCALL_GET_THREADREGS 2
#define V850ICE_SYSCALL_SET_THREADREGS 3
#define V850ICE_SYSCALL_GET_CURRTHREAD 4
#define V850ICE_SYSCALL_GET_THREADINFO 5
#define V850ICE_SYSCALL_CONSOLE_INPUT 6
 
/* System call information area layout */
#define ICE_SYSCALL_INFO_VALIDATOR (*(int *)&hal_v85x_ice_syscall_info[0])
#define ICE_SYSCALL_INFO_STARTPC (*(int *)&hal_v85x_ice_syscall_info[4])
#define ICE_SYSCALL_INFO_ENDPC (*(int *)&hal_v85x_ice_syscall_info[8])
#define ICE_SYSCALL_INFO_STACK (*(int *)&hal_v85x_ice_syscall_info[12])
#define ICE_SYSCALL_INFO_IOBUF (*(int *)&hal_v85x_ice_syscall_info[16])
#define ICE_SYSCALL_INFO_DIAGOUTPC (*(int *)&hal_v85x_ice_syscall_info[20])
#define ICE_SYSCALL_INFO_DIAGOUTBUF (*(int *)&hal_v85x_ice_syscall_info[24])
#define ICE_SYSCALL_INFO_DIAGOUTBUFEND (*(int *)&hal_v85x_ice_syscall_info[28])
 
/* We can't use normal memcpy when invoked via the ICE. It may be unsafe. */
static void
my_memcpy( void *vd, const void *vs, int n)
{
char *d = (char *)vd;
char *s = (char *)vs;
 
while (n--)
*d++=*s++;
}
 
static void
my_memset( void *vs, char c, int n)
{
char *s = (char *)vs;
 
while (n--)
*s++ = c;
}
 
/* ----------------------------------------------------------------------- */
/* Support for diag output via ICE */
 
#ifdef CYGDBG_HAL_V85X_V850_ICE_DIAG
 
#include <cyg/hal/hal_if.h>
 
static volatile cyg_uint8 v850ice_output_buf[128];
static volatile cyg_uint8 *v850ice_output_end = v850ice_output_buf;
#define OUTPUT_BUF_END (&v850ice_output_buf[ sizeof(v850ice_output_buf)])
static volatile cyg_uint8 v850ice_input_buf[128];
#define INPUT_BUF_END (&v850ice_input_buf[ sizeof(v850ice_input_buf)])
static volatile cyg_uint8 *v850ice_input_ptr_put = v850ice_input_buf;
static volatile cyg_uint8 *v850ice_input_ptr_get = v850ice_input_buf;
static volatile cyg_uint8 v850ice_input_buf_bytes_used = 0;
 
__externC void hal_v850_ice_output_break(void);
 
static void
hal_v850_ice_indicate_output(void)
{
HAL_BREAKPOINT(hal_v850_ice_output_break);
}
 
// Actually write character
void
cyg_hal_plf_diag_ice_putc(void* __ch_data, cyg_uint8 c)
{
CYGARC_HAL_SAVE_GP();
 
// Send character
*v850ice_output_end++ = c;
 
if (c == '\n' ||
v850ice_output_end == OUTPUT_BUF_END) {
hal_v850_ice_indicate_output();
v850ice_output_end = v850ice_output_buf;
}
 
CYGARC_HAL_RESTORE_GP();
}
 
static cyg_bool
cyg_hal_plf_diag_ice_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
if ( v850ice_input_buf_bytes_used == 0 )
return false; // buffer empty
 
*ch = *v850ice_input_ptr_get++;
if ( v850ice_input_ptr_get == INPUT_BUF_END ) {
v850ice_input_ptr_get = v850ice_input_buf;
}
 
v850ice_input_buf_bytes_used--;
 
return true;
}
 
cyg_uint8
cyg_hal_plf_diag_ice_getc(void* __ch_data)
{
cyg_uint8 ch;
CYGARC_HAL_SAVE_GP();
 
while(!cyg_hal_plf_diag_ice_getc_nonblock(__ch_data, &ch));
 
CYGARC_HAL_RESTORE_GP();
return ch;
}
 
static cyg_bool
cyg_hal_plf_diag_ice_receive_char(cyg_uint8 ch)
{
/* buffer full? */
if ( v850ice_input_buf_bytes_used == sizeof(v850ice_input_buf) )
return false;
 
*v850ice_input_ptr_put++ = ch;
if ( v850ice_input_ptr_put == INPUT_BUF_END ) {
v850ice_input_ptr_put = v850ice_input_buf;
}
return true;
}
 
static void
cyg_hal_plf_diag_ice_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
#define MIN(__x, __y) ((__x) < (__y) ? (__x) : (__y))
 
while(__len > 0) {
int copylen = MIN(__len,
(cyg_uint32) (OUTPUT_BUF_END - v850ice_output_end));
 
my_memcpy( (void *)v850ice_output_buf, __buf, copylen );
__len -= copylen;
v850ice_output_end += copylen;
hal_v850_ice_indicate_output();
v850ice_output_end = v850ice_output_buf;
}
CYGARC_HAL_RESTORE_GP();
}
 
static void
cyg_hal_plf_diag_ice_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
*__buf++ = cyg_hal_plf_diag_ice_getc(__ch_data);
 
CYGARC_HAL_RESTORE_GP();
}
 
static cyg_int32 msec_timeout = 1000;
 
cyg_bool
cyg_hal_plf_diag_ice_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
int delay_count = msec_timeout * 10; // delay in .1 ms steps
cyg_bool res;
CYGARC_HAL_SAVE_GP();
 
for(;;) {
res = cyg_hal_plf_diag_ice_getc_nonblock(__ch_data, ch);
if (res || 0 == delay_count--)
break;
CYGACC_CALL_IF_DELAY_US(100);
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static int
cyg_hal_plf_diag_ice_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
int ret = 0;
CYGARC_HAL_SAVE_GP();
 
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = 0;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
 
va_start(ap, __func);
 
ret = msec_timeout;
msec_timeout = va_arg(ap, cyg_uint32);
 
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
 
static int
cyg_hal_plf_diag_ice_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
CYGARC_HAL_SAVE_GP();
*__ctrlc = 0;
CYGARC_HAL_RESTORE_GP();
return 0;
}
 
__externC void
cyg_hal_plf_ice_diag_init()
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 
// Init channels
ICE_SYSCALL_INFO_DIAGOUTPC = (int)&hal_v850_ice_output_break;
ICE_SYSCALL_INFO_DIAGOUTBUF = (int)&v850ice_output_buf[0];
ICE_SYSCALL_INFO_DIAGOUTBUFEND = (int)&v850ice_output_end;
 
// Setup procs in the vector table
 
// Set channel 1
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, 0);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_diag_ice_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_diag_ice_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_diag_ice_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_diag_ice_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_diag_ice_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_diag_ice_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_diag_ice_getc_timeout);
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
 
#endif // ifdef CYGDBG_HAL_V85X_V850_ICE_DIAG
 
 
/* ----------------------------------------------------------------------- */
/* Support for debugging via ICE */
 
#define ICE_STACK_SIZE 1024/sizeof(int)
static int ice_stack[ICE_STACK_SIZE]; // ints so as to ensure alignment
static int ice_iobuf[128];
 
static void
hal_v85x_ice_syscall_end(void)
{
for (;;);
}
 
static void
hal_v85x_ice_syscall(void)
{
int code, len;
code = ice_iobuf[0];
len = ice_iobuf[1];
switch (code) {
case V850ICE_SYSCALL_GET_THREADNEXT:
{
int ret;
threadref currthread, nextthread;
int thread_id;
 
/* Unmarshall thread ref */
my_memcpy( &currthread, &ice_iobuf[2], 8 );
#if ICEDEBUG
diag_printf("*NEXTTHREAD* currthread=%08x,%08x\n",
*(int *)&currthread[0],
*(int *)(((char *)&currthread[0])+4));
#endif
// null threadref?
if ((ice_iobuf[2] == 0) &&
(ice_iobuf[3] == 0)) {
#if ICEDEBUG
diag_printf("null threadref\n");
#endif
ret = dbg_threadlist( 1, NULL, &nextthread );
} else {
#if ICEDEBUG
diag_printf("non-null threadref\n");
#endif
ret = dbg_threadlist( 0, &currthread, &nextthread );
}
#if ICEDEBUG
diag_printf("*NEXTTHREAD* nextthread=%08x,%08x\n",
*(int *)&nextthread[0],
*(int *)(((char *)&nextthread[0])+4));
#endif
if (ret) { // if valid thread found
thread_id = dbg_thread_id( &nextthread );
/* Returns 0 on error */
if (thread_id != 0) {
ice_iobuf[1] = thread_id;
my_memcpy( &ice_iobuf[2], nextthread, 8 );
// set return data size to 12
ice_iobuf[0] = 12;
#if ICEDEBUG
{
int i;
for (i=0; i<3; i++)
diag_printf("%x, ", ice_iobuf[i]);
diag_printf("\n");
}
#endif
} else {
ret = 0;
}
}
if (!ret) {
// set to null
my_memset( &ice_iobuf[1], 0, 12 );
}
}
break;
case V850ICE_SYSCALL_GET_THREADREGS:
{
int ret;
threadref thread;
 
/* Unmarshall thread ref */
my_memcpy( &thread, &ice_iobuf[2], 8 );
#if ICEDEBUG
diag_printf("*GTHREADREGS* thread=%08x,%08x\n", *(int *)&thread[0],
*(int *)(((char *)&thread[0])+4));
#endif
ret = dbg_getthreadreg( &thread, NUMREGS, &ice_iobuf[1]);
if (ret)
ice_iobuf[0] = NUMREGS * 4;
else
ice_iobuf[0] = 0;
}
break;
case V850ICE_SYSCALL_SET_THREADREGS:
{
int ret;
threadref thread;
 
/* Unmarshall thread ref */
my_memcpy( &thread, &ice_iobuf[2], 8 );
#if ICEDEBUG
diag_printf("*STHREADREGS* thread=%08x,%08x\n", *(int *)&thread[0],
*(int *)(((char *)&thread[0])+4));
#endif
ret = dbg_setthreadreg( &thread, NUMREGS, &ice_iobuf[4]);
if (ret)
ice_iobuf[0] = 1;
else
ice_iobuf[0] = 0;
}
break;
case V850ICE_SYSCALL_GET_CURRTHREAD:
{
int ret, thread_id;
threadref thread;
 
ret = dbg_currthread( &thread );
#if ICEDEBUG
diag_printf("*CURRTHREAD* thread=%08x,%08x\n", *(int *)&thread[0],
*(int *)(((char *)&thread[0])+4));
#endif
if (ret) {
thread_id = dbg_thread_id( &thread );
/* Returns 0 on error */
if (thread_id != 0) {
ice_iobuf[1] = thread_id;
my_memcpy( &ice_iobuf[2], thread, 8 );
}
else {
ret = 0;
}
}
if (ret)
ice_iobuf[0] = 12;
else
ice_iobuf[0] = 0;
}
break;
case V850ICE_SYSCALL_GET_THREADINFO:
{
int ret;
threadref thread;
struct cygmon_thread_debug_info info;
char *s=(char *)&ice_iobuf[1], *p;
 
/* Unmarshall thread ref */
my_memcpy( &thread, &ice_iobuf[2], 8 );
#if ICEDEBUG
diag_printf("*INFO* thread=%08x,%08x\n", *(int *)&thread[0],
*(int *)(((char *)&thread[0])+4));
#endif
 
ret = dbg_threadinfo( &thread, &info );
if (ret) {
if (info.thread_display) {
my_memcpy (s, "State: ", 7);
s += 7;
p = info.thread_display;
while (*p) {
*s++ = *p++;
}
}
 
if (info.unique_thread_name && info.unique_thread_name[0]) {
my_memcpy (s, ", Name: ", 8);
s += 8;
p = info.unique_thread_name;
while (*p) {
*s++ = *p++;
}
}
 
if (info.more_display) {
my_memcpy (s, ", ", 2);
s += 2;
p = info.more_display;
while (*p) {
*s++ = *p++;
}
}
 
}
*s++ = '\0';
if (ret)
ice_iobuf[0] = s - (char *)&ice_iobuf[1];
else
ice_iobuf[0] = 0;
}
break;
case V850ICE_SYSCALL_CONSOLE_INPUT:
{
#ifdef CYGDBG_HAL_V85X_V850_ICE_DIAG
int len = ice_iobuf[0];
int i;
 
for (i=1; i <= len; i++) {
if (false == cyg_hal_plf_diag_ice_receive_char(ice_iobuf[i]))
break;
}
ice_iobuf[0] = i-1;
#else
ice_iobuf[0] = 0;
#endif
}
break;
default:
// set return data size to 0
ice_iobuf[0] = 0;
break;
}
hal_v85x_ice_syscall_end();
}
 
class Cyg_dummy_ice_syscall_init_class {
public:
Cyg_dummy_ice_syscall_init_class() {
 
const int valid_string = 0x45434956; // "VICE"
 
ICE_SYSCALL_INFO_STARTPC = (int)&hal_v85x_ice_syscall;
ICE_SYSCALL_INFO_ENDPC = (int)&hal_v85x_ice_syscall_end;
// top of stack, less 4 ints for parameter flushback area as per ABI
ICE_SYSCALL_INFO_STACK = (int)&ice_stack[ICE_STACK_SIZE-4];
ICE_SYSCALL_INFO_IOBUF = (int)&ice_iobuf[0];
 
HAL_REORDER_BARRIER();
 
// Leave validation string to last
ICE_SYSCALL_INFO_VALIDATOR = valid_string;
}
};
 
static Cyg_dummy_ice_syscall_init_class dummy_syscall_class;
 
#endif // ifdef CYGDBG_HAL_V850_ICE
 
// EOF v850_ice.cxx
/src/context.S
0,0 → 1,214
// #=============================================================================
// #
// # context.S
// #
// # NEC/V850 context switch code
// #
// #=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
// #=============================================================================
// ######DESCRIPTIONBEGIN####
// #
// # Author(s): nickg, gthomas
// # Contributors: nickg, gthomas
// # Date: 1998-09-15
// # Purpose: NEC/V850 context switch code
// # Description: This file contains implementations of the thread context
// # switch routines. It also contains the longjmp() and setjmp() routines.
// #
// #####DESCRIPTIONEND####
// #
// #=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/nec_offsets.inc>
 
.text
// ------------------------------------------------------------------------------
// hal_thread_switch_context
// Switch thread contexts
// R6 = address of sp of next thread to execute
// R7 = address of sp save location of current thread
.globl __hal_thread_switch_context
__hal_thread_switch_context:
addi -CYGARC_EXCEPTION_FRAME_SIZE,sp,sp
st.w ep,CYGARC_REG_EP[sp]
mov sp,ep
sst.w r1,CYGARC_REG_R1[ep]
sst.w r2,CYGARC_REG_R2[ep]
addi CYGARC_EXCEPTION_FRAME_SIZE,ep,r1
sst.w r1,CYGARC_REG_SP[ep] // sp
sst.w r4,CYGARC_REG_R4[ep]
sst.w r5,CYGARC_REG_R5[ep]
sst.w r6,CYGARC_REG_R6[ep]
sst.w r7,CYGARC_REG_R7[ep]
sst.w r8,CYGARC_REG_R8[ep]
sst.w r9,CYGARC_REG_R9[ep]
sst.w r10,CYGARC_REG_R10[ep]
sst.w r11,CYGARC_REG_R11[ep]
sst.w r12,CYGARC_REG_R12[ep]
sst.w r13,CYGARC_REG_R13[ep]
sst.w r14,CYGARC_REG_R14[ep]
sst.w r15,CYGARC_REG_R15[ep]
sst.w r16,CYGARC_REG_R16[ep]
sst.w r17,CYGARC_REG_R17[ep]
sst.w r18,CYGARC_REG_R18[ep]
sst.w r19,CYGARC_REG_R19[ep]
sst.w r20,CYGARC_REG_R20[ep]
sst.w r21,CYGARC_REG_R21[ep]
sst.w r22,CYGARC_REG_R22[ep]
sst.w r23,CYGARC_REG_R23[ep]
sst.w r24,CYGARC_REG_R24[ep]
sst.w r25,CYGARC_REG_R25[ep]
sst.w r26,CYGARC_REG_R26[ep]
sst.w r27,CYGARC_REG_R27[ep]
sst.w r28,CYGARC_REG_R28[ep]
sst.w r29,CYGARC_REG_R29[ep]
sst.w lp,CYGARC_REG_LP[ep]
sst.w lp,CYGARC_REG_PC[ep]
stsr PSW,r1
st.w r1,CYGARC_REG_PSW[ep]
st.w sp,0[r7] // return new stack pointer
 
# Now load the destination thread by dropping through
# to hal_thread_load_context
// ------------------------------------------------------------------------------
// hal_thread_load_context
// Load thread context
// R6 = address of sp of next thread to execute
// Note that this function is also the second half of hal_thread_switch_context
// and is simply dropped into from it.
 
.globl __hal_thread_load_context
__hal_thread_load_context:
di // disable interrupts while updating state
ld.w 0[r6],ep // get pointer to saved state
ld.w CYGARC_REG_PSW[ep],r6
sld.w CYGARC_REG_LP[ep],r7
sld.w CYGARC_REG_R1[ep],r1 // restore volatile registers
sld.w CYGARC_REG_R2[ep],r2
ldsr r6,EIPSW // avoids pipline bubble
ldsr r7,EIPC
sld.w CYGARC_REG_R4[ep],r4
sld.w CYGARC_REG_R5[ep],r5
sld.w CYGARC_REG_R6[ep],r6
sld.w CYGARC_REG_R7[ep],r7
sld.w CYGARC_REG_R8[ep],r8
sld.w CYGARC_REG_R9[ep],r9
sld.w CYGARC_REG_R10[ep],r10
sld.w CYGARC_REG_R11[ep],r11
sld.w CYGARC_REG_R12[ep],r12
sld.w CYGARC_REG_R13[ep],r13
sld.w CYGARC_REG_R14[ep],r14
sld.w CYGARC_REG_R15[ep],r15
sld.w CYGARC_REG_R16[ep],r16
sld.w CYGARC_REG_R17[ep],r17
sld.w CYGARC_REG_R18[ep],r18
sld.w CYGARC_REG_R19[ep],r19
sld.w CYGARC_REG_R20[ep],r20
sld.w CYGARC_REG_R21[ep],r21
sld.w CYGARC_REG_R22[ep],r22
sld.w CYGARC_REG_R23[ep],r23
sld.w CYGARC_REG_R24[ep],r24
sld.w CYGARC_REG_R25[ep],r25
sld.w CYGARC_REG_R26[ep],r26
sld.w CYGARC_REG_R27[ep],r27
sld.w CYGARC_REG_R28[ep],r28
sld.w CYGARC_REG_R29[ep],r29
sld.w CYGARC_REG_LP[ep],lp
sld.w CYGARC_REG_SP[ep],sp
sld.w CYGARC_REG_EP[ep],ep
reti
// ------------------------------------------------------------------------------
// HAL longjmp, setjmp implementations
 
#define fp r29
 
.globl _hal_setjmp
_hal_setjmp:
st.w r1,CYGARC_JMPBUF_R1[r6]
st.w r2,CYGARC_JMPBUF_R2[r6]
st.w r4,CYGARC_JMPBUF_R4[r6]
st.w r5,CYGARC_JMPBUF_R5[r6]
st.w sp,CYGARC_JMPBUF_SP[r6]
st.w gp,CYGARC_JMPBUF_GP[r6]
st.w tp,CYGARC_JMPBUF_TP[r6]
st.w r20,CYGARC_JMPBUF_R20[r6]
st.w r21,CYGARC_JMPBUF_R21[r6]
st.w r22,CYGARC_JMPBUF_R22[r6]
st.w r23,CYGARC_JMPBUF_R23[r6]
st.w r24,CYGARC_JMPBUF_R24[r6]
st.w r25,CYGARC_JMPBUF_R25[r6]
st.w r26,CYGARC_JMPBUF_R26[r6]
st.w r27,CYGARC_JMPBUF_R27[r6]
st.w r28,CYGARC_JMPBUF_R28[r6]
st.w fp,CYGARC_JMPBUF_FP[r6]
st.w ep,CYGARC_JMPBUF_EP[r6]
st.w lp,CYGARC_JMPBUF_LP[r6]
mov r0,r10
jmp [lp]
 
// hal_longjmp loads state from [arg0] and returns arg1
 
.globl _hal_longjmp
_hal_longjmp:
ld.w CYGARC_JMPBUF_SP[r6],sp
ld.w CYGARC_JMPBUF_GP[r6],gp
ld.w CYGARC_JMPBUF_TP[r6],tp
ld.w CYGARC_JMPBUF_R1[r6],r1
ld.w CYGARC_JMPBUF_R2[r6],r2
ld.w CYGARC_JMPBUF_R4[r6],r4
ld.w CYGARC_JMPBUF_R5[r6],r5
ld.w CYGARC_JMPBUF_R20[r6],r20
ld.w CYGARC_JMPBUF_R21[r6],r21
ld.w CYGARC_JMPBUF_R22[r6],r22
ld.w CYGARC_JMPBUF_R23[r6],r23
ld.w CYGARC_JMPBUF_R24[r6],r24
ld.w CYGARC_JMPBUF_R25[r6],r25
ld.w CYGARC_JMPBUF_R26[r6],r26
ld.w CYGARC_JMPBUF_R27[r6],r27
ld.w CYGARC_JMPBUF_R28[r6],r28
ld.w CYGARC_JMPBUF_FP[r6],fp
ld.w CYGARC_JMPBUF_EP[r6],ep
ld.w CYGARC_JMPBUF_LP[r6],lp
mov r7,r10
jmp [lp]
 
// ------------------------------------------------------------------------------
// end of context.S
 
/src/hal_diag.c
0,0 → 1,452
/*=============================================================================
//
// hal_diag.c
//
// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas
// Contributors:nickg, gthomas, jlarmour
// Date: 2001-03-21
// Purpose: HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
 
#if CYGINT_HAL_V850_DIAG_ONCHIP_SERIAL0
 
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H
 
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_arch.h> // basic machine info
#include <cyg/hal/hal_intr.h> // interrupt macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_diag.h>
 
#include <cyg/hal/hal_stub.h> // target_register_t
#include <cyg/hal/hal_if.h> // Calling interface definitions
#include <cyg/hal/hal_misc.h> // Helper functions
#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
 
#include <cyg/hal/v850_common.h> // hardware registers, etc.
 
 
#define BAUD_COUNT ((CYGHWR_HAL_V85X_CPU_FREQ/2)/CYGHWR_HAL_V85X_V850_DIAG_BAUD)
#define BAUD_DIVISOR 1
 
/*---------------------------------------------------------------------------*/
// V850
 
void
init_serial_channel(void* base)
{
volatile unsigned char *mode = (volatile unsigned char *)V850_REG_ASIM0;
volatile unsigned char *brgc = (volatile unsigned char *)V850_REG_BRGC0;
volatile unsigned char *brgm0 = (volatile unsigned char *)V850_REG_BRGMC00;
#ifdef V850_REG_BRGMC01
volatile unsigned char *brgm1 = (volatile unsigned char *)V850_REG_BRGMC01;
#endif
volatile unsigned char *rxstat = (volatile unsigned char *)V850_REG_SRIC0;
volatile unsigned char *rxerr = (volatile unsigned char *)V850_REG_SERIC0;
volatile unsigned char *txstat = (volatile unsigned char *)V850_REG_STIC0;
int count = BAUD_COUNT;
int divisor = BAUD_DIVISOR;
 
while (count > 0xFF) {
count >>= 1;
divisor++;
}
 
*mode = 0xC8;
*brgc = count;
*brgm0 = divisor & 0x07;
#ifdef V850_REG_BRGMC01
*brgm1 = divisor >> 3;
#endif
*rxstat = 0x47;
*rxerr = 0;
*txstat = 0x47;
}
 
// Actually send character down the wire
void
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 c)
{
volatile unsigned char *TxDATA = (volatile unsigned char *)V850_REG_TXS0;
volatile unsigned char *TxSTAT = (volatile unsigned char *)V850_REG_STIC0;
int timeout = 0xFFFF;
 
CYGARC_HAL_SAVE_GP();
 
// Send character
*TxDATA = (unsigned char)c;
// Wait for Tx not busy
while ((*TxSTAT & 0x80) == 0x00) {
if (--timeout == 0)
break;
}
*TxSTAT &= ~0x80;
 
CYGARC_HAL_RESTORE_GP();
}
 
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
volatile unsigned char *RxDATA = (volatile unsigned char *)V850_REG_RXB0;
volatile unsigned char *RxSTAT = (volatile unsigned char *)V850_REG_SRIC0;
 
if ((*RxSTAT & 0x80) == 0x00)
return false;
 
*ch = (char)*RxDATA;
*RxSTAT &= ~0x80;
return true;
}
 
cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
cyg_uint8 ch;
CYGARC_HAL_SAVE_GP();
 
while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
 
CYGARC_HAL_RESTORE_GP();
return ch;
}
 
static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
cyg_hal_plf_serial_putc(__ch_data, *__buf++);
 
CYGARC_HAL_RESTORE_GP();
}
 
static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
 
CYGARC_HAL_RESTORE_GP();
}
 
static cyg_int32 msec_timeout = 1000;
 
cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
int delay_count = msec_timeout * 10; // delay in .1 ms steps
cyg_bool res;
CYGARC_HAL_SAVE_GP();
 
for(;;) {
res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
if (res || 0 == delay_count--)
break;
CYGACC_CALL_IF_DELAY_US(100);
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
int ret = 0;
CYGARC_HAL_SAVE_GP();
 
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_VECTOR_INTCSI1);
irq_state = 1;
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(CYGNUM_HAL_VECTOR_INTCSI1);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = CYGNUM_HAL_VECTOR_INTCSI1;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
 
va_start(ap, __func);
 
ret = msec_timeout;
msec_timeout = va_arg(ap, cyg_uint32);
 
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
 
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
volatile unsigned char *RxDATA = (volatile unsigned char *)V850_REG_RXB0;
cyg_uint8 c;
int res = 0;
CYGARC_HAL_SAVE_GP();
 
c = (char)*RxDATA;
*__ctrlc = 0;
if( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
 
cyg_drv_interrupt_acknowledge(CYGNUM_HAL_VECTOR_INTCSI1);
 
res = CYG_ISR_HANDLED;
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 
// Disable interrupts.
HAL_INTERRUPT_MASK(CYGNUM_HAL_VECTOR_INTCSI1);
 
// Init channels
init_serial_channel((cyg_uint8*)0);
 
// Setup procs in the vector table
 
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, 0);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
 
__externC void cyg_hal_plf_ice_diag_init();
 
void
cyg_hal_plf_comms_init(void)
{
static int initialized = 0;
 
if (initialized)
return;
 
initialized = 1;
 
cyg_hal_plf_serial_init();
 
#ifdef CYGDBG_HAL_V85X_V850_ICE_DIAG
cyg_hal_plf_ice_diag_init();
#endif
}
 
//=============================================================================
// Compatibility with older stubs
//=============================================================================
 
#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
// Assumption: all diagnostic output must be GDB packetized unless this is a ROM (i.e.
// totally stand-alone) system.
 
//#ifdef CYGSEM_HAL_ROM_MONITOR
//#define CYG_HAL_STARTUP_ROM
//#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
//#endif
 
#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) \
&& !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
#define HAL_DIAG_USES_HARDWARE
#else
#if !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
#define HAL_DIAG_USES_HARDWARE
#endif
#endif
 
void hal_diag_init(void)
{
init_serial_channel(0);
}
 
#ifdef HAL_DIAG_USES_HARDWARE
 
void hal_diag_write_char(char c)
{
CYG_INTERRUPT_STATE old;
HAL_DISABLE_INTERRUPTS(old);
cyg_hal_plf_serial_putc(0, c);
HAL_RESTORE_INTERRUPTS(old);
}
 
void hal_diag_read_char(char *c)
{
*c = cyg_hal_plf_serial_getc(0);
}
 
#else // HAL_DIAG relies on GDB
 
void
hal_diag_read_char(char *c)
{
*c = cyg_hal_plf_serial_getc(0);
}
 
void
hal_diag_write_char(char c)
{
static char line[100];
static int pos = 0;
 
// No need to send CRs
if( c == '\r' ) return;
 
line[pos++] = c;
 
if( c == '\n' || pos == sizeof(line) )
{
CYG_INTERRUPT_STATE old;
 
// Disable interrupts. This prevents GDB trying to interrupt us
// while we are in the middle of sending a packet. The serial
// receive interrupt will be seen when we re-enable interrupts
// later.
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
#else
HAL_DISABLE_INTERRUPTS(old);
#endif
 
while(1)
{
static char hex[] = "0123456789ABCDEF";
cyg_uint8 csum = 0;
int i;
char c1;
cyg_hal_plf_serial_putc(0, '$');
cyg_hal_plf_serial_putc(0, 'O');
csum += 'O';
for( i = 0; i < pos; i++ )
{
char ch = line[i];
char h = hex[(ch>>4)&0xF];
char l = hex[ch&0xF];
cyg_hal_plf_serial_putc(0, h);
cyg_hal_plf_serial_putc(0, l);
csum += h;
csum += l;
}
cyg_hal_plf_serial_putc(0, '#');
cyg_hal_plf_serial_putc(0, hex[(csum>>4)&0xF]);
cyg_hal_plf_serial_putc(0, hex[csum&0xF]);
 
// Wait for the ACK character '+' from GDB here and handle
// receiving a ^C instead. This is the reason for this clause
// being a loop.
c1 = cyg_hal_plf_serial_getc(0);
 
if( c1 == '+' )
break; // a good acknowledge
 
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) && \
defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
cyg_drv_interrupt_acknowledge(CYGNUM_HAL_VECTOR_INTCSI1);
if( c1 == 3 ) {
// Ctrl-C: breakpoint.
cyg_hal_gdb_interrupt (__builtin_return_address(0));
break;
}
#endif
// otherwise, loop round again
}
pos = 0;
 
// And re-enable interrupts
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
#else
HAL_RESTORE_INTERRUPTS(old);
#endif
}
}
#endif // USE HARDWARE
 
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
#endif // #if CYGINT_HAL_V850_DIAG_ONCHIP_SERIAL0
 
/*---------------------------------------------------------------------------*/
/* End of hal_diag.c */
/src/v85x_v850.ld
0,0 → 1,153
//=============================================================================
//
// MLT linker script for NEC
// adapted from packages/hal/arm/pid/v1_1/src/pid.ld
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
 
#include <pkgconf/system.h>
 
STARTUP(vectors.o)
// Enter at reset_vector in non-RAM startups so they are more representative
// of actual execution when loaded over ICE
#ifdef CYG_HAL_STARTUP_RAM
ENTRY(start)
#else
ENTRY(reset_vector)
#endif
#ifdef EXTRAS
INPUT(extras.o)
#endif
#if (__GNUC__ >= 3)
GROUP(libtarget.a libgcc.a libsupc++.a)
#else
GROUP(libtarget.a libgcc.a)
#endif
 
#define ALIGN_LMA 4
#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1))
#define LMA_EQ_VMA
#define FORCE_OUTPUT . = .
 
#define SECTIONS_BEGIN \
/* Debug information */ \
.debug_aranges 0 : { *(.debug_aranges) } \
.debug_pubnames 0 : { *(.debug_pubnames) } \
.debug_info 0 : { *(.debug_info) } \
.debug_abbrev 0 : { *(.debug_abbrev) } \
.debug_line 0 : { *(.debug_line) } \
.debug_frame 0 : { *(.debug_frame) } \
.debug_str 0 : { *(.debug_str) } \
.debug_loc 0 : { *(.debug_loc) } \
.debug_macinfo 0 : { *(.debug_macinfo) }
 
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
.rom_vectors _vma_ : _lma_ \
{ FORCE_OUTPUT; KEEP (*(.vectors)) } \
> _region_
 
#define SECTION_ram_vectors(_region_, _vma_, _lma_) \
.ram_vectors _vma_ : _lma_ \
{ ___ram_vectors_start = ABSOLUTE(.); \
FORCE_OUTPUT; KEEP (*(.ram_vectors)) \
___ram_vectors_end = ABSOLUTE(.); \
} > _region_ \
___ram_vectors_loadaddr = LOADADDR(.ram_vectors);
 
#define SECTION_text(_region_, _vma_, _lma_) \
.text _vma_ : _lma_ \
{ stext = ABSOLUTE(.); \
PROVIDE (__stext = ABSOLUTE(.)); \
*(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) \
*(.glue_7) *(.glue_7t) \
} > _region_ \
etext = .; PROVIDE (__etext = .);
 
#define SECTION_fini(_region_, _vma_, _lma_) \
.fini _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.fini) } \
> _region_
 
#define SECTION_rodata(_region_, _vma_, _lma_) \
.rodata _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.rodata*) } \
> _region_
 
#define SECTION_rodata1(_region_, _vma_, _lma_) \
.rodata1 _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.rodata1) } \
> _region_
 
#define SECTION_fixup(_region_, _vma_, _lma_) \
.fixup _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.fixup) } \
> _region_
 
#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \
.gcc_except_table _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.gcc_except_table) } \
> _region_
 
#define SECTION_data(_region_, _vma_, _lma_) \
.data _vma_ : _lma_ \
{ ___ram_data_start = ABSOLUTE (.); *(.data*) *(.data1); \
_GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \
_GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \
. = ALIGN (4); \
KEEP(*( SORT (.ecos.table.*))) ; \
___CTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.ctors*))) ___CTOR_END__ = ABSOLUTE (.); \
___DTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.dtors*))) ___DTOR_END__ = ABSOLUTE (.); \
*(.eh_frame) \
*(.dynamic) *(.sdata*) *(.sbss*) } \
> _region_ \
___rom_data_start = LOADADDR (.data); \
___ram_data_end = .; PROVIDE (___ram_data_end = .); _edata = .; PROVIDE (edata = .); \
PROVIDE (___rom_data_end = LOADADDR (.data) + SIZEOF(.data));
 
#define SECTION_bss(_region_, _vma_, _lma_) \
.bss _vma_ : _lma_ \
{ ___bss_start = ABSOLUTE (.); \
*(.scommon) *(.dynbss) *(.bss*) *(COMMON) \
___bss_end = ABSOLUTE (.); } \
> _region_
 
#include <cyg/hal/plf_sections.h>
 
#include <pkgconf/hal_v85x.h>
#include <pkgconf/hal_v85x_v850.h>
#include CYGHWR_MEMORY_LAYOUT_LDI
 
// EOF v85x_v850.ld
/src/v850_misc.c
0,0 → 1,150
//==========================================================================
//
// v850_misc.c
//
// HAL CPU variant miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas
// Date: 2000-03-15
// Purpose: HAL miscellaneous functions
// Description: This file contains miscellaneous functions provided by the
// HAL.
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // Base types
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/v850_common.h>
 
externC void cyg_hal_platform_hardware_init(void);
 
//
// Interrupt management functions
//
 
static volatile unsigned char *interrupt_control_registers[] = {
CYG_HAL_V85X_INTERRUPT_CONTROL_REGISTERS // Defined in <plf_intr.h>
};
 
#define INT_CONTROL_PENDING 0x80
#define INT_CONTROL_DISABLE 0x40
#define INT_CONTROL_LEVEL(n) n
 
#define INT_CONTROL_DEFAULT INT_CONTROL_DISABLE|INT_CONTROL_LEVEL(7)
 
//
// Mask, i.e. disable, interrupt #vector from occurring
//
void
hal_interrupt_mask(int vector)
{
volatile unsigned char *ctl;
CYG_ASSERT(vector >= CYGNUM_HAL_ISR_MIN, "invalid interrupt vector [< MIN]");
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX, "invalid interrupt vector [> MAX]");
ctl = interrupt_control_registers[vector-CYGNUM_HAL_ISR_MIN];
CYG_ASSERT((void *)ctl != 0, "invalid interrupt vector [not defined]");
if (ctl ) {
*ctl |= INT_CONTROL_DISABLE;
}
}
 
//
// Unmask, i.e. enable, interrupt #vector
//
void
hal_interrupt_unmask(int vector)
{
volatile unsigned char *ctl;
CYG_ASSERT(vector >= CYGNUM_HAL_ISR_MIN, "invalid interrupt vector [< MIN]");
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX, "invalid interrupt vector [> MAX]");
ctl = interrupt_control_registers[vector-CYGNUM_HAL_ISR_MIN];
CYG_ASSERT((void *)ctl != 0, "invalid interrupt vector [not defined]");
if (ctl ) {
*ctl &= ~INT_CONTROL_DISABLE;
}
}
 
//
// Acknowledge, i.e. clear, interrupt #vector
//
void
hal_interrupt_acknowledge(int vector)
{
volatile unsigned char *ctl;
CYG_ASSERT(vector >= CYGNUM_HAL_ISR_MIN, "invalid interrupt vector [< MIN]");
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX, "invalid interrupt vector [> MAX]");
ctl = interrupt_control_registers[vector-CYGNUM_HAL_ISR_MIN];
CYG_ASSERT((void *)ctl != 0, "invalid interrupt vector [not defined]");
if (ctl ) {
*ctl &= ~INT_CONTROL_PENDING;
}
}
 
static void
init_interrupts(void)
{
int i;
volatile unsigned char *ctl;
for (i = CYGNUM_HAL_ISR_MIN; i <= CYGNUM_HAL_ISR_MAX; i++) {
ctl = interrupt_control_registers[i-CYGNUM_HAL_ISR_MIN];
if (ctl) {
*ctl = INT_CONTROL_DEFAULT;
}
}
}
 
//
// Initialize the hardware. This may involve platform specific code.
//
void
cyg_hal_hardware_init(void)
{
init_interrupts();
cyg_hal_platform_hardware_init();
}
 
/*------------------------------------------------------------------------*/
/* End of v850_misc.c */

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