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/or1k/trunk/insight/sim/mn10300
```
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/mn10300.igen

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mn10300.igen Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: op_utils.c =================================================================== --- op_utils.c (nonexistent) +++ op_utils.c (revision 1765) @@ -0,0 +1,227 @@ +#include "sim-main.h" +#include "targ-vals.h" + +#ifdef HAVE_UTIME_H +#include +#endif + +#ifdef HAVE_TIME_H +#include +#endif + +#ifdef HAVE_UNISTD_H +#include +#endif + +#ifdef HAVE_STRING_H +#include +#else +#ifdef HAVE_STRINGS_H +#include +#endif +#endif +#include +#include +#include + + + +#define REG0(X) ((X) & 0x3) +#define REG1(X) (((X) & 0xc) >> 2) +#define REG0_4(X) (((X) & 0x30) >> 4) +#define REG0_8(X) (((X) & 0x300) >> 8) +#define REG1_8(X) (((X) & 0xc00) >> 10) +#define REG0_16(X) (((X) & 0x30000) >> 16) +#define REG1_16(X) (((X) & 0xc0000) >> 18) + + +INLINE_SIM_MAIN (void) +genericAdd(unsigned32 source, unsigned32 destReg) +{ + int z, c, n, v; + unsigned32 dest, sum; + + dest = State.regs[destReg]; + sum = source + dest; + State.regs[destReg] = sum; + + z = (sum == 0); + n = (sum & 0x80000000); + c = (sum < source) || (sum < dest); + v = ((dest & 0x80000000) == (source & 0x80000000) + && (dest & 0x80000000) != (sum & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + + + + +INLINE_SIM_MAIN (void) +genericSub(unsigned32 source, unsigned32 destReg) +{ + int z, c, n, v; + unsigned32 dest, difference; + + dest = State.regs[destReg]; + difference = dest - source; + State.regs[destReg] = difference; + + z = (difference == 0); + n = (difference & 0x80000000); + c = (source > dest); + v = ((dest & 0x80000000) != (source & 0x80000000) + && (dest & 0x80000000) != (difference & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +INLINE_SIM_MAIN (void) +genericCmp(unsigned32 leftOpnd, unsigned32 rightOpnd) +{ + int z, c, n, v; + unsigned32 value; + + value = rightOpnd - leftOpnd; + + z = (value == 0); + n = (value & 0x80000000); + c = (leftOpnd > rightOpnd); + v = ((rightOpnd & 0x80000000) != (leftOpnd & 0x80000000) + && (rightOpnd & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + + +INLINE_SIM_MAIN (void) +genericOr(unsigned32 source, unsigned32 destReg) +{ + int n, z; + + State.regs[destReg] |= source; + z = (State.regs[destReg] == 0); + n = (State.regs[destReg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + + +INLINE_SIM_MAIN (void) +genericXor(unsigned32 source, unsigned32 destReg) +{ + int n, z; + + State.regs[destReg] ^= source; + z = (State.regs[destReg] == 0); + n = (State.regs[destReg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + + +INLINE_SIM_MAIN (void) +genericBtst(unsigned32 leftOpnd, unsigned32 rightOpnd) +{ + unsigned32 temp; + int z, n; + + temp = rightOpnd; + temp &= leftOpnd; + n = (temp & 0x80000000) != 0; + z = (temp == 0); + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); +} + +/* Read/write functions for system call interface. */ +INLINE_SIM_MAIN (int) +syscall_read_mem (host_callback *cb, struct cb_syscall *sc, + unsigned long taddr, char *buf, int bytes) +{ + SIM_DESC sd = (SIM_DESC) sc->p1; + sim_cpu *cpu = STATE_CPU(sd, 0); + + return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); +} + +INLINE_SIM_MAIN (int) +syscall_write_mem (host_callback *cb, struct cb_syscall *sc, + unsigned long taddr, const char *buf, int bytes) +{ + SIM_DESC sd = (SIM_DESC) sc->p1; + sim_cpu *cpu = STATE_CPU(sd, 0); + + return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); +} + + +/* syscall */ +INLINE_SIM_MAIN (void) +do_syscall () +{ + + /* We use this for simulated system calls; we may need to change + it to a reserved instruction if we conflict with uses at + Matsushita. */ + int save_errno = errno; + errno = 0; + +/* Registers passed to trap 0 */ + +/* Function number. */ +#define FUNC (State.regs[0]) + +/* Parameters. */ +#define PARM1 (State.regs[1]) +#define PARM2 (load_word (State.regs[REG_SP] + 12)) +#define PARM3 (load_word (State.regs[REG_SP] + 16)) + +/* Registers set by trap 0 */ + +#define RETVAL State.regs[0] /* return value */ +#define RETERR State.regs[1] /* return error code */ + +/* Turn a pointer in a register into a pointer into real memory. */ +#define MEMPTR(x) (State.mem + x) + + if ( FUNC == TARGET_SYS_exit ) + { + /* EXIT - caller can look in PARM1 to work out the reason */ + if (PARM1 == 0xdead) + State.exception = SIGABRT; + else + { + sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, + sim_exited, PARM1); + State.exception = SIGQUIT; + } + State.exited = 1; + } + else + { + CB_SYSCALL syscall; + + CB_SYSCALL_INIT (&syscall); + syscall.arg1 = PARM1; + syscall.arg2 = PARM2; + syscall.arg3 = PARM3; + syscall.func = FUNC; + syscall.p1 = (PTR) simulator; + syscall.read_mem = syscall_read_mem; + syscall.write_mem = syscall_write_mem; + cb_syscall (STATE_CALLBACK (simulator), &syscall); + RETERR = syscall.errcode; + RETVAL = syscall.result; + } + + + errno = save_errno; +} +

op_utils.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: configure =================================================================== --- configure (nonexistent) +++ configure (revision 1765) @@ -0,0 +1,4542 @@ +#! /bin/sh + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +sim_inline="-DDEFAULT_INLINE=0" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +# This file is derived from `gettext.m4'. The difference is that the +# included macros assume Cygnus-style source and build trees. + +# Macro to add for using GNU gettext. +# Ulrich Drepper , 1995. +# +# This file file be copied and used freely without restrictions. It can +# be used in projects which are not available under the GNU Public License +# but which still want to provide support for the GNU gettext functionality. +# Please note that the actual code is *not* freely available. + +# serial 3 + + + + + +# Search path for a program which passes the given test. +# Ulrich Drepper , 1996. +# +# This file file be copied and used freely without restrictions. It can +# be used in projects which are not available under the GNU Public License +# but which still want to provide support for the GNU gettext functionality. +# Please note that the actual code is *not* freely available. + +# serial 1 + + + +# Check whether LC_MESSAGES is available in . +# Ulrich Drepper , 1995. +# +# This file file be copied and used freely without restrictions. It can +# be used in projects which are not available under the GNU Public License +# but which still want to provide support for the GNU gettext functionality. +# Please note that the actual code is *not* freely available. + +# serial 1 + + + + + + +# Guess values for system-dependent variables and create Makefiles. +# Generated automatically using autoconf version 2.13 +# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. + +# Defaults: +ac_help= +ac_default_prefix=/usr/local +# Any additions from configure.in: +ac_help="$ac_help + --disable-nls do not use Native Language Support" +ac_help="$ac_help + --with-included-gettext use the GNU gettext library included here" +ac_help="$ac_help + --enable-maintainer-mode Enable developer functionality." +ac_help="$ac_help + --enable-sim-bswap Use Host specific BSWAP instruction." +ac_help="$ac_help + --enable-sim-cflags=opts Extra CFLAGS for use in building simulator" +ac_help="$ac_help + --enable-sim-debug=opts Enable debugging flags" +ac_help="$ac_help + --enable-sim-stdio Specify whether to use stdio for console input/output." +ac_help="$ac_help + --enable-sim-trace=opts Enable tracing flags" +ac_help="$ac_help + --enable-sim-profile=opts Enable profiling flags" +ac_help="$ac_help + --enable-sim-endian=endian Specify target byte endian orientation." +ac_help="$ac_help + --enable-sim-alignment=align Specify strict, nonstrict or forced alignment of memory accesses." +ac_help="$ac_help + --enable-sim-hostendian=end Specify host byte endian orientation." +ac_help="$ac_help + --enable-build-warnings[=LIST] Enable build-time compiler warnings" +ac_help="$ac_help + --enable-sim-reserved-bits Specify whether to check reserved bits in instruction." +ac_help="$ac_help + --enable-sim-bitsize=N Specify target bitsize (32 or 64)." +ac_help="$ac_help + --enable-sim-inline=inlines Specify which functions should be inlined." +ac_help="$ac_help + --enable-sim-hardware=LIST Specify the hardware to be included in the build." +ac_help="$ac_help + --enable-sim-common Enable common simulator" + +# Initialize some variables set by options. +# The variables have the same names as the options, with +# dashes changed to underlines. +build=NONE +cache_file=./config.cache +exec_prefix=NONE +host=NONE +no_create= +nonopt=NONE +no_recursion= +prefix=NONE +program_prefix=NONE +program_suffix=NONE +program_transform_name=s,x,x, +silent= +site= +sitefile= +srcdir= +target=NONE +verbose= +x_includes=NONE +x_libraries=NONE +bindir='${exec_prefix}/bin' +sbindir='${exec_prefix}/sbin' +libexecdir='${exec_prefix}/libexec' +datadir='${prefix}/share' +sysconfdir='${prefix}/etc' +sharedstatedir='${prefix}/com' +localstatedir='${prefix}/var' +libdir='${exec_prefix}/lib' +includedir='${prefix}/include' +oldincludedir='/usr/include' +infodir='${prefix}/info' +mandir='${prefix}/man' + +# Initialize some other variables. +subdirs= +MFLAGS= MAKEFLAGS= +SHELL=${CONFIG_SHELL-/bin/sh} +# Maximum number of lines to put in a shell here document. +ac_max_here_lines=12 + +ac_prev= +for ac_option +do + + # If the previous option needs an argument, assign it. + if test -n "$ac_prev"; then + eval "$ac_prev=\$ac_option" + ac_prev= + continue + fi + + case "$ac_option" in + -*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;; + *) ac_optarg= ;; + esac + + # Accept the important Cygnus configure options, so we can diagnose typos. + + case "$ac_option" in + + -bindir | --bindir | --bindi | --bind | --bin | --bi) + ac_prev=bindir ;; + -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*) + bindir="$ac_optarg" ;; + + -build | --build | --buil | --bui | --bu) + ac_prev=build ;; + -build=* | --build=* | --buil=* | --bui=* | --bu=*) + build="$ac_optarg" ;; + + -cache-file | --cache-file | --cache-fil | --cache-fi \ + | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c) + ac_prev=cache_file ;; + -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \ + | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*) + cache_file="$ac_optarg" ;; + + -datadir | --datadir | --datadi | --datad | --data | --dat | --da) + ac_prev=datadir ;; + -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \ + | --da=*) + datadir="$ac_optarg" ;; + + -disable-* | --disable-*) + ac_feature=`echo $ac_option|sed -e 's/-*disable-//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_feature| sed 's/[-a-zA-Z0-9_]//g'`"; then + { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; } + fi + ac_feature=`echo $ac_feature| sed 's/-/_/g'` + eval "enable_${ac_feature}=no" ;; + + -enable-* | --enable-*) + ac_feature=`echo $ac_option|sed -e 's/-*enable-//' -e 's/=.*//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_feature| sed 's/[-_a-zA-Z0-9]//g'`"; then + { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; } + fi + ac_feature=`echo $ac_feature| sed 's/-/_/g'` + case "$ac_option" in + *=*) ;; + *) ac_optarg=yes ;; + esac + eval "enable_${ac_feature}='$ac_optarg'" ;; + + -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \ + | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \ + | --exec | --exe | --ex) + ac_prev=exec_prefix ;; + -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \ + | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \ + | --exec=* | --exe=* | --ex=*) + exec_prefix="$ac_optarg" ;; + + -gas | --gas | --ga | --g) + # Obsolete; use --with-gas. + with_gas=yes ;; + + -help | --help | --hel | --he) + # Omit some internal or obsolete options to make the list less imposing. + # This message is too long to be a string in the A/UX 3.1 sh. + cat << EOF +Usage: configure [options] [host] +Options: [defaults in brackets after descriptions] +Configuration: + --cache-file=FILE cache test results in FILE + --help print this message + --no-create do not create output files + --quiet, --silent do not print \`checking...' messages + --site-file=FILE use FILE as the site file + --version print the version of autoconf that created configure +Directory and file names: + --prefix=PREFIX install architecture-independent files in PREFIX + [$ac_default_prefix] + --exec-prefix=EPREFIX install architecture-dependent files in EPREFIX + [same as prefix] + --bindir=DIR user executables in DIR [EPREFIX/bin] + --sbindir=DIR system admin executables in DIR [EPREFIX/sbin] + --libexecdir=DIR program executables in DIR [EPREFIX/libexec] + --datadir=DIR read-only architecture-independent data in DIR + [PREFIX/share] + --sysconfdir=DIR read-only single-machine data in DIR [PREFIX/etc] + --sharedstatedir=DIR modifiable architecture-independent data in DIR + [PREFIX/com] + --localstatedir=DIR modifiable single-machine data in DIR [PREFIX/var] + --libdir=DIR object code libraries in DIR [EPREFIX/lib] + --includedir=DIR C header files in DIR [PREFIX/include] + --oldincludedir=DIR C header files for non-gcc in DIR [/usr/include] + --infodir=DIR info documentation in DIR [PREFIX/info] + --mandir=DIR man documentation in DIR [PREFIX/man] + --srcdir=DIR find the sources in DIR [configure dir or ..] + --program-prefix=PREFIX prepend PREFIX to installed program names + --program-suffix=SUFFIX append SUFFIX to installed program names + --program-transform-name=PROGRAM + run sed PROGRAM on installed program names +EOF + cat << EOF +Host type: + --build=BUILD configure for building on BUILD [BUILD=HOST] + --host=HOST configure for HOST [guessed] + --target=TARGET configure for TARGET [TARGET=HOST] +Features and packages: + --disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no) + --enable-FEATURE[=ARG] include FEATURE [ARG=yes] + --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] + --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no) + --x-includes=DIR X include files are in DIR + --x-libraries=DIR X library files are in DIR +EOF + if test -n "$ac_help"; then + echo "--enable and --with options recognized:$ac_help" + fi + exit 0 ;; + + -host | --host | --hos | --ho) + ac_prev=host ;; + -host=* | --host=* | --hos=* | --ho=*) + host="$ac_optarg" ;; + + -includedir | --includedir | --includedi | --included | --include \ + | --includ | --inclu | --incl | --inc) + ac_prev=includedir ;; + -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \ + | --includ=* | --inclu=* | --incl=* | --inc=*) + includedir="$ac_optarg" ;; + + -infodir | --infodir | --infodi | --infod | --info | --inf) + ac_prev=infodir ;; + -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*) + infodir="$ac_optarg" ;; + + -libdir | --libdir | --libdi | --libd) + ac_prev=libdir ;; + -libdir=* | --libdir=* | --libdi=* | --libd=*) + libdir="$ac_optarg" ;; + + -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \ + | --libexe | --libex | --libe) + ac_prev=libexecdir ;; + -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \ + | --libexe=* | --libex=* | --libe=*) + libexecdir="$ac_optarg" ;; + + -localstatedir | --localstatedir | --localstatedi | --localstated \ + | --localstate | --localstat | --localsta | --localst \ + | --locals | --local | --loca | --loc | --lo) + ac_prev=localstatedir ;; + -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \ + | --localstate=* | --localstat=* | --localsta=* | --localst=* \ + | --locals=* | --local=* | --loca=* | --loc=* | --lo=*) + localstatedir="$ac_optarg" ;; + + -mandir | --mandir | --mandi | --mand | --man | --ma | --m) + ac_prev=mandir ;; + -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*) + mandir="$ac_optarg" ;; + + -nfp | --nfp | --nf) + # Obsolete; use --without-fp. + with_fp=no ;; + + -no-create | --no-create | --no-creat | --no-crea | --no-cre \ + | --no-cr | --no-c) + no_create=yes ;; + + -no-recursion | --no-recursion | --no-recursio | --no-recursi \ + | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) + no_recursion=yes ;; + + -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \ + | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \ + | --oldin | --oldi | --old | --ol | --o) + ac_prev=oldincludedir ;; + -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \ + | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \ + | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*) + oldincludedir="$ac_optarg" ;; + + -prefix | --prefix | --prefi | --pref | --pre | --pr | --p) + ac_prev=prefix ;; + -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*) + prefix="$ac_optarg" ;; + + -program-prefix | --program-prefix | --program-prefi | --program-pref \ + | --program-pre | --program-pr | --program-p) + ac_prev=program_prefix ;; + -program-prefix=* | --program-prefix=* | --program-prefi=* \ + | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*) + program_prefix="$ac_optarg" ;; + + -program-suffix | --program-suffix | --program-suffi | --program-suff \ + | --program-suf | --program-su | --program-s) + ac_prev=program_suffix ;; + -program-suffix=* | --program-suffix=* | --program-suffi=* \ + | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*) + program_suffix="$ac_optarg" ;; + + -program-transform-name | --program-transform-name \ + | --program-transform-nam | --program-transform-na \ + | --program-transform-n | --program-transform- \ + | --program-transform | --program-transfor \ + | --program-transfo | --program-transf \ + | --program-trans | --program-tran \ + | --progr-tra | --program-tr | --program-t) + ac_prev=program_transform_name ;; + -program-transform-name=* | --program-transform-name=* \ + | --program-transform-nam=* | --program-transform-na=* \ + | --program-transform-n=* | --program-transform-=* \ + | --program-transform=* | --program-transfor=* \ + | --program-transfo=* | --program-transf=* \ + | --program-trans=* | --program-tran=* \ + | --progr-tra=* | --program-tr=* | --program-t=*) + program_transform_name="$ac_optarg" ;; + + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil) + silent=yes ;; + + -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb) + ac_prev=sbindir ;; + -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \ + | --sbi=* | --sb=*) + sbindir="$ac_optarg" ;; + + -sharedstatedir | --sharedstatedir | --sharedstatedi \ + | --sharedstated | --sharedstate | --sharedstat | --sharedsta \ + | --sharedst | --shareds | --shared | --share | --shar \ + | --sha | --sh) + ac_prev=sharedstatedir ;; + -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \ + | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \ + | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \ + | --sha=* | --sh=*) + sharedstatedir="$ac_optarg" ;; + + -site | --site | --sit) + ac_prev=site ;; + -site=* | --site=* | --sit=*) + site="$ac_optarg" ;; + + -site-file | --site-file | --site-fil | --site-fi | --site-f) + ac_prev=sitefile ;; + -site-file=* | --site-file=* | --site-fil=* | --site-fi=* | --site-f=*) + sitefile="$ac_optarg" ;; + + -srcdir | --srcdir | --srcdi | --srcd | --src | --sr) + ac_prev=srcdir ;; + -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*) + srcdir="$ac_optarg" ;; + + -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \ + | --syscon | --sysco | --sysc | --sys | --sy) + ac_prev=sysconfdir ;; + -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \ + | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*) + sysconfdir="$ac_optarg" ;; + + -target | --target | --targe | --targ | --tar | --ta | --t) + ac_prev=target ;; + -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*) + target="$ac_optarg" ;; + + -v | -verbose | --verbose | --verbos | --verbo | --verb) + verbose=yes ;; + + -version | --version | --versio | --versi | --vers) + echo "configure generated by autoconf version 2.13" + exit 0 ;; + + -with-* | --with-*) + ac_package=`echo $ac_option|sed -e 's/-*with-//' -e 's/=.*//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_package| sed 's/[-_a-zA-Z0-9]//g'`"; then + { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; } + fi + ac_package=`echo $ac_package| sed 's/-/_/g'` + case "$ac_option" in + *=*) ;; + *) ac_optarg=yes ;; + esac + eval "with_${ac_package}='$ac_optarg'" ;; + + -without-* | --without-*) + ac_package=`echo $ac_option|sed -e 's/-*without-//'` + # Reject names that are not valid shell variable names. + if test -n "`echo $ac_package| sed 's/[-a-zA-Z0-9_]//g'`"; then + { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; } + fi + ac_package=`echo $ac_package| sed 's/-/_/g'` + eval "with_${ac_package}=no" ;; + + --x) + # Obsolete; use --with-x. + with_x=yes ;; + + -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \ + | --x-incl | --x-inc | --x-in | --x-i) + ac_prev=x_includes ;; + -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \ + | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*) + x_includes="$ac_optarg" ;; + + -x-libraries | --x-libraries | --x-librarie | --x-librari \ + | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l) + ac_prev=x_libraries ;; + -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \ + | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*) + x_libraries="$ac_optarg" ;; + + -*) { echo "configure: error: $ac_option: invalid option; use --help to show usage" 1>&2; exit 1; } + ;; + + *) + if test -n "`echo $ac_option| sed 's/[-a-z0-9.]//g'`"; then + echo "configure: warning: $ac_option: invalid host type" 1>&2 + fi + if test "x$nonopt" != xNONE; then + { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } + fi + nonopt="$ac_option" + ;; + + esac +done + +if test -n "$ac_prev"; then + { echo "configure: error: missing argument to --`echo $ac_prev | sed 's/_/-/g'`" 1>&2; exit 1; } +fi + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +# File descriptor usage: +# 0 standard input +# 1 file creation +# 2 errors and warnings +# 3 some systems may open it to /dev/tty +# 4 used on the Kubota Titan +# 6 checking for... messages and results +# 5 compiler messages saved in config.log +if test "$silent" = yes; then + exec 6>/dev/null +else + exec 6>&1 +fi +exec 5>./config.log + +echo "\ +This file contains any messages produced by compilers while +running configure, to aid debugging if configure makes a mistake. +" 1>&5 + +# Strip out --no-create and --no-recursion so they do not pile up. +# Also quote any args containing shell metacharacters. +ac_configure_args= +for ac_arg +do + case "$ac_arg" in + -no-create | --no-create | --no-creat | --no-crea | --no-cre \ + | --no-cr | --no-c) ;; + -no-recursion | --no-recursion | --no-recursio | --no-recursi \ + | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) ;; + *" "*|*" "*|*[\[\]\~\#\$\^\&\*\{\}\\\|\;\<\>\?]*) + ac_configure_args="$ac_configure_args '$ac_arg'" ;; + *) ac_configure_args="$ac_configure_args $ac_arg" ;; + esac +done + +# NLS nuisances. +# Only set these to C if already set. These must not be set unconditionally +# because not all systems understand e.g. LANG=C (notably SCO). +# Fixing LC_MESSAGES prevents Solaris sh from translating var values in `set'! +# Non-C LC_CTYPE values break the ctype check. +if test "${LANG+set}" = set; then LANG=C; export LANG; fi +if test "${LC_ALL+set}" = set; then LC_ALL=C; export LC_ALL; fi +if test "${LC_MESSAGES+set}" = set; then LC_MESSAGES=C; export LC_MESSAGES; fi +if test "${LC_CTYPE+set}" = set; then LC_CTYPE=C; export LC_CTYPE; fi + +# confdefs.h avoids OS command line length limits that DEFS can exceed. +rm -rf conftest* confdefs.h +# AIX cpp loses on an empty file, so make sure it contains at least a newline. +echo > confdefs.h + +# A filename unique to this package, relative to the directory that +# configure is in, which we can look for to find out if srcdir is correct. +ac_unique_file=Makefile.in + +# Find the source files, if location was not specified. +if test -z "$srcdir"; then + ac_srcdir_defaulted=yes + # Try the directory containing this script, then its parent. + ac_prog=$0 + ac_confdir=`echo $ac_prog|sed 's%/[^/][^/]*$%%'` + test "x$ac_confdir" = "x$ac_prog" && ac_confdir=. + srcdir=$ac_confdir + if test ! -r $srcdir/$ac_unique_file; then + srcdir=.. + fi +else + ac_srcdir_defaulted=no +fi +if test ! -r $srcdir/$ac_unique_file; then + if test "$ac_srcdir_defaulted" = yes; then + { echo "configure: error: can not find sources in $ac_confdir or .." 1>&2; exit 1; } + else + { echo "configure: error: can not find sources in $srcdir" 1>&2; exit 1; } + fi +fi +srcdir=`echo "${srcdir}" | sed 's%$[^/]$/*$%\1%'` + +# Prefer explicitly selected file to automatically selected ones. +if test -z "$sitefile"; then + if test -z "$CONFIG_SITE"; then + if test "x$prefix" != xNONE; then + CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site" + else + CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site" + fi + fi +else + CONFIG_SITE="$sitefile" +fi +for ac_site_file in $CONFIG_SITE; do + if test -r "$ac_site_file"; then + echo "loading site script $ac_site_file" + . "$ac_site_file" + fi +done + +if test -r "$cache_file"; then + echo "loading cache $cache_file" + . $cache_file +else + echo "creating cache $cache_file" + > $cache_file +fi + +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +ac_exeext= +ac_objext=o +if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null; then + # Stardent Vistra SVR4 grep lacks -e, says ghazi@caip.rutgers.edu. + if (echo -n testing; echo 1,2,3) | sed s/-n/xn/ | grep xn >/dev/null; then + ac_n= ac_c=' +' ac_t=' ' + else + ac_n=-n ac_c= ac_t= + fi +else + ac_n= ac_c='\c' ac_t= +fi + + + +echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6 +echo "configure:697: checking how to run the C preprocessor" >&5 +# On Suns, sometimes $CPP names a directory. +if test -n "$CPP" && test -d "$CPP"; then + CPP= +fi +if test -z "$CPP"; then +if eval "test \"`echo '$''{'ac_cv_prog_CPP'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + # This must be in double quotes, not single quotes, because CPP may get + # substituted into the Makefile and "${CC-cc}" will confuse make. + CPP="${CC-cc} -E" + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. + cat > conftest.$ac_ext < +Syntax Error +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:718: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + : +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CPP="${CC-cc} -E -traditional-cpp" + cat > conftest.$ac_ext < +Syntax Error +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:735: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + : +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CPP="${CC-cc} -nologo -E" + cat > conftest.$ac_ext < +Syntax Error +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:752: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + : +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CPP=/lib/cpp +fi +rm -f conftest* +fi +rm -f conftest* +fi +rm -f conftest* + ac_cv_prog_CPP="$CPP" +fi + CPP="$ac_cv_prog_CPP" +else + ac_cv_prog_CPP="$CPP" +fi +echo "$ac_t""$CPP" 1>&6 + +echo $ac_n "checking whether ${MAKE-make} sets \${MAKE}""... $ac_c" 1>&6 +echo "configure:777: checking whether ${MAKE-make} sets \${MAKE}" >&5 +set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftestmake <<\EOF +all: + @echo 'ac_maketemp="${MAKE}"' +EOF +# GNU make sometimes prints "make[1]: Entering...", which would confuse us. +eval `${MAKE-make} -f conftestmake 2>/dev/null | grep temp=` +if test -n "$ac_maketemp"; then + eval ac_cv_prog_make_${ac_make}_set=yes +else + eval ac_cv_prog_make_${ac_make}_set=no +fi +rm -f conftestmake +fi +if eval "test \"`echo '$ac_cv_prog_make_'${ac_make}_set`\" = yes"; then + echo "$ac_t""yes" 1>&6 + SET_MAKE= +else + echo "$ac_t""no" 1>&6 + SET_MAKE="MAKE=${MAKE-make}" +fi + +echo $ac_n "checking for POSIXized ISC""... $ac_c" 1>&6 +echo "configure:804: checking for POSIXized ISC" >&5 +if test -d /etc/conf/kconfig.d && + grep _POSIX_VERSION /usr/include/sys/unistd.h >/dev/null 2>&1 +then + echo "$ac_t""yes" 1>&6 + ISC=yes # If later tests want to check for ISC. + cat >> confdefs.h <<\EOF +#define _POSIX_SOURCE 1 +EOF + + if test "$GCC" = yes; then + CC="$CC -posix" + else + CC="$CC -Xp" + fi +else + echo "$ac_t""no" 1>&6 + ISC= +fi + +echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6 +echo "configure:825: checking for ANSI C header files" >&5 +if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +#include +#include +#include +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:838: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + ac_cv_header_stdc=yes +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_header_stdc=no +fi +rm -f conftest* + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. +cat > conftest.$ac_ext < +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "memchr" >/dev/null 2>&1; then + : +else + rm -rf conftest* + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. +cat > conftest.$ac_ext < +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "free" >/dev/null 2>&1; then + : +else + rm -rf conftest* + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. +if test "$cross_compiling" = yes; then + : +else + cat > conftest.$ac_ext < +#define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +#define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int main () { int i; for (i = 0; i < 256; i++) +if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2); +exit (0); } + +EOF +if { (eval echo configure:905: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +then + : +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -fr conftest* + ac_cv_header_stdc=no +fi +rm -fr conftest* +fi + +fi +fi + +echo "$ac_t""$ac_cv_header_stdc" 1>&6 +if test $ac_cv_header_stdc = yes; then + cat >> confdefs.h <<\EOF +#define STDC_HEADERS 1 +EOF + +fi + +echo $ac_n "checking for working const""... $ac_c" 1>&6 +echo "configure:929: checking for working const" >&5 +if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <j = 5; +} +{ /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */ + const int foo = 10; +} + +; return 0; } +EOF +if { (eval echo configure:983: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_c_const=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_c_const=no +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_c_const" 1>&6 +if test $ac_cv_c_const = no; then + cat >> confdefs.h <<\EOF +#define const +EOF + +fi + +echo $ac_n "checking for inline""... $ac_c" 1>&6 +echo "configure:1004: checking for inline" >&5 +if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_cv_c_inline=no +for ac_kw in inline __inline__ __inline; do + cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_c_inline=$ac_kw; break +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 +fi +rm -f conftest* +done + +fi + +echo "$ac_t""$ac_cv_c_inline" 1>&6 +case "$ac_cv_c_inline" in + inline | yes) ;; + no) cat >> confdefs.h <<\EOF +#define inline +EOF + ;; + *) cat >> confdefs.h <&6 +echo "configure:1044: checking for off_t" >&5 +if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +#if STDC_HEADERS +#include +#include +#endif +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "(^|[^a-zA-Z_0-9])off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then + rm -rf conftest* + ac_cv_type_off_t=yes +else + rm -rf conftest* + ac_cv_type_off_t=no +fi +rm -f conftest* + +fi +echo "$ac_t""$ac_cv_type_off_t" 1>&6 +if test $ac_cv_type_off_t = no; then + cat >> confdefs.h <<\EOF +#define off_t long +EOF + +fi + +echo $ac_n "checking for size_t""... $ac_c" 1>&6 +echo "configure:1077: checking for size_t" >&5 +if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +#if STDC_HEADERS +#include +#include +#endif +EOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + egrep "(^|[^a-zA-Z_0-9])size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then + rm -rf conftest* + ac_cv_type_size_t=yes +else + rm -rf conftest* + ac_cv_type_size_t=no +fi +rm -f conftest* + +fi +echo "$ac_t""$ac_cv_type_size_t" 1>&6 +if test $ac_cv_type_size_t = no; then + cat >> confdefs.h <<\EOF +#define size_t unsigned +EOF + +fi + +# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works +# for constant arguments. Useless! +echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6 +echo "configure:1112: checking for working alloca.h" >&5 +if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +int main() { +char *p = alloca(2 * sizeof(int)); +; return 0; } +EOF +if { (eval echo configure:1124: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + ac_cv_header_alloca_h=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_header_alloca_h=no +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_header_alloca_h" 1>&6 +if test $ac_cv_header_alloca_h = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_ALLOCA_H 1 +EOF + +fi + +echo $ac_n "checking for alloca""... $ac_c" 1>&6 +echo "configure:1145: checking for alloca" >&5 +if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +# define alloca _alloca +# else +# if HAVE_ALLOCA_H +# include +# else +# ifdef _AIX + #pragma alloca +# else +# ifndef alloca /* predefined by HP cc +Olibcalls */ +char *alloca (); +# endif +# endif +# endif +# endif +#endif + +int main() { +char *p = (char *) alloca(1); +; return 0; } +EOF +if { (eval echo configure:1178: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + ac_cv_func_alloca_works=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_func_alloca_works=no +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_func_alloca_works" 1>&6 +if test $ac_cv_func_alloca_works = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_ALLOCA 1 +EOF + +fi + +if test $ac_cv_func_alloca_works = no; then + # The SVR3 libPW and SVR4 libucb both contain incompatible functions + # that cause trouble. Some versions do not even contain alloca or + # contain a buggy version. If you still want to use their alloca, + # use ar to extract alloca.o from them instead of compiling alloca.c. + ALLOCA=alloca.${ac_objext} + cat >> confdefs.h <<\EOF +#define C_ALLOCA 1 +EOF + + +echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6 +echo "configure:1210: checking whether alloca needs Cray hooks" >&5 +if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <&5 | + egrep "webecray" >/dev/null 2>&1; then + rm -rf conftest* + ac_cv_os_cray=yes +else + rm -rf conftest* + ac_cv_os_cray=no +fi +rm -f conftest* + +fi + +echo "$ac_t""$ac_cv_os_cray" 1>&6 +if test $ac_cv_os_cray = yes; then +for ac_func in _getb67 GETB67 getb67; do + echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:1240: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:1268: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + cat >> confdefs.h <&6 +fi + +done +fi + +echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6 +echo "configure:1295: checking stack direction for C alloca" >&5 +if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test "$cross_compiling" = yes; then + ac_cv_c_stack_direction=0 +else + cat > conftest.$ac_ext < addr) ? 1 : -1; +} +main () +{ + exit (find_stack_direction() < 0); +} +EOF +if { (eval echo configure:1322: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +then + ac_cv_c_stack_direction=1 +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -fr conftest* + ac_cv_c_stack_direction=-1 +fi +rm -fr conftest* +fi + +fi + +echo "$ac_t""$ac_cv_c_stack_direction" 1>&6 +cat >> confdefs.h <&6 +echo "configure:1347: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:1357: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + +for ac_func in getpagesize +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:1386: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:1414: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + +echo $ac_n "checking for working mmap""... $ac_c" 1>&6 +echo "configure:1439: checking for working mmap" >&5 +if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test "$cross_compiling" = yes; then + ac_cv_func_mmap_fixed_mapped=no +else + cat > conftest.$ac_ext < +#include +#include + +/* This mess was copied from the GNU getpagesize.h. */ +#ifndef HAVE_GETPAGESIZE +# ifdef HAVE_UNISTD_H +# include +# endif + +/* Assume that all systems that can run configure have sys/param.h. */ +# ifndef HAVE_SYS_PARAM_H +# define HAVE_SYS_PARAM_H 1 +# endif + +# ifdef _SC_PAGESIZE +# define getpagesize() sysconf(_SC_PAGESIZE) +# else /* no _SC_PAGESIZE */ +# ifdef HAVE_SYS_PARAM_H +# include +# ifdef EXEC_PAGESIZE +# define getpagesize() EXEC_PAGESIZE +# else /* no EXEC_PAGESIZE */ +# ifdef NBPG +# define getpagesize() NBPG * CLSIZE +# ifndef CLSIZE +# define CLSIZE 1 +# endif /* no CLSIZE */ +# else /* no NBPG */ +# ifdef NBPC +# define getpagesize() NBPC +# else /* no NBPC */ +# ifdef PAGESIZE +# define getpagesize() PAGESIZE +# endif /* PAGESIZE */ +# endif /* no NBPC */ +# endif /* no NBPG */ +# endif /* no EXEC_PAGESIZE */ +# else /* no HAVE_SYS_PARAM_H */ +# define getpagesize() 8192 /* punt totally */ +# endif /* no HAVE_SYS_PARAM_H */ +# endif /* no _SC_PAGESIZE */ + +#endif /* no HAVE_GETPAGESIZE */ + +#ifdef __cplusplus +extern "C" { void *malloc(unsigned); } +#else +char *malloc(); +#endif + +int +main() +{ + char *data, *data2, *data3; + int i, pagesize; + int fd; + + pagesize = getpagesize(); + + /* + * First, make a file with some known garbage in it. + */ + data = malloc(pagesize); + if (!data) + exit(1); + for (i = 0; i < pagesize; ++i) + *(data + i) = rand(); + umask(0); + fd = creat("conftestmmap", 0600); + if (fd < 0) + exit(1); + if (write(fd, data, pagesize) != pagesize) + exit(1); + close(fd); + + /* + * Next, try to mmap the file at a fixed address which + * already has something else allocated at it. If we can, + * also make sure that we see the same garbage. + */ + fd = open("conftestmmap", O_RDWR); + if (fd < 0) + exit(1); + data2 = malloc(2 * pagesize); + if (!data2) + exit(1); + data2 += (pagesize - ((int) data2 & (pagesize - 1))) & (pagesize - 1); + if (data2 != mmap(data2, pagesize, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_FIXED, fd, 0L)) + exit(1); + for (i = 0; i < pagesize; ++i) + if (*(data + i) != *(data2 + i)) + exit(1); + + /* + * Finally, make sure that changes to the mapped area + * do not percolate back to the file as seen by read(). + * (This is a bug on some variants of i386 svr4.0.) + */ + for (i = 0; i < pagesize; ++i) + *(data2 + i) = *(data2 + i) + 1; + data3 = malloc(pagesize); + if (!data3) + exit(1); + if (read(fd, data3, pagesize) != pagesize) + exit(1); + for (i = 0; i < pagesize; ++i) + if (*(data + i) != *(data3 + i)) + exit(1); + close(fd); + unlink("conftestmmap"); + exit(0); +} + +EOF +if { (eval echo configure:1587: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +then + ac_cv_func_mmap_fixed_mapped=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -fr conftest* + ac_cv_func_mmap_fixed_mapped=no +fi +rm -fr conftest* +fi + +fi + +echo "$ac_t""$ac_cv_func_mmap_fixed_mapped" 1>&6 +if test $ac_cv_func_mmap_fixed_mapped = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_MMAP 1 +EOF + +fi + +echo $ac_n "checking for Cygwin environment""... $ac_c" 1>&6 +echo "configure:1610: checking for Cygwin environment" >&5 +if eval "test \"`echo '$''{'ac_cv_cygwin'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_cygwin=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_cygwin=no +fi +rm -f conftest* +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_cygwin" 1>&6 +CYGWIN= +test "$ac_cv_cygwin" = yes && CYGWIN=yes +echo $ac_n "checking for mingw32 environment""... $ac_c" 1>&6 +echo "configure:1643: checking for mingw32 environment" >&5 +if eval "test \"`echo '$''{'ac_cv_mingw32'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_mingw32=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_mingw32=no +fi +rm -f conftest* +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_mingw32" 1>&6 +MINGW32= +test "$ac_cv_mingw32" = yes && MINGW32=yes + +# autoconf.info says this should be called right after AC_INIT. + + +ac_aux_dir= +for ac_dir in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../..; do + if test -f $ac_dir/install-sh; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install-sh -c" + break + elif test -f $ac_dir/install.sh; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install.sh -c" + break + fi +done +if test -z "$ac_aux_dir"; then + { echo "configure: error: can not find install-sh or install.sh in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../.." 1>&2; exit 1; } +fi +ac_config_guess=$ac_aux_dir/config.guess +ac_config_sub=$ac_aux_dir/config.sub +ac_configure=$ac_aux_dir/configure # This should be Cygnus configure. + + +# Do some error checking and defaulting for the host and target type. +# The inputs are: +# configure --host=HOST --target=TARGET --build=BUILD NONOPT +# +# The rules are: +# 1. You are not allowed to specify --host, --target, and nonopt at the +# same time. +# 2. Host defaults to nonopt. +# 3. If nonopt is not specified, then host defaults to the current host, +# as determined by config.guess. +# 4. Target and build default to nonopt. +# 5. If nonopt is not specified, then target and build default to host. + +# The aliases save the names the user supplied, while $host etc. +# will get canonicalized. +case $host---$target---$nonopt in +NONE---*---* | *---NONE---* | *---*---NONE) ;; +*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;; +esac + + +# Make sure we can run config.sub. +if ${CONFIG_SHELL-/bin/sh} $ac_config_sub sun4 >/dev/null 2>&1; then : +else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; } +fi + +echo $ac_n "checking host system type""... $ac_c" 1>&6 +echo "configure:1722: checking host system type" >&5 + +host_alias=$host +case "$host_alias" in +NONE) + case $nonopt in + NONE) + if host_alias=`${CONFIG_SHELL-/bin/sh} $ac_config_guess`; then : + else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; } + fi ;; + *) host_alias=$nonopt ;; + esac ;; +esac + +host=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $host_alias` +host_cpu=`echo $host | sed 's/^$[^-]*$-$[^-]*$-$.*$$/\1/'` +host_vendor=`echo $host | sed 's/^$[^-]*$-$[^-]*$-$.*$$/\2/'` +host_os=`echo $host | sed 's/^$[^-]*$-$[^-]*$-$.*$$/\3/'` +echo "$ac_t""$host" 1>&6 + +echo $ac_n "checking target system type""... $ac_c" 1>&6 +echo "configure:1743: checking target system type" >&5 + +target_alias=$target +case "$target_alias" in +NONE) + case $nonopt in + NONE) target_alias=$host_alias ;; + *) target_alias=$nonopt ;; + esac ;; +esac + +target=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $target_alias` +target_cpu=`echo $target | sed 's/^$[^-]*$-$[^-]*$-$.*$$/\1/'` +target_vendor=`echo $target | sed 's/^$[^-]*$-$[^-]*$-$.*$$/\2/'` +target_os=`echo $target | sed 's/^$[^-]*$-$[^-]*$-$.*$$/\3/'` +echo "$ac_t""$target" 1>&6 + +echo $ac_n "checking build system type""... $ac_c" 1>&6 +echo "configure:1761: checking build system type" >&5 + +build_alias=$build +case "$build_alias" in +NONE) + case $nonopt in + NONE) build_alias=$host_alias ;; + *) build_alias=$nonopt ;; + esac ;; +esac + +build=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $build_alias` +build_cpu=`echo $build | sed 's/^$[^-]*$-$[^-]*$-$.*$$/\1/'` +build_vendor=`echo $build | sed 's/^$[^-]*$-$[^-]*$-$.*$$/\2/'` +build_os=`echo $build | sed 's/^$[^-]*$-$[^-]*$-$.*$$/\3/'` +echo "$ac_t""$build" 1>&6 + +test "$host_alias" != "$target_alias" && + test "$program_prefix$program_suffix$program_transform_name" = \ + NONENONEs,x,x, && + program_prefix=${target_alias}- + +if test "$program_transform_name" = s,x,x,; then + program_transform_name= +else + # Double any \ or $. echo might interpret backslashes. + cat <<\EOF_SED > conftestsed +s,\\,\\\\,g; s,\$,$$,g +EOF_SED + program_transform_name="`echo $program_transform_name|sed -f conftestsed`" + rm -f conftestsed +fi +test "$program_prefix" != NONE && + program_transform_name="s,^,${program_prefix},; $program_transform_name" +# Use a double $ so make ignores it. +test "$program_suffix" != NONE && + program_transform_name="s,\$\$,${program_suffix},; $program_transform_name" + +# sed with no file args requires a program. +test "$program_transform_name" = "" && program_transform_name="s,x,x," + +# Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1805: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="gcc" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1835: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_prog_rejected=no + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + break + fi + done + IFS="$ac_save_ifs" +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# -gt 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + set dummy "$ac_dir/$ac_word" "$@" + shift + ac_cv_prog_CC="$@" + fi +fi +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + if test -z "$CC"; then + case "`uname -s`" in + *win32* | *WIN32*) + # Extract the first word of "cl", so it can be a program name with args. +set dummy cl; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1886: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="cl" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + ;; + esac + fi + test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; } +fi + +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 +echo "configure:1918: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 + +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +cat > conftest.$ac_ext << EOF + +#line 1929 "configure" +#include "confdefs.h" + +main(){return(0);} +EOF +if { (eval echo configure:1934: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + ac_cv_prog_cc_works=yes + # If we can't run a trivial program, we are probably using a cross compiler. + if (./conftest; exit) 2>/dev/null; then + ac_cv_prog_cc_cross=no + else + ac_cv_prog_cc_cross=yes + fi +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + ac_cv_prog_cc_works=no +fi +rm -fr conftest* +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +echo "$ac_t""$ac_cv_prog_cc_works" 1>&6 +if test $ac_cv_prog_cc_works = no; then + { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } +fi +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 +echo "configure:1960: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 +cross_compiling=$ac_cv_prog_cc_cross + +echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 +echo "configure:1965: checking whether we are using GNU C" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.c <&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then + ac_cv_prog_gcc=yes +else + ac_cv_prog_gcc=no +fi +fi + +echo "$ac_t""$ac_cv_prog_gcc" 1>&6 + +if test $ac_cv_prog_gcc = yes; then + GCC=yes +else + GCC= +fi + +ac_test_CFLAGS="${CFLAGS+set}" +ac_save_CFLAGS="$CFLAGS" +CFLAGS= +echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 +echo "configure:1993: checking whether ${CC-cc} accepts -g" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + echo 'void f(){}' > conftest.c +if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then + ac_cv_prog_cc_g=yes +else + ac_cv_prog_cc_g=no +fi +rm -f conftest* + +fi + +echo "$ac_t""$ac_cv_prog_cc_g" 1>&6 +if test "$ac_test_CFLAGS" = set; then + CFLAGS="$ac_save_CFLAGS" +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi + +# Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# ./install, which can be erroneously created by make from ./install.sh. +echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 +echo "configure:2036: checking for a BSD compatible install" >&5 +if test -z "$INSTALL"; then +if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + IFS="${IFS= }"; ac_save_IFS="$IFS"; IFS=":" + for ac_dir in $PATH; do + # Account for people who put trailing slashes in PATH elements. + case "$ac_dir/" in + /|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + if test -f $ac_dir/$ac_prog; then + if test $ac_prog = install && + grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + else + ac_cv_path_install="$ac_dir/$ac_prog -c" + break 2 + fi + fi + done + ;; + esac + done + IFS="$ac_save_IFS" + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL="$ac_cv_path_install" + else + # As a last resort, use the slow shell script. We don't cache a + # path for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the path is relative. + INSTALL="$ac_install_sh" + fi +fi +echo "$ac_t""$INSTALL" 1>&6 + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + + +# Put a plausible default for CC_FOR_BUILD in Makefile. +if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' +else + CC_FOR_BUILD=gcc +fi + + + + +AR=${AR-ar} + +# Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2104: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_RANLIB="ranlib" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_prog_RANLIB" && ac_cv_prog_RANLIB=":" +fi +fi +RANLIB="$ac_cv_prog_RANLIB" +if test -n "$RANLIB"; then + echo "$ac_t""$RANLIB" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + +ALL_LINGUAS= + + for ac_hdr in argz.h limits.h locale.h nl_types.h malloc.h string.h \ +unistd.h values.h sys/param.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:2139: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2149: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + + for ac_func in getcwd munmap putenv setenv setlocale strchr strcasecmp \ +__argz_count __argz_stringify __argz_next +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:2179: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:2207: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + + + if test "${ac_cv_func_stpcpy+set}" != "set"; then + for ac_func in stpcpy +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:2236: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:2264: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + + fi + if test "${ac_cv_func_stpcpy}" = "yes"; then + cat >> confdefs.h <<\EOF +#define HAVE_STPCPY 1 +EOF + + fi + + if test $ac_cv_header_locale_h = yes; then + echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6 +echo "configure:2298: checking for LC_MESSAGES" >&5 +if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +int main() { +return LC_MESSAGES +; return 0; } +EOF +if { (eval echo configure:2310: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + am_cv_val_LC_MESSAGES=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + am_cv_val_LC_MESSAGES=no +fi +rm -f conftest* +fi + +echo "$ac_t""$am_cv_val_LC_MESSAGES" 1>&6 + if test $am_cv_val_LC_MESSAGES = yes; then + cat >> confdefs.h <<\EOF +#define HAVE_LC_MESSAGES 1 +EOF + + fi + fi + echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6 +echo "configure:2331: checking whether NLS is requested" >&5 + # Check whether --enable-nls or --disable-nls was given. +if test "${enable_nls+set}" = set; then + enableval="$enable_nls" + USE_NLS=$enableval +else + USE_NLS=yes +fi + + echo "$ac_t""$USE_NLS" 1>&6 + + + USE_INCLUDED_LIBINTL=no + + if test "$USE_NLS" = "yes"; then + cat >> confdefs.h <<\EOF +#define ENABLE_NLS 1 +EOF + + echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6 +echo "configure:2351: checking whether included gettext is requested" >&5 + # Check whether --with-included-gettext or --without-included-gettext was given. +if test "${with_included_gettext+set}" = set; then + withval="$with_included_gettext" + nls_cv_force_use_gnu_gettext=$withval +else + nls_cv_force_use_gnu_gettext=no +fi + + echo "$ac_t""$nls_cv_force_use_gnu_gettext" 1>&6 + + nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext" + if test "$nls_cv_force_use_gnu_gettext" != "yes"; then + nls_cv_header_intl= + nls_cv_header_libgt= + CATOBJEXT=NONE + + ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for libintl.h""... $ac_c" 1>&6 +echo "configure:2370: checking for libintl.h" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2380: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6 +echo "configure:2397: checking for gettext in libc" >&5 +if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +int main() { +return (int) gettext ("") +; return 0; } +EOF +if { (eval echo configure:2409: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + gt_cv_func_gettext_libc=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + gt_cv_func_gettext_libc=no +fi +rm -f conftest* +fi + +echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6 + + if test "$gt_cv_func_gettext_libc" != "yes"; then + echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6 +echo "configure:2425: checking for bindtextdomain in -lintl" >&5 +ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_save_LIBS="$LIBS" +LIBS="-lintl $LIBS" +cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=no" +fi +rm -f conftest* +LIBS="$ac_save_LIBS" + +fi +if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then + echo "$ac_t""yes" 1>&6 + echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6 +echo "configure:2460: checking for gettext in libintl" >&5 +if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + gt_cv_func_gettext_libintl=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + gt_cv_func_gettext_libintl=no +fi +rm -f conftest* +fi + +echo "$ac_t""$gt_cv_func_gettext_libintl" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + fi + + if test "$gt_cv_func_gettext_libc" = "yes" \ + || test "$gt_cv_func_gettext_libintl" = "yes"; then + cat >> confdefs.h <<\EOF +#define HAVE_GETTEXT 1 +EOF + + # Extract the first word of "msgfmt", so it can be a program name with args. +set dummy msgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2500: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$MSGFMT" in + /*) + ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then + ac_cv_path_MSGFMT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="no" + ;; +esac +fi +MSGFMT="$ac_cv_path_MSGFMT" +if test -n "$MSGFMT"; then + echo "$ac_t""$MSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + if test "$MSGFMT" != "no"; then + for ac_func in dcgettext +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:2534: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:2562: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + + # Extract the first word of "gmsgfmt", so it can be a program name with args. +set dummy gmsgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2589: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$GMSGFMT" in + /*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path. + ;; + ?:/*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_path_GMSGFMT="$ac_dir/$ac_word" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT" + ;; +esac +fi +GMSGFMT="$ac_cv_path_GMSGFMT" +if test -n "$GMSGFMT"; then + echo "$ac_t""$GMSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + # Extract the first word of "xgettext", so it can be a program name with args. +set dummy xgettext; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2625: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$XGETTEXT" in + /*) + ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then + ac_cv_path_XGETTEXT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":" + ;; +esac +fi +XGETTEXT="$ac_cv_path_XGETTEXT" +if test -n "$XGETTEXT"; then + echo "$ac_t""$XGETTEXT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + CATOBJEXT=.gmo + DATADIRNAME=share +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + CATOBJEXT=.mo + DATADIRNAME=lib +fi +rm -f conftest* + INSTOBJEXT=.mo + fi + fi + +else + echo "$ac_t""no" 1>&6 +fi + + + + if test "$CATOBJEXT" = "NONE"; then + nls_cv_use_gnu_gettext=yes + fi + fi + + if test "$nls_cv_use_gnu_gettext" = "yes"; then + INTLOBJS="\$(GETTOBJS)" + # Extract the first word of "msgfmt", so it can be a program name with args. +set dummy msgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2697: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$MSGFMT" in + /*) + ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then + ac_cv_path_MSGFMT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="msgfmt" + ;; +esac +fi +MSGFMT="$ac_cv_path_MSGFMT" +if test -n "$MSGFMT"; then + echo "$ac_t""$MSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + # Extract the first word of "gmsgfmt", so it can be a program name with args. +set dummy gmsgfmt; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2731: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$GMSGFMT" in + /*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path. + ;; + ?:/*) + ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_path_GMSGFMT="$ac_dir/$ac_word" + break + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT" + ;; +esac +fi +GMSGFMT="$ac_cv_path_GMSGFMT" +if test -n "$GMSGFMT"; then + echo "$ac_t""$GMSGFMT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + # Extract the first word of "xgettext", so it can be a program name with args. +set dummy xgettext; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:2767: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + case "$XGETTEXT" in + /*) + ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path. + ;; + *) + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:" + for ac_dir in $PATH; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then + ac_cv_path_XGETTEXT="$ac_dir/$ac_word" + break + fi + fi + done + IFS="$ac_save_ifs" + test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":" + ;; +esac +fi +XGETTEXT="$ac_cv_path_XGETTEXT" +if test -n "$XGETTEXT"; then + echo "$ac_t""$XGETTEXT" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + + USE_INCLUDED_LIBINTL=yes + CATOBJEXT=.gmo + INSTOBJEXT=.mo + DATADIRNAME=share + INTLDEPS='$(top_builddir)/../intl/libintl.a' + INTLLIBS=$INTLDEPS + LIBS=`echo $LIBS | sed -e 's/-lintl//'` + nls_cv_header_intl=libintl.h + nls_cv_header_libgt=libgettext.h + fi + + if test "$XGETTEXT" != ":"; then + if $XGETTEXT --omit-header /dev/null 2> /dev/null; then + : ; + else + echo "$ac_t""found xgettext programs is not GNU xgettext; ignore it" 1>&6 + XGETTEXT=":" + fi + fi + + # We need to process the po/ directory. + POSUB=po + else + DATADIRNAME=share + nls_cv_header_intl=libintl.h + nls_cv_header_libgt=libgettext.h + fi + + # If this is used in GNU gettext we have to set USE_NLS to `yes' + # because some of the sources are only built for this goal. + if test "$PACKAGE" = gettext; then + USE_NLS=yes + USE_INCLUDED_LIBINTL=yes + fi + + for lang in $ALL_LINGUAS; do + GMOFILES="$GMOFILES $lang.gmo" + POFILES="$POFILES $lang.po" + done + + + + + + + + + + + + + + + if test "x$CATOBJEXT" != "x"; then + if test "x$ALL_LINGUAS" = "x"; then + LINGUAS= + else + echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6 +echo "configure:2857: checking for catalogs to be installed" >&5 + NEW_LINGUAS= + for lang in ${LINGUAS=$ALL_LINGUAS}; do + case "$ALL_LINGUAS" in + *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;; + esac + done + LINGUAS=$NEW_LINGUAS + echo "$ac_t""$LINGUAS" 1>&6 + fi + + if test -n "$LINGUAS"; then + for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done + fi + fi + + if test $ac_cv_header_locale_h = yes; then + INCLUDE_LOCALE_H="#include " + else + INCLUDE_LOCALE_H="\ +/* The system does not provide the header . Take care yourself. */" + fi + + + if test -f $srcdir/po2tbl.sed.in; then + if test "$CATOBJEXT" = ".cat"; then + ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6 +echo "configure:2885: checking for linux/version.h" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2895: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + msgformat=linux +else + echo "$ac_t""no" 1>&6 +msgformat=xopen +fi + + + sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed + fi + sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \ + $srcdir/po2tbl.sed.in > po2tbl.sed + fi + + if test "$PACKAGE" = "gettext"; then + GT_NO="#NO#" + GT_YES= + else + GT_NO= + GT_YES="#YES#" + fi + + + + MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs" + + + l= + + + if test -d $srcdir/po; then + test -d po || mkdir po + if test "x$srcdir" != "x."; then + if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then + posrcprefix="$srcdir/" + else + posrcprefix="../$srcdir/" + fi + else + posrcprefix="../" + fi + rm -f po/POTFILES + sed -e "/^#/d" -e "/^\$/d" -e "s,.*, $posrcprefix& \\\\," -e "\$s/$.*$ \\\\/\1/" \ + < $srcdir/po/POTFILES.in > po/POTFILES + fi + + +# Check for common headers. +# FIXME: Seems to me this can cause problems for i386-windows hosts. +# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*. +for ac_hdr in stdlib.h string.h strings.h unistd.h time.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:2964: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:2974: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + +for ac_hdr in sys/time.h sys/resource.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:3004: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:3014: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + +for ac_hdr in fcntl.h fpu_control.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:3044: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:3054: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + +for ac_hdr in dlfcn.h errno.h sys/stat.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:3084: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:3094: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + +for ac_func in getrusage time sigaction __setfpucw +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:3123: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:3151: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + + +# Check for socket libraries +echo $ac_n "checking for bind in -lsocket""... $ac_c" 1>&6 +echo "configure:3178: checking for bind in -lsocket" >&5 +ac_lib_var=`echo socket'_'bind | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_save_LIBS="$LIBS" +LIBS="-lsocket $LIBS" +cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=no" +fi +rm -f conftest* +LIBS="$ac_save_LIBS" + +fi +if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_lib=HAVE_LIB`echo socket | sed -e 's/[^a-zA-Z0-9_]/_/g' \ + -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'` + cat >> confdefs.h <&6 +fi + +echo $ac_n "checking for gethostbyname in -lnsl""... $ac_c" 1>&6 +echo "configure:3225: checking for gethostbyname in -lnsl" >&5 +ac_lib_var=`echo nsl'_'gethostbyname | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_save_LIBS="$LIBS" +LIBS="-lnsl $LIBS" +cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=no" +fi +rm -f conftest* +LIBS="$ac_save_LIBS" + +fi +if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_lib=HAVE_LIB`echo nsl | sed -e 's/[^a-zA-Z0-9_]/_/g' \ + -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'` + cat >> confdefs.h <&6 +fi + + +. ${srcdir}/../../bfd/configure.host + + + +USE_MAINTAINER_MODE=no +# Check whether --enable-maintainer-mode or --disable-maintainer-mode was given. +if test "${enable_maintainer_mode+set}" = set; then + enableval="$enable_maintainer_mode" + case "${enableval}" in + yes) MAINT="" USE_MAINTAINER_MODE=yes ;; + no) MAINT="#" ;; + *) { echo "configure: error: "--enable-maintainer-mode does not take a value"" 1>&2; exit 1; }; MAINT="#" ;; +esac +if test x"$silent" != x"yes" && test x"$MAINT" = x""; then + echo "Setting maintainer mode" 6>&1 +fi +else + MAINT="#" +fi + + + +# Check whether --enable-sim-bswap or --disable-sim-bswap was given. +if test "${enable_sim_bswap+set}" = set; then + enableval="$enable_sim_bswap" + case "${enableval}" in + yes) sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";; + no) sim_bswap="-DWITH_BSWAP=0";; + *) { echo "configure: error: "--enable-sim-bswap does not take a value"" 1>&2; exit 1; }; sim_bswap="";; +esac +if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then + echo "Setting bswap flags = $sim_bswap" 6>&1 +fi +else + sim_bswap="" +fi + + + +# Check whether --enable-sim-cflags or --disable-sim-cflags was given. +if test "${enable_sim_cflags+set}" = set; then + enableval="$enable_sim_cflags" + case "${enableval}" in + yes) sim_cflags="-O2 -fomit-frame-pointer";; + trace) { echo "configure: error: "Please use --enable-sim-debug instead."" 1>&2; exit 1; }; sim_cflags="";; + no) sim_cflags="";; + *) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then + echo "Setting sim cflags = $sim_cflags" 6>&1 +fi +else + sim_cflags="" +fi + + + +# Check whether --enable-sim-debug or --disable-sim-debug was given. +if test "${enable_sim_debug+set}" = set; then + enableval="$enable_sim_debug" + case "${enableval}" in + yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";; + no) sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";; + *) sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";; +esac +if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then + echo "Setting sim debug = $sim_debug" 6>&1 +fi +else + sim_debug="" +fi + + + +# Check whether --enable-sim-stdio or --disable-sim-stdio was given. +if test "${enable_sim_stdio+set}" = set; then + enableval="$enable_sim_stdio" + case "${enableval}" in + yes) sim_stdio="-DWITH_STDIO=DO_USE_STDIO";; + no) sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";; + *) { echo "configure: error: "Unknown value $enableval passed to --enable-sim-stdio"" 1>&2; exit 1; }; sim_stdio="";; +esac +if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then + echo "Setting stdio flags = $sim_stdio" 6>&1 +fi +else + sim_stdio="" +fi + + + +# Check whether --enable-sim-trace or --disable-sim-trace was given. +if test "${enable_sim_trace+set}" = set; then + enableval="$enable_sim_trace" + case "${enableval}" in + yes) sim_trace="-DTRACE=1 -DWITH_TRACE=-1";; + no) sim_trace="-DTRACE=0 -DWITH_TRACE=0";; + [-0-9]*) + sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";; + [a-z]*) + sim_trace="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_trace" = x; then + sim_trace="-DWITH_TRACE='(TRACE_$x" + else + sim_trace="${sim_trace}|TRACE_$x" + fi + done + sim_trace="$sim_trace)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then + echo "Setting sim trace = $sim_trace" 6>&1 +fi +else + sim_trace="" +fi + + + +# Check whether --enable-sim-profile or --disable-sim-profile was given. +if test "${enable_sim_profile+set}" = set; then + enableval="$enable_sim_profile" + case "${enableval}" in + yes) sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";; + no) sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";; + [-0-9]*) + sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";; + [a-z]*) + sim_profile="" + for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + if test x"$sim_profile" = x; then + sim_profile="-DWITH_PROFILE='(PROFILE_$x" + else + sim_profile="${sim_profile}|PROFILE_$x" + fi + done + sim_profile="$sim_profile)'" ;; +esac +if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then + echo "Setting sim profile = $sim_profile" 6>&1 +fi +else + sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1" +fi + + + +echo $ac_n "checking return type of signal handlers""... $ac_c" 1>&6 +echo "configure:3420: checking return type of signal handlers" >&5 +if eval "test \"`echo '$''{'ac_cv_type_signal'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +#include +#ifdef signal +#undef signal +#endif +#ifdef __cplusplus +extern "C" void (*signal (int, void (*)(int)))(int); +#else +void (*signal ()) (); +#endif + +int main() { +int i; +; return 0; } +EOF +if { (eval echo configure:3442: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_type_signal=void +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_type_signal=int +fi +rm -f conftest* +fi + +echo "$ac_t""$ac_cv_type_signal" 1>&6 +cat >> confdefs.h <&6 +echo "configure:3464: checking for executable suffix" >&5 +if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test "$CYGWIN" = yes || test "$MINGW32" = yes; then + ac_cv_exeext=.exe +else + rm -f conftest* + echo 'int main () { return 0; }' > conftest.$ac_ext + ac_cv_exeext= + if { (eval echo configure:3474: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then + for file in conftest.*; do + case $file in + *.c | *.o | *.obj | *.ilk | *.pdb) ;; + *) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;; + esac + done + else + { echo "configure: error: installation or configuration problem: compiler cannot create executables." 1>&2; exit 1; } + fi + rm -f conftest* + test x"${ac_cv_exeext}" = x && ac_cv_exeext=no +fi +fi + +EXEEXT="" +test x"${ac_cv_exeext}" != xno && EXEEXT=${ac_cv_exeext} +echo "$ac_t""${ac_cv_exeext}" 1>&6 +ac_exeext=$EXEEXT + + +sim_link_files= +sim_link_links= + +sim_link_links=tconfig.h +if test -f ${srcdir}/tconfig.in +then + sim_link_files=tconfig.in +else + sim_link_files=../common/tconfig.in +fi + +# targ-vals.def points to the libc macro description file. +case "${target}" in +*-*-*) TARG_VALS_DEF=../common/nltvals.def ;; +esac +sim_link_files="${sim_link_files} ${TARG_VALS_DEF}" +sim_link_links="${sim_link_links} targ-vals.def" + + + + +wire_endian="LITTLE_ENDIAN" +default_endian="" +# Check whether --enable-sim-endian or --disable-sim-endian was given. +if test "${enable_sim_endian+set}" = set; then + enableval="$enable_sim_endian" + case "${enableval}" in + b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BIG_ENDIAN";; + l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=LITTLE_ENDIAN";; + yes) if test x"$wire_endian" != x; then + sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}" + else + if test x"$default_endian" != x; then + sim_endian="-DWITH_TARGET_BYTE_ORDER=${default_endian}" + else + echo "No hard-wired endian for target $target" 1>&6 + sim_endian="-DWITH_TARGET_BYTE_ORDER=0" + fi + fi;; + no) if test x"$default_endian" != x; then + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}" + else + if test x"$wire_endian" != x; then + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${wire_endian}" + else + echo "No default endian for target $target" 1>&6 + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=0" + fi + fi;; + *) { echo "configure: error: "Unknown value $enableval for --enable-sim-endian"" 1>&2; exit 1; }; sim_endian="";; +esac +if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then + echo "Setting endian flags = $sim_endian" 6>&1 +fi +else + if test x"$default_endian" != x; then + sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}" +else + if test x"$wire_endian" != x; then + sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}" + else + sim_endian= + fi +fi +fi + +wire_alignment="NONSTRICT_ALIGNMENT" +default_alignment="" + +# Check whether --enable-sim-alignment or --disable-sim-alignment was given. +if test "${enable_sim_alignment+set}" = set; then + enableval="$enable_sim_alignment" + case "${enableval}" in + strict | STRICT) sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";; + nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";; + forced | FORCED) sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";; + yes) if test x"$wire_alignment" != x; then + sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}" + else + if test x"$default_alignment" != x; then + sim_alignment="-DWITH_ALIGNMENT=${default_alignment}" + else + echo "No hard-wired alignment for target $target" 1>&6 + sim_alignment="-DWITH_ALIGNMENT=0" + fi + fi;; + no) if test x"$default_alignment" != x; then + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}" + else + if test x"$wire_alignment" != x; then + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}" + else + echo "No default alignment for target $target" 1>&6 + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0" + fi + fi;; + *) { echo "configure: error: "Unknown value $enableval passed to --enable-sim-alignment"" 1>&2; exit 1; }; sim_alignment="";; +esac +if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then + echo "Setting alignment flags = $sim_alignment" 6>&1 +fi +else + if test x"$default_alignment" != x; then + sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}" +else + if test x"$wire_alignment" != x; then + sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}" + else + sim_alignment= + fi +fi +fi + + +# Check whether --enable-sim-hostendian or --disable-sim-hostendian was given. +if test "${enable_sim_hostendian+set}" = set; then + enableval="$enable_sim_hostendian" + case "${enableval}" in + no) sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";; + b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";; + l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";; + *) { echo "configure: error: "Unknown value $enableval for --enable-sim-hostendian"" 1>&2; exit 1; }; sim_hostendian="";; +esac +if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then + echo "Setting hostendian flags = $sim_hostendian" 6>&1 +fi +else + +if test "x$cross_compiling" = "xno"; then + echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6 +echo "configure:3625: checking whether byte ordering is bigendian" >&5 +if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + ac_cv_c_bigendian=unknown +# See if sys/param.h defines the BYTE_ORDER macro. +cat > conftest.$ac_ext < +#include +int main() { + +#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN + bogus endian macros +#endif +; return 0; } +EOF +if { (eval echo configure:3643: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + # It does; now see whether it defined to BIG_ENDIAN or not. +cat > conftest.$ac_ext < +#include +int main() { + +#if BYTE_ORDER != BIG_ENDIAN + not big endian +#endif +; return 0; } +EOF +if { (eval echo configure:3658: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + rm -rf conftest* + ac_cv_c_bigendian=yes +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + ac_cv_c_bigendian=no +fi +rm -f conftest* +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 +fi +rm -f conftest* +if test $ac_cv_c_bigendian = unknown; then +if test "$cross_compiling" = yes; then + { echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; } +else + cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +then + ac_cv_c_bigendian=no +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -fr conftest* + ac_cv_c_bigendian=yes +fi +rm -fr conftest* +fi + +fi +fi + +echo "$ac_t""$ac_cv_c_bigendian" 1>&6 +if test $ac_cv_c_bigendian = yes; then + cat >> confdefs.h <<\EOF +#define WORDS_BIGENDIAN 1 +EOF + +fi + + if test $ac_cv_c_bigendian = yes; then + sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN" + else + sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN" + fi +else + sim_hostendian="-DWITH_HOST_BYTE_ORDER=0" +fi +fi + + +# Check whether --enable-build-warnings or --disable-build-warnings was given. +if test "${enable_build_warnings+set}" = set; then + enableval="$enable_build_warnings" + build_warnings="-Wall -Wpointer-arith -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations" +case "${enableval}" in + yes) ;; + no) build_warnings="-w";; + ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${build_warnings} ${t}";; + *,) t=`echo "${enableval}" | sed -e "s/,/ /g"` + build_warnings="${t} ${build_warnings}";; + *) build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;; +esac +if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then + echo "Setting warning flags = $build_warnings" 6>&1 +fi +WARN_CFLAGS="" +WERROR_CFLAGS="" +if test "x${build_warnings}" != x -a "x$GCC" = xyes +then + # Separate out the -Werror flag as some files just cannot be + # compiled with it enabled. + for w in ${build_warnings}; do + case $w in + -Werr*) WERROR_CFLAGS=-Werror ;; + *) WARN_CFLAGS="${WARN_CFLAGS} $w" + esac + done +fi +else + build_warnings="" +fi + + +default_sim_reserved_bits="1" +# Check whether --enable-sim-reserved-bits or --disable-sim-reserved-bits was given. +if test "${enable_sim_reserved_bits+set}" = set; then + enableval="$enable_sim_reserved_bits" + case "${enableval}" in + yes) sim_reserved_bits="-DWITH_RESERVED_BITS=1";; + no) sim_reserved_bits="-DWITH_RESERVED_BITS=0";; + *) { echo "configure: error: "--enable-sim-reserved-bits does not take a value"" 1>&2; exit 1; }; sim_reserved_bits="";; +esac +if test x"$silent" != x"yes" && test x"$sim_reserved_bits" != x""; then + echo "Setting reserved flags = $sim_reserved_bits" 6>&1 +fi +else + sim_reserved_bits="-DWITH_RESERVED_BITS=${default_sim_reserved_bits}" +fi + +wire_word_bitsize="32" +wire_word_msb="31" +wire_address_bitsize="" +wire_cell_bitsize="" +# Check whether --enable-sim-bitsize or --disable-sim-bitsize was given. +if test "${enable_sim_bitsize+set}" = set; then + enableval="$enable_sim_bitsize" + sim_bitsize= +case "${enableval}" in + 64,63 | 64,63,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=63";; + 32,31 | 32,31,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31";; + 64,0 | 64,0,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0";; + 32,0 | 64,0,* ) sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0";; + 32) if test x"$wire_word_msb" != x -a x"$wire_word_msb" != x0; then + sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31" + else + sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=0" + fi ;; + 64) if test x"$wire_word_msb" != x -a x"$wire_word_msb" != x0; then + sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=63" + else + sim_bitsize="-DWITH_TARGET_WORD_BITSIZE=64 -DWITH_TARGET_WORD_MSB=0" + fi ;; + *) { echo "configure: error: "--enable-sim-bitsize was given $enableval. Expected 32 or 64"" 1>&2; exit 1; } ;; +esac +# address bitsize +tmp=`echo "${enableval}" | sed -e "s/^[0-9]*,*[0-9]*,*//"` +case x"${tmp}" in + x ) ;; + x32 | x32,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_ADDRESS_BITSIZE=32" ;; + x64 | x64,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_ADDRESS_BITSIZE=64" ;; + * ) { echo "configure: error: "--enable-sim-bitsize was given address size $enableval. Expected 32 or 64"" 1>&2; exit 1; } ;; +esac +# cell bitsize +tmp=`echo "${enableval}" | sed -e "s/^[0-9]*,*[0-9*]*,*[0-9]*,*//"` +case x"${tmp}" in + x ) ;; + x32 | x32,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_CELL_BITSIZE=32" ;; + x64 | x64,* ) sim_bitsize="${sim_bitsize} -DWITH_TARGET_CELL_BITSIZE=64" ;; + * ) { echo "configure: error: "--enable-sim-bitsize was given cell size $enableval. Expected 32 or 64"" 1>&2; exit 1; } ;; +esac +if test x"$silent" != x"yes" && test x"$sim_bitsize" != x""; then + echo "Setting bitsize flags = $sim_bitsize" 6>&1 +fi +else + sim_bitsize="" +if test x"$wire_word_bitsize" != x; then + sim_bitsize="$sim_bitsize -DWITH_TARGET_WORD_BITSIZE=$wire_word_bitsize" +fi +if test x"$wire_word_msb" != x; then + sim_bitsize="$sim_bitsize -DWITH_TARGET_WORD_MSB=$wire_word_msb" +fi +if test x"$wire_address_bitsize" != x; then + sim_bitsize="$sim_bitsize -DWITH_TARGET_ADDRESS_BITSIZE=$wire_address_bitsize" +fi +if test x"$wire_cell_bitsize" != x; then + sim_bitsize="$sim_bitsize -DWITH_TARGET_CELL_BITSIZE=$wire_cell_bitsize" +fi +fi + + +default_sim_inline="" +# Check whether --enable-sim-inline or --disable-sim-inline was given. +if test "${enable_sim_inline+set}" = set; then + enableval="$enable_sim_inline" + sim_inline="" +case "$enableval" in + no) sim_inline="-DDEFAULT_INLINE=0";; + 0) sim_inline="-DDEFAULT_INLINE=0";; + yes | 2) sim_inline="-DDEFAULT_INLINE=ALL_C_INLINE";; + 1) sim_inline="-DDEFAULT_INLINE=INLINE_LOCALS";; + *) for x in `echo "$enableval" | sed -e "s/,/ /g"`; do + new_flag="" + case "$x" in + *_INLINE=*) new_flag="-D$x";; + *=*) new_flag=`echo "$x" | sed -e "s/=/_INLINE=/" -e "s/^/-D/"`;; + *_INLINE) new_flag="-D$x=ALL_C_INLINE";; + *) new_flag="-D$x""_INLINE=ALL_C_INLINE";; + esac + if test x"$sim_inline" = x""; then + sim_inline="$new_flag" + else + sim_inline="$sim_inline $new_flag" + fi + done;; +esac +if test x"$silent" != x"yes" && test x"$sim_inline" != x""; then + echo "Setting inline flags = $sim_inline" 6>&1 +fi +else + +if test "x$cross_compiling" = "xno"; then + if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then + sim_inline="${default_sim_inline}" + if test x"$silent" != x"yes"; then + echo "Setting inline flags = $sim_inline" 6>&1 + fi + else + sim_inline="" + fi +else + sim_inline="-DDEFAULT_INLINE=0" +fi +fi + + +if test x"yes" = x"yes"; then + sim_hw_p=yes +else + sim_hw_p=no +fi +if test ""; then + hardware="core pal glue" +else + hardware="core pal glue mn103cpu mn103int mn103tim mn103ser mn103iop" +fi +sim_hw_cflags="-DWITH_HW=1" +sim_hw="$hardware" +sim_hw_objs="\$(SIM_COMMON_HW_OBJS) `echo $sim_hw | sed -e 's/$[^ ][^ ]*$/dv-\1.o/g'`" +# Check whether --enable-sim-hardware or --disable-sim-hardware was given. +if test "${enable_sim_hardware+set}" = set; then + enableval="$enable_sim_hardware" + +case "${enableval}" in + yes) sim_hw_p=yes;; + no) sim_hw_p=no;; + ,*) sim_hw_p=yes; hardware="${hardware} `echo ${enableval} | sed -e 's/,/ /'`";; + *,) sim_hw_p=yes; hardware="`echo ${enableval} | sed -e 's/,/ /'` ${hardware}";; + *) sim_hw_p=yes; hardware="`echo ${enableval} | sed -e 's/,/ /'`"'';; +esac +if test "$sim_hw_p" != yes; then + sim_hw_objs= + sim_hw_cflags="-DWITH_HW=0" + sim_hw= +else + sim_hw_cflags="-DWITH_HW=1" + # remove duplicates + sim_hw="" + sim_hw_objs="\$(SIM_COMMON_HW_OBJS)" + for i in x $hardware ; do + case " $f " in + x) ;; + *" $i "*) ;; + *) sim_hw="$sim_hw $i" ; sim_hw_objs="$sim_hw_objs dv-$i.o";; + esac + done +fi +if test x"$silent" != x"yes" && test "$sim_hw_p" = "yes"; then + echo "Setting hardware to $sim_hw_cflags, $sim_hw, $sim_hw_objs" +fi +else + +if test "$sim_hw_p" != yes; then + sim_hw_objs= + sim_hw_cflags="-DWITH_HW=0" + sim_hw= +fi +if test x"$silent" != x"yes"; then + echo "Setting hardware to $sim_hw_cflags, $sim_hw, $sim_hw_objs" +fi +fi + + +for ac_func in time chmod utime fork execve execv chown +do +echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 +echo "configure:3941: checking for $ac_func" >&5 +if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char $ac_func(); + +int main() { + +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. Some functions are actually named + something starting with __ and the normal name is an alias. */ +#if defined (__stub_$ac_func) || defined (__stub___$ac_func) +choke me +#else +$ac_func(); +#endif + +; return 0; } +EOF +if { (eval echo configure:3969: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_func_$ac_func=yes" +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_func_$ac_func=no" +fi +rm -f conftest* +fi + +if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'` + cat >> confdefs.h <&6 +fi +done + +for ac_hdr in unistd.h stdlib.h string.h strings.h utime.h time.h +do +ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` +echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 +echo "configure:3997: checking for $ac_hdr" >&5 +if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.$ac_ext < +EOF +ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" +{ (eval echo configure:4007: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` +if test -z "$ac_err"; then + rm -rf conftest* + eval "ac_cv_header_$ac_safe=yes" +else + echo "$ac_err" >&5 + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + rm -rf conftest* + eval "ac_cv_header_$ac_safe=no" +fi +rm -f conftest* +fi +if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then + echo "$ac_t""yes" 1>&6 + ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'` + cat >> confdefs.h <&6 +fi +done + + +# +# Enable common +# +# Check whether --enable-sim-common or --disable-sim-common was given. +if test "${enable_sim_common+set}" = set; then + enableval="$enable_sim_common" + case "${enableval}" in + yes) sim_gen="-DWITH_COMMON=1"; mn10300_common="WITH";; + no) sim_gen="-DWITH_COMMON=0"; mn10300_common="WITHOUT";; + *) { echo "configure: error: "Unknown value $enableval passed to --enable-sim-common"" 1>&2; exit 1; }; sim_gen="";; +esac +if test x"$silent" != x"yes" && test x"$sim_gen" != x""; then + echo "Setting sim_common = $sim_common" 6>&1 +fi +else + sim_gen="-DWITH_COMMON=1"; mn10300_common="WITH" +fi + + + + + +trap '' 1 2 15 +cat > confcache <<\EOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs. It is not useful on other systems. +# If it contains results you don't want to keep, you may remove or edit it. +# +# By default, configure uses ./config.cache as the cache file, +# creating it if it does not exist already. You can give configure +# the --cache-file=FILE option to use a different cache file; that is +# what configure does when it calls configure scripts in +# subdirectories, so they share the cache. +# Giving --cache-file=/dev/null disables caching, for debugging configure. +# config.status only pays attention to the cache file if you give it the +# --recheck option to rerun configure. +# +EOF +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, don't put newlines in cache variables' values. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +(set) 2>&1 | + case `(ac_space=' '; set | grep ac_space) 2>&1` in + *ac_space=\ *) + # `set' does not quote correctly, so add quotes (double-quote substitution + # turns \\\\ into \\, and sed turns \\ into \). + sed -n \ + -e "s/'/'\\\\''/g" \ + -e "s/^\$[a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\$=\$.*\$/\\1=\${\\1='\\2'}/p" + ;; + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n -e 's/^$[a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*$=$.*$/\1=${\1=\2}/p' + ;; + esac >> confcache +if cmp -s $cache_file confcache; then + : +else + if test -w $cache_file; then + echo "updating cache $cache_file" + cat confcache > $cache_file + else + echo "not updating unwritable cache $cache_file" + fi +fi +rm -f confcache + +trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15 + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +# Any assignment to VPATH causes Sun make to only execute +# the first set of double-colon rules, so remove it if not needed. +# If there is a colon in the path, we need to keep it. +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d' +fi + +trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15 + +DEFS=-DHAVE_CONFIG_H + +# Without the "./", some shells look in PATH for config.status. +: ${CONFIG_STATUS=./config.status} + +echo creating $CONFIG_STATUS +rm -f $CONFIG_STATUS +cat > $CONFIG_STATUS </dev/null | sed 1q`: +# +# $0 $ac_configure_args +# +# Compiler output produced by configure, useful for debugging +# configure, is in ./config.log if it exists. + +ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]" +for ac_option +do + case "\$ac_option" in + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" + exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; + -version | --version | --versio | --versi | --vers | --ver | --ve | --v) + echo "$CONFIG_STATUS generated by autoconf version 2.13" + exit 0 ;; + -help | --help | --hel | --he | --h) + echo "\$ac_cs_usage"; exit 0 ;; + *) echo "\$ac_cs_usage"; exit 1 ;; + esac +done + +ac_given_srcdir=$srcdir +ac_given_INSTALL="$INSTALL" + +trap 'rm -fr `echo "Makefile.sim:Makefile.in Make-common.sim:../common/Make-common.in .gdbinit:../common/gdbinit.in config.h:config.in" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15 +EOF +cat >> $CONFIG_STATUS < conftest.subs <<\\CEOF +$ac_vpsub +$extrasub +s%@sim_environment@%$sim_environment%g +s%@sim_alignment@%$sim_alignment%g +s%@sim_assert@%$sim_assert%g +s%@sim_bitsize@%$sim_bitsize%g +s%@sim_endian@%$sim_endian%g +s%@sim_hostendian@%$sim_hostendian%g +s%@sim_float@%$sim_float%g +s%@sim_scache@%$sim_scache%g +s%@sim_default_model@%$sim_default_model%g +s%@sim_hw_cflags@%$sim_hw_cflags%g +s%@sim_hw_objs@%$sim_hw_objs%g +s%@sim_hw@%$sim_hw%g +s%@sim_inline@%$sim_inline%g +s%@sim_packages@%$sim_packages%g +s%@sim_regparm@%$sim_regparm%g +s%@sim_reserved_bits@%$sim_reserved_bits%g +s%@sim_smp@%$sim_smp%g +s%@sim_stdcall@%$sim_stdcall%g +s%@sim_xor_endian@%$sim_xor_endian%g +s%@WARN_CFLAGS@%$WARN_CFLAGS%g +s%@WERROR_CFLAGS@%$WERROR_CFLAGS%g +s%@SHELL@%$SHELL%g +s%@CFLAGS@%$CFLAGS%g +s%@CPPFLAGS@%$CPPFLAGS%g +s%@CXXFLAGS@%$CXXFLAGS%g +s%@FFLAGS@%$FFLAGS%g +s%@DEFS@%$DEFS%g +s%@LDFLAGS@%$LDFLAGS%g +s%@LIBS@%$LIBS%g +s%@exec_prefix@%$exec_prefix%g +s%@prefix@%$prefix%g +s%@program_transform_name@%$program_transform_name%g +s%@bindir@%$bindir%g +s%@sbindir@%$sbindir%g +s%@libexecdir@%$libexecdir%g +s%@datadir@%$datadir%g +s%@sysconfdir@%$sysconfdir%g +s%@sharedstatedir@%$sharedstatedir%g +s%@localstatedir@%$localstatedir%g +s%@libdir@%$libdir%g +s%@includedir@%$includedir%g +s%@oldincludedir@%$oldincludedir%g +s%@infodir@%$infodir%g +s%@mandir@%$mandir%g +s%@host@%$host%g +s%@host_alias@%$host_alias%g +s%@host_cpu@%$host_cpu%g +s%@host_vendor@%$host_vendor%g +s%@host_os@%$host_os%g +s%@target@%$target%g +s%@target_alias@%$target_alias%g +s%@target_cpu@%$target_cpu%g +s%@target_vendor@%$target_vendor%g +s%@target_os@%$target_os%g +s%@build@%$build%g +s%@build_alias@%$build_alias%g +s%@build_cpu@%$build_cpu%g +s%@build_vendor@%$build_vendor%g +s%@build_os@%$build_os%g +s%@CC@%$CC%g +s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g +s%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g +s%@INSTALL_DATA@%$INSTALL_DATA%g +s%@CC_FOR_BUILD@%$CC_FOR_BUILD%g +s%@HDEFINES@%$HDEFINES%g +s%@AR@%$AR%g +s%@RANLIB@%$RANLIB%g +s%@SET_MAKE@%$SET_MAKE%g +s%@CPP@%$CPP%g +s%@ALLOCA@%$ALLOCA%g +s%@USE_NLS@%$USE_NLS%g +s%@MSGFMT@%$MSGFMT%g +s%@GMSGFMT@%$GMSGFMT%g +s%@XGETTEXT@%$XGETTEXT%g +s%@USE_INCLUDED_LIBINTL@%$USE_INCLUDED_LIBINTL%g +s%@CATALOGS@%$CATALOGS%g +s%@CATOBJEXT@%$CATOBJEXT%g +s%@DATADIRNAME@%$DATADIRNAME%g +s%@GMOFILES@%$GMOFILES%g +s%@INSTOBJEXT@%$INSTOBJEXT%g +s%@INTLDEPS@%$INTLDEPS%g +s%@INTLLIBS@%$INTLLIBS%g +s%@INTLOBJS@%$INTLOBJS%g +s%@POFILES@%$POFILES%g +s%@POSUB@%$POSUB%g +s%@INCLUDE_LOCALE_H@%$INCLUDE_LOCALE_H%g +s%@GT_NO@%$GT_NO%g +s%@GT_YES@%$GT_YES%g +s%@MKINSTALLDIRS@%$MKINSTALLDIRS%g +s%@l@%$l%g +s%@MAINT@%$MAINT%g +s%@sim_bswap@%$sim_bswap%g +s%@sim_cflags@%$sim_cflags%g +s%@sim_debug@%$sim_debug%g +s%@sim_stdio@%$sim_stdio%g +s%@sim_trace@%$sim_trace%g +s%@sim_profile@%$sim_profile%g +s%@EXEEXT@%$EXEEXT%g +s%@sim_gen@%$sim_gen%g +s%@mn10300_common@%$mn10300_common%g + +CEOF +EOF + +cat >> $CONFIG_STATUS <<\EOF + +# Split the substitutions into bite-sized pieces for seds with +# small command number limits, like on Digital OSF/1 and HP-UX. +ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script. +ac_file=1 # Number of current file. +ac_beg=1 # First line for current file. +ac_end=$ac_max_sed_cmds # Line after last line for current file. +ac_more_lines=: +ac_sed_cmds="" +while $ac_more_lines; do + if test $ac_beg -gt 1; then + sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file + else + sed "${ac_end}q" conftest.subs > conftest.s$ac_file + fi + if test ! -s conftest.s$ac_file; then + ac_more_lines=false + rm -f conftest.s$ac_file + else + if test -z "$ac_sed_cmds"; then + ac_sed_cmds="sed -f conftest.s$ac_file" + else + ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file" + fi + ac_file=`expr $ac_file + 1` + ac_beg=$ac_end + ac_end=`expr $ac_end + $ac_max_sed_cmds` + fi +done +if test -z "$ac_sed_cmds"; then + ac_sed_cmds=cat +fi +EOF + +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories. + + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`" + # A "../" for each directory in $ac_dir_suffix. + ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'` + else + ac_dir_suffix= ac_dots= + fi + + case "$ac_given_srcdir" in + .) srcdir=. + if test -z "$ac_dots"; then top_srcdir=. + else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;; + /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;; + *) # Relative path. + srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix" + top_srcdir="$ac_dots$ac_given_srcdir" ;; + esac + + case "$ac_given_INSTALL" in + [/$]*) INSTALL="$ac_given_INSTALL" ;; + *) INSTALL="$ac_dots$ac_given_INSTALL" ;; + esac + + echo creating "$ac_file" + rm -f "$ac_file" + configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure." + case "$ac_file" in + *Makefile*) ac_comsub="1i\\ +# $configure_input" ;; + *) ac_comsub= ;; + esac + + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + sed -e "$ac_comsub +s%@configure_input@%$configure_input%g +s%@srcdir@%$srcdir%g +s%@top_srcdir@%$top_srcdir%g +s%@INSTALL@%$INSTALL%g +" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file +fi; done +rm -f conftest.s* + +# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where +# NAME is the cpp macro being defined and VALUE is the value it is being given. +# +# ac_d sets the value in "#define NAME VALUE" lines. +ac_dA='s%^$[ ]*$#$[ ]*define[ ][ ]*$' +ac_dB='$[ ][ ]*$[^ ]*%\1#\2' +ac_dC='\3' +ac_dD='%g' +# ac_u turns "#undef NAME" with trailing blanks into "#define NAME VALUE". +ac_uA='s%^$[ ]*$#$[ ]*$undef$[ ][ ]*$' +ac_uB='$[ ]$%\1#\2define\3' +ac_uC=' ' +ac_uD='\4%g' +# ac_e turns "#undef NAME" without trailing blanks into "#define NAME VALUE". +ac_eA='s%^$[ ]*$#$[ ]*$undef$[ ][ ]*$' +ac_eB='$%\1#\2define\3' +ac_eC=' ' +ac_eD='%g' + +if test "${CONFIG_HEADERS+set}" != set; then +EOF +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +fi +for ac_file in .. $CONFIG_HEADERS; do if test "x$ac_file" != x..; then + # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". + case "$ac_file" in + *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'` + ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;; + *) ac_file_in="${ac_file}.in" ;; + esac + + echo creating $ac_file + + rm -f conftest.frag conftest.in conftest.out + ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"` + cat $ac_file_inputs > conftest.in + +EOF + +# Transform confdefs.h into a sed script conftest.vals that substitutes +# the proper values into config.h.in to produce config.h. And first: +# Protect against being on the right side of a sed subst in config.status. +# Protect against being in an unquoted here document in config.status. +rm -f conftest.vals +cat > conftest.hdr <<\EOF +s/[\\&%]/\\&/g +s%[\\$`]%\\&%g +s%#define $[A-Za-z_][A-Za-z0-9_]*$ *$.*$%${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD}%gp +s%ac_d%ac_u%gp +s%ac_u%ac_e%gp +EOF +sed -n -f conftest.hdr confdefs.h > conftest.vals +rm -f conftest.hdr + +# This sed command replaces #undef with comments. This is necessary, for +# example, in the case of _POSIX_SOURCE, which is predefined and required +# on some systems where configure will not decide to define it. +cat >> conftest.vals <<\EOF +s%^[ ]*#[ ]*undef[ ][ ]*[a-zA-Z_][a-zA-Z_0-9]*%/* & */% +EOF + +# Break up conftest.vals because some shells have a limit on +# the size of here documents, and old seds have small limits too. + +rm -f conftest.tail +while : +do + ac_lines=`grep -c . conftest.vals` + # grep -c gives empty output for an empty file on some AIX systems. + if test -z "$ac_lines" || test "$ac_lines" -eq 0; then break; fi + # Write a limited-size here document to conftest.frag. + echo ' cat > conftest.frag <> $CONFIG_STATUS + sed ${ac_max_here_lines}q conftest.vals >> $CONFIG_STATUS + echo 'CEOF + sed -f conftest.frag conftest.in > conftest.out + rm -f conftest.in + mv conftest.out conftest.in +' >> $CONFIG_STATUS + sed 1,${ac_max_here_lines}d conftest.vals > conftest.tail + rm -f conftest.vals + mv conftest.tail conftest.vals +done +rm -f conftest.vals + +cat >> $CONFIG_STATUS <<\EOF + rm -f conftest.frag conftest.h + echo "/* $ac_file. Generated automatically by configure. */" > conftest.h + cat conftest.in >> conftest.h + rm -f conftest.in + if cmp -s $ac_file conftest.h 2>/dev/null; then + echo "$ac_file is unchanged" + rm -f conftest.h + else + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + fi + rm -f $ac_file + mv conftest.h $ac_file + fi +fi; done + +EOF + +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +srcdir=$ac_given_srcdir +while test -n "$ac_sources"; do + set $ac_dests; ac_dest=$1; shift; ac_dests=$* + set $ac_sources; ac_source=$1; shift; ac_sources=$* + + echo "linking $srcdir/$ac_source to $ac_dest" + + if test ! -r $srcdir/$ac_source; then + { echo "configure: error: $srcdir/$ac_source: File not found" 1>&2; exit 1; } + fi + rm -f $ac_dest + + # Make relative symlinks. + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dest_dir=`echo $ac_dest|sed 's%/[^/][^/]*$%%'` + if test "$ac_dest_dir" != "$ac_dest" && test "$ac_dest_dir" != .; then + # The dest file is in a subdirectory. + test ! -d "$ac_dest_dir" && mkdir "$ac_dest_dir" + ac_dest_dir_suffix="/`echo $ac_dest_dir|sed 's%^\./%%'`" + # A "../" for each directory in $ac_dest_dir_suffix. + ac_dots=`echo $ac_dest_dir_suffix|sed 's%/[^/]*%../%g'` + else + ac_dest_dir_suffix= ac_dots= + fi + + case "$srcdir" in + [/$]*) ac_rel_source="$srcdir/$ac_source" ;; + *) ac_rel_source="$ac_dots$srcdir/$ac_source" ;; + esac + + # Make a symlink if possible; otherwise try a hard link. + if ln -s $ac_rel_source $ac_dest 2>/dev/null || + ln $srcdir/$ac_source $ac_dest; then : + else + { echo "configure: error: can not link $ac_dest to $srcdir/$ac_source" 1>&2; exit 1; } + fi +done +EOF +cat >> $CONFIG_STATUS <> $CONFIG_STATUS <<\EOF +case "x$CONFIG_FILES" in + xMakefile*) + echo "Merging Makefile.sim+Make-common.sim into Makefile ..." + rm -f Makesim1.tmp Makesim2.tmp Makefile + sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' Makesim1.tmp + sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' Makesim2.tmp + sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \ + -e '/^## COMMON_POST_/ r Makesim2.tmp' \ + Makefile + rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp + ;; + esac + case "x$CONFIG_HEADERS" in xconfig.h:config.in) echo > stamp-h ;; esac + +exit 0 +EOF +chmod +x $CONFIG_STATUS +rm -fr confdefs* $ac_clean_files +test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1 + +

configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: interp.c =================================================================== --- interp.c (nonexistent) +++ interp.c (revision 1765) @@ -0,0 +1,1422 @@ +#include + +#if WITH_COMMON +#include "sim-main.h" +#include "sim-options.h" +#include "sim-hw.h" +#else +#include "mn10300_sim.h" +#endif + +#include "sysdep.h" +#include "bfd.h" +#include "sim-assert.h" + + +#ifdef HAVE_STDLIB_H +#include +#endif + +#ifdef HAVE_STRING_H +#include +#else +#ifdef HAVE_STRINGS_H +#include +#endif +#endif + +#include "bfd.h" + +#ifndef INLINE +#ifdef __GNUC__ +#define INLINE inline +#else +#define INLINE +#endif +#endif + + +host_callback *mn10300_callback; +int mn10300_debug; +struct _state State; + + +/* simulation target board. NULL=default configuration */ +static char* board = NULL; + +static DECLARE_OPTION_HANDLER (mn10300_option_handler); + +enum { + OPTION_BOARD = OPTION_START, +}; + +static SIM_RC +mn10300_option_handler (sd, cpu, opt, arg, is_command) + SIM_DESC sd; + sim_cpu *cpu; + int opt; + char *arg; + int is_command; +{ + int cpu_nr; + switch (opt) + { + case OPTION_BOARD: + { + if (arg) + { + board = zalloc(strlen(arg) + 1); + strcpy(board, arg); + } + return SIM_RC_OK; + } + } + + return SIM_RC_OK; +} + +static const OPTION mn10300_options[] = +{ +#define BOARD_AM32 "stdeval1" + { {"board", required_argument, NULL, OPTION_BOARD}, + '\0', "none" /* rely on compile-time string concatenation for other options */ + "|" BOARD_AM32 + , "Customize simulation for a particular board.", mn10300_option_handler }, + + { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } +}; + +#if WITH_COMMON +#else +static void dispatch PARAMS ((uint32, uint32, int)); +static long hash PARAMS ((long)); +static void init_system PARAMS ((void)); + +static SIM_OPEN_KIND sim_kind; +static char *myname; +#define MAX_HASH 127 + +struct hash_entry +{ + struct hash_entry *next; + long opcode; + long mask; + struct simops *ops; +#ifdef HASH_STAT + unsigned long count; +#endif +}; + +static int max_mem = 0; +struct hash_entry hash_table[MAX_HASH+1]; + + +/* This probably doesn't do a very good job at bucket filling, but + it's simple... */ +static INLINE long +hash(insn) + long insn; +{ + /* These are one byte insns, we special case these since, in theory, + they should be the most heavily used. */ + if ((insn & 0xffffff00) == 0) + { + switch (insn & 0xf0) + { + case 0x00: + return 0x70; + + case 0x40: + return 0x71; + + case 0x10: + return 0x72; + + case 0x30: + return 0x73; + + case 0x50: + return 0x74; + + case 0x60: + return 0x75; + + case 0x70: + return 0x76; + + case 0x80: + return 0x77; + + case 0x90: + return 0x78; + + case 0xa0: + return 0x79; + + case 0xb0: + return 0x7a; + + case 0xe0: + return 0x7b; + + default: + return 0x7c; + } + } + + /* These are two byte insns */ + if ((insn & 0xffff0000) == 0) + { + if ((insn & 0xf000) == 0x2000 + || (insn & 0xf000) == 0x5000) + return ((insn & 0xfc00) >> 8) & 0x7f; + + if ((insn & 0xf000) == 0x4000) + return ((insn & 0xf300) >> 8) & 0x7f; + + if ((insn & 0xf000) == 0x8000 + || (insn & 0xf000) == 0x9000 + || (insn & 0xf000) == 0xa000 + || (insn & 0xf000) == 0xb000) + return ((insn & 0xf000) >> 8) & 0x7f; + + if ((insn & 0xff00) == 0xf000 + || (insn & 0xff00) == 0xf100 + || (insn & 0xff00) == 0xf200 + || (insn & 0xff00) == 0xf500 + || (insn & 0xff00) == 0xf600) + return ((insn & 0xfff0) >> 4) & 0x7f; + + if ((insn & 0xf000) == 0xc000) + return ((insn & 0xff00) >> 8) & 0x7f; + + return ((insn & 0xffc0) >> 6) & 0x7f; + } + + /* These are three byte insns. */ + if ((insn & 0xff000000) == 0) + { + if ((insn & 0xf00000) == 0x000000) + return ((insn & 0xf30000) >> 16) & 0x7f; + + if ((insn & 0xf00000) == 0x200000 + || (insn & 0xf00000) == 0x300000) + return ((insn & 0xfc0000) >> 16) & 0x7f; + + if ((insn & 0xff0000) == 0xf80000) + return ((insn & 0xfff000) >> 12) & 0x7f; + + if ((insn & 0xff0000) == 0xf90000) + return ((insn & 0xfffc00) >> 10) & 0x7f; + + return ((insn & 0xff0000) >> 16) & 0x7f; + } + + /* These are four byte or larger insns. */ + if ((insn & 0xf0000000) == 0xf0000000) + return ((insn & 0xfff00000) >> 20) & 0x7f; + + return ((insn & 0xff000000) >> 24) & 0x7f; +} + +static INLINE void +dispatch (insn, extension, length) + uint32 insn; + uint32 extension; + int length; +{ + struct hash_entry *h; + + h = &hash_table[hash(insn)]; + + while ((insn & h->mask) != h->opcode + || (length != h->ops->length)) + { + if (!h->next) + { + (*mn10300_callback->printf_filtered) (mn10300_callback, + "ERROR looking up hash for 0x%x, PC=0x%x\n", insn, PC); + exit(1); + } + h = h->next; + } + + +#ifdef HASH_STAT + h->count++; +#endif + + /* Now call the right function. */ + (h->ops->func)(insn, extension); + PC += length; +} + +void +sim_size (power) + int power; + +{ + if (State.mem) + free (State.mem); + + max_mem = 1 << power; + State.mem = (uint8 *) calloc (1, 1 << power); + if (!State.mem) + { + (*mn10300_callback->printf_filtered) (mn10300_callback, "Allocation of main memory failed.\n"); + exit (1); + } +} + +static void +init_system () +{ + if (!State.mem) + sim_size(19); +} + +int +sim_write (sd, addr, buffer, size) + SIM_DESC sd; + SIM_ADDR addr; + unsigned char *buffer; + int size; +{ + int i; + + init_system (); + + for (i = 0; i < size; i++) + store_byte (addr + i, buffer[i]); + + return size; +} + +/* Compare two opcode table entries for qsort. */ +static int +compare_simops (arg1, arg2) + const PTR arg1; + const PTR arg2; +{ + unsigned long code1 = ((struct simops *)arg1)->opcode; + unsigned long code2 = ((struct simops *)arg2)->opcode; + + if (code1 < code2) + return -1; + if (code2 < code1) + return 1; + return 0; +} + +SIM_DESC +sim_open (kind, cb, abfd, argv) + SIM_OPEN_KIND kind; + host_callback *cb; + struct _bfd *abfd; + char **argv; +{ + struct simops *s; + struct hash_entry *h; + char **p; + int i; + + mn10300_callback = cb; + + /* Sort the opcode array from smallest opcode to largest. + This will generally improve simulator performance as the smaller + opcodes are generally preferred to the larger opcodes. */ + for (i = 0, s = Simops; s->func; s++, i++) + ; + qsort (Simops, i, sizeof (Simops[0]), compare_simops); + + sim_kind = kind; + myname = argv[0]; + + for (p = argv + 1; *p; ++p) + { + if (strcmp (*p, "-E") == 0) + ++p; /* ignore endian spec */ + else +#ifdef DEBUG + if (strcmp (*p, "-t") == 0) + mn10300_debug = DEBUG; + else +#endif + (*mn10300_callback->printf_filtered) (mn10300_callback, "ERROR: unsupported option(s): %s\n",*p); + } + + /* put all the opcodes in the hash table */ + for (s = Simops; s->func; s++) + { + h = &hash_table[hash(s->opcode)]; + + /* go to the last entry in the chain */ + while (h->next) + { + /* Don't insert the same opcode more than once. */ + if (h->opcode == s->opcode + && h->mask == s->mask + && h->ops == s) + break; + else + h = h->next; + } + + /* Don't insert the same opcode more than once. */ + if (h->opcode == s->opcode + && h->mask == s->mask + && h->ops == s) + continue; + + if (h->ops) + { + h->next = calloc(1,sizeof(struct hash_entry)); + h = h->next; + } + h->ops = s; + h->mask = s->mask; + h->opcode = s->opcode; +#if HASH_STAT + h->count = 0; +#endif + } + + + /* fudge our descriptor for now */ + return (SIM_DESC) 1; +} + + +void +sim_close (sd, quitting) + SIM_DESC sd; + int quitting; +{ + /* nothing to do */ +} + +void +sim_set_profile (n) + int n; +{ + (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile %d\n", n); +} + +void +sim_set_profile_size (n) + int n; +{ + (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile_size %d\n", n); +} + +int +sim_stop (sd) + SIM_DESC sd; +{ + return 0; +} + +void +sim_resume (sd, step, siggnal) + SIM_DESC sd; + int step, siggnal; +{ + uint32 inst; + reg_t oldpc; + struct hash_entry *h; + + if (step) + State.exception = SIGTRAP; + else + State.exception = 0; + + State.exited = 0; + + do + { + unsigned long insn, extension; + + /* Fetch the current instruction. */ + inst = load_mem_big (PC, 2); + oldpc = PC; + + /* Using a giant case statement may seem like a waste because of the + code/rodata size the table itself will consume. However, using + a giant case statement speeds up the simulator by 10-15% by avoiding + cascading if/else statements or cascading case statements. */ + + switch ((inst >> 8) & 0xff) + { + /* All the single byte insns except 0x80, 0x90, 0xa0, 0xb0 + which must be handled specially. */ + case 0x00: + case 0x04: + case 0x08: + case 0x0c: + case 0x10: + case 0x11: + case 0x12: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + case 0x18: + case 0x19: + case 0x1a: + case 0x1b: + case 0x1c: + case 0x1d: + case 0x1e: + case 0x1f: + case 0x3c: + case 0x3d: + case 0x3e: + case 0x3f: + case 0x40: + case 0x41: + case 0x44: + case 0x45: + case 0x48: + case 0x49: + case 0x4c: + case 0x4d: + case 0x50: + case 0x51: + case 0x52: + case 0x53: + case 0x54: + case 0x55: + case 0x56: + case 0x57: + case 0x60: + case 0x61: + case 0x62: + case 0x63: + case 0x64: + case 0x65: + case 0x66: + case 0x67: + case 0x68: + case 0x69: + case 0x6a: + case 0x6b: + case 0x6c: + case 0x6d: + case 0x6e: + case 0x6f: + case 0x70: + case 0x71: + case 0x72: + case 0x73: + case 0x74: + case 0x75: + case 0x76: + case 0x77: + case 0x78: + case 0x79: + case 0x7a: + case 0x7b: + case 0x7c: + case 0x7d: + case 0x7e: + case 0x7f: + case 0xcb: + case 0xd0: + case 0xd1: + case 0xd2: + case 0xd3: + case 0xd4: + case 0xd5: + case 0xd6: + case 0xd7: + case 0xd8: + case 0xd9: + case 0xda: + case 0xdb: + case 0xe0: + case 0xe1: + case 0xe2: + case 0xe3: + case 0xe4: + case 0xe5: + case 0xe6: + case 0xe7: + case 0xe8: + case 0xe9: + case 0xea: + case 0xeb: + case 0xec: + case 0xed: + case 0xee: + case 0xef: + case 0xff: + insn = (inst >> 8) & 0xff; + extension = 0; + dispatch (insn, extension, 1); + break; + + /* Special cases where dm == dn is used to encode a different + instruction. */ + case 0x80: + case 0x85: + case 0x8a: + case 0x8f: + case 0x90: + case 0x95: + case 0x9a: + case 0x9f: + case 0xa0: + case 0xa5: + case 0xaa: + case 0xaf: + case 0xb0: + case 0xb5: + case 0xba: + case 0xbf: + insn = inst; + extension = 0; + dispatch (insn, extension, 2); + break; + + case 0x81: + case 0x82: + case 0x83: + case 0x84: + case 0x86: + case 0x87: + case 0x88: + case 0x89: + case 0x8b: + case 0x8c: + case 0x8d: + case 0x8e: + case 0x91: + case 0x92: + case 0x93: + case 0x94: + case 0x96: + case 0x97: + case 0x98: + case 0x99: + case 0x9b: + case 0x9c: + case 0x9d: + case 0x9e: + case 0xa1: + case 0xa2: + case 0xa3: + case 0xa4: + case 0xa6: + case 0xa7: + case 0xa8: + case 0xa9: + case 0xab: + case 0xac: + case 0xad: + case 0xae: + case 0xb1: + case 0xb2: + case 0xb3: + case 0xb4: + case 0xb6: + case 0xb7: + case 0xb8: + case 0xb9: + case 0xbb: + case 0xbc: + case 0xbd: + case 0xbe: + insn = (inst >> 8) & 0xff; + extension = 0; + dispatch (insn, extension, 1); + break; + + /* The two byte instructions. */ + case 0x20: + case 0x21: + case 0x22: + case 0x23: + case 0x28: + case 0x29: + case 0x2a: + case 0x2b: + case 0x42: + case 0x43: + case 0x46: + case 0x47: + case 0x4a: + case 0x4b: + case 0x4e: + case 0x4f: + case 0x58: + case 0x59: + case 0x5a: + case 0x5b: + case 0x5c: + case 0x5d: + case 0x5e: + case 0x5f: + case 0xc0: + case 0xc1: + case 0xc2: + case 0xc3: + case 0xc4: + case 0xc5: + case 0xc6: + case 0xc7: + case 0xc8: + case 0xc9: + case 0xca: + case 0xce: + case 0xcf: + case 0xf0: + case 0xf1: + case 0xf2: + case 0xf3: + case 0xf4: + case 0xf5: + case 0xf6: + insn = inst; + extension = 0; + dispatch (insn, extension, 2); + break; + + /* The three byte insns with a 16bit operand in little endian + format. */ + case 0x01: + case 0x02: + case 0x03: + case 0x05: + case 0x06: + case 0x07: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0d: + case 0x0e: + case 0x0f: + case 0x24: + case 0x25: + case 0x26: + case 0x27: + case 0x2c: + case 0x2d: + case 0x2e: + case 0x2f: + case 0x30: + case 0x31: + case 0x32: + case 0x33: + case 0x34: + case 0x35: + case 0x36: + case 0x37: + case 0x38: + case 0x39: + case 0x3a: + case 0x3b: + case 0xcc: + insn = load_byte (PC); + insn <<= 16; + insn |= load_half (PC + 1); + extension = 0; + dispatch (insn, extension, 3); + break; + + /* The three byte insns without 16bit operand. */ + case 0xde: + case 0xdf: + case 0xf8: + case 0xf9: + insn = load_mem_big (PC, 3); + extension = 0; + dispatch (insn, extension, 3); + break; + + /* Four byte insns. */ + case 0xfa: + case 0xfb: + if ((inst & 0xfffc) == 0xfaf0 + || (inst & 0xfffc) == 0xfaf4 + || (inst & 0xfffc) == 0xfaf8) + insn = load_mem_big (PC, 4); + else + { + insn = inst; + insn <<= 16; + insn |= load_half (PC + 2); + extension = 0; + } + dispatch (insn, extension, 4); + break; + + /* Five byte insns. */ + case 0xcd: + insn = load_byte (PC); + insn <<= 24; + insn |= (load_half (PC + 1) << 8); + insn |= load_byte (PC + 3); + extension = load_byte (PC + 4); + dispatch (insn, extension, 5); + break; + + case 0xdc: + insn = load_byte (PC); + insn <<= 24; + extension = load_word (PC + 1); + insn |= (extension & 0xffffff00) >> 8; + extension &= 0xff; + dispatch (insn, extension, 5); + break; + + /* Six byte insns. */ + case 0xfc: + case 0xfd: + insn = (inst << 16); + extension = load_word (PC + 2); + insn |= ((extension & 0xffff0000) >> 16); + extension &= 0xffff; + dispatch (insn, extension, 6); + break; + + case 0xdd: + insn = load_byte (PC) << 24; + extension = load_word (PC + 1); + insn |= ((extension >> 8) & 0xffffff); + extension = (extension & 0xff) << 16; + extension |= load_byte (PC + 5) << 8; + extension |= load_byte (PC + 6); + dispatch (insn, extension, 7); + break; + + case 0xfe: + insn = inst << 16; + extension = load_word (PC + 2); + insn |= ((extension >> 16) & 0xffff); + extension <<= 8; + extension &= 0xffff00; + extension |= load_byte (PC + 6); + dispatch (insn, extension, 7); + break; + + default: + abort (); + } + } + while (!State.exception); + +#ifdef HASH_STAT + { + int i; + for (i = 0; i < MAX_HASH; i++) + { + struct hash_entry *h; + h = &hash_table[i]; + + printf("hash 0x%x:\n", i); + + while (h) + { + printf("h->opcode = 0x%x, count = 0x%x\n", h->opcode, h->count); + h = h->next; + } + + printf("\n\n"); + } + fflush (stdout); + } +#endif + +} + +int +sim_trace (sd) + SIM_DESC sd; +{ +#ifdef DEBUG + mn10300_debug = DEBUG; +#endif + sim_resume (sd, 0, 0); + return 1; +} + +void +sim_info (sd, verbose) + SIM_DESC sd; + int verbose; +{ + (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_info\n"); +} + +SIM_RC +sim_create_inferior (sd, abfd, argv, env) + SIM_DESC sd; + struct _bfd *abfd; + char **argv; + char **env; +{ + if (abfd != NULL) + PC = bfd_get_start_address (abfd); + else + PC = 0; + return SIM_RC_OK; +} + +void +sim_set_callbacks (p) + host_callback *p; +{ + mn10300_callback = p; +} + +/* All the code for exiting, signals, etc needs to be revamped. + + This is enough to get c-torture limping though. */ + +void +sim_stop_reason (sd, reason, sigrc) + SIM_DESC sd; + enum sim_stop *reason; + int *sigrc; +{ + if (State.exited) + *reason = sim_exited; + else + *reason = sim_stopped; + + if (State.exception == SIGQUIT) + *sigrc = 0; + else + *sigrc = State.exception; +} + +int +sim_read (sd, addr, buffer, size) + SIM_DESC sd; + SIM_ADDR addr; + unsigned char *buffer; + int size; +{ + int i; + for (i = 0; i < size; i++) + buffer[i] = load_byte (addr + i); + + return size; +} + +void +sim_do_command (sd, cmd) + SIM_DESC sd; + char *cmd; +{ + (*mn10300_callback->printf_filtered) (mn10300_callback, "\"%s\" is not a valid mn10300 simulator command.\n", cmd); +} + +SIM_RC +sim_load (sd, prog, abfd, from_tty) + SIM_DESC sd; + char *prog; + bfd *abfd; + int from_tty; +{ + extern bfd *sim_load_file (); /* ??? Don't know where this should live. */ + bfd *prog_bfd; + + prog_bfd = sim_load_file (sd, myname, mn10300_callback, prog, abfd, + sim_kind == SIM_OPEN_DEBUG, + 0, sim_write); + if (prog_bfd == NULL) + return SIM_RC_FAIL; + if (abfd == NULL) + bfd_close (prog_bfd); + return SIM_RC_OK; +} +#endif /* not WITH_COMMON */ + + +#if WITH_COMMON + +/* For compatibility */ +SIM_DESC simulator; + +/* These default values correspond to expected usage for the chip. */ + +SIM_DESC +sim_open (kind, cb, abfd, argv) + SIM_OPEN_KIND kind; + host_callback *cb; + struct _bfd *abfd; + char **argv; +{ + SIM_DESC sd = sim_state_alloc (kind, cb); + mn10300_callback = cb; + + SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); + + /* for compatibility */ + simulator = sd; + + /* FIXME: should be better way of setting up interrupts. For + moment, only support watchpoints causing a breakpoint (gdb + halt). */ + STATE_WATCHPOINTS (sd)->pc = &(PC); + STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); + STATE_WATCHPOINTS (sd)->interrupt_handler = NULL; + STATE_WATCHPOINTS (sd)->interrupt_names = NULL; + + if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) + return 0; + sim_add_option_table (sd, NULL, mn10300_options); + + /* Allocate core managed memory */ + sim_do_command (sd, "memory region 0,0x100000"); + sim_do_command (sd, "memory region 0x40000000,0x200000"); + + /* getopt will print the error message so we just have to exit if this fails. + FIXME: Hmmm... in the case of gdb we need getopt to call + print_filtered. */ + if (sim_parse_args (sd, argv) != SIM_RC_OK) + { + /* Uninstall the modules to avoid memory leaks, + file descriptor leaks, etc. */ + sim_module_uninstall (sd); + return 0; + } + + if ( NULL != board + && (strcmp(board, BOARD_AM32) == 0 ) ) + { + /* environment */ + STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT; + + sim_do_command (sd, "memory region 0x44000000,0x40000"); + sim_do_command (sd, "memory region 0x48000000,0x400000"); + + /* device support for mn1030002 */ + /* interrupt controller */ + + sim_hw_parse (sd, "/mn103int@0x34000100/reg 0x34000100 0x7C 0x34000200 0x8 0x34000280 0x8"); + + /* DEBUG: NMI input's */ + sim_hw_parse (sd, "/glue@0x30000000/reg 0x30000000 12"); + sim_hw_parse (sd, "/glue@0x30000000 > int0 nmirq /mn103int"); + sim_hw_parse (sd, "/glue@0x30000000 > int1 watchdog /mn103int"); + sim_hw_parse (sd, "/glue@0x30000000 > int2 syserr /mn103int"); + + /* DEBUG: ACK input */ + sim_hw_parse (sd, "/glue@0x30002000/reg 0x30002000 4"); + sim_hw_parse (sd, "/glue@0x30002000 > int ack /mn103int"); + + /* DEBUG: LEVEL output */ + sim_hw_parse (sd, "/glue@0x30004000/reg 0x30004000 8"); + sim_hw_parse (sd, "/mn103int > nmi int0 /glue@0x30004000"); + sim_hw_parse (sd, "/mn103int > level int1 /glue@0x30004000"); + + /* DEBUG: A bunch of interrupt inputs */ + sim_hw_parse (sd, "/glue@0x30006000/reg 0x30006000 32"); + sim_hw_parse (sd, "/glue@0x30006000 > int0 irq-0 /mn103int"); + sim_hw_parse (sd, "/glue@0x30006000 > int1 irq-1 /mn103int"); + sim_hw_parse (sd, "/glue@0x30006000 > int2 irq-2 /mn103int"); + sim_hw_parse (sd, "/glue@0x30006000 > int3 irq-3 /mn103int"); + sim_hw_parse (sd, "/glue@0x30006000 > int4 irq-4 /mn103int"); + sim_hw_parse (sd, "/glue@0x30006000 > int5 irq-5 /mn103int"); + sim_hw_parse (sd, "/glue@0x30006000 > int6 irq-6 /mn103int"); + sim_hw_parse (sd, "/glue@0x30006000 > int7 irq-7 /mn103int"); + + /* processor interrupt device */ + + /* the device */ + sim_hw_parse (sd, "/mn103cpu@0x20000000"); + sim_hw_parse (sd, "/mn103cpu@0x20000000/reg 0x20000000 0x42"); + + /* DEBUG: ACK output wired upto a glue device */ + sim_hw_parse (sd, "/glue@0x20002000"); + sim_hw_parse (sd, "/glue@0x20002000/reg 0x20002000 4"); + sim_hw_parse (sd, "/mn103cpu > ack int0 /glue@0x20002000"); + + /* DEBUG: RESET/NMI/LEVEL wired up to a glue device */ + sim_hw_parse (sd, "/glue@0x20004000"); + sim_hw_parse (sd, "/glue@0x20004000/reg 0x20004000 12"); + sim_hw_parse (sd, "/glue@0x20004000 > int0 reset /mn103cpu"); + sim_hw_parse (sd, "/glue@0x20004000 > int1 nmi /mn103cpu"); + sim_hw_parse (sd, "/glue@0x20004000 > int2 level /mn103cpu"); + + /* REAL: The processor wired up to the real interrupt controller */ + sim_hw_parse (sd, "/mn103cpu > ack ack /mn103int"); + sim_hw_parse (sd, "/mn103int > level level /mn103cpu"); + sim_hw_parse (sd, "/mn103int > nmi nmi /mn103cpu"); + + + /* PAL */ + + /* the device */ + sim_hw_parse (sd, "/pal@0x31000000"); + sim_hw_parse (sd, "/pal@0x31000000/reg 0x31000000 64"); + sim_hw_parse (sd, "/pal@0x31000000/poll? true"); + + /* DEBUG: PAL wired up to a glue device */ + sim_hw_parse (sd, "/glue@0x31002000"); + sim_hw_parse (sd, "/glue@0x31002000/reg 0x31002000 16"); + sim_hw_parse (sd, "/pal@0x31000000 > countdown int0 /glue@0x31002000"); + sim_hw_parse (sd, "/pal@0x31000000 > timer int1 /glue@0x31002000"); + sim_hw_parse (sd, "/pal@0x31000000 > int int2 /glue@0x31002000"); + sim_hw_parse (sd, "/glue@0x31002000 > int0 int3 /glue@0x31002000"); + sim_hw_parse (sd, "/glue@0x31002000 > int1 int3 /glue@0x31002000"); + sim_hw_parse (sd, "/glue@0x31002000 > int2 int3 /glue@0x31002000"); + + /* REAL: The PAL wired up to the real interrupt controller */ + sim_hw_parse (sd, "/pal@0x31000000 > countdown irq-0 /mn103int"); + sim_hw_parse (sd, "/pal@0x31000000 > timer irq-1 /mn103int"); + sim_hw_parse (sd, "/pal@0x31000000 > int irq-2 /mn103int"); + + /* 8 and 16 bit timers */ + sim_hw_parse (sd, "/mn103tim@0x34001000/reg 0x34001000 36 0x34001080 100 0x34004000 16"); + + /* Hook timer interrupts up to interrupt controller */ + sim_hw_parse (sd, "/mn103tim > timer-0-underflow timer-0-underflow /mn103int"); + sim_hw_parse (sd, "/mn103tim > timer-1-underflow timer-1-underflow /mn103int"); + sim_hw_parse (sd, "/mn103tim > timer-2-underflow timer-2-underflow /mn103int"); + sim_hw_parse (sd, "/mn103tim > timer-3-underflow timer-3-underflow /mn103int"); + sim_hw_parse (sd, "/mn103tim > timer-4-underflow timer-4-underflow /mn103int"); + sim_hw_parse (sd, "/mn103tim > timer-5-underflow timer-5-underflow /mn103int"); + sim_hw_parse (sd, "/mn103tim > timer-6-underflow timer-6-underflow /mn103int"); + sim_hw_parse (sd, "/mn103tim > timer-6-compare-a timer-6-compare-a /mn103int"); + sim_hw_parse (sd, "/mn103tim > timer-6-compare-b timer-6-compare-b /mn103int"); + + + /* Serial devices 0,1,2 */ + sim_hw_parse (sd, "/mn103ser@0x34000800/reg 0x34000800 48"); + sim_hw_parse (sd, "/mn103ser@0x34000800/poll? true"); + + /* Hook serial interrupts up to interrupt controller */ + sim_hw_parse (sd, "/mn103ser > serial-0-receive serial-0-receive /mn103int"); + sim_hw_parse (sd, "/mn103ser > serial-0-transmit serial-0-transmit /mn103int"); + sim_hw_parse (sd, "/mn103ser > serial-1-receive serial-1-receive /mn103int"); + sim_hw_parse (sd, "/mn103ser > serial-1-transmit serial-1-transmit /mn103int"); + sim_hw_parse (sd, "/mn103ser > serial-2-receive serial-2-receive /mn103int"); + sim_hw_parse (sd, "/mn103ser > serial-2-transmit serial-2-transmit /mn103int"); + + sim_hw_parse (sd, "/mn103iop@0x36008000/reg 0x36008000 8 0x36008020 8 0x36008040 0xc 0x36008060 8 0x36008080 8"); + + /* Memory control registers */ + sim_do_command (sd, "memory region 0x32000020,0x30"); + /* Cache control register */ + sim_do_command (sd, "memory region 0x20000070,0x4"); + /* Cache purge regions */ + sim_do_command (sd, "memory region 0x28400000,0x800"); + sim_do_command (sd, "memory region 0x28401000,0x800"); + /* DMA registers */ + sim_do_command (sd, "memory region 0x32000100,0xF"); + sim_do_command (sd, "memory region 0x32000200,0xF"); + sim_do_command (sd, "memory region 0x32000400,0xF"); + sim_do_command (sd, "memory region 0x32000800,0xF"); + } + else + { + if (board != NULL) + { + sim_io_eprintf (sd, "Error: Board `%s' unknown.\n", board); + return 0; + } + } + + + + /* check for/establish the a reference program image */ + if (sim_analyze_program (sd, + (STATE_PROG_ARGV (sd) != NULL + ? *STATE_PROG_ARGV (sd) + : NULL), + abfd) != SIM_RC_OK) + { + sim_module_uninstall (sd); + return 0; + } + + /* establish any remaining configuration options */ + if (sim_config (sd) != SIM_RC_OK) + { + sim_module_uninstall (sd); + return 0; + } + + if (sim_post_argv_init (sd) != SIM_RC_OK) + { + /* Uninstall the modules to avoid memory leaks, + file descriptor leaks, etc. */ + sim_module_uninstall (sd); + return 0; + } + + + /* set machine specific configuration */ +/* STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT */ +/* | PSW_CY | PSW_OV | PSW_S | PSW_Z); */ + + return sd; +} + + +void +sim_close (sd, quitting) + SIM_DESC sd; + int quitting; +{ + sim_module_uninstall (sd); +} + + +SIM_RC +sim_create_inferior (sd, prog_bfd, argv, env) + SIM_DESC sd; + struct _bfd *prog_bfd; + char **argv; + char **env; +{ + memset (&State, 0, sizeof (State)); + if (prog_bfd != NULL) { + PC = bfd_get_start_address (prog_bfd); + } else { + PC = 0; + } + CIA_SET (STATE_CPU (sd, 0), (unsigned64) PC); + + return SIM_RC_OK; +} + +void +sim_do_command (sd, cmd) + SIM_DESC sd; + char *cmd; +{ + char *mm_cmd = "memory-map"; + char *int_cmd = "interrupt"; + + if (sim_args_command (sd, cmd) != SIM_RC_OK) + { + if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0)) + sim_io_eprintf (sd, "`memory-map' command replaced by `sim memory'\n"); + else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0) + sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n"); + else + sim_io_eprintf (sd, "Unknown command `%s'\n", cmd); + } +} +#endif /* WITH_COMMON */ + +/* FIXME These would more efficient to use than load_mem/store_mem, + but need to be changed to use the memory map. */ + +uint8 +get_byte (x) + uint8 *x; +{ + return *x; +} + +uint16 +get_half (x) + uint8 *x; +{ + uint8 *a = x; + return (a[1] << 8) + (a[0]); +} + +uint32 +get_word (x) + uint8 *x; +{ + uint8 *a = x; + return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]); +} + +void +put_byte (addr, data) + uint8 *addr; + uint8 data; +{ + uint8 *a = addr; + a[0] = data; +} + +void +put_half (addr, data) + uint8 *addr; + uint16 data; +{ + uint8 *a = addr; + a[0] = data & 0xff; + a[1] = (data >> 8) & 0xff; +} + +void +put_word (addr, data) + uint8 *addr; + uint32 data; +{ + uint8 *a = addr; + a[0] = data & 0xff; + a[1] = (data >> 8) & 0xff; + a[2] = (data >> 16) & 0xff; + a[3] = (data >> 24) & 0xff; +} + +int +sim_fetch_register (sd, rn, memory, length) + SIM_DESC sd; + int rn; + unsigned char *memory; + int length; +{ + put_word (memory, State.regs[rn]); + return -1; +} + +int +sim_store_register (sd, rn, memory, length) + SIM_DESC sd; + int rn; + unsigned char *memory; + int length; +{ + State.regs[rn] = get_word (memory); + return -1; +} + + +void +mn10300_core_signal (SIM_DESC sd, + sim_cpu *cpu, + sim_cia cia, + unsigned map, + int nr_bytes, + address_word addr, + transfer_type transfer, + sim_core_signals sig) +{ + const char *copy = (transfer == read_transfer ? "read" : "write"); + address_word ip = CIA_ADDR (cia); + + switch (sig) + { + case sim_core_unmapped_signal: + sim_io_eprintf (sd, "mn10300-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n", + nr_bytes, copy, + (unsigned long) addr, (unsigned long) ip); + program_interrupt(sd, cpu, cia, SIM_SIGSEGV); + break; + + case sim_core_unaligned_signal: + sim_io_eprintf (sd, "mn10300-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n", + nr_bytes, copy, + (unsigned long) addr, (unsigned long) ip); + program_interrupt(sd, cpu, cia, SIM_SIGBUS); + break; + + default: + sim_engine_abort (sd, cpu, cia, + "mn10300_core_signal - internal error - bad switch"); + } +} + + +void +program_interrupt (SIM_DESC sd, + sim_cpu *cpu, + sim_cia cia, + SIM_SIGNAL sig) +{ + int status; + struct hw *device; + static int in_interrupt = 0; + +#ifdef SIM_CPU_EXCEPTION_TRIGGER + SIM_CPU_EXCEPTION_TRIGGER(sd,cpu,cia); +#endif + + /* avoid infinite recursion */ + if (in_interrupt) + { + (*mn10300_callback->printf_filtered) (mn10300_callback, + "ERROR: recursion in program_interrupt during software exception dispatch."); + } + else + { + in_interrupt = 1; + /* copy NMI handler code from dv-mn103cpu.c */ + store_word (SP - 4, CIA_GET (cpu)); + store_half (SP - 8, PSW); + + /* Set the SYSEF flag in NMICR by backdoor method. See + dv-mn103int.c:write_icr(). This is necessary because + software exceptions are not modelled by actually talking to + the interrupt controller, so it cannot set its own SYSEF + flag. */ + if ((NULL != board) && (strcmp(board, BOARD_AM32) == 0)) + store_byte (0x34000103, 0x04); + } + + PSW &= ~PSW_IE; + SP = SP - 8; + CIA_SET (cpu, 0x40000008); + + in_interrupt = 0; + sim_engine_halt(sd, cpu, NULL, cia, sim_stopped, sig); +} + + +void +mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia) +{ + ASSERT(cpu != NULL); + + if(State.exc_suspended > 0) + sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", State.exc_suspended); + + CIA_SET (cpu, cia); + memcpy(State.exc_trigger_regs, State.regs, sizeof(State.exc_trigger_regs)); + State.exc_suspended = 0; +} + +void +mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception) +{ + ASSERT(cpu != NULL); + + if(State.exc_suspended > 0) + sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n", + State.exc_suspended, exception); + + memcpy(State.exc_suspend_regs, State.regs, sizeof(State.exc_suspend_regs)); + memcpy(State.regs, State.exc_trigger_regs, sizeof(State.regs)); + CIA_SET (cpu, PC); /* copy PC back from new State.regs */ + State.exc_suspended = exception; +} + +void +mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception) +{ + ASSERT(cpu != NULL); + + if(exception == 0 && State.exc_suspended > 0) + { + if(State.exc_suspended != SIGTRAP) /* warn not for breakpoints */ + sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n", + State.exc_suspended); + } + else if(exception != 0 && State.exc_suspended > 0) + { + if(exception != State.exc_suspended) + sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n", + State.exc_suspended, exception); + + memcpy(State.regs, State.exc_suspend_regs, sizeof(State.regs)); + CIA_SET (cpu, PC); /* copy PC back from new State.regs */ + } + else if(exception != 0 && State.exc_suspended == 0) + { + sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception); + } + State.exc_suspended = 0; +}

interp.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: Makefile.in =================================================================== --- Makefile.in (nonexistent) +++ Makefile.in (revision 1765) @@ -0,0 +1,159 @@ +# Makefile template for Configure for the mn10300 sim library. +# Copyright (C) 1996, 1997, 2000, 2001 Free Software Foundation, Inc. +# Written by Cygnus Support. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +## COMMON_PRE_CONFIG_FRAG + +WITHOUT_COMMON_OBJS = table.o simops.o sim-load.o +WITHOUT_COMMON_INTERP_DEP = table.c +WITH_COMMON_OBJS = \ + itable.o semantics.o idecode.o icache.o engine.o irun.o support.o \ + $(SIM_NEW_COMMON_OBJS) \ + op_utils.o \ + sim-engine.o \ + sim-hload.o \ + sim-hrw.o \ + sim-resume.o \ + sim-reason.o \ + sim-stop.o \ + dv-sockser.o +WITH_COMMON_INTERP_DEP = + +MN10300_OBJS = $(@mn10300_common@_COMMON_OBJS) +MN10300_INTERP_DEP = $(@mn10300_common@_COMMON_INTERP_DEP) + +SIM_OBJS = $(MN10300_OBJS) interp.o + +# List of main object files for `run'. +WITHOUT_COMMON_RUN_OBJS = run.o +WITH_COMMON_RUN_OBJS = nrun.o +SIM_RUN_OBJS = $(@mn10300_common@_COMMON_RUN_OBJS) + +SIM_EXTRA_CLEAN = clean-extra + +# Select mn10300 support in nltvals.def. +NL_TARGET = -DNL_TARGET_mn10300 + +INCLUDE = mn10300_sim.h $(srcdir)/../../include/callback.h + +# List of extra flags to always pass to $(CC). +SIM_EXTRA_CFLAGS = @sim_gen@ -DPOLL_QUIT_INTERVAL=0x20 + +## COMMON_POST_CONFIG_FRAG + + +# +# Old generator (default) +# + +simops.h: gencode + ./gencode -h >$@ + +table.c: gencode simops.h + ./gencode >$@ + +gencode.o: gencode.c $(INCLUDE) + $(CC_FOR_BUILD) $(BUILD_CFLAGS) -c $(srcdir)/gencode.c + +m10300-opc.o: $(srcdir)/../../opcodes/m10300-opc.c + $(CC_FOR_BUILD) $(BUILD_CFLAGS) -c $(srcdir)/../../opcodes/m10300-opc.c + +gencode: gencode.o m10300-opc.o + $(CC_FOR_BUILD) $(BUILD_CFLAGS) -o gencode gencode.o m10300-opc.o $(BUILD_LIB) + +idecode.o op_utils.o semantics.o simops.o: targ-vals.h + + +BUILT_SRC_FROM_IGEN = \ + icache.h \ + icache.c \ + idecode.h \ + idecode.c \ + semantics.h \ + semantics.c \ + model.h \ + model.c \ + support.h \ + support.c \ + itable.h \ + itable.c \ + engine.h \ + engine.c \ + irun.c +$(BUILT_SRC_FROM_IGEN): tmp-igen + + +.PHONY: clean-igen +clean-igen: + rm -f $(BUILT_SRC_FROM_IGEN) + rm -f tmp-igen tmp-insns + +../igen/igen: + cd ../igen && $(MAKE) + +IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries +IGEN_INSN=$(srcdir)/mn10300.igen $(srcdir)/am33.igen +IGEN_DC=$(srcdir)/mn10300.dc +tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen + cd ../igen && $(MAKE) + ../igen/igen \ + $(IGEN_TRACE) \ + -G gen-direct-access \ + -M mn10300,am33 -G gen-multi-sim=am33 \ + -I $(srcdir) \ + -i $(IGEN_INSN) \ + -o $(IGEN_DC) \ + -x \ + -n icache.h -hc tmp-icache.h \ + -n icache.c -c tmp-icache.c \ + -n semantics.h -hs tmp-semantics.h \ + -n semantics.c -s tmp-semantics.c \ + -n idecode.h -hd tmp-idecode.h \ + -n idecode.c -d tmp-idecode.c \ + -n model.h -hm tmp-model.h \ + -n model.c -m tmp-model.c \ + -n support.h -hf tmp-support.h \ + -n support.c -f tmp-support.c \ + -n itable.h -ht tmp-itable.h \ + -n itable.c -t tmp-itable.c \ + -n engine.h -he tmp-engine.h \ + -n engine.c -e tmp-engine.c \ + -n irun.c -r tmp-irun.c + $(SHELL) $(srcdir)/../../move-if-change tmp-icache.h icache.h + $(SHELL) $(srcdir)/../../move-if-change tmp-icache.c icache.c + $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.h idecode.h + $(SHELL) $(srcdir)/../../move-if-change tmp-idecode.c idecode.c + $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.h semantics.h + $(SHELL) $(srcdir)/../../move-if-change tmp-semantics.c semantics.c + $(SHELL) $(srcdir)/../../move-if-change tmp-model.h model.h + $(SHELL) $(srcdir)/../../move-if-change tmp-model.c model.c + $(SHELL) $(srcdir)/../../move-if-change tmp-support.h support.h + $(SHELL) $(srcdir)/../../move-if-change tmp-support.c support.c + $(SHELL) $(srcdir)/../../move-if-change tmp-itable.h itable.h + $(SHELL) $(srcdir)/../../move-if-change tmp-itable.c itable.c + $(SHELL) $(srcdir)/../../move-if-change tmp-engine.h engine.h + $(SHELL) $(srcdir)/../../move-if-change tmp-engine.c engine.c + $(SHELL) $(srcdir)/../../move-if-change tmp-irun.c irun.c + touch tmp-igen + + +interp.o: interp.c $(MN10300_INTERP_DEP) $(INCLUDE) +simops.o: simops.c simops.h $(INCLUDE) +table.o: table.c + +clean-extra: clean-igen + rm -f table.c simops.h gencode

Makefile.in Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mn10300.dc =================================================================== --- mn10300.dc (nonexistent) +++ mn10300.dc (revision 1765) @@ -0,0 +1,4 @@ +switch : 7 : 0 : : : : 0 : : +switch : 7 : 0 : : : : 1 : : +switch : 7 : 0 : : : : 2 : : +switch : 7 : 0 : : : : 3 : :

mn10300.dc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: am33.igen =================================================================== --- am33.igen (nonexistent) +++ am33.igen (revision 1765) @@ -0,0 +1,8676 @@ +// Helper: +// +// Given an extended register number, translate it into an index into the +// register array. This is necessary as the upper 8 extended registers are +// actually synonyms for the d0-d3/a0-a3 registers. +// +// + +:function:::int:translate_rreg:int rreg +{ + + /* The higher register numbers actually correspond to the + basic machine's address and data registers. */ + if (rreg > 7 && rreg < 12) + return REG_A0 + rreg - 8; + else if (rreg > 11 && rreg < 16) + return REG_D0 + rreg - 12; + else + return REG_E0 + rreg; +} + +:function:::int:translate_xreg:int xreg +{ + switch (xreg) + { + case 0: + return REG_SP; + case 1: + return REG_MDRQ; + case 2: + return REG_MCRH; + case 3: + return REG_MCRL; + case 4: + return REG_MCVF; + default: + abort (); + } +} + +// 1111 0000 0010 00An; mov USP,An +8.0xf0+4.0x2,00,2.AN0:D0m:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_A0 + AN0] = State.regs[REG_USP]; +} + + +// 1111 0000 0010 01An; mov SSP,An +8.0xf0+4.0x2,01,2.AN0:D0n:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_A0 + AN0] = State.regs[REG_SSP]; +} + + +// 1111 0000 0010 10An; mov MSP,An +8.0xf0+4.0x2,10,2.AN0:D0o:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_A0 + AN0] = State.regs[REG_MSP]; +} + + +// 1111 0000 0010 11An; mov PC,An +8.0xf0+4.0x2,11,2.AN0:D0p:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_A0 + AN0] = PC; +} + + +// 1111 0000 0011 Am00; mov Am,USP +8.0xf0+4.0x3,2.AM1,00:D0q:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_USP] = State.regs[REG_A0 + AM1]; +} + +// 1111 0000 0011 Am01; mov Am,SSP +8.0xf0+4.0x3,2.AM1,01:D0r:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_SSP] = State.regs[REG_A0 + AM1]; +} + +// 1111 0000 0011 Am10; mov Am,MSP +8.0xf0+4.0x3,2.AM1,10:D0s:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_MSP] = State.regs[REG_A0 + AM1]; +} + + +// 1111 0000 1110 imm4; syscall +8.0xf0+4.0xe,IMM4:D0t:::syscall +"syscall" +*am33 +{ + unsigned32 sp, next_pc; + + PC = cia; + sp = State.regs[REG_SP]; + next_pc = State.regs[REG_PC] + 2; + store_word (sp - 4, next_pc); + store_word (sp - 8, PSW); + State.regs[REG_PC] = 0x40000000 + IMM4 * 8; + nia = PC; +} + + +// 1111 0010 1110 11Dn; mov EPSW,Dn +8.0xf2+4.0xe,11,2.DN0:D0u:::mov +"mov" +*am33 +{ + PC = cia; + State.regs[REG_D0 + DN0] = PSW; +} + + +// 1111 0010 1111 Dm01; mov Dm,EPSW +8.0xf2+4.0xf,2.DM1,01:D0v:::mov +"mov" +*am33 +{ + PC = cia; + PSW = State.regs[REG_D0 + DM1]; +} + +// 1111 0101 00Am Rn; mov Am,Rn +8.0xf5+00,2.AM1,4.RN0:D0w:::mov +"mov" +*am33 +{ + int destreg = translate_rreg (SD_, RN0); + + PC = cia; + State.regs[destreg] = State.regs[REG_A0 + AM1]; +} + +// 1111 0101 01Dm Rn; mov Dm,Rn +8.0xf5+01,2.DM1,4.RN0:D0x:::mov +"mov" +*am33 +{ + int destreg = translate_rreg (SD_, RN0); + + PC = cia; + State.regs[destreg] = State.regs[REG_D0 + DM1]; +} + +// 1111 0101 10Rm An; mov Rm,An +8.0xf5+10,4.RM1,2.AN0:D0y:::mov +"mov" +*am33 +{ + int destreg = translate_rreg (SD_, RM1); + + PC = cia; + State.regs[REG_A0 + AN0] = State.regs[destreg]; +} + +// 1111 0101 11Rm Dn; mov Rm,Dn +8.0xf5+11,4.RM1,2.DN0:D0z:::mov +"mov" +*am33 +{ + int destreg = translate_rreg (SD_, RM1); + + PC = cia; + State.regs[REG_D0 + DN0] = State.regs[destreg]; +} + + +// 1111 1000 1100 1110 regs....; movm (USP),regs +8.0xf8+8.0xce+8.REGS:D1a:::movm +"movm" +*am33 +{ + unsigned32 usp = State.regs[REG_USP]; + unsigned32 mask; + + PC = cia; + mask = REGS; + + if (mask & 0x8) + { + usp += 4; + State.regs[REG_LAR] = load_word (usp); + usp += 4; + State.regs[REG_LIR] = load_word (usp); + usp += 4; + State.regs[REG_MDR] = load_word (usp); + usp += 4; + State.regs[REG_A0 + 1] = load_word (usp); + usp += 4; + State.regs[REG_A0] = load_word (usp); + usp += 4; + State.regs[REG_D0 + 1] = load_word (usp); + usp += 4; + State.regs[REG_D0] = load_word (usp); + usp += 4; + } + + if (mask & 0x10) + { + State.regs[REG_A0 + 3] = load_word (usp); + usp += 4; + } + + if (mask & 0x20) + { + State.regs[REG_A0 + 2] = load_word (usp); + usp += 4; + } + + if (mask & 0x40) + { + State.regs[REG_D0 + 3] = load_word (usp); + usp += 4; + } + + if (mask & 0x80) + { + State.regs[REG_D0 + 2] = load_word (usp); + usp += 4; + } + + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33 + ) + { + if (mask & 0x1) + { + /* Need to restore MDQR, MCRH, MCRL, and MCVF */ + usp += 16; + State.regs[REG_E0 + 1] = load_word (usp); + usp += 4; + State.regs[REG_E0 + 0] = load_word (usp); + usp += 4; + } + + if (mask & 0x2) + { + State.regs[REG_E0 + 7] = load_word (usp); + usp += 4; + State.regs[REG_E0 + 6] = load_word (usp); + usp += 4; + State.regs[REG_E0 + 5] = load_word (usp); + usp += 4; + State.regs[REG_E0 + 4] = load_word (usp); + usp += 4; + } + + if (mask & 0x4) + { + State.regs[REG_E0 + 3] = load_word (usp); + usp += 4; + State.regs[REG_E0 + 2] = load_word (usp); + usp += 4; + } + } + + /* And make sure to update the stack pointer. */ + State.regs[REG_USP] = usp; +} + +// 1111 1000 1100 1111 regs....; movm (USP),regs +8.0xf8+8.0xcf+8.REGS:D1b:::movm +"movm" +*am33 +{ + unsigned32 usp = State.regs[REG_USP]; + unsigned32 mask; + + PC = cia; + mask = REGS; + + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33 + ) + { + if (mask & 0x4) + { + usp -= 4; + store_word (usp, State.regs[REG_E0 + 2]); + usp -= 4; + store_word (usp, State.regs[REG_E0 + 3]); + } + + if (mask & 0x2) + { + usp -= 4; + store_word (usp, State.regs[REG_E0 + 4]); + usp -= 4; + store_word (usp, State.regs[REG_E0 + 5]); + usp -= 4; + store_word (usp, State.regs[REG_E0 + 6]); + usp -= 4; + store_word (usp, State.regs[REG_E0 + 7]); + } + + if (mask & 0x1) + { + usp -= 4; + store_word (usp, State.regs[REG_E0 + 0]); + usp -= 4; + store_word (usp, State.regs[REG_E0 + 1]); + usp -= 16; + /* Need to save MDQR, MCRH, MCRL, and MCVF */ + } + } + + if (mask & 0x80) + { + usp -= 4; + store_word (usp, State.regs[REG_D0 + 2]); + } + + if (mask & 0x40) + { + usp -= 4; + store_word (usp, State.regs[REG_D0 + 3]); + } + + if (mask & 0x20) + { + usp -= 4; + store_word (usp, State.regs[REG_A0 + 2]); + } + + if (mask & 0x10) + { + usp -= 4; + store_word (usp, State.regs[REG_A0 + 3]); + } + + if (mask & 0x8) + { + usp -= 4; + store_word (usp, State.regs[REG_D0]); + usp -= 4; + store_word (usp, State.regs[REG_D0 + 1]); + usp -= 4; + store_word (usp, State.regs[REG_A0]); + usp -= 4; + store_word (usp, State.regs[REG_A0 + 1]); + usp -= 4; + store_word (usp, State.regs[REG_MDR]); + usp -= 4; + store_word (usp, State.regs[REG_LIR]); + usp -= 4; + store_word (usp, State.regs[REG_LAR]); + usp -= 4; + } + + /* And make sure to update the stack pointer. */ + State.regs[REG_USP] = usp; +} + +// 1111 1100 1111 1100 imm32...; and imm32,EPSW +8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and +"and" +*am33 +{ + PC = cia; + PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); +} + +// 1111 1100 1111 1101 imm32...; or imm32,EPSW +8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or +"or" +*am33 +{ + PC = cia; + PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); +} + +// 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn) +8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = State.regs[srcreg]; +} + +// 1111 1001 0001 1000 Rn Rn; ext Rn +8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext +"mov" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + if (State.regs[srcreg] & 0x80000000) + State.regs[REG_MDR] = -1; + else + State.regs[REG_MDR] = 0; +} + +// 1111 1001 0010 1000 Rm Rn; extb Rm,Rn +8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb +"extb" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = EXTEND8 (State.regs[srcreg]); +} + +// 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn +8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu +"extbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = State.regs[srcreg] & 0xff; +} + +// 1111 1001 0100 1000 Rm Rn; exth Rm,Rn +8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth +"exth" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = EXTEND16 (State.regs[srcreg]); +} + +// 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn +8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu +"exthu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = State.regs[srcreg] & 0xffff; +} + +// 1111 1001 0110 1000 Rn Rn; clr Rn +8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr +"clr" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = 0; + PSW |= PSW_Z; + PSW &= ~(PSW_V | PSW_C | PSW_N); +} + +// 1111 1001 0111 1000 Rm Rn; add Rm,Rn +8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add +"add" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + genericAdd (State.regs[srcreg], dstreg); +} + +// 1111 1001 1000 1000 Rm Rn; addc Rm,Rn +8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc +"addc" +*am33 +{ + int srcreg, dstreg; + int z, c, n, v; + unsigned32 reg1, reg2, sum; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + reg1 = State.regs[srcreg]; + reg2 = State.regs[dstreg]; + sum = reg1 + reg2 + ((PSW & PSW_C) != 0); + State.regs[dstreg] = sum; + + z = ((PSW & PSW_Z) != 0) && (sum == 0); + n = (sum & 0x80000000); + c = (sum < reg1) || (sum < reg2); + v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (sum & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1001 1001 1000 Rm Rn; sub Rm,Rn +8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub +"sub" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + genericSub (State.regs[srcreg], dstreg); +} + +// 1111 1001 1010 1000 Rm Rn; subc Rm,Rn +8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc +"subc" +*am33 +{ + int srcreg, dstreg; + int z, c, n, v; + unsigned32 reg1, reg2, difference; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + reg1 = State.regs[srcreg]; + reg2 = State.regs[dstreg]; + difference = reg2 - reg1 - ((PSW & PSW_C) != 0); + State.regs[dstreg] = difference; + + z = ((PSW & PSW_Z) != 0) && (difference == 0); + n = (difference & 0x80000000); + c = (reg1 > reg2); + v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (difference & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1001 1011 1000 Rn Rn; inc Rn +8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc +"inc" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + genericAdd (1, dstreg); +} + +// 1111 1001 1101 1000 Rn Rn; inc Rn +8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4 +"inc4" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + genericAdd (4, dstreg); +} + +// 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn +8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp +"cmp" +*am33 +{ + int srcreg1, srcreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RN0); + srcreg2 = translate_rreg (SD_, RM2); + genericCmp (State.regs[srcreg2], State.regs[srcreg1]); +} + +// 1111 1001 1110 1000 XRm Rn; mov XRm,Rn +8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov +"mov" +*am33 +{ + int dstreg, srcreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + srcreg = translate_xreg (SD_, XRM2); + + State.regs[dstreg] = State.regs[srcreg]; +} + +// 1111 1001 1111 1000 Rm XRn; mov Rm,XRn +8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_xreg (SD_, XRN0); + + State.regs[dstreg] = State.regs[srcreg]; +} + +// 1111 1001 0000 1001 Rm Rn; and Rm,Rn +8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and +"and" +*am33 +{ + int srcreg, dstreg; + int z, n; + + PC = cia; + + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] &= State.regs[srcreg]; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 0001 1001 Rm Rn; or Rm,Rn +8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or +"or" +*am33 +{ + int srcreg, dstreg; + int z, n; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] |= State.regs[srcreg]; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 0010 1001 Rm Rn; xor Rm,Rn +8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor +"xor" +*am33 +{ + int srcreg, dstreg; + int z, n; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] ^= State.regs[srcreg]; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 0011 1001 Rn Rn; not Rn +8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not +"not" +*am33 +{ + int dstreg; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] = ~State.regs[dstreg]; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 0100 1001 Rm Rn; asr Rm,Rn +8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr +"asr" +*am33 +{ + int srcreg, dstreg; + signed32 temp; + int c, z, n; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = State.regs[dstreg]; + c = temp & 1; + temp >>= State.regs[srcreg]; + State.regs[dstreg] = temp; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn +8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr +"lsr" +*am33 +{ + int srcreg, dstreg; + int z, n, c; + + PC = cia; + + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + c = State.regs[dstreg] & 1; + State.regs[dstreg] >>= State.regs[srcreg]; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1001 0110 1001 Rm Rn; asl Rm,Rn +8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl +"asl" +*am33 +{ + int srcreg, dstreg; + int z, n; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] <<= State.regs[srcreg]; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 0111 1001 Rn Rn; asl2 Rn +8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2 +"asl2" +*am33 +{ + int dstreg; + int n, z; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] <<= 2; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 1000 1001 Rn Rn; ror Rn +8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror +"ror" +*am33 +{ + int dstreg; + int c, n, z; + unsigned32 value; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + value = State.regs[dstreg]; + c = (value & 0x1); + + value >>= 1; + value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0; + State.regs[dstreg] = value; + z = (value == 0); + n = (value & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1001 1001 1001 Rn Rn; rol Rn +8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol +"rol" +*am33 +{ + int dstreg; + int c, n, z; + unsigned32 value; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + value = State.regs[dstreg]; + c = (value & 0x80000000) ? 1 : 0; + + value <<= 1; + value |= ((PSW & PSW_C) != 0); + State.regs[dstreg] = value; + z = (value == 0); + n = (value & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1001 1010 1001 Rm Rn; mul Rm,Rn +8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul +"mul" +*am33 +{ + int srcreg, dstreg; + unsigned64 temp; + int n, z; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = ((signed64)(signed32)State.regs[dstreg] + * (signed64)(signed32)State.regs[srcreg]); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn +8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu +"mulu" +*am33 +{ + int srcreg, dstreg; + unsigned64 temp; + int n, z; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = ((unsigned64)State.regs[dstreg] + * (unsigned64)State.regs[srcreg]); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 1100 1001 Rm Rn; div Rm,Rn +8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div +"div" +*am33 +{ + int srcreg, dstreg; + signed64 temp; + int n, z; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = State.regs[REG_MDR]; + temp <<= 32; + temp |= State.regs[dstreg]; + State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg]; + temp /= (signed32)State.regs[srcreg]; + State.regs[dstreg] = temp & 0xffffffff; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 1101 1001 Rm Rn; divu Rm,Rn +8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu +"divu" +*am33 +{ + int srcreg, dstreg; + unsigned64 temp; + int n, z; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = State.regs[REG_MDR]; + temp <<= 32; + temp |= State.regs[dstreg]; + State.regs[REG_MDR] = temp % State.regs[srcreg]; + temp /= State.regs[srcreg]; + State.regs[dstreg] = temp & 0xffffffff; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + + +// 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn +8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg]); +} + +// 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn) +8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg], State.regs[srcreg]); +} + +// 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn +8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[srcreg]); +} + +// 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn) +8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_byte (State.regs[dstreg], State.regs[srcreg]); +} + +// 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn +8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg]); +} + +// 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn) +8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg], State.regs[srcreg]); +} + +// 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn +8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += 4; +} + +// 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+) +8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg], State.regs[srcreg]); + State.regs[dstreg] += 4; +} + +// 1111 1001 1000 1010 Rn 0000; mov (sp),Rn +8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[REG_SP]); +} + +// 1111 1001 1001 1010 Rm 0000; mov Rm, (sp) +8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov +"mov" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_word (State.regs[REG_SP], State.regs[srcreg]); +} + +// 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn +8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu +"movbu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[REG_SP]); +} + +// 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp) +8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu +"movbu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_byte (State.regs[REG_SP], State.regs[srcreg]); +} + +// 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn +8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu +"movhu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[REG_SP]); +} + +// 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp) +8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu +"movhu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_half (State.regs[REG_SP], State.regs[srcreg]); +} + +// 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn +8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg]); + State.regs[srcreg] += 2; +} + +// 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+) +8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg], State.regs[srcreg]); + State.regs[dstreg] += 2; +} + + +// 1111 1001 0000 1011 Rm Rn; mac Rm,Rn +8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac +"mac" +*am33 +{ + int srcreg1, srcreg2; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((signed64)(signed32)State.regs[srcreg2] + * (signed64)(signed32)State.regs[srcreg1]); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 0001 1011 Rm Rn; macu Rm,Rn +8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu +"macu" +*am33 +{ + int srcreg1, srcreg2; + unsigned64 temp, sum; + int c, v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((unsigned64)State.regs[srcreg2] + * (unsigned64)State.regs[srcreg1]); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 0010 1011 Rm Rn; macb Rm,Rn +8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb +"macb" +*am33 +{ + int srcreg1, srcreg2; + signed32 temp, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff) + * (signed32)(signed8)(State.regs[srcreg1] & 0xff)); + sum = State.regs[REG_MCRL] + temp; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn +8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu +"macbu" +*am33 +{ + int srcreg1, srcreg2; + signed64 temp, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((unsigned32)(State.regs[srcreg2] & 0xff) + * (unsigned32)(State.regs[srcreg1] & 0xff)); + sum = State.regs[REG_MCRL] + temp; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 0100 1011 Rm Rn; mach Rm,Rn +8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach +"mach" +*am33 +{ + int srcreg1, srcreg2; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff) + * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff)); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 0101 1011 Rm Rn; machu Rm,Rn +8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu +"machu" +*am33 +{ + int srcreg1, srcreg2; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((unsigned64)(State.regs[srcreg2] & 0xffff) + * (unsigned64)(State.regs[srcreg1] & 0xffff)); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn +8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach +"dmach" +*am33 +{ + int srcreg1, srcreg2; + signed32 temp, temp2, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn +8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu +"dmachu" +*am33 +{ + int srcreg1, srcreg2; + unsigned32 temp, temp2, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + + temp = ((unsigned32)(State.regs[srcreg2] & 0xffff) + * (unsigned32)(State.regs[srcreg1] & 0xffff)); + temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff) + * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn +8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh +"dmulh" +*am33 +{ + int srcreg, dstreg; + signed32 temp; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg] & 0xffff)); + State.regs[REG_MDRQ] = temp; + temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff)); + State.regs[dstreg] = temp; +} + +// 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn +8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu +"dmachu" +*am33 +{ + int srcreg, dstreg; + unsigned32 temp; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = ((unsigned32)(State.regs[dstreg] & 0xffff) + * (unsigned32)(State.regs[srcreg] & 0xffff)); + State.regs[REG_MDRQ] = temp; + temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff) + * (unsigned32)((State.regs[srcreg] >>16) & 0xffff)); + State.regs[dstreg] = temp; +} + +// 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn +8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16 +"sat16" +*am33 +{ + int srcreg, dstreg; + int value, z, n; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + value = State.regs[srcreg]; + + if (value >= 0x7fff) + State.regs[dstreg] = 0x7fff; + else if (value <= 0xffff8000) + State.regs[dstreg] = 0xffff8000; + else + State.regs[dstreg] = value; + + n = (State.regs[dstreg] & 0x8000) != 0; + z = (State.regs[dstreg] == 0); + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn +8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste +"mcste" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + PSW &= ~(PSW_V | PSW_C); + PSW |= (State.regs[REG_MCVF] ? PSW_V : 0); + + /* 32bit saturation. */ + if (State.regs[srcreg] == 0x20) + { + signed64 tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7fffffff) + State.regs[dstreg] = 0x7fffffff; + else if (tmp < 0xffffffff80000000LL) + State.regs[dstreg] = 0x80000000; + else + State.regs[dstreg] = tmp; + } + /* 16bit saturation */ + else if (State.regs[srcreg] == 0x10) + { + signed64 tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7fff) + State.regs[dstreg] = 0x7fff; + else if (tmp < 0xffffffffffff8000LL) + State.regs[dstreg] = 0x8000; + else + State.regs[dstreg] = tmp; + } + /* 8 bit saturation */ + else if (State.regs[srcreg] == 0x8) + { + signed64 tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7f) + State.regs[dstreg] = 0x7f; + else if (tmp < 0xffffffffffffff80LL) + State.regs[dstreg] = 0x80; + else + State.regs[dstreg] = tmp; + } + /* 9 bit saturation */ + else if (State.regs[srcreg] == 0x9) + { + signed64 tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x80) + State.regs[dstreg] = 0x80; + else if (tmp < 0xffffffffffffff81LL) + State.regs[dstreg] = 0x81; + else + State.regs[dstreg] = tmp; + } + /* 9 bit saturation */ + else if (State.regs[srcreg] == 0x30) + { + signed64 tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7fffffffffffLL) + tmp = 0x7fffffffffffLL; + else if (tmp < 0xffff800000000000LL) + tmp = 0xffff800000000000LL; + + tmp >>= 16; + State.regs[dstreg] = tmp; + } +} + +// 1111 1001 1100 1011 Rm Rn; swap Rm,Rn +8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap +"swap" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24) + | (((State.regs[srcreg] >> 8) & 0xff) << 16) + | (((State.regs[srcreg] >> 16) & 0xff) << 8) + | ((State.regs[srcreg] >> 24) & 0xff)); +} + +// 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn +8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph +"swaph" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8) + | ((State.regs[srcreg] >> 8) & 0xff) + | (((State.regs[srcreg] >> 16) & 0xff) << 24) + | (((State.regs[srcreg] >> 24) & 0xff) << 16)); +} + +// 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn +8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw +"swhw" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16) + | ((State.regs[srcreg] >> 16) & 0xffff)); +} + +// 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn +8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch +"bsch" +*am33 +{ + int temp, c, i; + int srcreg, dstreg; + int start; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + temp = State.regs[srcreg]; + start = (State.regs[dstreg] & 0x1f) - 1; + if (start == -1) + start = 31; + + c = 0; + for (i = start; i >= 0; i--) + { + if (temp & (1 << i)) + { + c = 1; + State.regs[dstreg] = i; + break; + } + } + + if (i < 0) + { + c = 0; + State.regs[dstreg] = 0; + } + PSW &= ~(PSW_C); + PSW |= (c ? PSW_C : 0); +} + + +// 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn +8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = EXTEND8 (IMM8); +} + +// 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn +8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu +"movu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = IMM8 & 0xff; +} + +// 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn +8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add +"add" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + genericAdd (EXTEND8 (IMM8), dstreg); +} + +// 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn +8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc +"addc" +*am33 +{ + int dstreg, imm; + int z, c, n, v; + unsigned32 reg2, sum; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + imm = EXTEND8 (IMM8); + reg2 = State.regs[dstreg]; + sum = imm + reg2 + ((PSW & PSW_C) != 0); + State.regs[dstreg] = sum; + + z = ((PSW & PSW_Z) != 0) && (sum == 0); + n = (sum & 0x80000000); + c = (sum < imm) || (sum < reg2); + v = ((reg2 & 0x80000000) == (imm & 0x80000000) + && (reg2 & 0x80000000) != (sum & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn +8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub +"sub" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + genericSub (EXTEND8 (IMM8), dstreg); +} + +// 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn +8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc +"subc" +*am33 +{ + int imm, dstreg; + int z, c, n, v; + unsigned32 reg2, difference; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + imm = EXTEND8 (IMM8); + reg2 = State.regs[dstreg]; + difference = reg2 - imm - ((PSW & PSW_C) != 0); + State.regs[dstreg] = difference; + + z = ((PSW & PSW_Z) != 0) && (difference == 0); + n = (difference & 0x80000000); + c = (imm > reg2); + v = ((reg2 & 0x80000000) == (imm & 0x80000000) + && (reg2 & 0x80000000) != (difference & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn +8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp +"cmp" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + genericCmp (EXTEND8 (IMM8), State.regs[srcreg]); +} + +// 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn +8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_xreg (SD_, XRN0); + + State.regs[dstreg] = IMM8; +} + +// 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn +8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and +"and" +*am33 +{ + int dstreg; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] &= (IMM8 & 0xff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn +8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or +"or" +*am33 +{ + int dstreg; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] |= (IMM8 & 0xff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn +8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor +"xor" +*am33 +{ + int dstreg; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] ^= (IMM8 & 0xff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn +8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr +"asr" +*am33 +{ + int dstreg; + signed32 temp; + int c, z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = State.regs[dstreg]; + c = temp & 1; + temp >>= (IMM8 & 0xff); + State.regs[dstreg] = temp; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn +8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr +"lsr" +*am33 +{ + int dstreg; + int z, n, c; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + c = State.regs[dstreg] & 1; + State.regs[dstreg] >>= (IMM8 & 0xff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn +8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl +"asl" +*am33 +{ + int dstreg; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] <<= (IMM8 & 0xff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn +8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul +"mul" +*am33 +{ + int dstreg; + unsigned64 temp; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = ((signed64)(signed32)State.regs[dstreg] + * (signed64)(signed32)EXTEND8 (IMM8)); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn +8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu +"mulu" +*am33 +{ + int dstreg; + unsigned64 temp; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = ((unsigned64)State.regs[dstreg] + * (unsigned64)(IMM8 & 0xff)); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn +8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst +"btst" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + genericBtst(IMM8, State.regs[srcreg]); +} + +// 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn +8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8)); +} + +// 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn) +8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]); +} + +// 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn +8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8)); +} + +// 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn) +8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]); +} + +// 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn +8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8)); +} + +// 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn) +8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]); +} + +// 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn +8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND8 (IMM8); +} + +// 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+) +8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg], State.regs[srcreg]); + State.regs[dstreg] += EXTEND8 (IMM8); +} + + +// 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn +8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[REG_SP] + IMM8); +} + +// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,sp) +8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov +"mov" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_word (State.regs[REG_SP] + IMM8, State.regs[srcreg]); +} + +// 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn +8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu +"movbu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[REG_SP] + IMM8); +} + +// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(d8,sp) +8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu +"movbu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_byte (State.regs[REG_SP] + IMM8, State.regs[srcreg]); +} + +// 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn +8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu +"movhu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[REG_SP] + IMM8); +} + +// 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp) +8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu +"movhu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_half (State.regs[REG_SP] + IMM8, State.regs[srcreg]); +} + +// 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn +8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg]); + State.regs[srcreg] += EXTEND8 (IMM8); +} + +// 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+) +8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg], State.regs[srcreg]); + State.regs[dstreg] += EXTEND8 (IMM8); +} + + +// 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn +8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac +"mac" +*am33 +{ + int srcreg; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((signed64)(signed32)EXTEND8 (IMM8) + * (signed64)(signed32)State.regs[srcreg]); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn +8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu +"macu" +*am33 +{ + int srcreg; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((unsigned64) (IMM8) + * (unsigned64)State.regs[srcreg]); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn +8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb +"macb" +*am33 +{ + int srcreg; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((signed64)(signed8)EXTEND8 (IMM8) + * (signed64)(signed8)State.regs[srcreg] & 0xff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn +8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu +"macbu" +*am33 +{ + int srcreg; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((unsigned64) (IMM8) + * (unsigned64)State.regs[srcreg] & 0xff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn +8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach +"mach" +*am33 +{ + int srcreg; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((signed64)(signed16)EXTEND8 (IMM8) + * (signed64)(signed16)State.regs[srcreg] & 0xffff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn +8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu +"machu" +*am33 +{ + int srcreg; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((unsigned64) (IMM8) + * (unsigned64)State.regs[srcreg] & 0xffff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn +8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste +"mcste" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + PSW &= ~(PSW_V | PSW_C); + PSW |= (State.regs[REG_MCVF] ? PSW_V : 0); + + /* 32bit saturation. */ + if (IMM8 == 0x20) + { + signed64 tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7fffffff) + State.regs[dstreg] = 0x7fffffff; + else if (tmp < 0xffffffff80000000LL) + State.regs[dstreg] = 0x80000000; + else + State.regs[dstreg] = tmp; + } + /* 16bit saturation */ + else if (IMM8 == 0x10) + { + signed64 tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7fff) + State.regs[dstreg] = 0x7fff; + else if (tmp < 0xffffffffffff8000LL) + State.regs[dstreg] = 0x8000; + else + State.regs[dstreg] = tmp; + } + /* 8 bit saturation */ + else if (IMM8 == 0x8) + { + signed64 tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7f) + State.regs[dstreg] = 0x7f; + else if (tmp < 0xffffffffffffff80LL) + State.regs[dstreg] = 0x80; + else + State.regs[dstreg] = tmp; + } + /* 9 bit saturation */ + else if (IMM8 == 0x9) + { + signed64 tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x80) + State.regs[dstreg] = 0x80; + else if (tmp < 0xffffffffffffff81LL) + State.regs[dstreg] = 0x81; + else + State.regs[dstreg] = tmp; + } + /* 9 bit saturation */ + else if (IMM8 == 0x30) + { + signed64 tmp; + + tmp = State.regs[REG_MCRH]; + tmp <<= 32; + tmp += State.regs[REG_MCRL]; + + if (tmp > 0x7fffffffffffLL) + tmp = 0x7fffffffffffLL; + else if (tmp < 0xffff800000000000LL) + tmp = 0xffff800000000000LL; + + tmp >>= 16; + State.regs[dstreg] = tmp; + } +} + +// 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd +8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add +"add" +*am33 +{ + int z, c, n, v; + unsigned32 sum, source1, source2; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + source1 = State.regs[srcreg1]; + source2 = State.regs[srcreg2]; + sum = source1 + source2; + State.regs[dstreg] = sum; + + z = (sum == 0); + n = (sum & 0x80000000); + c = (sum < source1) || (sum < source2); + v = ((source1 & 0x80000000) == (source2 & 0x80000000) + && (source1 & 0x80000000) != (sum & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd +8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc +"addc" +*am33 +{ + int z, c, n, v; + unsigned32 sum, source1, source2; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + source1 = State.regs[srcreg1]; + source2 = State.regs[srcreg2]; + sum = source1 + source2 + ((PSW & PSW_C) != 0); + State.regs[dstreg] = sum; + + z = ((PSW & PSW_Z) != 0) && (sum == 0); + n = (sum & 0x80000000); + c = (sum < source1) || (sum < source2); + v = ((source1 & 0x80000000) == (source2 & 0x80000000) + && (source1 & 0x80000000) != (sum & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd +8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub +"sub" +*am33 +{ + int z, c, n, v; + unsigned32 difference, source1, source2; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + source1 = State.regs[srcreg1]; + source2 = State.regs[srcreg2]; + difference = source2 - source1; + State.regs[dstreg] = difference; + + z = (difference == 0); + n = (difference & 0x80000000); + c = (source1 > source1); + v = ((source1 & 0x80000000) == (source2 & 0x80000000) + && (source1 & 0x80000000) != (difference & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd +8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc +"subc" +*am33 +{ + int z, c, n, v; + unsigned32 difference, source1, source2; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + source1 = State.regs[srcreg1]; + source2 = State.regs[srcreg2]; + difference = source2 - source1 - ((PSW & PSW_C) != 0); + State.regs[dstreg] = difference; + + z = ((PSW & PSW_Z) != 0) && (difference == 0); + n = (difference & 0x80000000); + c = (source1 > source2); + v = ((source1 & 0x80000000) == (source2 & 0x80000000) + && (source1 & 0x80000000) != (difference & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd +8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and +"and" +*am33 +{ + int z, n; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2]; + + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd +8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or +"or" +*am33 +{ + int z, n; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2]; + + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd +8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor +"xor" +*am33 +{ + int z, n; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2]; + + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd +8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr +"asr" +*am33 +{ + int z, c, n; + signed32 temp; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + temp = State.regs[srcreg2]; + c = temp & 1; + temp >>= State.regs[srcreg1]; + State.regs[dstreg] = temp; + + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd +8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr +"lsr" +*am33 +{ + int z, c, n; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + c = State.regs[srcreg2] & 1; + State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1]; + + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd +8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl +"asl" +*am33 +{ + int z, n; + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1]; + + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2 +8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul +"mul" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed64 temp; + int n, z; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD2); + + temp = ((signed64)(signed32)State.regs[srcreg1] + * (signed64)(signed32)State.regs[srcreg2]); + State.regs[dstreg2] = temp & 0xffffffff; + State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32; + + z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0); + n = (State.regs[dstreg1] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2 +8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu +"mulu" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed64 temp; + int n, z; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD2); + + temp = ((unsigned64)State.regs[srcreg1] + * (unsigned64)State.regs[srcreg2]); + State.regs[dstreg2] = temp & 0xffffffff; + State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32; + + z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0); + n = (State.regs[dstreg1] & 0x80000000); + + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)); +} + +// 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn +8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (IMM8); +} + +// 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8) +8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov +"mov" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_word (IMM8, State.regs[srcreg]); +} + +// 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn +8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu +"movbu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (IMM8); +} + +// 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8) +8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu +"movbu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_byte (IMM8, State.regs[srcreg]); +} + +// 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn +8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu +"movhu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (IMM8); +} + +// 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8) +8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu +"movhu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_half (IMM8, State.regs[srcreg]); +} + +// 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn +8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov +"mov" +*am33 +{ + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM0); + srcreg2 = translate_rreg (SD_, RI0); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]); +} + +// 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm) +8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov +"mov" +*am33 +{ + int srcreg, dstreg1, dstreg2; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg1 = translate_rreg (SD_, RI0); + dstreg2 = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]); +} + +// 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn +8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu +"movbu" +*am33 +{ + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM0); + srcreg2 = translate_rreg (SD_, RI0); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]); +} + +// 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm) +8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg1, dstreg2; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg1 = translate_rreg (SD_, RI0); + dstreg2 = translate_rreg (SD_, RN0); + store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]); +} + +// 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn +8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu +"movhu" +*am33 +{ + int srcreg1, srcreg2, dstreg; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM0); + srcreg2 = translate_rreg (SD_, RI0); + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]); +} + +// 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm) +8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg1, dstreg2; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg1 = translate_rreg (SD_, RI0); + dstreg2 = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]); +} + +// 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2 +8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac +"mac" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed64 temp; + unsigned32 sum; + int c, v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD2); + + temp = ((signed64)(signed32)State.regs[srcreg1] + * (signed64)(signed32)State.regs[srcreg2]); + + sum = State.regs[dstreg2] + (temp & 0xffffffff); + c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff)); + State.regs[dstreg2] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[dstreg1] + temp + c; + v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg1] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= (( v ? PSW_V : 0)); + } +} + +// 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2 +8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu +"macu" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed64 temp; + unsigned32 sum; + int c, v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD2); + + temp = ((unsigned64)State.regs[srcreg1] + * (unsigned64)State.regs[srcreg2]); + + sum = State.regs[dstreg2] + (temp & 0xffffffff); + c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff)); + State.regs[dstreg2] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[dstreg1] + temp + c; + v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg1] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= (( v ? PSW_V : 0)); + } +} + +// 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1 +8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb +"macb" +*am33 +{ + int srcreg1, srcreg2, dstreg; + signed32 temp, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + temp = ((signed32)(State.regs[srcreg2] & 0xff) + * (signed32)(State.regs[srcreg1] & 0xff)); + sum = State.regs[dstreg] + temp; + v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= ((v ? PSW_V : 0)); + } +} + +// 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1 +8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu +"macbu" +*am33 +{ + int srcreg1, srcreg2, dstreg; + signed32 temp, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + temp = ((unsigned32)(State.regs[srcreg2] & 0xff) + * (unsigned32)(State.regs[srcreg1] & 0xff)); + sum = State.regs[dstreg] + temp; + v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= ((v ? PSW_V : 0)); + } +} + +// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2 +8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach +"mach" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed64 temp, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD0); + + temp = ((signed32)(State.regs[srcreg2] & 0xffff) + * (signed32)(State.regs[srcreg1] & 0xffff)); + State.regs[dstreg2] += (temp & 0xffffffff); + sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff); + v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg1] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= ((v ? PSW_V : 0)); + } +} + +// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2 +8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu +"machu" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed64 temp, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD0); + + temp = ((unsigned32)(State.regs[srcreg2] & 0xffff) + * (unsigned32)(State.regs[srcreg1] & 0xffff)); + State.regs[dstreg2] += (temp & 0xffffffff); + sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff); + v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg1] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= ((v ? PSW_V : 0)); + } +} + +// 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1 +8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach +"dmach" +*am33 +{ + int srcreg1, srcreg2, dstreg; + signed32 temp, temp2, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + temp = ((signed32)(State.regs[srcreg2] & 0xffff) + * (signed32)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)((State.regs[srcreg2] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[dstreg]; + v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= ((v ? PSW_V : 0)); + } +} + +// 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1 +8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu +"dmachu" +*am33 +{ + int srcreg1, srcreg2, dstreg; + signed32 temp, temp2, sum; + int v; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + temp = ((unsigned32)(State.regs[srcreg2] & 0xffff) + * (unsigned32)(State.regs[srcreg1] & 0xffff)); + temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff) + * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[dstreg]; + v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[dstreg] = sum; + if (v) + { + State.regs[REG_MCVF] = 1; + PSW &= ~(PSW_V); + PSW |= ((v ? PSW_V : 0)); + } +} + +// 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2 +8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh +"dmulh" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed64 temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD2); + + temp = ((signed32)(State.regs[srcreg1] & 0xffff) + * (signed32)(State.regs[srcreg1] & 0xffff)); + State.regs[dstreg2] = temp; + temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)((State.regs[srcreg1] >>16) & 0xffff)); + State.regs[dstreg1] = temp; +} + +// 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2 +8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu +"dmulhu" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed64 temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg1 = translate_rreg (SD_, RD0); + dstreg2 = translate_rreg (SD_, RD2); + + temp = ((unsigned32)(State.regs[srcreg1] & 0xffff) + * (unsigned32)(State.regs[srcreg1] & 0xffff)); + State.regs[dstreg2] = temp; + temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff) + * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff)); + State.regs[dstreg1] = temp; +} + +// 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn +8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24 +"sat24" +*am33 +{ + int srcreg, dstreg; + int value, n, z; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + + value = State.regs[srcreg]; + + if (value >= 0x7fffff) + State.regs[dstreg] = 0x7fffff; + else if (value <= 0xff800000) + State.regs[dstreg] = 0xff800000; + else + State.regs[dstreg] = value; + + n = (State.regs[dstreg] & 0x800000) != 0; + z = (State.regs[dstreg] == 0); + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1 +8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch +"bsch" +*am33 +{ + int temp, c, i; + int srcreg1, srcreg2, dstreg; + int start; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM2); + srcreg2 = translate_rreg (SD_, RN0); + dstreg = translate_rreg (SD_, RD0); + + temp = State.regs[srcreg1]; + start = (State.regs[srcreg2] & 0x1f) - 1; + if (start == -1) + start = 31; + + c = 0; + for (i = start; i >= 0; i--) + { + if (temp & (1 << i)) + { + c = 1; + State.regs[dstreg] = i; + break; + } + } + + if (i < 0) + { + c = 0; + State.regs[dstreg] = 0; + } + PSW &= ~(PSW_C); + PSW |= (c ? PSW_C : 0); +} + +// 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn +8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn +8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu +"movu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff; +} + +// 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn +8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add +"add" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg); +} + +// 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn +8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc +"addc" +*am33 +{ + int dstreg, z, n, c, v; + unsigned32 sum, imm, reg2; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); + reg2 = State.regs[dstreg]; + sum = imm + reg2 + ((PSW & PSW_C) != 0); + State.regs[dstreg] = sum; + + z = ((PSW & PSW_Z) != 0) && (sum == 0); + n = (sum & 0x80000000); + c = (sum < imm) || (sum < reg2); + v = ((reg2 & 0x80000000) == (imm & 0x80000000) + && (reg2 & 0x80000000) != (sum & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn +8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub +"sub" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg); +} + +// 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn +8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc +"subc" +*am33 +{ + int dstreg, z, n, c, v; + unsigned32 difference, imm, reg2; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); + reg2 = State.regs[dstreg]; + difference = reg2 - imm - ((PSW & PSW_C) != 0); + State.regs[dstreg] = difference; + + z = ((PSW & PSW_Z) != 0) && (difference == 0); + n = (difference & 0x80000000); + c = (imm > reg2); + v = ((reg2 & 0x80000000) == (imm & 0x80000000) + && (reg2 & 0x80000000) != (difference & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn +8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp +"cmp" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]); +} + +// 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn +8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_xreg (SD_, XRN0); + + State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff; +} + +// 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn +8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and +"and" +*am33 +{ + int dstreg; + int z,n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn +8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or +"or" +*am33 +{ + int dstreg; + int z,n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn +8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor +"xor" +*am33 +{ + int dstreg; + int z,n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn +8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr +"asr" +*am33 +{ + int dstreg; + signed32 temp; + int c, z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = State.regs[dstreg]; + c = temp & 1; + temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C)); + State.regs[dstreg] = temp; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + + +// 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn +8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr +"lsr" +*am33 +{ + int dstreg; + int z, n, c; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + c = State.regs[dstreg] & 1; + State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C)); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn +8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl +"asl" +*am33 +{ + int dstreg; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C)); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn +8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul +"mul" +*am33 +{ + int dstreg; + unsigned64 temp; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = ((signed64)(signed32)State.regs[dstreg] + * (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn +8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu +"mulu" +*am33 +{ + int dstreg; + unsigned64 temp; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = ((unsigned64)State.regs[dstreg] + * (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn +8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst +"btst" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); +} + +// 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn +8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg] + + EXTEND24 (FETCH24 (IMM24A, + IMM24B, IMM24C))); +} + +// 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn) +8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), + State.regs[srcreg]); +} + +// 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn +8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[srcreg] + + EXTEND24 (FETCH24 (IMM24A, + IMM24B, IMM24C))); +} + +// 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn) +8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), + State.regs[srcreg]); +} + +// 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn +8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg] + + EXTEND24 (FETCH24 (IMM24A, + IMM24B, IMM24C))); +} + +// 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn) +8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), + State.regs[srcreg]); +} + +// 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn +8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+) +8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg], State.regs[srcreg]); + State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + + +// 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn +8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[REG_SP] + + FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp) +8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov +"mov" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C), + State.regs[srcreg]); +} + +// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,sp),Rn +8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu +"movbu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[REG_SP] + + FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp) +8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu +"movbu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C), + State.regs[srcreg]); +} + +// 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn +8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu +"movhu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[REG_SP] + + FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp) +8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu +"movhu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C), + State.regs[srcreg]); +} + +// 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn +8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg]); + State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+) +8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg], State.regs[srcreg]); + State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn +8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac +"mac" +*am33 +{ + int srcreg; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)) + * (signed64)State.regs[srcreg]); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn +8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu +"macu" +*am33 +{ + int srcreg; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C)) + * (unsigned64)State.regs[srcreg]); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn +8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb +"macb" +*am33 +{ + int srcreg; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C)) + * (signed64)State.regs[srcreg] & 0xff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn +8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu +"macbu" +*am33 +{ + int srcreg; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C)) + * (unsigned64)State.regs[srcreg] & 0xff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn +8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach +"mach" +*am33 +{ + int srcreg; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C)) + * (signed64)State.regs[srcreg] & 0xffff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn +8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu +"machu" +*am33 +{ + int srcreg; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN2); + + temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff) + * (unsigned64)State.regs[srcreg] & 0xffff); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn +8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24) +8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov +"mov" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); +} + + +// 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn +8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu +"movbu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24) +8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu +"movbu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); +} + + +// 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn +8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu +"movhu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C)); +} + +// 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24) +8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu +"movhu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]); +} + + +// 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn +8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); +} + +// 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn +8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu +"movu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); +} + +// 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn +8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add +"add" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg); +} + +// 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn +8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc +"addc" +*am33 +{ + int dstreg; + unsigned32 imm, reg2, sum; + int z, n, c, v; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + reg2 = State.regs[dstreg]; + sum = imm + reg2 + ((PSW & PSW_C) != 0); + State.regs[dstreg] = sum; + + z = ((PSW & PSW_Z) != 0) && (sum == 0); + n = (sum & 0x80000000); + c = (sum < imm) || (sum < reg2); + v = ((reg2 & 0x80000000) == (imm & 0x80000000) + && (reg2 & 0x80000000) != (sum & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn +8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub +"sub" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg); +} + +// 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn +8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc +"subc" +*am33 +{ + int dstreg; + unsigned32 imm, reg2, difference; + int z, n, c, v; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + reg2 = State.regs[dstreg]; + difference = reg2 - imm - ((PSW & PSW_C) != 0); + State.regs[dstreg] = difference; + + z = ((PSW & PSW_Z) != 0) && (difference == 0); + n = (difference & 0x80000000); + c = (imm > reg2); + v = ((reg2 & 0x80000000) == (imm & 0x80000000) + && (reg2 & 0x80000000) != (difference & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +// 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn +8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp +"cmp" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); +} + +// 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn +8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_xreg (SD_, XRN0); + + State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D); +} + +// 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn +8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and +"and" +*am33 +{ + int dstreg; + int z,n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn +8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or +"or" +*am33 +{ + int dstreg; + int z,n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn +8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor +"xor" +*am33 +{ + int dstreg; + int z,n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn +8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr +"asr" +*am33 +{ + int dstreg; + signed32 temp; + int c, z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = State.regs[dstreg]; + c = temp & 1; + temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); + State.regs[dstreg] = temp; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn +8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr +"lsr" +*am33 +{ + int dstreg; + int z, n, c; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + c = State.regs[dstreg] & 1; + State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +// 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn +8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl +"asl" +*am33 +{ + int dstreg; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn +8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul +"mul" +*am33 +{ + int dstreg; + unsigned64 temp; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = ((signed64)(signed32)State.regs[dstreg] + * (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D))); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn +8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu +"mulu" +*am33 +{ + int dstreg; + unsigned64 temp; + int z, n; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + + temp = ((unsigned64)State.regs[dstreg] + * (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D))); + State.regs[dstreg] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[dstreg] == 0); + n = (State.regs[dstreg] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +// 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn +8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst +"btst" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); +} + +// 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn +8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg] + + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn) +8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), + State.regs[srcreg]); +} + +// 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn +8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[srcreg] + + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn) +8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu +"movbu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), + State.regs[srcreg]); +} + +// 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn +8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg] + + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn) +8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), + State.regs[srcreg]); +} + +// 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn +8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); +} + +// 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+) +8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov +"mov" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_word (State.regs[dstreg], State.regs[srcreg]); + State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); +} + + +// 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn +8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (State.regs[REG_SP] + + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp) +8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov +"mov" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), + State.regs[srcreg]); +} + +// 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn +8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu +"movbu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (State.regs[REG_SP] + + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp) +8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu +"movbu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), + State.regs[srcreg]); +} + +// 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn +8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu +"movhu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[REG_SP] + + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp) +8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu +"movhu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), + State.regs[srcreg]); +} + + +// 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn +8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM0); + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (State.regs[srcreg]); + State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); +} + +// 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+) +8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu +"movhu" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + dstreg = translate_rreg (SD_, RN0); + store_half (State.regs[dstreg], State.regs[srcreg]); + State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); +} + + +// 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn +8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac +"mac" +*am33 +{ + int srcreg, imm; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((signed64)(signed32)State.regs[srcreg] + * (signed64)(signed32)imm); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn +8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu +"macu" +*am33 +{ + int srcreg, imm; + signed64 temp, sum; + int c, v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((unsigned64)State.regs[srcreg] + * (unsigned64)imm); + sum = State.regs[REG_MCRL] + (temp & 0xffffffff); + c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff)); + State.regs[REG_MCRL] = sum; + temp >>= 32; + temp &= 0xffffffff; + sum = State.regs[REG_MCRH] + temp + c; + v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRH] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn +8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb +"macb" +*am33 +{ + int srcreg, imm; + signed32 temp, sum; + int v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff) + * (signed32)(signed8)(imm & 0xff)); + sum = State.regs[REG_MCRL] + temp; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn +8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu +"macbu" +*am33 +{ + int srcreg, imm; + signed32 temp, sum; + int v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((unsigned32)(State.regs[srcreg] & 0xff) + * (unsigned32)(imm & 0xff)); + sum = State.regs[REG_MCRL] + temp; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn +8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach +"mach" +*am33 +{ + int srcreg, imm; + signed32 temp, sum; + int v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff) + * (signed32)(signed16)(imm & 0xffff)); + sum = State.regs[REG_MCRL] + temp; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn +8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu +"machu" +*am33 +{ + int srcreg, imm; + signed32 temp, sum; + int v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((unsigned32)(State.regs[srcreg] & 0xffff) + * (unsigned32)(imm & 0xffff)); + sum = State.regs[REG_MCRL] + temp; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn +8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach +"dmach" +*am33 +{ + int srcreg, imm; + signed32 temp, temp2, sum; + int v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff) + * (signed32)(signed16)(imm & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff) + * (signed32)(signed16)((imm >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn +8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu +"dmachu" +*am33 +{ + int srcreg, imm; + signed32 temp, temp2, sum; + int v; + + PC = cia; + srcreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((unsigned32)(State.regs[srcreg] & 0xffff) + * (unsigned32)(imm & 0xffff)); + temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff) + * (unsigned32)((imm >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000) + && (temp & 0x80000000) != (sum & 0x80000000)); + State.regs[REG_MCRL] = sum; + if (v) + State.regs[REG_MCVF] = 1; +} + +// 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn +8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh +"dmulh" +*am33 +{ + int imm, dstreg; + signed32 temp; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff) + * (signed32)(signed16)(imm & 0xffff)); + State.regs[REG_MDRQ] = temp; + temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff) + * (signed32)(signed16)((imm>>16) & 0xffff)); + State.regs[dstreg] = temp; +} + +// 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn +8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu +"dmulhu" +*am33 +{ + int imm, dstreg; + signed32 temp; + + PC = cia; + dstreg = translate_rreg (SD_, RN0); + imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D); + + temp = ((unsigned32)(State.regs[dstreg] & 0xffff) + * (unsigned32)(imm & 0xffff)); + State.regs[REG_MDRQ] = temp; + temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff) + * (unsigned32)((imm >>16) & 0xffff)); + State.regs[dstreg] = temp; +} + +// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn +8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov +"mov" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32) +8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov +"mov" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); +} + +// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn +8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu +"movbu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32) +8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu +"movbu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); +} + +// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn +8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu +"movhu" +*am33 +{ + int dstreg; + + PC = cia; + dstreg = translate_rreg (SD_, RN2); + State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)); +} + +// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32) +8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu +"movhu" +*am33 +{ + int srcreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM2); + store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]); +} + +// 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add +"add_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add +"add_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub +"add_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub +"add_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp +"add_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] += State.regs[srcreg1]; +} + +// 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp +"add_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] += State.regs[srcreg1]; +} + +// 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov +"add_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov +"add_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr +"add_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr +"add_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr +"add_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr +"add_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl +"add_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl +"add_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + State.regs[srcreg1]; + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add +"cmp_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] += State.regs[srcreg2]; +} + +// 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add +"cmp_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] += EXTEND4 (IMM4); +} + +// 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub +"cmp_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] -= State.regs[srcreg2]; +} + +// 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub +"cmp_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] -= EXTEND4 (IMM4); +} + +// 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov +"cmp_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] = State.regs[srcreg2]; +} + +// 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov +"cmp_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] = EXTEND4 (IMM4); +} + +// 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr +"cmp_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; +} + +// 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr +"cmp_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; +} + +// 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr +"cmp_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] >>= State.regs[srcreg2]; +} + +// 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr +"cmp_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] >>= IMM4; +} + + +// 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl +"cmp_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] <<= State.regs[srcreg2]; +} + +// 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl +"cmp_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg1], State.regs[dstreg1]); + State.regs[dstreg2] <<= IMM4; +} + +// 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add +"sub_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add +"sub_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub +"sub_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub +"sub_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp +"sub_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] -= State.regs[srcreg1]; +} + +// 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp +"sub_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] -= State.regs[srcreg1]; +} + +// 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov +"sub_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov +"sub_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr +"sub_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr +"sub_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr +"sub_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr +"sub_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl +"sub_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl +"sub_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - State.regs[srcreg1]; + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add +"mov_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add +"mov_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub +"mov_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub +"mov_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp +"mov_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] = State.regs[srcreg1]; +} + +// 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp +"mov_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] = State.regs[srcreg1]; +} + +// 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov +"mov_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov +"mov_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr +"mov_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr +"mov_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr +"mov_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr +"mov_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl +"mov_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl +"mov_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[srcreg1]; + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add +"add_add" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add +"add_add" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub +"add_sub" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub +"add_sub" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp +"add_cmp" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] += EXTEND4 (IMM4A); +} + +// 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp +"add_cmp" +*am33 +{ + int dstreg1, dstreg2; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] += EXTEND4 (IMM4A); +} + +// 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov +"add_mov" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov +"add_mov" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr +"add_asr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr +"add_asr" +*am33 +{ + int dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr +"add_lsr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr +"add_lsr" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl +"add_asl" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl +"add_asl" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] + EXTEND4 (IMM4A); + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add +"cmp_add" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] += State.regs[srcreg2]; +} + +// 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add +"cmp_add" +*am33 +{ + int dstreg1, dstreg2; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] += EXTEND4 (IMM4); +} + +// 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub +"cmp_sub" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] -= State.regs[srcreg2]; +} + +// 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub +"cmp_sub" +*am33 +{ + int dstreg1, dstreg2; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] -= EXTEND4 (IMM4); +} + +// 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov +"cmp_mov" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] = State.regs[srcreg2]; +} + +// 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov +"cmp_mov" +*am33 +{ + int dstreg1, dstreg2; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] = EXTEND4 (IMM4); +} + +// 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr +"cmp_asr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + signed int temp; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; +} + +// 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr +"cmp_asr" +*am33 +{ + int dstreg1, dstreg2; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; +} + +// 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr +"cmp_lsr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] >>= State.regs[srcreg2]; +} + +// 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr +"cmp_lsr" +*am33 +{ + int dstreg1, dstreg2; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] >>= IMM4; +} + + +// 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl +"cmp_asl" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] <<= State.regs[srcreg2]; +} + +// 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl +"cmp_asl" +*am33 +{ + int dstreg1, dstreg2; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]); + State.regs[dstreg2] <<= IMM4; +} + +// 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add +"sub_add" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add +"sub_add" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub +"sub_sub" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub +"sub_sub" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp +"sub_cmp" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] -= EXTEND4 (IMM4A); +} + +// 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp +"sub_cmp" +*am33 +{ + int dstreg1, dstreg2; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] -= EXTEND4 (IMM4A); +} + +// 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov +"sub_mov" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov +"sub_mov" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr +"sub_asr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr +"sub_asr" +*am33 +{ + int dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr +"sub_lsr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr +"sub_lsr" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl +"sub_asl" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl +"sub_asl" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] - EXTEND4 (IMM4A); + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add +"mov_add" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add +"mov_add" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub +"mov_sub" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub +"mov_sub" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp +"mov_cmp" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] = EXTEND4 (IMM4A); +} + +// 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp +"mov_cmp" +*am33 +{ + int dstreg1, dstreg2; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] = EXTEND4 (IMM4A); +} + +// 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov +"mov_mov" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov +"mov_mov" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr +"mov_asr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr +"mov_asr" +*am33 +{ + int dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr +"mov_lsr" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr +"mov_lsr" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2 +8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl +"mov_asl" +*am33 +{ + int srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2 +8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl +"mov_asl" +*am33 +{ + int dstreg1, dstreg2; + int result1; + + PC = cia; + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = EXTEND4 (IMM4A); + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add +"and_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add +"and_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub +"and_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub +"and_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp +"and_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] &= State.regs[srcreg1]; +} + +// 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp +"and_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] &= State.regs[srcreg1]; +} + +// 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov +"and_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov +"and_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr +"and_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr +"and_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr +"and_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr +"and_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl +"and_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl +"and_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] & State.regs[srcreg1]; + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add +"dmach_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed32 temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = sum; +} + +// 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add +"dmach_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + signed32 temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = sum; +} + +// 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub +"dmach_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed32 temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = sum; +} + +// 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub +"dmach_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + signed32 temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = sum; +} + +// 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp +"dmach_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed32 temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] = sum; +} + +// 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp +"dmach_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + signed32 temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] = sum; +} + +// 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov +"dmach_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed32 temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = sum; +} + +// 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov +"dmach_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + signed32 temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = sum; +} + +// 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr +"dmach_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed32 temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = sum; +} + +// 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr +"dmach_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + signed32 temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = sum; +} + +// 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr +"dmach_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed32 temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = sum; +} + +// 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr +"dmach_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + signed32 temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = sum; +} + + +// 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl +"dmach_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + signed32 temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = sum; +} + +// 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl +"dmach_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + signed32 temp, temp2, sum; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff) + * (signed32)(signed16)(State.regs[srcreg1] & 0xffff)); + temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff) + * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff)); + sum = temp + temp2 + State.regs[REG_MCRL]; + + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = sum; +} + +// 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add +"xor_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add +"xor_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub +"xor_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub +"xor_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp +"xor_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] ^= State.regs[srcreg1]; +} + +// 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp +"xor_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] ^= State.regs[srcreg1]; +} + +// 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov +"xor_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov +"xor_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr +"xor_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr +"xor_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr +"xor_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr +"xor_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl +"xor_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl +"xor_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add +"swhw_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] ^ State.regs[srcreg1]; + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add +"swhw_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub +"swhw_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub +"swhw_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp +"swhw_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); +} + +// 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp +"swhw_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); +} + +// 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov +"swhw_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov +"swhw_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr +"swhw_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr +"swhw_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr +"swhw_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr +"swhw_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl +"swhw_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl +"swhw_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = (((State.regs[srcreg1] & 0xffff) << 16) + | ((State.regs[srcreg1] >> 16) & 0xffff)); + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add +"or_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add +"or_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub +"or_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub +"or_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp +"or_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[srcreg2], State.regs[dstreg2]); + State.regs[dstreg1] |= State.regs[srcreg1]; +} + +// 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp +"or_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + State.regs[dstreg1] |= State.regs[srcreg1]; +} + +// 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov +"or_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov +"or_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr +"or_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr +"or_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr +"or_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr +"or_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl +"or_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl +"or_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + result1 = State.regs[dstreg1] | State.regs[srcreg1]; + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add +"sat16_add" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] += State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add +"sat16_add" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] += EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub +"sat16_sub" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] -= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub +"sat16_sub" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] -= EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp +"sat16_cmp" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (State.regs[dstreg2], State.regs[dstreg1]); + if (State.regs[srcreg1] >= 0x7fff) + State.regs[dstreg1] = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + State.regs[dstreg1] = 0xffff8000; + else + State.regs[dstreg1] = State.regs[srcreg1]; +} + +// 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp +"sat16_cmp" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]); + if (State.regs[srcreg1] >= 0x7fff) + State.regs[dstreg1] = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + State.regs[dstreg1] = 0xffff8000; + else + State.regs[dstreg1] = State.regs[srcreg1]; +} + +// 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov +"sat16_mov" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] = State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov +"sat16_mov" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] = EXTEND4 (IMM4); + State.regs[dstreg1] = result1; +} + +// 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr +"sat16_asr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + temp = State.regs[dstreg2]; + temp >>= State.regs[srcreg2]; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr +"sat16_asr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + signed int temp; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + temp = State.regs[dstreg2]; + temp >>= IMM4; + State.regs[dstreg2] = temp; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr +"sat16_lsr" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] >>= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr +"sat16_lsr" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] >>= IMM4; + State.regs[dstreg1] = result1; +} + + +// 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2 +8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl +"sat16_asl" +*am33 +{ + int srcreg1, srcreg2, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + srcreg2 = translate_rreg (SD_, RM2); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] <<= State.regs[srcreg2]; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2 +8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl +"sat16_asl" +*am33 +{ + int srcreg1, dstreg1, dstreg2; + int result1; + + PC = cia; + srcreg1 = translate_rreg (SD_, RM1); + dstreg1 = translate_rreg (SD_, RN1); + dstreg2 = translate_rreg (SD_, RN2); + + if (State.regs[srcreg1] >= 0x7fff) + result1 = 0x7fff; + else if (State.regs[srcreg1] <= 0xffff8000) + result1 = 0xffff8000; + else + result1 = State.regs[srcreg1]; + + State.regs[dstreg2] <<= IMM4; + State.regs[dstreg1] = result1; +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt +"mov_llt" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt +"mov_lgt" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (!((PSW & PSW_Z) + || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge +"mov_lge" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle +"mov_lle" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if ((PSW & PSW_Z) + || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs +"mov_lcs" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (PSW & PSW_C) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi +"mov_lhi" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc +"mov_lcc" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (!(PSW & PSW_C)) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls +"mov_lls" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq +"mov_leq" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (PSW & PSW_Z) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne +"mov_lne" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + if (!(PSW & PSW_Z)) + { + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; + } +} + +// 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn +8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra +"mov_lra" +*am33 +{ + int srcreg, dstreg; + + PC = cia; + srcreg = translate_rreg (SD_, RM); + dstreg = translate_rreg (SD_, RN); + + State.regs[dstreg] = load_word (State.regs[srcreg]); + State.regs[srcreg] += EXTEND4 (IMM4); + + State.regs[REG_PC] = State.regs[REG_LAR] - 4; + nia = PC; +} +

am33.igen Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: gencode.c =================================================================== --- gencode.c (nonexistent) +++ gencode.c (revision 1765) @@ -0,0 +1,163 @@ +#include "mn10300_sim.h" + +static void write_header PARAMS ((void)); +static void write_opcodes PARAMS ((void)); +static void write_template PARAMS ((void)); + +long Opcodes[512]; +static int curop=0; + +int +main (argc, argv) + int argc; + char *argv[]; +{ + if ((argc > 1) && (strcmp (argv[1], "-h") == 0)) + write_header(); + else if ((argc > 1) && (strcmp (argv[1], "-t") == 0)) + write_template (); + else + write_opcodes(); + return 0; +} + + +static void +write_header () +{ + struct mn10300_opcode *opcode; + + for (opcode = (struct mn10300_opcode *)mn10300_opcodes; opcode->name; opcode++) + printf("void OP_%X PARAMS ((unsigned long, unsigned long));\t\t/* %s */\n", + opcode->opcode, opcode->name); +} + + +/* write_template creates a file all required functions, ready */ +/* to be filled out */ + +static void +write_template () +{ + struct mn10300_opcode *opcode; + int i,j; + + printf ("#include \"mn10300_sim.h\"\n"); + printf ("#include \"simops.h\"\n"); + + for (opcode = (struct mn10300_opcode *)mn10300_opcodes; opcode->name; opcode++) + { + printf("/* %s */\nvoid\nOP_%X (insn, extension)\n unsigned long insn, extension;\n{\n", opcode->name, opcode->opcode); + + /* count operands */ + j = 0; + for (i = 0; i < 6; i++) + { + int flags = mn10300_operands[opcode->operands[i]].flags; + + if (flags) + j++; + } + switch (j) + { + case 0: + printf ("printf(\" %s\\n\");\n", opcode->name); + break; + case 1: + printf ("printf(\" %s\\t%%x\\n\", OP[0]);\n", opcode->name); + break; + case 2: + printf ("printf(\" %s\\t%%x,%%x\\n\",OP[0],OP[1]);\n", + opcode->name); + break; + case 3: + printf ("printf(\" %s\\t%%x,%%x,%%x\\n\",OP[0],OP[1],OP[2]);\n", + opcode->name); + break; + default: + fprintf (stderr,"Too many operands: %d\n", j); + } + printf ("}\n\n"); + } +} + +static void +write_opcodes () +{ + struct mn10300_opcode *opcode; + int i, j; + int numops; + + /* write out opcode table */ + printf ("#include \"mn10300_sim.h\"\n"); + printf ("#include \"simops.h\"\n\n"); + printf ("struct simops Simops[] = {\n"); + + for (opcode = (struct mn10300_opcode *)mn10300_opcodes; opcode->name; opcode++) + { + int size; + + if (opcode->format == FMT_S0) + size = 1; + else if (opcode->format == FMT_S1 + || opcode->format == FMT_D0) + size = 2; + else if (opcode->format == FMT_S2 + || opcode->format == FMT_D1) + size = 3; + else if (opcode->format == FMT_S4) + size = 5; + else if (opcode->format == FMT_D2) + size = 4; + else if (opcode->format == FMT_D4) + size = 6; + else + size = 7; + + printf (" { 0x%x,0x%x,OP_%X,%d,%d,", + opcode->opcode, opcode->mask, opcode->opcode, + size, opcode->format); + + Opcodes[curop++] = opcode->opcode; + + /* count operands */ + j = 0; + for (i = 0; i < 6; i++) + { + int flags = mn10300_operands[opcode->operands[i]].flags; + + if (flags) + j++; + } + printf ("%d,{",j); + + j = 0; + numops = 0; + for (i = 0; i < 6; i++) + { + int flags = mn10300_operands[opcode->operands[i]].flags; + int shift = mn10300_operands[opcode->operands[i]].shift; + + if (flags) + { + if (j) + printf (", "); + printf ("%d,%d,%d", shift, + mn10300_operands[opcode->operands[i]].bits,flags); + j = 1; + numops++; + } + } + + switch (numops) + { + case 0: + printf ("0,0,0"); + case 1: + printf (",0,0,0"); + } + + printf ("}},\n"); + } + printf ("{ 0,0,NULL,0,0,0,{0,0,0,0,0,0}},\n};\n"); +}

gencode.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: configure.in =================================================================== --- configure.in (nonexistent) +++ configure.in (revision 1765) @@ -0,0 +1,37 @@ +dnl Process this file with autoconf to produce a configure script. +sinclude(../common/aclocal.m4) +dnl 2.12 botches SHELL substitution +AC_PREREQ(2.12.1)dnl +AC_INIT(Makefile.in) + +SIM_AC_COMMON + +SIM_AC_OPTION_ENDIAN(LITTLE_ENDIAN) +SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT) +SIM_AC_OPTION_HOSTENDIAN +SIM_AC_OPTION_WARNINGS +SIM_AC_OPTION_RESERVED_BITS +SIM_AC_OPTION_BITSIZE(32,31) +SIM_AC_OPTION_INLINE() +SIM_AC_OPTION_HARDWARE(yes,,mn103cpu mn103int mn103tim mn103ser mn103iop) + +AC_CHECK_FUNCS(time chmod utime fork execve execv chown) +AC_CHECK_HEADERS(unistd.h stdlib.h string.h strings.h utime.h time.h) + +# +# Enable common +# +AC_ARG_ENABLE(sim-common, +[ --enable-sim-common Enable common simulator], +[case "${enableval}" in + yes) sim_gen="-DWITH_COMMON=1"; mn10300_common="WITH";; + no) sim_gen="-DWITH_COMMON=0"; mn10300_common="WITHOUT";; + *) AC_MSG_ERROR("Unknown value $enableval passed to --enable-sim-common"); sim_gen="";; +esac +if test x"$silent" != x"yes" && test x"$sim_gen" != x""; then + echo "Setting sim_common = $sim_common" 6>&1 +fi],[sim_gen="-DWITH_COMMON=1"; mn10300_common="WITH"])dnl +AC_SUBST(sim_gen) +AC_SUBST(mn10300_common) + +SIM_AC_OUTPUT

configure.in Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: ChangeLog =================================================================== --- ChangeLog (nonexistent) +++ ChangeLog (revision 1765) @@ -0,0 +1,978 @@ +2001-05-06 Jim Blandy + + * mn10300.igen: Doc fixes. + +2001-04-26 Alexandre Oliva + + * Makefile.in (idecode.o, op_utils.o, semantics.o, simops.o): + Depend on targ-vals.h. + +2001-04-15 J.T. Conklin + + * Makefile.in (simops.o): Add simops.h to dependency list. + +Wed Aug 9 02:24:53 2000 Graham Stott + + * am33.igen: Warning clean-up. + (movm): Initialize PC and mask. + (mov, movbu, movhu): Set srcreg2 from RI0. + (bsch): Initialize c. + (sat16_cmp): Actually do the comparison. + (mov_llt): Do not overwrite dstreg with uninitialized variable. + +Tue May 23 21:39:23 2000 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2000-05-22 Alexandre Oliva + + * am33.igen: Fix leading comments of SP-relative offset insns that + referred to other registers. Make their offsets unsigned. + +2000-05-18 Alexandre Oliva + + * mn10300_sim.h (genericAdd, genericSub, genericCmp, genericOr, + genericXor, genericBtst): Use `unsigned32'. + * op_utils.c: Likewise. + * mn10300.igen, am33.igen: Use `unsigned32', `signed32', + `unsigned64' or `signed64' where type width is relevant. + +2000-04-25 Alexandre Oliva + + * am33.igen (inc4 Rn): Use genericAdd so as to modify flags. + +2000-04-09 Alexandre Oliva + + * am33.igen: Make SP-relative offsets unsigned. Add `*am33' for + some instructions that were missing it. + +2000-03-03 Alexandre Oliva + + * Makefile.in (IGEN_INSN): Added am33.igen. + +Thu Sep 2 18:15:53 1999 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Jul 13 13:26:20 1999 Andrew Cagney + + * interp.c: Clarify error message reporting an unknown board. + +1999-05-08 Felix Lee + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +1999-04-16 Frank Ch. Eigler + + * interp.c (program_interrupt): Detect undesired recursion using + static flag. Set NMIRC register's SYSEF flag during + --board=stdeval1 mode. + * dv-mn103-int.c (write_icr): Add backdoor address to allow CPU to + set SYSEF flag. + +1999-04-02 Keith Seitz + + * Makefile.in (SIM_EXTRA_CFLAGS): Define a POLL_QUIT_INTERVAL + for use in the simulator so that the poll_quit callback is + not called too often. + +Tue Mar 9 21:26:41 1999 Andrew Cagney + + * dv-mn103int.c (mn103int_ioctl): Return something. + * dv-mn103tim.c (write_tm6md): GCC suggested parentheses around && + within ||. + +Tue Feb 16 23:57:17 1999 Jeffrey A Law (law@cygnus.com) + + * mn10300.igen (retf): Fix return address computation and store + the new pc value into nia. + +1998-12-29 Frank Ch. Eigler + + * Makefile.in (WITH_COMMON_OBJS): Build also dv-sockser.o. + * interp.c (sim_open): Add stub mn103002 cache control memory regions. + Set OPERATING_ENVIRONMENT on "stdeval1" board. + (mn10300_core_signal): New function to intercept memory errors. + (program_interrupt): New function to dispatch to exception vector + (mn10300_exception_*): New functions to snapshot pre/post exception + state. + * sim-main.h (SIM_CORE_SIGNAL): Define hook - call mn10300_core_signal. + (SIM_ENGINE_HALT_HOOK): Do nothing. + (SIM_CPU_EXCEPTION*): Define hooks to call mn10300_cpu_exception*(). + (_sim_cpu): Add exc_* fields to store register value snapshots. + * dv-mn103ser.c (*): Support dv-sockser backend for UART I/O. + Various endianness and warning fixes. + * mn10300.igen (illegal): Call program_interrupt on error. + (break): Call program_interrupt on breakpoint + + Several changes from and + merged in: + * dv-mn103int.c (mn103int_ioctl): New function for NMI + generation. (mn103int_finish): Install it as ioctl handler. + * dv-mn103tim.c: Support timer 6 specially. Endianness fixes. + +Wed Oct 14 12:11:05 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen: Allow autoincrement stores using the same register + for source and destination operands. + +Mon Aug 31 10:19:55 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen: Reverse HI/LO outputs of 4 operand "mul" and "mulu". + +Fri Aug 28 14:40:49 1998 Joyce Janczyn + + * interp.c (sim_open): Check for invalid --board option, fix + indentation, allocate memory for mem control and DMA regs. + +Wed Aug 26 09:29:38 1998 Joyce Janczyn + + * mn10300.igen (div,divu): Fix divide instructions so divide by 0 + behaves like the hardware. + +Mon Aug 24 11:50:09 1998 Joyce Janczyn + + * sim-main.h (SIM_HANDLES_LMA): Define SIM_HANDLES_LMA. + +Wed Aug 12 12:36:07 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen: Handle case where first DSP operation modifies a + register used in the second DSP operation correctly. + +Tue Jul 28 10:10:25 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen: Detect cases where two operands must not match for + DSP instructions too. + +Mon Jul 27 12:04:17 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen: Detect cases where two operands must not match in + non-DSP instructions. + +Fri Jul 24 18:15:21 1998 Joyce Janczyn + + * op_utils.c (do_syscall): Rewrite to use common/syscall.c. + (syscall_read_mem, syscall_write_mem): New functions for syscall + callbacks. + * mn10300_sim.h: Add prototypes for syscall_read_mem and + syscall_write_mem. + * mn10300.igen: Change C++ style comments to C style comments. + Check for divide by zero in div and divu ops. + +Fri Jul 24 12:49:28 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen (translate_xreg): New function. Use it as needed. + +Thu Jul 23 10:05:28 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen: Add some missing instructions. + + * am33.igen: Autoincrement loads/store fixes. + +Tue Jul 21 09:48:14 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen: Add mov_lCC DSP instructions. + + * am33.igen: Add most am33 DSP instructions. + +Thu Jul 9 10:06:55 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300.igen: Fix Z bit for addc and subc instructions. + Minor fixes in multiply/divide patterns. + + * am33.igen: Add missing mul[u] imm32,Rn. Fix condition code + handling for many instructions. Fix sign extension for some + 24bit immediates. + + * am33.igen: Fix Z bit for remaining addc/subc instructions. + Do not sign extend immediate for mov imm,XRn. + More random mul, mac & div fixes. + Remove some unused variables. + Sign extend 24bit displacement in memory addresses. + + * am33.igen: Fix Z bit for addc Rm,Rn and subc Rm,Rn. Various + fixes to 2 register multiply, divide and mac instructions. Set + Z,N correctly for sat16. Sign extend 24 bit immediate for add, + and sub instructions. + + * am33.igen: Add remaining non-DSP instructions. + +Wed Jul 8 16:29:12 1998 Jeffrey A Law (law@cygnus.com) + + * am33.igen (translate_rreg): New function. Use it as appropriate. + + * am33.igen: More am33 instructions. Fix "div". + +Mon Jul 6 15:39:22 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300.igen: Add am33 support. + + * Makefile.in: Use multi-sim to support both a mn10300 and am33 + simulator. + + * am33.igen: Add many more am33 instructions. + +Wed Jul 1 17:07:09 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300_sim.h (FETCH24): Define. + + * mn10300_sim.h: Add defines for some registers found on the AM33. + * am33.igen: New file with some am33 support. + +Tue Jun 30 11:23:20 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300_sim.h: Include bfd.h + (struct state): Add more room for processor specific registers. + (REG_E0): Define. + +Thu Jun 25 10:12:03 1998 Joyce Janczyn + + * dv-mn103tim.c: Include sim-assert.h + * dv-mn103ser.c (do_polling_event): Check for incoming data on + serial line and schedule next polling event. + (read_status_reg): schedule events to check for incoming data on + serial line and issue interrupt if necessary. + +Fri Jun 19 16:47:27 1998 Joyce Janczyn + + * interp.c (sim_open): hook up serial 1 and 2 ports properly (typo). + +Fri Jun 19 11:59:26 1998 Joyce Janczyn + + * interp.c (board): Rename am32 to stdeval1 as this is the name + consistently used to refer to the mn1030002 board. + +Thu June 18 14:37:14 1998 Joyce Janczyn + * interp.c (sim_open): Fix typo in address of EXTMD register + (0x34000280, not 0x3400280). + +Wed Jun 17 18:00:18 1998 Jeffrey A Law (law@cygnus.com) + + * simops.c (syscall): Handle change in opcode # for syscall. + * mn10300.igen (syscall): Likewise. + +Tue June 16 09:36:21 1998 Joyce Janczyn + * dv-mn103int.c (mn103int_finish): Regular interrupts (not NMI or + reset) are not enabled on reset. + +Sun June 14 17:04:00 1998 Joyce Janczyn + * dv-mn103iop.c (write_*_reg): Check for attempt to write r/o + register bits. + * dv-mn103ser.c: Fill in methods for reading and writing to serial + device registers. + * interp.c (sim_open): Make the serial device a polling device. + +Fri June 12 16:24:00 1998 Joyce Janczyn + * dv-mn103iop.c: New file for handling am32 io ports. + * configure.in: Add mn103iop to hw_device list. + * configure: Re-generate. + * interp.c (sim_open): Create io port device. + +Wed June 10 14:34:00 1998 Joyce Janczyn + * dv-mn103int.c (external_group): Use enumerated types to access + correct group addresses. + * dv-mn103tim.c (do_counter_event): Underflow of cascaded timer + triggers an interrupt on the higher-numbered timer's port. + +Mon June 8 13:30:00 1998 Joyce Janczyn + * interp.c: (mn10300_option_handler): New function parses arguments + using sim-options. + * (board): Add --board option for specifying am32. + * (sim_open): Create new timer and serial devices and control + configuration of other am32 devices via board option. + * dv-mn103tim.c, dv-mn103ser.c: New files for timers and serial devices. + * dv-mn103cpu.c: Fix typos in opening comments. + * dv-mn103int.c: Adjust interrupt controller settings for am32 instead of am30. + * configure.in: Add mn103tim and mn103ser to hw_device list. + * configure: Re-generate. + +Mon May 25 20:50:35 1998 Andrew Cagney + + * dv-mn103int.c, dv-mn103cpu.c: Rename *_callback to *_method. + + * dv-mn103cpu.c, dv-mn103int.c: Include hw-main.h and + sim-main.h. Declare a struct hw_descriptor instead of struct + hw_device_descriptor. + +Mon May 25 17:33:33 1998 Andrew Cagney + + * dv-mn103cpu.c (struct mn103cpu): Change type of pending_handler + to struct hw_event. + +Fri May 22 12:17:41 1998 Andrew Cagney + + * configure.in (SIM_AC_OPTION_HARDWARE): Add argument "yes". + +Wed May 6 13:29:06 1998 Andrew Cagney + + * interp.c (sim_open): Create a polling PAL device. + +Fri May 1 16:39:15 1998 Andrew Cagney + + * dv-mn103int.c (mn103int_port_event): + (mn103int_port_event): + (mn103int_io_read_buffer): + (mn103int_io_write_buffer): + + * dv-mn103cpu.c (deliver_mn103cpu_interrupt): Drop CPU/CIA args. + (mn103cpu_port_event): Ditto. + (mn103cpu_io_read_buffer): Ditto. + (mn103cpu_io_write_buffer): Ditto. + +Tue Apr 28 18:33:31 1998 Geoffrey Noer + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sun Apr 26 15:31:55 1998 Tom Tromey + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Sun Apr 26 15:19:55 1998 Tom Tromey + + * acconfig.h: New file. + * configure.in: Reverted change of Apr 24; use sinclude again. + +Fri Apr 24 14:16:40 1998 Tom Tromey + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Fri Apr 24 11:19:07 1998 Tom Tromey + + * configure.in: Don't call sinclude. + +Tue Apr 14 10:03:02 1998 Andrew Cagney + + * mn10300_sim.h: Declare all functions in op_utils.c using + INLINE_SIM_MAIN. + * op_utils.c: Ditto. + * sim-main.c: New file. Include op_utils.c. + + * mn10300.igen (mov, cmp): Use new igen operators `!' and `=' to + differentiate between MOV/CMP immediate/register instructions. + + * configure.in (SIM_AC_OPTION_INLINE): Add and enable. + * configure: Regenerate. + +Sat Apr 4 20:36:25 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Mar 27 16:15:52 1998 Andrew Cagney + + * interp.c (hw): Delete variable, moved to SIM_DESC. + (sim_open): Delete calls to hw_tree_create, hw_tree_finish. + Handled by sim-module. + (sim_open): Do not anotate tree with trace properties, handled by + sim-hw.c + (sim_open): Call sim_hw_parse instead of hw_tree_parse. + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Thu Mar 26 20:46:18 1998 Stu Grossman + + * dv-mn103cpu.c (deliver_mn103cpu_interrupt): Save the entire PC + on the stack when delivering interrupts (not just the lower + half)... + * mn10300.igen (mov (Di,Am),Dn): Fix decode. Registers were + specified in the wrong order. + +Fri Mar 27 00:56:40 1998 Andrew Cagney + + * dv-mn103cpu.c (deliver_mn103cpu_interrupt): Stop loss of + succeeding interrupts, clear pending_handler when the handler + isn't re-scheduled. + +Thu Mar 26 10:11:01 1998 Stu Grossman + + * Makefile.in (tmp-igen): Prefix all usage of move-if-change + script with $(SHELL) to make NT native builds happy. + * configure: Regenerate because of change to ../common/aclocal.m4. + +Thu Mar 26 11:22:31 1998 Andrew Cagney + + * configure.in: Make --enable-sim-common the default. + * configure: Re-generate. + + * sim-main.h (CIA_GET, CIA_SET): Save/restore current instruction + address into Sate.regs[REG_PC] instead of common struct. + +Wed Mar 25 17:42:00 1998 Joyce Janczyn + + * mn10300.igen (cmp imm8,An): Do not sign extend imm8 value. + +Wed Mar 25 12:08:00 1998 Joyce Janczyn + + * simops.c (OP_F0FD): Initialise variable 'sp'. + +Thu Mar 26 00:21:32 1998 Andrew Cagney + + * dv-mn103int.c (decode_group): A group register every 4 bytes not + 8. + (write_icr): Rewrite equation updating request field. + (read_iagr): Fix check that interrupt is still pending. + +Wed Mar 25 16:14:50 1998 Andrew Cagney + + * interp.c (sim_open): Tidy up device creation. + + * dv-mn103int.c (mn103int_port_event): Drive NMI with non-zero + value. + (mn103int_io_read_buffer): Convert absolute address to register + block offsets. + (read_icr, write_icr): Convert block offset into group offset. + +Wed Mar 25 15:08:49 1998 Andrew Cagney + + * interp.c (sim_open): Create second 1mb memory region at + 0x40000000. + (sim_open): Create a device tree. + (sim-hw.h): Include. + (do_interrupt): Delete, needs to use dv-mn103cpu.c + + * dv-mn103int.c, dv-mn103cpu.c: New files. + +Wed Mar 25 08:47:38 1998 Andrew Cagney + + * mn10300_sim.h (EXTRACT_PSW_LM, INSERT_PSW_LM, PSW_IE, PSW_LM): + Define. + (SP): Define. + +Wed Mar 25 12:35:29 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Mar 25 10:24:48 1998 Andrew Cagney + + * interp.c (sim-options.h): Include. + (sim_kind, myname): Declare when not using common framework. + + * mn10300_sim.h (do_syscall, generic*): Provide prototypes for + functions found in op_utils.c + + * mn10300.igen (add): Discard unused variables. + + * configure, config.in: Re-generate with autoconf 2.12.1. + +Tue Mar 24 15:27:00 1998 Joyce Janczyn + + Add support for --enable-sim-common option. + * Makefile.in (WITHOUT_COMMON_OBJS): Files included if + ! --enable-sim-common + (WITH_COMMON_OBJS): Files included if --enable-sim-common. + (MN10300_OBJS,MN10300_INTERP_DEP): New variables. + (SIM_OBJS): Rewrite. + ({WITHOUT,WITH}_COMMON_RUN_OBJS,SIM_RUN_OBJS): New variables. + (SIM_EXTRA_CFLAGS): New variable. + (clean-extra): Clean up igen files. + (../igen/igen,clean-igen,tmp-igen): New rules. + * configure.in: Add support for common framework via + --enable-sim-common. + * configure: Regenerate. + * interp.c: #include sim-main if WITH_COMMON, not mn10300_sim.h. + (hash,dispatch,sim_size): Don't compile if ! WITH_COMMON. + (init_system,sim_write,compare_simops): Likewise. + (sim_set_profile,sim_set_profile_size): Likewise. + (sim_stop,sim_resume,sim_trace,sim_info): Likewise. + (sim_set_callbacks,sim_stop_reason,sim_read,sim_load): Likewise. + (enum interrupt_type): New enum. + (interrupt_names): New global. + (do_interrupt): New function. + (sim_open): Define differently if WITH_COMMON. + (sim_close,sim_create_inferior,sim_do_command): Likewise. + * mn10300_sim.h ({load,store}_{byte,half,word}): Define versions + for WITH_COMMON. + * mn10300.igen: New file. + * mn10300.dc: New file. + * op_utils.c: New file. + * sim-main.h: New file. + +Wed Mar 18 12:38:12 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Feb 27 18:36:04 1998 Jeffrey A Law (law@cygnus.com) + + * simops.c (inc): Fix typo. + +Wed Feb 25 01:59:29 1998 Jeffrey A Law (law@cygnus.com) + + * simops.c (signed multiply instructions): Cast input operands to + signed32 before casting them to signed64 so that the sign bit + is propagated properly. + +Mon Feb 23 20:23:19 1998 Mark Alexander + + * Makefile.in: Last change was bad. Define NL_TARGET + so that targ-vals.h will be used instead of syscall.h. + * simops.c: Use targ-vals.h instead of syscall.h. + (OP_F020): Disable unsupported system calls. + +Mon Feb 23 09:44:38 1998 Mark Alexander + + * Makefile.in: Get header files from libgloss/mn10300/sys. + +Sun Feb 22 16:02:24 1998 Jeffrey A Law (law@cygnus.com) + + * simops.c: Include sim-types.h. + +Wed Feb 18 13:07:08 1998 Jeffrey A Law (law@cygnus.com) + + * simops.c (multiply instructions): Cast input operands to a + signed64/unsigned64 type as appropriate. + +Tue Feb 17 12:47:16 1998 Andrew Cagney + + * interp.c (sim_store_register, sim_fetch_register): Pass in + length parameter. Return -1. + +Sun Feb 1 16:47:51 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sat Jan 31 18:15:41 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Jan 19 22:26:29 1998 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Dec 15 23:17:11 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Thu Dec 4 09:21:05 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Nov 11 10:38:52 1997 Jeffrey A Law (law@cygnus.com) + + * simops.c (call:16 call:32): Stack adjustment is determined solely + by the imm8 field. + +Wed Oct 22 14:43:00 1997 Andrew Cagney + + * interp.c (sim_load): Pass lma_p and sim_write args to + sim_load_file. + +Tue Oct 21 10:12:03 1997 Jeffrey A Law (law@cygnus.com) + + * simops.c: Correctly handle register restores for "ret" and "retf" + instructions. + +Fri Oct 3 09:28:00 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Sep 24 17:38:57 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Sep 23 11:04:38 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Sep 22 11:46:20 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Sep 19 17:45:25 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Sep 15 17:36:15 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Thu Sep 4 17:21:23 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Aug 27 18:13:22 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Tue Aug 26 10:41:07 1997 Andrew Cagney + + * interp.c (sim_kill): Delete. + (sim_create_inferior): Add ABFD argument. + (sim_load): Move setting of PC from here. + (sim_create_inferior): To here. + +Mon Aug 25 17:50:22 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Mon Aug 25 16:14:44 1997 Andrew Cagney + + * interp.c (sim_open): Add ABFD argument. + +Tue Jun 24 13:46:20 1997 Jeffrey A Law (law@cygnus.com) + + * interp.c (sim_resume): Clear State.exited. + (sim_stop_reason): If State.exited is nonzero, then indicate that + the simulator exited instead of stopped. + * mn10300_sim.h (struct _state): Add exited field. + * simops.c (syscall): Set State.exited for SYS_exit. + +Wed Jun 11 22:07:56 1997 Jeffrey A Law (law@cygnus.com) + + * simops.c: Fix thinko in last change. + +Tue Jun 10 12:31:32 1997 Jeffrey A Law (law@cygnus.com) + + * simops.c: "call" stores the callee saved registers into the + stack! Update the stack pointer properly when done with + register saves. + + * simops.c: Fix return address computation for "call" instructions. + +Thu May 22 01:43:11 1997 Jeffrey A Law (law@cygnus.com) + + * interp.c (sim_open): Fix typo. + +Wed May 21 23:27:58 1997 Jeffrey A Law (law@cygnus.com) + + * interp.c (sim_resume): Add missing case in big switch + statement (for extb instruction). + +Tue May 20 17:51:30 1997 Jeffrey A Law (law@cygnus.com) + + * interp.c: Replace all references to load_mem and store_mem + with references to load_byte, load_half, load_3_byte, load_word + and store_byte, store_half, store_3_byte, store_word. + (INLINE): Delete definition. + (load_mem_big): Likewise. + (max_mem): Make it global. + (dispatch): Make this function inline. + (load_mem, store_mem): Delete functions. + * mn10300_sim.h (INLINE): Define. + (RLW): Delete unused definition. + (load_mem, store_mem): Delete declarations. + (load_mem_big): New definition. + (load_byte, load_half, load_3_byte, load_word): New functions. + (store_byte, store_half, store_3_byte, store_word): New functions. + * simops.c: Replace all references to load_mem and store_mem + with references to load_byte, load_half, load_3_byte, load_word + and store_byte, store_half, store_3_byte, store_word. + +Tue May 20 10:21:51 1997 Andrew Cagney + + * interp.c (sim_open): Add callback to arguments. + (sim_set_callbacks): Delete SIM_DESC argument. + +Mon May 19 13:54:22 1997 Jeffrey A Law (law@cygnus.com) + + * interp.c (dispatch): Make this an inline function. + + * simops.c (syscall): Use callback->write regardless of + what file descriptor we're writing too. + +Sun May 18 16:46:31 1997 Jeffrey A Law (law@cygnus.com) + + * interp.c (load_mem_big): Remove function. It's now a macro + defined elsewhere. + (compare_simops): New function. + (sim_open): Sort the Simops table before inserting entries + into the hash table. + * mn10300_sim.h: Remove unused #defines. + (load_mem_big): Define. + +Fri May 16 16:36:17 1997 Jeffrey A Law (law@cygnus.com) + + * interp.c (load_mem): If we get a load from an out of range + address, abort. + (store_mem): Likewise for stores. + (max_mem): New variable. + +Tue May 6 13:24:36 1997 Jeffrey A Law (law@cygnus.com) + + * mn10300_sim.h: Fix ordering of bits in the PSW. + + * interp.c: Improve hashing routine to avoid long list + traversals for common instructions. Add HASH_STAT support. + Rewrite opcode dispatch code using a big switch instead of + cascaded if/else statements. Avoid useless calls to load_mem. + +Mon May 5 18:07:48 1997 Jeffrey A Law (law@cygnus.com) + + * mn10300_sim.h (struct _state): Add space for mdrq register. + (REG_MDRQ): Define. + * simops.c: Don't abort for trap. Add support for the extended + instructions, "getx", "putx", "mulq", "mulqu", "sat16", "sat24", + and "bsch". + +Thu Apr 24 00:39:51 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Apr 18 14:04:04 1997 Andrew Cagney + + * interp.c (sim_stop): Add stub function. + +Thu Apr 17 03:26:59 1997 Doug Evans + + * Makefile.in (SIM_OBJS): Add sim-load.o. + * interp.c (sim_kind, myname): New static locals. + (sim_open): Set sim_kind, myname. Ignore -E arg. + (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to + load file into simulator. Set start address from bfd. + (sim_create_inferior): Return SIM_RC. Delete arg start_address. + +Wed Apr 16 19:30:44 1997 Andrew Cagney + + * simops.c (OP_F020): SYS_execv, SYS_time, SYS_times, SYS_utime + only include if implemented by host. + (OP_F020): Typecast arg passed to time function; + +Mon Apr 7 23:57:49 1997 Jeffrey A Law (law@cygnus.com) + + * simops.c (syscall): Handle new mn10300 calling conventions. + +Mon Apr 7 15:45:02 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Fri Apr 4 20:02:37 1997 Ian Lance Taylor + + * Makefile.in: Change mn10300-opc.o to m10300-opc.o, to match + corresponding change in opcodes directory. + +Wed Apr 2 15:06:28 1997 Doug Evans + + * interp.c (sim_open): New arg `kind'. + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Apr 2 14:34:19 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Thu Mar 20 11:58:02 1997 Jeffrey A Law (law@cygnus.com) + + * simops.c: Fix register extraction for a two "movbu" variants. + Somewhat simplify "sub" instructions. + Correctly sign extend operands for "mul". Put the correct + half of the result in MDR for "mul" and "mulu". + Implement remaining instructions. + Tweak opcode for "syscall". + +Tue Mar 18 14:21:21 1997 Jeffrey A Law (law@cygnus.com) + + * simops.c: Do syscall emulation in "syscall" instruction. Add + dummy "trap" instruction. + +Wed Mar 19 01:14:00 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Mar 17 15:10:07 1997 Andrew Cagney + + * configure: Re-generate. + +Fri Mar 14 10:34:11 1997 Michael Meissner + + * configure: Regenerate to track ../common/aclocal.m4 changes. + +Thu Mar 13 12:54:45 1997 Doug Evans + + * interp.c (sim_open): New SIM_DESC result. Argument is now + in argv form. + (other sim_*): New SIM_DESC argument. + +Wed Mar 12 15:04:00 1997 Jeffrey A Law (law@cygnus.com) + + * simops.c: Fix carry bit computation for "add" instructions. + + * simops.c: Fix typos in bset insns. Fix arguments to store_mem + for bset imm8,(d8,an) and bclr imm8,(d8,an). + +Wed Mar 5 15:00:10 1997 Jeffrey A Law (law@cygnus.com) + + * simops.c: Fix register references when computing Z and N bits + for lsr imm8,dn. + +Tue Feb 4 13:33:30 1997 Doug Evans + + * Makefile.in (@COMMON_MAKEFILE_FRAG): Use + COMMON_{PRE,POST}_CONFIG_FRAG instead. + * configure.in: sinclude ../common/aclocal.m4. + * configure: Regenerated. + +Fri Jan 24 10:47:25 1997 Jeffrey A Law (law@cygnus.com) + + * interp.c (init_system): Allocate 2^19 bytes of space for the + simulator. + +Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com) + + * configure configure.in Makefile.in: Update to new configure + scheme which is more compatible with WinGDB builds. + * configure.in: Improve comment on how to run autoconf. + * configure: Re-run autoconf to get new ../common/aclocal.m4. + * Makefile.in: Use autoconf substitution to install common + makefile fragment. + +Tue Jan 21 15:03:04 1997 Jeffrey A Law (law@cygnus.com) + + * simops.c: Undo last change to "rol" and "ror", original code + was correct! + +Thu Jan 16 11:28:14 1997 Jeffrey A Law (law@cygnus.com) + + * simops.c: Fix "rol" and "ror". + +Wed Jan 15 06:45:58 1997 Jeffrey A Law (law@cygnus.com) + + * simops.c: Fix typo in last change. + +Mon Jan 13 13:22:35 1997 Jeffrey A Law (law@cygnus.com) + + * simops.c: Use REG macros in few places not using them yet. + +Mon Jan 6 16:21:19 1997 Jeffrey A Law (law@cygnus.com) + + * mn10300_sim.h (struct _state): Fix number of registers! + +Tue Dec 31 16:20:41 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300_sim.h (struct _state): Put all registers into a single + array to make gdb implementation easier. + (REG_*): Add definitions for all registers in the state array. + (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros. + * simops.c: Related changes. + +Wed Dec 18 10:10:45 1996 Jeffrey A Law (law@cygnus.com) + + * interp.c (sim_resume): Handle 0xff as a single byte insn. + + * simops.c: Fix overflow computation for "add" and "inc" + instructions. + +Mon Dec 16 10:03:52 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c: Handle "break" instruction. + + * simops.c: Fix restoring the PC for "ret" and "retf" instructions. + +Wed Dec 11 09:53:10 1996 Jeffrey A Law (law@cygnus.com) + + * gencode.c (write_opcodes): Also write out the format of the + opcode. + * mn10300_sim.h (simops): Add "format" field. + * interp.c (sim_resume): Deal with endianness issues here. + +Tue Dec 10 15:05:37 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c (REG0_4): Define. + Use REG0_4 for indexed loads/stores. + +Sat Dec 7 09:50:28 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c (REG0_16): Fix typo. + +Fri Dec 6 14:13:34 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c: Call abort for any instruction that's not currently + simulated. + + * simops.c: Define accessor macros to extract register + values from instructions. Use them consistently. + + * interp.c: Delete unused global variable "OP". + (sim_resume): Remove unused variable "opcode". + * simops.c: Fix some uninitialized variable problems, add + parens to fix various -Wall warnings. + + * gencode.c (write_header): Add "insn" and "extension" arguments + to the OP_* declarations. + (write_template): Similarly for function templates. + * interp.c (insn, extension): Remove global variables. Instead + pass them as arguments to the OP_* functions. + * mn10300_sim.h: Remove decls for "insn" and "extension". + * simops.c (OP_*): Accept "insn" and "extension" as arguments + instead of using globals. + +Thu Dec 5 22:26:31 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)" + + * simops.c: Fix thinkos in last change to "inc dn". + +Wed Dec 4 10:57:53 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c: "add imm,sp" does not effect the condition codes. + "inc dn" does effect the condition codes. + +Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c: Treat both operands as signed values for + "div" instruction. + + * simops.c: Fix simulation of division instructions. + Fix typos/thinkos in several "cmp" and "sub" instructions. + +Mon Dec 2 12:31:40 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c: Fix carry bit handling in "sub" and "cmp" + instructions. + + * simops.c: Fix "mov imm8,an" and "mov imm16,dn". + +Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c: Fix overflow computation for many instructions. + + * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)". + + * simops.c: Fix "mov am, dn". + + * simops.c: Fix more bugs in "add imm,an" and + "add imm,dn". + +Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c: Fix bugs in "movm" and "add imm,an". + + * simops.c: Don't lose the upper 24 bits of the return + pointer in "call" and "calls" instructions. Rough cut + at emulated system calls. + + * simops.c: Implement the remaining 5, 6 and 7 byte instructions. + + * simops.c: Implement remaining 4 byte instructions. + + * simops.c: Implement remaining 3 byte instructions. + + * simops.c: Implement remaining 2 byte instructions. Call + abort for instructions we're not implementing now. + +Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com) + + * simops.c: Implement lots of random instructions. + + * simops.c: Implement "movm" and "bCC" insns. + + * mn10300_sim.h (_state): Add another register (MDR). + (REG_MDR): Define. + * simops.c: Implement "cmp", "calls", "rets", "jmp" and + a few additional random insns. + + * mn10300_sim.h (PSW_*): Define for CC status tracking. + (REG_D0, REG_A0, REG_SP): Define. + * simops.c: Implement "add", "addc" and a few other random + instructions. + + * gencode.c, interp.c: Snapshot current simulator code. + +Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com) + + * Makefile.in, config.in, configure, configure.in: New files. + * gencode.c, interp.c, mn10300_sim.h, simops.c: New files. +

ChangeLog Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sim-main.c =================================================================== --- sim-main.c (nonexistent) +++ sim-main.c (revision 1765) @@ -0,0 +1,4 @@ +#ifndef SIM_MAIN_C +#define SIM_MAIN_C +#include "op_utils.c" +#endif

sim-main.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: simops.c =================================================================== --- simops.c (nonexistent) +++ simops.c (revision 1765) @@ -0,0 +1,3239 @@ +#include "config.h" + +#include +#ifdef HAVE_UNISTD_H +#include +#endif +#include "mn10300_sim.h" +#include "simops.h" +#include "sim-types.h" +#include "targ-vals.h" +#include "bfd.h" +#include +#include +#include +#include + +#define REG0(X) ((X) & 0x3) +#define REG1(X) (((X) & 0xc) >> 2) +#define REG0_4(X) (((X) & 0x30) >> 4) +#define REG0_8(X) (((X) & 0x300) >> 8) +#define REG1_8(X) (((X) & 0xc00) >> 10) +#define REG0_16(X) (((X) & 0x30000) >> 16) +#define REG1_16(X) (((X) & 0xc0000) >> 18) + +/* mov imm8, dn */ +void OP_8000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_8 (insn)] = SEXT8 (insn & 0xff); +} + +/* mov dm, dn */ +void OP_80 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)]; +} + +/* mov dm, an */ +void OP_F1E0 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)]; +} + +/* mov am, dn */ +void OP_F1D0 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)]; +} + +/* mov imm8, an */ +void OP_9000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG0_8 (insn)] = insn & 0xff; +} + +/* mov am, an */ +void OP_90 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)]; +} + +/* mov sp, an */ +void OP_3C (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_SP]; +} + +/* mov am, sp */ +void OP_F2F0 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_SP] = State.regs[REG_A0 + REG1 (insn)]; +} + +/* mov psw, dn */ +void OP_F2E4 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0 (insn)] = PSW; +} + +/* mov dm, psw */ +void OP_F2F3 (insn, extension) + unsigned long insn, extension; +{ + PSW = State.regs[REG_D0 + REG1 (insn)]; +} + +/* mov mdr, dn */ +void OP_F2E0 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDR]; +} + +/* mov dm, mdr */ +void OP_F2F2 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_MDR] = State.regs[REG_D0 + REG1 (insn)]; +} + +/* mov (am), dn */ +void OP_70 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG1 (insn)] + = load_word (State.regs[REG_A0 + REG0 (insn)]); +} + +/* mov (d8,am), dn */ +void OP_F80000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG1_8 (insn)] + = load_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff))); +} + +/* mov (d16,am), dn */ +void OP_FA000000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG1_16 (insn)] + = load_word ((State.regs[REG_A0 + REG0_16 (insn)] + + SEXT16 (insn & 0xffff))); +} + +/* mov (d32,am), dn */ +void OP_FC000000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG1_16 (insn)] + = load_word ((State.regs[REG_A0 + REG0_16 (insn)] + + ((insn & 0xffff) << 16) + extension)); +} + +/* mov (d8,sp), dn */ +void OP_5800 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_8 (insn)] + = load_word (State.regs[REG_SP] + (insn & 0xff)); +} + +/* mov (d16,sp), dn */ +void OP_FAB40000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_16 (insn)] + = load_word (State.regs[REG_SP] + (insn & 0xffff)); +} + +/* mov (d32,sp), dn */ +void OP_FCB40000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_16 (insn)] + = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension)); +} + +/* mov (di,am), dn */ +void OP_F300 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_4 (insn)] + = load_word ((State.regs[REG_A0 + REG0 (insn)] + + State.regs[REG_D0 + REG1 (insn)])); +} + +/* mov (abs16), dn */ +void OP_300000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_16 (insn)] = load_word ((insn & 0xffff)); +} + +/* mov (abs32), dn */ +void OP_FCA40000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_16 (insn)] + = load_word ((((insn & 0xffff) << 16) + extension)); +} + +/* mov (am), an */ +void OP_F000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG1 (insn)] + = load_word (State.regs[REG_A0 + REG0 (insn)]); +} + +/* mov (d8,am), an */ +void OP_F82000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG1_8 (insn)] + = load_word ((State.regs[REG_A0 + REG0_8 (insn)] + + SEXT8 (insn & 0xff))); +} + +/* mov (d16,am), an */ +void OP_FA200000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG1_16 (insn)] + = load_word ((State.regs[REG_A0 + REG0_16 (insn)] + + SEXT16 (insn & 0xffff))); +} + +/* mov (d32,am), an */ +void OP_FC200000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG1_16 (insn)] + = load_word ((State.regs[REG_A0 + REG0_16 (insn)] + + ((insn & 0xffff) << 16) + extension)); +} + +/* mov (d8,sp), an */ +void OP_5C00 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG0_8 (insn)] + = load_word (State.regs[REG_SP] + (insn & 0xff)); +} + +/* mov (d16,sp), an */ +void OP_FAB00000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG0_16 (insn)] + = load_word (State.regs[REG_SP] + (insn & 0xffff)); +} + +/* mov (d32,sp), an */ +void OP_FCB00000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG0_16 (insn)] + = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension)); +} + +/* mov (di,am), an */ +void OP_F380 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG0_4 (insn)] + = load_word ((State.regs[REG_A0 + REG0 (insn)] + + State.regs[REG_D0 + REG1 (insn)])); +} + +/* mov (abs16), an */ +void OP_FAA00000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG0_16 (insn)] = load_word ((insn & 0xffff)); +} + +/* mov (abs32), an */ +void OP_FCA00000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG0_16 (insn)] + = load_word ((((insn & 0xffff) << 16) + extension)); +} + +/* mov (d8,am), sp */ +void OP_F8F000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_SP] + = load_word ((State.regs[REG_A0 + REG0_8 (insn)] + + SEXT8 (insn & 0xff))); +} + +/* mov dm, (an) */ +void OP_60 (insn, extension) + unsigned long insn, extension; +{ + store_word (State.regs[REG_A0 + REG0 (insn)], + State.regs[REG_D0 + REG1 (insn)]); +} + +/* mov dm, (d8,an) */ +void OP_F81000 (insn, extension) + unsigned long insn, extension; +{ + store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)), + State.regs[REG_D0 + REG1_8 (insn)]); +} + +/* mov dm (d16,an) */ +void OP_FA100000 (insn, extension) + unsigned long insn, extension; +{ + store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)), + State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* mov dm (d32,an) */ +void OP_FC100000 (insn, extension) + unsigned long insn, extension; +{ + store_word ((State.regs[REG_A0 + REG0_16 (insn)] + + ((insn & 0xffff) << 16) + extension), + State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* mov dm, (d8,sp) */ +void OP_4200 (insn, extension) + unsigned long insn, extension; +{ + store_word (State.regs[REG_SP] + (insn & 0xff), + State.regs[REG_D0 + REG1_8 (insn)]); +} + +/* mov dm, (d16,sp) */ +void OP_FA910000 (insn, extension) + unsigned long insn, extension; +{ + store_word (State.regs[REG_SP] + (insn & 0xffff), + State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* mov dm, (d32,sp) */ +void OP_FC910000 (insn, extension) + unsigned long insn, extension; +{ + store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), + State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* mov dm, (di,an) */ +void OP_F340 (insn, extension) + unsigned long insn, extension; +{ + store_word ((State.regs[REG_A0 + REG0 (insn)] + + State.regs[REG_D0 + REG1 (insn)]), + State.regs[REG_D0 + REG0_4 (insn)]); +} + +/* mov dm, (abs16) */ +void OP_10000 (insn, extension) + unsigned long insn, extension; +{ + store_word ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* mov dm, (abs32) */ +void OP_FC810000 (insn, extension) + unsigned long insn, extension; +{ + store_word ((((insn & 0xffff) << 16) + extension), + State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* mov am, (an) */ +void OP_F010 (insn, extension) + unsigned long insn, extension; +{ + store_word (State.regs[REG_A0 + REG0 (insn)], + State.regs[REG_A0 + REG1 (insn)]); +} + +/* mov am, (d8,an) */ +void OP_F83000 (insn, extension) + unsigned long insn, extension; +{ + store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)), + State.regs[REG_A0 + REG1_8 (insn)]); +} + +/* mov am, (d16,an) */ +void OP_FA300000 (insn, extension) + unsigned long insn, extension; +{ + store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)), + State.regs[REG_A0 + REG1_16 (insn)]); +} + +/* mov am, (d32,an) */ +void OP_FC300000 (insn, extension) + unsigned long insn, extension; +{ + store_word ((State.regs[REG_A0 + REG0_16 (insn)] + + ((insn & 0xffff) << 16) + extension), + State.regs[REG_A0 + REG1_16 (insn)]); +} + +/* mov am, (d8,sp) */ +void OP_4300 (insn, extension) + unsigned long insn, extension; +{ + store_word (State.regs[REG_SP] + (insn & 0xff), + State.regs[REG_A0 + REG1_8 (insn)]); +} + +/* mov am, (d16,sp) */ +void OP_FA900000 (insn, extension) + unsigned long insn, extension; +{ + store_word (State.regs[REG_SP] + (insn & 0xffff), + State.regs[REG_A0 + REG1_16 (insn)]); +} + +/* mov am, (d32,sp) */ +void OP_FC900000 (insn, extension) + unsigned long insn, extension; +{ + store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), + State.regs[REG_A0 + REG1_16 (insn)]); +} + +/* mov am, (di,an) */ +void OP_F3C0 (insn, extension) + unsigned long insn, extension; +{ + store_word ((State.regs[REG_A0 + REG0 (insn)] + + State.regs[REG_D0 + REG1 (insn)]), + State.regs[REG_A0 + REG0_4 (insn)]); +} + +/* mov am, (abs16) */ +void OP_FA800000 (insn, extension) + unsigned long insn, extension; +{ + store_word ((insn & 0xffff), State.regs[REG_A0 + REG1_16 (insn)]); +} + +/* mov am, (abs32) */ +void OP_FC800000 (insn, extension) + unsigned long insn, extension; +{ + store_word ((((insn & 0xffff) << 16) + extension), State.regs[REG_A0 + REG1_16 (insn)]); +} + +/* mov sp, (d8,an) */ +void OP_F8F400 (insn, extension) + unsigned long insn, extension; +{ + store_word (State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff), + State.regs[REG_SP]); +} + +/* mov imm16, dn */ +void OP_2C0000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long value; + + value = SEXT16 (insn & 0xffff); + State.regs[REG_D0 + REG0_16 (insn)] = value; +} + +/* mov imm32,dn */ +void OP_FCCC0000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long value; + + value = ((insn & 0xffff) << 16) + extension; + State.regs[REG_D0 + REG0_16 (insn)] = value; +} + +/* mov imm16, an */ +void OP_240000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long value; + + value = insn & 0xffff; + State.regs[REG_A0 + REG0_16 (insn)] = value; +} + +/* mov imm32, an */ +void OP_FCDC0000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long value; + + value = ((insn & 0xffff) << 16) + extension; + State.regs[REG_A0 + REG0_16 (insn)] = value; +} + +/* movbu (am), dn */ +void OP_F040 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG1 (insn)] + = load_byte (State.regs[REG_A0 + REG0 (insn)]); +} + +/* movbu (d8,am), dn */ +void OP_F84000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG1_8 (insn)] + = load_byte ((State.regs[REG_A0 + REG0_8 (insn)] + + SEXT8 (insn & 0xff))); +} + +/* movbu (d16,am), dn */ +void OP_FA400000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG1_16 (insn)] + = load_byte ((State.regs[REG_A0 + REG0_16 (insn)] + + SEXT16 (insn & 0xffff))); +} + +/* movbu (d32,am), dn */ +void OP_FC400000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG1_16 (insn)] + = load_byte ((State.regs[REG_A0 + REG0_16 (insn)] + + ((insn & 0xffff) << 16) + extension)); +} + +/* movbu (d8,sp), dn */ +void OP_F8B800 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_8 (insn)] + = load_byte ((State.regs[REG_SP] + (insn & 0xff))); +} + +/* movbu (d16,sp), dn */ +void OP_FAB80000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_16 (insn)] + = load_byte ((State.regs[REG_SP] + (insn & 0xffff))); +} + +/* movbu (d32,sp), dn */ +void OP_FCB80000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_16 (insn)] + = load_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension)); +} + +/* movbu (di,am), dn */ +void OP_F400 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_4 (insn)] + = load_byte ((State.regs[REG_A0 + REG0 (insn)] + + State.regs[REG_D0 + REG1 (insn)])); +} + +/* movbu (abs16), dn */ +void OP_340000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_16 (insn)] = load_byte ((insn & 0xffff)); +} + +/* movbu (abs32), dn */ +void OP_FCA80000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_16 (insn)] + = load_byte ((((insn & 0xffff) << 16) + extension)); +} + +/* movbu dm, (an) */ +void OP_F050 (insn, extension) + unsigned long insn, extension; +{ + store_byte (State.regs[REG_A0 + REG0 (insn)], + State.regs[REG_D0 + REG1 (insn)]); +} + +/* movbu dm, (d8,an) */ +void OP_F85000 (insn, extension) + unsigned long insn, extension; +{ + store_byte ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)), + State.regs[REG_D0 + REG1_8 (insn)]); +} + +/* movbu dm, (d16,an) */ +void OP_FA500000 (insn, extension) + unsigned long insn, extension; +{ + store_byte ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)), + State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* movbu dm, (d32,an) */ +void OP_FC500000 (insn, extension) + unsigned long insn, extension; +{ + store_byte ((State.regs[REG_A0 + REG0_16 (insn)] + + ((insn & 0xffff) << 16) + extension), + State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* movbu dm, (d8,sp) */ +void OP_F89200 (insn, extension) + unsigned long insn, extension; +{ + store_byte (State.regs[REG_SP] + (insn & 0xff), + State.regs[REG_D0 + REG1_8 (insn)]); +} + +/* movbu dm, (d16,sp) */ +void OP_FA920000 (insn, extension) + unsigned long insn, extension; +{ + store_byte (State.regs[REG_SP] + (insn & 0xffff), + State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* movbu dm (d32,sp) */ +void OP_FC920000 (insn, extension) + unsigned long insn, extension; +{ + store_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), + State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* movbu dm, (di,an) */ +void OP_F440 (insn, extension) + unsigned long insn, extension; +{ + store_byte ((State.regs[REG_A0 + REG0 (insn)] + + State.regs[REG_D0 + REG1 (insn)]), + State.regs[REG_D0 + REG0_4 (insn)]); +} + +/* movbu dm, (abs16) */ +void OP_20000 (insn, extension) + unsigned long insn, extension; +{ + store_byte ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* movbu dm, (abs32) */ +void OP_FC820000 (insn, extension) + unsigned long insn, extension; +{ + store_byte ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* movhu (am), dn */ +void OP_F060 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG1 (insn)] + = load_half (State.regs[REG_A0 + REG0 (insn)]); +} + +/* movhu (d8,am), dn */ +void OP_F86000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG1_8 (insn)] + = load_half ((State.regs[REG_A0 + REG0_8 (insn)] + + SEXT8 (insn & 0xff))); +} + +/* movhu (d16,am), dn */ +void OP_FA600000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG1_16 (insn)] + = load_half ((State.regs[REG_A0 + REG0_16 (insn)] + + SEXT16 (insn & 0xffff))); +} + +/* movhu (d32,am), dn */ +void OP_FC600000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG1_16 (insn)] + = load_half ((State.regs[REG_A0 + REG0_16 (insn)] + + ((insn & 0xffff) << 16) + extension)); +} + +/* movhu (d8,sp) dn */ +void OP_F8BC00 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_8 (insn)] + = load_half ((State.regs[REG_SP] + (insn & 0xff))); +} + +/* movhu (d16,sp), dn */ +void OP_FABC0000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_16 (insn)] + = load_half ((State.regs[REG_SP] + (insn & 0xffff))); +} + +/* movhu (d32,sp), dn */ +void OP_FCBC0000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_16 (insn)] + = load_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension)); +} + +/* movhu (di,am), dn */ +void OP_F480 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_4 (insn)] + = load_half ((State.regs[REG_A0 + REG0 (insn)] + + State.regs[REG_D0 + REG1 (insn)])); +} + +/* movhu (abs16), dn */ +void OP_380000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_16 (insn)] = load_half ((insn & 0xffff)); +} + +/* movhu (abs32), dn */ +void OP_FCAC0000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0_16 (insn)] + = load_half ((((insn & 0xffff) << 16) + extension)); +} + +/* movhu dm, (an) */ +void OP_F070 (insn, extension) + unsigned long insn, extension; +{ + store_half (State.regs[REG_A0 + REG0 (insn)], + State.regs[REG_D0 + REG1 (insn)]); +} + +/* movhu dm, (d8,an) */ +void OP_F87000 (insn, extension) + unsigned long insn, extension; +{ + store_half ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)), + State.regs[REG_D0 + REG1_8 (insn)]); +} + +/* movhu dm, (d16,an) */ +void OP_FA700000 (insn, extension) + unsigned long insn, extension; +{ + store_half ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)), + State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* movhu dm, (d32,an) */ +void OP_FC700000 (insn, extension) + unsigned long insn, extension; +{ + store_half ((State.regs[REG_A0 + REG0_16 (insn)] + + ((insn & 0xffff) << 16) + extension), + State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* movhu dm,(d8,sp) */ +void OP_F89300 (insn, extension) + unsigned long insn, extension; +{ + store_half (State.regs[REG_SP] + (insn & 0xff), + State.regs[REG_D0 + REG1_8 (insn)]); +} + +/* movhu dm,(d16,sp) */ +void OP_FA930000 (insn, extension) + unsigned long insn, extension; +{ + store_half (State.regs[REG_SP] + (insn & 0xffff), + State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* movhu dm,(d32,sp) */ +void OP_FC930000 (insn, extension) + unsigned long insn, extension; +{ + store_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), + State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* movhu dm, (di,an) */ +void OP_F4C0 (insn, extension) + unsigned long insn, extension; +{ + store_half ((State.regs[REG_A0 + REG0 (insn)] + + State.regs[REG_D0 + REG1 (insn)]), + State.regs[REG_D0 + REG0_4 (insn)]); +} + +/* movhu dm, (abs16) */ +void OP_30000 (insn, extension) + unsigned long insn, extension; +{ + store_half ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* movhu dm, (abs32) */ +void OP_FC830000 (insn, extension) + unsigned long insn, extension; +{ + store_half ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]); +} + +/* ext dn */ +void OP_F2D0 (insn, extension) + unsigned long insn, extension; +{ + if (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) + State.regs[REG_MDR] = -1; + else + State.regs[REG_MDR] = 0; +} + +/* extb dn */ +void OP_10 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0 (insn)] = SEXT8 (State.regs[REG_D0 + REG0 (insn)]); +} + +/* extbu dn */ +void OP_14 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0 (insn)] &= 0xff; +} + +/* exth dn */ +void OP_18 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0 (insn)] + = SEXT16 (State.regs[REG_D0 + REG0 (insn)]); +} + +/* exthu dn */ +void OP_1C (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG0 (insn)] &= 0xffff; +} + +/* movm (sp), reg_list */ +void OP_CE00 (insn, extension) + unsigned long insn, extension; +{ + unsigned long sp = State.regs[REG_SP]; + unsigned long mask; + + mask = insn & 0xff; + + if (mask & 0x8) + { + sp += 4; + State.regs[REG_LAR] = load_word (sp); + sp += 4; + State.regs[REG_LIR] = load_word (sp); + sp += 4; + State.regs[REG_MDR] = load_word (sp); + sp += 4; + State.regs[REG_A0 + 1] = load_word (sp); + sp += 4; + State.regs[REG_A0] = load_word (sp); + sp += 4; + State.regs[REG_D0 + 1] = load_word (sp); + sp += 4; + State.regs[REG_D0] = load_word (sp); + sp += 4; + } + + if (mask & 0x10) + { + State.regs[REG_A0 + 3] = load_word (sp); + sp += 4; + } + + if (mask & 0x20) + { + State.regs[REG_A0 + 2] = load_word (sp); + sp += 4; + } + + if (mask & 0x40) + { + State.regs[REG_D0 + 3] = load_word (sp); + sp += 4; + } + + if (mask & 0x80) + { + State.regs[REG_D0 + 2] = load_word (sp); + sp += 4; + } + + /* And make sure to update the stack pointer. */ + State.regs[REG_SP] = sp; +} + +/* movm reg_list, (sp) */ +void OP_CF00 (insn, extension) + unsigned long insn, extension; +{ + unsigned long sp = State.regs[REG_SP]; + unsigned long mask; + + mask = insn & 0xff; + + if (mask & 0x80) + { + sp -= 4; + store_word (sp, State.regs[REG_D0 + 2]); + } + + if (mask & 0x40) + { + sp -= 4; + store_word (sp, State.regs[REG_D0 + 3]); + } + + if (mask & 0x20) + { + sp -= 4; + store_word (sp, State.regs[REG_A0 + 2]); + } + + if (mask & 0x10) + { + sp -= 4; + store_word (sp, State.regs[REG_A0 + 3]); + } + + if (mask & 0x8) + { + sp -= 4; + store_word (sp, State.regs[REG_D0]); + sp -= 4; + store_word (sp, State.regs[REG_D0 + 1]); + sp -= 4; + store_word (sp, State.regs[REG_A0]); + sp -= 4; + store_word (sp, State.regs[REG_A0 + 1]); + sp -= 4; + store_word (sp, State.regs[REG_MDR]); + sp -= 4; + store_word (sp, State.regs[REG_LIR]); + sp -= 4; + store_word (sp, State.regs[REG_LAR]); + sp -= 4; + } + + /* And make sure to update the stack pointer. */ + State.regs[REG_SP] = sp; +} + +/* clr dn */ +void OP_0 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_D0 + REG1 (insn)] = 0; + + PSW |= PSW_Z; + PSW &= ~(PSW_V | PSW_C | PSW_N); +} + +/* add dm,dn */ +void OP_E0 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, reg2, value; + + reg1 = State.regs[REG_D0 + REG1 (insn)]; + reg2 = State.regs[REG_D0 + REG0 (insn)]; + value = reg1 + reg2; + State.regs[REG_D0 + REG0 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (value < reg1) || (value < reg2); + v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* add dm, an */ +void OP_F160 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, reg2, value; + + reg1 = State.regs[REG_D0 + REG1 (insn)]; + reg2 = State.regs[REG_A0 + REG0 (insn)]; + value = reg1 + reg2; + State.regs[REG_A0 + REG0 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (value < reg1) || (value < reg2); + v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* add am, dn */ +void OP_F150 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, reg2, value; + + reg1 = State.regs[REG_A0 + REG1 (insn)]; + reg2 = State.regs[REG_D0 + REG0 (insn)]; + value = reg1 + reg2; + State.regs[REG_D0 + REG0 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (value < reg1) || (value < reg2); + v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* add am,an */ +void OP_F170 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, reg2, value; + + reg1 = State.regs[REG_A0 + REG1 (insn)]; + reg2 = State.regs[REG_A0 + REG0 (insn)]; + value = reg1 + reg2; + State.regs[REG_A0 + REG0 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (value < reg1) || (value < reg2); + v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* add imm8, dn */ +void OP_2800 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_D0 + REG0_8 (insn)]; + imm = SEXT8 (insn & 0xff); + value = reg1 + imm; + State.regs[REG_D0 + REG0_8 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (value < reg1) || (value < imm); + v = ((reg1 & 0x80000000) == (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* add imm16, dn */ +void OP_FAC00000 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_D0 + REG0_16 (insn)]; + imm = SEXT16 (insn & 0xffff); + value = reg1 + imm; + State.regs[REG_D0 + REG0_16 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (value < reg1) || (value < imm); + v = ((reg1 & 0x80000000) == (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* add imm32,dn */ +void OP_FCC00000 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_D0 + REG0_16 (insn)]; + imm = ((insn & 0xffff) << 16) + extension; + value = reg1 + imm; + State.regs[REG_D0 + REG0_16 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (value < reg1) || (value < imm); + v = ((reg1 & 0x80000000) == (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* add imm8, an */ +void OP_2000 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_A0 + REG0_8 (insn)]; + imm = SEXT8 (insn & 0xff); + value = reg1 + imm; + State.regs[REG_A0 + REG0_8 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (value < reg1) || (value < imm); + v = ((reg1 & 0x80000000) == (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* add imm16, an */ +void OP_FAD00000 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_A0 + REG0_16 (insn)]; + imm = SEXT16 (insn & 0xffff); + value = reg1 + imm; + State.regs[REG_A0 + REG0_16 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (value < reg1) || (value < imm); + v = ((reg1 & 0x80000000) == (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* add imm32, an */ +void OP_FCD00000 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_A0 + REG0_16 (insn)]; + imm = ((insn & 0xffff) << 16) + extension; + value = reg1 + imm; + State.regs[REG_A0 + REG0_16 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (value < reg1) || (value < imm); + v = ((reg1 & 0x80000000) == (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* add imm8, sp */ +void OP_F8FE00 (insn, extension) + unsigned long insn, extension; +{ + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_SP]; + imm = SEXT8 (insn & 0xff); + value = reg1 + imm; + State.regs[REG_SP] = value; +} + +/* add imm16,sp */ +void OP_FAFE0000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_SP]; + imm = SEXT16 (insn & 0xffff); + value = reg1 + imm; + State.regs[REG_SP] = value; +} + +/* add imm32, sp */ +void OP_FCFE0000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_SP]; + imm = ((insn & 0xffff) << 16) + extension; + value = reg1 + imm; + State.regs[REG_SP] = value; +} + +/* addc dm,dn */ +void OP_F140 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, reg2, value; + + reg1 = State.regs[REG_D0 + REG1 (insn)]; + reg2 = State.regs[REG_D0 + REG0 (insn)]; + value = reg1 + reg2 + ((PSW & PSW_C) != 0); + State.regs[REG_D0 + REG0 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (value < reg1) || (value < reg2); + v = ((reg2 & 0x80000000) == (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* sub dm, dn */ +void OP_F100 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, reg2, value; + + reg1 = State.regs[REG_D0 + REG1 (insn)]; + reg2 = State.regs[REG_D0 + REG0 (insn)]; + value = reg2 - reg1; + State.regs[REG_D0 + REG0 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 > reg2); + v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* sub dm, an */ +void OP_F120 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, reg2, value; + + reg1 = State.regs[REG_D0 + REG1 (insn)]; + reg2 = State.regs[REG_A0 + REG0 (insn)]; + value = reg2 - reg1; + State.regs[REG_A0 + REG0 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 > reg2); + v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* sub am, dn */ +void OP_F110 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, reg2, value; + + reg1 = State.regs[REG_A0 + REG1 (insn)]; + reg2 = State.regs[REG_D0 + REG0 (insn)]; + value = reg2 - reg1; + State.regs[REG_D0 + REG0 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 > reg2); + v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* sub am, an */ +void OP_F130 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, reg2, value; + + reg1 = State.regs[REG_A0 + REG1 (insn)]; + reg2 = State.regs[REG_A0 + REG0 (insn)]; + value = reg2 - reg1; + State.regs[REG_A0 + REG0 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 > reg2); + v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* sub imm32, dn */ +void OP_FCC40000 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_D0 + REG0_16 (insn)]; + imm = ((insn & 0xffff) << 16) + extension; + value = reg1 - imm; + State.regs[REG_D0 + REG0_16 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 < imm); + v = ((reg1 & 0x80000000) != (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* sub imm32, an */ +void OP_FCD40000 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_A0 + REG0_16 (insn)]; + imm = ((insn & 0xffff) << 16) + extension; + value = reg1 - imm; + State.regs[REG_A0 + REG0_16 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 < imm); + v = ((reg1 & 0x80000000) != (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* subc dm, dn */ +void OP_F180 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, reg2, value; + + reg1 = State.regs[REG_D0 + REG1 (insn)]; + reg2 = State.regs[REG_D0 + REG0 (insn)]; + value = reg2 - reg1 - ((PSW & PSW_C) != 0); + State.regs[REG_D0 + REG0 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 > reg2); + v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* mul dm, dn */ +void OP_F240 (insn, extension) + unsigned long insn, extension; +{ + unsigned long long temp; + int n, z; + + temp = ((signed64)(signed32)State.regs[REG_D0 + REG0 (insn)] + * (signed64)(signed32)State.regs[REG_D0 + REG1 (insn)]); + State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;; + z = (State.regs[REG_D0 + REG0 (insn)] == 0); + n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* mulu dm, dn */ +void OP_F250 (insn, extension) + unsigned long insn, extension; +{ + unsigned long long temp; + int n, z; + + temp = ((unsigned64)State.regs[REG_D0 + REG0 (insn)] + * (unsigned64)State.regs[REG_D0 + REG1 (insn)]); + State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; + State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32; + z = (State.regs[REG_D0 + REG0 (insn)] == 0); + n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* div dm, dn */ +void OP_F260 (insn, extension) + unsigned long insn, extension; +{ + long long temp; + int n, z; + + temp = State.regs[REG_MDR]; + temp <<= 32; + temp |= State.regs[REG_D0 + REG0 (insn)]; + State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + REG1 (insn)]; + temp /= (long)State.regs[REG_D0 + REG1 (insn)]; + State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; + z = (State.regs[REG_D0 + REG0 (insn)] == 0); + n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* divu dm, dn */ +void OP_F270 (insn, extension) + unsigned long insn, extension; +{ + unsigned long long temp; + int n, z; + + temp = State.regs[REG_MDR]; + temp <<= 32; + temp |= State.regs[REG_D0 + REG0 (insn)]; + State.regs[REG_MDR] = temp % State.regs[REG_D0 + REG1 (insn)]; + temp /= State.regs[REG_D0 + REG1 (insn)]; + State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; + z = (State.regs[REG_D0 + REG0 (insn)] == 0); + n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* inc dn */ +void OP_40 (insn, extension) + unsigned long insn, extension; +{ + int z,n,c,v; + unsigned int value, imm, reg1; + + reg1 = State.regs[REG_D0 + REG1 (insn)]; + imm = 1; + value = reg1 + imm; + State.regs[REG_D0 + REG1 (insn)] = value; + + z = (value == 0); + n = (value & 0x80000000); + c = (value < imm); + v = ((reg1 & 0x80000000) == (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* inc an */ +void OP_41 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG1 (insn)] += 1; +} + +/* inc4 an */ +void OP_50 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_A0 + REG0 (insn)] += 4; +} + +/* cmp imm8, dn */ +void OP_A000 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_D0 + REG0_8 (insn)]; + imm = SEXT8 (insn & 0xff); + value = reg1 - imm; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 < imm); + v = ((reg1 & 0x80000000) != (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* cmp dm, dn */ +void OP_A0 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, reg2, value; + + reg1 = State.regs[REG_D0 + REG1 (insn)]; + reg2 = State.regs[REG_D0 + REG0 (insn)]; + value = reg2 - reg1; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 > reg2); + v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* cmp dm, an */ +void OP_F1A0 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, reg2, value; + + reg1 = State.regs[REG_D0 + REG1 (insn)]; + reg2 = State.regs[REG_A0 + REG0 (insn)]; + value = reg2 - reg1; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 > reg2); + v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* cmp am, dn */ +void OP_F190 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, reg2, value; + + reg1 = State.regs[REG_A0 + REG1 (insn)]; + reg2 = State.regs[REG_D0 + REG0 (insn)]; + value = reg2 - reg1; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 > reg2); + v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* cmp imm8, an */ +void OP_B000 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_A0 + REG0_8 (insn)]; + imm = insn & 0xff; + value = reg1 - imm; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 < imm); + v = ((reg1 & 0x80000000) != (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* cmp am, an */ +void OP_B0 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, reg2, value; + + reg1 = State.regs[REG_A0 + REG1 (insn)]; + reg2 = State.regs[REG_A0 + REG0 (insn)]; + value = reg2 - reg1; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 > reg2); + v = ((reg2 & 0x80000000) != (reg1 & 0x80000000) + && (reg2 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* cmp imm16, dn */ +void OP_FAC80000 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_D0 + REG0_16 (insn)]; + imm = SEXT16 (insn & 0xffff); + value = reg1 - imm; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 < imm); + v = ((reg1 & 0x80000000) != (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* cmp imm32, dn */ +void OP_FCC80000 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_D0 + REG0_16 (insn)]; + imm = ((insn & 0xffff) << 16) + extension; + value = reg1 - imm; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 < imm); + v = ((reg1 & 0x80000000) != (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* cmp imm16, an */ +void OP_FAD80000 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_A0 + REG0_16 (insn)]; + imm = insn & 0xffff; + value = reg1 - imm; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 < imm); + v = ((reg1 & 0x80000000) != (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* cmp imm32, an */ +void OP_FCD80000 (insn, extension) + unsigned long insn, extension; +{ + int z, c, n, v; + unsigned long reg1, imm, value; + + reg1 = State.regs[REG_A0 + REG0_16 (insn)]; + imm = ((insn & 0xffff) << 16) + extension; + value = reg1 - imm; + + z = (value == 0); + n = (value & 0x80000000); + c = (reg1 < imm); + v = ((reg1 & 0x80000000) != (imm & 0x80000000) + && (reg1 & 0x80000000) != (value & 0x80000000)); + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) + | (c ? PSW_C : 0) | (v ? PSW_V : 0)); +} + +/* and dm, dn */ +void OP_F200 (insn, extension) + unsigned long insn, extension; +{ + int n, z; + + State.regs[REG_D0 + REG0 (insn)] &= State.regs[REG_D0 + REG1 (insn)]; + z = (State.regs[REG_D0 + REG0 (insn)] == 0); + n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* and imm8, dn */ +void OP_F8E000 (insn, extension) + unsigned long insn, extension; +{ + int n, z; + + State.regs[REG_D0 + REG0_8 (insn)] &= (insn & 0xff); + z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* and imm16, dn */ +void OP_FAE00000 (insn, extension) + unsigned long insn, extension; +{ + int n, z; + + State.regs[REG_D0 + REG0_16 (insn)] &= (insn & 0xffff); + z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* and imm32, dn */ +void OP_FCE00000 (insn, extension) + unsigned long insn, extension; +{ + int n, z; + + State.regs[REG_D0 + REG0_16 (insn)] + &= ((insn & 0xffff) << 16) + extension; + z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* and imm16, psw */ +void OP_FAFC0000 (insn, extension) + unsigned long insn, extension; +{ + PSW &= (insn & 0xffff); +} + +/* or dm, dn*/ +void OP_F210 (insn, extension) + unsigned long insn, extension; +{ + int n, z; + + State.regs[REG_D0 + REG0 (insn)] |= State.regs[REG_D0 + REG1 (insn)]; + z = (State.regs[REG_D0 + REG0 (insn)] == 0); + n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* or imm8, dn */ +void OP_F8E400 (insn, extension) + unsigned long insn, extension; +{ + int n, z; + + State.regs[REG_D0 + REG0_8 (insn)] |= insn & 0xff; + z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* or imm16, dn*/ +void OP_FAE40000 (insn, extension) + unsigned long insn, extension; +{ + int n, z; + + State.regs[REG_D0 + REG0_16 (insn)] |= insn & 0xffff; + z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* or imm32, dn */ +void OP_FCE40000 (insn, extension) + unsigned long insn, extension; +{ + int n, z; + + State.regs[REG_D0 + REG0_16 (insn)] + |= ((insn & 0xffff) << 16) + extension; + z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* or imm16,psw */ +void OP_FAFD0000 (insn, extension) + unsigned long insn, extension; +{ + PSW |= (insn & 0xffff); +} + +/* xor dm, dn */ +void OP_F220 (insn, extension) + unsigned long insn, extension; +{ + int n, z; + + State.regs[REG_D0 + REG0 (insn)] ^= State.regs[REG_D0 + REG1 (insn)]; + z = (State.regs[REG_D0 + REG0 (insn)] == 0); + n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* xor imm16, dn */ +void OP_FAE80000 (insn, extension) + unsigned long insn, extension; +{ + int n, z; + + State.regs[REG_D0 + REG0_16 (insn)] ^= insn & 0xffff; + z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* xor imm32, dn */ +void OP_FCE80000 (insn, extension) + unsigned long insn, extension; +{ + int n, z; + + State.regs[REG_D0 + REG0_16 (insn)] + ^= ((insn & 0xffff) << 16) + extension; + z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* not dn */ +void OP_F230 (insn, extension) + unsigned long insn, extension; +{ + int n, z; + + State.regs[REG_D0 + REG0 (insn)] = ~State.regs[REG_D0 + REG0 (insn)]; + z = (State.regs[REG_D0 + REG0 (insn)] == 0); + n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* btst imm8, dn */ +void OP_F8EC00 (insn, extension) + unsigned long insn, extension; +{ + unsigned long temp; + int z, n; + + temp = State.regs[REG_D0 + REG0_8 (insn)]; + temp &= (insn & 0xff); + n = (temp & 0x80000000) != 0; + z = (temp == 0); + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); +} + +/* btst imm16, dn */ +void OP_FAEC0000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long temp; + int z, n; + + temp = State.regs[REG_D0 + REG0_16 (insn)]; + temp &= (insn & 0xffff); + n = (temp & 0x80000000) != 0; + z = (temp == 0); + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); +} + +/* btst imm32, dn */ +void OP_FCEC0000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long temp; + int z, n; + + temp = State.regs[REG_D0 + REG0_16 (insn)]; + temp &= ((insn & 0xffff) << 16) + extension; + n = (temp & 0x80000000) != 0; + z = (temp == 0); + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); +} + +/* btst imm8,(abs32) */ +void OP_FE020000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long temp; + int n, z; + + temp = load_byte (((insn & 0xffff) << 16) | (extension >> 8)); + temp &= (extension & 0xff); + n = (temp & 0x80000000) != 0; + z = (temp == 0); + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); +} + +/* btst imm8,(d8,an) */ +void OP_FAF80000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long temp; + int n, z; + + temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)] + + SEXT8 ((insn & 0xff00) >> 8))); + temp &= (insn & 0xff); + n = (temp & 0x80000000) != 0; + z = (temp == 0); + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); +} + +/* bset dm, (an) */ +void OP_F080 (insn, extension) + unsigned long insn, extension; +{ + unsigned long temp; + int z; + + temp = load_byte (State.regs[REG_A0 + REG0 (insn)]); + z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0; + temp |= State.regs[REG_D0 + REG1 (insn)]; + store_byte (State.regs[REG_A0 + REG0 (insn)], temp); + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= (z ? PSW_Z : 0); +} + +/* bset imm8, (abs32) */ +void OP_FE000000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long temp; + int z; + + temp = load_byte (((insn & 0xffff) << 16 | (extension >> 8))); + z = (temp & (extension & 0xff)) == 0; + temp |= (extension & 0xff); + store_byte ((((insn & 0xffff) << 16) | (extension >> 8)), temp); + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= (z ? PSW_Z : 0); +} + +/* bset imm8,(d8,an) */ +void OP_FAF00000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long temp; + int z; + + temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)] + + SEXT8 ((insn & 0xff00) >> 8))); + z = (temp & (insn & 0xff)) == 0; + temp |= (insn & 0xff); + store_byte ((State.regs[REG_A0 + REG0_16 (insn)] + + SEXT8 ((insn & 0xff00) >> 8)), temp); + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= (z ? PSW_Z : 0); +} + +/* bclr dm, (an) */ +void OP_F090 (insn, extension) + unsigned long insn, extension; +{ + unsigned long temp; + int z; + + temp = load_byte (State.regs[REG_A0 + REG0 (insn)]); + z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0; + temp = temp & ~State.regs[REG_D0 + REG1 (insn)]; + store_byte (State.regs[REG_A0 + REG0 (insn)], temp); + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= (z ? PSW_Z : 0); +} + +/* bclr imm8, (abs32) */ +void OP_FE010000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long temp; + int z; + + temp = load_byte (((insn & 0xffff) << 16) | (extension >> 8)); + z = (temp & (extension & 0xff)) == 0; + temp = temp & ~(extension & 0xff); + store_byte (((insn & 0xffff) << 16) | (extension >> 8), temp); + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= (z ? PSW_Z : 0); +} + +/* bclr imm8,(d8,an) */ +void OP_FAF40000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long temp; + int z; + + temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)] + + SEXT8 ((insn & 0xff00) >> 8))); + z = (temp & (insn & 0xff)) == 0; + temp = temp & ~(insn & 0xff); + store_byte ((State.regs[REG_A0 + REG0_16 (insn)] + + SEXT8 ((insn & 0xff00) >> 8)), temp); + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= (z ? PSW_Z : 0); +} + +/* asr dm, dn */ +void OP_F2B0 (insn, extension) + unsigned long insn, extension; +{ + long temp; + int z, n, c; + + temp = State.regs[REG_D0 + REG0 (insn)]; + c = temp & 1; + temp >>= State.regs[REG_D0 + REG1 (insn)]; + State.regs[REG_D0 + REG0 (insn)] = temp; + z = (State.regs[REG_D0 + REG0 (insn)] == 0); + n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +/* asr imm8, dn */ +void OP_F8C800 (insn, extension) + unsigned long insn, extension; +{ + long temp; + int z, n, c; + + temp = State.regs[REG_D0 + REG0_8 (insn)]; + c = temp & 1; + temp >>= (insn & 0xff); + State.regs[REG_D0 + REG0_8 (insn)] = temp; + z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +/* lsr dm, dn */ +void OP_F2A0 (insn, extension) + unsigned long insn, extension; +{ + int z, n, c; + + c = State.regs[REG_D0 + REG0 (insn)] & 1; + State.regs[REG_D0 + REG0 (insn)] + >>= State.regs[REG_D0 + REG1 (insn)]; + z = (State.regs[REG_D0 + REG0 (insn)] == 0); + n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +/* lsr imm8, dn */ +void OP_F8C400 (insn, extension) + unsigned long insn, extension; +{ + int z, n, c; + + c = State.regs[REG_D0 + REG0_8 (insn)] & 1; + State.regs[REG_D0 + REG0_8 (insn)] >>= (insn & 0xff); + z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +/* asl dm, dn */ +void OP_F290 (insn, extension) + unsigned long insn, extension; +{ + int n, z; + + State.regs[REG_D0 + REG0 (insn)] + <<= State.regs[REG_D0 + REG1 (insn)]; + z = (State.regs[REG_D0 + REG0 (insn)] == 0); + n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* asl imm8, dn */ +void OP_F8C000 (insn, extension) + unsigned long insn, extension; +{ + int n, z; + + State.regs[REG_D0 + REG0_8 (insn)] <<= (insn & 0xff); + z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* asl2 dn */ +void OP_54 (insn, extension) + unsigned long insn, extension; +{ + int n, z; + + State.regs[REG_D0 + REG0 (insn)] <<= 2; + z = (State.regs[REG_D0 + REG0 (insn)] == 0); + n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* ror dn */ +void OP_F284 (insn, extension) + unsigned long insn, extension; +{ + unsigned long value; + int c,n,z; + + value = State.regs[REG_D0 + REG0 (insn)]; + c = (value & 0x1); + + value >>= 1; + value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0; + State.regs[REG_D0 + REG0 (insn)] = value; + z = (value == 0); + n = (value & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +/* rol dn */ +void OP_F280 (insn, extension) + unsigned long insn, extension; +{ + unsigned long value; + int c,n,z; + + value = State.regs[REG_D0 + REG0 (insn)]; + c = (value & 0x80000000) ? 1 : 0; + + value <<= 1; + value |= ((PSW & PSW_C) != 0); + State.regs[REG_D0 + REG0 (insn)] = value; + z = (value == 0); + n = (value & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0)); +} + +/* beq label:8 */ +void OP_C800 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 2 after we return, so + we subtract two here to make things right. */ + if (PSW & PSW_Z) + State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; +} + +/* bne label:8 */ +void OP_C900 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 2 after we return, so + we subtract two here to make things right. */ + if (!(PSW & PSW_Z)) + State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; +} + +/* bgt label:8 */ +void OP_C100 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 2 after we return, so + we subtract two here to make things right. */ + if (!((PSW & PSW_Z) + || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))) + State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; +} + +/* bge label:8 */ +void OP_C200 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 2 after we return, so + we subtract two here to make things right. */ + if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) + State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; +} + +/* ble label:8 */ +void OP_C300 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 2 after we return, so + we subtract two here to make things right. */ + if ((PSW & PSW_Z) + || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) + State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; +} + +/* blt label:8 */ +void OP_C000 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 2 after we return, so + we subtract two here to make things right. */ + if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)) + State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; +} + +/* bhi label:8 */ +void OP_C500 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 2 after we return, so + we subtract two here to make things right. */ + if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)) + State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; +} + +/* bcc label:8 */ +void OP_C600 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 2 after we return, so + we subtract two here to make things right. */ + if (!(PSW & PSW_C)) + State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; +} + +/* bls label:8 */ +void OP_C700 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 2 after we return, so + we subtract two here to make things right. */ + if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0) + State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; +} + +/* bcs label:8 */ +void OP_C400 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 2 after we return, so + we subtract two here to make things right. */ + if (PSW & PSW_C) + State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; +} + +/* bvc label:8 */ +void OP_F8E800 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 3 after we return, so + we subtract two here to make things right. */ + if (!(PSW & PSW_V)) + State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3; +} + +/* bvs label:8 */ +void OP_F8E900 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 3 after we return, so + we subtract two here to make things right. */ + if (PSW & PSW_V) + State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3; +} + +/* bnc label:8 */ +void OP_F8EA00 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 3 after we return, so + we subtract two here to make things right. */ + if (!(PSW & PSW_N)) + State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3; +} + +/* bns label:8 */ +void OP_F8EB00 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 3 after we return, so + we subtract two here to make things right. */ + if (PSW & PSW_N) + State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3; +} + +/* bra label:8 */ +void OP_CA00 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 2 after we return, so + we subtract two here to make things right. */ + State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2; +} + +/* leq */ +void OP_D8 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 1 after we return, so + we subtract one here to make things right. */ + if (PSW & PSW_Z) + State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; +} + +/* lne */ +void OP_D9 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 1 after we return, so + we subtract one here to make things right. */ + if (!(PSW & PSW_Z)) + State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; +} + +/* lgt */ +void OP_D1 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 1 after we return, so + we subtract one here to make things right. */ + if (!((PSW & PSW_Z) + || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))) + State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; +} + +/* lge */ +void OP_D2 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 1 after we return, so + we subtract one here to make things right. */ + if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) + State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; +} + +/* lle */ +void OP_D3 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 1 after we return, so + we subtract one here to make things right. */ + if ((PSW & PSW_Z) + || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))) + State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; +} + +/* llt */ +void OP_D0 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 1 after we return, so + we subtract one here to make things right. */ + if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)) + State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; +} + +/* lhi */ +void OP_D5 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 1 after we return, so + we subtract one here to make things right. */ + if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)) + State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; +} + +/* lcc */ +void OP_D6 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 1 after we return, so + we subtract one here to make things right. */ + if (!(PSW & PSW_C)) + State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; +} + +/* lls */ +void OP_D7 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 1 after we return, so + we subtract one here to make things right. */ + if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0) + State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; +} + +/* lcs */ +void OP_D4 (insn, extension) + unsigned long insn, extension; +{ + /* The dispatching code will add 1 after we return, so + we subtract one here to make things right. */ + if (PSW & PSW_C) + State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; +} + +/* lra */ +void OP_DA (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1; +} + +/* setlb */ +void OP_DB (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_LIR] = load_mem_big (State.regs[REG_PC] + 1, 4); + State.regs[REG_LAR] = State.regs[REG_PC] + 5; +} + +/* jmp (an) */ +void OP_F0F4 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2; +} + +/* jmp label:16 */ +void OP_CC0000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 3; +} + +/* jmp label:32 */ +void OP_DC000000 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_PC] += (((insn & 0xffffff) << 8) + extension) - 5; +} + +/* call label:16,reg_list,imm8 */ +void OP_CD000000 (insn, extension) + unsigned long insn, extension; +{ + unsigned int next_pc, sp; + unsigned long mask; + + sp = State.regs[REG_SP]; + next_pc = State.regs[REG_PC] + 5; + State.mem[sp] = next_pc & 0xff; + State.mem[sp+1] = (next_pc & 0xff00) >> 8; + State.mem[sp+2] = (next_pc & 0xff0000) >> 16; + State.mem[sp+3] = (next_pc & 0xff000000) >> 24; + + mask = insn & 0xff; + + if (mask & 0x80) + { + sp -= 4; + store_word (sp, State.regs[REG_D0 + 2]); + } + + if (mask & 0x40) + { + sp -= 4; + store_word (sp, State.regs[REG_D0 + 3]); + } + + if (mask & 0x20) + { + sp -= 4; + store_word (sp, State.regs[REG_A0 + 2]); + } + + if (mask & 0x10) + { + sp -= 4; + store_word (sp, State.regs[REG_A0 + 3]); + } + + if (mask & 0x8) + { + sp -= 4; + store_word (sp, State.regs[REG_D0]); + sp -= 4; + store_word (sp, State.regs[REG_D0 + 1]); + sp -= 4; + store_word (sp, State.regs[REG_A0]); + sp -= 4; + store_word (sp, State.regs[REG_A0 + 1]); + sp -= 4; + store_word (sp, State.regs[REG_MDR]); + sp -= 4; + store_word (sp, State.regs[REG_LIR]); + sp -= 4; + store_word (sp, State.regs[REG_LAR]); + sp -= 4; + } + + /* Update the stack pointer, note that the register saves to do not + modify SP. The SP adjustment is derived totally from the imm8 + field. */ + State.regs[REG_SP] -= extension; + State.regs[REG_MDR] = next_pc; + State.regs[REG_PC] += SEXT16 ((insn & 0xffff00) >> 8) - 5; +} + +/* call label:32,reg_list,imm8*/ +void OP_DD000000 (insn, extension) + unsigned long insn, extension; +{ + unsigned int next_pc, sp, adjust; + unsigned long mask; + + sp = State.regs[REG_SP]; + next_pc = State.regs[REG_PC] + 7; + State.mem[sp] = next_pc & 0xff; + State.mem[sp+1] = (next_pc & 0xff00) >> 8; + State.mem[sp+2] = (next_pc & 0xff0000) >> 16; + State.mem[sp+3] = (next_pc & 0xff000000) >> 24; + + mask = (extension & 0xff00) >> 8; + + if (mask & 0x80) + { + sp -= 4; + store_word (sp, State.regs[REG_D0 + 2]); + } + + if (mask & 0x40) + { + sp -= 4; + store_word (sp, State.regs[REG_D0 + 3]); + } + + if (mask & 0x20) + { + sp -= 4; + store_word (sp, State.regs[REG_A0 + 2]); + } + + if (mask & 0x10) + { + sp -= 4; + store_word (sp, State.regs[REG_A0 + 3]); + } + + if (mask & 0x8) + { + sp -= 4; + store_word (sp, State.regs[REG_D0]); + sp -= 4; + store_word (sp, State.regs[REG_D0 + 1]); + sp -= 4; + store_word (sp, State.regs[REG_A0]); + sp -= 4; + store_word (sp, State.regs[REG_A0 + 1]); + sp -= 4; + store_word (sp, State.regs[REG_MDR]); + sp -= 4; + store_word (sp, State.regs[REG_LIR]); + sp -= 4; + store_word (sp, State.regs[REG_LAR]); + sp -= 4; + } + + /* Update the stack pointer, note that the register saves to do not + modify SP. The SP adjustment is derived totally from the imm8 + field. */ + State.regs[REG_SP] -= (extension & 0xff); + State.regs[REG_MDR] = next_pc; + State.regs[REG_PC] += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7; +} + +/* calls (an) */ +void OP_F0F0 (insn, extension) + unsigned long insn, extension; +{ + unsigned int next_pc, sp; + + sp = State.regs[REG_SP]; + next_pc = State.regs[REG_PC] + 2; + State.mem[sp] = next_pc & 0xff; + State.mem[sp+1] = (next_pc & 0xff00) >> 8; + State.mem[sp+2] = (next_pc & 0xff0000) >> 16; + State.mem[sp+3] = (next_pc & 0xff000000) >> 24; + State.regs[REG_MDR] = next_pc; + State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2; +} + +/* calls label:16 */ +void OP_FAFF0000 (insn, extension) + unsigned long insn, extension; +{ + unsigned int next_pc, sp; + + sp = State.regs[REG_SP]; + next_pc = State.regs[REG_PC] + 4; + State.mem[sp] = next_pc & 0xff; + State.mem[sp+1] = (next_pc & 0xff00) >> 8; + State.mem[sp+2] = (next_pc & 0xff0000) >> 16; + State.mem[sp+3] = (next_pc & 0xff000000) >> 24; + State.regs[REG_MDR] = next_pc; + State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 4; +} + +/* calls label:32 */ +void OP_FCFF0000 (insn, extension) + unsigned long insn, extension; +{ + unsigned int next_pc, sp; + + sp = State.regs[REG_SP]; + next_pc = State.regs[REG_PC] + 6; + State.mem[sp] = next_pc & 0xff; + State.mem[sp+1] = (next_pc & 0xff00) >> 8; + State.mem[sp+2] = (next_pc & 0xff0000) >> 16; + State.mem[sp+3] = (next_pc & 0xff000000) >> 24; + State.regs[REG_MDR] = next_pc; + State.regs[REG_PC] += (((insn & 0xffff) << 16) + extension) - 6; +} + +/* ret reg_list, imm8 */ +void OP_DF0000 (insn, extension) + unsigned long insn, extension; +{ + unsigned int sp, offset; + unsigned long mask; + + State.regs[REG_SP] += insn & 0xff; + sp = State.regs[REG_SP]; + + offset = -4; + mask = (insn & 0xff00) >> 8; + + if (mask & 0x80) + { + State.regs[REG_D0 + 2] = load_word (sp + offset); + offset -= 4; + } + + if (mask & 0x40) + { + State.regs[REG_D0 + 3] = load_word (sp + offset); + offset -= 4; + } + + if (mask & 0x20) + { + State.regs[REG_A0 + 2] = load_word (sp + offset); + offset -= 4; + } + + if (mask & 0x10) + { + State.regs[REG_A0 + 3] = load_word (sp + offset); + offset -= 4; + } + + if (mask & 0x8) + { + State.regs[REG_D0] = load_word (sp + offset); + offset -= 4; + State.regs[REG_D0 + 1] = load_word (sp + offset); + offset -= 4; + State.regs[REG_A0] = load_word (sp + offset); + offset -= 4; + State.regs[REG_A0 + 1] = load_word (sp + offset); + offset -= 4; + State.regs[REG_MDR] = load_word (sp + offset); + offset -= 4; + State.regs[REG_LIR] = load_word (sp + offset); + offset -= 4; + State.regs[REG_LAR] = load_word (sp + offset); + offset -= 4; + } + + /* Restore the PC value. */ + State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8) + | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24)); + State.regs[REG_PC] -= 3; +} + +/* retf reg_list,imm8 */ +void OP_DE0000 (insn, extension) + unsigned long insn, extension; +{ + unsigned int sp, offset; + unsigned long mask; + + State.regs[REG_SP] += (insn & 0xff); + sp = State.regs[REG_SP]; + State.regs[REG_PC] = State.regs[REG_MDR] - 3; + + offset = -4; + mask = (insn & 0xff00) >> 8; + + if (mask & 0x80) + { + State.regs[REG_D0 + 2] = load_word (sp + offset); + offset -= 4; + } + + if (mask & 0x40) + { + State.regs[REG_D0 + 3] = load_word (sp + offset); + offset -= 4; + } + + if (mask & 0x20) + { + State.regs[REG_A0 + 2] = load_word (sp + offset); + offset -= 4; + } + + if (mask & 0x10) + { + State.regs[REG_A0 + 3] = load_word (sp + offset); + offset -= 4; + } + + if (mask & 0x8) + { + State.regs[REG_D0] = load_word (sp + offset); + offset -= 4; + State.regs[REG_D0 + 1] = load_word (sp + offset); + offset -= 4; + State.regs[REG_A0] = load_word (sp + offset); + offset -= 4; + State.regs[REG_A0 + 1] = load_word (sp + offset); + offset -= 4; + State.regs[REG_MDR] = load_word (sp + offset); + offset -= 4; + State.regs[REG_LIR] = load_word (sp + offset); + offset -= 4; + State.regs[REG_LAR] = load_word (sp + offset); + offset -= 4; + } +} + +/* rets */ +void OP_F0FC (insn, extension) + unsigned long insn, extension; +{ + unsigned int sp; + + sp = State.regs[REG_SP]; + State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8) + | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24)); + State.regs[REG_PC] -= 2; +} + +/* rti */ +void OP_F0FD (insn, extension) + unsigned long insn, extension; +{ + unsigned int sp, next_pc; + + sp = State.regs[REG_SP]; + PSW = State.mem[sp] | (State.mem[sp + 1] << 8); + State.regs[REG_PC] = (State.mem[sp+4] | (State.mem[sp+5] << 8) + | (State.mem[sp+6] << 16) | (State.mem[sp+7] << 24)); + State.regs[REG_SP] += 8; +} + +/* trap */ +void OP_F0FE (insn, extension) + unsigned long insn, extension; +{ + unsigned int sp, next_pc; + + sp = State.regs[REG_SP]; + next_pc = State.regs[REG_PC] + 2; + State.mem[sp] = next_pc & 0xff; + State.mem[sp+1] = (next_pc & 0xff00) >> 8; + State.mem[sp+2] = (next_pc & 0xff0000) >> 16; + State.mem[sp+3] = (next_pc & 0xff000000) >> 24; + State.regs[REG_PC] = 0x40000010 - 2; +} + +/* syscall */ +void OP_F0C0 (insn, extension) + unsigned long insn, extension; +{ + /* We use this for simulated system calls; we may need to change + it to a reserved instruction if we conflict with uses at + Matsushita. */ + int save_errno = errno; + errno = 0; + +/* Registers passed to trap 0 */ + +/* Function number. */ +#define FUNC (State.regs[0]) + +/* Parameters. */ +#define PARM1 (State.regs[1]) +#define PARM2 (load_word (State.regs[REG_SP] + 12)) +#define PARM3 (load_word (State.regs[REG_SP] + 16)) + +/* Registers set by trap 0 */ + +#define RETVAL State.regs[0] /* return value */ +#define RETERR State.regs[1] /* return error code */ + +/* Turn a pointer in a register into a pointer into real memory. */ + +#define MEMPTR(x) (State.mem + x) + + switch (FUNC) + { +#if !defined(__GO32__) && !defined(_WIN32) +#ifdef TARGET_SYS_fork + case TARGET_SYS_fork: + RETVAL = fork (); + break; +#endif +#ifdef TARGET_SYS_execve + case TARGET_SYS_execve: + RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), + (char **)MEMPTR (PARM3)); + break; +#endif +#ifdef TARGET_SYS_execv + case TARGET_SYS_execv: + RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL); + break; +#endif +#endif /* ! GO32 and ! WIN32 */ + + case TARGET_SYS_read: + RETVAL = mn10300_callback->read (mn10300_callback, PARM1, + MEMPTR (PARM2), PARM3); + break; + case TARGET_SYS_write: + RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1, + MEMPTR (PARM2), PARM3); + break; + case TARGET_SYS_lseek: + RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3); + break; + case TARGET_SYS_close: + RETVAL = mn10300_callback->close (mn10300_callback, PARM1); + break; + case TARGET_SYS_open: + RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2); + break; + case TARGET_SYS_exit: + /* EXIT - caller can look in PARM1 to work out the + reason */ + if (PARM1 == 0xdead) + State.exception = SIGABRT; + else + State.exception = SIGQUIT; + State.exited = 1; + break; + + case TARGET_SYS_stat: /* added at hmsi */ + /* stat system call */ + { + struct stat host_stat; + reg_t buf; + + RETVAL = stat (MEMPTR (PARM1), &host_stat); + + buf = PARM2; + + /* Just wild-assed guesses. */ + store_half (buf, host_stat.st_dev); + store_half (buf + 2, host_stat.st_ino); + store_word (buf + 4, host_stat.st_mode); + store_half (buf + 8, host_stat.st_nlink); + store_half (buf + 10, host_stat.st_uid); + store_half (buf + 12, host_stat.st_gid); + store_half (buf + 14, host_stat.st_rdev); + store_word (buf + 16, host_stat.st_size); + store_word (buf + 20, host_stat.st_atime); + store_word (buf + 28, host_stat.st_mtime); + store_word (buf + 36, host_stat.st_ctime); + } + break; + +#ifdef TARGET_SYS_chown + case TARGET_SYS_chown: + RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3); + break; +#endif + case TARGET_SYS_chmod: + RETVAL = chmod (MEMPTR (PARM1), PARM2); + break; +#ifdef TARGET_SYS_time + case TARGET_SYS_time: + RETVAL = time ((void*) MEMPTR (PARM1)); + break; +#endif +#ifdef TARGET_SYS_times + case TARGET_SYS_times: + { + struct tms tms; + RETVAL = times (&tms); + store_word (PARM1, tms.tms_utime); + store_word (PARM1 + 4, tms.tms_stime); + store_word (PARM1 + 8, tms.tms_cutime); + store_word (PARM1 + 12, tms.tms_cstime); + break; + } +#endif +#ifdef TARGET_SYS_gettimeofday + case TARGET_SYS_gettimeofday: + { + struct timeval t; + struct timezone tz; + RETVAL = gettimeofday (&t, &tz); + store_word (PARM1, t.tv_sec); + store_word (PARM1 + 4, t.tv_usec); + store_word (PARM2, tz.tz_minuteswest); + store_word (PARM2 + 4, tz.tz_dsttime); + break; + } +#endif +#ifdef TARGET_SYS_utime + case TARGET_SYS_utime: + /* Cast the second argument to void *, to avoid type mismatch + if a prototype is present. */ + RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)); + break; +#endif + default: + abort (); + } + RETERR = errno; + errno = save_errno; +} + +/* rtm */ +void OP_F0FF (insn, extension) + unsigned long insn, extension; +{ + abort (); +} + +/* nop */ +void OP_CB (insn, extension) + unsigned long insn, extension; +{ +} + +/* putx dm,dm */ +void OP_F500 (insn, extension) + unsigned long insn, extension; +{ + State.regs[REG_MDRQ] = State.regs[REG_D0 + REG0 (insn)]; +} + +/* getx dm,dm */ +void OP_F6F0 (insn, extension) + unsigned long insn, extension; +{ + int z, n; + z = (State.regs[REG_MDRQ] == 0); + n = ((State.regs[REG_MDRQ] & 0x80000000) != 0); + State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDRQ]; + + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); +} + +/* mulq dm,dn */ +void OP_F600 (insn, extension) + unsigned long insn, extension; +{ + unsigned long long temp; + int n, z; + + temp = ((signed64)(signed32)State.regs[REG_D0 + REG0 (insn)] + * (signed64)(signed32)State.regs[REG_D0 + REG1 (insn)]); + State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; + State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; + z = (State.regs[REG_D0 + REG0 (insn)] == 0); + n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* mulq imm8,dn */ +void OP_F90000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long long temp; + int n, z; + + temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_8 (insn)] + * (signed64)(signed32)SEXT8 (insn & 0xff)); + State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff; + State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; + z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* mulq imm16,dn */ +void OP_FB000000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long long temp; + int n, z; + + temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_16 (insn)] + * (signed64)(signed32)SEXT16 (insn & 0xffff)); + State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff; + State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; + z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* mulq imm32,dn */ +void OP_FD000000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long long temp; + int n, z; + + temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_16 (insn)] + * (signed64)(signed32)(((insn & 0xffff) << 16) + extension)); + State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff; + State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; + z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* mulqu dm,dn */ +void OP_F610 (insn, extension) + unsigned long insn, extension; +{ + unsigned long long temp; + int n, z; + + temp = ((unsigned64) State.regs[REG_D0 + REG0 (insn)] + * (unsigned64) State.regs[REG_D0 + REG1 (insn)]); + State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff; + State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; + z = (State.regs[REG_D0 + REG0 (insn)] == 0); + n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* mulqu imm8,dn */ +void OP_F91400 (insn, extension) + unsigned long insn, extension; +{ + unsigned long long temp; + int n, z; + + temp = ((unsigned64)State.regs[REG_D0 + REG0_8 (insn)] + * (unsigned64)SEXT8 (insn & 0xff)); + State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff; + State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; + z = (State.regs[REG_D0 + REG0_8 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* mulqu imm16,dn */ +void OP_FB140000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long long temp; + int n, z; + + temp = ((unsigned64)State.regs[REG_D0 + REG0_16 (insn)] + * (unsigned64) SEXT16 (insn & 0xffff)); + State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff; + State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; + z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* mulqu imm32,dn */ +void OP_FD140000 (insn, extension) + unsigned long insn, extension; +{ + unsigned long long temp; + int n, z; + + temp = ((unsigned64)State.regs[REG_D0 + REG0_16 (insn)] + * (unsigned64)(((insn & 0xffff) << 16) + extension)); + State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff; + State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;; + z = (State.regs[REG_D0 + REG0_16 (insn)] == 0); + n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0; + PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); + PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); +} + +/* sat16 dm,dn */ +void OP_F640 (insn, extension) + unsigned long insn, extension; +{ + int temp; + + temp = State.regs[REG_D0 + REG1 (insn)]; + temp = (temp > 0x7fff ? 0x7fff : temp); + temp = (temp < -0x8000 ? -0x8000 : temp); + State.regs[REG_D0 + REG0 (insn)] = temp; +} + +/* sat24 dm,dn */ +void OP_F650 (insn, extension) + unsigned long insn, extension; +{ + int temp; + + temp = State.regs[REG_D0 + REG1 (insn)]; + temp = (temp > 0x7fffff ? 0x7fffff : temp); + temp = (temp < -0x800000 ? -0x800000 : temp); + State.regs[REG_D0 + REG0 (insn)] = temp; +} + +/* bsch dm,dn */ +void OP_F670 (insn, extension) + unsigned long insn, extension; +{ + int temp, c; + + temp = State.regs[REG_D0 + REG1 (insn)]; + temp <<= (State.regs[REG_D0 + REG0 (insn)] & 0x1f); + c = (temp != 0 ? 1 : 0); + PSW &= ~(PSW_C); + PSW |= (c ? PSW_C : 0); +} + +/* breakpoint */ +void +OP_FF (insn, extension) + unsigned long insn, extension; +{ + State.exception = SIGTRAP; + PC -= 1; +} +

simops.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: mn10300_sim.h =================================================================== --- mn10300_sim.h (nonexistent) +++ mn10300_sim.h (revision 1765) @@ -0,0 +1,390 @@ +#include +#include +#include "ansidecl.h" +#include "callback.h" +#include "opcode/mn10300.h" +#include +#include "remote-sim.h" +#include "bfd.h" + +#ifndef INLINE +#ifdef __GNUC__ +#define INLINE inline +#else +#define INLINE +#endif +#endif + +extern host_callback *mn10300_callback; +extern SIM_DESC simulator; + +#define DEBUG_TRACE 0x00000001 +#define DEBUG_VALUES 0x00000002 + +extern int mn10300_debug; + +#if UCHAR_MAX == 255 +typedef unsigned char uint8; +typedef signed char int8; +#else +#error "Char is not an 8-bit type" +#endif + +#if SHRT_MAX == 32767 +typedef unsigned short uint16; +typedef signed short int16; +#else +#error "Short is not a 16-bit type" +#endif + +#if INT_MAX == 2147483647 + +typedef unsigned int uint32; +typedef signed int int32; + +#else +# if LONG_MAX == 2147483647 + +typedef unsigned long uint32; +typedef signed long int32; + +# else +# error "Neither int nor long is a 32-bit type" +# endif +#endif + +typedef uint32 reg_t; + +struct simops +{ + long opcode; + long mask; + void (*func)(); + int length; + int format; + int numops; + int operands[16]; +}; + +/* The current state of the processor; registers, memory, etc. */ + +struct _state +{ + reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw, + lir, lar, mdrq, plus some room for processor + specific regs. */ + uint8 *mem; /* main memory */ + int exception; + int exited; + + /* All internal state modified by signal_exception() that may need to be + rolled back for passing moment-of-exception image back to gdb. */ + reg_t exc_trigger_regs[32]; + reg_t exc_suspend_regs[32]; + int exc_suspended; + +#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA) +#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC) +#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC) +}; + +extern struct _state State; +extern uint32 OP[4]; +extern struct simops Simops[]; + +#define PC (State.regs[REG_PC]) +#define SP (State.regs[REG_SP]) + +#define PSW (State.regs[11]) +#define PSW_Z 0x1 +#define PSW_N 0x2 +#define PSW_C 0x4 +#define PSW_V 0x8 +#define PSW_IE LSBIT (11) +#define PSW_LM LSMASK (10, 8) + +#define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8) +#define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8) + +#define REG_D0 0 +#define REG_A0 4 +#define REG_SP 8 +#define REG_PC 9 +#define REG_MDR 10 +#define REG_PSW 11 +#define REG_LIR 12 +#define REG_LAR 13 +#define REG_MDRQ 14 +#define REG_E0 15 +#define REG_SSP 23 +#define REG_MSP 24 +#define REG_USP 25 +#define REG_MCRH 26 +#define REG_MCRL 27 +#define REG_MCVF 28 + +#if WITH_COMMON +/* These definitions conflict with similar macros in common. */ +#else +#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4) + +/* sign-extend a 4-bit number */ +#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8) + +/* sign-extend a 5-bit number */ +#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10) + +/* sign-extend an 8-bit number */ +#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80) + +/* sign-extend a 9-bit number */ +#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100) + +/* sign-extend a 16-bit number */ +#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000) + +/* sign-extend a 22-bit number */ +#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000) + +#define MAX32 0x7fffffffLL +#define MIN32 0xff80000000LL +#define MASK32 0xffffffffLL +#define MASK40 0xffffffffffLL +#endif /* not WITH_COMMON */ + +#ifdef _WIN32 +#define SIGTRAP 5 +#define SIGQUIT 3 +#endif + +#if WITH_COMMON + +#define FETCH32(a,b,c,d) \ + ((a)+((b)<<8)+((c)<<16)+((d)<<24)) + +#define FETCH24(a,b,c) \ + ((a)+((b)<<8)+((c)<<16)) + +#define FETCH16(a,b) ((a)+((b)<<8)) + +#define load_byte(ADDR) \ +sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR)) + +#define load_half(ADDR) \ +sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR)) + +#define load_word(ADDR) \ +sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR)) + +#define store_byte(ADDR, DATA) \ +sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \ + PC, write_map, (ADDR), (DATA)) + + +#define store_half(ADDR, DATA) \ +sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \ + PC, write_map, (ADDR), (DATA)) + + +#define store_word(ADDR, DATA) \ +sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \ + PC, write_map, (ADDR), (DATA)) +#endif /* WITH_COMMON */ + +#if WITH_COMMON +#else +#define load_mem_big(addr,len) \ + (len == 1 ? *((addr) + State.mem) : \ + len == 2 ? ((*((addr) + State.mem) << 8) \ + | *(((addr) + 1) + State.mem)) : \ + len == 3 ? ((*((addr) + State.mem) << 16) \ + | (*(((addr) + 1) + State.mem) << 8) \ + | *(((addr) + 2) + State.mem)) : \ + ((*((addr) + State.mem) << 24) \ + | (*(((addr) + 1) + State.mem) << 16) \ + | (*(((addr) + 2) + State.mem) << 8) \ + | *(((addr) + 3) + State.mem))) + +static INLINE uint32 +load_byte (addr) + SIM_ADDR addr; +{ + uint8 *p = (addr & 0xffffff) + State.mem; + +#ifdef CHECK_ADDR + if ((addr & 0xffffff) > max_mem) + abort (); +#endif + + return p[0]; +} + +static INLINE uint32 +load_half (addr) + SIM_ADDR addr; +{ + uint8 *p = (addr & 0xffffff) + State.mem; + +#ifdef CHECK_ADDR + if ((addr & 0xffffff) > max_mem) + abort (); +#endif + + return p[1] << 8 | p[0]; +} + +static INLINE uint32 +load_3_byte (addr) + SIM_ADDR addr; +{ + uint8 *p = (addr & 0xffffff) + State.mem; + +#ifdef CHECK_ADDR + if ((addr & 0xffffff) > max_mem) + abort (); +#endif + + return p[2] << 16 | p[1] << 8 | p[0]; +} + +static INLINE uint32 +load_word (addr) + SIM_ADDR addr; +{ + uint8 *p = (addr & 0xffffff) + State.mem; + +#ifdef CHECK_ADDR + if ((addr & 0xffffff) > max_mem) + abort (); +#endif + + return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0]; +} + +static INLINE uint32 +load_mem (addr, len) + SIM_ADDR addr; + int len; +{ + uint8 *p = (addr & 0xffffff) + State.mem; + +#ifdef CHECK_ADDR + if ((addr & 0xffffff) > max_mem) + abort (); +#endif + + switch (len) + { + case 1: + return p[0]; + case 2: + return p[1] << 8 | p[0]; + case 3: + return p[2] << 16 | p[1] << 8 | p[0]; + case 4: + return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0]; + default: + abort (); + } +} + +static INLINE void +store_byte (addr, data) + SIM_ADDR addr; + uint32 data; +{ + uint8 *p = (addr & 0xffffff) + State.mem; + +#ifdef CHECK_ADDR + if ((addr & 0xffffff) > max_mem) + abort (); +#endif + + p[0] = data; +} + +static INLINE void +store_half (addr, data) + SIM_ADDR addr; + uint32 data; +{ + uint8 *p = (addr & 0xffffff) + State.mem; + +#ifdef CHECK_ADDR + if ((addr & 0xffffff) > max_mem) + abort (); +#endif + + p[0] = data; + p[1] = data >> 8; +} + +static INLINE void +store_3_byte (addr, data) + SIM_ADDR addr; + uint32 data; +{ + uint8 *p = (addr & 0xffffff) + State.mem; + +#ifdef CHECK_ADDR + if ((addr & 0xffffff) > max_mem) + abort (); +#endif + + p[0] = data; + p[1] = data >> 8; + p[2] = data >> 16; +} + +static INLINE void +store_word (addr, data) + SIM_ADDR addr; + uint32 data; +{ + uint8 *p = (addr & 0xffffff) + State.mem; + +#ifdef CHECK_ADDR + if ((addr & 0xffffff) > max_mem) + abort (); +#endif + + p[0] = data; + p[1] = data >> 8; + p[2] = data >> 16; + p[3] = data >> 24; +} +#endif /* not WITH_COMMON */ + +/* Function declarations. */ + +uint32 get_word PARAMS ((uint8 *)); +uint16 get_half PARAMS ((uint8 *)); +uint8 get_byte PARAMS ((uint8 *)); +void put_word PARAMS ((uint8 *, uint32)); +void put_half PARAMS ((uint8 *, uint16)); +void put_byte PARAMS ((uint8 *, uint8)); + +extern uint8 *map PARAMS ((SIM_ADDR addr)); + +INLINE_SIM_MAIN (void) genericAdd PARAMS ((unsigned32 source, unsigned32 destReg)); +INLINE_SIM_MAIN (void) genericSub PARAMS ((unsigned32 source, unsigned32 destReg)); +INLINE_SIM_MAIN (void) genericCmp PARAMS ((unsigned32 leftOpnd, unsigned32 rightOpnd)); +INLINE_SIM_MAIN (void) genericOr PARAMS ((unsigned32 source, unsigned32 destReg)); +INLINE_SIM_MAIN (void) genericXor PARAMS ((unsigned32 source, unsigned32 destReg)); +INLINE_SIM_MAIN (void) genericBtst PARAMS ((unsigned32 leftOpnd, unsigned32 rightOpnd)); +INLINE_SIM_MAIN (int) syscall_read_mem PARAMS ((host_callback *cb, + struct cb_syscall *sc, + unsigned long taddr, + char *buf, + int bytes)); +INLINE_SIM_MAIN (int) syscall_write_mem PARAMS ((host_callback *cb, + struct cb_syscall *sc, + unsigned long taddr, + const char *buf, + int bytes)); +INLINE_SIM_MAIN (void) do_syscall PARAMS ((void)); +void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig); + +void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc); +void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception); +void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);

mn10300_sim.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: dv-mn103iop.c =================================================================== --- dv-mn103iop.c (nonexistent) +++ dv-mn103iop.c (revision 1765) @@ -0,0 +1,555 @@ +/* This file is part of the program GDB, the GNU debugger. + + Copyright (C) 1998 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + */ + +#include "sim-main.h" +#include "hw-main.h" + +/* DEVICE + + + mn103iop - mn103002 I/O ports 0-3. + + + DESCRIPTION + + Implements the mn103002 i/o ports as described in the mn103002 user guide. + + + PROPERTIES + + reg =

... + + + BUGS + + */ + + +/* The I/O ports' registers' address block */ + +struct mn103iop_block { + unsigned_word base; + unsigned_word bound; +}; + + + +enum io_port_register_types { + P0OUT, + P1OUT, + P2OUT, + P3OUT, + P0MD, + P1MD, + P2MD, + P3MD, + P2SS, + P4SS, + P0DIR, + P1DIR, + P2DIR, + P3DIR, + P0IN, + P1IN, + P2IN, + P3IN, +}; + +#define NR_PORTS 4 + +enum { + OUTPUT_BLOCK, + MODE_BLOCK, + DED_CTRL_BLOCK, + CTRL_BLOCK, + PIN_BLOCK, + NR_BLOCKS +}; + +typedef struct _mn10300_ioport { + unsigned8 output, output_mode, control, pin; + struct hw_event *event; +} mn10300_ioport; + + + +struct mn103iop { + struct mn103iop_block block[NR_BLOCKS]; + mn10300_ioport port[NR_PORTS]; + unsigned8 p2ss, p4ss; +}; + + +/* Finish off the partially created hw device. Attach our local + callbacks. Wire up our port names etc */ + +static hw_io_read_buffer_method mn103iop_io_read_buffer; +static hw_io_write_buffer_method mn103iop_io_write_buffer; + +static void +attach_mn103iop_regs (struct hw *me, + struct mn103iop *io_port) +{ + int i; + unsigned_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + for (i=0; i < NR_BLOCKS; ++i ) + { + if (!hw_find_reg_array_property (me, "reg", i, ®)) + hw_abort (me, "\"reg\" property must contain five addr/size entries"); + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, + &attach_address, + me); + io_port->block[i].base = attach_address; + hw_unit_size_to_attach_size (hw_parent (me), + ®.size, + &attach_size, me); + io_port->block[i].bound = attach_address + (attach_size - 1); + hw_attach_address (hw_parent (me), + 0, + attach_space, attach_address, attach_size, + me); + } +} + +static void +mn103iop_finish (struct hw *me) +{ + struct mn103iop *io_port; + int i; + + io_port = HW_ZALLOC (me, struct mn103iop); + set_hw_data (me, io_port); + set_hw_io_read_buffer (me, mn103iop_io_read_buffer); + set_hw_io_write_buffer (me, mn103iop_io_write_buffer); + + /* Attach ourself to our parent bus */ + attach_mn103iop_regs (me, io_port); + + /* Initialize the i/o port registers. */ + for ( i=0; iport[i].output = 0; + io_port->port[i].output_mode = 0; + io_port->port[i].control = 0; + io_port->port[i].pin = 0; + } + io_port->port[2].output_mode = 0xff; + io_port->p2ss = 0; + io_port->p4ss = 0x0f; +} + + +/* read and write */ + +static int +decode_addr (struct hw *me, + struct mn103iop *io_port, + unsigned_word address) +{ + unsigned_word offset; + offset = address - io_port->block[0].base; + switch (offset) + { + case 0x00: return P0OUT; + case 0x01: return P1OUT; + case 0x04: return P2OUT; + case 0x05: return P3OUT; + case 0x20: return P0MD; + case 0x21: return P1MD; + case 0x24: return P2MD; + case 0x25: return P3MD; + case 0x44: return P2SS; + case 0x48: return P4SS; + case 0x60: return P0DIR; + case 0x61: return P1DIR; + case 0x64: return P2DIR; + case 0x65: return P3DIR; + case 0x80: return P0IN; + case 0x81: return P1IN; + case 0x84: return P2IN; + case 0x85: return P3IN; + default: + { + hw_abort (me, "bad address"); + return -1; + } + } +} + + +static void +read_output_reg (struct hw *me, + struct mn103iop *io_port, + unsigned_word io_port_reg, + const void *dest, + unsigned nr_bytes) +{ + if ( nr_bytes == 1 ) + { + *(unsigned8 *)dest = io_port->port[io_port_reg].output; + } + else + { + hw_abort (me, "bad read size of %d bytes from P%dOUT.", nr_bytes, + io_port_reg); + } +} + + +static void +read_output_mode_reg (struct hw *me, + struct mn103iop *io_port, + unsigned_word io_port_reg, + const void *dest, + unsigned nr_bytes) +{ + if ( nr_bytes == 1 ) + { + /* check if there are fields which can't be written and + take appropriate action depending what bits are set */ + *(unsigned8 *)dest = io_port->port[io_port_reg].output_mode; + } + else + { + hw_abort (me, "bad read size of %d bytes to P%dMD.", nr_bytes, + io_port_reg); + } +} + + +static void +read_control_reg (struct hw *me, + struct mn103iop *io_port, + unsigned_word io_port_reg, + const void *dest, + unsigned nr_bytes) +{ + if ( nr_bytes == 1 ) + { + *(unsigned8 *)dest = io_port->port[io_port_reg].control; + } + else + { + hw_abort (me, "bad read size of %d bytes to P%dDIR.", nr_bytes, + io_port_reg); + } +} + + +static void +read_pin_reg (struct hw *me, + struct mn103iop *io_port, + unsigned_word io_port_reg, + const void *dest, + unsigned nr_bytes) +{ + if ( nr_bytes == 1 ) + { + *(unsigned8 *)dest = io_port->port[io_port_reg].pin; + } + else + { + hw_abort (me, "bad read size of %d bytes to P%dIN.", nr_bytes, + io_port_reg); + } +} + + +static void +read_dedicated_control_reg (struct hw *me, + struct mn103iop *io_port, + unsigned_word io_port_reg, + const void *dest, + unsigned nr_bytes) +{ + if ( nr_bytes == 1 ) + { + /* select on io_port_reg: */ + if ( io_port_reg == P2SS ) + { + *(unsigned8 *)dest = io_port->p2ss; + } + else + { + *(unsigned8 *)dest = io_port->p4ss; + } + } + else + { + hw_abort (me, "bad read size of %d bytes to PSS.", nr_bytes); + } +} + + +static unsigned +mn103iop_io_read_buffer (struct hw *me, + void *dest, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct mn103iop *io_port = hw_data (me); + enum io_port_register_types io_port_reg; + HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); + + io_port_reg = decode_addr (me, io_port, base); + switch (io_port_reg) + { + /* Port output registers */ + case P0OUT: + case P1OUT: + case P2OUT: + case P3OUT: + read_output_reg(me, io_port, io_port_reg-P0OUT, dest, nr_bytes); + break; + + /* Port output mode registers */ + case P0MD: + case P1MD: + case P2MD: + case P3MD: + read_output_mode_reg(me, io_port, io_port_reg-P0MD, dest, nr_bytes); + break; + + /* Port control registers */ + case P0DIR: + case P1DIR: + case P2DIR: + case P3DIR: + read_control_reg(me, io_port, io_port_reg-P0DIR, dest, nr_bytes); + break; + + /* Port pin registers */ + case P0IN: + case P1IN: + case P2IN: + read_pin_reg(me, io_port, io_port_reg-P0IN, dest, nr_bytes); + break; + + case P2SS: + case P4SS: + read_dedicated_control_reg(me, io_port, io_port_reg, dest, nr_bytes); + break; + + default: + hw_abort(me, "invalid address"); + } + + return nr_bytes; +} + + +static void +write_output_reg (struct hw *me, + struct mn103iop *io_port, + unsigned_word io_port_reg, + const void *source, + unsigned nr_bytes) +{ + unsigned8 buf = *(unsigned8 *)source; + if ( nr_bytes == 1 ) + { + if ( io_port_reg == 3 && (buf & 0xfc) != 0 ) + { + hw_abort(me, "Cannot write to read-only bits of P3OUT."); + } + else + { + io_port->port[io_port_reg].output = buf; + } + } + else + { + hw_abort (me, "bad read size of %d bytes from P%dOUT.", nr_bytes, + io_port_reg); + } +} + + +static void +write_output_mode_reg (struct hw *me, + struct mn103iop *io_port, + unsigned_word io_port_reg, + const void *source, + unsigned nr_bytes) +{ + unsigned8 buf = *(unsigned8 *)source; + if ( nr_bytes == 1 ) + { + /* check if there are fields which can't be written and + take appropriate action depending what bits are set */ + if ( ( io_port_reg == 3 && (buf & 0xfc) != 0 ) + || ( (io_port_reg == 0 || io_port_reg == 1) && (buf & 0xfe) != 0 ) ) + { + hw_abort(me, "Cannot write to read-only bits of output mode register."); + } + else + { + io_port->port[io_port_reg].output_mode = buf; + } + } + else + { + hw_abort (me, "bad write size of %d bytes to P%dMD.", nr_bytes, + io_port_reg); + } +} + + +static void +write_control_reg (struct hw *me, + struct mn103iop *io_port, + unsigned_word io_port_reg, + const void *source, + unsigned nr_bytes) +{ + unsigned8 buf = *(unsigned8 *)source; + if ( nr_bytes == 1 ) + { + if ( io_port_reg == 3 && (buf & 0xfc) != 0 ) + { + hw_abort(me, "Cannot write to read-only bits of P3DIR."); + } + else + { + io_port->port[io_port_reg].control = buf; + } + } + else + { + hw_abort (me, "bad write size of %d bytes to P%dDIR.", nr_bytes, + io_port_reg); + } +} + + +static void +write_dedicated_control_reg (struct hw *me, + struct mn103iop *io_port, + unsigned_word io_port_reg, + const void *source, + unsigned nr_bytes) +{ + unsigned8 buf = *(unsigned8 *)source; + if ( nr_bytes == 1 ) + { + /* select on io_port_reg: */ + if ( io_port_reg == P2SS ) + { + if ( (buf && 0xfc) != 0 ) + { + hw_abort(me, "Cannot write to read-only bits in p2ss."); + } + else + { + io_port->p2ss = buf; + } + } + else + { + if ( (buf && 0xf0) != 0 ) + { + hw_abort(me, "Cannot write to read-only bits in p4ss."); + } + else + { + io_port->p4ss = buf; + } + } + } + else + { + hw_abort (me, "bad write size of %d bytes to PSS.", nr_bytes); + } +} + + +static unsigned +mn103iop_io_write_buffer (struct hw *me, + const void *source, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct mn103iop *io_port = hw_data (me); + enum io_port_register_types io_port_reg; + HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); + + io_port_reg = decode_addr (me, io_port, base); + switch (io_port_reg) + { + /* Port output registers */ + case P0OUT: + case P1OUT: + case P2OUT: + case P3OUT: + write_output_reg(me, io_port, io_port_reg-P0OUT, source, nr_bytes); + break; + + /* Port output mode registers */ + case P0MD: + case P1MD: + case P2MD: + case P3MD: + write_output_mode_reg(me, io_port, io_port_reg-P0MD, source, nr_bytes); + break; + + /* Port control registers */ + case P0DIR: + case P1DIR: + case P2DIR: + case P3DIR: + write_control_reg(me, io_port, io_port_reg-P0DIR, source, nr_bytes); + break; + + /* Port pin registers */ + case P0IN: + case P1IN: + case P2IN: + hw_abort(me, "Cannot write to pin register."); + break; + + case P2SS: + case P4SS: + write_dedicated_control_reg(me, io_port, io_port_reg, source, nr_bytes); + break; + + default: + hw_abort(me, "invalid address"); + } + + return nr_bytes; +} + + +const struct hw_descriptor dv_mn103iop_descriptor[] = { + { "mn103iop", mn103iop_finish, }, + { NULL }, +};

dv-mn103iop.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: dv-mn103cpu.c =================================================================== --- dv-mn103cpu.c (nonexistent) +++ dv-mn103cpu.c (revision 1765) @@ -0,0 +1,431 @@ +/* This file is part of the program GDB, the GNU debugger. + + Copyright (C) 1998 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + */ + + +#include "sim-main.h" +#include "hw-main.h" + +/* DEVICE + + + mn103cpu - mn10300 cpu virtual device + + + DESCRIPTION + + + Implements the external mn10300 functionality. This includes the + delivery of interrupts generated from other devices and the + handling of device specific registers. + + + PROPERTIES + + + reg =

+ + Specify the address of the mn10300's control register block. This + block contains the Interrupt Vector Registers. + + The reg property value `0x20000000 0x42' locates the register block + at the address specified in the mn10300 user guide. + + + PORTS + + + reset (input) + + Currently ignored. + + + nmi (input) + + Deliver a non-maskable interrupt to the processor. + + + level (input) + + Maskable interrupt level port port. The interrupt controller + notifies the processor of any change in the level of pending + requested interrupts via this port. + + + ack (output) + + Output signal indicating that the processor is delivering a level + interrupt. The value passed with the event specifies the level of + the interrupt being delivered. + + + BUGS + + + When delivering an interrupt, this code assumes that there is only + one processor (number 0). + + This code does not attempt to be efficient at handling pending + interrupts. It simply schedules the interrupt delivery handler + every instruction cycle until all pending interrupts go away. An + alternative implementation might modify instructions that change + the PSW and have them check to see if the change makes an interrupt + delivery possible. + + */ + + +/* The interrupt vectors */ + +enum { NR_VECTORS = 7, }; + + +/* The interrupt controller register address blocks */ + +struct mn103cpu_block { + unsigned_word base; + unsigned_word bound; +}; + + +struct mn103cpu { + struct mn103cpu_block block; + struct hw_event *pending_handler; + int pending_level; + int pending_nmi; + int pending_reset; + /* the visible registers */ + unsigned16 interrupt_vector[NR_VECTORS]; + unsigned16 internal_memory_control; + unsigned16 cpu_mode; +}; + + + +/* input port ID's */ + +enum { + RESET_PORT, + NMI_PORT, + LEVEL_PORT, +}; + + +/* output port ID's */ + +enum { + ACK_PORT, +}; + +static const struct hw_port_descriptor mn103cpu_ports[] = { + + /* interrupt inputs */ + { "reset", RESET_PORT, 0, input_port, }, + { "nmi", NMI_PORT, 0, input_port, }, + { "level", LEVEL_PORT, 0, input_port, }, + + /* interrupt ack (latch) output from cpu */ + { "ack", ACK_PORT, 0, output_port, }, + + { NULL, }, +}; + + +/* Finish off the partially created hw device. Attach our local + callbacks. Wire up our port names etc */ + +static hw_io_read_buffer_method mn103cpu_io_read_buffer; +static hw_io_write_buffer_method mn103cpu_io_write_buffer; +static hw_port_event_method mn103cpu_port_event; + +static void +attach_mn103cpu_regs (struct hw *me, + struct mn103cpu *controller) +{ + unsigned_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, + &attach_address, + me); + controller->block.base = attach_address; + hw_unit_size_to_attach_size (hw_parent (me), + ®.size, + &attach_size, me); + controller->block.bound = attach_address + (attach_size - 1); + if ((controller->block.base & 3) != 0) + hw_abort (me, "cpu register block must be 4 byte aligned"); + hw_attach_address (hw_parent (me), + 0, + attach_space, attach_address, attach_size, + me); +} + + +static void +mn103cpu_finish (struct hw *me) +{ + struct mn103cpu *controller; + + controller = HW_ZALLOC (me, struct mn103cpu); + set_hw_data (me, controller); + set_hw_io_read_buffer (me, mn103cpu_io_read_buffer); + set_hw_io_write_buffer (me, mn103cpu_io_write_buffer); + set_hw_ports (me, mn103cpu_ports); + set_hw_port_event (me, mn103cpu_port_event); + + /* Attach ourself to our parent bus */ + attach_mn103cpu_regs (me, controller); + + /* Initialize the read-only registers */ + controller->pending_level = 7; /* FIXME */ + /* ... */ +} + + + +/* An event arrives on an interrupt port */ + +static void +deliver_mn103cpu_interrupt (struct hw *me, + void *data) +{ + struct mn103cpu *controller = hw_data (me); + SIM_DESC simulator = hw_system (me); + sim_cpu *cpu = STATE_CPU (simulator, 0); + + if (controller->pending_reset) + { + controller->pending_reset = 0; + /* need to clear all registers et.al! */ + HW_TRACE ((me, "Reset!")); + hw_abort (me, "Reset!"); + } + else if (controller->pending_nmi) + { + controller->pending_nmi = 0; + store_word (SP - 4, CIA_GET (cpu)); + store_half (SP - 8, PSW); + PSW &= ~PSW_IE; + SP = SP - 8; + CIA_SET (cpu, 0x40000008); + HW_TRACE ((me, "nmi pc=0x%08lx psw=0x%04x sp=0x%08lx", + (long) CIA_GET (cpu), (unsigned) PSW, (long) SP)); + } + else if ((controller->pending_level < EXTRACT_PSW_LM) + && (PSW & PSW_IE)) + { + /* Don't clear pending level. Request continues to be pending + until the interrupt controller clears/changes it */ + store_word (SP - 4, CIA_GET (cpu)); + store_half (SP - 8, PSW); + PSW &= ~PSW_IE; + PSW &= ~PSW_LM; + PSW |= INSERT_PSW_LM (controller->pending_level); + SP = SP - 8; + CIA_SET (cpu, 0x40000000 + controller->interrupt_vector[controller->pending_level]); + HW_TRACE ((me, "port-out ack %d", controller->pending_level)); + hw_port_event (me, ACK_PORT, controller->pending_level); + HW_TRACE ((me, "int level=%d pc=0x%08lx psw=0x%04x sp=0x%08lx", + controller->pending_level, + (long) CIA_GET (cpu), (unsigned) PSW, (long) SP)); + } + + if (controller->pending_level < 7) /* FIXME */ + { + /* As long as there is the potential need to deliver an + interrupt we keep rescheduling this routine. */ + if (controller->pending_handler != NULL) + controller->pending_handler = + hw_event_queue_schedule (me, 1, deliver_mn103cpu_interrupt, NULL); + } + else + { + /* Don't bother re-scheduling the interrupt handler as there is + nothing to deliver */ + controller->pending_handler = NULL; + } + +} + + +static void +mn103cpu_port_event (struct hw *me, + int my_port, + struct hw *source, + int source_port, + int level) +{ + struct mn103cpu *controller = hw_data (me); + + /* Schedule our event handler *now* */ + if (controller->pending_handler == NULL) + controller->pending_handler = + hw_event_queue_schedule (me, 0, deliver_mn103cpu_interrupt, NULL); + + switch (my_port) + { + + case RESET_PORT: + controller->pending_reset = 1; + HW_TRACE ((me, "port-in reset")); + break; + + case NMI_PORT: + controller->pending_nmi = 1; + HW_TRACE ((me, "port-in nmi")); + break; + + case LEVEL_PORT: + controller->pending_level = level; + HW_TRACE ((me, "port-in level=%d", level)); + break; + + default: + hw_abort (me, "bad switch"); + break; + + } +} + + +/* Read/write to a CPU register */ + +enum mn103cpu_regs { + INVALID_REG, + IVR0_REG, + IVR1_REG, + IVR2_REG, + IVR3_REG, + IVR4_REG, + IVR5_REG, + IVR6_REG, + IMCR_REG, + CPUM_REG, +}; + +static enum mn103cpu_regs +decode_mn103cpu_addr (struct hw *me, + struct mn103cpu *controller, + unsigned_word base) +{ + switch (base - controller->block.base) + { + case 0x000: return IVR0_REG; + case 0x004: return IVR1_REG; + case 0x008: return IVR2_REG; + case 0x00c: return IVR3_REG; + case 0x010: return IVR4_REG; + case 0x014: return IVR5_REG; + case 0x018: return IVR6_REG; + case 0x020: return IMCR_REG; + case 0x040: return CPUM_REG; + default: return INVALID_REG; + } +} + +static unsigned +mn103cpu_io_read_buffer (struct hw *me, + void *dest, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct mn103cpu *controller = hw_data (me); + unsigned16 val = 0; + enum mn103cpu_regs reg = decode_mn103cpu_addr (me, controller, base); + + switch (reg) + { + case IVR0_REG: + case IVR1_REG: + case IVR2_REG: + case IVR3_REG: + case IVR4_REG: + case IVR5_REG: + case IVR6_REG: + val = controller->interrupt_vector[reg - IVR0_REG]; + break; + case IMCR_REG: + val = controller->internal_memory_control; + break; + case CPUM_REG: + val = controller->cpu_mode; + break; + default: + /* just ignore the read */ + break; + } + + if (nr_bytes == 2) + *(unsigned16*) dest = H2LE_2 (val); + + return nr_bytes; +} + +static unsigned +mn103cpu_io_write_buffer (struct hw *me, + const void *source, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct mn103cpu *controller = hw_data (me); + unsigned16 val; + enum mn103cpu_regs reg; + + if (nr_bytes != 2) + hw_abort (me, "must be two byte write"); + + reg = decode_mn103cpu_addr (me, controller, base); + val = LE2H_2 (* (unsigned16 *) source); + + switch (reg) + { + case IVR0_REG: + case IVR1_REG: + case IVR2_REG: + case IVR3_REG: + case IVR4_REG: + case IVR5_REG: + case IVR6_REG: + controller->interrupt_vector[reg - IVR0_REG] = val; + HW_TRACE ((me, "ivr%d = 0x%04lx", reg - IVR0_REG, (long) val)); + break; + default: + /* just ignore the write */ + break; + } + + return nr_bytes; +} + + +const struct hw_descriptor dv_mn103cpu_descriptor[] = { + { "mn103cpu", mn103cpu_finish, }, + { NULL }, +};

dv-mn103cpu.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: tconfig.in =================================================================== --- tconfig.in (nonexistent) +++ tconfig.in (revision 1765) @@ -0,0 +1,26 @@ +/* mn10300 target configuration file. */ + +/* FIXME: This is unnecessarily necessary: */ +#include "ansidecl.h" +#include "callback.h" +#include "remote-sim.h" +#include "sim-module.h" + +MODULE_INSTALL_FN dv_sockser_install; +#define MODULE_LIST dv_sockser_install, + +/* Define this if the simulator supports profiling. + See the mips simulator for an example. + This enables the `-p foo' and `-s bar' options. + The target is required to provide sim_set_profile{,_size}. */ +/* #define SIM_HAVE_PROFILE */ + +/* Define this if the simulator uses an instruction cache. + See the h8/300 simulator for an example. + This enables the `-c size' option to set the size of the cache. + The target is required to provide sim_set_simcache_size. */ +/* #define SIM_HAVE_SIMCACHE */ + +/* Define this if the target cpu is bi-endian + and the simulator supports it. */ +/* #define SIM_HAVE_BIENDIAN */

tconfig.in Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: acconfig.h =================================================================== --- acconfig.h (nonexistent) +++ acconfig.h (revision 1765) @@ -0,0 +1,15 @@ + +/* Define to 1 if NLS is requested. */ +#undef ENABLE_NLS + +/* Define as 1 if you have catgets and don't want to use GNU gettext. */ +#undef HAVE_CATGETS + +/* Define as 1 if you have gettext and don't want to use GNU gettext. */ +#undef HAVE_GETTEXT + +/* Define as 1 if you have the stpcpy function. */ +#undef HAVE_STPCPY + +/* Define if your locale.h file contains LC_MESSAGES. */ +#undef HAVE_LC_MESSAGES

acconfig.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: dv-mn103tim.c =================================================================== --- dv-mn103tim.c (nonexistent) +++ dv-mn103tim.c (revision 1765) @@ -0,0 +1,1032 @@ +/* This file is part of the program GDB, the GNU debugger. + + Copyright (C) 1998 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + */ + +#include "sim-main.h" +#include "hw-main.h" +#include "sim-assert.h" + +/* DEVICE + + + mn103tim - mn103002 timers (8 and 16 bit) + + + DESCRIPTION + + Implements the mn103002 8 and 16 bit timers as described in the mn103002 user guide. + + + PROPERTIES + + reg = <8bit-timers-addr> <8bit-timers-size> <16bit-timers-addr> <16bit-timers-size> + + + BUGS + + */ + + +/* The timers' register address blocks */ + +struct mn103tim_block { + unsigned_word base; + unsigned_word bound; +}; + +enum { TIMER8_BLOCK, TIMER16_BLOCK, NR_TIMER_BLOCKS }; + +enum timer_register_types { + FIRST_MODE_REG = 0, + TM0MD = FIRST_MODE_REG, + TM1MD, + TM2MD, + TM3MD, + TM4MD, + TM5MD, + TM6MD, + LAST_MODE_REG = TM6MD, + FIRST_BASE_REG, + TM0BR = FIRST_BASE_REG, + TM1BR, + TM2BR, + TM3BR, + TM4BR, + TM5BR, + LAST_BASE_REG = TM5BR, + FIRST_COUNTER, + TM0BC = FIRST_COUNTER, + TM1BC, + TM2BC, + TM3BC, + TM4BC, + TM5BC, + TM6BC, + LAST_COUNTER = TM6BC, + TM6MDA, + TM6MDB, + TM6CA, + TM6CB, + LAST_TIMER_REG = TM6BC, +}; + + +/* Don't include timer 6 because it's handled specially. */ +#define NR_8BIT_TIMERS 4 +#define NR_16BIT_TIMERS 2 +#define NR_REG_TIMERS 6 /* Exclude timer 6 - it's handled specially. */ +#define NR_TIMERS 7 + +typedef struct _mn10300_timer_regs { + unsigned32 base; + unsigned8 mode; +} mn10300_timer_regs; + +typedef struct _mn10300_timer { + unsigned32 div_ratio, start; + struct hw_event *event; +} mn10300_timer; + + +struct mn103tim { + struct mn103tim_block block[NR_TIMER_BLOCKS]; + mn10300_timer_regs reg[NR_REG_TIMERS]; + mn10300_timer timer[NR_TIMERS]; + + /* treat timer 6 registers specially. */ + unsigned16 tm6md0, tm6md1, tm6bc, tm6ca, tm6cb; + unsigned8 tm6mda, tm6mdb; /* compare/capture mode regs for timer 6 */ +}; + +/* output port ID's */ + +/* for mn103002 */ +enum { + TIMER0_UFLOW, + TIMER1_UFLOW, + TIMER2_UFLOW, + TIMER3_UFLOW, + TIMER4_UFLOW, + TIMER5_UFLOW, + TIMER6_UFLOW, + TIMER6_CMPA, + TIMER6_CMPB, +}; + + +static const struct hw_port_descriptor mn103tim_ports[] = { + + { "timer-0-underflow", TIMER0_UFLOW, 0, output_port, }, + { "timer-1-underflow", TIMER1_UFLOW, 0, output_port, }, + { "timer-2-underflow", TIMER2_UFLOW, 0, output_port, }, + { "timer-3-underflow", TIMER3_UFLOW, 0, output_port, }, + { "timer-4-underflow", TIMER4_UFLOW, 0, output_port, }, + { "timer-5-underflow", TIMER5_UFLOW, 0, output_port, }, + + { "timer-6-underflow", TIMER6_UFLOW, 0, output_port, }, + { "timer-6-compare-a", TIMER6_CMPA, 0, output_port, }, + { "timer-6-compare-b", TIMER6_CMPB, 0, output_port, }, + + { NULL, }, +}; + +#define bits2to5_mask 0x3c +#define bits0to2_mask 0x07 +#define load_mask 0x40 +#define count_mask 0x80 +#define count_and_load_mask (load_mask | count_mask) +#define clock_mask 0x03 +#define clk_ioclk 0x00 +#define clk_cascaded 0x03 + + +/* Finish off the partially created hw device. Attach our local + callbacks. Wire up our port names etc */ + +static hw_io_read_buffer_method mn103tim_io_read_buffer; +static hw_io_write_buffer_method mn103tim_io_write_buffer; + +static void +attach_mn103tim_regs (struct hw *me, + struct mn103tim *timers) +{ + int i; + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + for (i = 0; i < NR_TIMER_BLOCKS; i++) + { + unsigned_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + if (!hw_find_reg_array_property (me, "reg", i, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, + &attach_address, + me); + timers->block[i].base = attach_address; + hw_unit_size_to_attach_size (hw_parent (me), + ®.size, + &attach_size, me); + timers->block[i].bound = attach_address + (attach_size - 1); + hw_attach_address (hw_parent (me), + 0, + attach_space, attach_address, attach_size, + me); + } +} + +static void +mn103tim_finish (struct hw *me) +{ + struct mn103tim *timers; + int i; + + timers = HW_ZALLOC (me, struct mn103tim); + set_hw_data (me, timers); + set_hw_io_read_buffer (me, mn103tim_io_read_buffer); + set_hw_io_write_buffer (me, mn103tim_io_write_buffer); + set_hw_ports (me, mn103tim_ports); + + /* Attach ourself to our parent bus */ + attach_mn103tim_regs (me, timers); + + /* Initialize the timers */ + for ( i=0; i < NR_REG_TIMERS; ++i ) + { + timers->reg[i].mode = 0x00; + timers->reg[i].base = 0; + } + for ( i=0; i < NR_TIMERS; ++i ) + { + timers->timer[i].event = NULL; + timers->timer[i].div_ratio = 0; + timers->timer[i].start = 0; + } + timers->tm6md0 = 0x00; + timers->tm6md1 = 0x00; + timers->tm6bc = 0x0000; + timers->tm6ca = 0x0000; + timers->tm6cb = 0x0000; + timers->tm6mda = 0x00; + timers->tm6mdb = 0x00; +} + + + +/* read and write */ + +static int +decode_addr (struct hw *me, + struct mn103tim *timers, + unsigned_word address) +{ + unsigned_word offset; + offset = address - timers->block[0].base; + + switch (offset) + { + case 0x00: return TM0MD; + case 0x01: return TM1MD; + case 0x02: return TM2MD; + case 0x03: return TM3MD; + case 0x10: return TM0BR; + case 0x11: return TM1BR; + case 0x12: return TM2BR; + case 0x13: return TM3BR; + case 0x20: return TM0BC; + case 0x21: return TM1BC; + case 0x22: return TM2BC; + case 0x23: return TM3BC; + case 0x80: return TM4MD; + case 0x82: return TM5MD; + case 0x84: /* fall through */ + case 0x85: return TM6MD; + case 0x90: return TM4BR; + case 0x92: return TM5BR; + case 0xa0: return TM4BC; + case 0xa2: return TM5BC; + case 0xa4: return TM6BC; + case 0xb4: return TM6MDA; + case 0xb5: return TM6MDB; + case 0xc4: return TM6CA; + case 0xd4: return TM6CB; + default: + { + hw_abort (me, "bad address"); + return -1; + } + } +} + +static void +read_mode_reg (struct hw *me, + struct mn103tim *timers, + int timer_nr, + void *dest, + unsigned nr_bytes) +{ + unsigned16 val16; + unsigned32 val32; + + switch ( nr_bytes ) + { + case 1: + /* Accessing 1 byte is ok for all mode registers. */ + if ( timer_nr == 6 ) + { + *(unsigned8*)dest = timers->tm6md0; + } + else + { + *(unsigned8*)dest = timers->reg[timer_nr].mode; + } + break; + + case 2: + if ( timer_nr == 6 ) + { + *(unsigned16 *)dest = (timers->tm6md0 << 8) | timers->tm6md1; + } + else if ( timer_nr == 0 || timer_nr == 2 ) + { + val16 = (timers->reg[timer_nr].mode << 8) + | timers->reg[timer_nr+1].mode; + *(unsigned16*)dest = val16; + } + else + { + hw_abort (me, "bad read size of 2 bytes to TM%dMD.", timer_nr); + } + break; + + case 4: + if ( timer_nr == 0 ) + { + val32 = (timers->reg[0].mode << 24 ) + | (timers->reg[1].mode << 16) + | (timers->reg[2].mode << 8) + | timers->reg[3].mode; + *(unsigned32*)dest = val32; + } + else + { + hw_abort (me, "bad read size of 4 bytes to TM%dMD.", timer_nr); + } + break; + + default: + hw_abort (me, "bad read size of %d bytes to TM%dMD.", + nr_bytes, timer_nr); + } +} + + +static void +read_base_reg (struct hw *me, + struct mn103tim *timers, + int timer_nr, + void *dest, + unsigned nr_bytes) +{ + unsigned16 val16; + unsigned32 val32; + + /* Check nr_bytes: accesses of 1, 2 and 4 bytes allowed depending on timer. */ + switch ( nr_bytes ) + { + case 1: + /* Reading 1 byte is ok for all registers. */ + if ( timer_nr < NR_8BIT_TIMERS ) + { + *(unsigned8*)dest = timers->reg[timer_nr].base; + } + break; + + case 2: + if ( timer_nr == 1 || timer_nr == 3 ) + { + hw_abort (me, "bad read size of 2 bytes to TM%dBR.", timer_nr); + } + else + { + if ( timer_nr < NR_8BIT_TIMERS ) + { + val16 = (timers->reg[timer_nr].base<<8) + | timers->reg[timer_nr+1].base; + } + else + { + val16 = timers->reg[timer_nr].base; + } + *(unsigned16*)dest = val16; + } + break; + + case 4: + if ( timer_nr == 0 ) + { + val32 = (timers->reg[0].base << 24) | (timers->reg[1].base << 16) + | (timers->reg[2].base << 8) | timers->reg[3].base; + *(unsigned32*)dest = val32; + } + else if ( timer_nr == 4 ) + { + val32 = (timers->reg[4].base << 16) | timers->reg[5].base; + *(unsigned32*)dest = val32; + } + else + { + hw_abort (me, "bad read size of 4 bytes to TM%dBR.", timer_nr); + } + break; + + default: + hw_abort (me, "bad read size must of %d bytes to TM%dBR.", + nr_bytes, timer_nr); + } +} + + +static void +read_counter (struct hw *me, + struct mn103tim *timers, + int timer_nr, + void *dest, + unsigned nr_bytes) +{ + unsigned32 val; + + if ( NULL == timers->timer[timer_nr].event ) + { + /* Timer is not counting, use value in base register. */ + if ( timer_nr == 6 ) + { + val = 0; /* timer 6 is an up counter */ + } + else + { + val = timers->reg[timer_nr].base; + } + } + else + { + if ( timer_nr == 6 ) /* timer 6 is an up counter. */ + { + val = hw_event_queue_time(me) - timers->timer[timer_nr].start; + } + else + { + /* ticks left = start time + div ratio - curr time */ + /* Cannot use base register because it can be written during counting and it + doesn't affect counter until underflow occurs. */ + + val = timers->timer[timer_nr].start + timers->timer[timer_nr].div_ratio + - hw_event_queue_time(me); + } + } + + switch (nr_bytes) { + case 1: + *(unsigned8 *)dest = val; + break; + + case 2: + *(unsigned16 *)dest = val; + break; + + case 4: + *(unsigned32 *)dest = val; + break; + + default: + hw_abort(me, "bad read size for reading counter"); + } + +} + + +static void +read_special_timer6_reg (struct hw *me, + struct mn103tim *timers, + int timer_nr, + void *dest, + unsigned nr_bytes) +{ + unsigned32 val; + + switch (nr_bytes) { + case 1: + { + switch ( timer_nr ) { + case TM6MDA: + *(unsigned8 *)dest = timers->tm6mda; + break; + + case TM6MDB: + *(unsigned8 *)dest = timers->tm6mdb; + break; + + case TM6CA: + *(unsigned8 *)dest = timers->tm6ca; + break; + + case TM6CB: + *(unsigned8 *)dest = timers->tm6cb; + break; + + default: + } + break; + } + + case 2: + if ( timer_nr == TM6CA ) + { + *(unsigned16 *)dest = timers->tm6ca; + } + else if ( timer_nr == TM6CB ) + { + *(unsigned16 *)dest = timers->tm6cb; + } + else + { + hw_abort(me, "bad read size for timer 6 mode A/B register"); + } + break; + + default: + hw_abort(me, "bad read size for timer 6 register"); + } + +} + + +static unsigned +mn103tim_io_read_buffer (struct hw *me, + void *dest, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct mn103tim *timers = hw_data (me); + enum timer_register_types timer_reg; + + HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); + + timer_reg = decode_addr (me, timers, base); + + /* It can be either a mode register, a base register, a binary counter, */ + /* or a special timer 6 register. Check in that order. */ + if ( timer_reg >= FIRST_MODE_REG && timer_reg <= LAST_MODE_REG ) + { + read_mode_reg(me, timers, timer_reg-FIRST_MODE_REG, dest, nr_bytes); + } + else if ( timer_reg <= LAST_BASE_REG ) + { + read_base_reg(me, timers, timer_reg-FIRST_BASE_REG, dest, nr_bytes); + } + else if ( timer_reg <= LAST_COUNTER ) + { + read_counter(me, timers, timer_reg-FIRST_COUNTER, dest, nr_bytes); + } + else if ( timer_reg <= LAST_TIMER_REG ) + { + read_special_timer6_reg(me, timers, timer_reg, dest, nr_bytes); + } + else + { + hw_abort(me, "invalid timer register address."); + } + + return nr_bytes; +} + + +static void +do_counter_event (struct hw *me, + void *data) +{ + struct mn103tim *timers = hw_data(me); + int timer_nr = (int) data; + int next_timer; + + /* Check if counting is still enabled. */ + if ( (timers->reg[timer_nr].mode & count_mask) != 0 ) + { + /* Generate an interrupt for the timer underflow (TIMERn_UFLOW). */ + + /* Port event occurs on port of last cascaded timer. */ + /* This works across timer range from 0 to NR_REG_TIMERS because */ + /* the first 16 bit timer (timer 4) is not allowed to be set as */ + /* a cascading timer. */ + for ( next_timer = timer_nr+1; next_timer < NR_REG_TIMERS; ++next_timer ) + { + if ( (timers->reg[next_timer].mode & clock_mask) != clk_cascaded ) + { + break; + } + } + hw_port_event (me, next_timer-1, 1); + + /* Schedule next timeout. */ + timers->timer[timer_nr].start = hw_event_queue_time(me); + /* FIX: Check if div_ratio has changed and if it's now 0. */ + timers->timer[timer_nr].event + = hw_event_queue_schedule (me, timers->timer[timer_nr].div_ratio, + do_counter_event, (void *)timer_nr); + } + else + { + timers->timer[timer_nr].event = NULL; + } + +} + + +static void +do_counter6_event (struct hw *me, + void *data) +{ + struct mn103tim *timers = hw_data(me); + int timer_nr = (int) data; + int next_timer; + + /* Check if counting is still enabled. */ + if ( (timers->reg[timer_nr].mode & count_mask) != 0 ) + { + /* Generate an interrupt for the timer underflow (TIMERn_UFLOW). */ + hw_port_event (me, timer_nr, 1); + + /* Schedule next timeout. */ + timers->timer[timer_nr].start = hw_event_queue_time(me); + /* FIX: Check if div_ratio has changed and if it's now 0. */ + timers->timer[timer_nr].event + = hw_event_queue_schedule (me, timers->timer[timer_nr].div_ratio, + do_counter6_event, (void *)timer_nr); + } + else + { + timers->timer[timer_nr].event = NULL; + } + +} + +static void +write_base_reg (struct hw *me, + struct mn103tim *timers, + int timer_nr, + const void *source, + unsigned nr_bytes) +{ + unsigned i; + const unsigned8 *buf8 = source; + const unsigned16 *buf16 = source; + + /* If TMnCNE == 0 (counting is off), writing to the base register + (TMnBR) causes a simultaneous write to the counter reg (TMnBC). + Else, the TMnBC is reloaded with the value from TMnBR when + underflow occurs. Since the counter register is not explicitly + maintained, this functionality is handled in read_counter. */ + + /* Check nr_bytes: write of 1, 2 or 4 bytes allowed depending on timer. */ + switch ( nr_bytes ) + { + case 1: + /* Storing 1 byte is ok for all registers. */ + timers->reg[timer_nr].base = buf8[0]; + break; + + case 2: + if ( timer_nr == 1 || timer_nr == 3 ) + { + hw_abort (me, "bad write size of 2 bytes to TM%dBR.", timer_nr); + } + else + { + if ( timer_nr < NR_8BIT_TIMERS ) + { + timers->reg[timer_nr].base = buf8[0]; + timers->reg[timer_nr+1].base = buf8[1]; + } + else + { + timers->reg[timer_nr].base = buf16[0]; + } + } + break; + + case 4: + if ( timer_nr == 0 ) + { + timers->reg[0].base = buf8[0]; + timers->reg[1].base = buf8[1]; + timers->reg[2].base = buf8[2]; + timers->reg[3].base = buf8[3]; + } + else if ( timer_nr == 4 ) + { + timers->reg[4].base = buf16[0]; + timers->reg[5].base = buf16[1]; + } + else + { + hw_abort (me, "bad write size of 4 bytes to TM%dBR.", timer_nr); + } + break; + + default: + hw_abort (me, "bad write size must of %d bytes to TM%dBR.", + nr_bytes, timer_nr); + } + +} + +static void +write_mode_reg (struct hw *me, + struct mn103tim *timers, + int timer_nr, + const void *source, + unsigned nr_bytes) + /* for timers 0 to 5 */ +{ + unsigned i; + unsigned8 mode_val, next_mode_val; + unsigned32 div_ratio; + + if ( nr_bytes != 1 ) + { + hw_abort (me, "bad write size of %d bytes to TM%dMD.", nr_bytes, timer_nr); + } + + mode_val = *(unsigned8 *)source; + timers->reg[timer_nr].mode = mode_val; + + if ( ( mode_val & count_and_load_mask ) == count_and_load_mask ) + { + hw_abort(me, "Cannot load base reg and start counting simultaneously."); + } + if ( ( mode_val & bits2to5_mask ) != 0 ) + { + hw_abort(me, "Cannot write to bits 2 to 5 of mode register"); + } + + if ( mode_val & count_mask ) + { + /* - de-schedule any previous event. */ + /* - add new event to queue to start counting. */ + /* - assert that counter == base reg? */ + + /* For cascaded timers, */ + if ( (mode_val & clock_mask) == clk_cascaded ) + { + if ( timer_nr == 0 || timer_nr == 4 ) + { + hw_abort(me, "Timer %d cannot be cascaded.", timer_nr); + } + } + else + { + div_ratio = timers->reg[timer_nr].base; + + /* Check for cascading. */ + if ( timer_nr < NR_8BIT_TIMERS ) + { + for ( i = timer_nr + 1; i <= 3; ++i ) + { + next_mode_val = timers->reg[i].mode; + if ( ( next_mode_val & clock_mask ) == clk_cascaded ) + { + /* Check that CNE is on. */ + if ( ( next_mode_val & count_mask ) == 0 ) + { + hw_abort (me, "cascaded timer not ready for counting"); + } + ASSERT(timers->timer[i].event == NULL); + ASSERT(timers->timer[i].div_ratio == 0); + div_ratio = div_ratio + | (timers->reg[i].base << (8*(i-timer_nr))); + } + else + { + break; + } + } + } + else + { + /* Mode register for a 16 bit timer */ + next_mode_val = timers->reg[timer_nr+1].mode; + if ( ( next_mode_val & clock_mask ) == clk_cascaded ) + { + /* Check that CNE is on. */ + if ( ( next_mode_val & count_mask ) == 0 ) + { + hw_abort (me, "cascaded timer not ready for counting"); + } + ASSERT(timers->timer[timer_nr+1].event == NULL); + ASSERT(timers->timer[timer_nr+1].div_ratio == 0); + div_ratio = div_ratio | (timers->reg[timer_nr+1].base << 16); + } + } + + timers->timer[timer_nr].div_ratio = div_ratio; + + if ( NULL != timers->timer[timer_nr].event ) + { + hw_event_queue_deschedule (me, timers->timer[timer_nr].event); + timers->timer[timer_nr].event = NULL; + } + + if ( div_ratio > 0 ) + { + /* Set start time. */ + timers->timer[timer_nr].start = hw_event_queue_time(me); + timers->timer[timer_nr].event + = hw_event_queue_schedule(me, div_ratio, + do_counter_event, + (void *)(timer_nr)); + } + } + } + else + { + /* Turn off counting */ + if ( NULL != timers->timer[timer_nr].event ) + { + ASSERT((timers->reg[timer_nr].mode & clock_mask) != clk_cascaded); + hw_event_queue_deschedule (me, timers->timer[timer_nr].event); + timers->timer[timer_nr].event = NULL; + } + else + { + if ( (timers->reg[timer_nr].mode & clock_mask) == clk_cascaded ) + { + ASSERT(timers->timer[timer_nr].event == NULL); + } + } + + } + +} + +static void +write_tm6md (struct hw *me, + struct mn103tim *timers, + unsigned_word address, + const void *source, + unsigned nr_bytes) +{ + unsigned8 mode_val0 = 0x00, mode_val1 = 0x00; + unsigned32 div_ratio; + int timer_nr = 6; + + unsigned_word offset = address - timers->block[0].base; + + if ((offset != 0x84 && nr_bytes > 1) || nr_bytes > 2 ) + { + hw_abort (me, "Bad write size of %d bytes to TM6MD", nr_bytes); + } + + if ( offset == 0x84 ) /* address of TM6MD */ + { + /* Fill in first byte of mode */ + mode_val0 = *(unsigned8 *)source; + timers->tm6md0 = mode_val0; + + if ( ( mode_val0 & 0x26 ) != 0 ) + { + hw_abort(me, "Cannot write to bits 5, 3, and 2 of TM6MD"); + } + } + + if ( offset == 0x85 || nr_bytes == 2 ) + { + /* Fill in second byte of mode */ + if ( nr_bytes == 2 ) + { + mode_val1 = *(unsigned8 *)source+1; + } + else + { + mode_val1 = *(unsigned8 *)source; + } + + timers->tm6md1 = mode_val1; + + if ( ( mode_val1 & count_and_load_mask ) == count_and_load_mask ) + { + hw_abort(me, "Cannot load base reg and start counting simultaneously."); + } + if ( ( mode_val1 & bits0to2_mask ) != 0 ) + { + hw_abort(me, "Cannot write to bits 8 to 10 of TM6MD"); + } + } + + if ( mode_val1 & count_mask ) + { + /* - de-schedule any previous event. */ + /* - add new event to queue to start counting. */ + /* - assert that counter == base reg? */ + + div_ratio = timers->tm6ca; /* binary counter for timer 6 */ + timers->timer[timer_nr].div_ratio = div_ratio; + if ( NULL != timers->timer[timer_nr].event ) + { + hw_event_queue_deschedule (me, timers->timer[timer_nr].event); + timers->timer[timer_nr].event = NULL; + } + + if ( div_ratio > 0 ) + { + /* Set start time. */ + timers->timer[timer_nr].start = hw_event_queue_time(me); + timers->timer[timer_nr].event + = hw_event_queue_schedule(me, div_ratio, + do_counter6_event, + (void *)(timer_nr)); + } + } + else + { + /* Turn off counting */ + if ( NULL != timers->timer[timer_nr].event ) + { + hw_event_queue_deschedule (me, timers->timer[timer_nr].event); + timers->timer[timer_nr].event = NULL; + } + } +} + + + +static void +write_special_timer6_reg (struct hw *me, + struct mn103tim *timers, + int timer_nr, + const void *source, + unsigned nr_bytes) +{ + unsigned32 val; + + switch (nr_bytes) { + case 1: + { + switch ( timer_nr ) { + case TM6MDA: + timers->tm6mda = *(unsigned8 *)source; + break; + + case TM6MDB: + timers->tm6mdb = *(unsigned8 *)source; + break; + + case TM6CA: + timers->tm6ca = *(unsigned8 *)source; + break; + + case TM6CB: + timers->tm6cb = *(unsigned8 *)source; + break; + + default: + } + break; + } + + case 2: + if ( timer_nr == TM6CA ) + { + timers->tm6ca = *(unsigned16 *)source; + } + else if ( timer_nr == TM6CB ) + { + timers->tm6cb = *(unsigned16 *)source; + } + else + { + hw_abort(me, "bad read size for timer 6 mode A/B register"); + } + break; + + default: + hw_abort(me, "bad read size for timer 6 register"); + } + +} + + +static unsigned +mn103tim_io_write_buffer (struct hw *me, + const void *source, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct mn103tim *timers = hw_data (me); + enum timer_register_types timer_reg; + + HW_TRACE ((me, "write to 0x%08lx length %d with 0x%x", (long) base, + (int) nr_bytes, *(unsigned32 *)source)); + + timer_reg = decode_addr (me, timers, base); + + /* It can be either a mode register, a base register, a binary counter, */ + /* or a special timer 6 register. Check in that order. */ + if ( timer_reg <= LAST_MODE_REG ) + { + if ( timer_reg == 6 ) + { + write_tm6md(me, timers, base, source, nr_bytes); + } + else + { + write_mode_reg(me, timers, timer_reg-FIRST_MODE_REG, + source, nr_bytes); + } + } + else if ( timer_reg <= LAST_BASE_REG ) + { + write_base_reg(me, timers, timer_reg-FIRST_BASE_REG, source, nr_bytes); + } + else if ( timer_reg <= LAST_COUNTER ) + { + hw_abort(me, "cannot write to counter"); + } + else if ( timer_reg <= LAST_TIMER_REG ) + { + write_special_timer6_reg(me, timers, timer_reg, source, nr_bytes); + } + else + { + hw_abort(me, "invalid reg type"); + } + + return nr_bytes; +} + + +const struct hw_descriptor dv_mn103tim_descriptor[] = { + { "mn103tim", mn103tim_finish, }, + { NULL }, +};

dv-mn103tim.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: dv-mn103ser.c =================================================================== --- dv-mn103ser.c (nonexistent) +++ dv-mn103ser.c (revision 1765) @@ -0,0 +1,712 @@ +/* This file is part of the program GDB, the GNU debugger. + + Copyright (C) 1998 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + */ + +#include "sim-main.h" +#include "hw-main.h" +#include "dv-sockser.h" + + +/* DEVICE + + + mn103ser - mn103002 serial devices 0, 1 and 2. + + + DESCRIPTION + + Implements the mn103002 serial interfaces as described in the + mn103002 user guide. + + + PROPERTIES + + reg =

+ + + BUGS + + */ + + +/* The serial devices' registers' address block */ + +struct mn103ser_block { + unsigned_word base; + unsigned_word bound; +}; + + + +enum serial_register_types { + SC0CTR, + SC1CTR, + SC2CTR, + SC0ICR, + SC1ICR, + SC2ICR, + SC0TXB, + SC1TXB, + SC2TXB, + SC0RXB, + SC1RXB, + SC2RXB, + SC0STR, + SC1STR, + SC2STR, + SC2TIM, +}; + + +/* Access dv-sockser state */ +extern char* sockser_addr; +#define USE_SOCKSER_P (sockser_addr != NULL) + + +#define NR_SERIAL_DEVS 3 +#define SIO_STAT_RRDY 0x0010 + +typedef struct _mn10300_serial { + unsigned16 status, control; + unsigned8 txb, rxb, intmode; + struct hw_event *event; +} mn10300_serial; + + + +struct mn103ser { + struct mn103ser_block block; + mn10300_serial device[NR_SERIAL_DEVS]; + unsigned8 serial2_timer_reg; + do_hw_poll_read_method *reader; +}; + +/* output port ID's */ + +/* for mn103002 */ +enum { + SERIAL0_RECEIVE, + SERIAL1_RECEIVE, + SERIAL2_RECEIVE, + SERIAL0_SEND, + SERIAL1_SEND, + SERIAL2_SEND, +}; + + +static const struct hw_port_descriptor mn103ser_ports[] = { + + { "serial-0-receive", SERIAL0_RECEIVE, 0, output_port, }, + { "serial-1-receive", SERIAL1_RECEIVE, 0, output_port, }, + { "serial-2-receive", SERIAL2_RECEIVE, 0, output_port, }, + { "serial-0-transmit", SERIAL0_SEND, 0, output_port, }, + { "serial-1-transmit", SERIAL1_SEND, 0, output_port, }, + { "serial-2-transmit", SERIAL2_SEND, 0, output_port, }, + + { NULL, }, +}; + + + +/* Finish off the partially created hw device. Attach our local + callbacks. Wire up our port names etc */ + +static hw_io_read_buffer_method mn103ser_io_read_buffer; +static hw_io_write_buffer_method mn103ser_io_write_buffer; + +static void +attach_mn103ser_regs (struct hw *me, + struct mn103ser *serial) +{ + unsigned_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, + &attach_address, + me); + serial->block.base = attach_address; + hw_unit_size_to_attach_size (hw_parent (me), + ®.size, + &attach_size, me); + serial->block.bound = attach_address + (attach_size - 1); + hw_attach_address (hw_parent (me), + 0, + attach_space, attach_address, attach_size, + me); +} + +static void +mn103ser_finish (struct hw *me) +{ + struct mn103ser *serial; + int i; + + serial = HW_ZALLOC (me, struct mn103ser); + set_hw_data (me, serial); + set_hw_io_read_buffer (me, mn103ser_io_read_buffer); + set_hw_io_write_buffer (me, mn103ser_io_write_buffer); + set_hw_ports (me, mn103ser_ports); + + /* Attach ourself to our parent bus */ + attach_mn103ser_regs (me, serial); + + /* If so configured, enable polled input */ + if (hw_find_property (me, "poll?") != NULL + && hw_find_boolean_property (me, "poll?")) + { + serial->reader = sim_io_poll_read; + } + else + { + serial->reader = sim_io_read; + } + + /* Initialize the serial device registers. */ + for ( i=0; idevice[i].txb = 0; + serial->device[i].rxb = 0; + serial->device[i].status = 0; + serial->device[i].control = 0; + serial->device[i].intmode = 0; + serial->device[i].event = NULL; + } +} + + +/* read and write */ + +static int +decode_addr (struct hw *me, + struct mn103ser *serial, + unsigned_word address) +{ + unsigned_word offset; + offset = address - serial->block.base; + switch (offset) + { + case 0x00: return SC0CTR; + case 0x04: return SC0ICR; + case 0x08: return SC0TXB; + case 0x09: return SC0RXB; + case 0x0C: return SC0STR; + case 0x10: return SC1CTR; + case 0x14: return SC1ICR; + case 0x18: return SC1TXB; + case 0x19: return SC1RXB; + case 0x1C: return SC1STR; + case 0x20: return SC2CTR; + case 0x24: return SC2ICR; + case 0x28: return SC2TXB; + case 0x29: return SC2RXB; + case 0x2C: return SC2STR; + case 0x2D: return SC2TIM; + default: + { + hw_abort (me, "bad address"); + return -1; + } + } +} + +static void +do_polling_event (struct hw *me, + void *data) +{ + struct mn103ser *serial = hw_data(me); + int serial_reg = (int) data; + char c; + int count; + + if(USE_SOCKSER_P) + { + int rd; + rd = dv_sockser_read (hw_system (me)); + if(rd != -1) + { + c = (char) rd; + count = 1; + } + else + { + count = HW_IO_NOT_READY; + } + } + else + { + count = do_hw_poll_read (me, serial->reader, + 0/*STDIN*/, &c, sizeof(c)); + } + + + switch (count) + { + case HW_IO_NOT_READY: + case HW_IO_EOF: + serial->device[serial_reg].rxb = 0; + serial->device[serial_reg].status &= ~SIO_STAT_RRDY; + break; + default: + serial->device[serial_reg].rxb = c; + serial->device[serial_reg].status |= SIO_STAT_RRDY; + hw_port_event (me, serial_reg+SERIAL0_RECEIVE, 1); + } + + /* Schedule next polling event */ + serial->device[serial_reg].event + = hw_event_queue_schedule (me, 1000, + do_polling_event, (void *)serial_reg); + +} + +static void +read_control_reg (struct hw *me, + struct mn103ser *serial, + unsigned_word serial_reg, + void *dest, + unsigned nr_bytes) +{ + /* really allow 1 byte read, too */ + if ( nr_bytes == 2 ) + { + *(unsigned16 *)dest = H2LE_2 (serial->device[serial_reg].control); + } + else + { + hw_abort (me, "bad read size of %d bytes from SC%dCTR.", nr_bytes, + serial_reg); + } +} + + +static void +read_intmode_reg (struct hw *me, + struct mn103ser *serial, + unsigned_word serial_reg, + void *dest, + unsigned nr_bytes) +{ + if ( nr_bytes == 1 ) + { + *(unsigned8 *)dest = serial->device[serial_reg].intmode; + } + else + { + hw_abort (me, "bad read size of %d bytes from SC%dICR.", nr_bytes, + serial_reg); + } +} + + +static void +read_txb (struct hw *me, + struct mn103ser *serial, + unsigned_word serial_reg, + void *dest, + unsigned nr_bytes) +{ + if ( nr_bytes == 1 ) + { + *(unsigned8 *)dest = serial->device[serial_reg].txb; + } + else + { + hw_abort (me, "bad read size of %d bytes from SC%dTXB.", nr_bytes, + serial_reg); + } +} + + +static void +read_rxb (struct hw *me, + struct mn103ser *serial, + unsigned_word serial_reg, + void *dest, + unsigned nr_bytes) +{ + if ( nr_bytes == 1 ) + { + *(unsigned8 *)dest = serial->device[serial_reg].rxb; + /* Reception buffer is now empty. */ + serial->device[serial_reg].status &= ~SIO_STAT_RRDY; + } + else + { + hw_abort (me, "bad read size of %d bytes from SC%dRXB.", nr_bytes, + serial_reg); + } +} + + +static void +read_status_reg (struct hw *me, + struct mn103ser *serial, + unsigned_word serial_reg, + void *dest, + unsigned nr_bytes) +{ + char c; + int count; + + if ( (serial->device[serial_reg].status & SIO_STAT_RRDY) == 0 ) + { + /* FIFO is empty */ + /* Kill current poll event */ + if ( NULL != serial->device[serial_reg].event ) + { + hw_event_queue_deschedule (me, serial->device[serial_reg].event); + serial->device[serial_reg].event = NULL; + } + + if(USE_SOCKSER_P) + { + int rd; + rd = dv_sockser_read (hw_system (me)); + if(rd != -1) + { + c = (char) rd; + count = 1; + } + else + { + count = HW_IO_NOT_READY; + } + } + else + { + count = do_hw_poll_read (me, serial->reader, + 0/*STDIN*/, &c, sizeof(c)); + } + + switch (count) + { + case HW_IO_NOT_READY: + case HW_IO_EOF: + serial->device[serial_reg].rxb = 0; + serial->device[serial_reg].status &= ~SIO_STAT_RRDY; + break; + default: + serial->device[serial_reg].rxb = c; + serial->device[serial_reg].status |= SIO_STAT_RRDY; + hw_port_event (me, serial_reg+SERIAL0_RECEIVE, 1); + } + + /* schedule polling event */ + serial->device[serial_reg].event + = hw_event_queue_schedule (me, 1000, + do_polling_event, + (void *)serial_reg); + } + + if ( nr_bytes == 1 ) + { + *(unsigned8 *)dest = (unsigned8)serial->device[serial_reg].status; + } + else if ( nr_bytes == 2 && serial_reg != SC2STR ) + { + *(unsigned16 *)dest = H2LE_2 (serial->device[serial_reg].status); + } + else + { + hw_abort (me, "bad read size of %d bytes from SC%dSTR.", nr_bytes, + serial_reg); + } +} + + +static void +read_serial2_timer_reg (struct hw *me, + struct mn103ser *serial, + void *dest, + unsigned nr_bytes) +{ + if ( nr_bytes == 1 ) + { + * (unsigned8 *) dest = (unsigned8) serial->serial2_timer_reg; + } + else + { + hw_abort (me, "bad read size of %d bytes to SC2TIM.", nr_bytes); + } +} + + +static unsigned +mn103ser_io_read_buffer (struct hw *me, + void *dest, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct mn103ser *serial = hw_data (me); + enum serial_register_types serial_reg; + HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); + + serial_reg = decode_addr (me, serial, base); + switch (serial_reg) + { + /* control registers */ + case SC0CTR: + case SC1CTR: + case SC2CTR: + read_control_reg(me, serial, serial_reg-SC0CTR, dest, nr_bytes); + HW_TRACE ((me, "read - ctrl reg%d has 0x%x\n", serial_reg-SC0CTR, + *(unsigned8 *)dest)); + break; + + /* interrupt mode registers */ + case SC0ICR: + case SC1ICR: + case SC2ICR: + read_intmode_reg(me, serial, serial_reg-SC0ICR, dest, nr_bytes); + HW_TRACE ((me, "read - intmode reg%d has 0x%x\n", serial_reg-SC0ICR, + *(unsigned8 *)dest)); + break; + + /* transmission buffers */ + case SC0TXB: + case SC1TXB: + case SC2TXB: + read_txb(me, serial, serial_reg-SC0TXB, dest, nr_bytes); + HW_TRACE ((me, "read - txb%d has %c\n", serial_reg-SC0TXB, + *(char *)dest)); + break; + + /* reception buffers */ + case SC0RXB: + case SC1RXB: + case SC2RXB: + read_rxb(me, serial, serial_reg-SC0RXB, dest, nr_bytes); + HW_TRACE ((me, "read - rxb%d has %c\n", serial_reg-SC0RXB, + *(char *)dest)); + break; + + /* status registers */ + case SC0STR: + case SC1STR: + case SC2STR: + read_status_reg(me, serial, serial_reg-SC0STR, dest, nr_bytes); + HW_TRACE ((me, "read - status reg%d has 0x%x\n", serial_reg-SC0STR, + *(unsigned8 *)dest)); + break; + + case SC2TIM: + read_serial2_timer_reg(me, serial, dest, nr_bytes); + HW_TRACE ((me, "read - serial2 timer reg %d\n", *(unsigned8 *)dest)); + break; + + default: + hw_abort(me, "invalid address"); + } + + return nr_bytes; +} + + +static void +write_control_reg (struct hw *me, + struct mn103ser *serial, + unsigned_word serial_reg, + const void *source, + unsigned nr_bytes) +{ + unsigned16 val = LE2H_2 (*(unsigned16 *)source); + + /* really allow 1 byte write, too */ + if ( nr_bytes == 2 ) + { + if ( serial_reg == 2 && (val & 0x0C04) != 0 ) + { + hw_abort(me, "Cannot write to read-only bits of SC2CTR."); + } + else + { + serial->device[serial_reg].control = val; + } + } + else + { + hw_abort (me, "bad read size of %d bytes from SC%dSTR.", nr_bytes, + serial_reg); + } +} + + +static void +write_intmode_reg (struct hw *me, + struct mn103ser *serial, + unsigned_word serial_reg, + const void *source, + unsigned nr_bytes) +{ +unsigned8 val = *(unsigned8 *)source; + + if ( nr_bytes == 1 ) + { + /* Check for attempt to write to read-only bits of register. */ + if ( ( serial_reg == 2 && (val & 0xCA) != 0 ) + || ( serial_reg != 2 && (val & 0x4A) != 0 ) ) + { + hw_abort(me, "Cannot write to read-only bits of SC%dICR.", + serial_reg); + } + else + { + serial->device[serial_reg].intmode = val; + } + } + else + { + hw_abort (me, "bad write size of %d bytes to SC%dICR.", nr_bytes, + serial_reg); + } +} + + +static void +write_txb (struct hw *me, + struct mn103ser *serial, + unsigned_word serial_reg, + const void *source, + unsigned nr_bytes) +{ + if ( nr_bytes == 1 ) + { + serial->device[serial_reg].txb = *(unsigned8 *)source; + + if(USE_SOCKSER_P) + { + dv_sockser_write(hw_system (me), * (char*) source); + } + else + { + sim_io_write_stdout(hw_system (me), (char *)source, 1); + sim_io_flush_stdout(hw_system (me)); + } + + hw_port_event (me, serial_reg+SERIAL0_SEND, 1); + } + else + { + hw_abort (me, "bad write size of %d bytes to SC%dTXB.", nr_bytes, + serial_reg); + } +} + + +static void +write_serial2_timer_reg (struct hw *me, + struct mn103ser *serial, + const void *source, + unsigned nr_bytes) +{ + if ( nr_bytes == 1 ) + { + serial->serial2_timer_reg = *(unsigned8 *)source; + } + else + { + hw_abort (me, "bad write size of %d bytes to SC2TIM.", nr_bytes); + } +} + + +static unsigned +mn103ser_io_write_buffer (struct hw *me, + const void *source, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct mn103ser *serial = hw_data (me); + enum serial_register_types serial_reg; + HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); + + serial_reg = decode_addr (me, serial, base); + switch (serial_reg) + { + /* control registers */ + case SC0CTR: + case SC1CTR: + case SC2CTR: + HW_TRACE ((me, "write - ctrl reg%d has 0x%x, nrbytes=%d.\n", + serial_reg-SC0CTR, *(unsigned8 *)source, nr_bytes)); + write_control_reg(me, serial, serial_reg-SC0CTR, source, nr_bytes); + break; + + /* interrupt mode registers */ + case SC0ICR: + case SC1ICR: + case SC2ICR: + HW_TRACE ((me, "write - intmode reg%d has 0x%x, nrbytes=%d.\n", + serial_reg-SC0ICR, *(unsigned8 *)source, nr_bytes)); + write_intmode_reg(me, serial, serial_reg-SC0ICR, source, nr_bytes); + break; + + /* transmission buffers */ + case SC0TXB: + case SC1TXB: + case SC2TXB: + HW_TRACE ((me, "write - txb%d has %c, nrbytes=%d.\n", + serial_reg-SC0TXB, *(char *)source, nr_bytes)); + write_txb(me, serial, serial_reg-SC0TXB, source, nr_bytes); + break; + + /* reception buffers */ + case SC0RXB: + case SC1RXB: + case SC2RXB: + hw_abort(me, "Cannot write to reception buffer."); + break; + + /* status registers */ + case SC0STR: + case SC1STR: + case SC2STR: + hw_abort(me, "Cannot write to status register."); + break; + + case SC2TIM: + HW_TRACE ((me, "read - serial2 timer reg %d (nrbytes=%d)\n", + *(unsigned8 *)source, nr_bytes)); + write_serial2_timer_reg(me, serial, source, nr_bytes); + break; + + default: + hw_abort(me, "invalid address"); + } + + return nr_bytes; +} + + +const struct hw_descriptor dv_mn103ser_descriptor[] = { + { "mn103ser", mn103ser_finish, }, + { NULL }, +};

dv-mn103ser.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sim-main.h =================================================================== --- sim-main.h (nonexistent) +++ sim-main.h (revision 1765) @@ -0,0 +1,107 @@ +/* This file is part of the program psim. + + Copyright (C) 1994-1997, Andrew Cagney + Copyright (C) 1997, Free Software Foundation + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + */ + + +#ifndef SIM_MAIN_H +#define SIM_MAIN_H + +#define WITH_CORE +#define WITH_WATCHPOINTS 1 +#define SIM_HANDLES_LMA 1 + +#define SIM_ENGINE_HALT_HOOK(SD,LAST_CPU,CIA) 0 /* disable this hook */ + +#include "sim-basics.h" +#include "sim-signal.h" + +#include /* For kill() in insns:do_trap */ + +#include +#ifdef HAVE_UNISTD_H +#include +#endif + +/* These are generated files. */ +#include "itable.h" +#include "idecode.h" +#include "idecode.h" + +typedef instruction_address sim_cia; +static const sim_cia null_cia = {0}; /* Dummy */ +#define NULL_CIA null_cia +/* FIXME: Perhaps igen should generate access macros for + `instruction_address' that we could use. */ +/*#define CIA_ADDR(cia) ((cia).ip) doesn't work for mn10300*/ + +#define WITH_WATCHPOINTS 1 + +#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ +mn10300_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR)) + + +#include "sim-base.h" + +#include "mn10300_sim.h" + +/* Bring data in from the cold */ + +#define IMEM8(EA) \ +(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA))) + +#define IMEM8_IMMED(EA, N) \ +(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA) + (N))) + + +/* FIXME: For moment, save/restore PC value found in struct State. + Struct State will one day go away, being placed in the sim_cpu + state. */ +#define CIA_GET(CPU) ((PC) + 0) +#define CIA_SET(CPU,VAL) ((CPU)->cia = (VAL), PC = (VAL)) + + +struct _sim_cpu { + sim_event *pending_nmi; + sim_cia cia; + sim_cpu_base base; +}; + + +struct sim_state { + + /* the processors proper */ + sim_cpu cpu; +#define STATE_CPU(sd, n) (&(sd)->cpu) + + /* The base class. */ + sim_state_base base; + +}; + +/* For compatibility, until all functions converted to passing + SIM_DESC as an argument */ +extern SIM_DESC simulator; + +/* (re) initialize the simulator */ + +extern void engine_init(SIM_DESC sd); +extern SIM_CORE_SIGNAL_FN mn10300_core_signal; + +#endif

sim-main.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: dv-mn103int.c =================================================================== --- dv-mn103int.c (nonexistent) +++ dv-mn103int.c (revision 1765) @@ -0,0 +1,831 @@ +/* This file is part of the program GDB, the GNU debugger. + + Copyright (C) 1998 Free Software Foundation, Inc. + Contributed by Cygnus Solutions. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + */ + + +#include "sim-main.h" +#include "hw-main.h" +#include "sim-hw.h" + +/* DEVICE + + + mn103int - mn103002 interrupt controller + + + DESCRIPTION + + + Implements the mn103002 interrupt controller described in the + mn103002 user guide. + + + PROPERTIES + + + reg =

+ + Specify the address of the ICR (total of 30 registers), IAGR and + EXTMD registers (within the parent bus). + + The reg property value `0x34000100 0x7C 0x34000200 0x8 0x3400280 + 0x8' locates the interrupt controller at the addresses specified in + the mn103002 interrupt controller user guide. + + + PORTS + + + nmi (output) + + Non-maskable interrupt output port. An event on this output ports + indicates a NMI request from the interrupt controller. The value + attached to the event should be ignored. + + + level (output) + + Maskable interrupt level output port. An event on this output port + indicates a maskable interrupt request at the specified level. The + event value defines the level being requested. + + The interrupt controller will generate an event on this port + whenever there is a change to the internal state of the interrupt + controller. + + + ack (input) + + Signal from processor indicating that a maskable interrupt has been + accepted and the interrupt controller should latch the IAGR with + value of the current highest priority interrupting group. + + The event value is the interrupt level being accepted by the + processor. It should be consistent with the most recent LEVEL sent + to the processor from the interrupt controller. + + + int[0..100] (input) + + Level or edge triggered interrupt input port. Each of the 30 + groups (0..30) can have up to 4 (0..3) interrupt inputs. The + interpretation of a port event/value is determined by the + configuration of the corresponding interrupt group. + + For convenience, numerous aliases to these interrupt inputs are + provided. + + + BUGS + + + For edge triggered interrupts, the interrupt controller does not + differentiate between POSITIVE (rising) and NEGATIVE (falling) + edges. Instead any input port event is considered to be an + interrupt trigger. + + For level sensitive interrupts, the interrupt controller ignores + active HIGH/LOW settings and instead always interprets a nonzero + port value as an interrupt assertion and a zero port value as a + negation. + + */ + + +/* The interrupt groups - numbered according to mn103002 convention */ + +enum mn103int_trigger { + ACTIVE_LOW, + ACTIVE_HIGH, + POSITIVE_EDGE, + NEGATIVE_EDGE, +}; + +enum mn103int_type { + NMI_GROUP, + LEVEL_GROUP, +}; + +struct mn103int_group { + int gid; + int level; + unsigned enable; + unsigned request; + unsigned input; + enum mn103int_trigger trigger; + enum mn103int_type type; +}; + +enum { + FIRST_NMI_GROUP = 0, + LAST_NMI_GROUP = 1, + FIRST_LEVEL_GROUP = 2, + LAST_LEVEL_GROUP = 30, + NR_GROUPS, +}; + +enum { + LOWEST_LEVEL = 7, +}; + +/* The interrupt controller register address blocks */ + +struct mn103int_block { + unsigned_word base; + unsigned_word bound; +}; + +enum { ICR_BLOCK, IAGR_BLOCK, EXTMD_BLOCK, NR_BLOCKS }; + + +struct mn103int { + struct mn103int_block block[NR_BLOCKS]; + struct mn103int_group group[NR_GROUPS]; + unsigned interrupt_accepted_group; +}; + + + +/* output port ID's */ + +enum { + NMI_PORT, + LEVEL_PORT, +}; + + +/* input port ID's */ + +enum { + G0_PORT = 0, + G1_PORT = 4, + G2_PORT = 8, + G3_PORT = 12, + G4_PORT = 16, + G5_PORT = 20, + G6_PORT = 24, + G7_PORT = 28, + G8_PORT = 32, + G9_PORT = 36, + G10_PORT = 40, + G11_PORT = 44, + G12_PORT = 48, + G13_PORT = 52, + G14_PORT = 56, + G15_PORT = 60, + G16_PORT = 64, + G17_PORT = 68, + G18_PORT = 72, + G19_PORT = 76, + G20_PORT = 80, + G21_PORT = 84, + G22_PORT = 88, + G23_PORT = 92, + IRQ0_PORT = G23_PORT, + G24_PORT = 96, + G25_PORT = 100, + G26_PORT = 104, + G27_PORT = 108, + IRQ4_PORT = G27_PORT, + G28_PORT = 112, + G29_PORT = 116, + G30_PORT = 120, + NR_G_PORTS = 124, + ACK_PORT, +}; + +static const struct hw_port_descriptor mn103int_ports[] = { + + /* interrupt outputs */ + + { "nmi", NMI_PORT, 0, output_port, }, + { "level", LEVEL_PORT, 0, output_port, }, + + /* interrupt ack (latch) input from cpu */ + + { "ack", ACK_PORT, 0, input_port, }, + + /* interrupt inputs (as names) */ + + { "nmirq", G0_PORT + 0, 0, input_port, }, + { "watchdog", G0_PORT + 1, 0, input_port, }, + { "syserr", G0_PORT + 2, 0, input_port, }, + + { "timer-0-underflow", G2_PORT, 0, input_port, }, + { "timer-1-underflow", G3_PORT, 0, input_port, }, + { "timer-2-underflow", G4_PORT, 0, input_port, }, + { "timer-3-underflow", G5_PORT, 0, input_port, }, + { "timer-4-underflow", G6_PORT, 0, input_port, }, + { "timer-5-underflow", G7_PORT, 0, input_port, }, + { "timer-6-underflow", G8_PORT, 0, input_port, }, + + { "timer-6-compare-a", G9_PORT, 0, input_port, }, + { "timer-6-compare-b", G10_PORT, 0, input_port, }, + + { "dma-0-end", G12_PORT, 0, input_port, }, + { "dma-1-end", G13_PORT, 0, input_port, }, + { "dma-2-end", G14_PORT, 0, input_port, }, + { "dma-3-end", G15_PORT, 0, input_port, }, + + { "serial-0-receive", G16_PORT, 0, input_port, }, + { "serial-0-transmit", G17_PORT, 0, input_port, }, + + { "serial-1-receive", G18_PORT, 0, input_port, }, + { "serial-1-transmit", G19_PORT, 0, input_port, }, + + { "serial-2-receive", G20_PORT, 0, input_port, }, + { "serial-2-transmit", G21_PORT, 0, input_port, }, + + { "irq-0", G23_PORT, 0, input_port, }, + { "irq-1", G24_PORT, 0, input_port, }, + { "irq-2", G25_PORT, 0, input_port, }, + { "irq-3", G26_PORT, 0, input_port, }, + { "irq-4", G27_PORT, 0, input_port, }, + { "irq-5", G28_PORT, 0, input_port, }, + { "irq-6", G29_PORT, 0, input_port, }, + { "irq-7", G30_PORT, 0, input_port, }, + + /* interrupt inputs (as generic numbers) */ + + { "int", 0, NR_G_PORTS, input_port, }, + + { NULL, }, +}; + + +/* Macros for extracting/restoring the various register bits */ + +#define EXTRACT_ID(X) (LSEXTRACTED8 ((X), 3, 0)) +#define INSERT_ID(X) (LSINSERTED8 ((X), 3, 0)) + +#define EXTRACT_IR(X) (LSEXTRACTED8 ((X), 7, 4)) +#define INSERT_IR(X) (LSINSERTED8 ((X), 7, 4)) + +#define EXTRACT_IE(X) (LSEXTRACTED8 ((X), 3, 0)) +#define INSERT_IE(X) (LSINSERTED8 ((X), 3, 0)) + +#define EXTRACT_LV(X) (LSEXTRACTED8 ((X), 6, 4)) +#define INSERT_LV(X) (LSINSERTED8 ((X), 6, 4)) + + + +/* Finish off the partially created hw device. Attach our local + callbacks. Wire up our port names etc */ + +static hw_io_read_buffer_method mn103int_io_read_buffer; +static hw_io_write_buffer_method mn103int_io_write_buffer; +static hw_port_event_method mn103int_port_event; +static hw_ioctl_method mn103int_ioctl; + + + +static void +attach_mn103int_regs (struct hw *me, + struct mn103int *controller) +{ + int i; + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + for (i = 0; i < NR_BLOCKS; i++) + { + unsigned_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + if (!hw_find_reg_array_property (me, "reg", i, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, + &attach_address, + me); + controller->block[i].base = attach_address; + hw_unit_size_to_attach_size (hw_parent (me), + ®.size, + &attach_size, me); + controller->block[i].bound = attach_address + (attach_size - 1); + hw_attach_address (hw_parent (me), + 0, + attach_space, attach_address, attach_size, + me); + } +} + +static void +mn103int_finish (struct hw *me) +{ + int gid; + struct mn103int *controller; + + controller = HW_ZALLOC (me, struct mn103int); + set_hw_data (me, controller); + set_hw_io_read_buffer (me, mn103int_io_read_buffer); + set_hw_io_write_buffer (me, mn103int_io_write_buffer); + set_hw_ports (me, mn103int_ports); + set_hw_port_event (me, mn103int_port_event); + me->to_ioctl = mn103int_ioctl; + + /* Attach ourself to our parent bus */ + attach_mn103int_regs (me, controller); + + /* Initialize all the groups according to their default configuration */ + for (gid = 0; gid < NR_GROUPS; gid++) + { + struct mn103int_group *group = &controller->group[gid]; + group->trigger = NEGATIVE_EDGE; + group->gid = gid; + if (FIRST_NMI_GROUP <= gid && gid <= LAST_NMI_GROUP) + { + group->enable = 0xf; + group->type = NMI_GROUP; + } + else if (FIRST_LEVEL_GROUP <= gid && gid <= LAST_LEVEL_GROUP) + { + group->enable = 0x0; + group->type = LEVEL_GROUP; + } + else + hw_abort (me, "internal error - unknown group id"); + } +} + + + +/* Perform the nasty work of figuring out which of the interrupt + groups should have its interrupt delivered. */ + +static int +find_highest_interrupt_group (struct hw *me, + struct mn103int *controller) +{ + int gid; + int selected; + + /* FIRST_NMI_GROUP (group zero) is used as a special default value + when searching for an interrupt group.*/ + selected = FIRST_NMI_GROUP; + controller->group[FIRST_NMI_GROUP].level = 7; + + for (gid = FIRST_LEVEL_GROUP; gid <= LAST_LEVEL_GROUP; gid++) + { + struct mn103int_group *group = &controller->group[gid]; + if ((group->request & group->enable) != 0) + { + /* Remember, lower level, higher priority. */ + if (group->level < controller->group[selected].level) + { + selected = gid; + } + } + } + return selected; +} + + +/* Notify the processor of an interrupt level update */ + +static void +push_interrupt_level (struct hw *me, + struct mn103int *controller) +{ + int selected = find_highest_interrupt_group (me, controller); + int level = controller->group[selected].level; + HW_TRACE ((me, "port-out - selected=%d level=%d", selected, level)); + hw_port_event (me, LEVEL_PORT, level); +} + + +/* An event arrives on an interrupt port */ + +static void +mn103int_port_event (struct hw *me, + int my_port, + struct hw *source, + int source_port, + int level) +{ + struct mn103int *controller = hw_data (me); + + switch (my_port) + { + + case ACK_PORT: + { + int selected = find_highest_interrupt_group (me, controller); + if (controller->group[selected].level != level) + hw_abort (me, "botched level synchronisation"); + controller->interrupt_accepted_group = selected; + HW_TRACE ((me, "port-event port=ack level=%d - selected=%d", + level, selected)); + break; + } + + default: + { + int gid; + int iid; + struct mn103int_group *group; + unsigned interrupt; + if (my_port > NR_G_PORTS) + hw_abort (me, "Event on unknown port %d", my_port); + + /* map the port onto an interrupt group */ + gid = (my_port % NR_G_PORTS) / 4; + group = &controller->group[gid]; + iid = (my_port % 4); + interrupt = 1 << iid; + + /* update our cached input */ + if (level) + group->input |= interrupt; + else + group->input &= ~interrupt; + + /* update the request bits */ + switch (group->trigger) + { + case ACTIVE_LOW: + case ACTIVE_HIGH: + if (level) + group->request |= interrupt; + break; + case NEGATIVE_EDGE: + case POSITIVE_EDGE: + group->request |= interrupt; + } + + /* force a corresponding output */ + switch (group->type) + { + + case NMI_GROUP: + { + /* for NMI's the event is the trigger */ + HW_TRACE ((me, "port-in port=%d group=%d interrupt=%d - NMI", + my_port, gid, iid)); + if ((group->request & group->enable) != 0) + { + HW_TRACE ((me, "port-out NMI")); + hw_port_event (me, NMI_PORT, 1); + } + break; + } + + case LEVEL_GROUP: + { + /* if an interrupt is now pending */ + HW_TRACE ((me, "port-in port=%d group=%d interrupt=%d - INT", + my_port, gid, iid)); + push_interrupt_level (me, controller); + break; + } + } + break; + } + + } +} + +/* Read/write to to an ICR (group control register) */ + +static struct mn103int_group * +decode_group (struct hw *me, + struct mn103int *controller, + unsigned_word base, + unsigned_word *offset) +{ + int gid = (base / 4) % NR_GROUPS; + *offset = (base % 4); + return &controller->group[gid]; +} + +static unsigned8 +read_icr (struct hw *me, + struct mn103int *controller, + unsigned_word base) +{ + unsigned_word offset; + struct mn103int_group *group = decode_group (me, controller, base, &offset); + unsigned8 val = 0; + switch (group->type) + { + + case NMI_GROUP: + switch (offset) + { + case 0: + val = INSERT_ID (group->request); + HW_TRACE ((me, "read-icr group=%d:0 nmi 0x%02x", + group->gid, val)); + break; + default: + break; + } + break; + + case LEVEL_GROUP: + switch (offset) + { + case 0: + val = (INSERT_IR (group->request) + | INSERT_ID (group->request & group->enable)); + HW_TRACE ((me, "read-icr group=%d:0 level 0x%02x", + group->gid, val)); + break; + case 1: + val = (INSERT_LV (group->level) + | INSERT_IE (group->enable)); + HW_TRACE ((me, "read-icr level-%d:1 level 0x%02x", + group->gid, val)); + break; + } + break; + + default: + break; + + } + + return val; +} + +static void +write_icr (struct hw *me, + struct mn103int *controller, + unsigned_word base, + unsigned8 val) +{ + unsigned_word offset; + struct mn103int_group *group = decode_group (me, controller, base, &offset); + switch (group->type) + { + + case NMI_GROUP: + switch (offset) + { + case 0: + HW_TRACE ((me, "write-icr group=%d:0 nmi 0x%02x", + group->gid, val)); + group->request &= ~EXTRACT_ID (val); + break; + /* Special backdoor access to SYSEF flag from CPU. See + interp.c:program_interrupt(). */ + case 3: + HW_TRACE ((me, "write-icr-special group=%d:0 nmi 0x%02x", + group->gid, val)); + group->request |= EXTRACT_ID (val); + default: + break; + } + break; + + case LEVEL_GROUP: + switch (offset) + { + case 0: /* request/detect */ + /* Clear any ID bits and then set them according to IR */ + HW_TRACE ((me, "write-icr group=%d:0 level 0x%02x %x:%x:%x", + group->gid, val, + group->request, EXTRACT_IR (val), EXTRACT_ID (val))); + group->request = + ((EXTRACT_IR (val) & EXTRACT_ID (val)) + | (EXTRACT_IR (val) & group->request) + | (~EXTRACT_IR (val) & ~EXTRACT_ID (val) & group->request)); + break; + case 1: /* level/enable */ + HW_TRACE ((me, "write-icr group=%d:1 level 0x%02x", + group->gid, val)); + group->level = EXTRACT_LV (val); + group->enable = EXTRACT_IE (val); + break; + default: + /* ignore */ + break; + } + push_interrupt_level (me, controller); + break; + + default: + break; + + } +} + + +/* Read the IAGR (Interrupt accepted group register) */ + +static unsigned8 +read_iagr (struct hw *me, + struct mn103int *controller, + unsigned_word offset) +{ + unsigned8 val; + switch (offset) + { + case 0: + { + if (!(controller->group[controller->interrupt_accepted_group].request + & controller->group[controller->interrupt_accepted_group].enable)) + { + /* oops, lost the request */ + val = 0; + HW_TRACE ((me, "read-iagr:0 lost-0")); + } + else + { + val = (controller->interrupt_accepted_group << 2); + HW_TRACE ((me, "read-iagr:0 %d", (int) val)); + } + break; + } + case 1: + val = 0; + HW_TRACE ((me, "read-iagr:1 %d", (int) val)); + break; + default: + val = 0; + HW_TRACE ((me, "read-iagr 0x%08lx bad offset", (long) offset)); + break; + } + return val; +} + + +/* Reads/writes to the EXTMD (external interrupt trigger configuration + register) */ + +static struct mn103int_group * +external_group (struct mn103int *controller, + unsigned_word offset) +{ + switch (offset) + { + case 0: + return &controller->group[IRQ0_PORT/4]; + case 1: + return &controller->group[IRQ4_PORT/4]; + default: + return NULL; + } +} + +static unsigned8 +read_extmd (struct hw *me, + struct mn103int *controller, + unsigned_word offset) +{ + int gid; + unsigned8 val = 0; + struct mn103int_group *group = external_group (controller, offset); + if (group != NULL) + { + for (gid = 0; gid < 4; gid++) + { + val |= (group[gid].trigger << (gid * 2)); + } + } + HW_TRACE ((me, "read-extmd 0x%02lx", (long) val)); + return val; +} + +static void +write_extmd (struct hw *me, + struct mn103int *controller, + unsigned_word offset, + unsigned8 val) +{ + int gid; + struct mn103int_group *group = external_group (controller, offset); + if (group != NULL) + { + for (gid = 0; gid < 4; gid++) + { + group[gid].trigger = (val >> (gid * 2)) & 0x3; + /* MAYBE: interrupts already pending? */ + } + } + HW_TRACE ((me, "write-extmd 0x%02lx", (long) val)); +} + + +/* generic read/write */ + +static int +decode_addr (struct hw *me, + struct mn103int *controller, + unsigned_word address, + unsigned_word *offset) +{ + int i; + for (i = 0; i < NR_BLOCKS; i++) + { + if (address >= controller->block[i].base + && address <= controller->block[i].bound) + { + *offset = address - controller->block[i].base; + return i; + } + } + hw_abort (me, "bad address"); + return -1; +} + +static unsigned +mn103int_io_read_buffer (struct hw *me, + void *dest, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct mn103int *controller = hw_data (me); + unsigned8 *buf = dest; + unsigned byte; + /* HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); */ + for (byte = 0; byte < nr_bytes; byte++) + { + unsigned_word address = base + byte; + unsigned_word offset; + switch (decode_addr (me, controller, address, &offset)) + { + case ICR_BLOCK: + buf[byte] = read_icr (me, controller, offset); + break; + case IAGR_BLOCK: + buf[byte] = read_iagr (me, controller, offset); + break; + case EXTMD_BLOCK: + buf[byte] = read_extmd (me, controller, offset); + break; + default: + hw_abort (me, "bad switch"); + } + } + return nr_bytes; +} + +static unsigned +mn103int_io_write_buffer (struct hw *me, + const void *source, + int space, + unsigned_word base, + unsigned nr_bytes) +{ + struct mn103int *controller = hw_data (me); + const unsigned8 *buf = source; + unsigned byte; + /* HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); */ + for (byte = 0; byte < nr_bytes; byte++) + { + unsigned_word address = base + byte; + unsigned_word offset; + switch (decode_addr (me, controller, address, &offset)) + { + case ICR_BLOCK: + write_icr (me, controller, offset, buf[byte]); + break; + case IAGR_BLOCK: + /* not allowed */ + break; + case EXTMD_BLOCK: + write_extmd (me, controller, offset, buf[byte]); + break; + default: + hw_abort (me, "bad switch"); + } + } + return nr_bytes; +} + +static int +mn103int_ioctl(struct hw *me, + hw_ioctl_request request, + va_list ap) +{ + struct mn103int *controller = (struct mn103int *)hw_data(me); + controller->group[0].request = EXTRACT_ID(4); + mn103int_port_event(me, 2 /* nmi_port(syserr) */, NULL, 0, 0); + return 0; +} + + +const struct hw_descriptor dv_mn103int_descriptor[] = { + { "mn103int", mn103int_finish, }, + { NULL }, +};

dv-mn103int.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: config.in =================================================================== --- config.in (nonexistent) +++ config.in (revision 1765) @@ -0,0 +1,183 @@ +/* config.in. Generated automatically from configure.in by autoheader. */ + +/* Define if using alloca.c. */ +#undef C_ALLOCA + +/* Define to empty if the keyword does not work. */ +#undef const + +/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems. + This function is required for alloca.c support on those systems. */ +#undef CRAY_STACKSEG_END + +/* Define if you have alloca, as a function or macro. */ +#undef HAVE_ALLOCA + +/* Define if you have and it should be used (not on Ultrix). */ +#undef HAVE_ALLOCA_H + +/* Define if you have a working `mmap' system call. */ +#undef HAVE_MMAP + +/* Define as __inline if that's what the C compiler calls it. */ +#undef inline + +/* Define to `long' if doesn't define. */ +#undef off_t + +/* Define if you need to in order for stat and other things to work. */ +#undef _POSIX_SOURCE + +/* Define as the return type of signal handlers (int or void). */ +#undef RETSIGTYPE + +/* Define to `unsigned' if doesn't define. */ +#undef size_t + +/* If using the C implementation of alloca, define if you know the + direction of stack growth for your system; otherwise it will be + automatically deduced at run-time. + STACK_DIRECTION > 0 => grows toward higher addresses + STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown + */ +#undef STACK_DIRECTION + +/* Define if you have the ANSI C header files. */ +#undef STDC_HEADERS + +/* Define if your processor stores words with the most significant + byte first (like Motorola and SPARC, unlike Intel and VAX). */ +#undef WORDS_BIGENDIAN + +/* Define to 1 if NLS is requested. */ +#undef ENABLE_NLS + +/* Define as 1 if you have gettext and don't want to use GNU gettext. */ +#undef HAVE_GETTEXT + +/* Define as 1 if you have the stpcpy function. */ +#undef HAVE_STPCPY + +/* Define if your locale.h file contains LC_MESSAGES. */ +#undef HAVE_LC_MESSAGES + +/* Define if you have the __argz_count function. */ +#undef HAVE___ARGZ_COUNT + +/* Define if you have the __argz_next function. */ +#undef HAVE___ARGZ_NEXT + +/* Define if you have the __argz_stringify function. */ +#undef HAVE___ARGZ_STRINGIFY + +/* Define if you have the __setfpucw function. */ +#undef HAVE___SETFPUCW + +/* Define if you have the chmod function. */ +#undef HAVE_CHMOD + +/* Define if you have the chown function. */ +#undef HAVE_CHOWN + +/* Define if you have the dcgettext function. */ +#undef HAVE_DCGETTEXT + +/* Define if you have the execv function. */ +#undef HAVE_EXECV + +/* Define if you have the execve function. */ +#undef HAVE_EXECVE + +/* Define if you have the fork function. */ +#undef HAVE_FORK + +/* Define if you have the getcwd function. */ +#undef HAVE_GETCWD + +/* Define if you have the getpagesize function. */ +#undef HAVE_GETPAGESIZE + +/* Define if you have the getrusage function. */ +#undef HAVE_GETRUSAGE + +/* Define if you have the munmap function. */ +#undef HAVE_MUNMAP + +/* Define if you have the putenv function. */ +#undef HAVE_PUTENV + +/* Define if you have the setenv function. */ +#undef HAVE_SETENV + +/* Define if you have the setlocale function. */ +#undef HAVE_SETLOCALE + +/* Define if you have the sigaction function. */ +#undef HAVE_SIGACTION + +/* Define if you have the stpcpy function. */ +#undef HAVE_STPCPY + +/* Define if you have the strcasecmp function. */ +#undef HAVE_STRCASECMP + +/* Define if you have the strchr function. */ +#undef HAVE_STRCHR + +/* Define if you have the time function. */ +#undef HAVE_TIME + +/* Define if you have the utime function. */ +#undef HAVE_UTIME + +/* Define if you have the header file. */ +#undef HAVE_ARGZ_H + +/* Define if you have the header file. */ +#undef HAVE_FCNTL_H + +/* Define if you have the header file. */ +#undef HAVE_FPU_CONTROL_H + +/* Define if you have the header file. */ +#undef HAVE_LIMITS_H + +/* Define if you have the header file. */ +#undef HAVE_LOCALE_H + +/* Define if you have the header file. */ +#undef HAVE_MALLOC_H + +/* Define if you have the header file. */ +#undef HAVE_NL_TYPES_H + +/* Define if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define if you have the header file. */ +#undef HAVE_STRING_H + +/* Define if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_PARAM_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_RESOURCE_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_TIME_H + +/* Define if you have the header file. */ +#undef HAVE_TIME_H + +/* Define if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define if you have the header file. */ +#undef HAVE_UTIME_H + +/* Define if you have the header file. */ +#undef HAVE_VALUES_H

config.in Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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