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  • This comparison shows the changes necessary to convert path 
    /or1k/trunk/mp3/syn/design_compiler
    from Rev 637 to Rev 1765
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  •

Rev 637 → Rev 1765

/bin/cons_vs_umc18.inc
0,0 → 1,52
/* Constraints */
CLK_UNCERTAINTY = 0.1 /* 100 ps */
DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */
DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */
 
/* Clocks constraints */
create_clock dwb_clk_i -period CLK_PERIOD
create_clock iwb_clk_i -period CLK_PERIOD
create_clock CLK -period CLK_PERIOD
set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY
set_dont_touch_network all_clocks()
 
/* Reset constraints */
set_driving_cell -none RST
set_drive 0 RST
set_dont_touch_network RST
 
/* All inputs except reset and clock */
all_inputs_wo_rst_clk = all_inputs() - CLK - RST
 
/* Set output delays and load for output signals
*
* All outputs are assumed to go directly into
* external flip-flops for the purpose of this
* synthesis
*/
set_output_delay DFFPQ2_SETUP -clock CLK all_outputs()
set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs()
 
/* Input delay and driving cell of all inputs
*
* All these signals are assumed to come directly from
* flip-flops for the purpose of this synthesis
*
*/
set_input_delay DFFPQ2_CKQ -clock CLK all_inputs_wo_rst_clk
set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk
 
/* Set design fanout */
/*
set_max_fanout 10 TOPLEVEL
*/
 
/* Set area constraint */
set_max_area MAX_AREA
 
/* Optimize all near-critical paths to give extra slack for layout */
c_range = CLK_PERIOD * 0.1
group_path -critical_range c_range -name CLK -to CLK
 
/* Operating conditions */
set_operating_conditions WORST
/bin/tech_vs_umc18.inc
0,0 → 1,24
/* Set Virtual Silicon UMC 0.18u standard cell library */
 
search_path = {. /libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ /libs/vs_rams/ /usr/dc/libraries/syn/ }
snps = get_unix_variable("SYNOPSYS")
synthetic_library = { \
snps + "/libraries/syn/dw01.sldb" \
snps + "/libraries/syn/dw02.sldb" \
snps + "/libraries/syn/dw03.sldb" \
snps + "/libraries/syn/dw04.sldb" \
snps + "/libraries/syn/dw05.sldb" \
snps + "/libraries/syn/dw06.sldb" \
snps + "/libraries/syn/dw07.sldb" }
target_library = { umcl18u250t2_wc.db \
vs_hdsp_2048x32_tc_1.2V_25C.db \
vs_hdsp_2048x8_tc_1.2V_25C.db \
vs_hdsp_512x20_tc_1.2V_25C.db \
vs_hdsp_64x14_tc_1.2V_25C.db \
vs_hdsp_64x22_tc_1.2V_25C.db \
vs_hdsp_64x24_tc_1.2V_25C.db \
vs_hdtp_64x32_tc_1.2V_25C.db \
}
link_library = target_library + synthetic_library
symbol_library = { umcl18u250t2.sdb }
 
/bin/top.scr
0,0 → 1,71
/*
* User defines for synthesizing RTC IP core
*
*/
TOPLEVEL = or1200_top
include ../bin/select_tech.inc
CLK = clk_i
RST = rst_i
CLK_PERIOD = 10 /* 250 MHz */
MAX_AREA = 0 /* Push hard */
DO_UNGROUP = no /* yes, no */
DO_VERIFY = no /* yes, no */
 
get_license DC-Ultra-Features
get_license DC-Ultra-Opt
get_license BOA-BRT
 
/* Starting timestamp */
sh date
 
/* Set some basic variables related to environment */
include ../bin/set_env.inc
STAGE = final
 
/* Load libraries */
include ../bin/tech_ + TECH + .inc
 
/* Load HDL source files */
include ../bin/read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log
 
/* Set design top */
current_design TOPLEVEL
 
/* Link all blocks and uniquify them */
link
uniquify
check_design > LOG_PATH + check_design_ + TOPLEVEL + .log
 
/* Apply constraints */
if (TECH == "vs_umc18") {
include ../bin/cons_vs_umc18.inc
} else if (TECH == "art_umc18") {
include ../bin/cons_art_umc18.inc
} else {
echo "Error: Unsupported technology"
exit
}
 
/* Lets do basic synthesis */
if (DO_UNGROUP == "yes") {
ungroup -all
}
/* set_ultra_optimization -f
compile -boundary_optimization -map_effort medium -ungroup_all
*/
compile -map_effort low
 
/* Dump gate-level from incremental synthesis */
include ../bin/save_design.inc
 
/* Generate reports for incremental synthesis */
include ../bin/reports.inc
 
/* Verify design */
if (DO_VERIFY == "yes") {
compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log
}
 
/* Finish */
sh date
exit
/bin/select_tech.inc
0,0 → 1,5
/* Defaults */
 
TECH = vs_umc18 /* vs_umc18, art_umc18 */
CLK_PERIOD = 10 /* 250 MHz */
MAX_AREA = 0 /* Push hard */
/bin/read_design.inc
0,0 → 1,56
/* Set search path for verilog include files */
search_path = search_path + RTL_PATH + { GATE_PATH }
 
/* Read verilog files of the RTC IP core */
if (TOPLEVEL == "or1200_top") {
 
read -f verilog ../src/asic.v
read -f verilog or1200_alu.v
read -f verilog or1200_amultp2_32x32.v
read -f verilog or1200_cfgr.v
read -f verilog or1200_cpu.v
read -f verilog or1200_ctrl.v
read -f verilog or1200_dc_fsm.v
read -f verilog or1200_dc_ram.v
read -f verilog or1200_dc_tag.v
read -f verilog or1200_dc_top.v
read -f verilog or1200_dmmu_tlb.v
read -f verilog or1200_dmmu_top.v
read -f verilog or1200_dpram_32x32.v
read -f verilog or1200_du.v
read -f verilog or1200_except.v
read -f verilog or1200_freeze.v
read -f verilog or1200_genpc.v
read -f verilog or1200_gmultp2_32x32.v
read -f verilog or1200_ic_fsm.v
read -f verilog or1200_ic_ram.v
read -f verilog or1200_ic_tag.v
read -f verilog or1200_ic_top.v
read -f verilog or1200_if.v
read -f verilog or1200_immu_tlb.v
read -f verilog or1200_immu_top.v
read -f verilog or1200_lsu.v
read -f verilog or1200_mem2reg.v
read -f verilog or1200_mult_mac.v
read -f verilog or1200_operandmuxes.v
read -f verilog or1200_pic.v
read -f verilog or1200_pm.v
read -f verilog or1200_reg2mem.v
read -f verilog or1200_rf.v
read -f verilog or1200_spram_2048x32.v
read -f verilog or1200_spram_2048x8.v
read -f verilog or1200_spram_512x20.v
read -f verilog or1200_spram_64x14.v
read -f verilog or1200_spram_64x22.v
read -f verilog or1200_spram_64x24.v
read -f verilog or1200_sprs.v
read -f verilog or1200_top.v
read -f verilog or1200_tt.v
read -f verilog or1200_wb_biu.v
read -f verilog or1200_wbmux.v
 
} else {
echo "Non-existing top level."
exit
}
 
/bin/save_design.inc
0,0 → 1,5
/* Save current design using synopsys format */
write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db
 
/* Save current design using verilog format */
write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v
/bin/reports.inc
0,0 → 1,10
/* Basic reports */
report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log
report_timing -nworst 10 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log
report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log
report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log
report_constraint > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log
/*
report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log
*/
 
/bin/set_env.inc
0,0 → 1,20
/* Enable Verilog HDL preprocessor */
hdlin_enable_vpp = true
 
/* Set log path */
LOG_PATH = "../log/"
 
/* Set gate-level netlist path */
GATE_PATH = "../out/"
 
/* Set RAMS_PATH */
RAMS_PATH = "../../../lib/"
 
/* Set RTL source path */
RTL_PATH = { "../../../rtl/verilog/", "../../../rtl/verilog/audio/", \
"../../../rtl/verilog/dbg_interface/", "../../../rtl/verilog/or1200/", \
"../../../rtl/verilog/mem_if/", "../../../rtl/verilog/ssvga/" }
 
/* Optimize adders */
synlib_model_map_effort = high
hlo_share_effort = medium
/bin/cons_art_umc18.inc
0,0 → 1,50
/* Constraints */
CLK_UNCERTAINTY = 0.1 /* 100 ps */
DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */
DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */
 
/* Clocks constraints */
create_clock CLK -period CLK_PERIOD
set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY
set_dont_touch_network all_clocks()
 
/* Reset constraints */
set_driving_cell -none RST
set_drive 0 RST
set_dont_touch_network RST
 
/* All inputs except reset and clock */
all_inputs_wo_rst_clk = all_inputs() - CLK - RST
 
/* Set output delays and load for output signals
*
* All outputs are assumed to go directly into
* external flip-flops for the purpose of this
* synthesis
*/
set_output_delay DFFHQX2_SETUP -clock CLK all_outputs()
set_load load_of(typical/DFFHQX2/D) * 1 all_outputs()
 
/* Input delay and driving cell of all inputs
*
* All these signals are assumed to come directly from
* flip-flops for the purpose of this synthesis
*
*/
set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk
set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk
 
/* Set design fanout */
/*
set_max_fanout 10 TOPLEVEL
*/
 
/* Set area constraint */
set_max_area MAX_AREA
 
/* Optimize all near-critical paths to give extra slack for layout */
c_range = CLK_PERIOD * 0.05
group_path -critical_range c_range -name CLK -to CLK
 
/* Operating conditions */
set_operating_conditions typical
/bin/tech_art_umc18.inc
0,0 → 1,17
/* Set Artisan Sage-X UMC 0.18u standard cell library */
 
search_path = {. /libs/Artisan/aci/sc-x/synopsys/ } + \
{ /libs/Artisan/aci/sc-x/symbols/synopsys/ }
snps = get_unix_variable("SYNOPSYS")
synthetic_library = { \
snps + "/libraries/syn/dw01.sldb" \
snps + "/libraries/syn/dw02.sldb" \
snps + "/libraries/syn/dw03.sldb" \
snps + "/libraries/syn/dw04.sldb" \
snps + "/libraries/syn/dw05.sldb" \
snps + "/libraries/syn/dw06.sldb" \
snps + "/libraries/syn/dw07.sldb" }
target_library = { typical.db }
link_library = target_library + synthetic_library
symbol_library = { umc18.sdb }
 
/run/dodesign
0,0 → 1,5
#!/bin/sh -f
 
# nohup dc_shell -f ../bin/top.scr | tee ../log/top.log
dc_shell -f ../bin/top.scr > ../log/top.log
mv command.log ../log
run/dodesign Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: out/README =================================================================== --- out/README (nonexistent) +++ out/README (revision 1765) @@ -0,0 +1 @@ +This directory containts gate-level netlists.

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