URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/or1k/trunk/rc203soc/syn/synplicity
- from Rev 1599 to Rev 1765
- ↔ Reverse comparison
Rev 1599 → Rev 1765
/rc203.tcl
0,0 → 1,130
project -new |
|
#Select FPGA |
set_option -technology VIRTEX2 |
set_option -part XC2V3000 |
set_option -grade -4 |
set_option -package FG676 |
set_option -frequency auto |
|
|
# |
# Add files to project |
# |
|
|
# Memory controllers |
add_file "../../rtl/verilog/rc203/rc203_zbtcontroller.v" |
add_file "../../rtl/verilog/rc203/rc203_romcontroller.v" |
add_file "../../rtl/verilog/rc203/rc203_ethcontroller.v" |
|
# RAM wrapppers (you can use unisim.v instead) |
add_file "../RAMB4_S16_S16.v" |
add_file "../RAMB4_S4.v" |
add_file "../RAMB4_S16.v" |
|
# Dbg_interface |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_wb_defines.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_cpu.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_cpu_defines.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_cpu_registers.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_crc32_d1.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_defines.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_register.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_top.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_wb.v" |
|
# Tap controller |
add_file "../../rtl/verilog/jtag/tap/rtl/verilog/tap_defines.v" |
add_file "../../rtl/verilog/jtag/tap/rtl/verilog/tap_top.v" |
|
# UART 16550 |
add_file "../../rtl/verilog/uart16550/rtl/verilog/raminfr.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_top.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v" |
|
# OR1200 (with 4KB data and instruction caches) |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_du.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_except.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_if.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_top.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v" |
|
# Depending of cache size and register file type you must add or |
# remove some of this files |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v" |
#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v" |
#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v" |
#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v" |
#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v" |
#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v" |
#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v" |
#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v" |
#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v" |
#add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v" |
|
# Top files |
add_file "../../rtl/verilog/tc_top.v" |
add_file "../../rtl/verilog/soc.v" |
|
# Include or1200_defines.v path |
set_option -include_path "../../rtl/verilog/or1200/rtl/verilog/" |
|
# Results |
impl -name "./rev_1" |
set_option -result_file "./rev_1/rc203soc.edf" |
set_option -top_module soc |
|
|
#RUN |
project -run synthesis |
/rc200.tcl
0,0 → 1,130
project -new |
|
#Select FPGA |
set_option -technology VIRTEX2 |
set_option -part XC2V1000 |
set_option -grade -4 |
set_option -package FG456 |
set_option -frequency 50.0 |
|
|
# |
# Add files to project |
# |
|
|
# Memory controllers |
add_file "../../rtl/verilog/rc203/rc203_zbtcontroller.v" |
add_file "../../rtl/verilog/rc203/rc203_romcontroller.v" |
add_file "../../rtl/verilog/rc203/rc203_ethcontroller.v" |
|
# RAM wrapppers |
add_file "../RAMB4_S16_S16.v" |
add_file "../RAMB4_S4.v" |
add_file "../RAMB4_S16.v" |
|
# Dbg_interface |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_wb_defines.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_cpu.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_cpu_defines.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_cpu_registers.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_crc32_d1.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_defines.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_register.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_top.v" |
add_file "../../rtl/verilog/dbg_interface/rtl/verilog/dbg_wb.v" |
|
# Tap controller |
add_file "../../rtl/verilog/jtag/tap/rtl/verilog/tap_defines.v" |
add_file "../../rtl/verilog/jtag/tap/rtl/verilog/tap_top.v" |
|
# UART 16550 |
add_file "../../rtl/verilog/uart16550/rtl/verilog/raminfr.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_debug_if.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_defines.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_receiver.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_regs.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_rfifo.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_sync_flops.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_tfifo.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_top.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_transmitter.v" |
add_file "../../rtl/verilog/uart16550/rtl/verilog/uart_wb.v" |
|
# OR1200 (with 4KB data and instruction caches) |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_alu.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_amultp2_32x32.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_cfgr.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_cpu.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_ctrl.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dc_fsm.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dc_ram.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dc_tag.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dc_top.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_defines.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_tlb.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dmmu_top.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_du.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_except.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_freeze.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_genpc.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_gmultp2_32x32.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_ic_fsm.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_ic_ram.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_ic_tag.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_ic_top.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_if.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_immu_tlb.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_immu_top.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_lsu.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_mem2reg.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_mult_mac.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_operandmuxes.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_pic.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_pm.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_qmem_top.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_reg2mem.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_rf.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_sb.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_sb_fifo.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_sprs.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_top.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_tt.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_wb_biu.v" |
|
# Depending of cache size and register file type you must add or |
# remove some of this files |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_dpram_32x32.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_rfram_generic.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_tpram_32x32.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x8.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_128x32.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x32_bw.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_2048x8.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_256x21.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_32x24.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x14.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x22.v" |
add_file "../../rtl/verilog/or1200/rtl/verilog/or1200_spram_64x24.v" |
|
# Top files |
add_file "../../rtl/verilog/tc_top.v" |
add_file "../../rtl/verilog/soc.v" |
|
# Include or1200_defines.v path |
set_option -include_path "../../rtl/verilog/or1200/rtl/verilog/" |
|
# Results |
impl -name "./rev_1" |
set_option -result_file "./rev_1/rc200soc.edf" |
set_option -top_module soc |
|
|
#RUN |
project -run synthesis |