OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

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    /or1k/trunk/rtems-20020807/doc/supplements/powerpc
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Rev 1028 → Rev 1765

/Makefile.in
0,0 → 1,614
# Makefile.in generated by automake 1.6.2 from Makefile.am.
# @configure_input@
 
# Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
# Free Software Foundation, Inc.
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# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
 
# This program is distributed in the hope that it will be useful,
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#
# Chapters which get automatic processing
#
 
$(srcdir)/cpumodel.texi: cpumodel.t
$(BMENU2) -p "Preface" \
-u "Top" \
-n "Calling Conventions" < $< > $@
 
$(srcdir)/callconv.texi: callconv.t
$(BMENU2) -p "CPU Model Dependent Features Low Power Model" \
-u "Top" \
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$(srcdir)/memmodel.texi: memmodel.t
$(BMENU2) -p "Calling Conventions User-Provided Routines" \
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# Interrupt Chapter:
# 1. Replace Times and Sizes
# 2. Build Node Structure
$(srcdir)/intr.texi: intr_NOTIMES.t PSIM_TIMES
${REPLACE2} -p $(srcdir)/PSIM_TIMES $(srcdir)/intr_NOTIMES.t | \
$(BMENU2) -p "Memory Model Flat Memory Model" \
-u "Top" \
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$(srcdir)/fatalerr.texi: fatalerr.t
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$(srcdir)/bsp.texi: bsp.t
$(BMENU2) -p "Default Fatal Error Processing Default Fatal Error Handler Operations" \
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$(srcdir)/cputable.texi: cputable.t
$(BMENU2) -p "Board Support Packages Processor Initialization" \
-u "Top" \
-n "Memory Requirements" < $< > $@
 
# Worksheets Chapter:
# 1. Obtain the Shared File
# 2. Replace Times and Sizes
# 3. Build Node Structure
 
$(srcdir)/wksheets.texi: $(top_srcdir)/common/wksheets.t PSIM_TIMES
${REPLACE2} -p $(srcdir)/PSIM_TIMES \
$(top_srcdir)/common/wksheets.t | \
$(BMENU2) -p "Processor Dependent Information Table CPU Dependent Information Table" \
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# Timing Specification Chapter:
# 1. Copy the Shared File
# 3. Build Node Structure
$(srcdir)/timing.texi: $(top_srcdir)/common/timing.t
$(BMENU2) -p "Memory Requirements RTEMS RAM Workspace Worksheet" \
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# Timing Data for PSIM BSP Chapter:
# 1. Copy the Shared File
# 2. Replace Times and Sizes
# 3. Build Node Structure
 
$(srcdir)/timePSIM.texi: $(top_srcdir)/common/timetbl.t timePSIM.t
cat $(srcdir)/timePSIM.t $(top_srcdir)/common/timetbl.t >timePSIM_.t
@echo >>timePSIM_.t
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@echo "@end tex" >>timePSIM_.t
${REPLACE2} -p $(srcdir)/PSIM_TIMES timePSIM_.t | \
$(BMENU2) -p "Timing Specification Terminology" \
-u "Top" \
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# Timing Data for DMV177 BSP Chapter:
# 1. Copy the Shared File
# 2. Replace Times and Sizes
# 3. Build Node Structure
 
$(srcdir)/timeDMV177.texi: $(top_srcdir)/common/timetbl.t timeDMV177.t
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@echo "@end tex" >>timeDMV177_.t
${REPLACE2} -p $(srcdir)/DMV177_TIMES timeDMV177_.t | \
$(BMENU2) -p "PSIM Timing Data Rate Monotonic Manager" \
-u "Top" \
-n "Command and Variable Index" > $@
# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
.NOEXPORT:
/stamp-vti
0,0 → 1,4
@set UPDATED 17 January 2002
@set UPDATED-MONTH January 2002
@set EDITION ss-20020717
@set VERSION ss-20020717
/bsp.t
0,0 → 1,76
@c
@c COPYRIGHT (c) 1988-2002.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c bsp.t,v 1.9 2002/01/17 21:47:46 joel Exp
@c
 
@chapter Board Support Packages
 
@section Introduction
 
An RTEMS Board Support Package (BSP) must be designed
to support a particular processor and target board combination.
This chapter presents a discussion of PowerPC specific BSP issues.
For more information on developing a BSP, refer to the chapter
titled Board Support Packages in the RTEMS
Applications User's Guide.
 
@section System Reset
 
An RTEMS based application is initiated or
re-initiated when the PowerPC processor is reset. The PowerPC
architecture defines a Reset Exception, but leaves the
details of the CPU state as implementation specific. Please
refer to the User's Manual for the CPU model in question.
 
In general, at power-up the PowerPC begin execution at address
0xFFF00100 in supervisor mode with all exceptions disabled. For
soft resets, the CPU will vector to either 0xFFF00100 or 0x00000100
depending upon the setting of the Exception Prefix bit in the MSR.
If during a soft reset, a Machine Check Exception occurs, then the
CPU may execute a hard reset.
 
@section Processor Initialization
 
It is the responsibility of the application's
initialization code to initialize the CPU and board
to a quiescent state before invoking the @code{rtems_initialize_executive}
directive. It is recommended that the BSP utilize the @code{predriver_hook}
to install default handlers for all exceptions. These default handlers
may be overwritten as various device drivers and subsystems install
their own exception handlers. Upon completion of RTEMS executive
initialization, all interrupts are enabled.
 
If this PowerPC implementation supports on-chip caching
and this is to be utilized, then it should be enabled during the
reset application initialization code. On-chip caching has been
observed to prevent some emulators from working properly, so it
may be necessary to run with caching disabled to use these emulators.
 
In addition to the requirements described in the
@b{Board Support Packages} chapter of the @b{@value{LANGUAGE}
Applications User's Manual} for the reset code
which is executed before the call to @code{rtems_initialize_executive},
the PowrePC version has the following specific requirements:
 
@itemize @bullet
@item Must leave the PR bit of the Machine State Register (MSR) set
to 0 so the PowerPC remains in the supervisor state.
 
@item Must set stack pointer (sp or r1) such that a minimum stack
size of MINIMUM_STACK_SIZE bytes is provided for the
@code{rtems_initialize_executive} directive.
 
@item Must disable all external interrupts (i.e. clear the EI (EE)
bit of the machine state register).
 
@item Must enable traps so window overflow and underflow
conditions can be properly handled.
 
@item Must initialize the PowerPC's initial Exception Table with default
handlers.
 
@end itemize
 
/DMV177_TIMES
0,0 → 1,248
#
# PowerPC/603e/PSIM Timing and Size Information
#
# DMV177_TIMES,v 1.4 2002/01/17 21:47:46 joel Exp
#
 
#
# CPU Model Information
#
RTEMS_BSP DMV177
RTEMS_CPU_MODEL PPC603e
#
# Interrupt Latency
#
# NOTE: In general, the text says it is hand-calculated to be
# RTEMS_MAXIMUM_DISABLE_PERIOD at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
# Mhz and this was last calculated for Release
# RTEMS_VERSION_FOR_MAXIMUM_DISABLE_PERIOD.
#
RTEMS_MAXIMUM_DISABLE_PERIOD TBD
RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ 100.0
RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD 4.0.0-lmco
#
# Context Switch Times
#
RTEMS_NO_FP_CONTEXTS 585
RTEMS_RESTORE_1ST_FP_TASK 730
RTEMS_SAVE_INIT_RESTORE_INIT 478
RTEMS_SAVE_IDLE_RESTORE_INIT 825
RTEMS_SAVE_IDLE_RESTORE_IDLE 478
#
# Task Manager Times
#
RTEMS_TASK_CREATE_ONLY 2301
RTEMS_TASK_IDENT_ONLY 2900
RTEMS_TASK_START_ONLY 794
RTEMS_TASK_RESTART_CALLING_TASK 1137
RTEMS_TASK_RESTART_SUSPENDED_RETURNS_TO_CALLER 906
RTEMS_TASK_RESTART_BLOCKED_RETURNS_TO_CALLER 1102
RTEMS_TASK_RESTART_READY_RETURNS_TO_CALLER 928
RTEMS_TASK_RESTART_SUSPENDED_PREEMPTS_CALLER 1483
RTEMS_TASK_RESTART_BLOCKED_PREEMPTS_CALLER 1640
RTEMS_TASK_RESTART_READY_PREEMPTS_CALLER 1601
RTEMS_TASK_DELETE_CALLING_TASK 2117
RTEMS_TASK_DELETE_SUSPENDED_TASK 1555
RTEMS_TASK_DELETE_BLOCKED_TASK 1609
RTEMS_TASK_DELETE_READY_TASK 1620
RTEMS_TASK_SUSPEND_CALLING_TASK 960
RTEMS_TASK_SUSPEND_RETURNS_TO_CALLER 433
RTEMS_TASK_RESUME_TASK_READIED_RETURNS_TO_CALLER 960
RTEMS_TASK_RESUME_TASK_READIED_PREEMPTS_CALLER 803
RTEMS_TASK_SET_PRIORITY_OBTAIN_CURRENT_PRIORITY 368
RTEMS_TASK_SET_PRIORITY_RETURNS_TO_CALLER 633
RTEMS_TASK_SET_PRIORITY_PREEMPTS_CALLER 1211
RTEMS_TASK_MODE_OBTAIN_CURRENT_MODE 184
RTEMS_TASK_MODE_NO_RESCHEDULE 213
RTEMS_TASK_MODE_RESCHEDULE_RETURNS_TO_CALLER 247
RTEMS_TASK_MODE_RESCHEDULE_PREEMPTS_CALLER 919
RTEMS_TASK_GET_NOTE_ONLY 382
RTEMS_TASK_SET_NOTE_ONLY 383
RTEMS_TASK_WAKE_AFTER_YIELD_RETURNS_TO_CALLER 245
RTEMS_TASK_WAKE_AFTER_YIELD_PREEMPTS_CALLER 851
RTEMS_TASK_WAKE_WHEN_ONLY 1275
#
# Interrupt Manager
#
RTEMS_INTR_ENTRY_RETURNS_TO_NESTED 201
RTEMS_INTR_ENTRY_RETURNS_TO_INTERRUPTED_TASK 206
RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK 202
RTEMS_INTR_EXIT_RETURNS_TO_NESTED 201
RTEMS_INTR_EXIT_RETURNS_TO_INTERRUPTED_TASK 213
RTEMS_INTR_EXIT_RETURNS_TO_PREEMPTING_TASK 857
#
# Clock Manager
#
RTEMS_CLOCK_SET_ONLY 792
RTEMS_CLOCK_GET_ONLY 78
RTEMS_CLOCK_TICK_ONLY 214
#
# Timer Manager
#
RTEMS_TIMER_CREATE_ONLY 357
RTEMS_TIMER_IDENT_ONLY 2828
RTEMS_TIMER_DELETE_INACTIVE 432
RTEMS_TIMER_DELETE_ACTIVE 471
RTEMS_TIMER_FIRE_AFTER_INACTIVE 607
RTEMS_TIMER_FIRE_AFTER_ACTIVE 646
RTEMS_TIMER_FIRE_WHEN_INACTIVE 766
RTEMS_TIMER_FIRE_WHEN_ACTIVE 764
RTEMS_TIMER_RESET_INACTIVE 552
RTEMS_TIMER_RESET_ACTIVE 766
RTEMS_TIMER_CANCEL_INACTIVE 339
RTEMS_TIMER_CANCEL_ACTIVE 378
#
# Semaphore Manager
#
RTEMS_SEMAPHORE_CREATE_ONLY 571
RTEMS_SEMAPHORE_IDENT_ONLY 3243
RTEMS_SEMAPHORE_DELETE_ONLY 575
RTEMS_SEMAPHORE_OBTAIN_AVAILABLE 414
RTEMS_SEMAPHORE_OBTAIN_NOT_AVAILABLE_NO_WAIT 414
RTEMS_SEMAPHORE_OBTAIN_NOT_AVAILABLE_CALLER_BLOCKS 1254
RTEMS_SEMAPHORE_RELEASE_NO_WAITING_TASKS 501
RTEMS_SEMAPHORE_RELEASE_TASK_READIED_RETURNS_TO_CALLER 636
RTEMS_SEMAPHORE_RELEASE_TASK_READIED_PREEMPTS_CALLER 982
#
# Message Manager
#
RTEMS_MESSAGE_QUEUE_CREATE_ONLY 2270
RTEMS_MESSAGE_QUEUE_IDENT_ONLY 2828
RTEMS_MESSAGE_QUEUE_DELETE_ONLY 708
RTEMS_MESSAGE_QUEUE_SEND_NO_WAITING_TASKS 923
RTEMS_MESSAGE_QUEUE_SEND_TASK_READIED_RETURNS_TO_CALLER 955
RTEMS_MESSAGE_QUEUE_SEND_TASK_READIED_PREEMPTS_CALLER 1322
RTEMS_MESSAGE_QUEUE_URGENT_NO_WAITING_TASKS 919
RTEMS_MESSAGE_QUEUE_URGENT_TASK_READIED_RETURNS_TO_CALLER 955
RTEMS_MESSAGE_QUEUE_URGENT_TASK_READIED_PREEMPTS_CALLER 1322
RTEMS_MESSAGE_QUEUE_BROADCAST_NO_WAITING_TASKS 589
RTEMS_MESSAGE_QUEUE_BROADCAST_TASK_READIED_RETURNS_TO_CALLER 1079
RTEMS_MESSAGE_QUEUE_BROADCAST_TASK_READIED_PREEMPTS_CALLER 1435
RTEMS_MESSAGE_QUEUE_RECEIVE_AVAILABLE 755
RTEMS_MESSAGE_QUEUE_RECEIVE_NOT_AVAILABLE_NO_WAIT 467
RTEMS_MESSAGE_QUEUE_RECEIVE_NOT_AVAILABLE_CALLER_BLOCKS 1283
RTEMS_MESSAGE_QUEUE_FLUSH_NO_MESSAGES_FLUSHED 369
RTEMS_MESSAGE_QUEUE_FLUSH_MESSAGES_FLUSHED 431
#
# Event Manager
#
RTEMS_EVENT_SEND_NO_TASK_READIED 354
RTEMS_EVENT_SEND_TASK_READIED_RETURNS_TO_CALLER 571
RTEMS_EVENT_SEND_TASK_READIED_PREEMPTS_CALLER 946
RTEMS_EVENT_RECEIVE_OBTAIN_CURRENT_EVENTS 43
RTEMS_EVENT_RECEIVE_AVAILABLE 357
RTEMS_EVENT_RECEIVE_NOT_AVAILABLE_NO_WAIT 331
RTEMS_EVENT_RECEIVE_NOT_AVAILABLE_CALLER_BLOCKS 1043
#
# Signal Manager
#
RTEMS_SIGNAL_CATCH_ONLY 267
RTEMS_SIGNAL_SEND_RETURNS_TO_CALLER 408
RTEMS_SIGNAL_SEND_SIGNAL_TO_SELF 607
RTEMS_SIGNAL_EXIT_ASR_OVERHEAD_RETURNS_TO_CALLING_TASK 464
RTEMS_SIGNAL_EXIT_ASR_OVERHEAD_RETURNS_TO_PREEMPTING_TASK 752
#
# Partition Manager
#
RTEMS_PARTITION_CREATE_ONLY 762
RTEMS_PARTITION_IDENT_ONLY 2828
RTEMS_PARTITION_DELETE_ONLY 426
RTEMS_PARTITION_GET_BUFFER_AVAILABLE 394
RTEMS_PARTITION_GET_BUFFER_NOT_AVAILABLE 376
RTEMS_PARTITION_RETURN_BUFFER_ONLY 420
#
# Region Manager
#
RTEMS_REGION_CREATE_ONLY 614
RTEMS_REGION_IDENT_ONLY 2878
RTEMS_REGION_DELETE_ONLY 425
RTEMS_REGION_GET_SEGMENT_AVAILABLE 515
RTEMS_REGION_GET_SEGMENT_NOT_AVAILABLE_NO_WAIT 472
RTEMS_REGION_GET_SEGMENT_NOT_AVAILABLE_CALLER_BLOCKS 1345
RTEMS_REGION_RETURN_SEGMENT_NO_WAITING_TASKS 544
RTEMS_REGION_RETURN_SEGMENT_TASK_READIED_RETURNS_TO_CALLER 935
RTEMS_REGION_RETURN_SEGMENT_TASK_READIED_PREEMPTS_CALLER 1296
#
# Dual-Ported Memory Manager
#
RTEMS_PORT_CREATE_ONLY 428
RTEMS_PORT_IDENT_ONLY 2828
RTEMS_PORT_DELETE_ONLY 421
RTEMS_PORT_INTERNAL_TO_EXTERNAL_ONLY 339
RTEMS_PORT_EXTERNAL_TO_INTERNAL_ONLY 339
#
# IO Manager
#
RTEMS_IO_INITIALIZE_ONLY 52
RTEMS_IO_OPEN_ONLY 42
RTEMS_IO_CLOSE_ONLY 44
RTEMS_IO_READ_ONLY 42
RTEMS_IO_WRITE_ONLY 44
RTEMS_IO_CONTROL_ONLY 42
#
# Rate Monotonic Manager
#
RTEMS_RATE_MONOTONIC_CREATE_ONLY 388
RTEMS_RATE_MONOTONIC_IDENT_ONLY 2826
RTEMS_RATE_MONOTONIC_CANCEL_ONLY 427
RTEMS_RATE_MONOTONIC_DELETE_ACTIVE 519
RTEMS_RATE_MONOTONIC_DELETE_INACTIVE 465
RTEMS_RATE_MONOTONIC_PERIOD_INITIATE_PERIOD_RETURNS_TO_CALLER 556
RTEMS_RATE_MONOTONIC_PERIOD_CONCLUDE_PERIOD_CALLER_BLOCKS 842
RTEMS_RATE_MONOTONIC_PERIOD_OBTAIN_STATUS 377
#
# Size Information
#
#
# xxx alloted for numbers
#
RTEMS_DATA_SPACE 428
RTEMS_MINIMUM_CONFIGURATION 30,980
RTEMS_MAXIMUM_CONFIGURATION 55540
# x,xxx alloted for numbers
RTEMS_CORE_CODE_SIZE 21,516
RTEMS_INITIALIZATION_CODE_SIZE 1,412
RTEMS_TASK_CODE_SIZE 4,804
RTEMS_INTERRUPT_CODE_SIZE 96
RTEMS_CLOCK_CODE_SIZE 536
RTEMS_TIMER_CODE_SIZE 1,380
RTEMS_SEMAPHORE_CODE_SIZE 1,928
RTEMS_MESSAGE_CODE_SIZE 532
RTEMS_EVENT_CODE_SIZE 100
RTEMS_SIGNAL_CODE_SIZE 100
RTEMS_PARTITION_CODE_SIZE 1,384
RTEMS_REGION_CODE_SIZE 1,780
RTEMS_DPMEM_CODE_SIZE 928
RTEMS_IO_CODE_SIZE 1,244
RTEMS_FATAL_ERROR_CODE_SIZE 44
RTEMS_RATE_MONOTONIC_CODE_SIZE 1,756
RTEMS_MULTIPROCESSING_CODE_SIZE 11,448
# xxx alloted for numbers
RTEMS_TIMER_CODE_OPTSIZE 340
RTEMS_SEMAPHORE_CODE_OPTSIZE 308
RTEMS_MESSAGE_CODE_OPTSIZE 532
RTEMS_EVENT_CODE_OPTSIZE 100
RTEMS_SIGNAL_CODE_OPTSIZE 100
RTEMS_PARTITION_CODE_OPTSIZE 244
RTEMS_REGION_CODE_OPTSIZE 292
RTEMS_DPMEM_CODE_OPTSIZE 244
RTEMS_IO_CODE_OPTSIZE NA
RTEMS_RATE_MONOTONIC_CODE_OPTSIZE 336
RTEMS_MULTIPROCESSING_CODE_OPTSIZE 612
# xxx alloted for numbers
RTEMS_BYTES_PER_TASK 456
RTEMS_BYTES_PER_TIMER 68
RTEMS_BYTES_PER_SEMAPHORE 120
RTEMS_BYTES_PER_MESSAGE_QUEUE 144
RTEMS_BYTES_PER_REGION 140
RTEMS_BYTES_PER_PARTITION 56
RTEMS_BYTES_PER_PORT 36
RTEMS_BYTES_PER_PERIOD 36
RTEMS_BYTES_PER_EXTENSION 64
RTEMS_BYTES_PER_FP_TASK 264
RTEMS_BYTES_PER_NODE 48
RTEMS_BYTES_PER_GLOBAL_OBJECT 20
RTEMS_BYTES_PER_PROXY 124
# x,xxx alloted for numbers
RTEMS_BYTES_OF_FIXED_SYSTEM_REQUIREMENTS 10008
 
/powerpc.texi
0,0 → 1,114
\input texinfo @c -*-texinfo-*-
@c %**start of header
@setfilename powerpc
@setcontentsaftertitlepage
@syncodeindex vr fn
@synindex ky cp
@paragraphindent 0
@c %**end of header
 
@c
@c COPYRIGHT (c) 1988-2002.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c powerpc.texi,v 1.16 2002/01/17 21:47:46 joel Exp
@c
 
@c
@c Master file for the PowerPC Applications Supplement
@c
 
@include version.texi
@include common/setup.texi
 
@ifset use-ascii
@dircategory RTEMS Target Supplements
@direntry
* RTEMS PowerPC Applications Supplement: (powerpc).
@end direntry
@end ifset
 
@c
@c Title Page Stuff
@c
 
@c
@c I don't really like having a short title page. --joel
@c
@c @shorttitlepage RTEMS PowerPC Applications Supplement
 
@setchapternewpage odd
@settitle RTEMS PowerPC Applications Supplement
@titlepage
@finalout
 
@title RTEMS PowerPC Applications Supplement
@subtitle Edition @value{EDITION}, for RTEMS @value{VERSION}
@sp 1
@subtitle @value{UPDATED}
@author On-Line Applications Research Corporation
@page
@include common/cpright.texi
@end titlepage
 
@c This prevents a black box from being printed on "overflow" lines.
@c The alternative is to rework a sentence to avoid this problem.
 
@include preface.texi
@include cpumodel.texi
@include callconv.texi
@include memmodel.texi
@include intr.texi
@include fatalerr.texi
@include bsp.texi
@include cputable.texi
@include wksheets.texi
@include timing.texi
@include timePSIM.texi
@include timeDMV177.texi
@ifinfo
@node Top, Preface, (dir), (dir)
@top powerpc
 
This is the online version of the RTEMS PowerPC Applications Supplement.
 
@menu
* Preface::
* CPU Model Dependent Features::
* Calling Conventions::
* Memory Model::
* Interrupt Processing::
* Default Fatal Error Processing::
* Board Support Packages::
* Processor Dependent Information Table::
* Memory Requirements::
* Timing Specification::
* PSIM Timing Data::
* DMV177 Timing Data::
* Command and Variable Index::
* Concept Index::
@end menu
 
@end ifinfo
@c
@c
@c Need to copy the emacs stuff and "trailer stuff" (index, toc) into here
@c
 
@node Command and Variable Index, Concept Index, DMV177 Timing Data Rate Monotonic Manager, Top
@unnumbered Command and Variable Index
 
There are currently no Command and Variable Index entries.
 
@c @printindex fn
 
@node Concept Index, , Command and Variable Index, Top
@unnumbered Concept Index
 
There are currently no Concept Index entries.
@c @printindex cp
 
@contents
@bye
 
/ChangeLog
0,0 → 1,15
2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
 
* Makefile.am: Remove AUTOMAKE_OPTIONS.
 
2002-01-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
 
* Makefile.am: Require automake-1.5.
 
2001-01-17 Joel Sherrill <joel@OARcorp.com>
 
* .cvsignore: Added rtems_header.html and rtems_footer.html.
 
2000-08-10 Joel Sherrill <joel@OARcorp.com>
 
* ChangeLog: New file.
/timePSIM.t
0,0 → 1,97
@c
@c Timing information for PSIM
@c
@c COPYRIGHT (c) 1988-2002.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c timePSIM.t,v 1.12 2002/01/17 21:47:46 joel Exp
@c
 
@include common/timemac.texi
@tex
\global\advance \smallskipamount by -4pt
@end tex
 
@chapter RTEMS_BSP Timing Data
 
@section Introduction
 
The timing data for RTEMS on the RTEMS_BSP target
is provided along with the target
dependent aspects concerning the gathering of the timing data.
The hardware platform used to gather the times is described to
give the reader a better understanding of each directive time
provided. Also, provided is a description of the interrupt
latency and the context switch times as they pertain to the
PowerPC version of RTEMS.
 
@section Hardware Platform
 
All times reported in this chapter were measured using the PowerPC
Instruction Simulator (PSIM). PSIM simulates a variety of PowerPC
6xx models with the PPC603e being used as the basis for the measurements
reported in this chapter.
 
The PowerPC decrementer register was was used to gather
all timing information. In real hardware implementations
of the PowerPC architecture, this register would typically
count something like CPU cycles or be a function of the clock
speed. However, with PSIM each count of the decrementer register
represents an instruction. Thus all measurements in this
chapter are reported as the actual number of instructions
executed. All sources of hardware interrupts were disabled,
although traps were enabled and the interrupt level of the
PowerPC allows all interrupts.
 
@section Interrupt Latency
 
The maximum period with traps disabled or the
processor interrupt level set to it's highest value inside RTEMS
is less than RTEMS_MAXIMUM_DISABLE_PERIOD
microseconds including the instructions which
disable and re-enable interrupts. The time required for the
PowerPC to vector an interrupt and for the RTEMS entry overhead
before invoking the user's trap handler are a total of
RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
microseconds. These combine to yield a worst case interrupt
latency of less than RTEMS_MAXIMUM_DISABLE_PERIOD +
RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK microseconds at
RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz.
[NOTE: The maximum period with interrupts disabled was last
determined for Release RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
 
The maximum period with interrupts disabled within
RTEMS is hand-timed with some assistance from RTEMS_BSP. The maximum
period with interrupts disabled with RTEMS occurs was not measured
on this target.
 
The interrupt vector and entry overhead time was
generated on the RTEMS_BSP benchmark platform using the PowerPC's
decrementer register. This register was programmed to generate
an interrupt after one countdown.
 
@section Context Switch
 
The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS
instructions on the RTEMS_BSP benchmark platform when no floating
point context is saved or restored. Additional execution time
is required when a TASK_SWITCH user extension is configured.
The use of the TASK_SWITCH extension is application dependent.
Thus, its execution time is not considered part of the raw
context switch time.
 
Since RTEMS was designed specifically for embedded
missile applications which are floating point intensive, the
executive is optimized to avoid unnecessarily saving and
restoring the state of the numeric coprocessor. The state of
the numeric coprocessor is only saved when an FLOATING_POINT
task is dispatched and that task was not the last task to
utilize the coprocessor. In a system with only one
FLOATING_POINT task, the state of the numeric coprocessor will
never be saved or restored. When the first FLOATING_POINT task
is dispatched, RTEMS does not need to save the current state of
the numeric coprocessor.
 
The following table summarizes the context switch
times for the RTEMS_BSP benchmark platform:
/version.texi
0,0 → 1,4
@set UPDATED 17 January 2002
@set UPDATED-MONTH January 2002
@set EDITION ss-20020717
@set VERSION ss-20020717
/memmodel.t
0,0 → 1,110
@c
@c COPYRIGHT (c) 1988-2002.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c memmodel.t,v 1.8 2002/01/17 21:47:46 joel Exp
@c
 
@chapter Memory Model
 
@section Introduction
 
A processor may support any combination of memory
models ranging from pure physical addressing to complex demand
paged virtual memory systems. RTEMS supports a flat memory
model which ranges contiguously over the processor's allowable
address space. RTEMS does not support segmentation or virtual
memory of any kind. The appropriate memory model for RTEMS
provided by the targeted processor and related characteristics
of that model are described in this chapter.
 
@section Flat Memory Model
 
The PowerPC architecture supports a variety of memory models.
RTEMS supports the PowerPC using a flat memory model with
paging disabled. In this mode, the PowerPC automatically
converts every address from a logical to a physical address
each time it is used. The PowerPC uses information provided
in the Block Address Translation (BAT) to convert these addresses.
 
Implementations of the PowerPC architecture may be thirty-two or sixty-four bit.
The PowerPC architecture supports a flat thirty-two or sixty-four bit address
space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
gigabytes) in thirty-two bit implementations or to 0xFFFFFFFFFFFFFFFF
in sixty-four bit implementations. Each address is represented
by either a thirty-two bit or sixty-four bit value and is byte addressable.
The address may be used to reference a single byte, half-word
(2-bytes), word (4 bytes), or in sixty-four bit implementations a
doubleword (8 bytes). Memory accesses within the address space are
performed in big or little endian fashion by the PowerPC based
upon the current setting of the Little-endian mode enable bit (LE)
in the Machine State Register (MSR). While the processor is in
big endian mode, memory accesses which are not properly aligned
generate an "alignment exception" (vector offset 0x00600). In
little endian mode, the PowerPC architecture does not require
the processor to generate alignment exceptions.
 
The following table lists the alignment requirements for a variety
of data accesses:
 
@ifset use-ascii
@example
@group
+--------------+-----------------------+
| Data Type | Alignment Requirement |
+--------------+-----------------------+
| byte | 1 |
| half-word | 2 |
| word | 4 |
| doubleword | 8 |
+--------------+-----------------------+
@end group
@end example
@end ifset
 
@ifset use-tex
@sp 1
@tex
\centerline{\vbox{\offinterlineskip\halign{
\vrule\strut#&
\hbox to 1.75in{\enskip\hfil#\hfil}&
\vrule#&
\hbox to 1.75in{\enskip\hfil#\hfil}&
\vrule#\cr
\noalign{\hrule}
&\bf Data Type &&\bf Alignment Requirement&\cr\noalign{\hrule}
&byte&&1&\cr\noalign{\hrule}
&half-word&&2&\cr\noalign{\hrule}
&word&&4&\cr\noalign{\hrule}
&doubleword&&8&\cr\noalign{\hrule}
}}\hfil}
@end tex
@end ifset
@ifset use-html
@html
<CENTER>
<TABLE COLS=2 WIDTH="60%" BORDER=2>
<TR><TD ALIGN=center><STRONG>Data Type</STRONG></TD>
<TD ALIGN=center><STRONG>Alignment Requirement</STRONG></TD></TR>
<TR><TD ALIGN=center>byte</TD>
<TD ALIGN=center>1</TD></TR>
<TR><TD ALIGN=center>half-word</TD>
<TD ALIGN=center>2</TD></TR>
<TR><TD ALIGN=center>word</TD>
<TD ALIGN=center>4</TD></TR>
<TR><TD ALIGN=center>doubleword</TD>
<TD ALIGN=center>8</TD></TR>
</TABLE>
</CENTER>
@end html
@end ifset
 
Doubleword load and store operations are only available in
PowerPC CPU models which are sixty-four bit implementations.
 
RTEMS does not directly support any PowerPC Memory Management
Units, therefore, virtual memory or segmentation systems
involving the PowerPC are not supported.
 
/cputable.t
0,0 → 1,155
@c
@c COPYRIGHT (c) 1988-2002.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c cputable.t,v 1.12 2002/01/17 21:47:46 joel Exp
@c
 
@chapter Processor Dependent Information Table
 
@section Introduction
 
Any highly processor dependent information required
to describe a processor to RTEMS is provided in the CPU
Dependent Information Table. This table is not required for all
processors supported by RTEMS. This chapter describes the
contents, if any, for a particular processor type.
 
@section CPU Dependent Information Table
 
The PowerPC version of the RTEMS CPU Dependent
Information Table is given by the C structure definition is
shown below:
 
@example
typedef struct @{
void (*pretasking_hook)( void );
void (*predriver_hook)( void );
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
unsigned32 idle_task_stack_size;
unsigned32 interrupt_stack_size;
unsigned32 extra_mpci_receive_server_stack;
void * (*stack_allocate_hook)( unsigned32 );
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
 
unsigned32 clicks_per_usec; /* Timer clicks per microsecond */
void (*spurious_handler)(
unsigned32 vector, CPU_Interrupt_frame *);
boolean exceptions_in_RAM; /* TRUE if in RAM */
 
#if defined(ppc403)
unsigned32 serial_per_sec; /* Serial clocks per second */
boolean serial_external_clock;
boolean serial_xon_xoff;
boolean serial_cts_rts;
unsigned32 serial_rate;
unsigned32 timer_average_overhead; /* in ticks */
unsigned32 timer_least_valid; /* Least valid number from timer */
#endif
@};
@end example
 
@table @code
@item pretasking_hook
is the address of the user provided routine which is invoked
once RTEMS APIs are initialized. This routine will be invoked
before any system tasks are created. Interrupts are disabled.
This field may be NULL to indicate that the hook is not utilized.
 
@item predriver_hook
is the address of the user provided
routine that is invoked immediately before the
the device drivers and MPCI are initialized. RTEMS
initialization is complete but interrupts and tasking are disabled.
This field may be NULL to indicate that the hook is not utilized.
 
@item postdriver_hook
is the address of the user provided
routine that is invoked immediately after the
the device drivers and MPCI are initialized. RTEMS
initialization is complete but interrupts and tasking are disabled.
This field may be NULL to indicate that the hook is not utilized.
 
@item idle_task
is the address of the optional user
provided routine which is used as the system's IDLE task. If
this field is not NULL, then the RTEMS default IDLE task is not
used. This field may be NULL to indicate that the default IDLE
is to be used.
 
@item do_zero_of_workspace
indicates whether RTEMS should
zero the Workspace as part of its initialization. If set to
TRUE, the Workspace is zeroed. Otherwise, it is not.
 
@item idle_task_stack_size
is the size of the RTEMS idle task stack in bytes.
If this number is less than MINIMUM_STACK_SIZE, then the
idle task's stack will be MINIMUM_STACK_SIZE in byte.
 
@item interrupt_stack_size
is the size of the RTEMS allocated interrupt stack in bytes.
This value must be at least as large as MINIMUM_STACK_SIZE.
 
@item extra_mpci_receive_server_stack
is the extra stack space allocated for the RTEMS MPCI receive server task
in bytes. The MPCI receive server may invoke nearly all directives and
may require extra stack space on some targets.
 
@item stack_allocate_hook
is the address of the optional user provided routine which allocates
memory for task stacks. If this hook is not NULL, then a stack_free_hook
must be provided as well.
 
@item stack_free_hook
is the address of the optional user provided routine which frees
memory for task stacks. If this hook is not NULL, then a stack_allocate_hook
must be provided as well.
 
@item clicks_per_usec
is the number of decrementer interupts that occur each microsecond.
 
@item spurious_handler
is the address of the
routine which is invoked when a spurious interrupt occurs.
 
@item exceptions_in_RAM
indicates whether the exception vectors are located in RAM or ROM. If
they are located in RAM dynamic vector installation occurs, otherwise
it does not.
 
@item serial_per_sec
is a PPC403 specific field which specifies the number of clock
ticks per second for the PPC403 serial timer.
 
@item serial_rate
is a PPC403 specific field which specifies the baud rate for the
PPC403 serial port.
 
@item serial_external_clock
is a PPC403 specific field which indicates whether or not to mask in a 0x2 into
the Input/Output Configuration Register (IOCR) during initialization of the
PPC403 console. (NOTE: This bit is defined as "reserved" 6-12?)
 
@item serial_xon_xoff
is a PPC403 specific field which indicates whether or not
XON/XOFF flow control is supported for the PPC403 serial port.
 
@item serial_cts_rts
is a PPC403 specific field which indicates whether or not to set the
least significant bit of the Input/Output Configuration Register
(IOCR) during initialization of the PPC403 console. (NOTE: This
bit is defined as "reserved" 6-12?)
 
@item timer_average_overhead
is a PPC403 specific field which specifies the average number of overhead ticks that occur on the PPC403 timer.
 
@item timer_least_valid
is a PPC403 specific field which specifies the maximum valid PPC403 timer value.
 
@end table
 
/fatalerr.t
0,0 → 1,47
@c
@c COPYRIGHT (c) 1988-2002.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c fatalerr.t,v 1.7 2002/01/17 21:47:46 joel Exp
@c
 
@chapter Default Fatal Error Processing
 
@section Introduction
 
Upon detection of a fatal error by either the
application or RTEMS the fatal error manager is invoked. The
fatal error manager will invoke the user-supplied fatal error
handlers. If no user-supplied handlers are configured, the
RTEMS provided default fatal error handler is invoked. If the
user-supplied fatal error handlers return to the executive the
default fatal error handler is then invoked. This chapter
describes the precise operations of the default fatal error
handler.
 
@section Default Fatal Error Handler Operations
 
The default fatal error handler which is invoked by
the @code{rtems_fatal_error_occurred} directive when there is no user handler
configured or the user handler returns control to RTEMS. The
default fatal error handler performs the following actions:
 
@itemize @bullet
 
@item places the error code in r3, and
 
@item executes a trap instruction which results in a Program Exception.
 
@end itemize
 
If the Program Exception returns, then the following actions are performed:
 
@itemize @bullet
 
@item disables all processor exceptions by loading a 0 into the MSR, and
 
@item goes into an infinite loop to simulate a halt processor instruction.
 
@end itemize
 
/callconv.t
0,0 → 1,229
@c
@c COPYRIGHT (c) 1988-2002.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c callconv.t,v 1.8 2002/01/17 21:47:46 joel Exp
@c
 
@chapter Calling Conventions
 
@section Introduction
 
Each high-level language compiler generates
subroutine entry and exit code based upon a set of rules known
as the compiler's calling convention. These rules address the
following issues:
 
@itemize @bullet
@item register preservation and usage
 
@item parameter passing
 
@item call and return mechanism
@end itemize
 
A compiler's calling convention is of importance when
interfacing to subroutines written in another language either
assembly or high-level. Even when the high-level language and
target processor are the same, different compilers may use
different calling conventions. As a result, calling conventions
are both processor and compiler dependent.
 
RTEMS supports the Embedded Application Binary Interface (EABI)
calling convention. Documentation for EABI is available by sending
a message with a subject line of "EABI" to eabi@@goth.sis.mot.com.
 
@section Programming Model
 
This section discusses the programming model for the
PowerPC architecture.
 
@subsection Non-Floating Point Registers
 
The PowerPC architecture defines thirty-two non-floating point registers
directly visible to the programmer. In thirty-two bit implementations, each
register is thirty-two bits wide. In sixty-four bit implementations, each
register is sixty-four bits wide.
 
These registers are referred to as @code{gpr0} to @code{gpr31}.
 
Some of the registers serve defined roles in the EABI programming model.
The following table describes the role of each of these registers:
 
@ifset use-ascii
@example
@group
+---------------+----------------+------------------------------+
| Register Name | Alternate Name | Description |
+---------------+----------------+------------------------------+
| r1 | sp | stack pointer |
+---------------+----------------+------------------------------+
| | | global pointer to the Small |
| r2 | na | Constant Area (SDA2) |
+---------------+----------------+------------------------------+
| r3 - r12 | na | parameter and result passing |
+---------------+----------------+------------------------------+
| | | global pointer to the Small |
| r13 | na | Data Area (SDA) |
+---------------+----------------+------------------------------+
@end group
@end example
@end ifset
 
@ifset use-tex
@sp 1
@tex
\centerline{\vbox{\offinterlineskip\halign{
\vrule\strut#&
\hbox to 1.75in{\enskip\hfil#\hfil}&
\vrule#&
\hbox to 1.75in{\enskip\hfil#\hfil}&
\vrule#&
\hbox to 2.50in{\enskip\hfil#\hfil}&
\vrule#\cr
\noalign{\hrule}
&\bf Register Name &&\bf Alternate Names&&\bf Description&\cr\noalign{\hrule}
&r1&&sp&&stack pointer&\cr\noalign{\hrule}
&r2&&NA&&global pointer to the Small&\cr
&&&&&Constant Area (SDA2)&\cr\noalign{\hrule}
&r3 - r12&&NA&&parameter and result passing&\cr\noalign{\hrule}
&r13&&NA&&global pointer to the Small&\cr
&&&&&Data Area (SDA2)&\cr\noalign{\hrule}
}}\hfil}
@end tex
@end ifset
@ifset use-html
@html
<CENTER>
<TABLE COLS=3 WIDTH="80%" BORDER=2>
<TR><TD ALIGN=center><STRONG>Register Name</STRONG></TD>
<TD ALIGN=center><STRONG>Alternate Name</STRONG></TD>
<TD ALIGN=center><STRONG>Description</STRONG></TD></TR>
<TR><TD ALIGN=center>r1</TD>
<TD ALIGN=center>sp</TD>
<TD ALIGN=center>stack pointer</TD></TR>
<TR><TD ALIGN=center>r2</TD>
<TD ALIGN=center>na</TD>
<TD ALIGN=center>global pointer to the Small Constant Area (SDA2)</TD></TR>
<TR><TD ALIGN=center>r3 - r12</TD>
<TD ALIGN=center>NA</TD>
<TD ALIGN=center>parameter and result passing</TD></TR>
<TR><TD ALIGN=center>r13</TD>
<TD ALIGN=center>NA</TD>
<TD ALIGN=center>global pointer to the Small Data Area (SDA)</TD></TR>
</TABLE>
</CENTER>
@end html
@end ifset
 
 
@subsection Floating Point Registers
 
The PowerPC architecture includes thirty-two, sixty-four bit
floating point registers. All PowerPC floating point instructions
interpret these registers as 32 double precision floating point registers,
regardless of whether the processor has 64-bit or 32-bit implementation.
 
The floating point status and control register (fpscr) records exceptions
and the type of result generated by floating-point operations.
Additionally, it controls the rounding mode of operations and allows the
reporting of floating exceptions to be enabled or disabled.
 
@subsection Special Registers
 
The PowerPC architecture includes a number of special registers
which are critical to the programming model:
 
@table @b
 
@item Machine State Register
 
The MSR contains the processor mode, power management mode, endian mode,
exception information, privilege level, floating point available and
floating point excepiton mode, address translation information and
the exception prefix.
 
@item Link Register
 
The LR contains the return address after a function call. This register
must be saved before a subsequent subroutine call can be made. The
use of this register is discussed further in the @b{Call and Return
Mechanism} section below.
 
@item Count Register
 
The CTR contains the iteration variable for some loops. It may also be used
for indirect function calls and jumps.
 
@end table
 
@section Call and Return Mechanism
 
The PowerPC architecture supports a simple yet effective call
and return mechanism. A subroutine is invoked
via the "branch and link" (@code{bl}) and
"brank and link absolute" (@code{bla})
instructions. This instructions place the return address
in the Link Register (LR). The callee returns to the caller by
executing a "branch unconditional to the link register" (@code{blr})
instruction. Thus the callee returns to the caller via a jump
to the return address which is stored in the LR.
 
The previous contents of the LR are not automatically saved
by either the @code{bl} or @code{bla}. It is the responsibility
of the callee to save the contents of the LR before invoking
another subroutine. If the callee invokes another subroutine,
it must restore the LR before executing the @code{blr} instruction
to return to the caller.
 
It is important to note that the PowerPC subroutine
call and return mechanism does not automatically save and
restore any registers.
 
The LR may be accessed as special purpose register 8 (@code{SPR8}) using the
"move from special register" (@code{mfspr}) and
"move to special register" (@code{mtspr}) instructions.
 
@section Calling Mechanism
 
All RTEMS directives are invoked using the regular
PowerPC EABI calling convention via the @code{bl} or
@code{bla} instructions.
 
@section Register Usage
 
As discussed above, the call instruction does not
automatically save any registers. It is the responsibility
of the callee to save and restore any registers which must be preserved
across subroutine calls. The callee is responsible for saving
callee-preserved registers to the program stack and restoring them
before returning to the caller.
 
@section Parameter Passing
 
RTEMS assumes that arguments are placed in the
general purpose registers with the first argument in
register 3 (@code{r3}), the second argument in general purpose
register 4 (@code{r4}), and so forth until the seventh
argument is in general purpose register 10 (@code{r10}).
If there are more than seven arguments, then subsequent arguments
are placed on the program stack. The following pseudo-code
illustrates the typical sequence used to call a RTEMS directive
with three (3) arguments:
 
@example
load third argument into r5
load second argument into r4
load first argument into r3
invoke directive
@end example
 
@section User-Provided Routines
 
All user-provided routines invoked by RTEMS, such as
user extensions, device drivers, and MPCI routines, must also
adhere to these same calling conventions.
 
 
/timeDMV177.t
0,0 → 1,113
@c
@c Timing information for the DMV177
@c
@c COPYRIGHT (c) 1988-2002.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c timeDMV177.t,v 1.7 2002/01/17 21:47:46 joel Exp
@c
 
@include common/timemac.texi
@tex
\global\advance \smallskipamount by -4pt
@end tex
 
@chapter RTEMS_BSP Timing Data
 
@section Introduction
 
The timing data for RTEMS on the DY-4 RTEMS_BSP board
is provided along with the target
dependent aspects concerning the gathering of the timing data.
The hardware platform used to gather the times is described to
give the reader a better understanding of each directive time
provided. Also, provided is a description of the interrupt
latency and the context switch times as they pertain to the
PowerPC version of RTEMS.
 
@section Hardware Platform
 
All times reported in this chapter were measured using a RTEMS_BSP board.
All data and code caching was disabled. This results in very deterministic
times which represent the worst possible performance. Many embedded
applications disable caching to insure that execution times are
repeatable. Moreover, the JTAG port on certain revisions of the PowerPC
603e does not operate properly if caching is enabled. Thus during
development and debug, caching must be off.
 
The PowerPC decrementer register was was used to gather
all timing information. In the PowerPC architecture,
this register typically counts
something like CPU cycles or is a function of the clock
speed. On the PPC603e decrements once for every four (4) bus cycles.
On the RTEMS_BSP, the bus operates at a clock speed of
33 Mhz. This result in a very accurate number since it is a function of the
microprocessor itself. Thus all measurements in this
chapter are reported as the actual number of decrementer
clicks reported.
 
To convert the numbers reported to microseconds, one should
divide the number reported by 8.650752. This number was derived as
shown below:
 
@example
((33 * 1048576) / 1000000) / 4 = 8.650752
@end example
 
All sources of hardware interrupts were disabled,
although traps were enabled and the interrupt level of the
PowerPC allows all interrupts.
 
@section Interrupt Latency
 
The maximum period with traps disabled or the
processor interrupt level set to it's highest value inside RTEMS
is less than RTEMS_MAXIMUM_DISABLE_PERIOD
microseconds including the instructions which
disable and re-enable interrupts. The time required for the
PowerPC to vector an interrupt and for the RTEMS entry overhead
before invoking the user's trap handler are a total of
RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
microseconds. These combine to yield a worst case interrupt
latency of less than RTEMS_MAXIMUM_DISABLE_PERIOD +
RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK microseconds at
RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz.
[NOTE: The maximum period with interrupts disabled was last
determined for Release RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
 
The maximum period with interrupts disabled within
RTEMS is hand-timed with some assistance from the PowerPC simulator.
The maximum period with interrupts disabled with RTEMS has not
been calculated on this target.
 
The interrupt vector and entry overhead time was
generated on the PSIM benchmark platform using the PowerPC's
decrementer register. This register was programmed to generate
an interrupt after one countdown.
 
@section Context Switch
 
The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS
bus cycle on the RTEMS_BSP benchmark platform when no floating
point context is saved or restored. Additional execution time
is required when a TASK_SWITCH user extension is configured.
The use of the TASK_SWITCH extension is application dependent.
Thus, its execution time is not considered part of the raw
context switch time.
 
Since RTEMS was designed specifically for embedded
missile applications which are floating point intensive, the
executive is optimized to avoid unnecessarily saving and
restoring the state of the numeric coprocessor. The state of
the numeric coprocessor is only saved when an FLOATING_POINT
task is dispatched and that task was not the last task to
utilize the coprocessor. In a system with only one
FLOATING_POINT task, the state of the numeric coprocessor will
never be saved or restored. When the first FLOATING_POINT task
is dispatched, RTEMS does not need to save the current state of
the numeric coprocessor.
 
The following table summarizes the context switch
times for the RTEMS_BSP benchmark platform:
 
/PSIM_TIMES
0,0 → 1,248
#
# PowerPC/603e/PSIM Timing and Size Information
#
# PSIM_TIMES,v 1.4 2002/01/17 21:47:46 joel Exp
#
 
#
# CPU Model Information
#
RTEMS_BSP PSIM
RTEMS_CPU_MODEL PPC603e
#
# Interrupt Latency
#
# NOTE: In general, the text says it is hand-calculated to be
# RTEMS_MAXIMUM_DISABLE_PERIOD at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
# Mhz and this was last calculated for Release
# RTEMS_VERSION_FOR_MAXIMUM_DISABLE_PERIOD.
#
RTEMS_MAXIMUM_DISABLE_PERIOD TBD
RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ na
RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD 4.0.0-lmco
#
# Context Switch Times
#
RTEMS_NO_FP_CONTEXTS 214
RTEMS_RESTORE_1ST_FP_TASK 255
RTEMS_SAVE_INIT_RESTORE_INIT 140
RTEMS_SAVE_IDLE_RESTORE_INIT 140
RTEMS_SAVE_IDLE_RESTORE_IDLE 290
#
# Task Manager Times
#
RTEMS_TASK_CREATE_ONLY 1075
RTEMS_TASK_IDENT_ONLY 1637
RTEMS_TASK_START_ONLY 345
RTEMS_TASK_RESTART_CALLING_TASK 483
RTEMS_TASK_RESTART_SUSPENDED_RETURNS_TO_CALLER 396
RTEMS_TASK_RESTART_BLOCKED_RETURNS_TO_CALLER 491
RTEMS_TASK_RESTART_READY_RETURNS_TO_CALLER 404
RTEMS_TASK_RESTART_SUSPENDED_PREEMPTS_CALLER 644
RTEMS_TASK_RESTART_BLOCKED_PREEMPTS_CALLER 709
RTEMS_TASK_RESTART_READY_PREEMPTS_CALLER 686
RTEMS_TASK_DELETE_CALLING_TASK 941
RTEMS_TASK_DELETE_SUSPENDED_TASK 703
RTEMS_TASK_DELETE_BLOCKED_TASK 723
RTEMS_TASK_DELETE_READY_TASK 729
RTEMS_TASK_SUSPEND_CALLING_TASK 403
RTEMS_TASK_SUSPEND_RETURNS_TO_CALLER 181
RTEMS_TASK_RESUME_TASK_READIED_RETURNS_TO_CALLER 191
RTEMS_TASK_RESUME_TASK_READIED_PREEMPTS_CALLER 803
RTEMS_TASK_SET_PRIORITY_OBTAIN_CURRENT_PRIORITY 147
RTEMS_TASK_SET_PRIORITY_RETURNS_TO_CALLER 264
RTEMS_TASK_SET_PRIORITY_PREEMPTS_CALLER 517
RTEMS_TASK_MODE_OBTAIN_CURRENT_MODE 88
RTEMS_TASK_MODE_NO_RESCHEDULE 110
RTEMS_TASK_MODE_RESCHEDULE_RETURNS_TO_CALLER 112
RTEMS_TASK_MODE_RESCHEDULE_PREEMPTS_CALLER 386
RTEMS_TASK_GET_NOTE_ONLY 156
RTEMS_TASK_SET_NOTE_ONLY 155
RTEMS_TASK_WAKE_AFTER_YIELD_RETURNS_TO_CALLER 92
RTEMS_TASK_WAKE_AFTER_YIELD_PREEMPTS_CALLER 348
RTEMS_TASK_WAKE_WHEN_ONLY 546
#
# Interrupt Manager
#
RTEMS_INTR_ENTRY_RETURNS_TO_NESTED 60
RTEMS_INTR_ENTRY_RETURNS_TO_INTERRUPTED_TASK 62
RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK 61
RTEMS_INTR_EXIT_RETURNS_TO_NESTED 55
RTEMS_INTR_EXIT_RETURNS_TO_INTERRUPTED_TASK 67
RTEMS_INTR_EXIT_RETURNS_TO_PREEMPTING_TASK 344
#
# Clock Manager
#
RTEMS_CLOCK_SET_ONLY 340
RTEMS_CLOCK_GET_ONLY 29
RTEMS_CLOCK_TICK_ONLY 81
#
# Timer Manager
#
RTEMS_TIMER_CREATE_ONLY 144
RTEMS_TIMER_IDENT_ONLY 1595
RTEMS_TIMER_DELETE_INACTIVE 197
RTEMS_TIMER_DELETE_ACTIVE 181
RTEMS_TIMER_FIRE_AFTER_INACTIVE 252
RTEMS_TIMER_FIRE_AFTER_ACTIVE 269
RTEMS_TIMER_FIRE_WHEN_INACTIVE 333
RTEMS_TIMER_FIRE_WHEN_ACTIVE 334
RTEMS_TIMER_RESET_INACTIVE 233
RTEMS_TIMER_RESET_ACTIVE 250
RTEMS_TIMER_CANCEL_INACTIVE 156
RTEMS_TIMER_CANCEL_ACTIVE 140
#
# Semaphore Manager
#
RTEMS_SEMAPHORE_CREATE_ONLY 223
RTEMS_SEMAPHORE_IDENT_ONLY 1836
RTEMS_SEMAPHORE_DELETE_ONLY 1836
RTEMS_SEMAPHORE_OBTAIN_AVAILABLE 175
RTEMS_SEMAPHORE_OBTAIN_NOT_AVAILABLE_NO_WAIT 175
RTEMS_SEMAPHORE_OBTAIN_NOT_AVAILABLE_CALLER_BLOCKS 530
RTEMS_SEMAPHORE_RELEASE_NO_WAITING_TASKS 206
RTEMS_SEMAPHORE_RELEASE_TASK_READIED_RETURNS_TO_CALLER 272
RTEMS_SEMAPHORE_RELEASE_TASK_READIED_PREEMPTS_CALLER 415
#
# Message Manager
#
RTEMS_MESSAGE_QUEUE_CREATE_ONLY 1022
RTEMS_MESSAGE_QUEUE_IDENT_ONLY 1596
RTEMS_MESSAGE_QUEUE_DELETE_ONLY 308
RTEMS_MESSAGE_QUEUE_SEND_NO_WAITING_TASKS 421
RTEMS_MESSAGE_QUEUE_SEND_TASK_READIED_RETURNS_TO_CALLER 434
RTEMS_MESSAGE_QUEUE_SEND_TASK_READIED_PREEMPTS_CALLER 581
RTEMS_MESSAGE_QUEUE_URGENT_NO_WAITING_TASKS 422
RTEMS_MESSAGE_QUEUE_URGENT_TASK_READIED_RETURNS_TO_CALLER 435
RTEMS_MESSAGE_QUEUE_URGENT_TASK_READIED_PREEMPTS_CALLER 582
RTEMS_MESSAGE_QUEUE_BROADCAST_NO_WAITING_TASKS 244
RTEMS_MESSAGE_QUEUE_BROADCAST_TASK_READIED_RETURNS_TO_CALLER 482
RTEMS_MESSAGE_QUEUE_BROADCAST_TASK_READIED_PREEMPTS_CALLER 630
RTEMS_MESSAGE_QUEUE_RECEIVE_AVAILABLE 345
RTEMS_MESSAGE_QUEUE_RECEIVE_NOT_AVAILABLE_NO_WAIT 197
RTEMS_MESSAGE_QUEUE_RECEIVE_NOT_AVAILABLE_CALLER_BLOCKS 542
RTEMS_MESSAGE_QUEUE_FLUSH_NO_MESSAGES_FLUSHED 142
RTEMS_MESSAGE_QUEUE_FLUSH_MESSAGES_FLUSHED 170
#
# Event Manager
#
RTEMS_EVENT_SEND_NO_TASK_READIED 145
RTEMS_EVENT_SEND_TASK_READIED_RETURNS_TO_CALLER 250
RTEMS_EVENT_SEND_TASK_READIED_PREEMPTS_CALLER 407
RTEMS_EVENT_RECEIVE_OBTAIN_CURRENT_EVENTS 17
RTEMS_EVENT_RECEIVE_AVAILABLE 133
RTEMS_EVENT_RECEIVE_NOT_AVAILABLE_NO_WAIT 130
RTEMS_EVENT_RECEIVE_NOT_AVAILABLE_CALLER_BLOCKS 442
#
# Signal Manager
#
RTEMS_SIGNAL_CATCH_ONLY 95
RTEMS_SIGNAL_SEND_RETURNS_TO_CALLER 165
RTEMS_SIGNAL_SEND_SIGNAL_TO_SELF 275
RTEMS_SIGNAL_EXIT_ASR_OVERHEAD_RETURNS_TO_CALLING_TASK 216
RTEMS_SIGNAL_EXIT_ASR_OVERHEAD_RETURNS_TO_PREEMPTING_TASK 329
#
# Partition Manager
#
RTEMS_PARTITION_CREATE_ONLY 320
RTEMS_PARTITION_IDENT_ONLY 1596
RTEMS_PARTITION_DELETE_ONLY 168
RTEMS_PARTITION_GET_BUFFER_AVAILABLE 157
RTEMS_PARTITION_GET_BUFFER_NOT_AVAILABLE 149
RTEMS_PARTITION_RETURN_BUFFER_ONLY 172
#
# Region Manager
#
RTEMS_REGION_CREATE_ONLY 239
RTEMS_REGION_IDENT_ONLY 1625
RTEMS_REGION_DELETE_ONLY 167
RTEMS_REGION_GET_SEGMENT_AVAILABLE 206
RTEMS_REGION_GET_SEGMENT_NOT_AVAILABLE_NO_WAIT 190
RTEMS_REGION_GET_SEGMENT_NOT_AVAILABLE_CALLER_BLOCKS 556
RTEMS_REGION_RETURN_SEGMENT_NO_WAITING_TASKS 230
RTEMS_REGION_RETURN_SEGMENT_TASK_READIED_RETURNS_TO_CALLER 412
RTEMS_REGION_RETURN_SEGMENT_TASK_READIED_PREEMPTS_CALLER 562
#
# Dual-Ported Memory Manager
#
RTEMS_PORT_CREATE_ONLY 167
RTEMS_PORT_IDENT_ONLY 1594
RTEMS_PORT_DELETE_ONLY 165
RTEMS_PORT_INTERNAL_TO_EXTERNAL_ONLY 133
RTEMS_PORT_EXTERNAL_TO_INTERNAL_ONLY 134
#
# IO Manager
#
RTEMS_IO_INITIALIZE_ONLY 23
RTEMS_IO_OPEN_ONLY 18
RTEMS_IO_CLOSE_ONLY 18
RTEMS_IO_READ_ONLY 18
RTEMS_IO_WRITE_ONLY 18
RTEMS_IO_CONTROL_ONLY 18
#
# Rate Monotonic Manager
#
RTEMS_RATE_MONOTONIC_CREATE_ONLY 149
RTEMS_RATE_MONOTONIC_IDENT_ONLY 1595
RTEMS_RATE_MONOTONIC_CANCEL_ONLY 169
RTEMS_RATE_MONOTONIC_DELETE_ACTIVE 212
RTEMS_RATE_MONOTONIC_DELETE_INACTIVE 186
RTEMS_RATE_MONOTONIC_PERIOD_INITIATE_PERIOD_RETURNS_TO_CALLER 226
RTEMS_RATE_MONOTONIC_PERIOD_CONCLUDE_PERIOD_CALLER_BLOCKS 362
RTEMS_RATE_MONOTONIC_PERIOD_OBTAIN_STATUS 142
#
# Size Information
#
#
# xxx alloted for numbers
#
RTEMS_DATA_SPACE 428
RTEMS_MINIMUM_CONFIGURATION 30,912
RTEMS_MAXIMUM_CONFIGURATION 55,572
# x,xxx alloted for numbers
RTEMS_CORE_CODE_SIZE 21,452
RTEMS_INITIALIZATION_CODE_SIZE 1,408
RTEMS_TASK_CODE_SIZE 4,804
RTEMS_INTERRUPT_CODE_SIZE 96
RTEMS_CLOCK_CODE_SIZE 536
RTEMS_TIMER_CODE_SIZE 1,380
RTEMS_SEMAPHORE_CODE_SIZE 1,928
RTEMS_MESSAGE_CODE_SIZE 2,400
RTEMS_EVENT_CODE_SIZE 1,460
RTEMS_SIGNAL_CODE_SIZE 576
RTEMS_PARTITION_CODE_SIZE 1,384
RTEMS_REGION_CODE_SIZE 1,780
RTEMS_DPMEM_CODE_SIZE 928
RTEMS_IO_CODE_SIZE 1,244
RTEMS_FATAL_ERROR_CODE_SIZE 44
RTEMS_RATE_MONOTONIC_CODE_SIZE 1,756
RTEMS_MULTIPROCESSING_CODE_SIZE 11,448
# xxx alloted for numbers
RTEMS_TIMER_CODE_OPTSIZE 340
RTEMS_SEMAPHORE_CODE_OPTSIZE 308
RTEMS_MESSAGE_CODE_OPTSIZE 532
RTEMS_EVENT_CODE_OPTSIZE 100
RTEMS_SIGNAL_CODE_OPTSIZE 100
RTEMS_PARTITION_CODE_OPTSIZE 244
RTEMS_REGION_CODE_OPTSIZE 292
RTEMS_DPMEM_CODE_OPTSIZE 244
RTEMS_IO_CODE_OPTSIZE NA
RTEMS_RATE_MONOTONIC_CODE_OPTSIZE 336
RTEMS_MULTIPROCESSING_CODE_OPTSIZE 612
# xxx alloted for numbers
RTEMS_BYTES_PER_TASK 456
RTEMS_BYTES_PER_TIMER 68
RTEMS_BYTES_PER_SEMAPHORE 120
RTEMS_BYTES_PER_MESSAGE_QUEUE 144
RTEMS_BYTES_PER_REGION 140
RTEMS_BYTES_PER_PARTITION 56
RTEMS_BYTES_PER_PORT 36
RTEMS_BYTES_PER_PERIOD 36
RTEMS_BYTES_PER_EXTENSION 64
RTEMS_BYTES_PER_FP_TASK 264
RTEMS_BYTES_PER_NODE 48
RTEMS_BYTES_PER_GLOBAL_OBJECT 20
RTEMS_BYTES_PER_PROXY 124
# x,xxx alloted for numbers
RTEMS_BYTES_OF_FIXED_SYSTEM_REQUIREMENTS 10,008
 
/Makefile.am
0,0 → 1,124
#
# COPYRIGHT (c) 1988-2002.
# On-Line Applications Research Corporation (OAR).
# All rights reserved.
#
# Makefile.am,v 1.7 2002/03/28 00:53:55 joel Exp
#
 
 
PROJECT = powerpc
EDITION = 1
 
include $(top_srcdir)/project.am
include $(top_srcdir)/supplements/supplement.am
 
GENERATED_FILES = cpumodel.texi callconv.texi memmodel.texi intr.texi \
fatalerr.texi bsp.texi cputable.texi timing.texi wksheets.texi \
timePSIM.texi timeDMV177.texi
COMMON_FILES = $(top_srcdir)/common/setup.texi \
$(top_srcdir)/common/cpright.texi $(top_srcdir)/common/timemac.texi
 
FILES = preface.texi
 
info_TEXINFOS = powerpc.texi
powerpc_TEXINFOS = $(FILES) $(COMMON_FILES) $(GENERATED_FILES)
 
#
# Chapters which get automatic processing
#
 
$(srcdir)/cpumodel.texi: cpumodel.t
$(BMENU2) -p "Preface" \
-u "Top" \
-n "Calling Conventions" < $< > $@
 
$(srcdir)/callconv.texi: callconv.t
$(BMENU2) -p "CPU Model Dependent Features Low Power Model" \
-u "Top" \
-n "Memory Model" < $< > $@
 
$(srcdir)/memmodel.texi: memmodel.t
$(BMENU2) -p "Calling Conventions User-Provided Routines" \
-u "Top" \
-n "Interrupt Processing" < $< > $@
 
# Interrupt Chapter:
# 1. Replace Times and Sizes
# 2. Build Node Structure
$(srcdir)/intr.texi: intr_NOTIMES.t PSIM_TIMES
${REPLACE2} -p $(srcdir)/PSIM_TIMES $(srcdir)/intr_NOTIMES.t | \
$(BMENU2) -p "Memory Model Flat Memory Model" \
-u "Top" \
-n "Default Fatal Error Processing" > $@
 
$(srcdir)/fatalerr.texi: fatalerr.t
$(BMENU2) -p "Interrupt Processing Interrupt Stack" \
-u "Top" \
-n "Board Support Packages" < $< > $@
 
$(srcdir)/bsp.texi: bsp.t
$(BMENU2) -p "Default Fatal Error Processing Default Fatal Error Handler Operations" \
-u "Top" \
-n "Processor Dependent Information Table" < $< > $@
 
$(srcdir)/cputable.texi: cputable.t
$(BMENU2) -p "Board Support Packages Processor Initialization" \
-u "Top" \
-n "Memory Requirements" < $< > $@
 
# Worksheets Chapter:
# 1. Obtain the Shared File
# 2. Replace Times and Sizes
# 3. Build Node Structure
 
$(srcdir)/wksheets.texi: $(top_srcdir)/common/wksheets.t PSIM_TIMES
${REPLACE2} -p $(srcdir)/PSIM_TIMES \
$(top_srcdir)/common/wksheets.t | \
$(BMENU2) -p "Processor Dependent Information Table CPU Dependent Information Table" \
-u "Top" \
-n "Timing Specification" > $@
 
# Timing Specification Chapter:
# 1. Copy the Shared File
# 3. Build Node Structure
$(srcdir)/timing.texi: $(top_srcdir)/common/timing.t
$(BMENU2) -p "Memory Requirements RTEMS RAM Workspace Worksheet" \
-u "Top" \
-n "PSIM Timing Data" < $< > $@
 
# Timing Data for PSIM BSP Chapter:
# 1. Copy the Shared File
# 2. Replace Times and Sizes
# 3. Build Node Structure
 
$(srcdir)/timePSIM.texi: $(top_srcdir)/common/timetbl.t timePSIM.t
cat $(srcdir)/timePSIM.t $(top_srcdir)/common/timetbl.t >timePSIM_.t
@echo >>timePSIM_.t
@echo "@tex" >>timePSIM_.t
@echo "\\global\\advance \\smallskipamount by 4pt" >>timePSIM_.t
@echo "@end tex" >>timePSIM_.t
${REPLACE2} -p $(srcdir)/PSIM_TIMES timePSIM_.t | \
$(BMENU2) -p "Timing Specification Terminology" \
-u "Top" \
-n "DMV177 Timing Data" > $@
CLEANFILES += timePSIM_.t timeDMV177_.t
 
# Timing Data for DMV177 BSP Chapter:
# 1. Copy the Shared File
# 2. Replace Times and Sizes
# 3. Build Node Structure
 
$(srcdir)/timeDMV177.texi: $(top_srcdir)/common/timetbl.t timeDMV177.t
cat $(srcdir)/timeDMV177.t $(top_srcdir)/common/timetbl.t >timeDMV177_.t
@echo >>timeDMV177_.t
@echo "@tex" >>timeDMV177_.t
@echo "\\global\\advance \\smallskipamount by 4pt" >>timeDMV177_.t
@echo "@end tex" >>timeDMV177_.t
${REPLACE2} -p $(srcdir)/DMV177_TIMES timeDMV177_.t | \
$(BMENU2) -p "PSIM Timing Data Rate Monotonic Manager" \
-u "Top" \
-n "Command and Variable Index" > $@
 
EXTRA_DIST = DMV177_TIMES PSIM_TIMES bsp.t callconv.t cpumodel.t cputable.t \
fatalerr.t intr_NOTIMES.t memmodel.t timeDMV177.t timePSIM.t
/cpumodel.t
0,0 → 1,156
@c
@c COPYRIGHT (c) 1988-2002.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c cpumodel.t,v 1.7 2002/01/17 21:47:46 joel Exp
@c
 
@chapter CPU Model Dependent Features
 
@section Introduction
 
Microprocessors are generally classified into
families with a variety of CPU models or implementations within
that family. Within a processor family, there is a high level
of binary compatibility. This family may be based on either an
architectural specification or on maintaining compatibility with
a popular processor. Recent microprocessor families such as the
PowerPC, SPARC, and PA-RISC are based on an architectural specification
which is independent or any particular CPU model or
implementation. Older families such as the M68xxx and the iX86
evolved as the manufacturer strived to produce higher
performance processor models which maintained binary
compatibility with older models.
 
RTEMS takes advantage of the similarity of the
various models within a CPU family. Although the models do vary
in significant ways, the high level of compatibility makes it
possible to share the bulk of the CPU dependent executive code
across the entire family.
 
@section CPU Model Feature Flags
 
Each processor family supported by RTEMS has a
list of features which vary between CPU models
within a family. For example, the most common model dependent
feature regardless of CPU family is the presence or absence of a
floating point unit or coprocessor. When defining the list of
features present on a particular CPU model, one simply notes
that floating point hardware is or is not present and defines a
single constant appropriately. Conditional compilation is
utilized to include the appropriate source code for this CPU
model's feature set. It is important to note that this means
that RTEMS is thus compiled using the appropriate feature set
and compilation flags optimal for this CPU model used. The
alternative would be to generate a binary which would execute on
all family members using only the features which were always
present.
 
This section presents the set of features which vary
across PowerPC implementations and are of importance to RTEMS.
The set of CPU model feature macros are defined in the file
c/src/exec/score/cpu/ppc/ppc.h based upon the particular CPU
model defined on the compilation command line.
 
@subsection CPU Model Name
 
The macro CPU_MODEL_NAME is a string which designates
the name of this CPU model. For example, for the PowerPC 603e
model, this macro is set to the string "PowerPC 603e".
 
@subsection Floating Point Unit
 
The macro PPC_HAS_FPU is set to 1 to indicate that this CPU model
has a hardware floating point unit and 0 otherwise.
 
@subsection Alignment
 
The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment
requirement for data types on a byte boundary. This value is used
to derive the alignment restrictions for memory allocated from
regions and partitions.
 
@subsection Cache Alignment
 
The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache. It is
used to align the entry point of critical routines so that as much code
as possible can be retrieved with the initial read into cache. This
is done for the interrupt handler as well as the context switch routines.
 
In addition, the "shortcut" data structure used by the PowerPC implementation
to ease access to data elements frequently accessed by RTEMS routines
implemented in assembly language is aligned using this value.
 
@subsection Maximum Interrupts
 
The macro PPC_INTERRUPT_MAX is set to the number of exception sources
supported by this PowerPC model.
 
@subsection Has Double Precision Floating Point
 
The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model
has support for double precision floating point numbers. This is
important because the floating point registers need only be four bytes
wide (not eight) if double precision is not supported.
 
@subsection Critical Interrupts
 
The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model
has the Critical Interrupt capability as defined by the IBM 403 models.
 
@subsection Use Multiword Load/Store Instructions
 
The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and
store instructions should be used to perform context switch operations.
The relative efficiency of multiword load and store instructions versus
an equivalent set of single word load and store instructions varies based
upon the PowerPC model.
 
@subsection Instruction Cache Size
 
The macro PPC_I_CACHE is set to the size in bytes of the instruction cache.
 
@subsection Data Cache Size
 
The macro PPC_D_CACHE is set to the size in bytes of the data cache.
 
@subsection Debug Model
 
The macro PPC_DEBUG_MODEL is set to indicate the debug support features
present in this CPU model. The following debug support feature sets
are currently supported:
 
@table @b
 
@item @code{PPC_DEBUG_MODEL_STANDARD}
indicates that the single-step trace enable (SE) and branch trace
enable (BE) bits in the MSR are supported by this CPU model.
 
@item @code{PPC_DEBUG_MODEL_SINGLE_STEP_ONLY}
indicates that only the single-step trace enable (SE) bit in the MSR
is supported by this CPU model.
 
@item @code{PPC_DEBUG_MODEL_IBM4xx}
indicates that the debug exception enable (DE) bit in the MSR is supported
by this CPU model. At this time, this particular debug feature set
has only been seen in the IBM 4xx series.
 
@end table
 
@subsection Low Power Model
 
The macro PPC_LOW_POWER_MODE is set to indicate the low power model
supported by this CPU model. The following low power modes are currently
supported.
 
@table @b
 
@item @code{PPC_LOW_POWER_MODE_NONE}
indicates that this CPU model has no low power mode support.
 
@item @code{PPC_LOW_POWER_MODE_STANDARD}
indicates that this CPU model follows the low power model defined for
the PPC603e.
 
@end table
/intr_NOTIMES.t
0,0 → 1,184
@c
@c COPYRIGHT (c) 1988-2002.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c intr_NOTIMES.t,v 1.7 2002/01/17 21:47:46 joel Exp
@c
 
@chapter Interrupt Processing
 
@section Introduction
 
Different types of processors respond to the
occurrence of an interrupt in its own unique fashion. In
addition, each processor type provides a control mechanism to
allow for the proper handling of an interrupt. The processor
dependent response to the interrupt modifies the current
execution state and results in a change in the execution stream.
Most processors require that an interrupt handler utilize some
special control mechanisms to return to the normal processing
stream. Although RTEMS hides many of the processor dependent
details of interrupt processing, it is important to understand
how the RTEMS interrupt manager is mapped onto the processor's
unique architecture. Discussed in this chapter are the PowerPC's
interrupt response and control mechanisms as they pertain to
RTEMS.
 
RTEMS and associated documentation uses the terms
interrupt and vector. In the PowerPC architecture, these terms
correspond to exception and exception handler, respectively. The terms will
be used interchangeably in this manual.
 
@section Synchronous Versus Asynchronous Exceptions
 
In the PowerPC architecture exceptions can be either precise or
imprecise and either synchronous or asynchronous. Asynchronous
exceptions occur when an external event interrupts the processor.
Synchronous exceptions are caused by the actions of an
instruction. During an exception SRR0 is used to calculate where
instruction processing should resume. All instructions prior to
the resume instruction will have completed execution. SRR1 is used to
store the machine status.
 
There are two asynchronous nonmaskable, highest-priority exceptions
system reset and machine check. There are two asynchrononous maskable
low-priority exceptions external interrupt and decrementer. Nonmaskable
execptions are never delayed, therefore if two nonmaskable, asynchronous
exceptions occur in immediate succession, the state information saved by
the first exception may be overwritten when the subsequent exception occurs.
 
The PowerPC arcitecure defines one imprecise exception, the imprecise
floating point enabled exception. All other synchronous exceptions are
precise. The synchronization occuring during asynchronous precise
exceptions conforms to the requirements for context synchronization.
 
@section Vectoring of Interrupt Handler
 
Upon determining that an exception can be taken the PowerPC automatically
performs the following actions:
 
@itemize @bullet
@item an instruction address is loaded into SRR0
 
@item bits 33-36 and 42-47 of SRR1 are loaded with information
specific to the exception.
 
@item bits 0-32, 37-41, and 48-63 of SRR1 are loaded with corresponding
bits from the MSR.
 
@item the MSR is set based upon the exception type.
 
@item instruction fetch and execution resumes, using the new MSR value, at a location specific to the execption type.
 
@end itemize
 
If the interrupt handler was installed as an RTEMS
interrupt handler, then upon receipt of the interrupt, the
processor passes control to the RTEMS interrupt handler which
performs the following actions:
 
@itemize @bullet
@item saves the state of the interrupted task on it's stack,
 
@item saves all registers which are not normally preserved
by the calling sequence so the user's interrupt service
routine can be written in a high-level language.
 
@item if this is the outermost (i.e. non-nested) interrupt,
then the RTEMS interrupt handler switches from the current stack
to the interrupt stack,
 
@item enables exceptions,
 
@item invokes the vectors to a user interrupt service routine (ISR).
@end itemize
 
Asynchronous interrupts are ignored while exceptions are
disabled. Synchronous interrupts which occur while are
disabled result in the CPU being forced into an error mode.
 
A nested interrupt is processed similarly with the
exception that the current stack need not be switched to the
interrupt stack.
 
@section Interrupt Levels
 
The PowerPC architecture supports only a single external
asynchronous interrupt source. This interrupt source
may be enabled and disabled via the External Interrupt Enable (EE)
bit in the Machine State Register (MSR). Thus only two level (enabled
and disabled) of external device interrupt priorities are
directly supported by the PowerPC architecture.
 
Some PowerPC implementations include a Critical Interrupt capability
which is often used to receive interrupts from high priority external
devices.
 
The RTEMS interrupt level mapping scheme for the PowerPC is not
a numeric level as on most RTEMS ports. It is a bit mapping in
which the least three significiant bits of the interrupt level
are mapped directly to the enabling of specific interrupt
sources as follows:
 
@table @b
 
@item Critical Interrupt
Setting bit 0 (the least significant bit) of the interrupt level
enables the Critical Interrupt source, if it is available on this
CPU model.
 
@item Machine Check
Setting bit 1 of the interrupt level enables Machine Check execptions.
 
@item External Interrupt
Setting bit 2 of the interrupt level enables External Interrupt execptions.
 
@end table
 
All other bits in the RTEMS task interrupt level are ignored.
 
@section Disabling of Interrupts by RTEMS
 
During the execution of directive calls, critical
sections of code may be executed. When these sections are
encountered, RTEMS disables Critical Interrupts, External Interrupts
and Machine Checks before the execution of this section and restores
them to the previous level upon completion of the section. RTEMS has been
optimized to insure that interrupts are disabled for less than
RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a
RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz PowerPC 603e with zero
wait states. These numbers will vary based the number of wait
states and processor speed present on the target board.
[NOTE: The maximum period with interrupts disabled is hand calculated. This
calculation was last performed for Release
RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
 
If a PowerPC implementation provides non-maskable interrupts (NMI)
which cannot be disabled, ISRs which process these interrupts
MUST NEVER issue RTEMS system calls. If a directive is invoked,
unpredictable results may occur due to the inability of RTEMS
to protect its critical sections. However, ISRs that make no
system calls may safely execute as non-maskable interrupts.
 
@section Interrupt Stack
 
The PowerPC architecture does not provide for a
dedicated interrupt stack. Thus by default, exception handlers would
execute on the stack of the RTEMS task which they interrupted.
This artificially inflates the stack requirements for each task
since EVERY task stack would have to include enough space to
account for the worst case interrupt stack requirements in
addition to it's own worst case usage. RTEMS addresses this
problem on the PowerPC by providing a dedicated interrupt stack
managed by software.
 
During system initialization, RTEMS allocates the
interrupt stack from the Workspace Area. The amount of memory
allocated for the interrupt stack is determined by the
interrupt_stack_size field in the CPU Configuration Table. As
part of processing a non-nested interrupt, RTEMS will switch to
the interrupt stack before invoking the installed handler.
 
 
 
/preface.texi
0,0 → 1,94
@c
@c COPYRIGHT (c) 1988-2002.
@c On-Line Applications Research Corporation (OAR).
@c All rights reserved.
@c
@c preface.texi,v 1.5 2002/01/17 21:47:46 joel Exp
@c
 
@ifinfo
@node Preface, CPU Model Dependent Features, Top, Top
@end ifinfo
@unnumbered Preface
 
The Real Time Executive for Multiprocessor Systems
(RTEMS) is designed to be portable across multiple processor
architectures. However, the nature of real-time systems makes
it essential that the application designer understand certain
processor dependent implementation details. These processor
dependencies include calling convention, board support package
issues, interrupt processing, exact RTEMS memory requirements,
performance data, header files, and the assembly language
interface to the executive.
 
This document discusses the PowerPC architecture
dependencies in this port of RTEMS.
 
It is highly recommended that the PowerPC RTEMS
application developer obtain and become familiar with the
documentation for the processor being used as well as the
specification for the revision of the PowerPC architecture which
corresponds to that processor.
 
@subheading PowerPC Architecture Documents
 
For information on the PowerPC architecture, refer to
the following documents available from Motorola and IBM:
 
@itemize @bullet
 
@item @cite{PowerPC Microprocessor Family: The Programming Environment}
(Motorola Document MPRPPCFPE-01).
 
@item @cite{IBM PPC403GB Embedded Controller User's Manual}.
 
@item @cite{PoweRisControl MPC500 Family RCPU RISC Central Processing
Unit Reference Manual} (Motorola Document RCPUURM/AD).
 
@item @cite{PowerPC 601 RISC Microprocessor User's Manual}
(Motorola Document MPR601UM/AD).
 
@item @cite{PowerPC 603 RISC Microprocessor User's Manual}
(Motorola Document MPR603UM/AD).
 
@item @cite{PowerPC 603e RISC Microprocessor User's Manual}
(Motorola Document MPR603EUM/AD).
 
@item @cite{PowerPC 604 RISC Microprocessor User's Manual}
(Motorola Document MPR604UM/AD).
 
@item @cite{PowerPC MPC821 Portable Systems Microprocessor User's Manual}
(Motorola Document MPC821UM/AD).
 
@item @cite{PowerQUICC MPC860 User's Manual} (Motorola Document MPC860UM/AD).
 
 
@end itemize
 
Motorola maintains an on-line electronic library for the PowerPC
at the following URL:
 
@itemize @code{ }
@item @cite{http://www.mot.com/powerpc/library/library.html}
@end itemize
 
This site has a a wealth of information and examples. Many of the
manuals are available from that site in electronic format.
 
@subheading PowerPC Processor Simulator Information
 
PSIM is a program which emulates the Instruction Set Architecture
of the PowerPC microprocessor family. It is reely available in source
code form under the terms of the GNU General Public License (version
2 or later). PSIM can be integrated with the GNU Debugger (gdb) to
execute and debug PowerPC executables on non-PowerPC hosts. PSIM
supports the addition of user provided device models which can be
used to allow one to develop and debug embedded applications using
the simulator.
 
The latest version of PSIM is made available to the public via
anonymous ftp at ftp://ftp.ci.com.au/pub/psim or
ftp://cambridge.cygnus.com/pub/psim. There is also a mailing list
at powerpc-psim@@ci.com.au.
 
 
/.
. Property changes : Added: svn:ignore ## -0,0 +1,38 ## +Makefile +Makefile.in +bsp.texi +callconv.texi +cpumodel.texi +cputable.texi +fatalerr.texi +index.html +intr.t +intr.texi +mdate-sh +memmodel.texi +powerpc +powerpc*.html +powerpc-? +powerpc-?? +powerpc.aux +powerpc.cp +powerpc.dvi +powerpc.fn +powerpc.ky +powerpc.log +powerpc.pdf +powerpc.pg +powerpc.ps +powerpc.toc +powerpc.tp +powerpc.vr +timeDMV177.texi +timeDMV177_.t +timePSIM.texi +timePSIM_.t +timing.t +timing.texi +wksheets.t +wksheets.texi +rtems_header.html +rtems_footer.html

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