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  • This comparison shows the changes necessary to convert path
    /or1k/trunk/xess/xsv_cpld/syn/synplify
    from Rev 768 to Rev 1765
    Reverse comparison

Rev 768 → Rev 1765

/xsv_cpld.prd
0,0 → 1,13
#-- Synplicity, Inc.
#-- Version 7.0.3
#-- Project file G:\xess\xsv_cpld\syn\synplify\xsv_cpld.prd
#-- Written on Sat Mar 23 20:12:59 2002
 
#
### Watch Implementation type ###
#
watch_impl -active
#
### Watch Implementation properties ###
#
watch_prop -clear
xsv_cpld.prd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: xsv_cpld.prj =================================================================== --- xsv_cpld.prj (nonexistent) +++ xsv_cpld.prj (revision 1765) @@ -0,0 +1,43 @@ +#-- Synplicity, Inc. +#-- Version 7.0.3 +#-- Project file G:\xess\xsv_cpld\syn\synplify\xsv_cpld.prj +#-- Written on Sat Mar 23 20:12:59 2002 + + +#add_file options +add_file -verilog "../../rtl/verilog/tdm_master_if.v" +add_file -verilog "../../rtl/verilog/xsv_cpld_top.v" + +#reporting options + + +#implementation: "xsv_cpld_1" +impl -add xsv_cpld_1 + +#device options +set_option -technology XC9500 +set_option -part XC95108 +set_option -package TQ100 +set_option -speed_grade -20 + +#compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -resource_sharing 1 +set_option -top_module "xsv_cpld_top" + +#map options +set_option -frequency 100.000 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 + +#simulation options +set_option -write_verilog 0 +set_option -write_vhdl 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "xsv_cpld_1/xsv_cpld_top.edf" +impl -active "xsv_cpld_1"
xsv_cpld.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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