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- This comparison shows the changes necessary to convert path
/or1k/trunk/xess/xsv_cpld/syn
- from Rev 891 to Rev 1765
- ↔ Reverse comparison
Rev 891 → Rev 1765
/xilinx_pr/xsv_cpld.ucf
0,0 → 1,89
# |
# pin assignments for the XC95108 CPLD chip on the XSV Board |
# |
|
# set all the bits in the initial state of the power-on |
# counter so we get the maximum timeout interval |
#INST poweron_cnt_reg[*] INIT = S; |
|
# Virtex FPGA |
NET "V_dout" LOC = "p6"; |
NET "V_wrb" LOC = "p7"; |
NET "V_csb" LOC = "p8"; |
NET "V_initb" LOC = "p9"; |
NET "V_done" LOC = "p10"; |
NET "V_progb" LOC = "p11"; |
NET "V_cclk" LOC = "p12"; |
NET "V_m[0]" LOC = "p13"; |
NET "V_m[1]" LOC = "p14"; |
NET "V_m[2]" LOC = "p15"; |
|
# Flash RAM |
NET "resetb" LOC = "p3"; |
NET "ceb" LOC = "P46"; |
NET "oeb" LOC = "p42"; |
NET "web" LOC = "p43"; |
NET "a[0]" LOC = "p16"; |
NET "a[1]" LOC = "p17"; |
NET "a[2]" LOC = "p18"; |
NET "a[3]" LOC = "p19"; |
NET "a[4]" LOC = "p20"; |
NET "a[5]" LOC = "p23"; |
NET "a[6]" LOC = "p24"; |
NET "a[7]" LOC = "p25"; |
NET "a[8]" LOC = "p27"; |
NET "a[9]" LOC = "p28"; |
NET "a[10]" LOC = "p29"; |
NET "a[11]" LOC = "p30"; |
NET "a[12]" LOC = "p49"; |
NET "a[13]" LOC = "p50"; |
NET "a[14]" LOC = "p52"; |
NET "a[15]" LOC = "p53"; |
NET "a[16]" LOC = "p54"; |
NET "a[17]" LOC = "p55"; |
NET "a[18]" LOC = "p56"; |
NET "a[19]" LOC = "p58"; |
NET "a[20]" LOC = "p59"; |
|
# programmable oscillator |
NET "clk" LOC = "p22"; |
|
# parallel port |
#NET "ppd[0]" LOC = "p77"; |
#NET "ppd[1]" LOC = "p74"; |
NET "ppd[2]" LOC = "p72"; |
NET "ppd[3]" LOC = "p70"; |
NET "ppd[4]" LOC = "p68"; |
NET "ppd[5]" LOC = "p67"; |
#NET "ppd[6]" LOC = "p66"; |
#NET "ppd[7]" LOC = "p65"; |
#NET "ppc[0]" LOC = "p79"; |
#NET "ppc[1]" LOC = "p78"; |
#NET "ppc[3]" LOC = "p71"; |
#NET "pps[3]" LOC = "p76"; |
#NET "pps[4]" LOC = "p60"; |
NET "pps[5]" LOC = "p61"; |
#NET "pps[6]" LOC = "p64"; |
|
# UART |
NET "rxd" LOC = "p80"; # Connected to RS232 |
NET "txd" LOC = "p81"; # Connected to RS232 |
#NET "TXD1" LOC = "p9"; # INIT on Virtex = I/O after configuration |
#NET "RXD1" LOC = "p8"; # CS on Virtex = I/O after configuration unless the SelectMAP port is retained. |
|
# Ethernet |
NET "eth_leds" LOC = "p1"; |
NET "eth_ledr" LOC = "p95"; |
NET "eth_ledt" LOC = "p96"; |
NET "eth_ledl" LOC = "p97"; |
NET "eth_ledc" LOC = "p99"; |
NET "eth_mf[0]" LOC = "p91"; |
NET "eth_mf[1]" LOC = "p90"; |
NET "eth_mf[2]" LOC = "p89"; |
NET "eth_mf[3]" LOC = "p87"; |
NET "eth_mf[4]" LOC = "p86"; |
NET "eth_cfg[0]" LOC = "p93"; |
NET "eth_cfg[1]" LOC = "p2"; |
NET "eth_mddis" LOC = "p94"; |
NET "eth_fde" LOC = "p92"; |
|
xilinx_pr/xsv_cpld.ucf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: synplify/xsv_cpld.prd
===================================================================
--- synplify/xsv_cpld.prd (nonexistent)
+++ synplify/xsv_cpld.prd (revision 1765)
@@ -0,0 +1,13 @@
+#-- Synplicity, Inc.
+#-- Version 7.0.3
+#-- Project file G:\xess\xsv_cpld\syn\synplify\xsv_cpld.prd
+#-- Written on Sat Mar 23 20:12:59 2002
+
+#
+### Watch Implementation type ###
+#
+watch_impl -active
+#
+### Watch Implementation properties ###
+#
+watch_prop -clear
synplify/xsv_cpld.prd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: synplify/xsv_cpld.prj
===================================================================
--- synplify/xsv_cpld.prj (nonexistent)
+++ synplify/xsv_cpld.prj (revision 1765)
@@ -0,0 +1,43 @@
+#-- Synplicity, Inc.
+#-- Version 7.0.3
+#-- Project file G:\xess\xsv_cpld\syn\synplify\xsv_cpld.prj
+#-- Written on Sat Mar 23 20:12:59 2002
+
+
+#add_file options
+add_file -verilog "../../rtl/verilog/tdm_master_if.v"
+add_file -verilog "../../rtl/verilog/xsv_cpld_top.v"
+
+#reporting options
+
+
+#implementation: "xsv_cpld_1"
+impl -add xsv_cpld_1
+
+#device options
+set_option -technology XC9500
+set_option -part XC95108
+set_option -package TQ100
+set_option -speed_grade -20
+
+#compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -resource_sharing 1
+set_option -top_module "xsv_cpld_top"
+
+#map options
+set_option -frequency 100.000
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+
+#simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_file "xsv_cpld_1/xsv_cpld_top.edf"
+impl -active "xsv_cpld_1"
synplify/xsv_cpld.prj
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property