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    /or1k_old/trunk/rc203soc/sw/uClinux/include/asm-m68knommu
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Rev 1765 → Rev 1782

/traps.h
0,0 → 1,255
/*
* linux/include/asm/traps.h
*
* Copyright (C) 1993 Hamish Macdonald
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
 
#ifndef _M68K_TRAPS_H
#define _M68K_TRAPS_H
 
typedef void (*e_vector)(void);
 
extern e_vector vectors[];
 
#define VEC_BUSERR (2)
#define VEC_ADDRERR (3)
#define VEC_ILLEGAL (4)
#define VEC_ZERODIV (5)
#define VEC_CHK (6)
#define VEC_TRAP (7)
#define VEC_PRIV (8)
#define VEC_TRACE (9)
#define VEC_LINE10 (10)
#define VEC_LINE11 (11)
#define VEC_RESV1 (12)
#define VEC_COPROC (13)
#define VEC_FORMAT (14)
#define VEC_UNINT (15)
 
 
#define VEC_SYS (32)
#define VEC_TRAP1 (33)
#define VEC_TRAP2 (34)
#define VEC_TRAP3 (35)
#define VEC_TRAP4 (36)
#define VEC_TRAP5 (37)
#define VEC_TRAP6 (38)
#define VEC_TRAP7 (39)
#define VEC_TRAP8 (40)
#define VEC_TRAP9 (41)
#define VEC_TRAP10 (42)
#define VEC_TRAP11 (43)
#define VEC_TRAP12 (44)
#define VEC_TRAP13 (45)
#define VEC_TRAP14 (46)
#define VEC_TRAP15 (47)
#define VEC_FPBRUC (48)
#define VEC_FPIR (49)
#define VEC_FPDIVZ (50)
#define VEC_FPUNDER (51)
#define VEC_FPOE (52)
#define VEC_FPOVER (53)
#define VEC_FPNAN (54)
#define VEC_FPUNSUP (55)
#define VEC_UNIMPEA (60)
#define VEC_UNIMPII (61)
 
#define VEC_SPUR (64)
#define VEC_INT1 (65)
#define VEC_INT2 (66)
#define VEC_INT3 (67)
#define VEC_INT4 (68)
#define VEC_INT5 (69)
#define VEC_INT6 (70)
#define VEC_INT7 (71)
 
#define VECOFF(vec) ((vec)<<2)
 
/* Status register bits */
#define PS_T (0x8000)
#define PS_S (0x2000)
#define PS_M (0x1000)
#define PS_C (0x0001)
 
/* bits for 68020/68030 special status word */
 
#define FC (0x8000)
#define FB (0x4000)
#define RC (0x2000)
#define RB (0x1000)
#define DF (0x0100)
#define RM (0x0080)
#define RW (0x0040)
#define SZ (0x0030)
#define DFC (0x0007)
 
/* bits for 68030 MMU status register (mmusr,psr) */
 
#define MMU_B (0x8000) /* bus error */
#define MMU_L (0x4000) /* limit violation */
#define MMU_S (0x2000) /* supervisor violation */
#define MMU_WP (0x0800) /* write-protected */
#define MMU_I (0x0400) /* invalid descriptor */
#define MMU_M (0x0200) /* ATC entry modified */
#define MMU_T (0x0040) /* transparent translation */
#define MMU_NUM (0x0007) /* number of levels traversed */
 
 
/* bits for 68040 special status word */
#define CP_040 (0x8000)
#define CU_040 (0x4000)
#define CT_040 (0x2000)
#define CM_040 (0x1000)
#define MA_040 (0x0800)
#define ATC_040 (0x0400)
#define LK_040 (0x0200)
#define RW_040 (0x0100)
#define SIZ_040 (0x0060)
#define TT_040 (0x0018)
#define TM_040 (0x0007)
 
/* bits for 68040 write back status word */
#define WBV_040 (0x80)
#define WBSIZ_040 (0x60)
#define WBBYT_040 (0x20)
#define WBWRD_040 (0x40)
#define WBLNG_040 (0x00)
#define WBTT_040 (0x18)
#define WBTM_040 (0x07)
 
/* bus access size codes */
#define BA_SIZE_BYTE (0x20)
#define BA_SIZE_WORD (0x40)
#define BA_SIZE_LONG (0x00)
#define BA_SIZE_LINE (0x60)
 
/* bus access transfer type codes */
#define BA_TT_MOVE16 (0x08)
 
#ifndef NO_MMU
/* bits for 68040 MMU status register (mmusr) */
#define MMU_B_040 (0x0800)
#define MMU_G_040 (0x0400)
#define MMU_S_040 (0x0080)
#define MMU_CM_040 (0x0060)
#define MMU_M_040 (0x0010)
#define MMU_WP_040 (0x0004)
#define MMU_T_040 (0x0002)
#define MMU_R_040 (0x0001)
 
/* bits in the 68060 fault status long word (FSLW) */
#define MMU060_MA (0x08000000) /* misaligned */
#define MMU060_LK (0x02000000) /* locked transfer */
#define MMU060_RW (0x01800000) /* read/write */
# define MMU060_RW_W (0x00800000) /* write */
# define MMU060_RW_R (0x01000000) /* read */
# define MMU060_RW_RMW (0x01800000) /* read/modify/write */
# define MMU060_W (0x00800000) /* general write, includes rmw */
#define MMU060_SIZ (0x00600000) /* transfer size */
#define MMU060_TT (0x00180000) /* transfer type (TT) bits */
#define MMU060_TM (0x00070000) /* transfer modifier (TM) bits */
#define MMU060_IO (0x00008000) /* instruction or operand */
#define MMU060_PBE (0x00004000) /* push buffer bus error */
#define MMU060_SBE (0x00002000) /* store buffer bus error */
#define MMU060_PTA (0x00001000) /* pointer A fault */
#define MMU060_PTB (0x00000800) /* pointer B fault */
#define MMU060_IL (0x00000400) /* double indirect descr fault */
#define MMU060_PF (0x00000200) /* page fault (invalid descr) */
#define MMU060_SP (0x00000100) /* supervisor protection */
#define MMU060_WP (0x00000080) /* write protection */
#define MMU060_TWE (0x00000040) /* bus error on table search */
#define MMU060_RE (0x00000020) /* bus error on read */
#define MMU060_WE (0x00000010) /* bus error on write */
#define MMU060_TTR (0x00000008) /* error caused by TTR translation */
#define MMU060_BPE (0x00000004) /* branch prediction error */
#define MMU060_SEE (0x00000001) /* software emulated error */
 
/* cases of missing or invalid descriptors */
#define MMU060_DESC_ERR (MMU060_TWE | MMU060_PTA | MMU060_PTB | \
MMU060_IL | MMU060_PF)
/* bits that indicate real errors */
#define MMU060_ERR_BITS (MMU060_PBE | MMU060_SBE | MMU060_DESC_ERR | \
MMU060_SP | MMU060_WP | MMU060_RE | \
MMU060_WE)
#endif
 
 
/* structure for stack frames */
 
struct frame {
struct pt_regs ptregs;
union {
struct {
unsigned long iaddr; /* instruction address */
} fmt2;
struct {
unsigned long effaddr; /* effective address */
} fmt3;
struct {
unsigned long effaddr; /* effective address */
unsigned long pc; /* pc of faulted instr */
} fmt4;
struct {
unsigned long effaddr; /* effective address */
unsigned short ssw; /* special status word */
unsigned short wb3s; /* write back 3 status */
unsigned short wb2s; /* write back 2 status */
unsigned short wb1s; /* write back 1 status */
unsigned long faddr; /* fault address */
unsigned long wb3a; /* write back 3 address */
unsigned long wb3d; /* write back 3 data */
unsigned long wb2a; /* write back 2 address */
unsigned long wb2d; /* write back 2 data */
unsigned long wb1a; /* write back 1 address */
unsigned long wb1dpd0; /* write back 1 data/push data 0*/
unsigned long pd1; /* push data 1*/
unsigned long pd2; /* push data 2*/
unsigned long pd3; /* push data 3*/
} fmt7;
struct {
unsigned long iaddr; /* instruction address */
unsigned short int1[4]; /* internal registers */
} fmt9;
struct {
unsigned short int1;
unsigned short ssw; /* special status word */
unsigned short isc; /* instruction stage c */
unsigned short isb; /* instruction stage b */
unsigned long daddr; /* data cycle fault address */
unsigned short int2[2];
unsigned long dobuf; /* data cycle output buffer */
unsigned short int3[2];
} fmta;
struct {
unsigned short int1;
unsigned short ssw; /* special status word */
unsigned short isc; /* instruction stage c */
unsigned short isb; /* instruction stage b */
unsigned long daddr; /* data cycle fault address */
unsigned short int2[2];
unsigned long dobuf; /* data cycle output buffer */
unsigned short int3[4];
unsigned long baddr; /* stage B address */
unsigned short int4[2];
unsigned long dibuf; /* data cycle input buffer */
unsigned short int5[3];
unsigned ver : 4; /* stack frame version # */
unsigned int6:12;
unsigned short int7[18];
} fmtb;
struct {
unsigned long faddr; /* faulted address */
unsigned long dbuf;
unsigned long pc; /* current instruction PC */
unsigned short itc; /* internal transfer count */
unsigned code :2;
unsigned ssr :14; /* special status word */
} fmtc;
} un;
};
 
#endif /* _M68K_TRAPS_H */
/m5307dma.h
0,0 → 1,152
#ifndef _M5307_DMA_H
#define _M5307_DMA_H 1
 
 
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/irq.h>
 
 
#define MAX_DMA_CHANNELS 4
 
/*
*DMA Address Definitions
*/
 
 
#define MCF5307_DMA_SAR (MCF_MBAR+0x300) /*Source Address Register Channel */
#define MCF5307_DMA_DAR (MCF_MBAR+0x304) /*Destination Address Register Channel*/
#define MCF5307_DMA_DCR (MCF_MBAR+0x308) /*DMA Controll Register Channel*/
#define MCF5307_DMA_BCR (MCF_MBAR+0x30C) /*Byte Count Register Channel*/
#define MCF5307_DMA_SR (MCF_MBAR+0x310) /*Status Register Channel*/
#define MCF5307_DMA_IVR (MCF_MBAR+0x314) /*InterruptVectorRegister Channel*/
 
/*
*DMA Controll Register Definition
*/
 
 
#define MCF5307_DMA_DCR_INT (0x8000) /* Interrupt on Completion */
#define MCF5307_DMA_DCR_EEXT (0x4000) /* Enable External Request */
#define MCF5307_DMA_DCR_CS (0x2000) /* Cycle Steal */
#define MCF5307_DMA_DCR_AA (0x1000) /* Auto Align */
#define MCF5307_DMA_DCR_BWC_DMA (0x0000) /* Bandwidth: DMA Priority */
#define MCF5307_DMA_DCR_BWC_512 (0x0200) /* Bandwidth: 512 Bytes */
#define MCF5307_DMA_DCR_BWC_1024 (0x0400) /* Bandwidth: 1024 Bytes */
#define MCF5307_DMA_DCR_BWC_2048 (0x0600) /* Bandwidth: 2048 Bytes */
#define MCF5307_DMA_DCR_BWC_4096 (0x0800) /* Bandwidth: 4096 Bytes */
#define MCF5307_DMA_DCR_BWC_8192 (0x0a00) /* Bandwidth: 8192 Bytes */
#define MCF5307_DMA_DCR_BWC_16384 (0x0c00) /* Bandwidth: 16384 Bytes */
#define MCF5307_DMA_DCR_BWC_32768 (0x0e00) /* Bandwidth: 32768 Bytes */
#define MCF5307_DMA_DCR_SAA (0x0100) /* Single Address Access */
#define MCF5307_DMA_DCR_SRW (0x0080) /* Forces MRW Signal High */
#define MCF5307_DMA_DCR_SINC (0x0040) /* Source Increment */
#define MCF5307_DMA_DCR_SSIZE_LONG (0x0000) /* Source Size: Longword */
#define MCF5307_DMA_DCR_SSIZE_BYTE (0x0010) /* Source Size: Byte */
#define MCF5307_DMA_DCR_SSIZE_WORD (0x0020) /* Source Size: Word */
#define MCF5307_DMA_DCR_SSIZE_LINE (0x0030) /* Source Size: Line */
#define MCF5307_DMA_DCR_DINC (0x0008) /* Destination Increment */
#define MCF5307_DMA_DCR_DSIZE_LONG (0x0000) /* Destination Size: Longword */
#define MCF5307_DMA_DCR_DSIZE_BYTE (0x0002) /* Destination Size: Byte */
#define MCF5307_DMA_DCR_DSIZE_WORD (0x0004) /* Destination Size: Word */
#define MCF5307_DMA_DCR_DSIZE_LINE (0x0006) /* Destination Size: Line */
#define MCF5307_DMA_DCR_START (0x0001) /* Start Transfer */
 
/*
*DMA Status Register Definitions
*/
 
 
#define MCF5307_DMA_DSR_CE (0x40) /* Configuration Error */
#define MCF5307_DMA_DSR_BES (0x20) /* Bus Error on Source */
#define MCF5307_DMA_DSR_BED (0x10) /* Bus Error on Destination */
#define MCF5307_DMA_DSR_REQ (0x04) /* Request */
#define MCF5307_DMA_DSR_BSY (0x02) /* Busy */
#define MCF5307_DMA_DSR_DONE (0x01) /* Transaction Done */
 
 
#define DMA_STATE_BUSY 1
#define DMA_STATE_IDLE 0
#define DMA_STATE_CONFIGURATION_ERROR -1
#define DMA_STATE_SOURCE_ERROR -2
#define DMA_STATE_DESTINATION_ERROR -3
 
struct dma_mcf
{
const char *devname;
unsigned char* source;
unsigned char* dest;
unsigned short count;
unsigned short creg; /*16 bit controllregister use the defines above*/
void (*handler) (int, void *, struct pt_regs *);
unsigned int irq_vector;
unsigned int irq_level;
unsigned long irq_flags;
};
 
static __inline__ int dma_init(int channel)
{
int err;
if ((err = request_dma(channel, 0)) != 0) return err;
*(unsigned char*) (MCF_MBAR + MCFSIM_MPARK) |= 0x80; /* DMA BUS
MASTER with highest priority*/
return err;
}
 
 
 
static __inline__ void dma_set(int channel, struct dma_mcf dma)
{
*(unsigned int*) (MCF5307_DMA_SAR + (0x40 * channel)) = dma.source;
*(unsigned int*) (MCF5307_DMA_DAR + (0x40 * channel)) = dma.dest;
*(unsigned short*) (MCF5307_DMA_BCR + (0x40 * channel)) = dma.count;
if ((dma.creg & MCF5307_DMA_DCR_INT) !=0) /* DMA generates a Interrupt on complrtion*/
{ /* Now configure the Interrupt handler*/
*(unsigned short*) (MCF5307_DMA_IVR + (0x40 * channel)) = dma.irq_vector;
if (request_irq(dma.irq_vector,dma.handler,dma.irq_flags,
dma.devname, 0) !=0)
printk("request irq fail\n");
*(volatile unsigned char*)(MCF_MBAR + 0x52 + channel) = dma.irq_level | MCFSIM_ICR_AUTOVEC; /* set MBUS IRQ-Level and autovector */
mcf_setimr(mcf_getimr() & ~(0x4000 << channel));
printk("maskreg%X\n",mcf_getimr());
}
*(unsigned short*) (MCF5307_DMA_DCR + (0x40 * channel)) = dma.creg;
}
 
 
static __inline__ unsigned char dma_busy(unsigned char channel)
{
if ((*(unsigned char*) (MCF5307_DMA_SR + (0x40 * channel)) & MCF5307_DMA_DSR_BSY)!=0) return(0x1);
return 0;
}
 
static __inline__ void dma_done(unsigned char channel)
{
 
 
*(unsigned char*) (MCF5307_DMA_SR + (0x40 * channel)) = MCF5307_DMA_DSR_DONE;
}
 
 
static __inline__ void dma_clear(unsigned char channel)
{
*(unsigned short*) (MCF5307_DMA_DCR + (0x40 * channel)) = 0x0000;
}
 
 
static __inline__ unsigned char dma_get_status(unsigned char dsr)
{
if ((dsr & MCF5307_DMA_DSR_CE) != 0) return(DMA_STATE_CONFIGURATION_ERROR);
if ((dsr & MCF5307_DMA_DSR_BES) !=0) return(DMA_STATE_SOURCE_ERROR);
if ((dsr & MCF5307_DMA_DSR_BED) !=0) return(DMA_STATE_DESTINATION_ERROR);
return 0;
}
 
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
extern void free_dma(unsigned int dmanr); /* release it again */
#endif /* _M5307_DMA_H */
/byteorder.h
0,0 → 1,45
#ifndef _M68K_BYTEORDER_H
#define _M68K_BYTEORDER_H
 
#ifndef __BIG_ENDIAN
#define __BIG_ENDIAN 4321
#endif
 
#ifndef __BIG_ENDIAN_BITFIELD
#define __BIG_ENDIAN_BITFIELD
#endif
 
#undef ntohl
#undef ntohs
#undef htonl
#undef htons
 
extern unsigned long int ntohl(unsigned long int);
extern unsigned short int ntohs(unsigned short int);
extern unsigned long int htonl(unsigned long int);
extern unsigned short int htons(unsigned short int);
 
extern __inline__ unsigned long int __ntohl(unsigned long int);
extern __inline__ unsigned short int __ntohs(unsigned short int);
 
extern __inline__ unsigned long int
__ntohl(unsigned long int x)
{
return x;
}
 
extern __inline__ unsigned short int
__ntohs(unsigned short int x)
{
return x;
}
 
#define __htonl(x) __ntohl(x)
#define __htons(x) __ntohs(x)
 
#define ntohl(x) __ntohl(x)
#define ntohs(x) __ntohs(x)
#define htonl(x) __htonl(x)
#define htons(x) __htons(x)
 
#endif
/mcfpci.h
0,0 → 1,98
/****************************************************************************/
 
/*
* mcfpci.h -- PCI bridge on ColdFire eval boards.
*
* (C) Copyright 2000, Greg Ungerer (gerg@moreton.com.au)
*/
 
/****************************************************************************/
#ifndef mcfpci_h
#define mcfpci_h
/****************************************************************************/
 
#include <linux/config.h>
 
#ifdef CONFIG_PCI
 
/*
* Address regions in the PCI addres space are not mapped into the
* normal memory space of the ColdFire. They must be accessed via
* handler routines. This is easy for I/O space (inb/outb/etc) but
* needs some code changes to support ordinary memory. Interrupts
* also need to be vectored through the PCI handler first, then it
* will call the actual driver sub-handlers.
*/
 
/*
* Un-define all the standard I/O access routines.
*/
#undef inb
#undef inw
#undef inl
#undef insb
#undef insw
#undef insl
#undef outb
#undef outw
#undef outl
#undef outsb
#undef outsw
#undef outsl
 
#undef request_irq
#undef free_irq
 
 
/*
* Re-direct all I/O memory accesses functions to PCI specific ones.
*/
#define inb pci_inb
#define inw pci_inw
#define inl pci_inl
#define inb_p pci_inb
#define inw_p pci_inw
#define insb pci_insb
#define insw pci_insw
#define insl pci_insl
 
#define outb pci_outb
#define outw pci_outw
#define outl pci_outl
#define outb_p pci_outb
#define outw_p pci_outw
#define outsb pci_outsb
#define outsw pci_outsw
#define outsl pci_outsl
 
#define request_irq pci_request_irq
#define free_irq pci_free_irq
 
 
/*
* Prototypes of the real PCI functions (defined in bios32.c).
*/
unsigned char pci_inb(unsigned int addr);
unsigned short pci_inw(unsigned int addr);
unsigned int pci_inl(unsigned int addr);
void pci_insb(void *addr, void *buf, int len);
void pci_insw(void *addr, void *buf, int len);
void pci_insl(void *addr, void *buf, int len);
 
void pci_outb(unsigned char val, unsigned int addr);
void pci_outw(unsigned short val, unsigned int addr);
void pci_outl(unsigned int val, unsigned int addr);
void pci_outsb(void *addr, void *buf, int len);
void pci_outsw(void *addr, void *buf, int len);
void pci_outsl(void *addr, void *buf, int len);
 
int pci_request_irq(unsigned int irq,
void (*handler)(int, void *, struct pt_regs *),
unsigned long flags,
const char *device,
void *dev_id);
void pci_free_irq(unsigned int irq, void *dev_id);
 
#endif /* CONFIG_PCI */
/****************************************************************************/
#endif /* mcfpci_h */
/unaligned.h
0,0 → 1,36
#ifndef __M68K_UNALIGNED_H
#define __M68K_UNALIGNED_H
 
/*
* The m68k can do unaligned accesses itself.
*
* The strange macros are there to make sure these can't
* be misused in a way that makes them not work on other
* architectures where unaligned accesses aren't as simple.
*/
 
#ifdef BLASTED_MOTOROLA
 
#define get_unaligned(ptr) (*(ptr))
 
#define put_unaligned(val, ptr) ((void)( *(ptr) = (val) ))
 
#else
 
/* However, the simpler architecture m68k devices, including '328 and '332,
cannot perform unaligned access. - kja */
 
#define get_unaligned(ptr) ({ \
typeof((*(ptr))) x; \
memcpy(&x, (void*)ptr, sizeof(*(ptr))); \
x; \
})
 
#define put_unaligned(val, ptr) ({ \
typeof((*(ptr))) x = val; \
memcpy((void*)ptr, &x, sizeof(*(ptr))); \
})
 
#endif
 
#endif
/font.h
0,0 → 1,35
/*
* asm-m68k/font.h -- `Soft' font definitions
*
* Created 1995 by Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
 
#ifndef _ASM_M68K_FONT_H_
#define _ASM_M68K_FONT_H_
 
#include <linux/types.h>
 
 
/*
* Find a font with a specific name
*/
 
extern int findsoftfont(char *name, int *width, int *height, u_char *data[]);
 
 
/*
* Get the default font for a specific screen size
*/
 
extern void getdefaultfont(int xres, int yres, char *name[], int *width,
int *height, u_char *data[]);
 
 
/* Max. length for the name of a predefined font */
#define MAX_FONT_NAME 32
 
#endif /* _ASM_M68K_FONT_H_ */
/elf.h
0,0 → 1,62
#ifndef __ASMm68k_ELF_H
#define __ASMm68k_ELF_H
 
/*
* ELF register definitions..
*/
 
#include <asm/ptrace.h>
 
typedef unsigned long elf_greg_t;
 
#define ELF_NGREG 20 /* d1-d7/a0-a6/d0/usp/orig_d0/sr/pc/fmtvec */
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
 
typedef struct user_m68kfp_struct elf_fpregset_t;
 
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(x) ((x) == EM_68K)
 
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_CLASS ELFCLASS32
#define ELF_DATA ELFDATA2MSB;
#define ELF_ARCH EM_68K
 
/* For SVR4/m68k the function pointer to be registered with
`atexit' is passed in %a1. Although my copy of the ABI has
no such statement, it is actually used on ASV. */
#define ELF_PLAT_INIT(_r) _r->a1 = 0
 
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE 4096
 
#define ELF_CORE_COPY_REGS(pr_reg, regs) \
/* Bleech. */ \
pr_reg[0] = regs->d1; \
pr_reg[1] = regs->d2; \
pr_reg[2] = regs->d3; \
pr_reg[3] = regs->d4; \
pr_reg[4] = regs->d5; \
pr_reg[7] = regs->a0; \
pr_reg[8] = regs->a1; \
pr_reg[14] = regs->d0; \
pr_reg[15] = rdusp(); \
pr_reg[16] = 0; /* orig_d0 */ \
pr_reg[17] = regs->sr; \
pr_reg[18] = regs->pc; \
{ \
struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \
pr_reg[5] = sw->d6; \
pr_reg[6] = sw->d7; \
pr_reg[9] = sw->a2; \
pr_reg[10] = sw->a3; \
pr_reg[11] = sw->a4; \
pr_reg[12] = sw->a5; \
pr_reg[13] = sw->a6; \
}
 
#endif
/mcftimer.h
0,0 → 1,67
/****************************************************************************/
 
/*
* mcftimer.h -- ColdFire internal TIMER support defines.
*
* (C) Copyright 1999, Greg Ungerer (gerg@moreton.com.au)
*/
 
/****************************************************************************/
#ifndef mcftimer_h
#define mcftimer_h
/****************************************************************************/
 
#include <linux/config.h>
 
/*
* Get address specific defines for this ColdFire member.
*/
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5204)
#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */
#elif defined(CONFIG_M5307)
#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */
#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */
#endif
 
 
/*
* Define the TIMER register set addresses.
*/
#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */
#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */
#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */
#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */
#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
 
 
/*
* Bit definitions for the Timer Mode Register (TMR).
* Register bit flags are common accross ColdFires.
*/
#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */
#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */
#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */
#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */
#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */
#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */
#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */
#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */
#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */
#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */
#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */
#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */
#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */
#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */
#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */
#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */
#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */
 
/*
* Bit definitions for the Timer Event Registers (TER).
*/
#define MCFTIMER_TER_CAP 0x01 /* Capture event */
#define MCFTIMER_TER_REF 0x02 /* Refernece event */
 
/****************************************************************************/
#endif /* mcftimer_h */
/shglcore.h
0,0 → 1,66
 
/* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
* The Silver Hammer Group, Ltd.
*/
 
#ifndef _M68K_SHGLCORE_H
#define _M68K_SHGLCORE_H
 
#include <linux/config.h>
 
#ifdef CONFIG_SHGLCORE
 
#include <asm/MC68332.h>
 
#ifdef CONFIG_SHGLCORE_2MEG
 
#define SHGLCORE_ROM_BANK_0_ADDR 0x000000
#define SHGLCORE_ROM_BANK_1_ADDR 0x100000
#define SHGLCORE_RAM_BANK_0_ADDR 0x200000
#define SHGLCORE_RAM_BANK_1_ADDR 0x300000
#define SHGLCORE_FLASH_BANK_0_ADDR 0x400000
 
#define SHGLCORE_ROM_BANK_0_LENGTH 0x100000
#define SHGLCORE_ROM_BANK_1_LENGTH 0x100000
#define SHGLCORE_RAM_BANK_0_LENGTH 0x100000
#define SHGLCORE_RAM_BANK_1_LENGTH 0x100000
#define SHGLCORE_FLASH_BANK_0_LENGTH 0x80000
 
#define SHGLCORE_ACC_ADDR 0x600000
#define SHGLCORE_LANCE_ADDR 0x700000
 
#else
 
#define SHGLCORE_ROM_BANK_0_ADDR 0x000000
#define SHGLCORE_RAM_BANK_0_ADDR 0x100000
#define SHGLCORE_FLASH_BANK_0_ADDR 0x300000
 
#define SHGLCORE_ROM_BANK_0_LENGTH 0x100000
#define SHGLCORE_RAM_BANK_0_LENGTH 0x100000
#define SHGLCORE_FLASH_BANK_0_LENGTH 0x80000
 
#define SHGLCORE_ACC_ADDR 0x400000
#define SHGLCORE_LANCE_ADDR 0x500000
 
#endif
 
#define MAX_DMA_ADDRESS SHGLCORE_RAM_BANK_0_ADDR + SHGLCORE_RAM_BANK_0_LENGTH
 
#define SHGLCORE_LATCH_ADDR (SHGLCORE_ACC_ADDR+0x100)
#define SHGLCORE_1865_0_ADDR (SHGLCORE_ACC_ADDR+0x600)
#define SHGLCORE_1865_1_ADDR (SHGLCORE_ACC_ADDR+0x700)
 
#define SHGLCORE_LATCH_BIT(x) BYTE_REF(SHGLCORE_LATCH_ADDR+x)
 
#define SHGLCORE_LATCH_STATUS_LED 0
#define SHGLCORE_LATCH_ERROR_LED 1
#define SHGLCORE_LATCH_ALARM_LED 2
 
#define SHGLCORE_LATCH_1865 4
 
#define SHGLCORE_LATCH_RELAY_1 6
#define SHGLCORE_LATCH_RELAY_2 7
 
#endif /* SHGLCORE */
 
#endif /* _M68K_SHGLCORE_H */
/ioctl.h
0,0 → 1,80
/* $Id: ioctl.h,v 1.1 2005-12-20 11:40:27 jcastillo Exp $
*
* linux/ioctl.h for Linux by H.H. Bergman.
*/
 
#ifndef _M68K_IOCTL_H
#define _M68K_IOCTL_H
 
/* ioctl command encoding: 32 bits total, command in lower 16 bits,
* size of the parameter structure in the lower 14 bits of the
* upper 16 bits.
* Encoding the size of the parameter structure in the ioctl request
* is useful for catching programs compiled with old versions
* and to avoid overwriting user space outside the user buffer area.
* The highest 2 bits are reserved for indicating the ``access mode''.
* NOTE: This limits the max parameter size to 16kB -1 !
*/
 
/*
* I don't really have any idea about what this should look like, so
* for the time being, this is heavily based on the PC definitions.
*/
 
/*
* The following is for compatibility across the various Linux
* platforms. The i386 ioctl numbering scheme doesn't really enforce
* a type field. De facto, however, the top 8 bits of the lower 16
* bits are indeed used as a type field, so we might just as well make
* this explicit here. Please be sure to use the decoding macros
* below from now on.
*/
#define _IOC_NRBITS 8
#define _IOC_TYPEBITS 8
#define _IOC_SIZEBITS 14
#define _IOC_DIRBITS 2
 
#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
 
#define _IOC_NRSHIFT 0
#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)
#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
 
/*
* Direction bits.
*/
#define _IOC_NONE 0U
#define _IOC_WRITE 1U
#define _IOC_READ 2U
 
#define _IOC(dir,type,nr,size) \
(((dir) << _IOC_DIRSHIFT) | \
((type) << _IOC_TYPESHIFT) | \
((nr) << _IOC_NRSHIFT) | \
((size) << _IOC_SIZESHIFT))
 
/* used to create numbers */
#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))
#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
 
/* used to decode ioctl numbers.. */
#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
 
/* ...and for the drivers/sound files... */
 
#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
 
#endif /* _M68K_IOCTL_H */
/user.h
0,0 → 1,72
#ifndef _M68K_USER_H
#define _M68K_USER_H
 
#include <asm/page.h>
#include <linux/ptrace.h>
/* Core file format: The core file is written in such a way that gdb
can understand it and provide useful information to the user (under
linux we use the 'trad-core' bfd). There are quite a number of
obstacles to being able to view the contents of the floating point
registers, and until these are solved you will not be able to view the
contents of them. Actually, you can read in the core file and look at
the contents of the user struct to find out what the floating point
registers contain.
The actual file contents are as follows:
UPAGE: 1 page consisting of a user struct that tells gdb what is present
in the file. Directly after this is a copy of the task_struct, which
is currently not used by gdb, but it may come in useful at some point.
All of the registers are stored as part of the upage. The upage should
always be only one page.
DATA: The data area is stored. We use current->end_text to
current->brk to pick up all of the user variables, plus any memory
that may have been malloced. No attempt is made to determine if a page
is demand-zero or if a page is totally unused, we just cover the entire
range. All of the addresses are rounded in such a way that an integral
number of pages is written.
STACK: We need the stack information in order to get a meaningful
backtrace. We need to write the data from (esp) to
current->start_stack, so we round each of these off in order to be able
to write an integer number of pages.
The minimum core file size is 3 pages, or 12288 bytes.
*/
 
struct user_m68kfp_struct {
unsigned long fpregs[8*3]; /* fp0-fp7 registers */
unsigned long fpcntl[3]; /* fp control regs */
};
 
/* When the kernel dumps core, it starts by dumping the user struct -
this will be used by gdb to figure out where the data and stack segments
are within the file, and what virtual addresses to use. */
struct user{
/* We start with the registers, to mimic the way that "memory" is returned
from the ptrace(3,...) function. */
struct pt_regs regs; /* Where the registers are actually stored */
struct switch_stack regs2; /* Backward compatibility, sort of */
/* ptrace does not yet supply these. Someday.... */
int u_fpvalid; /* True if math co-processor being used. */
/* for this mess. Not yet used. */
struct user_m68kfp_struct m68kfp; /* Math Co-processor registers. */
/* The rest of this junk is to help gdb figure out what goes where */
unsigned long int u_tsize; /* Text segment size (pages). */
unsigned long int u_dsize; /* Data segment size (pages). */
unsigned long int u_ssize; /* Stack segment size (pages). */
unsigned long start_code; /* Starting virtual address of text. */
unsigned long start_stack; /* Starting virtual address of stack area.
This is actually the bottom of the stack,
the top of the stack is always found in the
esp register. */
long int signal; /* Signal that caused the core dump. */
int reserved; /* No longer used */
struct pt_regs * u_ar0; /* Used by gdb to help find the values for */
/* the registers. */
struct user_m68kfp_struct* u_fpstate; /* Math Co-processor pointer. */
unsigned long magic; /* To uniquely identify a core file */
char u_comm[32]; /* User command that was responsible */
};
#define NBPG PAGE_SIZE
#define UPAGES 1
#define HOST_TEXT_START_ADDR (u.start_code)
#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
 
#endif
/m5206sim.h
0,0 → 1,127
/****************************************************************************/
 
/*
* m5206sim.h -- ColdFire 5206 System Integration Module support.
*
* (C) Copyright 1999, Greg Ungerer (gerg@moreton.com.au)
*/
 
/****************************************************************************/
#ifndef m5206sim_h
#define m5206sim_h
/****************************************************************************/
 
#include <linux/config.h>
 
/*
* Define the 5206 SIM register set addresses.
*/
#define MCFSIM_SIMR 0x03 /* SIM Config reg (r/w) */
#define MCFSIM_ICR1 0x14 /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x15 /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x16 /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x17 /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ICR5 0x18 /* Intr Ctrl reg 5 (r/w) */
#define MCFSIM_ICR6 0x19 /* Intr Ctrl reg 6 (r/w) */
#define MCFSIM_ICR7 0x1a /* Intr Ctrl reg 7 (r/w) */
#define MCFSIM_ICR8 0x1b /* Intr Ctrl reg 8 (r/w) */
#define MCFSIM_ICR9 0x1c /* Intr Ctrl reg 9 (r/w) */
#define MCFSIM_ICR10 0x1d /* Intr Ctrl reg 10 (r/w) */
#define MCFSIM_ICR11 0x1e /* Intr Ctrl reg 11 (r/w) */
#define MCFSIM_ICR12 0x1f /* Intr Ctrl reg 12 (r/w) */
#define MCFSIM_ICR13 0x20 /* Intr Ctrl reg 13 (r/w) */
#ifdef CONFIG_M5206e
#define MCFSIM_ICR14 0x21 /* Intr Ctrl reg 14 (r/w) */
#define MCFSIM_ICR15 0x22 /* Intr Ctrl reg 15 (r/w) */
#endif
 
#define MCFSIM_IMR 0x36 /* Interrupt Mask reg (r/w) */
#define MCFSIM_IPR 0x3a /* Interrupt Pend reg (r/w) */
 
#define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */
#define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/
 
#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */
#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */
 
#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */
#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */
#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
 
#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */
#define MCFSIM_CSCR0 0x6e /* CS 0 Control reg (r/w) */
#define MCFSIM_CSAR1 0x70 /* CS 1 Address reg (r/w) */
#define MCFSIM_CSMR1 0x74 /* CS 1 Mask reg (r/w) */
#define MCFSIM_CSCR1 0x7a /* CS 1 Control reg (r/w) */
#define MCFSIM_CSAR2 0x7c /* CS 2 Address reg (r/w) */
#define MCFSIM_CSMR2 0x80 /* CS 2 Mask reg (r/w) */
#define MCFSIM_CSCR2 0x86 /* CS 2 Control reg (r/w) */
#define MCFSIM_CSAR3 0x88 /* CS 3 Address reg (r/w) */
#define MCFSIM_CSMR3 0x8c /* CS 3 Mask reg (r/w) */
#define MCFSIM_CSCR3 0x92 /* CS 3 Control reg (r/w) */
#define MCFSIM_CSAR4 0x94 /* CS 4 Address reg (r/w) */
#define MCFSIM_CSMR4 0x98 /* CS 4 Mask reg (r/w) */
#define MCFSIM_CSCR4 0x9e /* CS 4 Control reg (r/w) */
#define MCFSIM_CSAR5 0xa0 /* CS 5 Address reg (r/w) */
#define MCFSIM_CSMR5 0xa4 /* CS 5 Mask reg (r/w) */
#define MCFSIM_CSCR5 0xaa /* CS 5 Control reg (r/w) */
#define MCFSIM_CSAR6 0xac /* CS 6 Address reg (r/w) */
#define MCFSIM_CSMR6 0xb0 /* CS 6 Mask reg (r/w) */
#define MCFSIM_CSCR6 0xb6 /* CS 6 Control reg (r/w) */
#define MCFSIM_CSAR7 0xb8 /* CS 7 Address reg (r/w) */
#define MCFSIM_CSMR7 0xbc /* CS 7 Mask reg (r/w) */
#define MCFSIM_CSCR7 0xc2 /* CS 7 Control reg (r/w) */
#define MCFSIM_DMCR 0xc6 /* Default control */
 
#ifdef CONFIG_M5206e
#define MCFSIM_PAR 0xca /* Pin Assignment reg (r/w) */
#else
#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */
#endif
 
#define MCFSIM_PADDR 0x1c5 /* Parallel Direction (r/w) */
#define MCFSIM_PADAT 0x1c9 /* Parallel Port Value (r/w) */
 
/*
* Some symbol defines for the Parallel Port Pin Assignment Register
*/
#ifdef CONFIG_M5206e
#define MCFSIM_PAR_DREQ0 0x100 /* Set to select DREQ0 input */
/* Clear to select T0 input */
#define MCFSIM_PAR_DREQ1 0x200 /* Select DREQ1 input */
/* Clear to select T0 output */
#endif
 
/*
* Some symbol defines for the Interrupt Control Register
*/
#define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */
#define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */
#define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */
#define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */
#define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */
#ifdef CONFIG_M5206e
#define MCFSIM_DMA1ICR MCFSIM_ICR14 /* DMA 1 ICR */
#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
#endif
 
/*
* Macro to get and set IMR register. It is 16 bits on the 5206.
*/
#define mcf_getimr() \
*((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR))
 
#define mcf_setimr(imr) \
*((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR)) = (imr)
 
#define mcf_getipr() \
*((volatile unsigned short *) (MCF_MBAR + MCFSIM_IPR))
 
/****************************************************************************/
#endif /* m5206sim_h */
/m5307sim.h
0,0 → 1,176
/****************************************************************************/
 
/*
* m5307sim.h -- ColdFire 5307 System Integration Module support.
*
* (C) Copyright 1999, Moreton Bay Ventures Pty Ltd.
*
* Modified by David W. Miller for the MCF5307 Eval Board.
*/
 
/****************************************************************************/
#ifndef m5307sim_h
#define m5307sim_h
/****************************************************************************/
 
/*
* Define the 5307 SIM register set addresses.
*/
#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
 
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
 
#ifdef CONFIG_OLDMASK
#define MCFSIM_CSBAR 0x98 /* CS Base Address reg (r/w) */
#define MCFSIM_CSBAMR 0x9c /* CS Base Mask reg (r/w) */
#define MCFSIM_CSMR2 0x9e /* CS 2 Mask reg (r/w) */
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
#define MCFSIM_CSMR3 0xaa /* CS 3 Mask reg (r/w) */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
#define MCFSIM_CSMR4 0xb6 /* CS 4 Mask reg (r/w) */
#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
#define MCFSIM_CSMR5 0xc2 /* CS 5 Mask reg (r/w) */
#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
#define MCFSIM_CSMR6 0xce /* CS 6 Mask reg (r/w) */
#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
#define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
#else
#define MCFSIM_CSAR2 0x98 /* CS 2 Adress reg (r/w) */
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
#define MCFSIM_CSAR3 0xa4 /* CS 3 Adress reg (r/w) */
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
#define MCFSIM_CSAR4 0xb0 /* CS 4 Adress reg (r/w) */
#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
#define MCFSIM_CSAR5 0xbc /* CS 5 Adress reg (r/w) */
#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */
#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
#define MCFSIM_CSAR6 0xc8 /* CS 6 Adress reg (r/w) */
#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */
#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
#define MCFSIM_CSAR7 0xd4 /* CS 7 Adress reg (r/w) */
#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
#endif /* CONFIG_OLDMASK */
 
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
 
#define MCFSIM_PADDR 0x244 /* Parallel Direction (r/w) */
#define MCFSIM_PADAT 0x248 /* Parallel Data (r/w) */
 
 
/* Definition offset address for CS2-7 -- old mask 5307 */
 
#define MCF5307_CS2 (0x400000)
#define MCF5307_CS3 (0x600000)
#define MCF5307_CS4 (0x800000)
#define MCF5307_CS5 (0xA00000)
#define MCF5307_CS6 (0xC00000)
#define MCF5307_CS7 (0xE00000)
 
 
/*
* Some symbol defines for the above...
*/
#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
 
/*
* Macro to set IMR register. It is 32 bits on the 5307.
*/
#define mcf_getimr() \
*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
 
#define mcf_setimr(imr) \
*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
 
#define mcf_getipr() \
*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
 
 
/*
* Some symbol defines for the Parallel Port Pin Assignment Register
*/
#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */
/* Clear to select par I/O */
#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */
/* Clear to select par I/O */
 
/*
* Defines for the IRQPAR Register
*/
#define IRQ5_LEVEL4 0x80
#define IRQ3_LEVEL6 0x40
#define IRQ1_LEVEL2 0x20
 
 
/*
* Define the Cache register flags.
*/
#define CACR_EC (1<<31)
#define CACR_ESB (1<<29)
#define CACR_DPI (1<<28)
#define CACR_HLCK (1<<27)
#define CACR_CINVA (1<<24)
#define CACR_DNFB (1<<10)
#define CACR_DCM_WTHRU (0<<8)
#define CACR_DCM_WBACK (1<<8)
#define CACR_DCM_OFF_PRE (2<<8)
#define CACR_DCM_OFF_IMP (3<<8)
#define CACR_DW (1<<5)
 
#define ACR_BASE_POS 24
#define ACR_MASK_POS 16
#define ACR_ENABLE (1<<15)
#define ACR_USER (0<<13)
#define ACR_SUPER (1<<13)
#define ACR_ANY (2<<13)
#define ACR_CM_WTHRU (0<<5)
#define ACR_CM_WBACK (1<<5)
#define ACR_CM_OFF_PRE (2<<5)
#define ACR_CM_OFF_IMP (3<<5)
#define ACR_WPROTECT (1<<2)
 
/****************************************************************************/
#endif /* m5307sim_h */
/shglports.h
0,0 → 1,77
 
/* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
* 1997, 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
* The Silver Hammer Group, Ltd.
*/
 
#ifndef _M68K_SHGLPORTS_H
#define _M68K_SHGLPORTS_H
 
#include <linux/config.h>
#include <linux/sched.h>
 
#ifdef CONFIG_SHGLCORE
 
extern struct semaphore porte_interlock;
 
struct SHGLCORE_PORT_QS {
unsigned char
nullqs:1, /* COM1TX */
sbin:1, /* PQS6 (PCS3) */
sbclk:1, /* PQS5 (PCS2) */
sbout:1, /* PQS4 (PCS1) */
null4:4; /* MISO, MOSI, SCLK, /SS=PCS0 */
};
 
#define PORT_QS ((volatile struct SHGLCORE_PORT_QS*)PORTQS_ADDR)
 
struct SHGLCORE_PORT_E {
unsigned char
dead:1, /* LED */
sbirigb:1, /* PE6 */
ds:1, /* /DS */
nulle1:1, /* na */
sbpll:1, /* PE3 */
avec:1, /* /AVEC */
sbsrom:1, /* PE1 */
sbpanel:1; /* PE0 */
};
 
#define PORT_E ((volatile struct SHGLCORE_PORT_E*)PORTE_ADDR)
 
struct SHGLCORE_PORT_F {
unsigned char
nullf1:4,
nullf2:4;
};
 
#define PORT_F ((volatile struct SHGLCORE_PORT_F*)PORTF_ADDR)
 
extern int comm_status_led, comm_error_led, alarm_led;
 
static inline void SET_COMM_STATUS_LED(int value) {
BYTE_REF(SHGLCORE_ACC_ADDR+0x100+0) = comm_status_led = value;
}
static inline int GET_COMM_STATUS_LED(void) {
return comm_status_led;
}
 
 
static inline void SET_COMM_ERROR_LED(int value) {
BYTE_REF(SHGLCORE_ACC_ADDR+0x100+1) = comm_error_led = value;
}
static inline int GET_COMM_ERROR_LED(void) {
return comm_error_led;
}
 
 
static inline void SET_ALARM_LED(int value) {
BYTE_REF(SHGLCORE_ACC_ADDR+0x100+2) = alarm_led = value;
}
static inline int GET_ALARM_LED(void) {
return alarm_led;
}
 
#endif
 
#endif /* _M68K_SHGLPORTS_H */
/flat.h
0,0 → 1,46
 
/* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
* The Silver Hammer Group, Ltd.
*
*/
 
#ifndef _LINUX_FLAT_H
#define _LINUX_FLAT_H
 
struct flat_hdr {
char magic[4];
unsigned long rev;
unsigned long entry; /* Offset of first executable instruction with text segment from beginning of file*/
unsigned long data_start; /* Offset of data segment from beginning of file*/
unsigned long data_end; /* Offset of end of data segment from beginning of file*/
unsigned long bss_end; /* Offset of end of bss segment from beginning of file*/
/* (It is assumed that data_end through bss_end forms the
bss segment.) */
unsigned long stack_size; /* Size of stack, in bytes */
unsigned long reloc_start; /* Offset of relocation records from beginning of file */
unsigned long reloc_count; /* Number of relocation records */
unsigned long flags;
unsigned long filler[6]; /* Reservered, set to zero */
};
 
#define FLAT_RELOC_TYPE_TEXT 0
#define FLAT_RELOC_TYPE_DATA 1
#define FLAT_RELOC_TYPE_BSS 2
 
struct flat_reloc {
#ifdef CONFIG_COLDFIRE
unsigned long type : 2;
signed long offset : 30;
#else
signed long offset : 30;
unsigned long type : 2;
#endif
};
 
#define FLAT_FLAG_RAM 0x0001 /* program should be loaded entirely into RAM */
 
#endif /* _LINUX_FLAT_H */
/a.out.h
0,0 → 1,26
#ifndef __M68K_A_OUT_H__
#define __M68K_A_OUT_H__
 
struct exec
{
unsigned long a_info; /* Use macros N_MAGIC, etc for access */
unsigned a_text; /* length of text, in bytes */
unsigned a_data; /* length of data, in bytes */
unsigned a_bss; /* length of uninitialized data area for file, in bytes */
unsigned a_syms; /* length of symbol table data in file, in bytes */
unsigned a_entry; /* start address */
unsigned a_trsize; /* length of relocation info for text, in bytes */
unsigned a_drsize; /* length of relocation info for data, in bytes */
};
 
#define N_TRSIZE(a) ((a).a_trsize)
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
 
#ifdef __KERNEL__
 
#define STACK_TOP TASK_SIZE
 
#endif
 
#endif /* __M68K_A_OUT_H__ */
/irq.h
0,0 → 1,118
#ifndef _M68K_IRQ_H_
#define _M68K_IRQ_H_
 
extern void disable_irq(unsigned int);
extern void enable_irq(unsigned int);
 
#include <linux/config.h>
 
#ifdef CONFIG_COLDFIRE
/*
* On the ColdFire we keep track of all vectors. That way drivers
* can register whatever vector number they wish, and we can deal
* with it.
*/
#define SYS_IRQS 256
#define NR_IRQS SYS_IRQS
 
#else
 
/*
* # of m68k interrupts
*/
 
#define SYS_IRQS 8
 
/*
* This should be the same as the max(NUM_X_SOURCES) for all the
* different m68k hosts compiled into the kernel.
* Currently the Atari has 72 and the Amiga 24, but if both are
* supported in the kernel it is better to make room for 72.
*/
#if defined(CONFIG_ATARI)
#define NR_IRQS (72+SYS_IRQS)
#else
#define NR_IRQS (24+SYS_IRQS)
#endif
#endif /* CONFIG_COLDFIRE */
 
 
/*
* Interrupt source definitions
* General interrupt sources are the level 1-7.
* Adding an interrupt service routine for one of these sources
* results in the addition of that routine to a chain of routines.
* Each one is called in succession. Each individual interrupt
* service routine should determine if the device associated with
* that routine requires service.
*/
 
#define IRQ1 (1) /* level 1 interrupt */
#define IRQ2 (2) /* level 2 interrupt */
#define IRQ3 (3) /* level 3 interrupt */
#define IRQ4 (4) /* level 4 interrupt */
#define IRQ5 (5) /* level 5 interrupt */
#define IRQ6 (6) /* level 6 interrupt */
#define IRQ7 (7) /* level 7 interrupt (non-maskable) */
 
/*
* "Generic" interrupt sources
*/
 
#define IRQ_SCHED_TIMER (8) /* interrupt source for scheduling timer */
 
/*
* Machine specific interrupt sources.
*
* Adding an interrupt service routine for a source with this bit
* set indicates a special machine specific interrupt source.
* The machine specific files define these sources.
*/
 
#define IRQ_MACHSPEC (0x10000000L)
#define IRQ_IDX(irq) ((irq) & ~IRQ_MACHSPEC)
 
/*
* various flags for request_irq()
*/
#define IRQ_FLG_LOCK (0x0001) /* handler is not replaceable */
#define IRQ_FLG_REPLACE (0x0002) /* replace existing handler */
#define IRQ_FLG_FAST (0x0004)
#define IRQ_FLG_SLOW (0x0008)
#define IRQ_FLG_STD (0x8000) /* internally used */
 
#ifndef CONFIG_COLDFIRE
 
/*
* This structure is used to chain together the ISRs for a particular
* interrupt source (if it supports chaining).
*/
typedef struct irq_node {
void (*handler)(int, void *, struct pt_regs *);
unsigned long flags;
void *dev_id;
const char *devname;
struct irq_node *next;
} irq_node_t;
 
/*
* This function returns a new irq_node_t
*/
extern irq_node_t *new_irq_node(void);
 
#endif
 
/*
* This structure has only 4 elements for speed reasons
*/
typedef struct irq_handler {
void (*handler)(int, void *, struct pt_regs *);
unsigned long flags;
void *dev_id;
const char *devname;
} irq_handler_t;
 
/* count of spurious interrupts */
extern volatile unsigned int num_spurious;
 
#endif /* _M68K_IRQ_H_ */
/mcfmbus.h
0,0 → 1,70
/****************************************************************************/
 
/*
* mcfmbus.h -- Coldfire MBUS support defines.
*
* (C) Copyright 1999, Martin Floeer (mfloeer@axcent.de)
*/
 
/****************************************************************************/
 
 
#ifndef mcfmbus_h
#define mcfmbus_h
#include <linux/config.h>
 
 
#define MCFMBUS_BASE 0x280
#define MCFMBUS_IRQ_VECTOR 0x19
#define MCFMBUS_IRQ 0x1
#define MCFMBUS_CLK 0x3f
#define MCFMBUS_IRQ_LEVEL 0x07 /*IRQ Level 1*/
#define MCFMBUS_ADDRESS 0x01
 
 
/*
* Define the 5307 MBUS register set adresses
*/
 
#define MCFMBUS_MADR 0x00
#define MCFMBUS_MFDR 0x04
#define MCFMBUS_MBCR 0x08
#define MCFMBUS_MBSR 0x0C
#define MCFMBUS_MBDR 0x10
 
 
#define MCFMBUS_MADR_ADDR(a) (((a)&0x7F)<<0x01) /*Slave Address*/
 
#define MCFMBUS_MFDR_MBC(a) ((a)&0x3F) /*M-Bus Clock*/
 
/*
* Define bit flags in Controll Register
*/
 
#define MCFMBUS_MBCR_MEN (0x80) /* M-Bus Enable */
#define MCFMBUS_MBCR_MIEN (0x40) /* M-Bus Interrupt Enable */
#define MCFMBUS_MBCR_MSTA (0x20) /* Master/Slave Mode Select Bit */
#define MCFMBUS_MBCR_MTX (0x10) /* Transmit/Rcv Mode Select Bit */
#define MCFMBUS_MBCR_TXAK (0x08) /* Transmit Acknowledge Enable */
#define MCFMBUS_MBCR_RSTA (0x04) /* Repeat Start */
 
/*
* Define bit flags in Status Register
*/
 
#define MCFMBUS_MBSR_MCF (0x80) /* Data Transfer Complete */
#define MCFMBUS_MBSR_MAAS (0x40) /* Addressed as a Slave */
#define MCFMBUS_MBSR_MBB (0x20) /* Bus Busy */
#define MCFMBUS_MBSR_MAL (0x10) /* Arbitration Lost */
#define MCFMBUS_MBSR_SRW (0x04) /* Slave Transmit */
#define MCFMBUS_MBSR_MIF (0x02) /* M-Bus Interrupt */
#define MCFMBUS_MBSR_RXAK (0x01) /* No Acknowledge Received */
 
/*
* Define bit flags in DATA I/O Register
*/
 
#define MCFMBUS_MBDR_READ (0x01) /* 1=read 0=write MBUS */
 
#endif
/ioctls.h
0,0 → 1,76
#ifndef __ARCH_M68K_IOCTLS_H__
#define __ARCH_M68K_IOCTLS_H__
 
#include <asm/ioctl.h>
 
/* 0x54 is just a magic number to make these relatively unique ('T') */
 
#define TCGETS 0x5401
#define TCSETS 0x5402
#define TCSETSW 0x5403
#define TCSETSF 0x5404
#define TCGETA 0x5405
#define TCSETA 0x5406
#define TCSETAW 0x5407
#define TCSETAF 0x5408
#define TCSBRK 0x5409
#define TCXONC 0x540A
#define TCFLSH 0x540B
#define TIOCEXCL 0x540C
#define TIOCNXCL 0x540D
#define TIOCSCTTY 0x540E
#define TIOCGPGRP 0x540F
#define TIOCSPGRP 0x5410
#define TIOCOUTQ 0x5411
#define TIOCSTI 0x5412
#define TIOCGWINSZ 0x5413
#define TIOCSWINSZ 0x5414
#define TIOCMGET 0x5415
#define TIOCMBIS 0x5416
#define TIOCMBIC 0x5417
#define TIOCMSET 0x5418
#define TIOCGSOFTCAR 0x5419
#define TIOCSSOFTCAR 0x541A
#define FIONREAD 0x541B
#define TIOCINQ FIONREAD
#define TIOCLINUX 0x541C
#define TIOCCONS 0x541D
#define TIOCGSERIAL 0x541E
#define TIOCSSERIAL 0x541F
#define TIOCPKT 0x5420
#define FIONBIO 0x5421
#define TIOCNOTTY 0x5422
#define TIOCSETD 0x5423
#define TIOCGETD 0x5424
#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
#define TIOCTTYGSTRUCT 0x5426 /* For debugging only */
#define TIOCSBRK 0x5427 /* BSD compatibility */
#define TIOCCBRK 0x5428 /* BSD compatibility */
#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */
#define FIOCLEX 0x5451
#define FIOASYNC 0x5452
#define TIOCSERCONFIG 0x5453
#define TIOCSERGWILD 0x5454
#define TIOCSERSWILD 0x5455
#define TIOCGLCKTRMIOS 0x5456
#define TIOCSLCKTRMIOS 0x5457
#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
#define TIOCSERGETLSR 0x5459 /* Get line status register */
#define TIOCSERGETMULTI 0x545A /* Get multiport config */
#define TIOCSERSETMULTI 0x545B /* Set multiport config */
 
#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
 
/* Used for packet mode */
#define TIOCPKT_DATA 0
#define TIOCPKT_FLUSHREAD 1
#define TIOCPKT_FLUSHWRITE 2
#define TIOCPKT_STOP 4
#define TIOCPKT_START 8
#define TIOCPKT_NOSTOP 16
#define TIOCPKT_DOSTOP 32
 
#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
 
#endif /* __ARCH_M68K_IOCTLS_H__ */
/delay.h
0,0 → 1,59
#ifndef _M68K_DELAY_H
#define _M68K_DELAY_H
 
extern unsigned long loops_per_sec;
#include <linux/kernel.h>
#include <linux/config.h>
 
/*
* Copyright (C) 1994 Hamish Macdonald
*
* Delay routines, using a pre-computed "loops_per_second" value.
*/
 
 
extern __inline__ void __delay(unsigned long loops)
{
__asm__ __volatile__ ("1: subql #1,%0; jcc 1b"
: "=d" (loops) : "0" (loops));
}
 
/*
* Use only for very small delays ( < 1 msec). Should probably use a
* lookup table, really, as the multiplications take much too long with
* short delays. This is a "reasonable" implementation, though (and the
* first constant multiplications gets optimized away if the delay is
* a constant)
*/
extern __inline__ void udelay(unsigned long usecs)
{
#ifdef CONFIG_M68332
usecs *= 0x000010c6;
__asm__ __volatile__ ("mulul %1,%0:%2"
: "=d" (usecs)
: "d" (usecs),
"d" (loops_per_sec));
__delay(usecs);
 
#endif
#if defined(CONFIG_M68328) || defined(CONFIG_M68EZ328) || defined(CONFIG_COLDFIRE)
/* Sigh */
__delay(usecs);
#endif
}
 
#define muldiv(a, b, c) (((a)*(b))/(c))
 
/*
extern __inline__ unsigned long muldiv(unsigned long a, unsigned long b, unsigned long c)
{
unsigned long tmp;
 
__asm__ ("mulul %2,%0:%1; divul %3,%0:%1"
: "=d" (tmp), "=d" (a)
: "d" (b), "d" (c), "1" (a));
return a;
}
*/
 
#endif /* defined(_M68K_DELAY_H) */
/io_hw_swap.h
0,0 → 1,113
#ifndef _M68K_IO_HW_SWAP_H
#define _M68K_IO_HW_SWAP_H
 
/*
* swap functions are sometimes needed to interface little-endian hardware
*/
static inline unsigned short _swapw(volatile unsigned short v)
{
return ((v << 8) | (v >> 8));
}
 
static inline unsigned int _swapl(volatile unsigned long v)
{
return ((v << 24) | ((v & 0xff00) << 8) | ((v & 0xff0000) >> 8) | (v >> 24));
}
 
/*
* readX/writeX() are used to access memory mapped devices. On some
* architectures the memory mapped IO stuff needs to be accessed
* differently. On the m68k architecture, we just read/write the
* memory location directly.
*/
/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
* two accesses to memory, which may be undesireable for some devices.
*/
#define readb(addr) \
({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
#define readw(addr) \
({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
#define readl(addr) \
({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
 
#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b))
#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b))
#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
 
/* There is no difference between I/O and memory on 68k, these are the same */
#define inb(addr) \
({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
#define inw(addr) \
({ unsigned short __v = (*(volatile unsigned short *) (addr)); \
_swapw(__v); })
#define inl(addr) \
({ unsigned int __v = (*(volatile unsigned int *) (addr)); _swapl(__v); })
 
#define outb(b,addr) ((*(volatile unsigned char *) (addr)) = (b))
#define outw(b,addr) ((*(volatile unsigned short *) (addr)) = (_swapw(b)))
#define outl(b,addr) ((*(volatile unsigned int *) (addr)) = (_swapl(b)))
 
/* FIXME: these need to be optimized. Watch out for byte swapping, they
* are used mostly for Intel devices... */
#define outsw(addr,buf,len) \
({ unsigned short * __e = (unsigned short *)(buf) + (len); \
unsigned short * __p = (unsigned short *)(buf); \
while (__p < __e) { \
*(volatile unsigned short *)(addr) = *__p++;\
} \
})
 
#define insw(addr,buf,len) \
({ unsigned short * __e = (unsigned short *)(buf) + (len); \
unsigned short * __p = (unsigned short *)(buf); \
while (__p < __e) { \
*(__p++) = *(volatile unsigned short *)(addr); \
} \
})
 
 
static inline unsigned char get_user_byte_io(const char * addr)
{
register unsigned char _v;
 
__asm__ __volatile__ ("moveb %1,%0":"=dm" (_v):"m" (*addr));
return _v;
}
#define inb_p(addr) get_user_byte_io((char *)(addr))
 
static inline void put_user_byte_io(char val,char *addr)
{
__asm__ __volatile__ ("moveb %0,%1"
: /* no outputs */
:"idm" (val),"m" (*addr)
: "memory");
}
#define outb_p(x,addr) put_user_byte_io((x),(char *)(addr))
 
/*
* Change virtual addresses to physical addresses and vv.
* These are trivial on the 1:1 Linux/i386 mapping (but if we ever
* make the kernel segment mapped at 0, we need to do translation
* on the i386 as well)
*/
extern unsigned long mm_vtop(unsigned long addr);
extern unsigned long mm_ptov(unsigned long addr);
 
extern inline unsigned long virt_to_phys(volatile void * address)
{
return (unsigned long) mm_vtop((unsigned long)address);
}
 
extern inline void * phys_to_virt(unsigned long address)
{
return (void *) mm_ptov(address);
}
 
/*
* IO bus memory addresses are also 1:1 with the physical address
*/
#define virt_to_bus virt_to_phys
#define bus_to_virt phys_to_virt
 
 
#endif /* _M68K_IO_HW_SWAP_H */
/m68302.h
0,0 → 1,219
#ifndef _m68302_h_
#define _m68302_h_
 
 
#ifndef REG8 /* 8-bit reg */
#define REG8(addr) *((volatile unsigned char * ) (addr))
#endif
#ifndef REG16 /* 16-bit reg */
#define REG16(addr) *((volatile unsigned short * ) (addr))
#endif
#ifndef REG32 /* 32-bit reg */
#define REG32(addr) *((volatile unsigned long * ) (addr))
#endif
 
#ifndef AREG8 /* 8-bit reg */
#define AREG8(addr) ((volatile unsigned char * ) (addr))
#endif
#ifndef AREG16 /* 16-bit reg */
#define AREG16(addr) ((volatile unsigned short * ) (addr))
#endif
#ifndef AREG32 /* 32-bit reg */
#define AREG32(addr) ((volatile unsigned short * ) (addr))
#endif
 
/* These values must be the same as in begin.s */
#define BAR 0xF00000
//#define BAR 0xFFF000
 
#define GIMR BAR+0x812 /* Global Interrupt Mode Reg's Memory Address */
#define IMR BAR+0x816 /* Interrupt Mask Reg'S Memory Address */
#define ISR BAR+0x818
#define TMR1 BAR+0x840 /* Timer Mode Register 1 */
#define TRR1 BAR+0x842 /* Timer Reference Register 1 */
#define TCR1 BAR+0x844 /* Timer Capture Register 1 */
#define TCN1 BAR+0x846 /* Timer Counter 1 */
#define TER1 BAR+0x849 /* Timer Event Register 1 */
#define TMR2 BAR+0x850 /* Timer Mode Register 2 */
#define TRR2 BAR+0x852 /* Timer Reference Register 2 */
#define TCR2 BAR+0x854 /* Timer Capture Register 2 */
#define TCN2 BAR+0x856 /* Timer Counter 2 */
#define TER2 BAR+0x859 /* Timer Event Register 2 */
#define WRR BAR+0x84A /* Watchdog Reference Register */
#define WCN BAR+0x84C /* Watchdog Counter */
 
#define ISR_TMR1 (1 << 9) /* TIMER1 bit in the ISR and IMR */
#define ISR_TMR2 (1 << 6) /* TIMER3 bit in the ISR and IMR */
#define ISR_PB10 (1 << 14) /* PB10 bit in the ISR and IMR */
#define ISR_PB11 (1 << 15) /* PB11 bit in the ISR and IMR */
#define ISR_SCC1 (1 << 13) /* SCC1 bit in the ISR and IMR */
#define ISR_SCC2 (1 << 10) /* SCC2 bit in the ISR and IMR */
#define ISR_SCC3 (1 << 8) /* SCC3 bit in the ISR and IMR */
 
struct _68302_TMR
{
unsigned short PS:8;
unsigned short CE:2;
unsigned short OM:1;
unsigned short ORI:1;
unsigned short FRR:1;
unsigned short ICLK:2;
unsigned short RST:1;
};
 
struct _68302_TIMER
{
struct _68302_TMR TMR;
unsigned short TRR;
unsigned short TCR;
unsigned short TCN;
unsigned char RES;
unsigned char TER;
};
 
 
// port A
#define PACNT REG16(BAR+0x81E)
#define PADDR REG16(BAR+0x820)
#define PADAT REG16(BAR+0x822)
#define A_PADAT AREG16(BAR+0x822)
 
/* port B */
#define PBCNT REG16(BAR+0x824)
#define PBDDR REG16(BAR+0x826)
#define PBDAT REG16(BAR+0x828)
#define A_PBDAT AREG16(BAR+0x828)
 
 
// Common SCC
#define SIMODE REG16(BAR+0x8B4)
#define SIMASK REG16(BAR+0x8B2)
#define SPMODE REG16(BAR+0x8B0)
#define SMC2Rx REG16(BAR+0x66A)
#define SMC1Rx REG16(BAR+0x666)
#define SMC2Tx REG16(BAR+0x66C)
#define SCC_BD_SIZE 4 // Each BD has 4 ushorts
 
struct _68302_scc{
unsigned short res1;
unsigned short scon; // configuration
unsigned short scm; // mode
unsigned short dsr; // data sync
unsigned char scce; // event
unsigned char res2;
unsigned char sccm; // mask
unsigned char res3;
unsigned char sccs; // status
unsigned char res4;
unsigned short res5;
};
 
#define SCC1_BASE REG16(BAR+0x880)
#define SCC2_BASE REG16(BAR+0x890)
#define SCC3_BASE REG16(BAR+0x8A0)
 
 
#define SCM_MODE0 (1 << 0)
#define SCM_MODE1 (1 << 1)
#define SCM_ENT (1 << 2)
#define SCM_ENR (1 << 3)
#define SCM_DIAG0 (1 << 4)
#define SCM_DIAG1 (1 << 5)
 
#define SCCME_CTS (1 << 7)
#define SCCME_CD (1 << 6)
#define SCCME_IDL (1 << 5)
#define SCCME_BRK (1 << 4) // receive break
#define SCCME_CCR (1 << 3) // control char received
#define SCCME_BSY (1 << 2) // receive overrun
#define SCCME_TX (1 << 1) // buffer transmitted
#define SCCME_RX (1 << 0) // buffer received
 
#define SCCS_CTS (1 << 0)
#define SCCS_CD (1 << 1)
 
/* SCC1 */
 
#define SCON1 REG16(BAR+0x882)
#define SCM1 REG16(BAR+0x884)
#define SCCE1 REG8(BAR+0x888)
#define SCCM1 REG8(BAR+0x88A)
#define SCCS1 REG8(BAR+0x88C)
 
#define SCC1_BD_BASE REG16(BAR+0x400)
 
#define SCC1_TXBD0_1W REG16(BAR+0x440)
#define SCC1_TXBD0_2W REG16(BAR+0x442)
#define SCC1_TXBD0_1L REG32(BAR+0x444)
#define SCC1_RXBD0_1W REG16(BAR+0x400)
#define SCC1_RXBD0_2W REG16(BAR+0x402)
#define SCC1_RXBD0_1L REG32(BAR+0x404)
#define SCC1_MAX_IDL REG16(BAR+0x49C)
#define SCC1_BRKCR REG16(BAR+0x4A0)
#define SCC1_PAREC REG16(BAR+0x4A2)
#define SCC1_FRMEC REG16(BAR+0x4A4)
#define SCC1_NOSEC REG16(BAR+0x4A6)
#define SCC1_BRKEC REG16(BAR+0x4A8)
#define SCC1_MRBLR REG16(BAR+0x482)
#define SCC1_RFCR REG16(BAR+0x480)
#define SCC1_CARACT REG16(BAR+0x4B0)
#define SCC1_UADDR1 REG16(BAR+0x4aa)
#define SCC1_UADDR2 REG16(BAR+0x4ac)
 
/* SCC2 */
 
#define SCON2 REG16(BAR+0x892)
#define SCM2 REG16(BAR+0x894)
#define SCCE2 REG8(BAR+0x898)
#define SCCM2 REG8(BAR+0x89A)
#define SCCS2 REG8(BAR+0x89C)
 
#define SCC2_BD_BASE REG16(BAR+0x500)
 
#define SCC2_TXBD0_1W REG16(BAR+0x540)
#define SCC2_TXBD0_2W REG16(BAR+0x542)
#define SCC2_TXBD0_1L REG32(BAR+0x544)
#define SCC2_RXBD0_1W REG16(BAR+0x500)
#define SCC2_RXBD0_2W REG16(BAR+0x502)
#define SCC2_RXBD0_1L REG32(BAR+0x504)
#define SCC2_MAX_IDL REG16(BAR+0x59C)
#define SCC2_BRKCR REG16(BAR+0x5A0)
#define SCC2_PAREC REG16(BAR+0x5A2)
#define SCC2_FRMEC REG16(BAR+0x5A4)
#define SCC2_NOSEC REG16(BAR+0x5A6)
#define SCC2_BRKEC REG16(BAR+0x5A8)
#define SCC2_MRBLR REG16(BAR+0x582)
#define SCC2_RFCR REG16(BAR+0x580)
#define SCC2_CARACT REG16(BAR+0x5B0)
#define SCC2_UADDR1 REG16(BAR+0x5aa)
#define SCC2_UADDR2 REG16(BAR+0x5ac)
 
/* SCC3 */
 
#define SCON3 REG16(BAR+0x8A2)
#define SCM3 REG16(BAR+0x8A4)
#define SCCE3 REG8(BAR+0x8A8)
#define SCCM3 REG8(BAR+0x8AA)
#define SCCS3 REG8(BAR+0x8AC)
 
#define SCC3_BD_BASE REG16(BAR+0x600)
 
#define SCC3_TXBD0_1W REG16(BAR+0x640)
#define SCC3_TXBD0_2W REG16(BAR+0x642)
#define SCC3_TXBD0_1L REG32(BAR+0x644)
#define SCC3_RXBD0_1W REG16(BAR+0x600)
#define SCC3_RXBD0_2W REG16(BAR+0x602)
#define SCC3_RXBD0_1L REG32(BAR+0x604)
#define SCC3_MAX_IDL REG16(BAR+0x69C)
#define SCC3_BRKCR REG16(BAR+0x6A0)
#define SCC3_PAREC REG16(BAR+0x6A2)
#define SCC3_FRMEC REG16(BAR+0x6A4)
#define SCC3_NOSEC REG16(BAR+0x6A6)
#define SCC3_BRKEC REG16(BAR+0x6A8)
#define SCC3_MRBLR REG16(BAR+0x682)
#define SCC3_RFCR REG16(BAR+0x680)
#define SCC3_CARACT REG16(BAR+0x6B0)
#define SCC3_UADDR1 REG16(BAR+0x6aa)
#define SCC3_UADDR2 REG16(BAR+0x6ac)
 
#endif
/param.h
0,0 → 1,39
#ifndef _M68K_PARAM_H
#define _M68K_PARAM_H
 
#include <linux/config.h>
 
#ifndef HZ
#ifdef CONFIG_COLDFIRE
#define HZ 100
#endif
#ifdef CONFIG_M68EN302
#define HZ 100
#endif
#ifdef CONFIG_M68328
#define HZ 100
#endif
#ifdef CONFIG_M68EZ328
#define HZ 100
#endif
#ifdef CONFIG_UCSIMM
#define HZ 100
#endif
#ifdef CONFIG_SHGLCORE
#define HZ 50
#endif
#endif
 
#define EXEC_PAGESIZE 4096
 
#ifndef NGROUPS
#define NGROUPS 32
#endif
 
#ifndef NOGROUP
#define NOGROUP (-1)
#endif
 
#define MAXHOSTNAMELEN 64 /* max length of hostname */
 
#endif /* _M68K_PARAM_H */
/bugs.h
0,0 → 1,16
/*
* include/asm-m68k/bugs.h
*
* Copyright (C) 1994 Linus Torvalds
*/
 
/*
* This is included by init/main.c to check for architecture-dependent bugs.
*
* Needs:
* void check_bugs(void);
*/
 
static void check_bugs(void)
{
}
/bitops.h
0,0 → 1,282
#ifndef _ASM_GENERIC_BITOPS_H_
#define _ASM_GENERIC_BITOPS_H_
 
#ifdef __KERNEL__
#include <asm/system.h>
#endif
 
/*
* For the benefit of those who are trying to port Linux to another
* architecture, here are some C-language equivalents. You should
* recode these in the native assembly language, if at all possible.
* To guarantee atomicity, these routines call cli() and sti() to
* disable interrupts while they operate. (You have to provide inline
* routines to cli() and sti().)
*
* Also note, these routines assume that you have 32 bit integers.
* You will have to change this if you are trying to port Linux to the
* Alpha architecture or to a Cray. :-)
*
* C language equivalents written by Theodore Ts'o, 9/26/92
*/
 
extern __inline__ int set_bit(int nr, void * a)
{
int * addr = a;
int mask, retval;
unsigned long flags;
 
addr += nr >> 5;
mask = 1 << (nr & 0x1f);
save_flags(flags); cli();
retval = (mask & *addr) != 0;
*addr |= mask;
restore_flags(flags);
return retval;
}
 
extern __inline__ int clear_bit(int nr, void * a)
{
int * addr = a;
int mask, retval;
unsigned long flags;
 
addr += nr >> 5;
mask = 1 << (nr & 0x1f);
save_flags(flags); cli();
retval = (mask & *addr) != 0;
*addr &= ~mask;
restore_flags(flags);
return retval;
}
 
extern __inline__ unsigned long change_bit(unsigned long nr, void *addr)
{
int mask, flags;
unsigned long *ADDR = (unsigned long *) addr;
unsigned long oldbit;
 
ADDR += nr >> 5;
mask = 1 << (nr & 31);
save_flags(flags); cli();
oldbit = (mask & *ADDR);
*ADDR ^= mask;
restore_flags(flags);
return oldbit != 0;
}
 
extern __inline__ int test_bit(int nr, void * a)
{
int * addr = a;
int mask;
 
addr += nr >> 5;
mask = 1 << (nr & 0x1f);
return ((mask & *addr) != 0);
}
 
/* The easy/cheese version for now. */
extern __inline__ unsigned long ffz(unsigned long word)
{
unsigned long result = 0;
 
while(word & 1) {
result++;
word >>= 1;
}
return result;
}
 
/* find_next_zero_bit() finds the first zero bit in a bit string of length
* 'size' bits, starting the search at bit 'offset'. This is largely based
* on Linus's ALPHA routines, which are pretty portable BTW.
*/
 
extern __inline__ unsigned long find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
{
unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;
 
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if (offset) {
tmp = *(p++);
tmp |= ~0UL >> (32-offset);
if (size < 32)
goto found_first;
if (~tmp)
goto found_middle;
size -= 32;
result += 32;
}
while (size & ~31UL) {
if (~(tmp = *(p++)))
goto found_middle;
result += 32;
size -= 32;
}
if (!size)
return result;
tmp = *p;
 
found_first:
tmp |= ~0UL >> size;
found_middle:
return result + ffz(tmp);
}
 
/* Linus sez that gcc can optimize the following correctly, we'll see if this
* holds on the Sparc as it does for the ALPHA.
*/
 
#define find_first_zero_bit(addr, size) \
find_next_zero_bit((addr), (size), 0)
 
/* Now for the ext2 filesystem bit operations and helper routines. */
 
extern __inline__ int ext2_set_bit(int nr,void * addr)
{
int mask, retval, flags;
unsigned char *ADDR = (unsigned char *) addr;
 
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
save_flags(flags); cli();
retval = (mask & *ADDR) != 0;
*ADDR |= mask;
restore_flags(flags);
return retval;
}
 
extern __inline__ int ext2_clear_bit(int nr, void * addr)
{
int mask, retval, flags;
unsigned char *ADDR = (unsigned char *) addr;
 
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
save_flags(flags); cli();
retval = (mask & *ADDR) != 0;
*ADDR &= ~mask;
restore_flags(flags);
return retval;
}
 
extern __inline__ int ext2_test_bit(int nr, const void * addr)
{
int mask;
const unsigned char *ADDR = (const unsigned char *) addr;
 
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
return ((mask & *ADDR) != 0);
}
 
#define ext2_find_first_zero_bit(addr, size) \
ext2_find_next_zero_bit((addr), (size), 0)
 
extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
{
unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;
 
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if(offset) {
tmp = *(p++);
tmp |= ~0UL << (32-offset);
if(size < 32)
goto found_first;
if(~tmp)
goto found_middle;
size -= 32;
result += 32;
}
while(size & ~31UL) {
if(~(tmp = *(p++)))
goto found_middle;
result += 32;
size -= 32;
}
if(!size)
return result;
tmp = *p;
 
found_first:
tmp |= ~0UL << size;
found_middle:
tmp = ((tmp>>24) | ((tmp>>8)&0xff00) | ((tmp<<8)&0xff0000) | (tmp<<24));
return result + ffz(tmp);
}
 
#define __ext2_set_bit ext2_set_bit
#define __ext2_clear_bit ext2_clear_bit
 
extern __inline__ int __ext2_test_bit(int nr, __const__ void * addr)
{
int mask;
__const__ unsigned char *ADDR = (__const__ unsigned char *) addr;
 
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
return ((mask & *ADDR) != 0);
}
 
extern __inline__ unsigned short __swab16(unsigned short value)
{
return ((value >> 8) | (value << 8));
}
 
extern __inline__ unsigned long __swab32(unsigned long value)
{
return ((value >> 24) | ((value >> 8) & 0xff00) |
((value << 8) & 0xff0000) | (value << 24));
}
 
#define __ext2_find_first_zero_bit(addr, size) \
__ext2_find_next_zero_bit((addr), (size), 0)
 
extern __inline__ unsigned long __ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
{
unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;
 
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if(offset) {
tmp = *(p++);
tmp |= __swab32(~0UL >> (32-offset));
if(size < 32)
goto found_first;
if(~tmp)
goto found_middle;
size -= 32;
result += 32;
}
while(size & ~31UL) {
if(~(tmp = *(p++)))
goto found_middle;
result += 32;
size -= 32;
}
if(!size)
return result;
tmp = *p;
 
found_first:
return result + ffz(__swab32(tmp) | (~0UL << size));
found_middle:
return result + ffz(__swab32(tmp));
}
 
 
#endif /* _ASM_GENERIC_BITOPS_H */
/dma.h
0,0 → 1,207
#ifndef _M68K_DMA_H
#define _M68K_DMA_H 1
#include <linux/config.h>
 
#ifdef CONFIG_COLDFIRE
/*
* ColdFire DMA Model:
* ColdFire DMA supports two forms of DMA: Single and Dual address. Single
* address mode emits a source address, and expects that the device will either
* pick up the data (DMA READ) or source data (DMA WRITE). This implies that
* the device will place data on the correct byte(s) of the data bus, as the
* memory transactions are always 32 bits. This implies that only 32 bit
* devices will find single mode transfers useful. Dual address DMA mode
* performs two cycles: source read and destination write. ColdFire will
* align the data so that the device will always get the correct bytes, thus
* is useful for 8 and 16 bit devices. This is the mode that is supported
* below.
*/
 
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfdma.h>
 
/*
* Set number of channels of DMA on ColdFire for different implementations
*/
#if defined(CONFIG_M5307)
#define MAX_DMA_CHANNELS 4
#else
#define MAX_DMA_CHANNELS 2
#endif
 
extern unsigned int dma_base_addr[];
 
/* Storage for where to write/read DMA data to/from */
unsigned int dma_device_address[MAX_DMA_CHANNELS];
 
#define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */
#define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */
 
/* I/O to memory, 8 bits, mode */
#define DMA_MODE_READ 0
/* memory to I/O, 8 bits, mode */
#define DMA_MODE_WRITE 1
/* I/O to memory, 16 bits, mode */
#define DMA_MODE_READ_WORD 2
/* memory to I/O, 16 bits, mode */
#define DMA_MODE_WRITE_WORD 3
 
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
volatile unsigned short *dmawp;
 
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT;
 
}
 
static __inline__ void disable_dma(unsigned int dmanr)
{
volatile unsigned short *dmawp;
volatile unsigned char *dmapb;
 
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmapb = (unsigned char *) dma_base_addr[dmanr];
 
/* Turn off external requests, and stop any DMA in progress */
dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT;
dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE;
}
 
/* Clear the 'DMA Pointer Flip Flop'.
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
* Use this once to initialize the FF to a known state.
* After that, keep track of it. :-)
* --- In order to do that, the DMA routines below should ---
* --- only be used while interrupts are disabled! ---
*
* This is a NOP for ColdFire. Provide a stub for compatibility.
*/
 
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
}
 
/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
volatile unsigned char *dmabp;
volatile unsigned short *dmawp;
 
dmabp = (unsigned char *) dma_base_addr[dmanr];
dmawp = (unsigned short *) dma_base_addr[dmanr];
 
// Clear config errors
dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE;
 
// Set command register
dmawp[MCFDMA_DCR] =
MCFDMA_DCR_INT | // Enable completion irq
MCFDMA_DCR_CS | // Force one xfer per request
MCFDMA_DCR_AA | // Enable auto alignment
// Memory to I/O or I/O to Memory
((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) |
// 16 bit or 8 bit transfers
((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD :
MCFDMA_DCR_SSIZE_BYTE) |
((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_DSIZE_WORD :
MCFDMA_DCR_DSIZE_BYTE) ;
 
#ifdef DMA_DEBUG
printk("%s: Setting stat %x: %x ctrl %x: %x regs for chan %d\n",
__FUNCTION__,
&dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR],
&dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR],
dmanr);
#endif
}
/* Set transfer address for specific DMA channel */
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) {
volatile unsigned short *dmawp;
volatile unsigned int *dmalp;
 
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmalp = (unsigned int *) dma_base_addr[dmanr];
 
// Determine which address registers are used for memory/device accesses
if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) {
// Source incrementing, must be memory
dmalp[MCFDMA_SAR] = a;
// Set dest address, must be device
dmalp[MCFDMA_DAR] = dma_device_address[dmanr];
}
else {
// Destination incrementing, must be memory
dmalp[MCFDMA_DAR] = a;
// Set source address, must be device
dmalp[MCFDMA_SAR] = dma_device_address[dmanr];
}
 
#ifdef DMA_DEBUG
printk("%s: Setting src %x dest %x addr for chan %d\n",
__FUNCTION__, dmalp[MCFDMA_SAR], dmalp[MCFDMA_DAR], dmanr);
#endif
}
 
/*
* Specific for Coldfire - sets device address.
* Should be called after the mode set call, and before set DMA address.
*/
static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a) {
dma_device_address[dmanr] = a;
#ifdef DMA_DEBUG
printk("%s: Setting device addr %x for chan %d\n",
__FUNCTION__, dma_device_address[dmanr], dmanr);
#endif DMA_DEBUG
}
 
/*
* NOTE 2: "count" represents _bytes_.
*/
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
volatile unsigned short *dmawp;
 
dmawp = (unsigned short *) dma_base_addr[dmanr];
dmawp[MCFDMA_BCR] = (unsigned short)count;
 
#ifdef DMA_DEBUG
printk("%s: Setting count %x for chan %d\n",
__FUNCTION__, (unsigned short)count , dmanr);
#endif DMA_DEBUG
 
}
 
/* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
* Otherwise, it returns the number of _bytes_ left to transfer.
*
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
{
volatile unsigned short *dmawp;
unsigned short count;
 
dmawp = (unsigned short *) dma_base_addr[dmanr];
count = dmawp[MCFDMA_BCR];
return((int) count);
}
 
#else
#define MAX_DMA_CHANNELS 8
#endif /* CONFIG_COLDFIRE */
 
/* Don't define MAX_DMA_ADDRESS; it's useless on the m68k/coldfire and any
occurrence should be flagged as an error. */
 
/* These are in kernel/dma.c: */
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
extern void free_dma(unsigned int dmanr); /* release it again */
#endif /* _M68K_DMA_H */
/machdep.h
0,0 → 1,58
#ifndef _M68K_MACHDEP_H
#define _M68K_MACHDEP_H
 
#define VULP(x) (*(volatile unsigned long*)(x))
#define VUSP(x) (*(volatile unsigned short*)(x))
#define VUCP(x) (*(volatile unsigned char*)(x))
 
/*
#define M68K_REGBASE_328 (0xFFFF0000)
#define M68K_REG_IMR VULP(M68K_REGBASE_328 + 0xF304)
*/
 
struct pt_regs;
struct kbd_repeat;
struct mktime;
struct hwclk_time;
struct gendisk;
struct buffer_head;
 
extern void config_BSP(char *commandp, int size);
 
extern void (*mach_sched_init) (void (*handler)(int, void *, struct pt_regs *));
extern void (*mach_tick)(void);
/* machine dependent keyboard functions */
extern int (*mach_keyb_init) (void);
extern int (*mach_kbdrate) (struct kbd_repeat *);
extern void (*mach_kbd_leds) (unsigned int);
/* machine dependent irq functions */
extern void (*mach_init_IRQ) (void);
extern void (*(*mach_default_handler)[]) (int, void *, struct pt_regs *);
extern int (*mach_request_irq) (unsigned int irq, void (*handler)(int, void *, struct pt_regs *),
unsigned long flags, const char *devname, void *dev_id);
extern int (*mach_free_irq) (unsigned int irq, void *dev_id);
extern void (*mach_enable_irq) (unsigned int irq);
extern void (*mach_disable_irq) (unsigned int irq);
extern int (*mach_get_irq_list) (char *buf);
extern int (*mach_process_int) (int irq, struct pt_regs *fp);
extern void (*mach_trap_init) (void);
/* machine dependent timer functions */
extern unsigned long (*mach_gettimeoffset)(void);
extern void (*mach_gettod)(int *year, int *mon, int *day, int *hour,
int *min, int *sec);
extern int (*mach_hwclk)(int, struct hwclk_time*);
extern int (*mach_set_clock_mmss)(unsigned long);
extern void (*mach_mksound)( unsigned int count, unsigned int ticks );
extern void (*mach_reset)( void );
extern int (*mach_floppy_init) (void);
extern unsigned long (*mach_hd_init) (unsigned long, unsigned long);
extern void (*mach_hd_setup)(char *, int *);
extern void (*waitbut)(void);
extern struct fb_info *(*mach_fb_init)(long *);
extern long mach_max_dma_address;
extern void (*mach_debug_init)(void);
extern void (*mach_video_setup)(char *, int *);
extern void (*mach_floppy_setup)(char *, int *);
extern void (*mach_floppy_eject)(void);
 
#endif /* _M68K_MACHDEP_H */
/mmu_context.h
0,0 → 1,17
#ifndef __68K_MMU_CONTEXT_H
#define __68K_MMU_CONTEXT_H
 
#include <linux/config.h>
 
/*
* get a new mmu context.. do we need this on the m68k?
*/
#ifdef CONFIG_SHGLCORE
#define get_mmu_context(x) do { \
*(volatile unsigned char *)0xfffa13 |= 0x80; /* turn off the LED */\
} while (0)
#else
#define get_mmu_context(x) do { } while (0)
#endif
 
#endif
/checksum.h
0,0 → 1,128
#ifndef _M68K_CHECKSUM_H
#define _M68K_CHECKSUM_H
 
#include <linux/config.h>
 
/*
* computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit)
*
* returns a 32-bit number suitable for feeding into itself
* or csum_tcpudp_magic
*
* this function must be called with even lengths, except
* for the last fragment, which may be odd
*
* it's best to have buff aligned on a 32-bit boundary
*/
unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum);
 
/*
* the same as csum_partial_copy, but copies from src while it
* checksums
*
* here even more important to align src and dst on a 32-bit (or even
* better 64-bit) boundary
*/
 
unsigned int csum_partial_copy(const char *src, char *dst, int len, int sum);
 
 
/*
* the same as csum_partial_copy, but copies from user space.
*
* here even more important to align src and dst on a 32-bit (or even
* better 64-bit) boundary
*/
 
unsigned int csum_partial_copy_fromuser(const char *src, char *dst, int len, int sum);
 
unsigned short ip_fast_csum(unsigned char *iph, unsigned int ihl);
 
#ifdef BLASTED_MOTOROLA_CODE
/*
* This is a version of ip_compute_csum() optimized for IP headers,
* which always checksum on 4 octet boundaries.
*
*/
static inline unsigned short
ip_fast_csum(unsigned char *iph, unsigned int ihl)
{
unsigned int sum = 0;
 
__asm__ ("subqw #1,%2\n"
"1:\t"
"movel %1@+,%/d0\n\t"
"addxl %/d0,%0\n\t"
"dbra %2,1b\n\t"
"movel %0,%/d0\n\t"
"swap %/d0\n\t"
"addxw %/d0,%0\n\t"
"clrw %/d0\n\t"
"addxw %/d0,%0\n\t"
: "=d" (sum), "=a" (iph), "=d" (ihl)
: "0" (sum), "1" (iph), "2" (ihl)
: "d0");
return ~sum;
}
#endif
 
/*
* Fold a partial checksum
*/
 
static inline unsigned int csum_fold(unsigned int sum)
{
#ifdef CONFIG_COLDFIRE
sum = (sum & 0xffff) + (sum >> 16);
sum = (sum & 0xffff) + (sum >> 16);
#else
unsigned int tmp = sum;
__asm__("swap %1\n\t"
"addw %1, %0\n\t"
"clrw %1\n\t"
"addxw %1, %0"
: "=&d" (sum), "=&d" (tmp)
: "0" (sum), "1" (sum));
#endif
return ~sum;
}
 
 
/*
* computes the checksum of the TCP/UDP pseudo-header
* returns a 16-bit checksum, already complemented
*/
 
static inline unsigned short int
csum_tcpudp_magic(unsigned long saddr, unsigned long daddr, unsigned short len,
unsigned short proto, unsigned int sum)
{
__asm__ ("addl %1,%0\n\t"
"addxl %4,%0\n\t"
"addxl %5,%0\n\t"
"clrl %1\n\t"
"addxl %1,%0"
: "=&d" (sum), "=&d" (saddr)
: "0" (daddr), "1" (saddr), "d" (len + proto),
"d"(sum));
return csum_fold(sum);
}
 
/*
* this routine is used for miscellaneous IP-like checksums, mainly
* in icmp.c
*/
 
#ifdef BLASTED_MOTOROLA_CODE
static inline unsigned short
ip_compute_csum(unsigned char * buff, int len)
{
return csum_fold (csum_partial(buff, len, 0));
}
#else
extern unsigned short
ip_compute_csum(const unsigned char * buff, int len);
#endif
 
#endif /* _M68K_CHECKSUM_H */
/statfs.h
0,0 → 1,25
#ifndef _M68K_STATFS_H
#define _M68K_STATFS_H
 
#ifndef __KERNEL_STRICT_NAMES
 
#include <linux/types.h>
 
typedef __kernel_fsid_t fsid_t;
 
#endif
 
struct statfs {
long f_type;
long f_bsize;
long f_blocks;
long f_bfree;
long f_bavail;
long f_files;
long f_ffree;
__kernel_fsid_t f_fsid;
long f_namelen;
long f_spare[6];
};
 
#endif /* _M68K_STATFS_H */
/MC68332.h
0,0 → 1,153
 
/* include/asm-m68knommu/MC68332.h: '332 control registers
*
* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
* The Silver Hammer Group, Ltd.
*
*/
 
#ifndef _MC68332_H_
#define _MC68332_H_
 
#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
#define WORD_REF(addr) (*((volatile unsigned short*)addr))
 
#define PORTE_ADDR 0xfffa11
#define PORTE BYTE_REF(PORTE_ADDR)
#define DDRE_ADDR 0xfffa15
#define DDRE BYTE_REF(DDRE_ADDR)
#define PEPAR_ADDR 0xfffa17
#define PEPAR BYTE_REF(PEPAR_ADDR)
 
#define PORTF_ADDR 0xfffa19
#define PORTF BYTE_REF(PORTF_ADDR)
#define DDRF_ADDR 0xfffa1d
#define DDRF BYTE_REF(DDRF_ADDR)
#define PFPAR_ADDR 0xfffa1f
#define PFPAR BYTE_REF(PFPAR_ADDR)
 
#define PORTQS_ADDR 0xfffc15
#define PORTQS BYTE_REF(PORTQS_ADDR)
#define DDRQS_ADDR 0xfffc17
#define DDRQS BYTE_REF(DDRQS_ADDR)
#define PQSPAR_ADDR 0xfffc16
#define PQSPAR BYTE_REF(PQSPAR_ADDR)
 
#define CSPAR0_ADDR 0xFFFA44
#define CSPAR0 WORD_REF(CSPAR0_ADDR)
#define CSPAR1_ADDR 0xFFFA46
#define CSPAR1 WORD_REF(CSPAR1_ADDR)
#define CSARBT_ADDR 0xFFFA48
#define CSARBT WORD_REF(CSARBT_ADDR)
#define CSOPBT_ADDR 0xFFFA4A
#define CSOPBT WORD_REF(CSOPBT_ADDR)
#define CSBAR0_ADDR 0xFFFA4C
#define CSBAR0 WORD_REF(CSBAR0_ADDR)
#define CSOR0_ADDR 0xFFFA4E
#define CSOR0 WORD_REF(CSOR0_ADDR)
#define CSBAR1_ADDR 0xFFFA50
#define CSBAR1 WORD_REF(CSBAR1_ADDR)
#define CSOR1_ADDR 0xFFFA52
#define CSOR1 WORD_REF(CSOR1_ADDR)
#define CSBAR2_ADDR 0xFFFA54
#define CSBAR2 WORD_REF(CSBAR2_ADDR)
#define CSOR2_ADDR 0xFFFA56
#define CSOR2 WORD_REF(CSOR2_ADDR)
#define CSBAR3_ADDR 0xFFFA58
#define CSBAR3 WORD_REF(CSBAR3_ADDR)
#define CSOR3_ADDR 0xFFFA5A
#define CSOR3 WORD_REF(CSOR3_ADDR)
#define CSBAR4_ADDR 0xFFFA5C
#define CSBAR4 WORD_REF(CSBAR4_ADDR)
#define CSOR4_ADDR 0xFFFA5E
#define CSOR4 WORD_REF(CSOR4_ADDR)
#define CSBAR5_ADDR 0xFFFA60
#define CSBAR5 WORD_REF(CSBAR5_ADDR)
#define CSOR5_ADDR 0xFFFA62
#define CSOR5 WORD_REF(CSOR5_ADDR)
#define CSBAR6_ADDR 0xFFFA64
#define CSBAR6 WORD_REF(CSBAR6_ADDR)
#define CSOR6_ADDR 0xFFFA66
#define CSOR6 WORD_REF(CSOR6_ADDR)
#define CSBAR7_ADDR 0xFFFA68
#define CSBAR7 WORD_REF(CSBAR7_ADDR)
#define CSOR7_ADDR 0xFFFA6A
#define CSOR7 WORD_REF(CSOR7_ADDR)
#define CSBAR8_ADDR 0xFFFA6C
#define CSBAR8 WORD_REF(CSBAR8_ADDR)
#define CSOR8_ADDR 0xFFFA6E
#define CSOR8 WORD_REF(CSOR8_ADDR)
#define CSBAR9_ADDR 0xFFFA70
#define CSBAR9 WORD_REF(CSBAR9_ADDR)
#define CSOR9_ADDR 0xFFFA72
#define CSOR9 WORD_REF(CSOR9_ADDR)
#define CSBAR10_ADDR 0xFFFA74
#define CSBAR10 WORD_REF(CSBAR10_ADDR)
#define CSOR10_ADDR 0xFFFA76
#define CSOR10 WORD_REF(CSOR10_ADDR)
 
#define CSOR_MODE_ASYNC 0x0000
#define CSOR_MODE_SYNC 0x8000
#define CSOR_MODE_MASK 0x8000
#define CSOR_BYTE_DISABLE 0x0000
#define CSOR_BYTE_UPPER 0x4000
#define CSOR_BYTE_LOWER 0x2000
#define CSOR_BYTE_BOTH 0x6000
#define CSOR_BYTE_MASK 0x6000
#define CSOR_RW_RSVD 0x0000
#define CSOR_RW_READ 0x0800
#define CSOR_RW_WRITE 0x1000
#define CSOR_RW_BOTH 0x1800
#define CSOR_RW_MASK 0x1800
#define CSOR_STROBE_DS 0x0400
#define CSOR_STROBE_AS 0x0000
#define CSOR_STROBE_MASK 0x0400
#define CSOR_DSACK_WAIT(x) (wait << 6)
#define CSOR_DSACK_FTERM (14 << 6)
#define CSOR_DSACK_EXTERNAL (15 << 6)
#define CSOR_DSACK_MASK 0x03c0
#define CSOR_SPACE_CPU 0x0000
#define CSOR_SPACE_USER 0x0010
#define CSOR_SPACE_SU 0x0020
#define CSOR_SPACE_BOTH 0x0030
#define CSOR_SPACE_MASK 0x0030
#define CSOR_IPL_ALL 0x0000
#define CSOR_IPL_PRIORITY(x) (x << 1)
#define CSOR_IPL_MASK 0x000e
#define CSOR_AVEC_ON 0x0001
#define CSOR_AVEC_OFF 0x0000
#define CSOR_AVEC_MASK 0x0001
 
#define CSBAR_ADDR(x) ((addr >> 11) << 3)
#define CSBAR_ADDR_MASK 0xfff8
#define CSBAR_BLKSIZE_2K 0x0000
#define CSBAR_BLKSIZE_8K 0x0001
#define CSBAR_BLKSIZE_16K 0x0002
#define CSBAR_BLKSIZE_64K 0x0003
#define CSBAR_BLKSIZE_128K 0x0004
#define CSBAR_BLKSIZE_256K 0x0005
#define CSBAR_BLKSIZE_512K 0x0006
#define CSBAR_BLKSIZE_1M 0x0007
#define CSBAR_BLKSIZE_MASK 0x0007
 
#define CSPAR_DISC 0
#define CSPAR_ALT 1
#define CSPAR_CS8 2
#define CSPAR_CS16 3
#define CSPAR_MASK 3
 
#define CSPAR0_CSBOOT(x) (x << 0)
#define CSPAR0_CS0(x) (x << 2)
#define CSPAR0_CS1(x) (x << 4)
#define CSPAR0_CS2(x) (x << 6)
#define CSPAR0_CS3(x) (x << 8)
#define CSPAR0_CS4(x) (x << 10)
#define CSPAR0_CS5(x) (x << 12)
 
#define CSPAR1_CS6(x) (x << 0)
#define CSPAR1_CS7(x) (x << 2)
#define CSPAR1_CS8(x) (x << 4)
#define CSPAR1_CS9(x) (x << 6)
#define CSPAR1_CS10(x) (x << 8)
 
#endif
/shmparam.h
0,0 → 1,44
#ifndef _M68K_SHMPARAM_H
#define _M68K_SHMPARAM_H
 
/* address range for shared memory attaches if no address passed to shmat() */
#define SHM_RANGE_START 0xC0000000
#define SHM_RANGE_END 0xD0000000
 
/*
* Format of a swap-entry for shared memory pages currently out in
* swap space (see also mm/swap.c).
*
* SWP_TYPE = SHM_SWP_TYPE
* SWP_OFFSET is used as follows:
*
* bits 0..6 : id of shared memory segment page belongs to (SHM_ID)
* bits 7..21: index of page within shared memory segment (SHM_IDX)
* (actually fewer bits get used since SHMMAX is so low)
*/
 
/*
* Keep _SHM_ID_BITS as low as possible since SHMMNI depends on it and
* there is a static array of size SHMMNI.
*/
#define _SHM_ID_BITS 7
#define SHM_ID_MASK ((1<<_SHM_ID_BITS)-1)
 
#define SHM_IDX_SHIFT (_SHM_ID_BITS)
#define _SHM_IDX_BITS 15
#define SHM_IDX_MASK ((1<<_SHM_IDX_BITS)-1)
 
/*
* _SHM_ID_BITS + _SHM_IDX_BITS must be <= 24 on the i386 and
* SHMMAX <= (PAGE_SIZE << _SHM_IDX_BITS).
*/
 
#define SHMMAX 0x1000000 /* max shared seg size (bytes) */
#define SHMMIN 1 /* really PAGE_SIZE */ /* min shared seg size (bytes) */
#define SHMMNI (1<<_SHM_ID_BITS) /* max num of segs system wide */
#define SHMALL /* max shm system wide (pages) */ \
(1<<(_SHM_IDX_BITS+_SHM_ID_BITS))
#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
#define SHMSEG SHMMNI /* max shared segs per process */
 
#endif /* _M68K_SHMPARAM_H */
/anchor.h
0,0 → 1,99
/****************************************************************************/
 
/*
* anchor.h -- Anchor CO-MEM Lite PCI host bridge part.
*
* (C) Copyright 2000, Moreton Bay (www.moreton.com.au)
*/
 
/****************************************************************************/
#ifndef anchor_h
#define anchor_h
/****************************************************************************/
 
/*
* Define basic addressing info.
*/
#define COMEM_BASE 0x80000000 /* Base of CO-MEM address space */
#define COMEM_IRQ 25 /* IRQ of anchor part */
 
 
/*
* 4-byte registers of CO-MEM, so adjust register addresses for
* easy access. Handy macro for word access too.
*/
#define LREG(a) ((a) >> 2)
#define WREG(a) ((a) >> 1)
 
 
/*
* Define base addresses within CO-MEM Lite register address space.
*/
#define COMEM_I2O 0x0000 /* I2O registers */
#define COMEM_OPREGS 0x0400 /* Operation registers */
#define COMEM_PCIBUS 0x2000 /* Direct access to PCI bus */
#define COMEM_SHMEM 0x4000 /* Shared memory region */
 
 
/*
* Define CO-MEM Registers.
*/
#define COMEM_I2OHISR 0x0030 /* I2O host interrupt status */
#define COMEM_I2OHIMR 0x0034 /* I2O host interrupt mask */
#define COMEM_I2OLISR 0x0038 /* I2O local interrupt status */
#define COMEM_I2OLIMR 0x003c /* I2O local interrupt mask */
#define COMEM_IBFPFIFO 0x0040 /* I2O inbound free/post FIFO */
#define COMEM_OBPFFIFO 0x0044 /* I2O outbound post/free FIFO */
#define COMEM_IBPFFIFO 0x0048 /* I2O inbound post/free FIFO */
#define COMEM_OBFPFIFO 0x004c /* I2O outbound free/post FIFO */
 
#define COMEM_DAHBASE 0x0460 /* Direct access base address */
 
#define COMEM_NVCMD 0x04a0 /* I2C serial command */
#define COMEM_NVREAD 0x04a4 /* I2C serial read */
#define COMEM_NVSTAT 0x04a8 /* I2C status */
 
#define COMEM_DMALBASE 0x04b0 /* DMA local base address */
#define COMEM_DMAHBASE 0x04b4 /* DMA host base address */
#define COMEM_DMASIZE 0x04b8 /* DMA size */
#define COMEM_DMACTL 0x04bc /* DMA control */
 
#define COMEM_HCTL 0x04e0 /* Host control */
#define COMEM_HINT 0x04e4 /* Host interrupt control/status */
#define COMEM_HLDATA 0x04e8 /* Host to local data mailbox */
#define COMEM_LINT 0x04f4 /* Local interrupt contole status */
#define COMEM_LHDATA 0x04f8 /* Local to host data mailbox */
 
#define COMEM_LBUSCFG 0x04fc /* Local bus configuration */
 
 
/*
* Commands and flags for use with Direct Access Register.
*/
#define COMEM_DA_IACK 0x00000000 /* Interrupt acknowledge (read) */
#define COMEM_DA_SPCL 0x00000010 /* Special cycle (write) */
#define COMEM_DA_MEMRD 0x00000064 /* Memory read cycle */
#define COMEM_DA_MEMWR 0x00000074 /* Memory write cycle */
#define COMEM_DA_IORD 0x00000022 /* I/O read cycle */
#define COMEM_DA_IOWR 0x00000032 /* I/O write cycle */
#define COMEM_DA_CFGRD 0x000000a6 /* Configuration read cycle */
#define COMEM_DA_CFGWR 0x000000b6 /* Configuration write cycle */
 
#define COMEM_DA_ADDR(a) ((a) & 0xffffe000)
 
#define COMEM_DA_OFFSET(a) ((a) & 0x00001fff)
 
 
/*
* The PCI bus in the eLIA board is limited in what slots will
* actually be used - there is only really 4 possibilties.
* Define valid device numbers.
*/
#define COMEM_MINDEV 0 /* Minimum valid DEVICE */
#define COMEM_MAXDEV 3 /* Maximum valid DEVICE */
 
#define COMEM_MAXPCI (COMEM_MAXDEV+1) /* Maximum PCI devices */
 
 
/****************************************************************************/
#endif /* anchor_h */
/elia.h
0,0 → 1,80
/****************************************************************************/
 
/*
* elia.h -- Moreton Bay eLIA platform support.
*
* (C) Copyright 1999-2000, Moreton Bay (www.moreton.com.au)
*/
 
/****************************************************************************/
#ifndef elia_h
#define elia_h
/****************************************************************************/
 
#include <linux/config.h>
#include <asm/coldfire.h>
 
#ifdef CONFIG_eLIA
 
/*
* The eLIA board has 2 programmable LEDs. We use one as the
* alive indicator, the other is user configurable.
* The serial port DTR and DCD lines are also on the Parallel I/O
* as well, so define those too.
*/
#define eLIA_LEDDIAG 0x2000
#define eLIA_USER 0x1000
 
#define eLIA_DCD1 0x0001
#define eLIA_DCD0 0x0002
#define eLIA_DTR1 0x0004
#define eLIA_DTR0 0x0008
 
#define eLIA_PCIRESET 0x0020
 
 
/*
* User space routines for back door access to the LEDs :-)
* This is a complete and utter bastard hack... But quick...
* The "on" pattern turns on some LEDs permanently. The "off"
* pattern turns some LEDs off permantly. The "flash" pattern
* will flash a particular LED pattern.
*/
#define LEDON(x) *((unsigned char *) 0x3fe) |= (x)
#define LEDOFF(x) *((unsigned char *) 0x3fe) &= ~(x)
#define LEDFLASH(x) *((unsigned char *) 0x3ff) = (x)
 
#define GETLED() *((unsigned char *) 0x3fe)
#define GETFLASH() *((unsigned char *) 0x3ff)
 
 
/*
* Kernel macros to set and unset the LEDs.
*/
#ifndef __ASSEMBLY__
extern unsigned short ppdata;
#endif /* __ASSEMBLY__ */
 
/*
* The following macros set and unset the LEDS.
*/
#define setledpp(x) \
*((volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT)) = \
(ppdata &= ~(x))
 
#define unsetledpp(x) \
*((volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT)) = \
(ppdata |= (x))
 
 
/*
* Panic setup for eLIA. There may be no console so it may be
* difficult to tell if the kernel has paniced or not. So this little
* macro will turn on all the LEDS - for a visual indicator of panic.
*/
#define nettel_panic() { cli(); setledpp(0x3000); }
 
#endif /* CONFIG_eLIA */
 
/****************************************************************************/
#endif /* elia_h */
/atomic.h
0,0 → 1,62
#ifndef __ARCH_M68K_ATOMIC__
#define __ARCH_M68K_ATOMIC__
 
#include <linux/config.h>
 
/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc..
*/
 
/*
* We do not have SMP m68k systems, so we don't have to deal with that.
*/
 
typedef int atomic_t;
 
static __inline__ void atomic_add(atomic_t i, atomic_t *v)
{
#ifdef CONFIG_COLDFIRE
__asm__ __volatile__(
"movel %1,%/d0\t\n"
"addl %/d0,%0"
:
: "m" (*v), "id" (i)
: "d0");
#else
__asm__ __volatile__("addl %1,%0" : : "m" (*v), "id" (i));
#endif
}
 
static __inline__ void atomic_sub(atomic_t i, atomic_t *v)
{
#ifdef CONFIG_COLDFIRE
__asm__ __volatile__(
"movel %1,%/d0\t\n"
"subl %/d0,%0"
:
: "m" (*v), "id" (i)
: "d0");
#else
__asm__ __volatile__("subl %1,%0" : : "m" (*v), "id" (i));
#endif
}
 
static __inline__ void atomic_inc(atomic_t *v)
{
__asm__ __volatile__("addql #1,%0" : : "m" (*v));
}
 
static __inline__ void atomic_dec(atomic_t *v)
{
__asm__ __volatile__("subql #1,%0" : : "m" (*v));
}
 
static __inline__ int atomic_dec_and_test(atomic_t *v)
{
char c;
__asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c) : "m" (*v));
return c != 0;
}
 
#endif /* __ARCH_M68K_ATOMIC __ */
/pgtable.h
0,0 → 1,774
#ifndef _M68K_PGTABLE_H
#define _M68K_PGTABLE_H
 
extern unsigned long mm_vtop(unsigned long addr) __attribute__ ((const));
extern unsigned long mm_ptov(unsigned long addr) __attribute__ ((const));
 
#define VTOP(addr) (mm_vtop((unsigned long)(addr)))
#define PTOV(addr) (mm_ptov((unsigned long)(addr)))
 
#ifndef NO_MM
 
#include <asm/setup.h>
 
#ifndef __ASSEMBLY__
#include <linux/config.h>
 
/*
* This file contains the functions and defines necessary to modify and use
* the m68k page table tree.
*/
 
/*
* flush all atc entries (user-space entries only for the 680[46]0).
*/
static inline void __flush_tlb(void)
{
if (CPU_IS_040_OR_060)
__asm__ __volatile__(".word 0xf510\n"::); /* pflushan */
else
__asm__ __volatile__("pflusha\n"::);
}
 
static inline void __flush_tlb_one(unsigned long addr)
{
if (CPU_IS_040_OR_060) {
register unsigned long a0 __asm__ ("a0") = addr;
__asm__ __volatile__(".word 0xf508" /* pflush (%a0) */
: : "a" (a0));
} else
__asm__ __volatile__("pflush #0,#0,(%0)" : : "a" (addr));
}
 
#define flush_tlb() __flush_tlb()
 
/*
* flush all atc entries (both kernel and user-space entries).
*/
static inline void flush_tlb_all(void)
{
if (CPU_IS_040_OR_060)
__asm__ __volatile__(".word 0xf518\n"::); /* pflusha */
else
__asm__ __volatile__("pflusha\n"::);
}
 
static inline void flush_tlb_mm(struct mm_struct *mm)
{
if (mm == current->mm)
__flush_tlb();
}
 
static inline void flush_tlb_page(struct vm_area_struct *vma,
unsigned long addr)
{
if (vma->vm_mm == current->mm)
__flush_tlb_one(addr);
}
 
static inline void flush_tlb_range(struct mm_struct *mm,
unsigned long start, unsigned long end)
{
if (mm == current->mm)
__flush_tlb();
}
 
/* Certain architectures need to do special things when pte's
* within a page table are directly modified. Thus, the following
* hook is made available.
*/
#define set_pte(pteptr, pteval) do{ \
((*(pteptr)) = (pteval)); \
if (CPU_IS_060) \
__asm__ __volatile__(".word 0xf518\n"::); /* pflusha */ \
} while(0)
 
 
/* PMD_SHIFT determines the size of the area a second-level page table can map */
#define PMD_SHIFT 22
#define PMD_SIZE (1UL << PMD_SHIFT)
#define PMD_MASK (~(PMD_SIZE-1))
 
/* PGDIR_SHIFT determines what a third-level page table entry can map */
#define PGDIR_SHIFT 25
#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
#define PGDIR_MASK (~(PGDIR_SIZE-1))
 
/*
* entries per page directory level: the m68k is configured as three-level,
* so we do have PMD level physically.
*/
#define PTRS_PER_PTE 1024
#define PTRS_PER_PMD 8
#define PTRS_PER_PGD 128
 
/* the no. of pointers that fit on a page: this will go away */
#define PTRS_PER_PAGE (PAGE_SIZE/sizeof(void*))
 
typedef pgd_t pgd_table[PTRS_PER_PGD];
typedef pmd_t pmd_table[PTRS_PER_PMD];
typedef pte_t pte_table[PTRS_PER_PTE];
 
#define PGD_TABLES_PER_PAGE (PAGE_SIZE/sizeof(pgd_table))
#define PMD_TABLES_PER_PAGE (PAGE_SIZE/sizeof(pmd_table))
#define PTE_TABLES_PER_PAGE (PAGE_SIZE/sizeof(pte_table))
 
typedef pgd_table pgd_tablepage[PGD_TABLES_PER_PAGE];
typedef pmd_table pmd_tablepage[PMD_TABLES_PER_PAGE];
typedef pte_table pte_tablepage[PTE_TABLES_PER_PAGE];
 
/* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START ((high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
 
#endif /* __ASSEMBLY__ */
 
/*
* Definitions for MMU descriptors
*/
#define _PAGE_PRESENT 0x001
#define _PAGE_SHORT 0x002
#define _PAGE_RONLY 0x004
#define _PAGE_ACCESSED 0x008
#define _PAGE_DIRTY 0x010
#define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */
#define _PAGE_COW 0x800 /* implemented in software */
#define _PAGE_NOCACHE030 0x040 /* 68030 no-cache mode */
#define _PAGE_NOCACHE 0x060 /* 68040 cache mode, non-serialized */
#define _PAGE_NOCACHE_S 0x040 /* 68040 no-cache mode, serialized */
#define _PAGE_CACHE040 0x020 /* 68040 cache mode, cachable, copyback */
#define _PAGE_CACHE040W 0x000 /* 68040 cache mode, cachable, write-through */
 
#define _DESCTYPE_MASK 0x003
 
#define _CACHEMASK040 (~0x060)
#define _TABLE_MASK (0xfffffe00)
 
#define _PAGE_TABLE (_PAGE_SHORT)
#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_NOCACHE)
 
#ifndef __ASSEMBLY__
 
/* This is the cache mode to be used for pages containing page descriptors for
* processors >= '040. It is in pte_mknocache(), and the variable is defined
* and initialized in head.S */
extern int m68k_pgtable_cachemode;
 
#if defined(CONFIG_M68040_OR_M68060_ONLY)
#define mm_cachebits _PAGE_CACHE040
#elif defined(CONFIG_M68020_OR_M68030_ONLY)
#define mm_cachebits 0
#else
extern unsigned long mm_cachebits;
#endif
 
#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED | mm_cachebits)
#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | mm_cachebits)
#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED | mm_cachebits)
#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED | mm_cachebits)
#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | _PAGE_ACCESSED | mm_cachebits)
 
/* Alternate definitions that are compile time constants, for
initializing protection_map. The cachebits are fixed later. */
#define PAGE_NONE_C __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED)
#define PAGE_SHARED_C __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
#define PAGE_COPY_C __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED)
#define PAGE_READONLY_C __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED)
 
/*
* The m68k can't do page protection for execute, and considers that the same are read.
* Also, write permissions imply read permissions. This is the closest we can get..
*/
#define __P000 PAGE_NONE_C
#define __P001 PAGE_READONLY_C
#define __P010 PAGE_COPY_C
#define __P011 PAGE_COPY_C
#define __P100 PAGE_READONLY_C
#define __P101 PAGE_READONLY_C
#define __P110 PAGE_COPY_C
#define __P111 PAGE_COPY_C
 
#define __S000 PAGE_NONE_C
#define __S001 PAGE_READONLY_C
#define __S010 PAGE_SHARED_C
#define __S011 PAGE_SHARED_C
#define __S100 PAGE_READONLY_C
#define __S101 PAGE_READONLY_C
#define __S110 PAGE_SHARED_C
#define __S111 PAGE_SHARED_C
 
/* zero page used for uninitialized stuff */
extern unsigned long empty_zero_page;
 
/*
* BAD_PAGETABLE is used when we need a bogus page-table, while
* BAD_PAGE is used for a bogus page.
*
* ZERO_PAGE is a global shared page that is always zero: used
* for zero-mapped memory areas etc..
*/
extern pte_t __bad_page(void);
extern pte_t * __bad_pagetable(void);
 
#define BAD_PAGETABLE __bad_pagetable()
#define BAD_PAGE __bad_page()
#define ZERO_PAGE empty_zero_page
 
/* number of bits that fit into a memory pointer */
#define BITS_PER_PTR (8*sizeof(unsigned long))
 
/* to align the pointer to a pointer address */
#define PTR_MASK (~(sizeof(void*)-1))
 
/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
/* 64-bit machines, beware! SRB. */
#define SIZEOF_PTR_LOG2 2
 
/* to find an entry in a page-table */
#define PAGE_PTR(address) \
((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
 
extern unsigned long high_memory;
 
/* For virtual address to physical address conversion */
extern unsigned long mm_vtop(unsigned long addr) __attribute__ ((const));
extern unsigned long mm_ptov(unsigned long addr) __attribute__ ((const));
#define VTOP(addr) (mm_vtop((unsigned long)(addr)))
#define PTOV(addr) (mm_ptov((unsigned long)(addr)))
 
/*
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
*/
extern inline pte_t mk_pte(unsigned long page, pgprot_t pgprot)
{ pte_t pte; pte_val(pte) = VTOP(page) | pgprot_val(pgprot); return pte; }
 
extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
 
extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
{
int i;
 
ptep = (pte_t *) VTOP(ptep);
for (i = 0; i < 16; i++, ptep += PTRS_PER_PTE/16)
pmdp->pmd[i] = _PAGE_TABLE | _PAGE_ACCESSED | (unsigned long)ptep;
}
 
/* early termination version of the above */
extern inline void pmd_set_et(pmd_t * pmdp, pte_t * ptep)
{
int i;
 
ptep = (pte_t *) VTOP(ptep);
for (i = 0; i < 16; i++, ptep += PTRS_PER_PTE/16)
pmdp->pmd[i] = _PAGE_PRESENT | _PAGE_ACCESSED | (unsigned long)ptep;
}
 
extern inline void pgd_set(pgd_t * pgdp, pmd_t * pmdp)
{ pgd_val(*pgdp) = _PAGE_TABLE | _PAGE_ACCESSED | VTOP(pmdp); }
 
extern inline unsigned long pte_page(pte_t pte)
{ return PTOV(pte_val(pte) & PAGE_MASK); }
 
extern inline unsigned long pmd_page2(pmd_t *pmd)
{ return PTOV(pmd_val(*pmd) & _TABLE_MASK); }
#define pmd_page(pmd) pmd_page2(&(pmd))
 
extern inline unsigned long pgd_page(pgd_t pgd)
{ return PTOV(pgd_val(pgd) & _TABLE_MASK); }
 
extern inline int pte_none(pte_t pte) { return !pte_val(pte); }
extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; }
extern inline void pte_clear(pte_t *ptep) { pte_val(*ptep) = 0; }
 
extern inline int pmd_none2(pmd_t *pmd) { return !pmd_val(*pmd); }
#define pmd_none(pmd) pmd_none2(&(pmd))
extern inline int pmd_bad2(pmd_t *pmd) { return (pmd_val(*pmd) & _DESCTYPE_MASK) != _PAGE_TABLE || pmd_page(*pmd) > high_memory; }
#define pmd_bad(pmd) pmd_bad2(&(pmd))
extern inline int pmd_present2(pmd_t *pmd) { return pmd_val(*pmd) & _PAGE_TABLE; }
#define pmd_present(pmd) pmd_present2(&(pmd))
extern inline void pmd_clear(pmd_t * pmdp)
{
short i;
 
for (i = 15; i >= 0; i--)
pmdp->pmd[i] = 0;
}
 
extern inline int pgd_none(pgd_t pgd) { return !pgd_val(pgd); }
extern inline int pgd_bad(pgd_t pgd) { return (pgd_val(pgd) & _DESCTYPE_MASK) != _PAGE_TABLE || pgd_page(pgd) > high_memory; }
extern inline int pgd_present(pgd_t pgd) { return pgd_val(pgd) & _PAGE_TABLE; }
 
extern inline void pgd_clear(pgd_t * pgdp) { pgd_val(*pgdp) = 0; }
 
/*
* The following only work if pte_present() is true.
* Undefined behaviour if not..
*/
extern inline int pte_read(pte_t pte) { return 1; }
extern inline int pte_write(pte_t pte) { return !(pte_val(pte) & _PAGE_RONLY); }
extern inline int pte_exec(pte_t pte) { return 1; }
extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
 
extern inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) |= _PAGE_RONLY; return pte; }
extern inline pte_t pte_rdprotect(pte_t pte) { return pte; }
extern inline pte_t pte_exprotect(pte_t pte) { return pte; }
extern inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
extern inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) &= ~_PAGE_RONLY; return pte; }
extern inline pte_t pte_mkread(pte_t pte) { return pte; }
extern inline pte_t pte_mkexec(pte_t pte) { return pte; }
extern inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
extern inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
extern inline pte_t pte_mknocache(pte_t pte)
{
pte_val(pte) = (pte_val(pte) & _CACHEMASK040) | m68k_pgtable_cachemode;
return pte;
}
extern inline pte_t pte_mkcache(pte_t pte) { pte_val(pte) = (pte_val(pte) & _CACHEMASK040) | _PAGE_CACHE040; return pte; }
 
/* to set the page-dir */
extern inline void SET_PAGE_DIR(struct task_struct * tsk, pgd_t * pgdir)
{
tsk->tss.crp[0] = 0x80000000 | _PAGE_TABLE;
tsk->tss.crp[1] = VTOP(pgdir);
if (tsk == current) {
if (CPU_IS_040_OR_060)
__asm__ __volatile__ ("movel %0@,%/d0\n\t"
".long 0x4e7b0806\n\t"
/* movec d0,urp */
: : "a" (&tsk->tss.crp[1])
: "d0");
else
__asm__ __volatile__ ("movec %/cacr,%/d0\n\t"
"oriw #0x0808,%/d0\n\t"
"movec %/d0,%/cacr\n\t"
"pmove %0@,%/crp\n\t"
: : "a" (&tsk->tss.crp[0])
: "d0");
}
}
 
#define PAGE_DIR_OFFSET(tsk,address) pgd_offset((tsk),(address))
 
/* to find an entry in a page-table-directory */
extern inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address)
{
return mm->pgd + (address >> PGDIR_SHIFT);
}
 
extern pgd_t swapper_pg_dir[128];
extern pgd_t kernel_pg_dir[128];
 
extern inline pgd_t * pgd_offset_k(unsigned long address)
{
return kernel_pg_dir + (address >> PGDIR_SHIFT);
}
 
 
/* Find an entry in the second-level page table.. */
extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
{
return (pmd_t *) pgd_page(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PMD-1));
}
 
/* Find an entry in the third-level page table.. */
extern inline pte_t * pte_offset(pmd_t * pmdp, unsigned long address)
{
return (pte_t *) pmd_page(*pmdp) + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
}
 
/*
* Allocate and free page tables. The xxx_kernel() versions are
* used to allocate a kernel page table - this turns on ASN bits
* if any.
*/
 
extern inline void nocache_page (unsigned long vaddr)
{
if (CPU_IS_040_OR_060) {
pgd_t *dir;
pmd_t *pmdp;
pte_t *ptep;
 
if(CPU_IS_060)
__asm__ __volatile__ ("movel %0,%/a0\n\t"
".word 0xf470"
: : "g" (VTOP(vaddr))
: "a0");
 
dir = pgd_offset_k(vaddr);
pmdp = pmd_offset(dir,vaddr);
ptep = pte_offset(pmdp,vaddr);
*ptep = pte_mknocache(*ptep);
}
}
 
static inline void cache_page (unsigned long vaddr)
{
if (CPU_IS_040_OR_060) {
pgd_t *dir;
pmd_t *pmdp;
pte_t *ptep;
 
dir = pgd_offset_k(vaddr);
pmdp = pmd_offset(dir,vaddr);
ptep = pte_offset(pmdp,vaddr);
*ptep = pte_mkcache(*ptep);
}
}
 
 
extern const char PgtabStr_bad_pmd[];
extern const char PgtabStr_bad_pgd[];
extern const char PgtabStr_bad_pmdk[];
extern const char PgtabStr_bad_pgdk[];
 
extern inline void pte_free(pte_t * pte)
{
cache_page((unsigned long)pte);
free_page((unsigned long) pte);
}
 
extern inline pte_t * pte_alloc(pmd_t * pmd, unsigned long address)
{
address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
if (pmd_none(*pmd)) {
pte_t * page = (pte_t *)get_free_page(GFP_KERNEL);
if (pmd_none(*pmd)) {
if (page) {
nocache_page((unsigned long)page);
pmd_set(pmd,page);
return page + address;
}
pmd_set(pmd, BAD_PAGETABLE);
return NULL;
}
free_page((unsigned long)page);
}
if (pmd_bad(*pmd)) {
printk(PgtabStr_bad_pmd, pmd_val(*pmd));
pmd_set(pmd, BAD_PAGETABLE);
return NULL;
}
return (pte_t *) pmd_page(*pmd) + address;
}
 
extern pmd_t *get_pointer_table (void);
extern void free_pointer_table (pmd_t *);
extern pmd_t *get_kpointer_table (void);
extern void free_kpointer_table (pmd_t *);
 
extern inline void pmd_free(pmd_t * pmd)
{
free_pointer_table (pmd);
}
 
extern inline pmd_t * pmd_alloc(pgd_t * pgd, unsigned long address)
{
address = (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1);
if (pgd_none(*pgd)) {
pmd_t *page = get_pointer_table();
if (pgd_none(*pgd)) {
if (page) {
pgd_set(pgd, page);
return page + address;
}
pgd_set(pgd, (pmd_t *)BAD_PAGETABLE);
return NULL;
}
free_pointer_table(page);
}
if (pgd_bad(*pgd)) {
printk(PgtabStr_bad_pgd, pgd_val(*pgd));
pgd_set(pgd, (pmd_t *)BAD_PAGETABLE);
return NULL;
}
return (pmd_t *) pgd_page(*pgd) + address;
}
 
extern inline void pte_free_kernel(pte_t * pte)
{
cache_page((unsigned long)pte);
free_page((unsigned long) pte);
}
 
extern inline pte_t * pte_alloc_kernel(pmd_t * pmd, unsigned long address)
{
address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
if (pmd_none(*pmd)) {
pte_t * page = (pte_t *) get_free_page(GFP_KERNEL);
if (pmd_none(*pmd)) {
if (page) {
nocache_page((unsigned long)page);
pmd_set(pmd, page);
return page + address;
}
pmd_set(pmd, BAD_PAGETABLE);
return NULL;
}
free_page((unsigned long) page);
}
if (pmd_bad(*pmd)) {
printk(PgtabStr_bad_pmdk, pmd_val(*pmd));
pmd_set(pmd, BAD_PAGETABLE);
return NULL;
}
return (pte_t *) pmd_page(*pmd) + address;
}
 
extern inline void pmd_free_kernel(pmd_t * pmd)
{
free_kpointer_table(pmd);
}
 
extern inline pmd_t * pmd_alloc_kernel(pgd_t * pgd, unsigned long address)
{
address = (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1);
if (pgd_none(*pgd)) {
pmd_t *page = get_kpointer_table();
if (pgd_none(*pgd)) {
if (page) {
pgd_set(pgd, page);
return page + address;
}
pgd_set(pgd, (pmd_t *)BAD_PAGETABLE);
return NULL;
}
free_kpointer_table(page);
}
if (pgd_bad(*pgd)) {
printk(PgtabStr_bad_pgdk, pgd_val(*pgd));
pgd_set(pgd, (pmd_t *)BAD_PAGETABLE);
return NULL;
}
return (pmd_t *) pgd_page(*pgd) + address;
}
 
extern inline void pgd_free(pgd_t * pgd)
{
free_pointer_table ((pmd_t *) pgd);
}
 
extern inline pgd_t * pgd_alloc(void)
{
return (pgd_t *)get_pointer_table ();
}
 
#define flush_icache() \
do { \
if (CPU_IS_040_OR_060) \
asm __volatile__ ("nop; .word 0xf498 /* cinva %%ic */"); \
else \
asm __volatile__ ("movec %/cacr,%/d0;" \
"oriw %0,%/d0;" \
"movec %/d0,%/cacr" \
: /* no outputs */ \
: "i" (FLUSH_I) \
: "d0"); \
} while (0)
 
/*
* invalidate the cache for the specified memory range.
* It starts at the physical address specified for
* the given number of bytes.
*/
extern void cache_clear (unsigned long paddr, int len);
/*
* push any dirty cache in the specified memory range.
* It starts at the physical address specified for
* the given number of bytes.
*/
extern void cache_push (unsigned long paddr, int len);
 
/*
* push and invalidate pages in the specified user virtual
* memory range.
*/
extern void cache_push_v (unsigned long vaddr, int len);
 
/* cache code */
#define FLUSH_I_AND_D (0x00000808)
#define FLUSH_I (0x00000008)
 
/* This is needed whenever the virtual mapping of the current
process changes. */
#define __flush_cache_all() \
do { \
if (CPU_IS_040_OR_060) \
__asm__ __volatile__ ("nop; .word 0xf478\n" ::); \
else \
__asm__ __volatile__ ("movec %%cacr,%%d0\n\t" \
"orw %0,%%d0\n\t" \
"movec %%d0,%%cacr" \
: : "di" (FLUSH_I_AND_D) : "d0"); \
} while (0)
 
#define __flush_cache_030() \
do { \
if (CPU_IS_020_OR_030) \
__asm__ __volatile__ ("movec %%cacr,%%d0\n\t" \
"orw %0,%%d0\n\t" \
"movec %%d0,%%cacr" \
: : "di" (FLUSH_I_AND_D) : "d0"); \
} while (0)
 
#define flush_cache_all() __flush_cache_all()
 
extern inline void flush_cache_mm(struct mm_struct *mm)
{
#if FLUSH_VIRTUAL_CACHE_040
if (mm == current->mm) __flush_cache_all();
#else
if (mm == current->mm) __flush_cache_030();
#endif
}
 
extern inline void flush_cache_range(struct mm_struct *mm,
unsigned long start,
unsigned long end)
{
if (mm == current->mm){
#if FLUSH_VIRTUAL_CACHE_040
if (CPU_IS_040_OR_060)
cache_push_v(start, end-start);
else
#endif
__flush_cache_030();
}
}
 
extern inline void flush_cache_page(struct vm_area_struct *vma,
unsigned long vmaddr)
{
if (vma->vm_mm == current->mm){
#if FLUSH_VIRTUAL_CACHE_040
if (CPU_IS_040_OR_060)
cache_push_v(vmaddr, PAGE_SIZE);
else
#endif
__flush_cache_030();
}
}
 
/* Push the page at kernel virtual address and clear the icache */
extern inline void flush_page_to_ram (unsigned long address)
{
if (CPU_IS_040_OR_060) {
register unsigned long tmp __asm ("a0") = VTOP(address);
__asm__ __volatile__ ("nop\n\t"
".word 0xf470 /* cpushp %%dc,(%0) */\n\t"
".word 0xf490 /* cinvp %%ic,(%0) */"
: : "a" (tmp));
}
else
__asm volatile ("movec %%cacr,%%d0\n\t"
"orw %0,%%d0\n\t"
"movec %%d0,%%cacr"
: : "di" (FLUSH_I) : "d0");
}
 
/* Push n pages at kernel virtual address and clear the icache */
extern inline void flush_pages_to_ram (unsigned long address, int n)
{
if (CPU_IS_040_OR_060) {
while (n--) {
register unsigned long tmp __asm ("a0") = VTOP(address);
__asm__ __volatile__ ("nop\n\t"
".word 0xf470 /* cpushp %%dc,(%0) */\n\t"
".word 0xf490 /* cinvp %%ic,(%0) */"
: : "a" (tmp));
address += PAGE_SIZE;
}
}
else
__asm volatile ("movec %%cacr,%%d0\n\t"
"orw %0,%%d0\n\t"
"movec %%d0,%%cacr"
: : "di" (FLUSH_I) : "d0");
}
 
/*
* Check if the addr/len goes up to the end of a physical
* memory chunk. Used for DMA functions.
*/
int mm_end_of_chunk (unsigned long addr, int len);
 
/*
* Map some physical address range into the kernel address space. The
* code is copied and adapted from map_chunk().
*/
extern unsigned long kernel_map(unsigned long paddr, unsigned long size,
int nocacheflag, unsigned long *memavailp );
/*
* Change the cache mode of some kernel address range.
*/
extern void kernel_set_cachemode( unsigned long address, unsigned long size,
unsigned cmode );
 
/* Values for nocacheflag and cmode */
#define KERNELMAP_FULL_CACHING 0
#define KERNELMAP_NOCACHE_SER 1
#define KERNELMAP_NOCACHE_NONSER 2
#define KERNELMAP_NO_COPYBACK 3
 
/*
* The m68k doesn't have any external MMU info: the kernel page
* tables contain all the necessary information.
*/
extern inline void update_mmu_cache(struct vm_area_struct * vma,
unsigned long address, pte_t pte)
{
}
 
/*
* I don't know what is going on here, but since these were changed,
* swapping hasn't been working on the 68040.
*/
 
#define SWP_TYPE(entry) (((entry) >> 2) & 0x7f)
#if 0
#define SWP_OFFSET(entry) ((entry) >> 9)
#define SWP_ENTRY(type,offset) (((type) << 2) | ((offset) << 9))
#else
#define SWP_OFFSET(entry) ((entry) >> PAGE_SHIFT)
#define SWP_ENTRY(type,offset) (((type) << 2) | ((offset) << PAGE_SHIFT))
#endif
 
 
#endif /* __ASSEMBLY__ */
 
#else /* NO_MM */
 
extern inline void flush_cache_mm(struct mm_struct *mm)
{
}
 
extern inline void flush_cache_range(struct mm_struct *mm,
unsigned long start,
unsigned long end)
{
}
 
/* Push the page at kernel virtual address and clear the icache */
extern inline void flush_page_to_ram (unsigned long address)
{
}
 
/* Push n pages at kernel virtual address and clear the icache */
extern inline void flush_pages_to_ram (unsigned long address, int n)
{
}
 
#endif /* NO_MM */
 
#endif /* _M68K_PGTABLE_H */
/bootinfo.h
0,0 → 1,2
 
/* Nothing for m68knommu */
/termios.h
0,0 → 1,89
#ifndef _M68K_TERMIOS_H
#define _M68K_TERMIOS_H
 
#include <asm/termbits.h>
#include <asm/ioctls.h>
struct winsize {
unsigned short ws_row;
unsigned short ws_col;
unsigned short ws_xpixel;
unsigned short ws_ypixel;
};
 
#define NCC 8
struct termio {
unsigned short c_iflag; /* input mode flags */
unsigned short c_oflag; /* output mode flags */
unsigned short c_cflag; /* control mode flags */
unsigned short c_lflag; /* local mode flags */
unsigned char c_line; /* line discipline */
unsigned char c_cc[NCC]; /* control characters */
};
 
#ifdef __KERNEL__
/* intr=^C quit=^| erase=del kill=^U
eof=^D vtime=\0 vmin=\1 sxtc=\0
start=^Q stop=^S susp=^Z eol=\0
reprint=^R discard=^U werase=^W lnext=^V
eol2=\0
*/
#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
#endif
 
/* modem lines */
#define TIOCM_LE 0x001
#define TIOCM_DTR 0x002
#define TIOCM_RTS 0x004
#define TIOCM_ST 0x008
#define TIOCM_SR 0x010
#define TIOCM_CTS 0x020
#define TIOCM_CAR 0x040
#define TIOCM_RNG 0x080
#define TIOCM_DSR 0x100
#define TIOCM_CD TIOCM_CAR
#define TIOCM_RI TIOCM_RNG
 
/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
 
/* line disciplines */
#define N_TTY 0
#define N_SLIP 1
#define N_MOUSE 2
#define N_PPP 3
#define N_STRIP 4
 
#ifdef __KERNEL__
 
/*
* Translate a "termio" structure into a "termios". Ugh.
*/
extern inline void trans_from_termio(struct termio * termio,
struct termios * termios)
{
#define SET_LOW_BITS(x,y) ((x) = (0xffff0000 & (x)) | (y))
SET_LOW_BITS(termios->c_iflag, termio->c_iflag);
SET_LOW_BITS(termios->c_oflag, termio->c_oflag);
SET_LOW_BITS(termios->c_cflag, termio->c_cflag);
SET_LOW_BITS(termios->c_lflag, termio->c_lflag);
#undef SET_LOW_BITS
memcpy(termios->c_cc, termio->c_cc, NCC);
}
 
/*
* Translate a "termios" structure into a "termio". Ugh.
*/
extern inline void trans_to_termio(struct termios * termios,
struct termio * termio)
{
termio->c_iflag = termios->c_iflag;
termio->c_oflag = termios->c_oflag;
termio->c_cflag = termios->c_cflag;
termio->c_lflag = termios->c_lflag;
termio->c_line = termios->c_line;
memcpy(termio->c_cc, termios->c_cc, NCC);
}
 
#endif /* __KERNEL__ */
 
#endif /* _M68K_TERMIOS_H */
/m68en302.h
0,0 → 1,203
#ifndef _m68en302_h_
#define _m68en302_h_
 
 
 
#ifndef _m68302_h_
#include <asm/m68302.h>
#endif
 
 
 
//#define MOBARV 0xFFE000
#define MOBARV 0xF80000
#define MOBARREG 0xEE
 
#define IER MOBARV+2 /* INTERRUPT EXTENSION REGISTER */
 
 
 
#define ECNTRL0 MOBARV+0x800
#define EDMA0 MOBARV+0x802
#define EMRBRL0 MOBARV+0x804
#define INTR_VECT0 MOBARV+0x806
#define INTR_EVENT0 MOBARV+0x808
#define INTR_MASK0 MOBARV+0x80A
#define ECNFIG0 MOBARV+0x80C
#define ETHER_TEST0 MOBARV+0x80E
#define AR_CNTRL0 MOBARV+0x810
#define CET0 MOBARV+0xA00
#define EBD0 MOBARV+0xC00
 
 
#define ECNTRL_GTS 0x04
#define ECNTRL_ETHER_EN 0x02
#define ECNTRL_RESET 0x01
 
struct _68EN302_ECNTRL
{
unsigned short MBZ:13; /* must be zero */
unsigned short GTS:1; /* graceful transmit stop */
unsigned short ETHER_EN:1; /* ethernet enable */
unsigned short RESET:1; /* ethernet controller reset */
};
 
 
struct _68EN302_EDMA
{
unsigned short BDERR:7; /* Buffer descriptor error number */
unsigned short MBZ:1; /* must be zero */
unsigned short BDSIZE:2; /* buffer descritor size */
unsigned short TSRLY:1; /* transmit start early */
unsigned short WMRK:2; /* FIFO water mark */
unsigned short BLIM:3; /* burst limit */
};
 
 
 
 
 
 
/* ethernet test regsiter bits */
#define ETHR_TWS 0x0001
#define ETHR_RWS 0x0002
#define ETHR_DRTY 0x0004
#define ETHR_COLL 0x0008
#define ETHR_SLOT 0x0010
#define ETHR_TRND 0x0020
#define ETHR_TBO 0x0040
#define ETHR_BGT 0x0080
 
 
 
/* address control register bits */
 
#define ETHR_HASH_EN 0x8000
#define ETHR_INDEX_EN 0x4000
#define ETHR_MULT 0x3000
#define ETHR_PA_REJ 0x0800
#define ETHR_PROM 0x0400
 
 
struct _68EN302_AR_CNTRL
{
unsigned short HASH_EN:1;
unsigned short INDEX_EN:1;
unsigned short MULT:2;
unsigned short PA_REJ:1;
unsigned short PROM:1;
unsigned short MBZ:10;
};
 
 
struct _68EN302_ETHR_IVEC
{
unsigned short MBZ:7;
unsigned short VG:1;
unsigned short INV:8;
};
 
union _68EN302_ETHR_RXBD_FLAGS
{
unsigned short w;
struct
{
unsigned short E:1,RO:1,W:1,I:1,L:1,F:1, :1, M:1, :2, LG:1,NO:1,SH:1,CR:1,OV:1,CL:1;
} s;
};
 
struct _68EN302_ETHR_RXBD
{
union _68EN302_ETHR_RXBD_FLAGS flags;
unsigned short length;
union
{
unsigned long l;
struct
{
unsigned long Reason:2;
unsigned long ARIndex:6;
unsigned long Pointer:24;
} s;
} address;
};
 
union _68EN302_ETHR_TXBD_FLAGS
{
unsigned short w;
struct
{
unsigned short R:1,TO:1,W:1,I:1,L:1,TC:1,
DEF:1, HB:1, LC:1;
unsigned short RL:1,
xRC:4,
UN:1, CSL:1;
} s;
};
 
 
 
struct _68EN302_ETHR_TXBD
{
union _68EN302_ETHR_TXBD_FLAGS flags;
unsigned short length;
unsigned long address;
};
 
 
union _68EN302_ETHR_BD
{
struct _68EN302_ETHR_TXBD tx;
struct _68EN302_ETHR_RXBD rx;
};
 
 
struct _68EN302_ETHR
{
struct _68EN302_ECNTRL ECNTRL;
struct _68EN302_EDMA EDMA;
unsigned short EMRBRL;
struct _68EN302_ETHR_IVEC INTR_VEC;
 
/* interrupt masks */
unsigned short INTR_EVENT;
unsigned short INTR_MASK;
#define ETHR_RXB 0x0001
#define ETHR_TXB 0x0002
#define ETHR_BSY 0x0004
#define ETHR_RFINT 0x0008
#define ETHR_TFINT 0x0010
#define ETHR_EBERR 0x0020
#define ETHR_BOD 0x0040
#define ETHR_GRA 0x0080
#define ETHR_BABT 0x0100
#define ETHR_BABR 0x0200
#define ETHR_HBERR 0x0400
 
/* ethernet configuration refitser bits */
unsigned short ECNFIG;
#define ETHR_LOOP 0x0001
#define ETHR_FDEN 0x0002
#define ETHR_HDC 0x0004
#define ETHR_RDT 0x0008
 
unsigned short ETHER_TEST;
struct _68EN302_AR_CNTRL AR_CNTRL;
};
 
#define _68EN302_MAX_CET 64
struct _68EN302_ETHR_BLOCK
{
struct _68EN302_ETHR info;
unsigned char dummy[0x9ff+1-0x812];
unsigned char CET[_68EN302_MAX_CET][8];
union _68EN302_ETHR_BD BD[128];
};
 
 
 
#endif
/coldfire.h
0,0 → 1,40
/****************************************************************************/
 
/*
* coldfire.h -- Motorola ColdFire CPU sepecific defines
*
* (C) Copyright 1999-2000, Greg Ungerer (gerg@moreton.com.au)
*/
 
/****************************************************************************/
#ifndef coldfire_h
#define coldfire_h
/****************************************************************************/
 
#include <linux/config.h>
 
/*
* Define the processor support peripherals base address.
* This is generally setup by the boards start up code.
*/
#define MCF_MBAR 0x10000000
 
/*
* Define master clock frequency.
*/
#if defined(CONFIG_M5206)
#define MCF_CLK 25000000
#elif defined(CONFIG_M5206e)
#ifdef CONFIG_NETtel
#define MCF_CLK 40000000
#else
#define MCF_CLK 54000000
#endif
#elif defined(CONFIG_M5307)
#define MCF_CLK 45000000
#elif defined(CONFIG_M5204)
#define MCF_CLK 25000000
#endif
 
/****************************************************************************/
#endif /* coldfire_h */
/mcfdma.h
0,0 → 1,90
/****************************************************************************/
 
/*
* mcfdma.h -- Coldfire internal DMA support defines.
*
* (C) Copyright 1999, Rob Scott (rscott@mtrob.ml.org)
*/
 
/****************************************************************************/
#ifndef mcfdma_h
#define mcfdma_h
/****************************************************************************/
 
#include <linux/config.h>
 
/*
* Get address specific defines for this Coldfire member.
*/
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
#define MCFDMA_BASE0 0x200 /* Base address of DMA 0 */
#define MCFDMA_BASE1 0x240 /* Base address of DMA 1 */
#elif defined(CONFIG_M5307)
#define MCFDMA_BASE0 0x300 /* Base address of DMA 0 */
#define MCFDMA_BASE1 0x340 /* Base address of DMA 1 */
#define MCFDMA_BASE2 0x380 /* Base address of DMA 2 */
#define MCFDMA_BASE3 0x3C0 /* Base address of DMA 3 */
#endif
 
 
/*
* Define the DMA register set addresses.
* Note: these are longword registers, use unsigned long as data type
*/
#define MCFDMA_SAR 0x00 /* DMA source address (r/w) */
#define MCFDMA_DAR 0x01 /* DMA destination adr (r/w) */
/* these are word registers, use unsigned short data type */
#define MCFDMA_DCR 0x04 /* DMA control reg (r/w) */
#define MCFDMA_BCR 0x06 /* DMA byte count reg (r/w) */
/* these are byte registers, use unsiged char data type */
#define MCFDMA_DSR 0x10 /* DMA status reg (r/w) */
#define MCFDMA_DIVR 0x14 /* DMA interrupt vec (r/w) */
 
 
 
/*
* Bit definitions for the DMA Control Register (DCR).
*/
#define MCFDMA_DCR_INT 0x8000 /* Enable completion irq */
#define MCFDMA_DCR_EEXT 0x4000 /* Enable external DMA req */
#define MCFDMA_DCR_CS 0x2000 /* Enable cycle steal */
#define MCFDMA_DCR_AA 0x1000 /* Enable auto alignment */
#define MCFDMA_DCR_BWC_MASK 0x0E00 /* Bandwidth ctl mask */
#define MCFDMA_DCR_BWC_512 0x0200 /* Bandwidth: 512 Bytes */
#define MCFDMA_DCR_BWC_1024 0x0400 /* Bandwidth: 1024 Bytes */
#define MCFDMA_DCR_BWC_2048 0x0600 /* Bandwidth: 2048 Bytes */
#define MCFDMA_DCR_BWC_4096 0x0800 /* Bandwidth: 4096 Bytes */
#define MCFDMA_DCR_BWC_8192 0x0a00 /* Bandwidth: 8192 Bytes */
#define MCFDMA_DCR_BWC_16384 0x0c00 /* Bandwidth: 16384 Bytes */
#define MCFDMA_DCR_BWC_32768 0x0e00 /* Bandwidth: 32768 Bytes */
#define MCFDMA_DCR_SAA 0x0100 /* Single Address Access */
#define MCFDMA_DCR_S_RW 0x0080 /* SAA read/write value */
#define MCFDMA_DCR_SINC 0x0040 /* Source addr inc enable */
#define MCFDMA_DCR_SSIZE_MASK 0x0030 /* Src xfer size */
#define MCFDMA_DCR_SSIZE_LONG 0x0000 /* Src xfer size, 00 = longw */
#define MCFDMA_DCR_SSIZE_BYTE 0x0010 /* Src xfer size, 01 = byte */
#define MCFDMA_DCR_SSIZE_WORD 0x0020 /* Src xfer size, 10 = word */
#define MCFDMA_DCR_SSIZE_LINE 0x0030 /* Src xfer size, 11 = line */
#define MCFDMA_DCR_DINC 0x0008 /* Dest addr inc enable */
#define MCFDMA_DCR_DSIZE_MASK 0x0006 /* Dest xfer size */
#define MCFDMA_DCR_DSIZE_LONG 0x0000 /* Dest xfer size, 00 = long */
#define MCFDMA_DCR_DSIZE_BYTE 0x0002 /* Dest xfer size, 01 = byte */
#define MCFDMA_DCR_DSIZE_WORD 0x0004 /* Dest xfer size, 10 = word */
#define MCFDMA_DCR_DSIZE_LINE 0x0006 /* Dest xfer size, 11 = line */
#define MCFDMA_DCR_START 0x0001 /* Start transfer */
 
/*
* Bit definitions for the DMA Status Register (DSR).
*/
#define MCFDMA_DSR_CE 0x40 /* Config error */
#define MCFDMA_DSR_BES 0x20 /* Bus Error on source */
#define MCFDMA_DSR_BED 0x10 /* Bus Error on dest */
#define MCFDMA_DSR_REQ 0x04 /* Requests remaining */
#define MCFDMA_DSR_BSY 0x02 /* Busy */
#define MCFDMA_DSR_DONE 0x01 /* DMA transfer complete */
 
/****************************************************************************/
#endif /* mcfdma_h */
 
 
 
/termbits.h
0,0 → 1,169
#ifndef __ARCH_M68K_TERMBITS_H__
#define __ARCH_M68K_TERMBITS_H__
 
#include <linux/posix_types.h>
 
typedef unsigned char cc_t;
typedef unsigned int speed_t;
typedef unsigned int tcflag_t;
 
#define NCCS 19
struct termios {
tcflag_t c_iflag; /* input mode flags */
tcflag_t c_oflag; /* output mode flags */
tcflag_t c_cflag; /* control mode flags */
tcflag_t c_lflag; /* local mode flags */
cc_t c_line; /* line discipline */
cc_t c_cc[NCCS]; /* control characters */
};
 
/* c_cc characters */
#define VINTR 0
#define VQUIT 1
#define VERASE 2
#define VKILL 3
#define VEOF 4
#define VTIME 5
#define VMIN 6
#define VSWTC 7
#define VSTART 8
#define VSTOP 9
#define VSUSP 10
#define VEOL 11
#define VREPRINT 12
#define VDISCARD 13
#define VWERASE 14
#define VLNEXT 15
#define VEOL2 16
 
 
/* c_iflag bits */
#define IGNBRK 0000001
#define BRKINT 0000002
#define IGNPAR 0000004
#define PARMRK 0000010
#define INPCK 0000020
#define ISTRIP 0000040
#define INLCR 0000100
#define IGNCR 0000200
#define ICRNL 0000400
#define IUCLC 0001000
#define IXON 0002000
#define IXANY 0004000
#define IXOFF 0010000
#define IMAXBEL 0020000
 
/* c_oflag bits */
#define OPOST 0000001
#define OLCUC 0000002
#define ONLCR 0000004
#define OCRNL 0000010
#define ONOCR 0000020
#define ONLRET 0000040
#define OFILL 0000100
#define OFDEL 0000200
#define NLDLY 0000400
#define NL0 0000000
#define NL1 0000400
#define CRDLY 0003000
#define CR0 0000000
#define CR1 0001000
#define CR2 0002000
#define CR3 0003000
#define TABDLY 0014000
#define TAB0 0000000
#define TAB1 0004000
#define TAB2 0010000
#define TAB3 0014000
#define XTABS 0014000
#define BSDLY 0020000
#define BS0 0000000
#define BS1 0020000
#define VTDLY 0040000
#define VT0 0000000
#define VT1 0040000
#define FFDLY 0100000
#define FF0 0000000
#define FF1 0100000
 
/* c_cflag bit meaning */
#define CBAUD 0010017
#define B0 0000000 /* hang up */
#define B50 0000001
#define B75 0000002
#define B110 0000003
#define B134 0000004
#define B150 0000005
#define B200 0000006
#define B300 0000007
#define B600 0000010
#define B1200 0000011
#define B1800 0000012
#define B2400 0000013
#define B4800 0000014
#define B9600 0000015
#define B19200 0000016
#define B38400 0000017
#define EXTA B19200
#define EXTB B38400
#define CSIZE 0000060
#define CS5 0000000
#define CS6 0000020
#define CS7 0000040
#define CS8 0000060
#define CSTOPB 0000100
#define CREAD 0000200
#define PARENB 0000400
#define PARODD 0001000
#define HUPCL 0002000
#define CLOCAL 0004000
#define CBAUDEX 0010000
#define B57600 0010001
#define B115200 0010002
#define B230400 0010003
#define B460800 0010004
#define CBLOCKW 0020000 /* block output based on control signals */
#define CBLOCKR 0040000 /* block input based on control signals */
#define CIBAUD 002003600000 /* input baud rate (not used) */
#define CAUTORTS 010000000000 /* Automatic RTS */
#define CRTSCTS 020000000000 /* flow control */
 
#define C_CAUTORTS(tty) _C_FLAG((tty),CAUTORTS)
#define C_CBLOCKW(tty) _C_FLAG((tty),CBLOCKW)
#define C_CBLOCKR(tty) _C_FLAG((tty),CBLOCKR)
 
/* c_lflag bits */
#define ISIG 0000001
#define ICANON 0000002
#define XCASE 0000004
#define ECHO 0000010
#define ECHOE 0000020
#define ECHOK 0000040
#define ECHONL 0000100
#define NOFLSH 0000200
#define TOSTOP 0000400
#define ECHOCTL 0001000
#define ECHOPRT 0002000
#define ECHOKE 0004000
#define FLUSHO 0010000
#define PENDIN 0040000
#define IEXTEN 0100000
 
 
/* tcflow() and TCXONC use these */
#define TCOOFF 0
#define TCOON 1
#define TCIOFF 2
#define TCION 3
 
/* tcflush() and TCFLSH use these */
#define TCIFLUSH 0
#define TCOFLUSH 1
#define TCIOFLUSH 2
 
/* tcsetattr uses these */
#define TCSANOW 0
#define TCSADRAIN 1
#define TCSAFLUSH 2
 
#endif /* __ARCH_M68K_TERMBITS_H__ */
/nettel.h
0,0 → 1,136
/****************************************************************************/
 
/*
* nettel.h -- Moreton Bay NETtel support.
*
* (C) Copyright 1999, Moreton Bay (www.moreton.com.au)
*/
 
/****************************************************************************/
#ifndef nettel_h
#define nettel_h
/****************************************************************************/
 
#include <linux/config.h>
#include <asm/coldfire.h>
 
#ifdef CONFIG_NETtel
 
/*
* Define LED bank address and flags...
* Different NETtel modems are configured a little differently.
*/
 
#ifdef CONFIG_M5307
#define NETtel_LEDADDR 0x30400000
 
#define NETtel_LEDVPN 0x01
#define NETtel_LEDUSB2 0x02
#define NETtel_LEDTX1 0x04
#define NETtel_LEDRX1 0x08
#define NETtel_LEDTX2 0x10
#define NETtel_LEDRX2 0x20
#define NETtel_LEDUSB1 0x40
#define NETtel_LEDETH 0x80
 
/*
* The POWER and DIAG LEDs are on parallel I/O pins of 5307.
* The serial port DTR and DCD lines are also on the Parallel I/O.
*/
#define NETtel_LEDPWR 0x0040
#define NETtel_LEDDIAG 0x0020
 
#define NETtel_DCD1 0x0001
#define NETtel_DCD0 0x0002
#define NETtel_DTR1 0x0004
#define NETtel_DTR0 0x0008
#endif /* CONFIG_M5307 */
 
 
#ifdef CONFIG_M5206e
/*
* NETtel 1500 only has 4 LEDs.
*/
#define NETtel_LEDADDR 0x50000000
 
#define NETtel_LEDDIAG 0x01
#define NETtel_LEDDCD 0x02
#define NETtel_LEDOH 0x04
#define NETtel_LEDDATA 0x08
#endif /* CONFIG_M5206e */
 
 
/*
* User space routines for back door access to the LEDs :-)
* This is a complete and utter bastard hack... But quick...
* The "on" pattern turns on some LEDs permanently. The "off"
* pattern turns some LEDs off permantly. The "flash" pattern
* will flash a particular led pattern.
*/
#define LEDON(x) *((unsigned char *) 0x3fe) |= (x)
#define LEDOFF(x) *((unsigned char *) 0x3fe) &= ~(x)
#define LEDFLASH(x) *((unsigned char *) 0x3ff) = (x)
 
#define GETLED() *((unsigned char *) 0x3fe)
#define GETFLASH() *((unsigned char *) 0x3ff)
 
 
/*
* Kernel macros to set and unset the LEDs.
*/
#ifndef __ASSEMBLY__
extern unsigned char ledbank;
#ifdef CONFIG_M5307
extern unsigned short ppdata;
#endif /* CONFIG_M5307 */
#endif /* __ASSEMBLY__ */
 
/*
* The following macros apply to the basic latched LEDs.
* (Not any other LEDs hanging of PP bits)
*/
#define setled(x) \
*((volatile unsigned char *) NETtel_LEDADDR) = (ledbank &= ~(x))
 
#define unsetled(x) \
*((volatile unsigned char *) NETtel_LEDADDR) = (ledbank |= (x))
 
#define writeled(x) \
*((volatile unsigned char *) NETtel_LEDADDR) = (ledbank & ~(x))
 
#define rewriteled() \
*((volatile unsigned char *) NETtel_LEDADDR) = ledbank
 
 
/*
* The following macros set and unset the POWER and DIAG LEDS.
* They are treated separate since they are on ColdFire PP lines
* on the NETtels > 2500.
*/
#ifdef CONFIG_M5206e
#define setledpp(x) setled(x)
#define unsetledpp(x) unsetled(x)
#else
 
#define setledpp(x) \
*((volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT)) = \
(ppdata &= ~(x))
 
#define unsetledpp(x) \
*((volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT)) = \
(ppdata |= (x))
 
#endif
 
 
/*
* Panic setup for NETtel. No console on the NETtel so it may be
* difficult to tell if the unit has paniced or not. So this little
* macro will turn on all the LEDS - for a visual indicator of panic.
*/
#define nettel_panic() { cli(); setled(0xff); setledpp(0x60); }
 
#endif /* CONFIG_NETtel */
 
/****************************************************************************/
#endif /* nettel_h */
/setup.h
0,0 → 1,405
/*
** asm/setup.h -- Definition of the Linux/m68k boot information structure
**
** Copyright 1992 by Greg Harp
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created 09/29/92 by Greg Harp
**
** 5/2/94 Roman Hodek:
** Added bi_atari part of the machine dependent union bi_un; for now it
** contains just a model field to distinguish between TT and Falcon.
** 26/7/96 Roman Zippel:
** Renamed to setup.h; added some useful macros to allow gcc some
** optimizations if possible.
*/
 
#ifndef _M68K_SETUP_H
#define _M68K_SETUP_H
 
#include <linux/config.h>
 
#define CL_SIZE (256)
 
#if 0
 
#include <asm/zorro.h>
 
/*
* Amiga specific part of bootinfo structure.
*/
 
#define NUM_AUTO 16
 
#ifndef __ASSEMBLY__
 
#define AMIGAHW_DECLARE(name) unsigned name : 1
#define AMIGAHW_SET(name) (boot_info.bi_amiga.hw_present.name = 1)
#define AMIGAHW_PRESENT(name) (boot_info.bi_amiga.hw_present.name)
 
struct bi_Amiga {
int model; /* Amiga Model (3000?) */
int num_autocon; /* # of autoconfig devices found */
struct ConfigDev autocon[NUM_AUTO]; /* up to 16 autoconfig devices */
#ifdef HACKER_KERNEL
void (*exit_func)(void); /* addr of function to exit kernel */
unsigned long chip_addr; /* start of chip memory (bytes) */
#endif
unsigned long chip_size; /* size of chip memory (bytes) */
unsigned char vblank; /* VBLANK frequency */
unsigned char psfreq; /* power supply frequency */
unsigned long eclock; /* EClock frequency */
unsigned long chipset; /* native chipset present */
struct {
/* video hardware */
AMIGAHW_DECLARE(AMI_VIDEO); /* Amiga Video */
AMIGAHW_DECLARE(AMI_BLITTER); /* Amiga Blitter */
AMIGAHW_DECLARE(AMBER_FF); /* Amber Flicker Fixer */
/* sound hardware */
AMIGAHW_DECLARE(AMI_AUDIO); /* Amiga Audio */
/* disk storage interfaces */
AMIGAHW_DECLARE(AMI_FLOPPY); /* Amiga Floppy */
AMIGAHW_DECLARE(A3000_SCSI); /* SCSI (wd33c93, A3000 alike) */
AMIGAHW_DECLARE(A4000_SCSI); /* SCSI (ncr53c710, A4000T alike) */
AMIGAHW_DECLARE(A1200_IDE); /* IDE (A1200 alike) */
AMIGAHW_DECLARE(A4000_IDE); /* IDE (A4000 alike) */
AMIGAHW_DECLARE(CD_ROM); /* CD ROM drive */
/* other I/O hardware */
AMIGAHW_DECLARE(AMI_KEYBOARD); /* Amiga Keyboard */
AMIGAHW_DECLARE(AMI_MOUSE); /* Amiga Mouse */
AMIGAHW_DECLARE(AMI_SERIAL); /* Amiga Serial */
AMIGAHW_DECLARE(AMI_PARALLEL); /* Amiga Parallel */
/* real time clocks */
AMIGAHW_DECLARE(A2000_CLK); /* Hardware Clock (A2000 alike) */
AMIGAHW_DECLARE(A3000_CLK); /* Hardware Clock (A3000 alike) */
/* supporting hardware */
AMIGAHW_DECLARE(CHIP_RAM); /* Chip RAM */
AMIGAHW_DECLARE(PAULA); /* Paula (8364) */
AMIGAHW_DECLARE(DENISE); /* Denise (8362) */
AMIGAHW_DECLARE(DENISE_HR); /* Denise (8373) */
AMIGAHW_DECLARE(LISA); /* Lisa (8375) */
AMIGAHW_DECLARE(AGNUS_PAL); /* Normal/Fat PAL Agnus (8367/8371) */
AMIGAHW_DECLARE(AGNUS_NTSC); /* Normal/Fat NTSC Agnus (8361/8370) */
AMIGAHW_DECLARE(AGNUS_HR_PAL); /* Fat Hires PAL Agnus (8372) */
AMIGAHW_DECLARE(AGNUS_HR_NTSC); /* Fat Hires NTSC Agnus (8372) */
AMIGAHW_DECLARE(ALICE_PAL); /* PAL Alice (8374) */
AMIGAHW_DECLARE(ALICE_NTSC); /* NTSC Alice (8374) */
AMIGAHW_DECLARE(MAGIC_REKICK); /* A3000 Magic Hard Rekick */
AMIGAHW_DECLARE(ZORRO); /* Zorro AutoConfig */
} hw_present;
};
 
#else /* __ASSEMBLY__ */
BI_amiga_model = BI_un
BI_amiga_num_autcon = BI_amiga_model+4
BI_amiga_autocon = BI_amiga_num_autcon+4
#ifdef HACKER_KERNEL
BI_amiga_exit_func = BI_amiga_autocon+(CD_sizeof*NUM_AUTO)
BI_amiga_chip_addr = BI_amiga_exit_func+4
BI_amiga_chip_size = BI_amiga_chip_addr+4
#else
BI_amiga_chip_size = BI_amiga_autocon+(CD_sizeof*NUM_AUTO)
#endif
BI_amiga_vblank = BI_amiga_chip_size+4
BI_amiga_psfreq = BI_amiga_vblank+1
BI_amiga_eclock = BI_amiga_psfreq+1
BI_amiga_chipset = BI_amiga_eclock+4
BI_amiga_hw_present = BI_amiga_chipset+4
 
#endif /* __ASSEMBLY__ */
 
/* Atari specific part of bootinfo */
 
/*
* Define several Hardware-Chips for indication so that for the ATARI we do
* no longer decide whether it is a Falcon or other machine . It's just
* important what hardware the machine uses
*/
 
/* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */
 
#ifndef __ASSEMBLY__
 
#define ATARIHW_DECLARE(name) unsigned name : 1
#define ATARIHW_SET(name) (boot_info.bi_atari.hw_present.name = 1)
#define ATARIHW_PRESENT(name) (boot_info.bi_atari.hw_present.name)
 
struct bi_Atari {
struct {
/* video hardware */
ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */
ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */
ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */
ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */
/* sound hardware */
ATARIHW_DECLARE(YM_2149); /* Yamaha YM 2149 */
ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */
ATARIHW_DECLARE(CODEC); /* CODEC Sound (Falcon) */
/* disk storage interfaces */
ATARIHW_DECLARE(TT_SCSI); /* Directly mapped NCR5380 */
ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */
ATARIHW_DECLARE(ACSI); /* Standard ACSI like in STs */
ATARIHW_DECLARE(IDE); /* IDE Interface */
ATARIHW_DECLARE(FDCSPEED); /* 8/16 MHz switch for FDC */
/* other I/O hardware */
ATARIHW_DECLARE(ST_MFP); /* The ST-MFP (there should
be no Atari without
it... but who knows?) */
ATARIHW_DECLARE(TT_MFP); /* 2nd MFP */
ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */
ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */
ATARIHW_DECLARE(ANALOG_JOY); /* Paddle Interface for STe
and Falcon */
ATARIHW_DECLARE(MICROWIRE); /* Microwire Interface */
/* DMA */
ATARIHW_DECLARE(STND_DMA); /* 24 Bit limited ST-DMA */
ATARIHW_DECLARE(EXTD_DMA); /* 32 Bit ST-DMA */
ATARIHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */
ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */
/* real time clocks */
ATARIHW_DECLARE(TT_CLK); /* TT compatible clock chip */
ATARIHW_DECLARE(MSTE_CLK); /* Mega ST(E) clock chip */
/* supporting hardware */
ATARIHW_DECLARE(SCU); /* System Control Unit */
ATARIHW_DECLARE(BLITTER); /* Blitter */
ATARIHW_DECLARE(VME); /* VME Bus */
} hw_present;
unsigned long mch_cookie; /* _MCH cookie from TOS */
};
 
/* mch_cookie values (upper word) */
#define ATARI_MCH_ST 0
#define ATARI_MCH_STE 1
#define ATARI_MCH_TT 2
#define ATARI_MCH_FALCON 3
 
struct mem_info {
unsigned long addr; /* physical address of memory chunk */
unsigned long size; /* length of memory chunk (in bytes) */
};
 
#else /* __ASSEMBLY__ */
 
MI_addr = 0
MI_size = MI_addr+4
MI_sizeof = MI_size+4
 
#endif /* __ASSEMBLY__ */
 
#define NUM_MEMINFO 4
 
#define MACH_AMIGA 1
#define MACH_ATARI 2
#define MACH_MAC 3
 
/*
* CPU and FPU types
*/
 
#define CPUB_68020 0
#define CPUB_68030 1
#define CPUB_68040 2
#define CPUB_68060 3
#define FPUB_68881 5
#define FPUB_68882 6
#define FPUB_68040 7 /* Internal FPU */
#define FPUB_68060 8 /* Internal FPU */
 
#define CPU_68020 (1<<CPUB_68020)
#define CPU_68030 (1<<CPUB_68030)
#define CPU_68040 (1<<CPUB_68040)
#define CPU_68060 (1<<CPUB_68060)
#define CPU_MASK (31)
#define FPU_68881 (1<<FPUB_68881)
#define FPU_68882 (1<<FPUB_68882)
#define FPU_68040 (1<<FPUB_68040) /* Internal FPU */
#define FPU_68060 (1<<FPUB_68060) /* Internal FPU */
#define FPU_MASK (0xfe0)
 
#define CL_SIZE (256)
 
/*
* machine type definitions
*/
 
#if !defined(CONFIG_AMIGA)
# define MACH_IS_AMIGA (0)
#elif defined(CONFIG_ATARI) || defined(CONFIG_MAC)
# define MACH_IS_AMIGA (boot_info.machtype == MACH_AMIGA)
#else
# define CONFIG_AMIGA_ONLY
# define MACH_IS_AMIGA (1)
# define MACH_TYPE (MACH_AMIGA)
#endif
 
#if !defined(CONFIG_ATARI)
# define MACH_IS_ATARI (0)
#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC)
# define MACH_IS_ATARI (boot_info.machtype == MACH_ATARI)
#else
# define CONFIG_ATARI_ONLY
# define MACH_IS_ATARI (1)
# define MACH_TYPE (MACH_ATARI)
#endif
 
#if defined(CONFIG_MAC)
# error Currently no Mac support!
#endif
 
#ifndef MACH_TYPE
# define MACH_TYPE (boot_info.machtype)
#endif
 
/*
* cpu type definitions
*/
 
#if !defined(CONFIG_M68020)
# define CPU_IS_020 (0)
#elif defined(CONFIG_M68030) || defined(CONFIG_M68040) || defined(CONFIG_M68060)
# define CPU_IS_020 (boot_info.cputype & CPU_68020)
#else
# define CONFIG_M68020_ONLY
# define CPU_IS_020 (1)
#endif
 
#if !defined(CONFIG_M68030)
# define CPU_IS_030 (0)
#elif defined(CONFIG_M68020) || defined(CONFIG_M68040) || defined(CONFIG_M68060)
# define CPU_IS_030 (boot_info.cputype & CPU_68030)
#else
# define CONFIG_M68030_ONLY
# define CPU_IS_030 (1)
#endif
 
#if !defined(CONFIG_M68040)
# define CPU_IS_040 (0)
#elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68060)
# define CPU_IS_040 (boot_info.cputype & CPU_68040)
#else
# define CONFIG_M68040_ONLY
# define CPU_IS_040 (1)
#endif
 
#if !defined(CONFIG_M68060)
# define CPU_IS_060 (0)
#elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68040)
# define CPU_IS_060 (boot_info.cputype & CPU_68060)
#else
# define CONFIG_M68060_ONLY
# define CPU_IS_060 (1)
#endif
 
#if !defined(CONFIG_M68020) && !defined(CONFIG_M68030)
# define CPU_IS_020_OR_030 (0)
#else
# define CONFIG_M68020_OR_M68030
# if defined(CONFIG_M68040) || defined(CONFIG_M68060)
# define CPU_IS_020_OR_030 (!m68k_is040or060)
# else
# define CONFIG_M68020_OR_M68030_ONLY
# define CPU_IS_020_OR_030 (1)
# endif
#endif
 
#if !defined(CONFIG_M68040) && !defined(CONFIG_M68060)
# define CPU_IS_040_OR_060 (0)
#else
# define CONFIG_M68040_OR_M68060
# if defined(CONFIG_M68020) || defined(CONFIG_M68030)
# define CPU_IS_040_OR_060 (m68k_is040or060)
# else
# define CONFIG_M68040_OR_M68060_ONLY
# define CPU_IS_040_OR_060 (1)
# endif
#endif
 
#define CPU_TYPE (boot_info.cputype)
 
#ifndef __ASSEMBLY__
#ifdef __KERNEL__
/*
* m68k_is040or060 is != 0 for a '040 or higher;
* used numbers are 4 for 68040 and 6 for 68060.
*/
 
extern int m68k_is040or060;
#endif
 
struct bootinfo {
unsigned long machtype; /* machine type */
unsigned long cputype; /* system CPU & FPU */
struct mem_info memory[NUM_MEMINFO]; /* memory description */
int num_memory; /* # of memory blocks found */
unsigned long ramdisk_size; /* ramdisk size in 1024 byte blocks */
unsigned long ramdisk_addr; /* address of the ram disk in mem */
char command_line[CL_SIZE]; /* kernel command line parameters */
union {
struct bi_Amiga bi_ami; /* Amiga specific information */
struct bi_Atari bi_ata; /* Atari specific information */
} bi_un;
};
#define bi_amiga bi_un.bi_ami
#define bi_atari bi_un.bi_ata
#define bi_mac bi_un.bi_mac
 
extern struct bootinfo
boot_info;
 
#else /* __ASSEMBLY__ */
 
BI_machtype = 0
BI_cputype = BI_machtype+4
BI_memory = BI_cputype+4
BI_num_memory = BI_memory+(MI_sizeof*NUM_MEMINFO)
BI_ramdisk_size = BI_num_memory+4
BI_ramdisk_addr = BI_ramdisk_size+4
BI_command_line = BI_ramdisk_addr+4
BI_un = BI_command_line+CL_SIZE
 
#endif /* __ASSEMBLY__ */
 
 
/*
* Stuff for bootinfo interface versioning
*
* At the start of kernel code, a 'struct bootversion' is located. bootstrap
* checks for a matching version of the interface before booting a kernel, to
* avoid user confusion if kernel and bootstrap don't work together :-)
*
* If incompatible changes are made to the bootinfo interface, the major
* number below should be stepped (and the minor reset to 0) for the
* appropriate machine. If a change is backward-compatible, the minor should
* be stepped. "Backwards-compatible" means that booting will work, but
* certain features may not.
*/
 
#define BOOTINFOV_MAGIC 0x4249561A /* 'BIV^Z' */
#define MK_BI_VERSION(major,minor) (((major)<<16)+(minor))
#define BI_VERSION_MAJOR(v) (((v) >> 16) & 0xffff)
#define BI_VERSION_MINOR(v) ((v) & 0xffff)
 
#ifndef __ASSEMBLY__
 
struct bootversion {
unsigned short branch;
unsigned long magic;
struct {
unsigned long machtype;
unsigned long version;
} machversions[0];
};
 
#endif /* __ASSEMBLY__ */
 
#define AMIGA_BOOTI_VERSION MK_BI_VERSION( 1, 0 )
#define ATARI_BOOTI_VERSION MK_BI_VERSION( 1, 0 )
 
#endif
 
 
#endif /* _M68K_SETUP_H */
/mcfuart.h
0,0 → 1,170
/****************************************************************************/
 
/*
* mcfuart.h -- ColdFire internal UART support defines.
*
* (C) Copyright 1999, Greg Ungerer (gerg@moreton.com.au)
*/
 
/****************************************************************************/
#ifndef mcfuart_h
#define mcfuart_h
/****************************************************************************/
 
#include <linux/config.h>
 
/*
* Define the base address of the UARTS within the MBAR address
* space.
*/
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5204)
#if defined(CONFIG_NETtel)
#define MCFUART_BASE1 0x180 /* Base address of UART1 */
#define MCFUART_BASE2 0x140 /* Base address of UART2 */
#else
#define MCFUART_BASE1 0x140 /* Base address of UART1 */
#define MCFUART_BASE2 0x180 /* Base address of UART2 */
#endif
#elif defined(CONFIG_M5307)
#if defined(CONFIG_NETtel) || defined(CONFIG_MATtel)
#define MCFUART_BASE1 0x200 /* Base address of UART1 */
#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
#else
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
#endif
#endif
 
 
/*
* Define the ColdFire UART register set addresses.
*/
#define MCFUART_UMR 0x00 /* Mode register (r/w) */
#define MCFUART_USR 0x04 /* Status register (r) */
#define MCFUART_UCSR 0x04 /* Clock Select (w) */
#define MCFUART_UCR 0x08 /* Command register (w) */
#define MCFUART_URB 0x0c /* Receiver Buffer (r) */
#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
#define MCFUART_UISR 0x14 /* Interrup Status (r) */
#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
#define MCFUART_UIPR 0x34 /* Input Port (r) */
#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
 
 
/*
* Define bit flags in Mode Register 1 (MR1).
*/
#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
 
#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
#define MCFUART_MR1_PARITYMARK 0x06 /* Mark parity */
 
#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
 
/*
* Define bit flags in Mode Register 2 (MR2).
*/
#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
 
#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
 
/*
* Define bit flags in Status Register (USR).
*/
#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
#define MCFUART_USR_RXFULL 0x02 /* Receiver full */
#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
 
#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
 
/*
* Define bit flags in Clock Select Register (UCSR).
*/
#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
 
#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
 
/*
* Define bit flags in Command Register (UCR).
*/
#define MCFUART_UCR_CMDNULL 0x00 /* No command */
#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
 
#define MCFUART_UCR_TXNULL 0x00 /* No TX command */
#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
#define MCFUART_UCR_RXNULL 0x00 /* No RX command */
#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
 
/*
* Define bit flags in Input Port Change Register (UIPCR).
*/
#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
#define MCFUART_UIPCR_CTS 0x01 /* CTS value */
 
/*
* Define bit flags in Input Port Register (UIP).
*/
#define MCFUART_UIPR_CTS 0x01 /* CTS value */
 
/*
* Define bit flags in Output Port Registers (UOP).
* Clear bit by writing to UOP0, set by writing to UOP1.
*/
#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
 
/*
* Define bit flags in the Auxiliary Control Register (UACR).
*/
#define MCFUART_UACR_IEC 0x01 /* Input enable control */
 
/*
* Define bit flags in Interrupt Status Register (UISR).
* These same bits are used for the Interrupt Mask Register (UIMR).
*/
#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
 
/****************************************************************************/
#endif /* mcfuart_h */
/segment.h
0,0 → 1,386
#ifndef _M68K_SEGMENT_H
#define _M68K_SEGMENT_H
 
/* define constants */
/* Address spaces (FC0-FC2) */
#define USER_DATA (1)
#ifndef USER_DS
#define USER_DS (USER_DATA)
#endif
#define USER_PROGRAM (2)
#define SUPER_DATA (5)
#ifndef KERNEL_DS
#define KERNEL_DS (SUPER_DATA)
#endif
#define SUPER_PROGRAM (6)
#define CPU_SPACE (7)
 
#ifndef __ASSEMBLY__
 
/*
* Uh, these should become the main single-value transfer routines..
* They automatically use the right size if we just have the right
* pointer type..
*/
#define put_user(x,ptr) __put_user((unsigned long)(x),(ptr),sizeof(*(ptr)))
#define get_user(ptr) ((__typeof__(*(ptr)))__get_user((ptr),sizeof(*(ptr))))
 
/*
* This is a silly but good way to make sure that
* the __put_user function is indeed always optimized,
* and that we use the correct sizes..
*/
extern int bad_user_access_length(void);
 
#define __ptr(x) ((unsigned long *)(x))
 
static inline void __put_user(unsigned long x, void * y, int size)
{
switch (size) {
case 1:
__asm__ ("moveb %0,%1"
: /* no outputs */
:"d" (x),"m" (*__ptr(y)) : "memory");
break;
case 2:
__asm__ ("movew %0,%1"
: /* no outputs */
:"d" (x),"m" (*__ptr(y)) : "memory");
break;
case 4:
__asm__ ("movel %0,%1"
: /* no outputs */
:"d" (x),"m" (*__ptr(y)) : "memory");
break;
default:
bad_user_access_length();
}
}
 
static inline unsigned long __get_user(const void * y, int size)
{
unsigned long result;
 
switch (size) {
case 1:
__asm__ ("moveb %1,%0"
:"=d" (result)
:"m" (*__ptr(y)));
return (unsigned char) result;
case 2:
__asm__ ("movew %1,%0"
:"=d" (result)
:"m" (*__ptr(y)));
return (unsigned short) result;
case 4:
__asm__ ("movel %1,%0"
:"=d" (result)
:"m" (*__ptr(y)));
return result;
default:
return bad_user_access_length();
}
}
#undef __ptr
 
/*
* These are deprecated..
*
* Use "put_user()" and "get_user()" with the proper pointer types instead.
*/
 
#define get_fs_byte(addr) __get_user((const unsigned char *)(addr),1)
#define get_fs_word(addr) __get_user((const unsigned short *)(addr),2)
#define get_fs_long(addr) __get_user((const unsigned int *)(addr),4)
 
#define put_fs_byte(x,addr) __put_user((x),(unsigned char *)(addr),1)
#define put_fs_word(x,addr) __put_user((x),(unsigned short *)(addr),2)
#define put_fs_long(x,addr) __put_user((x),(unsigned int *)(addr),4)
 
#ifdef WE_REALLY_WANT_TO_USE_A_BROKEN_INTERFACE
 
static inline unsigned char get_user_byte(const char * addr)
{
return __get_user(addr,1);
}
 
static inline unsigned short get_user_word(const short *addr)
{
return __get_user(addr,2);
}
 
static inline unsigned long get_user_long(const int *addr)
{
return __get_user(addr,4);
}
 
static inline void put_user_byte(char val,char *addr)
{
__put_user(val, addr, 1);
}
 
static inline void put_user_word(short val,short * addr)
{
__put_user(val, addr, 2);
}
 
static inline void put_user_long(unsigned long val,int * addr)
{
__put_user(val, addr, 4);
}
 
#endif
 
static inline void __generic_memcpy_tofs(void * to, const void * from, unsigned long n)
{
memcpy(to, from, n);
/* Gah, idiots! */
#if 0
unsigned long tmp;
if (n == 0) return;
tmp = n;
n >>= 2;
if (n != 0)
__asm__ __volatile__ ("1:\t"
"movel %1@+,%/d0\n\t"
"movel %/d0,%2@+\n\t" /* moves */
"dbra %0,1b\n\t"
"clrw %0\n\t"
"subql #1,%0\n\t"
"bccs 1b\n\t"
: "=d" (n), "=a" (from), "=a" (to)
: "0" (n-1), "1" (from), "2" (to)
: "d0", "memory");
if (tmp & 2)
__asm__ __volatile__ ("movew %0@+,%/d0\n\t"
"movew %/d0,%1@+\n\t" /* moves */
: "=a" (from), "=a" (to)
: "0" (from), "1" (to)
: "d0", "memory");
if (tmp & 1)
__asm__ __volatile__ ("moveb %0@,%/d0\n\t"
"moveb %/d0,%1@\n\t" /* moves */
: /* no outputs */
: "a" (from), "a" (to)
: "d0", "memory");
#endif
}
 
static inline void __constant_memcpy_tofs(void * to, const void * from, unsigned long n)
{
memcpy(to, from, n);
#if 0
switch (n) {
case 0:
return;
case 1:
__put_user(*(const char *) from, (char *) to, 1);
return;
case 2:
__put_user(*(const short *) from, (short *) to, 2);
return;
case 3:
__put_user(*(const short *) from, (short *) to, 2);
__put_user(*(2+(const char *) from), 2+(char *) to, 1);
return;
case 4:
__put_user(*(const int *) from, (int *) to, 4);
return;
case 8:
__put_user(*(const int *) from, (int *) to, 4);
__put_user(*(1+(const int *) from), 1+(int *) to, 4);
return;
case 12:
__put_user(*(const int *) from, (int *) to, 4);
__put_user(*(1+(const int *) from), 1+(int *) to, 4);
__put_user(*(2+(const int *) from), 2+(int *) to, 4);
return;
case 16:
__put_user(*(const int *) from, (int *) to, 4);
__put_user(*(1+(const int *) from), 1+(int *) to, 4);
__put_user(*(2+(const int *) from), 2+(int *) to, 4);
__put_user(*(3+(const int *) from), 3+(int *) to, 4);
return;
}
/* moves */
#define COMMON(x) \
__asm__ __volatile__ ("1:\n\t" \
"movel %1@+,%/d0\n\t" \
"movel %/d0,%2@+\n\t" \
"dbra %0,1b\n\t" \
"clrw %0\n\t" \
"subql #1,%0\n\t" \
"bccs 1b\n\t" \
x \
: "=d" (n), "=a" (from), "=a" (to) \
: "1" (from), "2" (to), "0" (n/4-1) \
: "d0", "memory");
 
switch (n % 4) {
case 0:
COMMON("");
return;
case 1:
COMMON("moveb %1@+,%/d0; moveb %/d0,%2@+"); /* moves */
return;
case 2:
COMMON("movew %1@+,%/d0; movew %/d0,%2@+"); /* moves */
return;
case 3:
COMMON("movew %1@+,%/d0; movew %/d0,%2@+\n\t" /* moves */
"moveb %1@+,%/d0; moveb %/d0,%2@+"); /* moves */
return;
}
#undef COMMON
#endif
}
 
static inline void __generic_memcpy_fromfs(void * to, const void * from, unsigned long n)
{
memcpy(to, from, n);
/* Gah, idiots! */
#if 0
unsigned long tmp;
if (n == 0) return;
tmp = n;
n >>= 2;
if (n != 0)
__asm__ __volatile__ ("1:\t"
"movel %1@+,%/d0\n\t" /* moves */
"movel %/d0,%2@+\n\t"
"dbra %0,1b\n\t"
"clrw %0\n\t"
"subql #1,%0\n\t"
"bccs 1b\n\t"
: "=d" (n), "=a" (from), "=a" (to)
: "0" (n-1), "1" (from), "2" (to)
: "d0", "memory");
if (tmp & 2)
__asm__ __volatile__ ("movew %0@+,%/d0\n\t" /* moves */
"movew %/d0,%1@+\n\t"
: "=a" (from), "=a" (to)
: "0" (from), "1" (to)
: "d0", "memory");
if (tmp & 1)
__asm__ __volatile__ ("moveb %0@,%/d0\n\t" /* moves */
"moveb %/d0,%1@\n\t"
: /* no outputs */
: "a" (from), "a" (to)
: "d0", "memory");
#endif
}
 
static inline void __constant_memcpy_fromfs(void * to, const void * from, unsigned long n)
{
memcpy(to, from, n);
#if 0
switch (n) {
case 0:
return;
case 1:
*(char *)to = __get_user((const char *) from, 1);
return;
case 2:
*(short *)to = __get_user((const short *) from, 2);
return;
case 3:
*(short *) to = __get_user((const short *) from, 2);
*((char *) to + 2) = __get_user(2+(const char *) from, 1);
return;
case 4:
*(int *) to = __get_user((const int *) from, 4);
return;
case 8:
*(int *) to = __get_user((const int *) from, 4);
*(1+(int *) to) = __get_user(1+(const int *) from, 4);
return;
case 12:
*(int *) to = __get_user((const int *) from, 4);
*(1+(int *) to) = __get_user(1+(const int *) from, 4);
*(2+(int *) to) = __get_user(2+(const int *) from, 4);
return;
case 16:
*(int *) to = __get_user((const int *) from, 4);
*(1+(int *) to) = __get_user(1+(const int *) from, 4);
*(2+(int *) to) = __get_user(2+(const int *) from, 4);
*(3+(int *) to) = __get_user(3+(const int *) from, 4);
return;
}
/*moves*/
#define COMMON(x) \
__asm__ __volatile__ ("1:\n\t" \
"movel %1@+,%/d0\n\t" \
"movel %/d0,%2@+\n\t" \
"dbra %0,1b\n\t" \
"clrw %0\n\t" \
"subql #1,%0\n\t" \
"bccs 1b\n\t" \
x \
: "=d" (n), "=a" (from), "=a" (to) \
: "1" (from), "2" (to), "0" (n/4-1) \
: "d0", "memory");
 
switch (n % 4) {
case 0:
COMMON("");
return;
case 1:
COMMON("moveb %1@+,%/d0; moveb %/d0,%2@+"); /* moves */
return;
case 2:
COMMON("movew %1@+,%/d0; movew %/d0,%2@+"); /* moves */
return;
case 3:
COMMON("movew %1@+,%/d0; movew %/d0,%2@+\n\t" /* moves */
"moveb %1@+,%/d0; moveb %/d0,%2@+"); /* moves */
return;
}
#undef COMMON
#endif
}
 
#define memcpy_fromfs(to, from, n) \
(__builtin_constant_p(n) ? \
__constant_memcpy_fromfs((to),(from),(n)) : \
__generic_memcpy_fromfs((to),(from),(n)))
 
#define memcpy_tofs(to, from, n) \
(__builtin_constant_p(n) ? \
__constant_memcpy_tofs((to),(from),(n)) : \
__generic_memcpy_tofs((to),(from),(n)))
 
/*
* Get/set the SFC/DFC registers for MOVES instructions
*/
 
static inline unsigned long get_fs(void)
{
#ifdef NO_MM
return USER_DS;
#else
unsigned long _v;
__asm__ ("movec %/dfc,%0":"=r" (_v):);
 
return _v;
#endif
}
 
static inline unsigned long get_ds(void)
{
/* return the supervisor data space code */
return KERNEL_DS;
}
 
static inline void set_fs(unsigned long val)
{
#ifndef NO_MM
__asm__ __volatile__ ("movec %0,%/sfc\n\t"
"movec %0,%/dfc\n\t"
: /* no outputs */ : "r" (val) : "memory");
#endif
}
 
#endif /* __ASSEMBLY__ */
 
#endif /* _M68K_SEGMENT_H */
/types.h
0,0 → 1,52
#ifndef _M68K_TYPES_H
#define _M68K_TYPES_H
 
/*
* This file is never included by application software unless
* explicitly requested (e.g., via linux/types.h) in which case the
* application is Linux specific so (user-) name space pollution is
* not a major issue. However, for interoperability, libraries still
* need to be careful to avoid a name clashes.
*/
 
typedef unsigned short umode_t;
 
/*
* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
* header files exported to user space
*/
 
typedef __signed__ char __s8;
typedef unsigned char __u8;
 
typedef __signed__ short __s16;
typedef unsigned short __u16;
 
typedef __signed__ int __s32;
typedef unsigned int __u32;
 
#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
typedef __signed__ long long __s64;
typedef unsigned long long __u64;
#endif
 
/*
* These aren't exported outside the kernel to avoid name space clashes
*/
#ifdef __KERNEL__
 
typedef signed char s8;
typedef unsigned char u8;
 
typedef signed short s16;
typedef unsigned short u16;
 
typedef signed int s32;
typedef unsigned int u32;
 
typedef signed long long s64;
typedef unsigned long long u64;
 
#endif /* __KERNEL__ */
 
#endif /* _M68K_TYPES_H */
/fcntl.h
0,0 → 1,59
#ifndef _M68K_FCNTL_H
#define _M68K_FCNTL_H
 
/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
located on an ext2 file system */
#define O_ACCMODE 0003
#define O_RDONLY 00
#define O_WRONLY 01
#define O_RDWR 02
#define O_CREAT 0100 /* not fcntl */
#define O_EXCL 0200 /* not fcntl */
#define O_NOCTTY 0400 /* not fcntl */
#define O_TRUNC 01000 /* not fcntl */
#define O_APPEND 02000
#define O_NONBLOCK 04000
#define O_NDELAY O_NONBLOCK
#define O_SYNC 010000
#define FASYNC 020000 /* fcntl, for BSD compatibility */
 
#define F_DUPFD 0 /* dup */
#define F_GETFD 1 /* get f_flags */
#define F_SETFD 2 /* set f_flags */
#define F_GETFL 3 /* more flags (cloexec) */
#define F_SETFL 4
#define F_GETLK 5
#define F_SETLK 6
#define F_SETLKW 7
 
#define F_SETOWN 8 /* for sockets. */
#define F_GETOWN 9 /* for sockets. */
 
/* for F_[GET|SET]FL */
#define FD_CLOEXEC 1 /* actually anything with low bit set goes */
 
/* for posix fcntl() and lockf() */
#define F_RDLCK 0
#define F_WRLCK 1
#define F_UNLCK 2
 
/* for old implementation of bsd flock () */
#define F_EXLCK 4 /* or 3 */
#define F_SHLCK 8 /* or 4 */
 
/* operations for bsd flock(), also used by the kernel implementation */
#define LOCK_SH 1 /* shared lock */
#define LOCK_EX 2 /* exclusive lock */
#define LOCK_NB 4 /* or'd with one of the above to prevent
blocking */
#define LOCK_UN 8 /* remove lock */
 
struct flock {
short l_type;
short l_whence;
off_t l_start;
off_t l_len;
pid_t l_pid;
};
 
#endif /* _M68K_FCNTL_H */
/string.h
0,0 → 1,549
#ifndef _M68K_STRING_H_
#define _M68K_STRING_H_
 
#include <linux/config.h>
#include <asm/page.h>
 
#if 0
 
#define __HAVE_ARCH_STRCPY
extern inline char * strcpy(char * dest,const char *src)
{
char *xdest = dest;
 
__asm__ __volatile__
("1:\tmoveb %1@+,%0@+\n\t"
"jne 1b"
: "=a" (dest), "=a" (src)
: "0" (dest), "1" (src) : "memory");
return xdest;
}
 
#define __HAVE_ARCH_STRNCPY
extern inline char * strncpy(char *dest, const char *src, size_t n)
{
char *xdest = dest;
 
if (n == 0)
return xdest;
 
__asm__ __volatile__
("1:\tmoveb %1@+,%0@+\n\t"
"jeq 2f\n\t"
"subql #1,%2\n\t"
"jne 1b\n\t"
"2:"
: "=a" (dest), "=a" (src), "=d" (n)
: "0" (dest), "1" (src), "2" (n)
: "memory");
return xdest;
}
 
#define __HAVE_ARCH_STRCAT
extern inline char * strcat(char * dest, const char * src)
{
char *tmp = dest;
 
while (*dest)
dest++;
while ((*dest++ = *src++))
;
 
return tmp;
}
 
#define __HAVE_ARCH_STRNCAT
extern inline char * strncat(char *dest, const char *src, size_t count)
{
char *tmp = dest;
 
if (count) {
while (*dest)
dest++;
while ((*dest++ = *src++)) {
if (--count == 0) {
*dest++='\0';
break;
}
}
}
 
return tmp;
}
 
#define __HAVE_ARCH_STRCHR
extern inline char * strchr(const char * s, int c)
{
const char ch = c;
for(; *s != ch; ++s)
if (*s == '\0')
return( NULL );
return( (char *) s);
}
 
#define __HAVE_ARCH_STRPBRK
extern inline char * strpbrk(const char * cs,const char * ct)
{
const char *sc1,*sc2;
for( sc1 = cs; *sc1 != '\0'; ++sc1)
for( sc2 = ct; *sc2 != '\0'; ++sc2)
if (*sc1 == *sc2)
return((char *) sc1);
return( NULL );
}
 
#define __HAVE_ARCH_STRSPN
extern inline size_t strspn(const char *s, const char *accept)
{
const char *p;
const char *a;
size_t count = 0;
 
for (p = s; *p != '\0'; ++p)
{
for (a = accept; *a != '\0'; ++a)
if (*p == *a)
break;
if (*a == '\0')
return count;
else
++count;
}
 
return count;
}
 
#define __HAVE_ARCH_STRTOK
extern inline char * strtok(char * s,const char * ct)
{
char *sbegin, *send;
sbegin = s ? s : ___strtok;
if (!sbegin) {
return NULL;
}
sbegin += strspn(sbegin,ct);
if (*sbegin == '\0') {
___strtok = NULL;
return( NULL );
}
send = strpbrk( sbegin, ct);
if (send && *send != '\0')
*send++ = '\0';
___strtok = send;
return (sbegin);
}
 
/* strstr !! */
 
#define __HAVE_ARCH_STRLEN
extern inline size_t strlen(const char * s)
{
const char *sc;
for (sc = s; *sc != '\0'; ++sc) ;
return(sc - s);
}
 
/* strnlen !! */
 
#define __HAVE_ARCH_STRCMP
extern inline int strcmp(const char * cs,const char * ct)
{
char __res;
 
__asm__
("1:\tmoveb %0@+,%2\n\t" /* get *cs */
"cmpb %1@+,%2\n\t" /* compare a byte */
"jne 2f\n\t" /* not equal, break out */
"tstb %2\n\t" /* at end of cs? */
"jne 1b\n\t" /* no, keep going */
"jra 3f\n\t" /* strings are equal */
"2:\tsubb %1@-,%2\n\t" /* *cs - *ct */
"3:"
: "=a" (cs), "=a" (ct), "=d" (__res)
: "0" (cs), "1" (ct));
return __res;
}
 
#define __HAVE_ARCH_STRNCMP
extern inline int strncmp(const char * cs,const char * ct,size_t count)
{
char __res;
 
if (!count)
return 0;
__asm__
("1:\tmovb %0@+,%3\n\t" /* get *cs */
"cmpb %1@+,%3\n\t" /* compare a byte */
"jne 3f\n\t" /* not equal, break out */
"tstb %3\n\t" /* at end of cs? */
"jeq 4f\n\t" /* yes, all done */
"subql #1,%2\n\t" /* no, adjust count */
"jne 1b\n\t" /* more to do, keep going */
"2:\tmoveq #0,%3\n\t" /* strings are equal */
"jra 4f\n\t"
"3:\tsubb %1@-,%3\n\t" /* *cs - *ct */
"4:"
: "=a" (cs), "=a" (ct), "=d" (count), "=d" (__res)
: "0" (cs), "1" (ct), "2" (count));
return __res;
}
 
#define __HAVE_ARCH_MEMSET
/*
* This is really ugly, but its highly optimizatiable by the
* compiler and is meant as compensation for gcc's missing
* __builtin_memset(). For the 680[23]0 it might be worth considering
* the optimal number of misaligned writes compared to the number of
* tests'n'branches needed to align the destination address. The
* 680[46]0 doesn't really care due to their copy-back caches.
* 10/09/96 - Jes Sorensen
*/
extern inline void * __memset_g(void * s, int c, size_t count)
{
void *xs = s;
size_t temp;
 
if (!count)
return xs;
 
c &= 0xff;
c |= c << 8;
c |= c << 16;
 
if (count < 36){
long *ls = s;
 
switch(count){
case 32: case 33: case 34: case 35:
*ls++ = c;
case 28: case 29: case 30: case 31:
*ls++ = c;
case 24: case 25: case 26: case 27:
*ls++ = c;
case 20: case 21: case 22: case 23:
*ls++ = c;
case 16: case 17: case 18: case 19:
*ls++ = c;
case 12: case 13: case 14: case 15:
*ls++ = c;
case 8: case 9: case 10: case 11:
*ls++ = c;
case 4: case 5: case 6: case 7:
*ls++ = c;
break;
default:
break;
}
s = ls;
if (count & 0x02){
short *ss = s;
*ss++ = c;
s = ss;
}
if (count & 0x01){
char *cs = s;
*cs++ = c;
s = cs;
}
return xs;
}
 
if ((long) s & 1)
{
char *cs = s;
*cs++ = c;
s = cs;
count--;
}
if (count > 2 && (long) s & 2)
{
short *ss = s;
*ss++ = c;
s = ss;
count -= 2;
}
temp = count >> 2;
if (temp)
{
long *ls = s;
temp--;
do
*ls++ = c;
while (temp--);
s = ls;
}
if (count & 2)
{
short *ss = s;
*ss++ = c;
s = ss;
}
if (count & 1)
{
char *cs = s;
*cs = c;
}
return xs;
}
 
/*
* __memset_page assumes that data is longword aligned. Most, if not
* all, of these page sized memsets are performed on page aligned
* areas, thus we do not need to check if the destination is longword
* aligned. Of course we suffer a serious performance loss if this is
* not the case but I think the risk of this ever happening is
* extremely small. We spend a lot of time clearing pages in
* get_empty_page() so I think it is worth it anyway. Besides, the
* 680[46]0 do not really care about misaligned writes due to their
* copy-back cache.
*
* The optimized case for the 680[46]0 is implemented using the move16
* instruction. My tests showed that this implementation is 35-45%
* faster than the original implementation using movel, the only
* caveat is that the destination address must be 16-byte aligned.
* 01/09/96 - Jes Sorensen
*/
extern inline void * __memset_page(void * s,int c,size_t count)
{
unsigned long data, tmp;
void *xs, *sp;
 
xs = sp = s;
 
c = c & 255;
data = c | (c << 8);
data |= data << 16;
 
#if defined(CONFIG_OPTIMIZE_040) || defined(CONFIG_OPTIMIZE_060)
 
if (((unsigned long) s) & 0x0f)
memset(s, c, count);
else{
*((unsigned long *)(s))++ = data;
*((unsigned long *)(s))++ = data;
*((unsigned long *)(s))++ = data;
*((unsigned long *)(s))++ = data;
 
__asm__ __volatile__("1:\t"
"move16 %2@+,%0@+\n\t"
"subqw #8,%2\n\t"
"subqw #8,%2\n\t"
"subql #1,%1\n\t"
"bne 1b\n\t"
: "=a" (s), "=d" (tmp)
: "a" (sp), "0" (s), "1" ((count - 16) / 16)
);
}
 
#else
__asm__ __volatile__("1:\t"
"movel %2,%0@+\n\t"
"movel %2,%0@+\n\t"
"movel %2,%0@+\n\t"
"movel %2,%0@+\n\t"
"movel %2,%0@+\n\t"
"movel %2,%0@+\n\t"
"movel %2,%0@+\n\t"
"movel %2,%0@+\n\t"
"subql #1,%1\n\t"
"bne 1b\n\t"
: "=a" (s), "=d" (tmp)
: "d" (data), "0" (s), "1" (count / 32)
);
#endif
 
return xs;
}
 
#define __memset_const(s,c,count) \
((count==PAGE_SIZE) ? \
__memset_page((s),(c),(count)) : \
__memset_g((s),(c),(count)))
 
#define memset(s, c, count) \
(__builtin_constant_p(count) ? \
__memset_const((s),(c),(count)) : \
memset((s),(c),(count)))
 
#define __HAVE_ARCH_MEMCPY
/*
* __builtin_memcpy() does not handle page-sized memcpys very well,
* thus following the same assumptions as for page-sized memsets, this
* function copies page-sized areas using an unrolled loop, without
* considering alignment.
*
* For the 680[46]0 only kernels we use the move16 instruction instead
* as it writes through the data-cache, invalidating the cache-lines
* touched. In this way we do not use up the entire data-cache (well,
* half of it on the 68060) by copying a page. An unrolled loop of two
* move16 instructions seem to the fastest. The only caveat is that
* both source and destination must be 16-byte aligned, if not we fall
* back to the generic memcpy function. - Jes
*/
extern inline void * __memcpy_page(void * to, const void * from, size_t count)
{
unsigned long tmp;
void *xto = to;
 
#if defined(CONFIG_OPTIMIZE_040) || defined(CONFIG_OPTIMIZE_060)
 
if (((unsigned long) to | (unsigned long) from) & 0x0f)
return memcpy(to, from, count);
 
__asm__ __volatile__("1:\t"
"move16 %1@+,%0@+\n\t"
"move16 %1@+,%0@+\n\t"
"subql #1,%2\n\t"
"bne 1b\n\t"
: "=a" (to), "=a" (from), "=d" (tmp)
: "0" (to), "1" (from) , "2" (count / 32)
);
#else
__asm__ __volatile__("1:\t"
"movel %1@+,%0@+\n\t"
"movel %1@+,%0@+\n\t"
"movel %1@+,%0@+\n\t"
"movel %1@+,%0@+\n\t"
"movel %1@+,%0@+\n\t"
"movel %1@+,%0@+\n\t"
"movel %1@+,%0@+\n\t"
"movel %1@+,%0@+\n\t"
"subql #1,%2\n\t"
"bne 1b\n\t"
: "=a" (to), "=a" (from), "=d" (tmp)
: "0" (to), "1" (from) , "2" (count / 32)
);
#endif
return xto;
}
 
#define __memcpy_const(to, from, n) \
((n==PAGE_SIZE) ? \
__memcpy_page((to),(from),(n)) : \
__builtin_memcpy((to),(from),(n)))
 
#define memcpy(to, from, n) \
(__builtin_constant_p(n) ? \
__memcpy_const((to),(from),(n)) : \
memcpy((to),(from),(n)))
 
#define __HAVE_ARCH_MEMMOVE
extern inline void * memmove(void * dest,const void * src, size_t n)
{
void *xdest = dest;
size_t temp;
 
if (!n)
return xdest;
 
if (dest < src)
{
if ((long) dest & 1)
{
char *cdest = dest;
const char *csrc = src;
*cdest++ = *csrc++;
dest = cdest;
src = csrc;
n--;
}
if (n > 2 && (long) dest & 2)
{
short *sdest = dest;
const short *ssrc = src;
*sdest++ = *ssrc++;
dest = sdest;
src = ssrc;
n -= 2;
}
temp = n >> 2;
if (temp)
{
long *ldest = dest;
const long *lsrc = src;
temp--;
do
*ldest++ = *lsrc++;
while (temp--);
dest = ldest;
src = lsrc;
}
if (n & 2)
{
short *sdest = dest;
const short *ssrc = src;
*sdest++ = *ssrc++;
dest = sdest;
src = ssrc;
}
if (n & 1)
{
char *cdest = dest;
const char *csrc = src;
*cdest = *csrc;
}
}
else
{
dest = (char *) dest + n;
src = (const char *) src + n;
if ((long) dest & 1)
{
char *cdest = dest;
const char *csrc = src;
*--cdest = *--csrc;
dest = cdest;
src = csrc;
n--;
}
if (n > 2 && (long) dest & 2)
{
short *sdest = dest;
const short *ssrc = src;
*--sdest = *--ssrc;
dest = sdest;
src = ssrc;
n -= 2;
}
temp = n >> 2;
if (temp)
{
long *ldest = dest;
const long *lsrc = src;
temp--;
do
*--ldest = *--lsrc;
while (temp--);
dest = ldest;
src = lsrc;
}
if (n & 2)
{
short *sdest = dest;
const short *ssrc = src;
*--sdest = *--ssrc;
dest = sdest;
src = ssrc;
}
if (n & 1)
{
char *cdest = dest;
const char *csrc = src;
*--cdest = *--csrc;
}
}
return xdest;
}
 
#define __HAVE_ARCH_MEMCMP
#define memcmp(cs, ct, n) \
(__builtin_constant_p(n) ? \
__builtin_memcmp((cs),(ct),(n)) : \
memcmp((cs),(ct),(n)))
 
#endif
 
#endif /* _M68K_STRING_H_ */
/io.h
0,0 → 1,378
#ifndef _M68K_IO_H
#define _M68K_IO_H
 
/*
* readX/writeX() are used to access memory mapped devices. On some
* architectures the memory mapped IO stuff needs to be accessed
* differently. On the m68k architecture, we just read/write the
* memory location directly.
*/
/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
* two accesses to memory, which may be undesireable for some devices.
*/
#define readb(addr) \
({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
#define readw(addr) \
({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
#define readl(addr) \
({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
 
#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b))
#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b))
#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
 
#if 0
 
/* There is no difference between I/O and memory on 68k, these are the same */
#define inb(addr) \
({ unsigned char __v = (*(volatile unsigned char *) (addr)); printk("inb(%x)=%02x\n", (addr), __v); __v; })
#define inw(addr) \
({ unsigned short __v = (*(volatile unsigned short *) (addr)); printk("inw(%x)=%04x\n", (addr), __v); __v; })
#define inl(addr) \
({ unsigned int __v = (*(volatile unsigned int *) (addr)); printk("inl(%x)=%08x\n", (addr), __v); __v; })
 
#define outb(b,addr) { ((*(volatile unsigned char *) (addr)) = (b)) ; printk("outb(%x)=%02x\n", (addr), (b)); }
#define outw(b,addr) { ((*(volatile unsigned short *) (addr)) = (b)) ; printk("outw(%x)=%04x\n", (addr), (b)); }
#define outl(b,addr) { ((*(volatile unsigned int *) (addr)) = (b)) ; printk("outl(%x)=%08x\n", (addr), (b)); }
 
#else
 
/* There is no difference between I/O and memory on 68k, these are the same */
#define inb(addr) \
({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
#define inw(addr) \
({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
#define inl(addr) \
({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
 
#define outb(b,addr) ((*(volatile unsigned char *) (addr)) = (b))
#define outw(b,addr) ((*(volatile unsigned short *) (addr)) = (b))
#define outl(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
 
#endif
 
#ifdef CONFIG_COLDFIRE
 
#define inb_p inb
#define inw_p inw
#define outb_p outb
#define outw_p outw
 
 
static inline void outsb(void *addr, void *buf, int len)
{
volatile unsigned char *ap = (volatile unsigned char *) addr;
unsigned char *bp = (unsigned char *) buf;
while (len--)
*ap = *bp++;
}
 
static inline void outsw(void *addr, void *buf, int len)
{
volatile unsigned short *ap = (volatile unsigned short *) addr;
unsigned short *bp = (unsigned short *) buf;
while (len--)
*ap = *bp++;
}
 
static inline void outsl(void *addr, void *buf, int len)
{
volatile unsigned int *ap = (volatile unsigned int *) addr;
unsigned int *bp = (unsigned int *) buf;
while (len--)
*ap = *bp++;
}
 
static inline void insb(void *addr, void *buf, int len)
{
volatile unsigned char *ap = (volatile unsigned char *) addr;
unsigned char *bp = (unsigned char *) buf;
while (len--)
*bp++ = *ap;
}
 
static inline void insw(void *addr, void *buf, int len)
{
volatile unsigned short *ap = (volatile unsigned short *) addr;
unsigned short *bp = (unsigned short *) buf;
while (len--)
*bp++ = *ap;
}
 
static inline void insl(void *addr, void *buf, int len)
{
volatile unsigned int *ap = (volatile unsigned int *) addr;
unsigned int *bp = (unsigned int *) buf;
while (len--)
*bp++ = *ap;
}
 
#else
 
/* These try and unroll 64 transfers, then 8, then 1 at a time */
static inline void outsw(void *addr,void *buf,int len)
{
unsigned short * __e = (unsigned short *)(buf) + (len);
unsigned short * __p = (unsigned short *)(buf);
while (__p + 32 < __e) {
asm volatile ("
movem.w %0@+, %%d4-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d5, %2@;
movem.w %%d6-%%d7, %2@;
 
movem.w %0@+, %%d4-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d5, %2@;
movem.w %%d6-%%d7, %2@;
 
movem.w %0@+, %%d4-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d5, %2@;
movem.w %%d6-%%d7, %2@;
 
movem.w %0@+, %%d4-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d5, %2@;
movem.w %%d6-%%d7, %2@;
 
movem.w %0@+, %%d4-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d5, %2@;
movem.w %%d6-%%d7, %2@;
 
movem.w %0@+, %%d4-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d5, %2@;
movem.w %%d6-%%d7, %2@;
 
movem.w %0@+, %%d4-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d5, %2@;
movem.w %%d6-%%d7, %2@;
 
movem.w %0@+, %%d4-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d5, %2@;
movem.w %%d6-%%d7, %2@;
 
"
: "=a" (__p)
: "0" (__p) , "a" (addr)
: "d4", "d5", "d6", "d7");
}
while (__p + 8 < __e) {
asm volatile ("
movem.w %0@+, %%d4-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d5, %2@;
movem.w %%d6-%%d7, %2@;
movem.w %0@+, %%d4-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d5, %2@;
movem.w %%d6-%%d7, %2@;
"
: "=a" (__p)
: "0" (__p) , "a" (addr)
: "d4", "d5", "d6", "d7");
}
while (__p < __e) {
*(volatile unsigned short *)(addr) =
(((*__p) & 0xff) << 8) | ((*__p) >> 8);
__p++;
}
}
 
static inline void insw(void *addr,void *buf,int len)
{
unsigned short * __e = (unsigned short *)(buf) + (len);
unsigned short * __p = (unsigned short *)(buf);
unsigned short __v;
while (__p + 32 < __e) {
asm volatile ("
movem.w %2@, %%d4-%%d5;
movem.w %2@, %%d6-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d7, %0@;
addq #8, %0;
movem.w %2@, %%d4-%%d5;
movem.w %2@, %%d6-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d7, %0@;
addq #8, %0;
movem.w %2@, %%d4-%%d5;
movem.w %2@, %%d6-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d7, %0@;
addq #8, %0;
movem.w %2@, %%d4-%%d5;
movem.w %2@, %%d6-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d7, %0@;
addq #8, %0;
movem.w %2@, %%d4-%%d5;
movem.w %2@, %%d6-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d7, %0@;
addq #8, %0;
movem.w %2@, %%d4-%%d5;
movem.w %2@, %%d6-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d7, %0@;
addq #8, %0;
movem.w %2@, %%d4-%%d5;
movem.w %2@, %%d6-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d7, %0@;
addq #8, %0;
movem.w %2@, %%d4-%%d5;
movem.w %2@, %%d6-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d7, %0@;
addq #8, %0;
"
: "=a" (__p)
: "0" (__p) , "a" (addr)
: "d4", "d5", "d6", "d7");
}
while (__p + 8 < __e) {
asm volatile ("
movem.w %2@, %%d4-%%d5;
movem.w %2@, %%d6-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d7, %0@;
addq #8, %0;
movem.w %2@, %%d4-%%d5;
movem.w %2@, %%d6-%%d7;
rol.w #8, %%d4;
rol.w #8, %%d5;
rol.w #8, %%d6;
rol.w #8, %%d7;
movem.w %%d4-%%d7, %0@;
addq #8, %0;
"
: "=a" (__p)
: "0" (__p) , "a" (addr)
: "d4", "d5", "d6", "d7");
}
while (__p < __e) {
__v = *(volatile unsigned short *)(addr);
*(__p++) = ((__v & 0xff) << 8) | (__v >> 8);
}
}
 
#define inb_p(addr) get_user_byte_io((char *)(addr))
#define outb_p(x,addr) put_user_byte_io((x),(char *)(addr))
 
#endif /* CONFIG_COLDFIRE */
 
static inline unsigned char get_user_byte_io(const char * addr)
{
register unsigned char _v;
 
__asm__ __volatile__ ("moveb %1,%0":"=dm" (_v):"m" (*addr));
return _v;
}
 
static inline void put_user_byte_io(char val,char *addr)
{
__asm__ __volatile__ ("moveb %0,%1"
: /* no outputs */
:"idm" (val),"m" (*addr)
: "memory");
}
 
/*
* Change virtual addresses to physical addresses and vv.
* These are trivial on the 1:1 Linux/i386 mapping (but if we ever
* make the kernel segment mapped at 0, we need to do translation
* on the i386 as well)
*/
extern unsigned long mm_vtop(unsigned long addr);
extern unsigned long mm_ptov(unsigned long addr);
 
extern inline unsigned long virt_to_phys(volatile void * address)
{
return (unsigned long) mm_vtop((unsigned long)address);
}
 
extern inline void * phys_to_virt(unsigned long address)
{
return (void *) mm_ptov(address);
}
 
/*
* IO bus memory addresses are also 1:1 with the physical address
*/
#define virt_to_bus virt_to_phys
#define bus_to_virt phys_to_virt
 
 
#endif /* _M68K_IO_H */
/mcfsmc.h
0,0 → 1,166
/****************************************************************************/
 
/*
* mcfsmc.h -- SMC ethernet support for ColdFire environments.
*
* (C) Copyright 1999, Greg Ungerer (gerg@moreton.com.au)
*/
 
/****************************************************************************/
#ifndef mcfsmc_h
#define mcfsmc_h
/****************************************************************************/
 
#include <linux/config.h>
 
#undef outb
#undef inb
 
/*
* Re-defines for ColdFire environment... The SMC part is
* mapped into memory space, so remap the PC-style in/out
* routines to handle that.
*/
#define outb smc_outb
#define inb smc_inb
#define outw smc_outw
#define outwd smc_outwd
#define inw smc_inw
#define outl smc_outl
#define inl smc_inl
 
#define outsb smc_outsb
#define outsw smc_outsw
#define outsl smc_outsl
#define insb smc_insb
#define insw smc_insw
#define insl smc_insl
 
 
inline int smc_inb(unsigned int addr)
{
register unsigned short w;
w = *((volatile unsigned short *) (addr & ~0x1));
return(((addr & 0x1) ? w : (w >> 8)) & 0xff);
}
 
inline void smc_outw(unsigned int val, unsigned int addr)
{
*((volatile unsigned short *) addr) = ((val << 8) | (val >> 8));
}
 
inline int smc_inw(unsigned int addr)
{
register unsigned short w;
w = *((volatile unsigned short *) addr);
return(((w << 8) | (w >> 8)) & 0xffff);
}
 
inline void smc_outl(unsigned long val, unsigned int addr)
{
*((volatile unsigned long *) addr) =
((val << 8) & 0xff000000) | ((val >> 8) & 0x00ff0000) |
((val << 8) & 0x0000ff00) | ((val >> 8) & 0x000000ff);
}
 
inline void smc_outwd(unsigned int val, unsigned int addr)
{
*((volatile unsigned short *) addr) = val;
}
 
 
/*
* The rep* functions are used to feed the data port with
* raw data. So we do not byte swap them when copying.
*/
 
inline void smc_insb(unsigned int addr, void *vbuf, int unsigned long len)
{
volatile unsigned short *rp;
unsigned short *buf, *ebuf;
 
buf = (unsigned short *) vbuf;
rp = (volatile unsigned short *) addr;
 
/* Copy as words for as long as possible */
for (ebuf = buf + (len >> 1); (buf < ebuf); )
*buf++ = *rp;
 
/* Lastly, handle left over byte */
if (len & 0x1)
*((unsigned char *) buf) = (*rp >> 8) & 0xff;
}
 
inline void smc_insw(unsigned int addr, void *vbuf, unsigned long len)
{
volatile unsigned short *rp;
unsigned short *buf, *ebuf;
 
buf = (unsigned short *) vbuf;
rp = (volatile unsigned short *) addr;
for (ebuf = buf + len; (buf < ebuf); )
*buf++ = *rp;
}
 
inline void smc_insl(unsigned int addr, void *vbuf, unsigned long len)
{
volatile unsigned long *rp;
unsigned long *buf, *ebuf;
 
buf = (unsigned long *) vbuf;
rp = (volatile unsigned long *) addr;
for (ebuf = buf + len; (buf < ebuf); )
*buf++ = *rp;
}
 
inline void smc_outsw(unsigned int addr, const void *vbuf, unsigned long len)
{
volatile unsigned short *rp;
unsigned short *buf, *ebuf;
 
buf = (unsigned short *) vbuf;
rp = (volatile unsigned short *) addr;
for (ebuf = buf + len; (buf < ebuf); )
*rp = *buf++;
}
 
inline void smc_outsl(unsigned int addr, void *vbuf, unsigned long len)
{
volatile unsigned long *rp;
unsigned long *buf, *ebuf;
 
buf = (unsigned long *) vbuf;
rp = (volatile unsigned long *) addr;
for (ebuf = buf + len; (buf < ebuf); )
*rp = *buf++;
}
 
 
#ifdef CONFIG_NETtel
/*
* Re-map the address space of at least one of the SMC ethernet
* parts. Both parts power up decoding the same address, so we
* need to move one of them first, before doing enything else.
*/
 
void smc_remap(unsigned int ioaddr)
{
static int once = 0;
extern unsigned short ppdata;
if (once++ == 0) {
*((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADDR)) = 0x00ec;
ppdata |= 0x0080;
*((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADAT)) = ppdata;
outw(0x0001, ioaddr + BANK_SELECT);
outw(0x0001, ioaddr + BANK_SELECT);
outw(0x0067, ioaddr + BASE);
 
ppdata &= ~0x0080;
*((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADAT)) = ppdata;
}
}
 
#endif
 
/****************************************************************************/
#endif /* mcfsmc_h */
/MC68328.h
0,0 → 1,1241
 
/* include/asm-m68knommu/MC68328.h: '328 control registers
*
* Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
* Bear & Hare Software, Inc.
*
* Based on include/asm-m68knommu/MC68332.h
* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
* The Silver Hammer Group, Ltd.
*
*/
 
#ifndef _MC68328_H_
#define _MC68328_H_
 
#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
#define WORD_REF(addr) (*((volatile unsigned short*)addr))
#define LONG_REF(addr) (*((volatile unsigned long*)addr))
 
#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
 
/**********
*
* 0xFFFFF0xx -- System Control
*
**********/
/*
* System Control Register (SCR)
*/
#define SCR_ADDR 0xfffff000
#define SCR BYTE_REF(SCR_ADDR)
 
#define SCR_WDTH8 0x01 /* 8-Bit Width Select */
#define SCR_DMAP 0x04 /* Double Map */
#define SCR_SO 0x08 /* Supervisor Only */
#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
#define SCR_PRV 0x20 /* Privilege Violation */
#define SCR_WPV 0x40 /* Write Protect Violation */
#define SCR_BETO 0x80 /* Bus-Error TimeOut */
 
/*
* Mask Revision Register
*/
#define MRR_ADDR 0xfffff004
#define MRR LONG_REF(MRR_ADDR)
/**********
*
* 0xFFFFF1xx -- Chip-Select logic
*
**********/
 
/**********
*
* 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
*
**********/
 
/*
* Group Base Address Registers
*/
#define GRPBASEA_ADDR 0xfffff100
#define GRPBASEB_ADDR 0xfffff102
#define GRPBASEC_ADDR 0xfffff104
#define GRPBASED_ADDR 0xfffff106
 
#define GRPBASEA WORD_REF(GRPBASEA_ADDR)
#define GRPBASEB WORD_REF(GRPBASEB_ADDR)
#define GRPBASEC WORD_REF(GRPBASEC_ADDR)
#define GRPBASED WORD_REF(GRPBASED_ADDR)
 
#define GRPBASE_V 0x0001 /* Valid */
#define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
 
/*
* Group Base Address Mask Registers
*/
#define GRPMASKA_ADDR 0xfffff108
#define GRPMASKB_ADDR 0xfffff10a
#define GRPMASKC_ADDR 0xfffff10c
#define GRPMASKD_ADDR 0xfffff10e
 
#define GRPMASKA WORD_REF(GRPMASKA_ADDR)
#define GRPMASKB WORD_REF(GRPMASKB_ADDR)
#define GRPMASKC WORD_REF(GRPMASKC_ADDR)
#define GRPMASKD WORD_REF(GRPMASKD_ADDR)
 
#define GRMMASK_GMA_MASK 0xfffff0 /* Group Base Mask (bits 31-20) */
 
/*
* Chip-Select Option Registers (group A)
*/
#define CSA0_ADDR 0xfffff110
#define CSA1_ADDR 0xfffff114
#define CSA2_ADDR 0xfffff118
#define CSA3_ADDR 0xfffff11c
 
#define CSA0 LONG_REF(CSA0_ADDR)
#define CSA1 LONG_REF(CSA1_ADDR)
#define CSA2 LONG_REF(CSA2_ADDR)
#define CSA3 LONG_REF(CSA3_ADDR)
 
#define CSA_WAIT_MASK 0x00000007 /* Wait State Selection */
#define CSA_WAIT_SHIFT 0
#define CSA_RO 0x00000008 /* Read-Only */
#define CSA_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
#define CSA_AM_SHIFT 8
#define CSA_BUSW 0x00010000 /* Bus Width Select */
#define CSA_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
#define CSA_AC_SHIFT 24
 
/*
* Chip-Select Option Registers (group B)
*/
#define CSB0_ADDR 0xfffff120
#define CSB1_ADDR 0xfffff124
#define CSB2_ADDR 0xfffff128
#define CSB3_ADDR 0xfffff12c
 
#define CSB0 LONG_REF(CSB0_ADDR)
#define CSB1 LONG_REF(CSB1_ADDR)
#define CSB2 LONG_REF(CSB2_ADDR)
#define CSB3 LONG_REF(CSB3_ADDR)
 
#define CSB_WAIT_MASK 0x00000007 /* Wait State Selection */
#define CSB_WAIT_SHIFT 0
#define CSB_RO 0x00000008 /* Read-Only */
#define CSB_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */
#define CSB_AM_SHIFT 8
#define CSB_BUSW 0x00010000 /* Bus Width Select */
#define CSB_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */
#define CSB_AC_SHIFT 24
 
/*
* Chip-Select Option Registers (group C)
*/
#define CSC0_ADDR 0xfffff130
#define CSC1_ADDR 0xfffff134
#define CSC2_ADDR 0xfffff138
#define CSC3_ADDR 0xfffff13c
 
#define CSC0 LONG_REF(CSC0_ADDR)
#define CSC1 LONG_REF(CSC1_ADDR)
#define CSC2 LONG_REF(CSC2_ADDR)
#define CSC3 LONG_REF(CSC3_ADDR)
 
#define CSC_WAIT_MASK 0x00000007 /* Wait State Selection */
#define CSC_WAIT_SHIFT 0
#define CSC_RO 0x00000008 /* Read-Only */
#define CSC_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
#define CSC_AM_SHIFT 4
#define CSC_BUSW 0x00010000 /* Bus Width Select */
#define CSC_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
#define CSC_AC_SHIFT 20
 
/*
* Chip-Select Option Registers (group D)
*/
#define CSD0_ADDR 0xfffff140
#define CSD1_ADDR 0xfffff144
#define CSD2_ADDR 0xfffff148
#define CSD3_ADDR 0xfffff14c
 
#define CSD0 LONG_REF(CSD0_ADDR)
#define CSD1 LONG_REF(CSD1_ADDR)
#define CSD2 LONG_REF(CSD2_ADDR)
#define CSD3 LONG_REF(CSD3_ADDR)
 
#define CSD_WAIT_MASK 0x00000007 /* Wait State Selection */
#define CSD_WAIT_SHIFT 0
#define CSD_RO 0x00000008 /* Read-Only */
#define CSD_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */
#define CSD_AM_SHIFT 4
#define CSD_BUSW 0x00010000 /* Bus Width Select */
#define CSD_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */
#define CSD_AC_SHIFT 20
 
/**********
*
* 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
*
**********/
/*
* PLL Control Register
*/
#define PLLCR_ADDR 0xfffff200
#define PLLCR WORD_REF(PLLCR_ADDR)
 
#define PLLCR_DISPLL 0x0008 /* Disable PLL */
#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
#define PLLCR_SYSCLK_SEL_SHIFT 8
#define PLLCR_PIXCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
#define PLLCR_PIXCLK_SEL_SHIFT 11
 
/* 'EZ328-compatible definitions */
#define PLLCR_LCDCLK_SEL_MASK PLLCR_PIXCLK_SEL_MASK
#define PLLCR_LCDCLK_SEL_SHIFT PLLCR_PIXCLK_SEL_SHIFT
 
/*
* PLL Frequency Select Register
*/
#define PLLFSR_ADDR 0xfffff202
#define PLLFSR WORD_REF(PLLFSR_ADDR)
 
#define PLLFSR_PC_MASK 0x00ff /* P Count */
#define PLLFSR_PC_SHIFT 0
#define PLLFSR_QC_MASK 0x0f00 /* Q Count */
#define PLLFSR_QC_SHIFT 8
#define PLLFSR_PROT 0x4000 /* Protect P & Q */
#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
 
/*
* Power Control Register
*/
#define PCTRL_ADDR 0xfffff207
#define PCTRL BYTE_REF(PCTRL_ADDR)
 
#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
#define PCTRL_WIDTH_SHIFT 0
#define PCTRL_STOP 0x40 /* Enter power-save mode immediately */
#define PCTRL_PCEN 0x80 /* Power Control Enable */
 
/**********
*
* 0xFFFFF3xx -- Interrupt Controller
*
**********/
 
/*
* Interrupt Vector Register
*/
#define IVR_ADDR 0xfffff300
#define IVR BYTE_REF(IVR_ADDR)
 
#define IVR_VECTOR_MASK 0xF8
 
/*
* Interrupt control Register
*/
#define ICR_ADRR 0xffff302
#define ICR WORD_REF(ICR_ADDR)
 
#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
 
/*
* Interrupt Mask Register
*/
#define IMR_ADDR 0xfffff304
#define IMR LONG_REF(IMR_ADDR)
/*
* Define the names for bit positions first. This is useful for
* request_irq
*/
#define SPIM_IRQ_NUM 0 /* SPI Master interrupt */
#define TMR2_IRQ_NUM 1 /* Timer 2 interrupt */
#define UART_IRQ_NUM 2 /* UART interrupt */
#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
#define RTC_IRQ_NUM 4 /* RTC interrupt */
#define KB_IRQ_NUM 6 /* Keyboard Interrupt */
#define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */
#define INT0_IRQ_NUM 8 /* External INT0 */
#define INT1_IRQ_NUM 9 /* External INT1 */
#define INT2_IRQ_NUM 10 /* External INT2 */
#define INT3_IRQ_NUM 11 /* External INT3 */
#define INT4_IRQ_NUM 12 /* External INT4 */
#define INT5_IRQ_NUM 13 /* External INT5 */
#define INT6_IRQ_NUM 14 /* External INT6 */
#define INT7_IRQ_NUM 15 /* External INT7 */
#define IRQ1_IRQ_NUM 16 /* IRQ1 */
#define IRQ2_IRQ_NUM 17 /* IRQ2 */
#define IRQ3_IRQ_NUM 18 /* IRQ3 */
#define IRQ6_IRQ_NUM 19 /* IRQ6 */
#define PEN_IRQ_NUM 20 /* Pen Interrupt */
#define SPIS_IRQ_NUM 21 /* SPI Slave Interrupt */
#define TMR1_IRQ_NUM 22 /* Timer 1 interrupt */
#define IRQ7_IRQ_NUM 23 /* IRQ7 */
 
/* '328-compatible definitions */
#define SPI_IRQ_NUM SPIM_IRQ_NUM
#define TMR_IRQ_NUM TMR1_IRQ_NUM
/*
* Here go the bitmasks themselves
*/
#define IMR_MSPIM (1 << SPIM _IRQ_NUM) /* Mask SPI Master interrupt */
#define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */
#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
#define IMR_MINT4 (1 << INT4_IRQ_NUM) /* Mask External INT4 */
#define IMR_MINT5 (1 << INT5_IRQ_NUM) /* Mask External INT5 */
#define IMR_MINT6 (1 << INT6_IRQ_NUM) /* Mask External INT6 */
#define IMR_MINT7 (1 << INT7_IRQ_NUM) /* Mask External INT7 */
#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
#define IMR_MPEN (1 << PEN_IRQ_NUM) /* Mask Pen Interrupt */
#define IMR_MSPIS (1 << SPIS_IRQ_NUM) /* Mask SPI Slave Interrupt */
#define IMR_MTMR1 (1 << TMR1_IRQ_NUM) /* Mask Timer 1 interrupt */
#define IMR_MIRQ7 (1 << IRQ7_IRQ_NUM) /* Mask IRQ7 */
 
/* 'EZ328-compatible definitions */
#define IMR_MSPI IMR_MSPIM
#define IMR_MTMR IMR_MTMR1
 
/*
* Interrupt Wake-Up Enable Register
*/
#define IWR_ADDR 0xfffff308
#define IWR LONG_REF(IWR_ADDR)
 
#define IWR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */
#define IWR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
#define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
#define IWR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
#define IWR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
#define IWR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
#define IWR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
#define IWR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
#define IWR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
#define IWR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
#define IWR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
#define IWR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
#define IWR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
#define IWR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
#define IWR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
#define IWR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
#define IWR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
#define IWR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
#define IWR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
#define IWR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
#define IWR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
#define IWR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
#define IWR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
 
/*
* Interrupt Status Register
*/
#define ISR_ADDR 0xfffff30c
#define ISR LONG_REF(ISR_ADDR)
 
#define ISR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */
#define ISR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
#define ISR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
#define ISR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
#define ISR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
#define ISR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
#define ISR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
#define ISR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
#define ISR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
#define ISR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
 
/* 'EZ328-compatible definitions */
#define ISR_SPI ISR_SPIM
#define ISR_TMR ISR_TMR1
 
/*
* Interrupt Pending Register
*/
#define IPR_ADDR 0xfffff310
#define IPR LONG_REF(IPR_ADDR)
 
#define IPR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */
#define IPR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */
#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */
#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
#define IPR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */
#define IPR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */
#define IPR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */
#define IPR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */
#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
#define IPR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */
#define IPR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */
#define IPR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */
#define IPR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */
 
/* 'EZ328-compatible definitions */
#define IPR_SPI IPR_SPIM
#define IPR_TMR IPR_TMR1
 
/**********
*
* 0xFFFFF4xx -- Parallel Ports
*
**********/
 
/*
* Port A
*/
#define PADIR_ADDR 0xfffff400 /* Port A direction reg */
#define PADATA_ADDR 0xfffff401 /* Port A data register */
#define PASEL_ADDR 0xfffff403 /* Port A Select register */
 
#define PADIR BYTE_REF(PADIR_ADDR)
#define PADATA BYTE_REF(PADATA_ADDR)
#define PASEL BYTE_REF(PASEL_ADDR)
 
#define PA(x) (1 << (x))
#define PA_A(x) PA((x) - 16) /* This is specific to PA only! */
 
#define PA_A16 PA(0) /* Use A16 as PA(0) */
#define PA_A17 PA(1) /* Use A17 as PA(1) */
#define PA_A18 PA(2) /* Use A18 as PA(2) */
#define PA_A19 PA(3) /* Use A19 as PA(3) */
#define PA_A20 PA(4) /* Use A20 as PA(4) */
#define PA_A21 PA(5) /* Use A21 as PA(5) */
#define PA_A22 PA(6) /* Use A22 as PA(6) */
#define PA_A23 PA(7) /* Use A23 as PA(7) */
 
/*
* Port B
*/
#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
#define PBDATA_ADDR 0xfffff409 /* Port B data register */
#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
 
#define PBDIR BYTE_REF(PBDIR_ADDR)
#define PBDATA BYTE_REF(PBDATA_ADDR)
#define PBSEL BYTE_REF(PBSEL_ADDR)
 
#define PB(x) (1 << (x))
#define PB_D(x) PB(x) /* This is specific to port B only */
 
#define PB_D0 PB(0) /* Use D0 as PB(0) */
#define PB_D1 PB(1) /* Use D1 as PB(1) */
#define PB_D2 PB(2) /* Use D2 as PB(2) */
#define PB_D3 PB(3) /* Use D3 as PB(3) */
#define PB_D4 PB(4) /* Use D4 as PB(4) */
#define PB_D5 PB(5) /* Use D5 as PB(5) */
#define PB_D6 PB(6) /* Use D6 as PB(6) */
#define PB_D7 PB(7) /* Use D7 as PB(7) */
 
/*
* Port C
*/
#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
#define PCDATA_ADDR 0xfffff411 /* Port C data register */
#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
 
#define PCDIR BYTE_REF(PCDIR_ADDR)
#define PCDATA BYTE_REF(PCDATA_ADDR)
#define PCSEL BYTE_REF(PCSEL_ADDR)
 
#define PC(x) (1 << (x))
 
#define PC_WE PC(6) /* Use WE as PC(6) */
#define PC_DTACK PC(5) /* Use DTACK as PC(5) */
#define PC_IRQ7 PC(4) /* Use IRQ7 as PC(4) */
#define PC_LDS PC(2) /* Use LDS as PC(2) */
#define PC_UDS PC(1) /* Use UDS as PC(1) */
#define PC_MOCLK PC(0) /* Use MOCLK as PC(0) */
 
/*
* Port D
*/
#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
#define PDDATA_ADDR 0xfffff419 /* Port D data register */
#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
 
#define PDDIR BYTE_REF(PDDIR_ADDR)
#define PDDATA BYTE_REF(PDDATA_ADDR)
#define PDPUEN BYTE_REF(PDPUEN_ADDR)
#define PDPOL BYTE_REF(PDPOL_ADDR)
#define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
#define PDIQEG BYTE_REF(PDIQEG_ADDR)
 
#define PD(x) (1 << (x))
#define PD_KB(x) PD(x) /* This is specific for Port D only */
 
#define PD_KB0 PD(0) /* Use KB0 as PD(0) */
#define PD_KB1 PD(1) /* Use KB1 as PD(1) */
#define PD_KB2 PD(2) /* Use KB2 as PD(2) */
#define PD_KB3 PD(3) /* Use KB3 as PD(3) */
#define PD_KB4 PD(4) /* Use KB4 as PD(4) */
#define PD_KB5 PD(5) /* Use KB5 as PD(5) */
#define PD_KB6 PD(6) /* Use KB6 as PD(6) */
#define PD_KB7 PD(7) /* Use KB7 as PD(7) */
 
/*
* Port E
*/
#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
#define PEDATA_ADDR 0xfffff421 /* Port E data register */
#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
#define PESEL_ADDR 0xfffff423 /* Port E Select Register */
 
#define PEDIR BYTE_REF(PEDIR_ADDR)
#define PEDATA BYTE_REF(PEDATA_ADDR)
#define PEPUEN BYTE_REF(PEPUEN_ADDR)
#define PESEL BYTE_REF(PESEL_ADDR)
 
#define PE(x) (1 << (x))
 
#define PE_CSA1 PE(1) /* Use CSA1 as PE(1) */
#define PE_CSA2 PE(2) /* Use CSA2 as PE(2) */
#define PE_CSA3 PE(3) /* Use CSA3 as PE(3) */
#define PE_CSB0 PE(4) /* Use CSB0 as PE(4) */
#define PE_CSB1 PE(5) /* Use CSB1 as PE(5) */
#define PE_CSB2 PE(6) /* Use CSB2 as PE(6) */
#define PE_CSB3 PE(7) /* Use CSB3 as PE(7) */
 
/*
* Port F
*/
#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
#define PFDATA_ADDR 0xfffff429 /* Port F data register */
#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
 
#define PFDIR BYTE_REF(PFDIR_ADDR)
#define PFDATA BYTE_REF(PFDATA_ADDR)
#define PFPUEN BYTE_REF(PFPUEN_ADDR)
#define PFSEL BYTE_REF(PFSEL_ADDR)
 
#define PF(x) (1 << (x))
#define PF_A(x) PF((x) - 24) /* This is Port F specific only */
 
#define PF_A24 PF(0) /* Use A24 as PF(0) */
#define PF_A25 PF(1) /* Use A25 as PF(1) */
#define PF_A26 PF(2) /* Use A26 as PF(2) */
#define PF_A27 PF(3) /* Use A27 as PF(3) */
#define PF_A28 PF(4) /* Use A28 as PF(4) */
#define PF_A29 PF(5) /* Use A29 as PF(5) */
#define PF_A30 PF(6) /* Use A30 as PF(6) */
#define PF_A31 PF(7) /* Use A31 as PF(7) */
 
/*
* Port G
*/
#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
#define PGDATA_ADDR 0xfffff431 /* Port G data register */
#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
 
#define PGDIR BYTE_REF(PGDIR_ADDR)
#define PGDATA BYTE_REF(PGDATA_ADDR)
#define PGPUEN BYTE_REF(PGPUEN_ADDR)
#define PGSEL BYTE_REF(PGSEL_ADDR)
 
#define PG(x) (1 << (x))
 
#define PG_UART_TXD PG(0) /* Use UART_TXD as PG(0) */
#define PG_UART_RXD PG(1) /* Use UART_RXD as PG(1) */
#define PG_PWMOUT PG(2) /* Use PWMOUT as PG(2) */
#define PG_TOUT2 PG(3) /* Use TOUT2 as PG(3) */
#define PG_TIN2 PG(4) /* Use TIN2 as PG(4) */
#define PG_TOUT1 PG(5) /* Use TOUT1 as PG(5) */
#define PG_TIN1 PG(6) /* Use TIN1 as PG(6) */
#define PG_RTCOUT PG(7) /* Use RTCOUT as PG(7) */
 
/*
* Port J
*/
#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */
#define PJDATA_ADDR 0xfffff439 /* Port J data register */
#define PJSEL_ADDR 0xfffff43b /* Port J Select Register */
 
#define PJDIR BYTE_REF(PJDIR_ADDR)
#define PJDATA BYTE_REF(PJDATA_ADDR)
#define PJSEL BYTE_REF(PJSEL_ADDR)
 
#define PJ(x) (1 << (x))
 
#define PJ_CSD3 PJ(7) /* Use CSD3 as PJ(7) */
 
/*
* Port K
*/
#define PKDIR_ADDR 0xfffff440 /* Port K direction reg */
#define PKDATA_ADDR 0xfffff441 /* Port K data register */
#define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enable reg */
#define PKSEL_ADDR 0xfffff443 /* Port K Select Register */
 
#define PKDIR BYTE_REF(PKDIR_ADDR)
#define PKDATA BYTE_REF(PKDATA_ADDR)
#define PKPUEN BYTE_REF(PKPUEN_ADDR)
#define PKSEL BYTE_REF(PKSEL_ADDR)
 
#define PK(x) (1 << (x))
 
/*
* Port M
*/
#define PMDIR_ADDR 0xfffff438 /* Port M direction reg */
#define PMDATA_ADDR 0xfffff439 /* Port M data register */
#define PMPUEN_ADDR 0xfffff43a /* Port M Pull-Up enable reg */
#define PMSEL_ADDR 0xfffff43b /* Port M Select Register */
 
#define PMDIR BYTE_REF(PMDIR_ADDR)
#define PMDATA BYTE_REF(PMDATA_ADDR)
#define PMPUEN BYTE_REF(PMPUEN_ADDR)
#define PMSEL BYTE_REF(PMSEL_ADDR)
 
#define PM(x) (1 << (x))
 
/**********
*
* 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
*
**********/
 
/*
* PWM Control Register
*/
#define PWMC_ADDR 0xfffff500
#define PWMC WORD_REF(PWMC_ADDR)
 
#define PWMC_CLKSEL_MASK 0x0007 /* Clock Selection */
#define PWMC_CLKSEL_SHIFT 0
#define PWMC_PWMEN 0x0010 /* Enable PWM */
#define PMNC_POL 0x0020 /* PWM Output Bit Polarity */
#define PWMC_PIN 0x0080 /* Current PWM output pin status */
#define PWMC_LOAD 0x0100 /* Force a new period */
#define PWMC_IRQEN 0x4000 /* Interrupt Request Enable */
#define PWMC_CLKSRC 0x8000 /* Clock Source Select */
 
/* 'EZ328-compatible definitions */
#define PWMC_EN PWMC_PWMEN
 
/*
* PWM Period Register
*/
#define PWMP_ADDR 0xfffff502
#define PWMP WORD_REF(PWMP_ADDR)
 
/*
* PWM Width Register
*/
#define PWMW_ADDR 0xfffff504
#define PWMW WORD_REF(PWMW_ADDR)
 
/*
* PWM Counter Register
*/
#define PWMCNT_ADDR 0xfffff506
#define PWMCNT WORD_REF(PWMCNT_ADDR)
 
/**********
*
* 0xFFFFF6xx -- General-Purpose Timers
*
**********/
 
/*
* Timer Unit 1 and 2 Control Registers
*/
#define TCTL1_ADDR 0xfffff600
#define TCTL1 WORD_REF(TCTL1_ADDR)
#define TCTL2_ADDR 0xfffff60c
#define TCTL2 WORD_REF(TCTL2_ADDR)
 
#define TCTL_TEN 0x0001 /* Timer Enable */
#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
#define TCTL_IRQEN 0x0010 /* IRQ Enable */
#define TCTL_OM 0x0020 /* Output Mode */
#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
#define TCTL_FRR 0x0010 /* Free-Run Mode */
 
/* 'EZ328-compatible definitions */
#define TCTL_ADDR TCTL1_ADDR
#define TCTL TCTL1
 
/*
* Timer Unit 1 and 2 Prescaler Registers
*/
#define TPRER1_ADDR 0xfffff602
#define TPRER1 WORD_REF(TPRER1_ADDR)
#define TPRER2_ADDR 0xfffff60e
#define TPRER2 WORD_REF(TPRER2_ADDR)
 
/* 'EZ328-compatible definitions */
#define TPRER_ADDR TPRER1_ADDR
#define TPRER TPRER1
 
/*
* Timer Unit 1 and 2 Compare Registers
*/
#define TCMP1_ADDR 0xfffff604
#define TCMP1 WORD_REF(TCMP1_ADDR)
#define TCMP2_ADDR 0xfffff610
#define TCMP2 WORD_REF(TCMP2_ADDR)
 
/* 'EZ328-compatible definitions */
#define TCMP_ADDR TCMP1_ADDR
#define TCMP TCMP1
 
/*
* Timer Unit 1 and 2 Capture Registers
*/
#define TCR1_ADDR 0xfffff606
#define TCR1 WORD_REF(TCR1_ADDR)
#define TCR2_ADDR 0xfffff612
#define TCR2 WORD_REF(TCR2_ADDR)
 
/* 'EZ328-compatible definitions */
#define TCR_ADDR TCR1_ADDR
#define TCR TCR1
 
/*
* Timer Unit 1 and 2 Counter Registers
*/
#define TCN1_ADDR 0xfffff608
#define TCN1 WORD_REF(TCN1_ADDR)
#define TCN2_ADDR 0xfffff614
#define TCN2 WORD_REF(TCN2_ADDR)
 
/* 'EZ328-compatible definitions */
#define TCN_ADDR TCN1_ADDR
#define TCN TCN
 
/*
* Timer Unit 1 and 2 Status Registers
*/
#define TSTAT1_ADDR 0xfffff60a
#define TSTAT1 WORD_REF(TSTAT1_ADDR)
#define TSTAT2_ADDR 0xfffff616
#define TSTAT2 WORD_REF(TSTAT2_ADDR)
 
#define TSTAT_COMP 0x0001 /* Compare Event occurred */
#define TSTAT_CAPT 0x0001 /* Capture Event occurred */
 
/* 'EZ328-compatible definitions */
#define TSTAT_ADDR TSTAT1_ADDR
#define TSTAT TSTAT1
 
/*
* Watchdog Compare Register
*/
#define WRR_ADDR 0xfffff61a
#define WRR WORD_REF(WRR_ADDR)
 
/*
* Watchdog Counter Register
*/
#define WCN_ADDR 0xfffff61c
#define WCN WORD_REF(WCN_ADDR)
 
/*
* Watchdog Control and Status Register
*/
#define WCSR_ADDR 0xfffff618
#define WCSR WORD_REF(WCSR_ADDR)
 
#define WCSR_WDEN 0x0001 /* Watchdog Enable */
#define WCSR_FI 0x0002 /* Forced Interrupt (instead of SW reset)*/
#define WCSR_WRST 0x0004 /* Watchdog Reset */
 
/**********
*
* 0xFFFFF7xx -- Serial Periferial Interface Slave (SPIS)
*
**********/
 
/*
* SPI Slave Register
*/
#define SPISR_ADDR 0xfffff700
#define SPISR WORD_REF(SPISR_ADDR)
 
#define SPISR_DATA_ADDR 0xfffff701
#define SPISR_DATA BYTE_REF(SPISR_DATA_ADDR)
 
#define SPISR_DATA_MASK 0x00ff /* Shifted data from the external device */
#define SPISR_DATA_SHIFT 0
#define SPISR_SPISEN 0x0100 /* SPIS module enable */
#define SPISR_POL 0x0200 /* SPSCLK polarity control */
#define SPISR_PHA 0x0400 /* Phase relationship between SPSCLK & SPSRxD */
#define SPISR_OVWR 0x0800 /* Data buffer has been overwritten */
#define SPISR_DATARDY 0x1000 /* Data ready */
#define SPISR_ENPOL 0x2000 /* Enable Polarity */
#define SPISR_IRQEN 0x4000 /* SPIS IRQ Enable */
#define SPISR_SPISIRQ 0x8000 /* SPIS IRQ posted */
 
/**********
*
* 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
*
**********/
 
/*
* SPIM Data Register
*/
#define SPIMDATA_ADDR 0xfffff800
#define SPIMDATA WORD_REF(SPIMDATA_ADDR)
 
/*
* SPIM Control/Status Register
*/
#define SPIMCONT_ADDR 0xfffff802
#define SPIMCONT WORD_REF(SPIMCONT_ADDR)
 
#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
#define SPIMCONT_BIT_COUNT_SHIFT 0
#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
#define SPIMCONT_SPIMIRQ 0x0080 /* Interrupt Request */
#define SPIMCONT_XCH 0x0100 /* Exchange */
#define SPIMCONT_RSPIMEN 0x0200 /* Enable SPIM */
#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
#define SPIMCONT_DATA_RATE_SHIFT 13
 
/* 'EZ328-compatible definitions */
#define SPIMCONT_IRQ SPIMCONT_SPIMIRQ
#define SPIMCONT_ENABLE SPIMCONT_SPIMEN
/**********
*
* 0xFFFFF9xx -- UART
*
**********/
 
/*
* UART Status/Control Register
*/
#define USTCNT_ADDR 0xfffff900
#define USTCNT WORD_REF(USTCNT_ADDR)
 
#define USTCNT_TXAVAILEN 0x0001 /* Transmitter Available Int Enable */
#define USTCNT_TXHALFEN 0x0002 /* Transmitter Half Empty Int Enable */
#define USTCNT_TXEMPTYEN 0x0004 /* Transmitter Empty Int Enable */
#define USTCNT_RXREADYEN 0x0008 /* Receiver Ready Interrupt Enable */
#define USTCNT_RXHALFEN 0x0010 /* Receiver Half-Full Int Enable */
#define USTCNT_RXFULLEN 0x0020 /* Receiver Full Interrupt Enable */
#define USTCNT_CTSDELTAEN 0x0040 /* CTS Delta Interrupt Enable */
#define USTCNT_GPIODELTAEN 0x0080 /* Old Data Interrupt Enable */
#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
#define USTCNT_STOP 0x0200 /* Stop bit transmission */
#define USTCNT_ODD_EVEN 0x0400 /* Odd Parity */
#define USTCNT_PARITYEN 0x0800 /* Parity Enable */
#define USTCNT_CLKMODE 0x1000 /* Clock Mode Select */
#define USTCNT_TXEN 0x2000 /* Transmitter Enable */
#define USTCNT_RXEN 0x4000 /* Receiver Enable */
#define USTCNT_UARTEN 0x8000 /* UART Enable */
 
/* 'EZ328-compatible definitions */
#define USTCNT_TXAE USTCNT_TXAVAILEN
#define USTCNT_TXHE USTCNT_TXHALFEN
#define USTCNT_TXEE USTCNT_TXEMPTYEN
#define USTCNT_RXRE USTCNT_RXREADYEN
#define USTCNT_RXHE USTCNT_RXHALFEN
#define USTCNT_RXFE USTCNT_RXFULLEN
#define USTCNT_CTSD USTCNT_CTSDELTAEN
#define USTCNT_ODD USTCNT_ODD_EVEN
#define USTCNT_PEN USTCNT_PARITYEN
#define USTCNT_CLKM USTCNT_CLKMODE
#define USTCNT_UEN USTCNT_UARTEN
 
/*
* UART Baud Control Register
*/
#define UBAUD_ADDR 0xfffff902
#define UBAUD WORD_REF(UBAUD_ADDR)
 
#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
#define UBAUD_PRESCALER_SHIFT 0
#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */
#define UBAUD_DIVIDE_SHIFT 8
#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
#define UBAUD_GPIOSRC 0x1000 /* GPIO source */
#define UBAUD_GPIODIR 0x2000 /* GPIO Direction */
#define UBAUD_GPIO 0x4000 /* Current GPIO pin status */
#define UBAUD_GPIODELTA 0x8000 /* GPIO pin value changed */
 
/*
* UART Receiver Register
*/
#define URX_ADDR 0xfffff904
#define URX WORD_REF(URX_ADDR)
 
#define URX_RXDATA_ADDR 0xfffff905
#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
 
#define URX_RXDATA_MASK 0x00ff /* Received data */
#define URX_RXDATA_SHIFT 0
#define URX_PARITY_ERROR 0x0100 /* Parity Error */
#define URX_BREAK 0x0200 /* Break Detected */
#define URX_FRAME_ERROR 0x0400 /* Framing Error */
#define URX_OVRUN 0x0800 /* Serial Overrun */
#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
#define URX_FIFO_FULL 0x8000 /* FIFO is Full */
 
/*
* UART Transmitter Register
*/
#define UTX_ADDR 0xfffff906
#define UTX WORD_REF(UTX_ADDR)
 
#define UTX_TXDATA_ADDR 0xfffff907
#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
 
#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
#define UTX_TXDATA_SHIFT 0
#define UTX_CTS_DELTA 0x0100 /* CTS changed */
#define UTX_CTS_STATUS 0x0200 /* CTS State */
#define UTX_IGNORE_CTS 0x0800 /* Ignore CTS */
#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
 
/* 'EZ328-compatible definitions */
#define UTX_CTS_STAT UTX_CTS_STATUS
#define UTX_NOCTS UTX_IGNORE_CTS
 
/*
* UART Miscellaneous Register
*/
#define UMISC_ADDR 0xfffff908
#define UMISC WORD_REF(UMISC_ADDR)
 
#define UMISC_TX_POL 0x0004 /* Transmit Polarity */
#define UMISC_RX_POL 0x0008 /* Receive Polarity */
#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
#define UMISC_RTS 0x0040 /* Set RTS status */
#define UMISC_RTSCONT 0x0080 /* Choose RTS control */
#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
#define UMISC_CLKSRC 0x4000 /* Clock Source */
 
/**********
*
* 0xFFFFFAxx -- LCD Controller
*
**********/
 
/*
* LCD Screen Starting Address Register
*/
#define LSSA_ADDR 0xfffffa00
#define LSSA LONG_REF(LSSA_ADDR)
 
#define LSSA_SSA_MASK 0xfffffffe /* Bit 0 is reserved */
 
/*
* LCD Virtual Page Width Register
*/
#define LVPW_ADDR 0xfffffa05
#define LVPW BYTE_REF(LVPW_ADDR)
 
/*
* LCD Screen Width Register (not compatible with 'EZ328 !!!)
*/
#define LXMAX_ADDR 0xfffffa08
#define LXMAX WORD_REF(LXMAX_ADDR)
 
#define LXMAX_XM_MASK 0x02ff /* Bits 0-3 are reserved */
 
/*
* LCD Screen Height Register
*/
#define LYMAX_ADDR 0xfffffa0a
#define LYMAX WORD_REF(LYMAX_ADDR)
 
#define LYMAX_YM_MASK 0x02ff /* Bits 10-15 are reserved */
 
/*
* LCD Cursor X Position Register
*/
#define LCXP_ADDR 0xfffffa18
#define LCXP WORD_REF(LCXP_ADDR)
 
#define LCXP_CC_MASK 0xc000 /* Cursor Control */
#define LCXP_CC_TRAMSPARENT 0x0000
#define LCXP_CC_BLACK 0x4000
#define LCXP_CC_REVERSED 0x8000
#define LCXP_CC_WHITE 0xc000
#define LCXP_CXP_MASK 0x02ff /* Cursor X position */
 
/*
* LCD Cursor Y Position Register
*/
#define LCYP_ADDR 0xfffffa1a
#define LCYP WORD_REF(LCYP_ADDR)
 
#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
 
/*
* LCD Cursor Width and Heigth Register
*/
#define LCWCH_ADDR 0xfffffa1c
#define LCWCH WORD_REF(LCWCH_ADDR)
 
#define LCWCH_CH_MASK 0x001f /* Cursor Height */
#define LCWCH_CH_SHIFT 0
#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
#define LCWCH_CW_SHIFT 8
 
/*
* LCD Blink Control Register
*/
#define LBLKC_ADDR 0xfffffa1f
#define LBLKC BYTE_REF(LBLKC_ADDR)
 
#define LBLKC_BD_MASK 0x7f /* Blink Divisor */
#define LBLKC_BD_SHIFT 0
#define LBLKC_BKEN 0x80 /* Blink Enabled */
 
/*
* LCD Panel Interface Configuration Register
*/
#define LPICF_ADDR 0xfffffa20
#define LPICF BYTE_REF(LPICF_ADDR)
 
#define LPICF_GS_MASK 0x01 /* Gray-Scale Mode */
#define LPICF_GS_BW 0x00
#define LPICF_GS_GRAY_4 0x01
#define LPICF_PBSIZ_MASK 0x06 /* Panel Bus Width */
#define LPICF_PBSIZ_1 0x00
#define LPICF_PBSIZ_2 0x02
#define LPICF_PBSIZ_4 0x04
 
/*
* LCD Polarity Configuration Register
*/
#define LPOLCF_ADDR 0xfffffa21
#define LPOLCF BYTE_REF(LPOLCF_ADDR)
 
#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
 
/*
* LACD (LCD Alternate Crystal Direction) Rate Control Register
*/
#define LACDRC_ADDR 0xfffffa23
#define LACDRC BYTE_REF(LACDRC_ADDR)
 
#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
#define LACDRC_ACD_SHIFT 0
 
/*
* LCD Pixel Clock Divider Register
*/
#define LPXCD_ADDR 0xfffffa25
#define LPXCD BYTE_REF(LPXCD_ADDR)
 
#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
#define LPXCD_PCD_SHIFT 0
 
/*
* LCD Clocking Control Register
*/
#define LCKCON_ADDR 0xfffffa27
#define LCKCON BYTE_REF(LCKCON_ADDR)
 
#define LCKCON_PCDS 0x01 /* Pixel Clock Divider Source Select */
#define LCKCON_DWIDTH 0x02 /* Display Memory Width */
#define LCKCON_DWS_MASK 0x3c /* Display Wait-State */
#define LCKCON_DWS_SHIFT 2
#define LCKCON_DMA16 0x40 /* DMA burst length */
#define LCKCON_LCDON 0x80 /* Enable LCD Controller */
 
/* 'EZ328-compatible definitions */
#define LCKCON_DW_MASK LCKCON_DWS_MASK
#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
 
/*
* LCD Last Buffer Address Register
*/
#define LLBAR_ADDR 0xfffffa29
#define LLBAR BYTE_REF(LLBAR_ADDR)
 
#define LLBAR_LBAR_MASK 0x7f /* Number of memory words to fill 1 line */
#define LLBAR_LBAR_SHIFT 0
 
/*
* LCD Octet Terminal Count Register
*/
#define LOTCR_ADDR 0xfffffa2b
#define LOTCR BYTE_REF(LOTCR_ADDR)
 
/*
* LCD Panning Offset Register
*/
#define LPOSR_ADDR 0xfffffa2d
#define LPOSR BYTE_REF(LPOSR_ADDR)
 
#define LPOSR_BOS 0x08 /* Byte offset (for B/W mode only */
#define LPOSR_POS_MASK 0x07 /* Pixel Offset Code */
#define LPOSR_POS_SHIFT 0
 
/*
* LCD Frame Rate Control Modulation Register
*/
#define LFRCM_ADDR 0xfffffa31
#define LFRCM BYTE_REF(LFRCM_ADDR)
 
#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
#define LFRCM_YMOD_SHIFT 0
#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
#define LFRCM_XMOD_SHIFT 4
 
/*
* LCD Gray Palette Mapping Register
*/
#define LGPMR_ADDR 0xfffffa32
#define LGPMR WORD_REF(LGPMR_ADDR)
 
#define LGPMR_GLEVEL3_MASK 0x000f
#define LGPMR_GLEVEL3_SHIFT 0
#define LGPMR_GLEVEL2_MASK 0x00f0
#define LGPMR_GLEVEL2_SHIFT 4
#define LGPMR_GLEVEL0_MASK 0x0f00
#define LGPMR_GLEVEL0_SHIFT 8
#define LGPMR_GLEVEL1_MASK 0xf000
#define LGPMR_GLEVEL1_SHIFT 12
 
/**********
*
* 0xFFFFFBxx -- Real-Time Clock (RTC)
*
**********/
 
/*
* RTC Hours Minutes and Seconds Register
*/
#define RTCTIME_ADDR 0xfffffb00
#define RTCTIME LONG_REF(RTCTIME_ADDR)
 
#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
#define RTCTIME_SECONDS_SHIFT 0
#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
#define RTCTIME_MINUTES_SHIFT 16
#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
#define RTCTIME_HOURS_SHIFT 24
 
/*
* RTC Alarm Register
*/
#define RTCALRM_ADDR 0xfffffb04
#define RTCALRM LONG_REF(RTCALRM_ADDR)
 
#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
#define RTCALRM_SECONDS_SHIFT 0
#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
#define RTCALRM_MINUTES_SHIFT 16
#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
#define RTCALRM_HOURS_SHIFT 24
 
/*
* RTC Control Register
*/
#define RTCCTL_ADDR 0xfffffb0c
#define RTCCTL WORD_REF(RTCCTL_ADDR)
 
#define RTCCTL_384 0x0020 /* Crystal Selection */
#define RTCCTL_ENABLE 0x0080 /* RTC Enable */
 
/* 'EZ328-compatible definitions */
#define RTCCTL_XTL RTCCTL_384
#define RTCCTL_EN RTCCTL_ENABLE
 
/*
* RTC Interrupt Status Register
*/
#define RTCISR_ADDR 0xfffffb0e
#define RTCISR WORD_REF(RTCISR_ADDR)
 
#define RTCISR_SW 0x0001 /* Stopwatch timed out */
#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occured */
#define RTCISR_ALM 0x0004 /* Alarm interrupt has occured */
#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occured */
#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occured */
 
/*
* RTC Interrupt Enable Register
*/
#define RTCIENR_ADDR 0xfffffb10
#define RTCIENR WORD_REF(RTCIENR_ADDR)
 
#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
 
/*
* Stopwatch Minutes Register
*/
#define STPWCH_ADDR 0xfffffb12
#define STPWCH WORD_REF(STPWCH)
 
#define STPWCH_CNT_MASK 0x00ff /* Stopwatch countdown value */
#define SPTWCH_CNT_SHIFT 0
 
#endif /* _MC68328_H_ */
/stat.h
0,0 → 1,41
#ifndef _M68K_STAT_H
#define _M68K_STAT_H
 
struct old_stat {
unsigned short st_dev;
unsigned short st_ino;
unsigned short st_mode;
unsigned short st_nlink;
unsigned short st_uid;
unsigned short st_gid;
unsigned short st_rdev;
unsigned long st_size;
unsigned long st_atime;
unsigned long st_mtime;
unsigned long st_ctime;
};
 
struct new_stat {
unsigned short st_dev;
unsigned short __pad1;
unsigned long st_ino;
unsigned short st_mode;
unsigned short st_nlink;
unsigned short st_uid;
unsigned short st_gid;
unsigned short st_rdev;
unsigned short __pad2;
unsigned long st_size;
unsigned long st_blksize;
unsigned long st_blocks;
unsigned long st_atime;
unsigned long __unused1;
unsigned long st_mtime;
unsigned long __unused2;
unsigned long st_ctime;
unsigned long __unused3;
unsigned long __unused4;
unsigned long __unused5;
};
 
#endif /* _M68K_STAT_H */
/page.h
0,0 → 1,95
#ifndef _M68K_PAGE_H
#define _M68K_PAGE_H
 
#include <linux/config.h>
#include <asm/shglcore.h>
 
/* PAGE_SHIFT determines the page size */
#define PAGE_SHIFT 12
#define PAGE_SIZE (1UL << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
 
#ifdef __KERNEL__
 
#define STRICT_MM_TYPECHECKS
 
#ifdef STRICT_MM_TYPECHECKS
/*
* These are used to make use of C type-checking..
*/
typedef struct { unsigned long pte; } pte_t;
typedef struct { unsigned long pmd[16]; } pmd_t;
typedef struct { unsigned long pgd; } pgd_t;
typedef struct { unsigned long pgprot; } pgprot_t;
 
#define pte_val(x) ((x).pte)
#define pmd_val(x) ((&x)->pmd[0])
#define pgd_val(x) ((x).pgd)
#define pgprot_val(x) ((x).pgprot)
 
#define __pte(x) ((pte_t) { (x) } )
#define __pmd(x) ((pmd_t) { (x) } )
#define __pgd(x) ((pgd_t) { (x) } )
#define __pgprot(x) ((pgprot_t) { (x) } )
 
#else
/*
* .. while these make it easier on the compiler
*/
typedef unsigned long pte_t;
typedef struct { unsigned long pmd[16]; } pmd_t;
typedef unsigned long pgd_t;
typedef unsigned long pgprot_t;
 
#define pte_val(x) (x)
#define pmd_val(x) ((&x)->pmd[0])
#define pgd_val(x) (x)
#define pgprot_val(x) (x)
 
#define __pte(x) (x)
#define __pmd(x) ((pmd_t) { (x) } )
#define __pgd(x) (x)
#define __pgprot(x) (x)
 
#endif
 
/* to align the pointer to the (next) page boundary */
#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
 
/* This handles the memory map.. */
#ifdef CONFIG_COLDFIRE
#ifdef CONFIG_SMALL
#define PAGE_OFFSET 0x30020000
#else
#define PAGE_OFFSET 0x00000000
#endif
#endif
 
#ifdef CONFIG_PILOT
#ifdef CONFIG_M68328
#define PAGE_OFFSET 0x10000000
#endif
#ifdef CONFIG_M68EZ328
#define PAGE_OFFSET 0x00000000
#endif
#endif
#ifdef CONFIG_UCSIMM
#define PAGE_OFFSET 0x00000000
#endif
#ifdef CONFIG_M68EZ328ADS
#define PAGE_OFFSET 0x00000000
#endif
#ifdef CONFIG_ALMA_ANS
#define PAGE_OFFSET 0x00000000
#endif
#ifdef CONFIG_M68EN302
#define PAGE_OFFSET 0x00000000
#endif
#ifdef CONFIG_SHGLCORE
#define PAGE_OFFSET SHGLCORE_RAM_BANK_0_ADDR
#endif
#define MAP_NR(addr) ((((unsigned long)(addr)) - PAGE_OFFSET) >> PAGE_SHIFT)
 
#endif /* __KERNEL__ */
 
#endif /* _M68K_PAGE_H */
/mcfsim.h
0,0 → 1,89
/****************************************************************************/
 
/*
* mcfsim.h -- ColdFire System Integration Module support.
*
* (C) Copyright 1999, Greg Ungerer (gerg@moreton.com.au)
*/
 
/****************************************************************************/
#ifndef mcfsim_h
#define mcfsim_h
/****************************************************************************/
 
#include <linux/config.h>
 
/*
* Include 5206 or 5307 specific addresses.
*/
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
#include <asm/m5206sim.h>
#elif defined(CONFIG_M5204)
#include <asm/m5204sim.h>
#elif defined(CONFIG_M5307)
#include <asm/m5307sim.h>
#endif
 
 
/*
* Define the base address of the SIM within the MBAR address space.
*/
#define MCFSIM_BASE 0x0 /* Base address of SIM */
 
 
/*
* Bit definitions for the ICR family of registers.
*/
#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
 
#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
 
/*
* Bit definitions for the Interrupt Mask register (IMR).
*/
#define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */
#define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */
#define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */
#define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */
#define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */
#define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */
#define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */
 
#define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */
#define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */
#define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */
#define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */
#define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */
#define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */
 
#if defined(CONFIG_M5206e)
#define MCFSIM_IMR_DMA1 0x4000 /* DMA 1 intr */
#define MCFSIM_IMR_DMA2 0x8000 /* DMA 2 intr */
#elif defined(CONFIG_M5307)
#define MCFSIM_IMR_DMA0 0x4000 /* DMA 0 intr */
#define MCFSIM_IMR_DMA1 0x8000 /* DMA 1 intr */
#define MCFSIM_IMR_DMA2 0x10000 /* DMA 2 intr */
#define MCFSIM_IMR_DMA3 0x20000 /* DMA 3 intr */
#endif
 
#if defined(CONFIG_M5307)
#define MCFSIM_IMR_MASKALL 0x3fffe /* All intr sources */
#elif defined(CONFIG_M5206e)
#define MCFSIM_IMR_MASKALL 0xfffe /* All intr sources */
#else
#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */
#endif
 
/****************************************************************************/
#endif /* mcfsim_h */
/processor.h
0,0 → 1,120
/*
* include/asm-m68k/processor.h
*
* Copyright (C) 1995 Hamish Macdonald
*/
 
#ifndef __ASM_M68K_PROCESSOR_H
#define __ASM_M68K_PROCESSOR_H
 
#include <linux/config.h>
#include <asm/segment.h>
 
/*
* User space process size: 3.75GB. This is hardcoded into a few places,
* so don't change it unless you know what you are doing.
*/
/*#define TASK_SIZE (0xF0000000UL)*/
 
/*
* Bus types
*/
#define EISA_bus__is_a_macro 1
#define EISA_bus 0
#define MCA_bus__is_a_macro 1
#define MCA_bus 0
 
/*
* The m68k has no problems with write protection
*/
#define wp_works_ok__is_a_macro 1
#define wp_works_ok 1
 
/* MAX floating point unit state size (FSAVE/FRESTORE) */
#define FPSTATESIZE (216/sizeof(unsigned char))
 
/*
* if you change this structure, you must change the code and offsets
* in m68k/machasm.S
*/
struct thread_struct {
unsigned long ksp; /* kernel stack pointer */
unsigned long usp; /* user stack pointer */
unsigned short sr; /* saved status register */
unsigned short fs; /* saved fs (sfc, dfc) */
unsigned long crp[2]; /* cpu root pointer */
unsigned long esp0; /* points to SR of stack frame */
unsigned long fp[8*3];
unsigned long fpcntl[3]; /* fp control regs */
unsigned char fpstate[FPSTATESIZE]; /* floating point state */
};
 
#define INIT_MMAP { &init_mm, 0, 0x40000000, __pgprot(_PAGE_PRESENT|_PAGE_ACCESSED), VM_READ | VM_WRITE | VM_EXEC }
 
#define INIT_TSS { \
sizeof(init_kernel_stack) + (long) init_kernel_stack, 0, \
PS_S, KERNEL_DS, \
{0, 0}, 0, {0,}, {0, 0, 0}, {0,} \
}
 
#define alloc_kernel_stack() __get_free_page(GFP_KERNEL)
#define free_kernel_stack(page) free_page((page))
 
/*
* Do necessary setup to start up a newly executed thread.
*/
static inline void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long a5,
unsigned long usp)
{
#ifndef NO_MM
unsigned long nilstate = 0;
#endif
 
/* reads from user space */
set_fs(USER_DS);
 
regs->pc = pc;
regs->d5 = a5; /* What, me cheat? */
regs->sr &= ~0x2000;
/*regs->sr |= 0x4000; */ /* Trace on */
wrusp(usp);
}
 
#ifndef CONFIG_COLDFIRE
static inline void tron(void)
{
__asm__ __volatile__ ("
oriw #0x8000, %sr
");
}
 
static inline void troncof(void)
{
__asm__ __volatile__ ("
oriw #0x4000, %sr
");
}
 
static inline void troff(void)
{
__asm__ __volatile__ ("
andiw #0x3fff, %sr
");
}
#endif
 
/*
* Return saved PC of a blocked thread.
*/
extern inline unsigned long thread_saved_pc(struct thread_struct *t)
{
/*extern unsigned long high_memory;*/
unsigned long frame = ((struct switch_stack *)t->ksp)->a6;
/*if (frame > PAGE_SIZE && frame < high_memory)*/
return ((unsigned long *)frame)[1];
/*else
return 0;*/
}
 
#endif
/m5204sim.h
0,0 → 1,115
/****************************************************************************/
 
/*
* m5204sim.h
* from:
* m5206sim.h -- ColdFire 5206 System Integration Module support.
*
* (C) Copyright 1999, Greg Ungerer (gerg@moreton.com.au)
* (C) Copyright 1999, D. Jeff Dionne
*/
 
/****************************************************************************/
#ifndef m5204sim_h
#define m5204sim_h
/****************************************************************************/
 
#include <linux/config.h>
 
/*
* Define the 5206 SIM register set addresses.
*/
#define MCFSIM_SIMR 0x03 /* SIM Config reg (r/w) */
#define MCFSIM_ICR1 0x14 /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x15 /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x16 /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x17 /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ICR5 0x18 /* Intr Ctrl reg 5 (r/w) */
#define MCFSIM_ICR6 0x19 /* Intr Ctrl reg 6 (r/w) */
#define MCFSIM_ICR7 0x1a /* Intr Ctrl reg 7 (r/w) */
#define MCFSIM_ICR8 0x1b /* Intr Ctrl reg 8 (r/w) */
#define MCFSIM_ICR9 0x1c /* Intr Ctrl reg 9 (r/w) */
#define MCFSIM_ICR10 0x1d /* Intr Ctrl reg 10 (r/w) */
#define MCFSIM_ICR11 0x1e /* Intr Ctrl reg 11 (r/w) */
#define MCFSIM_ICR12 0x1f /* Intr Ctrl reg 12 (r/w) */
#define MCFSIM_ICR13 0x20 /* Intr Ctrl reg 13 (r/w) */
#ifdef CONFIG_M5206e
#define MCFSIM_ICR14 0x21 /* Intr Ctrl reg 14 (r/w) */
#define MCFSIM_ICR15 0x22 /* Intr Ctrl reg 15 (r/w) */
#endif
 
#define MCFSIM_IMR 0x36 /* Interrupt Mask reg (r/w) */
#define MCFSIM_IPR 0x3a /* Interrupt Pend reg (r/w) */
 
#define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */
#define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/
 
#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */
#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */
 
#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */
#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */
#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
 
#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */
#define MCFSIM_CSCR0 0x6e /* CS 0 Control reg (r/w) */
#define MCFSIM_CSAR1 0x70 /* CS 1 Address reg (r/w) */
#define MCFSIM_CSMR1 0x74 /* CS 1 Mask reg (r/w) */
#define MCFSIM_CSCR1 0x7a /* CS 1 Control reg (r/w) */
#define MCFSIM_CSAR2 0x7c /* CS 2 Address reg (r/w) */
#define MCFSIM_CSMR2 0x80 /* CS 2 Mask reg (r/w) */
#define MCFSIM_CSCR2 0x86 /* CS 2 Control reg (r/w) */
#define MCFSIM_CSAR3 0x88 /* CS 3 Address reg (r/w) */
#define MCFSIM_CSMR3 0x8c /* CS 3 Mask reg (r/w) */
#define MCFSIM_CSCR3 0x92 /* CS 3 Control reg (r/w) */
#define MCFSIM_CSAR4 0x94 /* CS 4 Address reg (r/w) */
#define MCFSIM_CSMR4 0x98 /* CS 4 Mask reg (r/w) */
#define MCFSIM_CSCR4 0x9e /* CS 4 Control reg (r/w) */
#define MCFSIM_CSAR5 0xa0 /* CS 5 Address reg (r/w) */
#define MCFSIM_CSMR5 0xa4 /* CS 5 Mask reg (r/w) */
#define MCFSIM_CSCR5 0xaa /* CS 5 Control reg (r/w) */
#define MCFSIM_CSAR6 0xac /* CS 6 Address reg (r/w) */
#define MCFSIM_CSMR6 0xb0 /* CS 6 Mask reg (r/w) */
#define MCFSIM_CSCR6 0xb6 /* CS 6 Control reg (r/w) */
#define MCFSIM_CSAR7 0xb8 /* CS 7 Address reg (r/w) */
#define MCFSIM_CSMR7 0xbc /* CS 7 Mask reg (r/w) */
#define MCFSIM_CSCR7 0xc2 /* CS 7 Control reg (r/w) */
#define MCFSIM_DMCR 0xc6 /* Default control */
 
#ifdef CONFIG_M5206e
#define MCFSIM_PAR 0xca /* Pin Assignment reg (r/w) */
#else
#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */
#endif
 
/*
* Some symbol defines for the above...
*/
#define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */
#define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */
#define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */
#define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */
#define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */
#ifdef CONFIG_M5206e
#define MCFSIM_DMA1ICR MCFSIM_ICR14 /* DMA 1 ICR */
#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
#endif
 
/*
* Macro to get and set IMR register. It is 16 bits on the 5206.
*/
#define mcf_getimr() \
*((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR))
 
#define mcf_setimr(imr) \
*((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR)) = (imr)
 
 
/****************************************************************************/
#endif /* m5204sim_h */
/semaphore.h
0,0 → 1,113
#ifndef _M68K_SEMAPHORE_H
#define _M68K_SEMAPHORE_H
 
#include <linux/linkage.h>
 
/*
* SMP- and interrupt-safe semaphores..
*
* (C) Copyright 1996 Linus Torvalds
*
* m68k version by Andreas Schwab
*/
 
struct semaphore {
int count;
int waking;
int lock; /* to make waking testing atomic */
struct wait_queue * wait;
};
 
#define MUTEX ((struct semaphore) { 1, 0, 0, NULL })
#define MUTEX_LOCKED ((struct semaphore) { 0, 0, 0, NULL })
 
asmlinkage void __down_failed(void /* special register calling convention */);
asmlinkage int __down_failed_interruptible(void); /* params in registers */
asmlinkage void __up_wakeup(void /* special register calling convention */);
 
extern void __down(struct semaphore * sem);
extern void __up(struct semaphore * sem);
 
/*
* This is ugly, but we want the default case to fall through.
* "down_failed" is a special asm handler that calls the C
* routine that actually waits. See arch/m68k/lib/semaphore.S
*/
extern inline void down(struct semaphore * sem)
{
register struct semaphore *sem1 __asm__ ("%a1") = sem;
__asm__ __volatile__(
"| atomic down operation\n\t"
"lea %%pc@(1f),%%a0\n\t"
"subql #1,%0@\n\t"
"jmi " SYMBOL_NAME_STR(__down_failed) "\n"
"1:"
: /* no outputs */
: "a" (sem1)
: "%a0", "memory");
}
 
 
/*
* This version waits in interruptible state so that the waiting
* process can be killed. The down_failed_interruptible routine
* returns negative for signalled and zero for semaphore acquired.
*/
extern inline int down_interruptible(struct semaphore * sem)
{
register int ret __asm__ ("%d0");
register struct semaphore *sem1 __asm__ ("%a1") = sem;
__asm__ __volatile__(
"| atomic down operation\n\t"
"lea %%pc@(1f),%%a0\n\t"
"subql #1,%1@\n\t"
"jmi " SYMBOL_NAME_STR(__down_failed_interruptible) "\n"
"clrl %0\n"
"1:"
: "=d" (ret)
: "a" (sem1)
: "%a0", "memory");
return(ret);
}
 
 
/*
* Primitives to spin on a lock. Needed only for SMP version ... so
* somebody should start playing with one of those Sony NeWS stations.
*/
extern inline void get_buzz_lock(int *lock_ptr)
{
#ifdef __SMP__
while (xchg(lock_ptr,1) != 0) ;
#endif
}
 
extern inline void give_buzz_lock(int *lock_ptr)
{
#ifdef __SMP__
*lock_ptr = 0 ;
#endif
}
 
 
/*
* Note! This is subtle. We jump to wake people up only if
* the semaphore was negative (== somebody was waiting on it).
* The default case (no contention) will result in NO
* jumps for both down() and up().
*/
extern inline void up(struct semaphore * sem)
{
register struct semaphore *sem1 __asm__ ("%a1") = sem;
__asm__ __volatile__(
"| atomic up operation\n\t"
"lea %%pc@(1f),%%a0\n\t"
"addql #1,%0@\n\t"
"jle " SYMBOL_NAME_STR(__up_wakeup) "\n"
"1:"
: /* no outputs */
: "a" (sem1)
: "%a0", "memory");
}
 
#endif
/system.h
0,0 → 1,253
#ifndef _M68K_SYSTEM_H
#define _M68K_SYSTEM_H
 
#include <linux/config.h> /* get configuration macros */
#include <linux/linkage.h>
#include <asm/segment.h>
 
#ifdef CONFIG_M68328
#include <asm/MC68328.h>
#endif
 
#ifdef CONFIG_M68EZ328
#include <asm/MC68EZ328.h>
#endif
 
extern inline unsigned long rdusp(void) {
#ifdef CONFIG_COLDFIRE
extern unsigned int sw_usp;
return(sw_usp);
#else
unsigned long usp;
__asm__ __volatile__("move %/usp,%0"
: "=a" (usp));
return usp;
#endif
}
 
extern inline void wrusp(unsigned long usp) {
#ifdef CONFIG_COLDFIRE
extern unsigned int sw_usp;
sw_usp = usp;
#else
__asm__ __volatile__("move %0,%/usp"
:
: "a" (usp));
#endif
}
 
extern inline unsigned long rda5(void) {
unsigned long a5;
 
__asm__ __volatile__("movel %/a5,%0"
: "=a" (a5));
return a5;
}
 
extern inline void wra5(unsigned long a5) {
__asm__ __volatile__("movel %0,%/a5"
:
: "a" (a5));
}
 
/*
* switch_to(n) should switch tasks to task ptr, first checking that
* ptr isn't the current task, in which case it does nothing. This
* also clears the TS-flag if the task we switched to has used the
* math co-processor latest.
*/
/*
* switch_to() saves the extra registers, that are not saved
* automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
* a0-a1. Some of these are used by schedule() and its predecessors
* and so we might get see unexpected behaviors when a task returns
* with unexpected register values.
*
* syscall stores these registers itself and none of them are used
* by syscall after the function in the syscall has been called.
*
* Beware that resume now expects *next to be in d1 and the offset of
* tss to be in a1. This saves a few instructions as we no longer have
* to push them onto the stack and read them back right after.
*
* 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
*
* Changed 96/09/19 by Andreas Schwab
* pass prev in a0, next in a1, offset of tss in d1, and whether
* the mm structures are shared in d2 (to avoid atc flushing).
*/
asmlinkage void resume(void);
#define switch_to(prev,next) { \
register void *_prev __asm__ ("a0") = (prev); \
register void *_next __asm__ ("a1") = (next); \
register int _tssoff __asm__ ("d1") = (int)&((struct task_struct *)0)->tss; \
register char _shared __asm__ ("d2") = ((prev)->mm == (next)->mm); \
__asm__ __volatile__("jbsr " SYMBOL_NAME_STR(resume) "\n\t" \
: : "a" (_prev), "a" (_next), "d" (_tssoff), \
"d" (_shared) \
: "d0", "d1", "d2", "d3", "d4", "d5", "a0", "a1"); \
}
 
#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
#define tas(ptr) (xchg((ptr),1))
 
struct __xchg_dummy { unsigned long a[100]; };
#define __xg(x) ((volatile struct __xchg_dummy *)(x))
 
#ifdef CONFIG_COLDFIRE
#define sti() __asm__ __volatile__ ( \
"move %/sr,%%d0\n\t" \
"andi.l #0xf8ff,%%d0\n\t" \
"move %%d0,%/sr\n" \
: /* no outputs */ \
: \
: "%d0", "memory")
#define cli() __asm__ __volatile__ ( \
"move %/sr,%%d0\n\t" \
"ori.l #0x0700,%%d0\n\t" \
"move %%d0,%/sr\n" \
: /* no inputs */ \
: \
: "%d0", "memory")
#else
#if defined(CONFIG_ATARI) && !defined(CONFIG_AMIGA) && !defined(CONFIG_MAC)
/* block out HSYNC on the atari */
#define sti() __asm__ __volatile__ ("andiw #0xfbff,%/sr": : : "memory")
#else /* portable version */
#define sti() __asm__ __volatile__ ("andiw #0xf8ff,%/sr": : : "memory")
#endif /* machine compilation types */
#define cli() __asm__ __volatile__ ("oriw #0x0700,%/sr": : : "memory")
#endif
 
#define nop() __asm__ __volatile__ ("nop"::)
#define mb() __asm__ __volatile__ ("" : : :"memory")
 
#define save_flags(x) \
__asm__ __volatile__("movew %/sr,%0":"=d" (x) : /* no input */ :"memory")
 
#define restore_flags(x) \
__asm__ __volatile__("movew %0,%/sr": /* no outputs */ :"d" (x) : "memory")
 
#define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc")
 
#ifndef CONFIG_RMW_INSNS
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
{
unsigned long tmp, flags;
 
save_flags(flags);
cli();
 
switch (size) {
case 1:
__asm__ __volatile__
("moveb %2,%0\n\t"
"moveb %1,%2"
: "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
break;
case 2:
__asm__ __volatile__
("movew %2,%0\n\t"
"movew %1,%2"
: "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
break;
case 4:
__asm__ __volatile__
("movel %2,%0\n\t"
"movel %1,%2"
: "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
break;
}
restore_flags(flags);
return tmp;
}
#else
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
{
switch (size) {
case 1:
__asm__ __volatile__
("moveb %2,%0\n\t"
"1:\n\t"
"casb %0,%1,%2\n\t"
"jne 1b"
: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
break;
case 2:
__asm__ __volatile__
("movew %2,%0\n\t"
"1:\n\t"
"casw %0,%1,%2\n\t"
"jne 1b"
: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
break;
case 4:
__asm__ __volatile__
("movel %2,%0\n\t"
"1:\n\t"
"casl %0,%1,%2\n\t"
"jne 1b"
: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
break;
}
return x;
}
#endif
 
#ifdef CONFIG_M68332
#define HARD_RESET_NOW() ({ \
cli(); \
asm(" \
movew #0x0000, 0xfffa6a; \
reset; \
/*movew #0x1557, 0xfffa44;*/ \
/*movew #0x0155, 0xfffa46;*/ \
moveal #0, %a0; \
movec %a0, %vbr; \
moveal 0, %sp; \
moveal 4, %a0; \
jmp (%a0); \
"); \
})
#endif
 
#if defined( CONFIG_M68328 ) || defined( CONFIG_M68EZ328 )
#define HARD_RESET_NOW() ({ \
cli(); \
asm(" \
moveal #0x10c00000, %a0; \
moveb #0, 0xFFFFF300; \
moveal 0(%a0), %sp; \
moveal 4(%a0), %a0; \
jmp (%a0); \
"); \
})
#endif
 
#ifdef CONFIG_COLDFIRE
#if defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || defined(CONFIG_MATtel)
#define HARD_RESET_NOW() ({ \
asm(" \
movew #0x2700, %sr; \
moveal #0x10000044, %a0; \
movel #0xffffffff, (%a0); \
moveal #0x10000001, %a0; \
moveb #0x00, (%a0); \
moveal #0xf0000004, %a0; \
moveal (%a0), %a0; \
jmp (%a0); \
"); \
})
#else
#define HARD_RESET_NOW() ({ \
asm(" \
movew #0x2700, %sr; \
moveal #0x4, %a0; \
moveal (%a0), %a0; \
jmp (%a0); \
"); \
})
#endif
#endif
 
#endif /* _M68K_SYSTEM_H */
/resource.h
0,0 → 1,39
#ifndef _M68K_RESOURCE_H
#define _M68K_RESOURCE_H
 
/*
* Resource limits
*/
 
#define RLIMIT_CPU 0 /* CPU time in ms */
#define RLIMIT_FSIZE 1 /* Maximum filesize */
#define RLIMIT_DATA 2 /* max data size */
#define RLIMIT_STACK 3 /* max stack size */
#define RLIMIT_CORE 4 /* max core file size */
#define RLIMIT_RSS 5 /* max resident set size */
#define RLIMIT_NPROC 6 /* max number of processes */
#define RLIMIT_NOFILE 7 /* max number of open files */
#define RLIMIT_MEMLOCK 8 /* max locked-in-memory address space*/
#define RLIMIT_AS 9 /* address space limit */
 
#define RLIM_NLIMITS 10
 
#ifdef __KERNEL__
 
#define INIT_RLIMITS \
{ \
{LONG_MAX, LONG_MAX}, \
{LONG_MAX, LONG_MAX}, \
{LONG_MAX, LONG_MAX}, \
{_STK_LIM, _STK_LIM}, \
{ 0, LONG_MAX}, \
{LONG_MAX, LONG_MAX}, \
{MAX_TASKS_PER_USER, MAX_TASKS_PER_USER}, \
{NR_OPEN, NR_OPEN}, \
{LONG_MAX, LONG_MAX}, \
{LONG_MAX, LONG_MAX} \
}
 
#endif /* __KERNEL__ */
 
#endif /* _M68K_RESOURCE_H */
/shm.h
0,0 → 1,24
#ifndef _M68K_SHM_H
#define _M68K_SHM_H
 
/* format of page table entries that correspond to shared memory pages
currently out in swap space (see also mm/swap.c):
bits 0-1 (PAGE_PRESENT) is = 0
bits 8..2 (SWP_TYPE) are = SHM_SWP_TYPE
bits 31..9 are used like this:
bits 15..9 (SHM_ID) the id of the shared memory segment
bits 30..16 (SHM_IDX) the index of the page within the shared memory segment
(actually only bits 25..16 get used since SHMMAX is so low)
bit 31 (SHM_READ_ONLY) flag whether the page belongs to a read-only attach
*/
/* on the m68k both bits 0 and 1 must be zero */
 
#define SHM_ID_SHIFT 9
#define _SHM_ID_BITS 7
#define SHM_ID_MASK ((1<<_SHM_ID_BITS)-1)
 
#define SHM_IDX_SHIFT (SHM_ID_SHIFT+_SHM_ID_BITS)
#define _SHM_IDX_BITS 15
#define SHM_IDX_MASK ((1<<_SHM_IDX_BITS)-1)
 
#endif /* _M68K_SHM_H */
/unistd.h
0,0 → 1,345
#ifndef _ASM_M68K_UNISTD_H_
#define _ASM_M68K_UNISTD_H_
 
/*
* This file contains the system call numbers.
*/
 
#define __NR_setup 0 /* used only by init, to get system going */
#define __NR_exit 1
#define __NR_fork 2
#define __NR_read 3
#define __NR_write 4
#define __NR_open 5
#define __NR_close 6
#define __NR_waitpid 7
#define __NR_creat 8
#define __NR_link 9
#define __NR_unlink 10
#define __NR_execve 11
#define __NR_chdir 12
#define __NR_time 13
#define __NR_mknod 14
#define __NR_chmod 15
#define __NR_chown 16
#define __NR_break 17
#define __NR_oldstat 18
#define __NR_lseek 19
#define __NR_getpid 20
#define __NR_mount 21
#define __NR_umount 22
#define __NR_setuid 23
#define __NR_getuid 24
#define __NR_stime 25
#define __NR_ptrace 26
#define __NR_alarm 27
#define __NR_oldfstat 28
#define __NR_pause 29
#define __NR_utime 30
#define __NR_stty 31
#define __NR_gtty 32
#define __NR_access 33
#define __NR_nice 34
#define __NR_ftime 35
#define __NR_sync 36
#define __NR_kill 37
#define __NR_rename 38
#define __NR_mkdir 39
#define __NR_rmdir 40
#define __NR_dup 41
#define __NR_pipe 42
#define __NR_times 43
#define __NR_prof 44
#define __NR_brk 45
#define __NR_setgid 46
#define __NR_getgid 47
#define __NR_signal 48
#define __NR_geteuid 49
#define __NR_getegid 50
#define __NR_acct 51
#define __NR_phys 52
#define __NR_lock 53
#define __NR_ioctl 54
#define __NR_fcntl 55
#define __NR_mpx 56
#define __NR_setpgid 57
#define __NR_ulimit 58
#define __NR_oldolduname 59
#define __NR_umask 60
#define __NR_chroot 61
#define __NR_ustat 62
#define __NR_dup2 63
#define __NR_getppid 64
#define __NR_getpgrp 65
#define __NR_setsid 66
#define __NR_sigaction 67
#define __NR_sgetmask 68
#define __NR_ssetmask 69
#define __NR_setreuid 70
#define __NR_setregid 71
#define __NR_sigsuspend 72
#define __NR_sigpending 73
#define __NR_sethostname 74
#define __NR_setrlimit 75
#define __NR_getrlimit 76
#define __NR_getrusage 77
#define __NR_gettimeofday 78
#define __NR_settimeofday 79
#define __NR_getgroups 80
#define __NR_setgroups 81
#define __NR_select 82
#define __NR_symlink 83
#define __NR_oldlstat 84
#define __NR_readlink 85
#define __NR_uselib 86
#define __NR_swapon 87
#define __NR_reboot 88
#define __NR_readdir 89
#define __NR_mmap 90
#define __NR_munmap 91
#define __NR_truncate 92
#define __NR_ftruncate 93
#define __NR_fchmod 94
#define __NR_fchown 95
#define __NR_getpriority 96
#define __NR_setpriority 97
#define __NR_profil 98
#define __NR_statfs 99
#define __NR_fstatfs 100
#define __NR_ioperm 101
#define __NR_socketcall 102
#define __NR_syslog 103
#define __NR_setitimer 104
#define __NR_getitimer 105
#define __NR_stat 106
#define __NR_lstat 107
#define __NR_fstat 108
#define __NR_olduname 109
#define __NR_iopl /* 110 */ not supported
#define __NR_vhangup 111
#define __NR_idle 112
#define __NR_vm86 /* 113 */ not supported
#define __NR_wait4 114
#define __NR_swapoff 115
#define __NR_sysinfo 116
#define __NR_ipc 117
#define __NR_fsync 118
#define __NR_sigreturn 119
#define __NR_clone 120
#define __NR_setdomainname 121
#define __NR_uname 122
#define __NR_cacheflush 123
#define __NR_adjtimex 124
#define __NR_mprotect 125
#define __NR_sigprocmask 126
#define __NR_create_module 127
#define __NR_init_module 128
#define __NR_delete_module 129
#define __NR_get_kernel_syms 130
#define __NR_quotactl 131
#define __NR_getpgid 132
#define __NR_fchdir 133
#define __NR_bdflush 134
#define __NR_sysfs 135
#define __NR_personality 136
#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
#define __NR_setfsuid 138
#define __NR_setfsgid 139
#define __NR__llseek 140
#define __NR_getdents 141
#define __NR__newselect 142
#define __NR_flock 143
#define __NR_msync 144
#define __NR_readv 145
#define __NR_writev 146
#define __NR_getsid 147
#define __NR_fdatasync 148
#define __NR__sysctl 149
#define __NR_mlock 150
#define __NR_munlock 151
#define __NR_mlockall 152
#define __NR_munlockall 153
#define __NR_sched_setparam 154
#define __NR_sched_getparam 155
#define __NR_sched_setscheduler 156
#define __NR_sched_getscheduler 157
#define __NR_sched_yield 158
#define __NR_sched_get_priority_max 159
#define __NR_sched_get_priority_min 160
#define __NR_sched_rr_get_interval 161
#define __NR_nanosleep 162
#define __NR_mremap 163
 
/* user-visible error numbers are in the range -1 - -122: see
<asm-m68k/errno.h> */
 
#define __syscall_return(type, res) \
do { \
if ((unsigned long)(res) >= (unsigned long)(-125)) { \
/* avoid using res which is declared to be in register d0; \
errno might expand to a function call and clobber it. */ \
int __err = -(res); \
errno = __err; \
res = -1; \
} \
return (type) (res); \
} while (0)
 
#define _syscall0(type,name) \
type name(void) \
{ \
register long __res __asm__ ("%d0") = __NR_##name; \
__asm__ __volatile__ ("trap #0" \
: "=g" (__res) \
: "0" (__res) \
: "%d0"); \
__syscall_return(type,__res); \
}
 
#define _syscall1(type,name,atype,a) \
type name(atype a) \
{ \
register long __res __asm__ ("%d0") = __NR_##name; \
register long __a __asm__ ("%d1") = (long)(a); \
__asm__ __volatile__ ("trap #0" \
: "=d" (__res) \
: "0" (__res), "d" (__a) \
: "%d0"); \
__syscall_return(type,__res); \
}
 
#define _syscall2(type,name,atype,a,btype,b) \
type name(atype a,btype b) \
{ \
register long __res __asm__ ("%d0") = __NR_##name; \
register long __a __asm__ ("%d1") = (long)(a); \
register long __b __asm__ ("%d2") = (long)(b); \
__asm__ __volatile__ ("trap #0" \
: "=d" (__res) \
: "0" (__res), "d" (__a), "d" (__b) \
: "%d0"); \
__syscall_return(type,__res); \
}
 
#define _syscall3(type,name,atype,a,btype,b,ctype,c) \
type name(atype a,btype b,ctype c) \
{ \
register long __res __asm__ ("%d0") = __NR_##name; \
register long __a __asm__ ("%d1") = (long)(a); \
register long __b __asm__ ("%d2") = (long)(b); \
register long __c __asm__ ("%d3") = (long)(c); \
__asm__ __volatile__ ("trap #0" \
: "=d" (__res) \
: "0" (__res), "d" (__a), "d" (__b), \
"d" (__c) \
: "%d0"); \
__syscall_return(type,__res); \
}
 
#define _syscall4(type,name,atype,a,btype,b,ctype,c,dtype,d) \
type name (atype a, btype b, ctype c, dtype d) \
{ \
register long __res __asm__ ("%d0") = __NR_##name; \
register long __a __asm__ ("%d1") = (long)(a); \
register long __b __asm__ ("%d2") = (long)(b); \
register long __c __asm__ ("%d3") = (long)(c); \
register long __d __asm__ ("%d4") = (long)(d); \
__asm__ __volatile__ ("trap #0" \
: "=d" (__res) \
: "0" (__res), "d" (__a), "d" (__b), \
"d" (__c), "d" (__d) \
: "%d0"); \
__syscall_return(type,__res); \
}
 
#define _syscall5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \
type name (atype a,btype b,ctype c,dtype d,etype e) \
{ \
register long __res __asm__ ("%d0") = __NR_##name; \
register long __a __asm__ ("%d1") = (long)(a); \
register long __b __asm__ ("%d2") = (long)(b); \
register long __c __asm__ ("%d3") = (long)(c); \
register long __d __asm__ ("%d4") = (long)(d); \
register long __e __asm__ ("%d5") = (long)(e); \
__asm__ __volatile__ ("trap #0" \
: "=d" (__res) \
: "0" (__res), "d" (__a), "d" (__b), \
"d" (__c), "d" (__d), "d" (__e) \
: "%d0"); \
__syscall_return(type,__res); \
}
 
#ifdef __KERNEL_SYSCALLS__
 
/*
* we need this inline - forking from kernel space will result
* in NO COPY ON WRITE (!!!), until an execve is executed. This
* is no problem, but for the stack. This is handled by not letting
* main() use the stack at all after fork(). Thus, no function
* calls - which means inline code for fork too, as otherwise we
* would use the stack upon exit from 'fork()'.
*
* Actually only pause and fork are needed inline, so that there
* won't be any messing with the stack from main(), but we define
* some others too.
*/
#define __NR__exit __NR_exit
static inline _syscall0(int,idle)
static inline _syscall0(int,fork)
static inline _syscall2(int,clone,unsigned long,flags,char *,usp)
static inline _syscall0(int,pause)
static inline _syscall0(int,setup)
static inline _syscall0(int,sync)
static inline _syscall0(pid_t,setsid)
static inline _syscall3(int,write,int,fd,const char *,buf,off_t,count)
static inline _syscall1(int,dup,int,fd)
static inline _syscall3(int,execve,const char *,file,char **,argv,char **,envp)
static inline _syscall3(int,open,const char *,file,int,flag,int,mode)
static inline _syscall1(int,close,int,fd)
static inline _syscall1(int,_exit,int,exitcode)
static inline _syscall3(pid_t,waitpid,pid_t,pid,int *,wait_stat,int,options)
 
/*
* This is the mechanism for creating a new kernel thread.
*
* NOTE! Only a kernel-only process(ie the swapper or direct descendants
* who haven't done an "execve()") should use this: it will work within
* a system call from a "real" process, but the process memory space will
* not be free'd until both the parent and the child have exited.
*/
static inline pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
{
register long retval __asm__ ("d0") = __NR_clone;
register long clone_arg __asm__ ("d1") = flags | CLONE_VM;
unsigned long fs;
 
fs = get_fs();
set_fs (KERNEL_DS);
 
__asm__ __volatile__
("movel %%sp,%%d2\n\t"
"trap #0\n\t" /* Linux/m68k system call */
"cmpl %%sp,%%d2\n\t" /* child or parent */
"jeq 1f\n\t" /* parent - jump */
"movel %3,%%sp@-\n\t" /* push argument */
"jsr %4@\n\t" /* call fn */
"movel %2,%0\n\t" /* exit */
"trap #0\n"
"1:"
: "=d" (retval)
: "0" (__NR_clone), "i" (__NR_exit),
"r" (arg), "a" (fn), "d" (clone_arg)
: "d0", "d2");
 
set_fs (fs);
return retval;
}
 
static inline pid_t wait(int * wait_stat)
{
return waitpid(-1,wait_stat,0);
}
 
#endif
 
#endif /* _ASM_M68K_UNISTD_H_ */
/MC68EZ328.h
0,0 → 1,1227
 
/* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
*
* Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
* Bear & Hare Software, Inc.
*
* Based on include/asm-m68knommu/MC68332.h
* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
* The Silver Hammer Group, Ltd.
*
*/
 
#ifndef _MC68EZ328_H_
#define _MC68EZ328_H_
 
#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
#define WORD_REF(addr) (*((volatile unsigned short*)addr))
#define LONG_REF(addr) (*((volatile unsigned long*)addr))
 
#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
 
/**********
*
* 0xFFFFF0xx -- System Control
*
**********/
/*
* System Control Register (SCR)
*/
#define SCR_ADDR 0xfffff000
#define SCR BYTE_REF(SCR_ADDR)
 
#define SCR_WDTH8 0x01 /* 8-Bit Width Select */
#define SCR_DMAP 0x04 /* Double Map */
#define SCR_SO 0x08 /* Supervisor Only */
#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
#define SCR_PRV 0x20 /* Privilege Violation */
#define SCR_WPV 0x40 /* Write Protect Violation */
#define SCR_BETO 0x80 /* Bus-Error TimeOut */
 
/*
* Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
*/
#define MRR_ADDR 0xfffff004
#define MRR LONG_REF(MRR_ADDR)
 
/**********
*
* 0xFFFFF1xx -- Chip-Select logic
*
**********/
/*
* Chip Select Group Base Registers
*/
#define CSGBA_ADDR 0xfffff100
#define CSGBB_ADDR 0xfffff102
 
#define CSGBC_ADDR 0xfffff104
#define CSGBD_ADDR 0xfffff106
 
#define CSGBA WORD_REF(CSGBA_ADDR)
#define CSGBB WORD_REF(CSGBB_ADDR)
#define CSGBC WORD_REF(CSGBC_ADDR)
#define CSGBD WORD_REF(CSGBD_ADDR)
 
/*
* Chip Select Registers
*/
#define CSA_ADDR 0xfffff110
#define CSB_ADDR 0xfffff112
#define CSC_ADDR 0xfffff114
#define CSD_ADDR 0xfffff116
 
#define CSA WORD_REF(CSA_ADDR)
#define CSB WORD_REF(CSB_ADDR)
#define CSC WORD_REF(CSC_ADDR)
#define CSD WORD_REF(CSD_ADDR)
 
#define CSA_EN 0x0001 /* Chip-Select Enable */
#define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
#define CSA_SIZ_SHIFT 1
#define CSA_WS_MASK 0x0070 /* Wait State */
#define CSA_WS_SHIFT 4
#define CSA_BSW 0x0080 /* Data Bus Width */
#define CSA_FLASH 0x0100 /* FLASH Memory Support */
#define CSA_RO 0x8000 /* Read-Only */
 
#define CSB_EN 0x0001 /* Chip-Select Enable */
#define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
#define CSB_SIZ_SHIFT 1
#define CSB_WS_MASK 0x0070 /* Wait State */
#define CSB_WS_SHIFT 4
#define CSB_BSW 0x0080 /* Data Bus Width */
#define CSB_FLASH 0x0100 /* FLASH Memory Support */
#define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
#define CSB_UPSIZ_SHIFT 11
#define CSB_ROP 0x2000 /* Readonly if protected */
#define CSB_SOP 0x4000 /* Supervisor only if protected */
#define CSB_RO 0x8000 /* Read-Only */
 
#define CSC_EN 0x0001 /* Chip-Select Enable */
#define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
#define CSC_SIZ_SHIFT 1
#define CSC_WS_MASK 0x0070 /* Wait State */
#define CSC_WS_SHIFT 4
#define CSC_BSW 0x0080 /* Data Bus Width */
#define CSC_FLASH 0x0100 /* FLASH Memory Support */
#define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
#define CSC_UPSIZ_SHIFT 11
#define CSC_ROP 0x2000 /* Readonly if protected */
#define CSC_SOP 0x4000 /* Supervisor only if protected */
#define CSC_RO 0x8000 /* Read-Only */
 
#define CSD_EN 0x0001 /* Chip-Select Enable */
#define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
#define CSD_SIZ_SHIFT 1
#define CSD_WS_MASK 0x0070 /* Wait State */
#define CSD_WS_SHIFT 4
#define CSD_BSW 0x0080 /* Data Bus Width */
#define CSD_FLASH 0x0100 /* FLASH Memory Support */
#define CSD_DRAM 0x0200 /* Dram Selection */
#define CSD_COMB 0x0400 /* Combining */
#define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
#define CSD_UPSIZ_SHIFT 11
#define CSD_ROP 0x2000 /* Readonly if protected */
#define CSD_SOP 0x4000 /* Supervisor only if protected */
#define CSD_RO 0x8000 /* Read-Only */
 
/*
* Emulation Chip-Select Register
*/
#define EMUCS_ADDR 0xfffff118
#define EMUCS WORD_REF(EMUCS_ADDR)
 
#define EMUCS_WS_MASK 0x0070
#define EMUCS_WS_SHIFT 4
 
/**********
*
* 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
*
**********/
 
/*
* PLL Control Register
*/
#define PLLCR_ADDR 0xfffff200
#define PLLCR WORD_REF(PLLCR_ADDR)
 
#define PLLCR_DISPLL 0x0008 /* Disable PLL */
#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
#define PLLCR_PRESC 0x0020 /* VCO prescaler */
#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
#define PLLCR_SYSCLK_SEL_SHIFT 8
#define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
#define PLLCR_LCDCLK_SEL_SHIFT 11
 
/* '328-compatible definitions */
#define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK
#define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT
 
/*
* PLL Frequency Select Register
*/
#define PLLFSR_ADDR 0xfffff202
#define PLLFSR WORD_REF(PLLFSR_ADDR)
 
#define PLLFSR_PC_MASK 0x00ff /* P Count */
#define PLLFSR_PC_SHIFT 0
#define PLLFSR_QC_MASK 0x0f00 /* Q Count */
#define PLLFSR_QC_SHIFT 8
#define PLLFSR_PROT 0x4000 /* Protect P & Q */
#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
 
/*
* Power Control Register
*/
#define PCTRL_ADDR 0xfffff207
#define PCTRL BYTE_REF(PCTRL_ADDR)
 
#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
#define PCTRL_WIDTH_SHIFT 0
#define PCTRL_PCEN 0x80 /* Power Control Enable */
 
/**********
*
* 0xFFFFF3xx -- Interrupt Controller
*
**********/
 
/*
* Interrupt Vector Register
*/
#define IVR_ADDR 0xfffff300
#define IVR BYTE_REF(IVR_ADDR)
 
#define IVR_VECTOR_MASK 0xF8
 
/*
* Interrupt control Register
*/
#define ICR_ADDR 0xffff302
#define ICR WORD_REF(ICR_ADDR)
 
#define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */
#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
 
/*
* Interrupt Mask Register
*/
#define IMR_ADDR 0xfffff304
#define IMR LONG_REF(IMR_ADDR)
 
/*
* Define the names for bit positions first. This is useful for
* request_irq
*/
#define SPI_IRQ_NUM 0 /* SPI interrupt */
#define TMR_IRQ_NUM 1 /* Timer interrupt */
#define UART_IRQ_NUM 2 /* UART interrupt */
#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
#define RTC_IRQ_NUM 4 /* RTC interrupt */
#define KB_IRQ_NUM 6 /* Keyboard Interrupt */
#define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */
#define INT0_IRQ_NUM 8 /* External INT0 */
#define INT1_IRQ_NUM 9 /* External INT1 */
#define INT2_IRQ_NUM 10 /* External INT2 */
#define INT3_IRQ_NUM 11 /* External INT3 */
#define IRQ1_IRQ_NUM 16 /* IRQ1 */
#define IRQ2_IRQ_NUM 17 /* IRQ2 */
#define IRQ3_IRQ_NUM 18 /* IRQ3 */
#define IRQ6_IRQ_NUM 19 /* IRQ6 */
#define IRQ5_IRQ_NUM 20 /* IRQ5 */
#define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */
#define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */
 
/* '328-compatible definitions */
#define SPIM_IRQ_NUM SPI_IRQ_NUM
#define TMR1_IRQ_NUM TMR_IRQ_NUM
 
/*
* Here go the bitmasks themselves
*/
#define IMR_MSPI (1 << SPI _IRQ_NUM) /* Mask SPI interrupt */
#define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */
#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
#define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */
#define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */
#define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */
 
/* '328-compatible definitions */
#define IMR_MSPIM IMR_MSPI
#define IMR_MTMR1 IMR_MTMR
 
/*
* Interrupt Status Register
*/
#define ISR_ADDR 0xfffff30c
#define ISR LONG_REF(ISR_ADDR)
 
#define ISR_SPI (1 << SPI _IRQ_NUM) /* SPI interrupt */
#define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
#define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
#define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
#define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
 
/* '328-compatible definitions */
#define ISR_SPIM ISR_SPI
#define ISR_TMR1 ISR_TMR
 
/*
* Interrupt Pending Register
*/
#define IPR_ADDR 0xfffff30c
#define IPR LONG_REF(IPR_ADDR)
 
#define IPR_SPI (1 << SPI _IRQ_NUM) /* SPI interrupt */
#define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
#define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
#define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
#define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
 
/* '328-compatible definitions */
#define IPR_SPIM IPR_SPI
#define IPR_TMR1 IPR_TMR
 
/**********
*
* 0xFFFFF4xx -- Parallel Ports
*
**********/
 
/*
* Port A
*/
#define PADIR_ADDR 0xfffff400 /* Port A direction reg */
#define PADATA_ADDR 0xfffff401 /* Port A data register */
#define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
 
#define PADIR BYTE_REF(PADIR_ADDR)
#define PADATA BYTE_REF(PADATA_ADDR)
#define PAPUEN BYTE_REF(PAPUEN_ADDR)
 
#define PA(x) (1 << (x))
 
/*
* Port B
*/
#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
#define PBDATA_ADDR 0xfffff409 /* Port B data register */
#define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
 
#define PBDIR BYTE_REF(PBDIR_ADDR)
#define PBDATA BYTE_REF(PBDATA_ADDR)
#define PBPUEN BYTE_REF(PBPUEN_ADDR)
#define PBSEL BYTE_REF(PBSEL_ADDR)
 
#define PB(x) (1 << (x))
 
#define PB_CSB0 0x01 /* Use CSB0 as PB[0] */
#define PB_CSB1 0x02 /* Use CSB1 as PB[1] */
#define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */
#define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */
#define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */
#define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */
#define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */
#define PB_PWMO 0x80 /* Use PWMO as PB[7] */
 
/*
* Port C
*/
#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
#define PCDATA_ADDR 0xfffff411 /* Port C data register */
#define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
 
#define PCDIR BYTE_REF(PCDIR_ADDR)
#define PCDATA BYTE_REF(PCDATA_ADDR)
#define PCPDEN BYTE_REF(PCPDEN_ADDR)
#define PCSEL BYTE_REF(PCSEL_ADDR)
 
#define PC(x) (1 << (x))
 
#define PC_LD0 0x01 /* Use LD0 as PC[0] */
#define PC_LD1 0x02 /* Use LD1 as PC[1] */
#define PC_LD2 0x04 /* Use LD2 as PC[2] */
#define PC_LD3 0x08 /* Use LD3 as PC[3] */
#define PC_LFLM 0x10 /* Use LFLM as PC[4] */
#define PC_LLP 0x20 /* Use LLP as PC[5] */
#define PC_LCLK 0x40 /* Use LCLK as PC[6] */
#define PC_LACD 0x80 /* Use LACD as PC[7] */
 
/*
* Port D
*/
#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
#define PDDATA_ADDR 0xfffff419 /* Port D data register */
#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
#define PDSEL_ADDR 0xfffff41b /* Port D Select Register */
#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
#define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */
#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
 
#define PDDIR BYTE_REF(PDDIR_ADDR)
#define PDDATA BYTE_REF(PDDATA_ADDR)
#define PDPUEN BYTE_REF(PDPUEN_ADDR)
#define PDSEL BYTE_REF(PDSEL_ADDR)
#define PDPOL BYTE_REF(PDPOL_ADDR)
#define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
#define PDKBEN BYTE_REF(PDKBEN_ADDR)
#define PDIQEG BYTE_REF(PDIQEG_ADDR)
 
#define PD(x) (1 << (x))
 
#define PD_INT0 0x01 /* Use INT0 as PD[0] */
#define PD_INT1 0x02 /* Use INT1 as PD[1] */
#define PD_INT2 0x04 /* Use INT2 as PD[2] */
#define PD_INT3 0x08 /* Use INT3 as PD[3] */
#define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */
#define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */
#define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */
#define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */
 
/*
* Port E
*/
#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
#define PEDATA_ADDR 0xfffff421 /* Port E data register */
#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
#define PESEL_ADDR 0xfffff423 /* Port E Select Register */
 
#define PEDIR BYTE_REF(PEDIR_ADDR)
#define PEDATA BYTE_REF(PEDATA_ADDR)
#define PEPUEN BYTE_REF(PEPUEN_ADDR)
#define PESEL BYTE_REF(PESEL_ADDR)
 
#define PE(x) (1 << (x))
 
#define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */
#define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */
#define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */
#define PE_DWE 0x08 /* Use DWE as PE[3] */
#define PE_RXD 0x10 /* Use RXD as PE[4] */
#define PE_TXD 0x20 /* Use TXD as PE[5] */
#define PE_RTS 0x40 /* Use RTS as PE[6] */
#define PE_CTS 0x80 /* Use CTS as PE[7] */
 
/*
* Port F
*/
#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
#define PFDATA_ADDR 0xfffff429 /* Port F data register */
#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
 
#define PFDIR BYTE_REF(PFDIR_ADDR)
#define PFDATA BYTE_REF(PFDATA_ADDR)
#define PFPUEN BYTE_REF(PFPUEN_ADDR)
#define PFSEL BYTE_REF(PFSEL_ADDR)
 
#define PF(x) (1 << (x))
 
#define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */
#define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */
#define PF_CLKO 0x04 /* Use CLKO as PF[2] */
#define PF_A20 0x08 /* Use A20 as PF[3] */
#define PF_A21 0x10 /* Use A21 as PF[4] */
#define PF_A22 0x20 /* Use A22 as PF[5] */
#define PF_A23 0x40 /* Use A23 as PF[6] */
#define PF_CSA1 0x80 /* Use CSA1 as PF[7] */
 
/*
* Port G
*/
#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
#define PGDATA_ADDR 0xfffff431 /* Port G data register */
#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
 
#define PGDIR BYTE_REF(PGDIR_ADDR)
#define PGDATA BYTE_REF(PGDATA_ADDR)
#define PGPUEN BYTE_REF(PGPUEN_ADDR)
#define PGSEL BYTE_REF(PGSEL_ADDR)
 
#define PG(x) (1 << (x))
 
#define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */
#define PG_A0 0x02 /* Use A0 as PG[1] */
#define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */
#define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */
#define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */
#define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */
 
/**********
*
* 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
*
**********/
 
/*
* PWM Control Register
*/
#define PWMC_ADDR 0xfffff500
#define PWMC WORD_REF(PWMC_ADDR)
 
#define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
#define PWMC_CLKSEL_SHIFT 0
#define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */
#define PWMC_REPEAT_SHIFT 2
#define PWMC_EN 0x0010 /* Enable PWM */
#define PMNC_FIFOAV 0x0020 /* FIFO Available */
#define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */
#define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */
#define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
#define PWMC_PRESCALER_SHIFT 8
#define PWMC_CLKSRC 0x8000 /* Clock Source Select */
 
/* '328-compatible definitions */
#define PWMC_PWMEN PWMC_EN
 
/*
* PWM Sample Register
*/
#define PWMS_ADDR 0xfffff502
#define PWMS WORD_REF(PWMS_ADDR)
 
/*
* PWM Period Register
*/
#define PWMP_ADDR 0xfffff504
#define PWMP BYTE_REF(PWMP_ADDR)
 
/*
* PWM Counter Register
*/
#define PWMCNT_ADDR 0xfffff505
#define PWMCNT BYTE_REF(PWMCNT_ADDR)
 
/**********
*
* 0xFFFFF6xx -- General-Purpose Timer
*
**********/
 
/*
* Timer Control register
*/
#define TCTL_ADDR 0xfffff600
#define TCTL WORD_REF(TCTL_ADDR)
 
#define TCTL_TEN 0x0001 /* Timer Enable */
#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
#define TCTL_IRQEN 0x0010 /* IRQ Enable */
#define TCTL_OM 0x0020 /* Output Mode */
#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
#define TCTL_FRR 0x0010 /* Free-Run Mode */
 
/* '328-compatible definitions */
#define TCTL1_ADDR TCTL_ADDR
#define TCTL1 TCTL
 
/*
* Timer Prescaler Register
*/
#define TPRER_ADDR 0xfffff602
#define TPRER WORD_REF(TPRER_ADDR)
 
/* '328-compatible definitions */
#define TPRER1_ADDR TPRER_ADDR
#define TPRER1 TPRER
 
/*
* Timer Compare Register
*/
#define TCMP_ADDR 0xfffff604
#define TCMP WORD_REF(TCMP_ADDR)
 
/* '328-compatible definitions */
#define TCMP1_ADDR TCMP_ADDR
#define TCMP1 TCMP
 
/*
* Timer Capture register
*/
#define TCR_ADDR 0xfffff606
#define TCR WORD_REF(TCR_ADDR)
 
/* '328-compatible definitions */
#define TCR1_ADDR TCR_ADDR
#define TCR1 TCR
 
/*
* Timer Counter Register
*/
#define TCN_ADDR 0xfffff608
#define TCN WORD_REF(TCN_ADDR)
 
/* '328-compatible definitions */
#define TCN1_ADDR TCN_ADDR
#define TCN1 TCN
 
/*
* Timer Status Register
*/
#define TSTAT_ADDR 0xfffff60a
#define TSTAT WORD_REF(TSTAT_ADDR)
 
#define TSTAT_COMP 0x0001 /* Compare Event occurred */
#define TSTAT_CAPT 0x0001 /* Capture Event occurred */
 
/* '328-compatible definitions */
#define TSTAT1_ADDR TSTAT_ADDR
#define TSTAT1 TSTAT
 
/**********
*
* 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
*
**********/
 
/*
* SPIM Data Register
*/
#define SPIMDATA_ADDR 0xfffff800
#define SPIMDATA WORD_REF(SPIMDATA_ADDR)
 
/*
* SPIM Control/Status Register
*/
#define SPIMCONT_ADDR 0xfffff802
#define SPIMCONT WORD_REF(SPIMCONT_ADDR)
 
#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
#define SPIMCONT_BIT_COUNT_SHIFT 0
#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
#define SPIMCONT_IRQ 0x0080 /* Interrupt Request */
#define SPIMCONT_XCH 0x0100 /* Exchange */
#define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */
#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
#define SPIMCONT_DATA_RATE_SHIFT 13
 
/* '328-compatible definitions */
#define SPIMCONT_SPIMIRQ SPIMCONT_IRQ
#define SPIMCONT_SPIMEN SPIMCONT_ENABLE
 
/**********
*
* 0xFFFFF9xx -- UART
*
**********/
 
/*
* UART Status/Control Register
*/
#define USTCNT_ADDR 0xfffff900
#define USTCNT WORD_REF(USTCNT_ADDR)
 
#define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */
#define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */
#define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */
#define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */
#define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
#define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */
#define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */
#define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */
#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
#define USTCNT_STOP 0x0200 /* Stop bit transmission */
#define USTCNT_ODD 0x0400 /* Odd Parity */
#define USTCNT_PEN 0x0800 /* Parity Enable */
#define USTCNT_CLKM 0x1000 /* Clock Mode Select */
#define USTCNT_TXEN 0x2000 /* Transmitter Enable */
#define USTCNT_RXEN 0x4000 /* Receiver Enable */
#define USTCNT_UEN 0x8000 /* UART Enable */
 
/* '328-compatible definitions */
#define USTCNT_TXAVAILEN USTCNT_TXAE
#define USTCNT_TXHALFEN USTCNT_TXHE
#define USTCNT_TXEMPTYEN USTCNT_TXEE
#define USTCNT_RXREADYEN USTCNT_RXRE
#define USTCNT_RXHALFEN USTCNT_RXHE
#define USTCNT_RXFULLEN USTCNT_RXFE
#define USTCNT_CTSDELTAEN USTCNT_CTSD
#define USTCNT_ODD_EVEN USTCNT_ODD
#define USTCNT_PARITYEN USTCNT_PEN
#define USTCNT_CLKMODE USTCNT_CLKM
#define USTCNT_UARTEN USTCNT_UEN
 
/*
* UART Baud Control Register
*/
#define UBAUD_ADDR 0xfffff902
#define UBAUD WORD_REF(UBAUD_ADDR)
 
#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
#define UBAUD_PRESCALER_SHIFT 0
#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */
#define UBAUD_DIVIDE_SHIFT 8
#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
 
/*
* UART Receiver Register
*/
#define URX_ADDR 0xfffff904
#define URX WORD_REF(URX_ADDR)
 
#define URX_RXDATA_ADDR 0xfffff905
#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
 
#define URX_RXDATA_MASK 0x00ff /* Received data */
#define URX_RXDATA_SHIFT 0
#define URX_PARITY_ERROR 0x0100 /* Parity Error */
#define URX_BREAK 0x0200 /* Break Detected */
#define URX_FRAME_ERROR 0x0400 /* Framing Error */
#define URX_OVRUN 0x0800 /* Serial Overrun */
#define URX_OLD_DATA 0x1000 /* Old data in FIFO */
#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
#define URX_FIFO_FULL 0x8000 /* FIFO is Full */
 
/*
* UART Transmitter Register
*/
#define UTX_ADDR 0xfffff906
#define UTX WORD_REF(UTX_ADDR)
 
#define UTX_TXDATA_ADDR 0xfffff907
#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
 
#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
#define UTX_TXDATA_SHIFT 0
#define UTX_CTS_DELTA 0x0100 /* CTS changed */
#define UTX_CTS_STAT 0x0200 /* CTS State */
#define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */
#define UTX_NOCTS 0x0800 /* Ignore CTS */
#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
 
/* '328-compatible definitions */
#define UTX_CTS_STATUS UTX_CTS_STAT
#define UTX_IGNORE_CTS UTX_NOCTS
 
/*
* UART Miscellaneous Register
*/
#define UMISC_ADDR 0xfffff908
#define UMISC WORD_REF(UMISC_ADDR)
 
#define UMISC_TX_POL 0x0004 /* Transmit Polarity */
#define UMISC_RX_POL 0x0008 /* Receive Polarity */
#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
#define UMISC_RTS 0x0040 /* Set RTS status */
#define UMISC_RTSCONT 0x0080 /* Choose RTS control */
#define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */
#define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */
#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
#define UMISC_CLKSRC 0x4000 /* Clock Source */
#define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */
 
/*
* UART Non-integer Prescaler Register
*/
#define NIPR_ADDR 0xfffff90a
#define NIPR WORD_REF(NIPR_ADDR)
 
#define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */
#define NIPR_STEP_VALUE_SHIFT 0
#define NIPR_SELECT_MASK 0x0700 /* Tap Selection */
#define NIPR_SELECT_SHIFT 8
#define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
 
/**********
*
* 0xFFFFFAxx -- LCD Controller
*
**********/
 
/*
* LCD Screen Starting Address Register
*/
#define LSSA_ADDR 0xfffffa00
#define LSSA LONG_REF(LSSA_ADDR)
 
#define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
 
/*
* LCD Virtual Page Width Register
*/
#define LVPW_ADDR 0xfffffa05
#define LVPW BYTE_REF(LVPW_ADDR)
 
/*
* LCD Screen Width Register (not compatible with '328 !!!)
*/
#define LXMAX_ADDR 0xfffffa08
#define LXMAX WORD_REF(LXMAX_ADDR)
 
#define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
 
/*
* LCD Screen Height Register
*/
#define LYMAX_ADDR 0xfffffa0a
#define LYMAX WORD_REF(LYMAX_ADDR)
 
#define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
 
/*
* LCD Cursor X Position Register
*/
#define LCXP_ADDR 0xfffffa18
#define LCXP WORD_REF(LCXP_ADDR)
 
#define LCXP_CC_MASK 0xc000 /* Cursor Control */
#define LCXP_CC_TRAMSPARENT 0x0000
#define LCXP_CC_BLACK 0x4000
#define LCXP_CC_REVERSED 0x8000
#define LCXP_CC_WHITE 0xc000
#define LCXP_CXP_MASK 0x02ff /* Cursor X position */
 
/*
* LCD Cursor Y Position Register
*/
#define LCYP_ADDR 0xfffffa1a
#define LCYP WORD_REF(LCYP_ADDR)
 
#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
 
/*
* LCD Cursor Width and Heigth Register
*/
#define LCWCH_ADDR 0xfffffa1c
#define LCWCH WORD_REF(LCWCH_ADDR)
 
#define LCWCH_CH_MASK 0x001f /* Cursor Height */
#define LCWCH_CH_SHIFT 0
#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
#define LCWCH_CW_SHIFT 8
 
/*
* LCD Blink Control Register
*/
#define LBLKC_ADDR 0xfffffa1f
#define LBLKC BYTE_REF(LBLKC_ADDR)
 
#define LBLKC_BD_MASK 0x7f /* Blink Divisor */
#define LBLKC_BD_SHIFT 0
#define LBLKC_BKEN 0x80 /* Blink Enabled */
 
/*
* LCD Panel Interface Configuration Register
*/
#define LPICF_ADDR 0xfffffa20
#define LPICF BYTE_REF(LPICF_ADDR)
 
#define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
#define LPICF_GS_BW 0x00
#define LPICF_GS_GRAY_4 0x01
#define LPICF_GS_GRAY_16 0x02
#define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */
#define LPICF_PBSIZ_1 0x00
#define LPICF_PBSIZ_2 0x04
#define LPICF_PBSIZ_4 0x08
 
/*
* LCD Polarity Configuration Register
*/
#define LPOLCF_ADDR 0xfffffa21
#define LPOLCF BYTE_REF(LPOLCF_ADDR)
 
#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
 
/*
* LACD (LCD Alternate Crystal Direction) Rate Control Register
*/
#define LACDRC_ADDR 0xfffffa23
#define LACDRC BYTE_REF(LACDRC_ADDR)
 
#define LACDRC_ACDSLT 0x80 /* Signal Source Select */
#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
#define LACDRC_ACD_SHIFT 0
 
/*
* LCD Pixel Clock Divider Register
*/
#define LPXCD_ADDR 0xfffffa25
#define LPXCD BYTE_REF(LPXCD_ADDR)
 
#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
#define LPXCD_PCD_SHIFT 0
 
/*
* LCD Clocking Control Register
*/
#define LCKCON_ADDR 0xfffffa27
#define LCKCON BYTE_REF(LCKCON_ADDR)
 
#define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
#define LCKCON_DWS_SHIFT 0
#define LCKCON_DWIDTH 0x40 /* Display Memory Width */
#define LCKCON_LCDON 0x80 /* Enable LCD Controller */
 
/* '328-compatible definitions */
#define LCKCON_DW_MASK LCKCON_DWS_MASK
#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
/*
* LCD Refresh Rate Adjustment Register
*/
#define LRRA_ADDR 0xfffffa29
#define LRRA BYTE_REF(LRRA_ADDR)
 
/*
* LCD Panning Offset Register
*/
#define LPOSR_ADDR 0xfffffa2d
#define LPOSR BYTE_REF(LPOSR_ADDR)
 
#define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */
#define LPOSR_POS_SHIFT 0
 
/*
* LCD Frame Rate Control Modulation Register
*/
#define LFRCM_ADDR 0xfffffa31
#define LFRCM BYTE_REF(LFRCM_ADDR)
 
#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
#define LFRCM_YMOD_SHIFT 0
#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
#define LFRCM_XMOD_SHIFT 4
 
/*
* LCD Gray Palette Mapping Register
*/
#define LGPMR_ADDR 0xfffffa33
#define LGPMR BYTE_REF(LGPMR_ADDR)
 
#define LGPMR_G1_MASK 0x0f
#define LGPMR_G1_SHIFT 0
#define LGPMR_G2_MASK 0xf0
#define LGPMR_G2_SHIFT 4
 
/*
* PWM Contrast Control Register
*/
#define PWMR_ADDR 0xfffffa36
#define PWMR WORD_REF(PWMR_ADDR)
 
#define PWMR_PW_MASK 0x00ff /* Pulse Width */
#define PWMR_PW_SHIFT 0
#define PWMR_CCPEN 0x0100 /* Contrast Control Enable */
#define PWMR_SRC_MASK 0x0600 /* Input Clock Source */
#define PWMR_SRC_LINE 0x0000 /* Line Pulse */
#define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */
#define PWMR_SRC_LCD 0x4000 /* LCD clock */
 
/**********
*
* 0xFFFFFBxx -- Real-Time Clock (RTC)
*
**********/
 
/*
* RTC Hours Minutes and Seconds Register
*/
#define RTCTIME_ADDR 0xfffffb00
#define RTCTIME LONG_REF(RTCTIME_ADDR)
 
#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
#define RTCTIME_SECONDS_SHIFT 0
#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
#define RTCTIME_MINUTES_SHIFT 16
#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
#define RTCTIME_HOURS_SHIFT 24
 
/*
* RTC Alarm Register
*/
#define RTCALRM_ADDR 0xfffffb04
#define RTCALRM LONG_REF(RTCALRM_ADDR)
 
#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
#define RTCALRM_SECONDS_SHIFT 0
#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
#define RTCALRM_MINUTES_SHIFT 16
#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
#define RTCALRM_HOURS_SHIFT 24
 
/*
* Watchdog Timer Register
*/
#define WATCHDOG_ADDR 0xfffffb0a
#define WATCHDOG WORD_REF(WATCHDOR_ADDR)
 
#define WATCHDOG_EN 0x0001 /* Watchdog Enabled */
#define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */
#define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occcured */
#define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */
#define WATCHDOG_CNT_SHIFT 8
 
/*
* RTC Control Register
*/
#define RTCCTL_ADDR 0xfffffb0c
#define RTCCTL WORD_REF(RTCCTL_ADDR)
 
#define RTCCTL_XTL 0x0020 /* Crystal Selection */
#define RTCCTL_EN 0x0080 /* RTC Enable */
 
/* '328-compatible definitions */
#define RTCCTL_384 RTCCTL_XTL
#define RTCCTL_ENABLE RTCCTL_EN
 
/*
* RTC Interrupt Status Register
*/
#define RTCISR_ADDR 0xfffffb0e
#define RTCISR WORD_REF(RTCISR_ADDR)
 
#define RTCISR_SW 0x0001 /* Stopwatch timed out */
#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occured */
#define RTCISR_ALM 0x0004 /* Alarm interrupt has occured */
#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occured */
#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occured */
#define RTCISR_HR 0x0020 /* 1-hour interrupt has occured */
#define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occured */
#define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occured */
#define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occured */
#define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occured */
#define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occured */
#define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occured */
#define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occured */
#define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occured */
 
/*
* RTC Interrupt Enable Register
*/
#define RTCIENR_ADDR 0xfffffb10
#define RTCIENR WORD_REF(RTCIENR_ADDR)
 
#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
#define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
#define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */
#define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */
#define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */
#define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */
#define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */
#define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */
#define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */
#define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */
 
/*
* Stopwatch Minutes Register
*/
#define STPWCH_ADDR 0xfffffb12
#define STPWCH WORD_REF(STPWCH)
 
#define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */
#define SPTWCH_CNT_SHIFT 0
 
/*
* RTC Day Count Register
*/
#define DAYR_ADDR 0xfffffb1a
#define DAYR WORD_REF(DAYR_ADDR)
 
#define DAYR_DAYS_MASK 0x1ff /* Day Setting */
#define DAYR_DAYS_SHIFT 0
 
/*
* RTC Day Alarm Register
*/
#define DAYALARM_ADDR 0xfffffb1c
#define DAYALARM WORD_REF(DAYALARM_ADDR)
 
#define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */
#define DAYALARM_DAYSAL_SHIFT 0
 
/**********
*
* 0xFFFFFCxx -- DRAM Controller
*
**********/
 
/*
* DRAM Memory Configuration Register
*/
#define DRAMMC_ADDR 0xfffffc00
#define DRAMMC WORD_REF(DRAMMC_ADDR)
 
#define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */
#define DRAMMC_ROW12_PA10 0x0000
#define DRAMMC_ROW12_PA21 0x4000
#define DRAMMC_ROW12_PA23 0x8000
#define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */
#define DRAMMC_ROW0_PA11 0x0000
#define DRAMMC_ROW0_PA22 0x1000
#define DRAMMC_ROW0_PA23 0x2000
#define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */
#define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */
#define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */
#define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */
#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */
#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */
#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */
#define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */
#define DRAMMC_REF_SHIFT 0
 
/*
* DRAM Control Register
*/
#define DRAMC_ADDR 0xfffffc02
#define DRAMC WORD_REF(DRAMC_ADDR)
 
#define DRAMC_DWE 0x0001 /* DRAM Write Enable */
#define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */
#define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
#define DRAMC_SLW 0x0008 /* Slow RAM */
#define DRAMC_LSP 0x0010 /* Light Sleep */
#define DRAMC_MSW 0x0020 /* Slow Multiplexing */
#define DRAMC_WS_MASK 0x00c0 /* Wait-states */
#define DRAMC_WS_SHIFT 6
#define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */
#define DRAMC_PGSZ_SHIFT 8
#define DRAMC_PGSZ_256K 0x0000
#define DRAMC_PGSZ_512K 0x0100
#define DRAMC_PGSZ_1024K 0x0200
#define DRAMC_PGSZ_2048K 0x0300
#define DRAMC_EDO 0x0400 /* EDO DRAM */
#define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */
#define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */
#define DRAMC_BC_SHIFT 12
#define DRAMC_RM 0x4000 /* Refresh Mode */
#define DRAMC_EN 0x8000 /* DRAM Controller enable */
 
 
/**********
*
* 0xFFFFFDxx -- In-Circuit Emulation (ICE)
*
**********/
 
/*
* ICE Module Address Compare Register
*/
#define ICEMACR_ADDR 0xfffffd00
#define ICEMACR LONG_REF(ICEMACR_ADDR)
 
/*
* ICE Module Address Mask Register
*/
#define ICEMAMR_ADDR 0xfffffd04
#define ICEMAMR LONG_REF(ICEMAMR_ADDR)
 
/*
* ICE Module Control Compare Register
*/
#define ICEMCCR_ADDR 0xfffffd08
#define ICEMCCR WORD_REF(ICEMCCR_ADDR)
 
#define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */
#define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */
 
/*
* ICE Module Control Mask Register
*/
#define ICEMCMR_ADDR 0xfffffd0a
#define ICEMCMR WORD_REF(ICEMCMR_ADDR)
 
#define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */
#define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */
 
/*
* ICE Module Control Register
*/
#define ICEMCR_ADDR 0xfffffd0c
#define ICEMCR WORD_REF(ICEMCR_ADDR)
 
#define ICEMCR_CEN 0x0001 /* Compare Enable */
#define ICEMCR_PBEN 0x0002 /* Program Break Enable */
#define ICEMCR_SB 0x0004 /* Single Breakpoint */
#define ICEMCR_HMDIS 0x0008 /* HardMap disable */
#define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */
 
/*
* ICE Module Status Register
*/
#define ICEMSR_ADDR 0xfffffd0e
#define ICEMSR WORD_REF(ICEMSR_ADDR)
 
#define ICEMSR_EMUEN 0x0001 /* Emulation Enable */
#define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */
#define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */
#define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */
 
#endif /* _MC68EZ328_H_ */
/sockios.h
0,0 → 1,12
#ifndef __ARCH_M68K_SOCKIOS__
#define __ARCH_M68K_SOCKIOS__
 
/* Socket-level I/O control calls. */
#define FIOSETOWN 0x8901
#define SIOCSPGRP 0x8902
#define FIOGETOWN 0x8903
#define SIOCGPGRP 0x8904
#define SIOCATMARK 0x8905
#define SIOCGSTAMP 0x8906 /* Get stamp */
 
#endif /* __ARCH_M68K_SOCKIOS__ */
/signal.h
0,0 → 1,98
#ifndef _M68K_SIGNAL_H
#define _M68K_SIGNAL_H
 
typedef unsigned long sigset_t; /* at least 32 bits */
 
/* An evil possibility: 31 would let us store a signal_struct within 508 bytes */
#define _NSIG 32
#define NSIG _NSIG
 
#define SIGHUP 1
#define SIGINT 2
#define SIGQUIT 3
#define SIGILL 4
#define SIGTRAP 5
#define SIGABRT 6
#define SIGIOT 6
#define SIGBUS 7
#define SIGFPE 8
#define SIGKILL 9
#define SIGUSR1 10
#define SIGSEGV 11
#define SIGUSR2 12
#define SIGPIPE 13
#define SIGALRM 14
#define SIGTERM 15
#define SIGSTKFLT 16
#define SIGCHLD 17
#define SIGCONT 18
#define SIGSTOP 19
#define SIGTSTP 20
#define SIGTTIN 21
#define SIGTTOU 22
#define SIGURG 23
#define SIGXCPU 24
#define SIGXFSZ 25
#define SIGVTALRM 26
#define SIGPROF 27
#define SIGWINCH 28
#define SIGIO 29
#define SIGPOLL SIGIO
/*
#define SIGLOST 29
*/
#define SIGPWR 30
 
#define SIGUNUSED 31
 
/*
* sa_flags values: SA_STACK is not currently supported, but will allow the
* usage of signal stacks by using the (now obsolete) sa_restorer field in
* the sigaction structure as a stack pointer. This is now possible due to
* the changes in signal handling. LBT 010493.
* SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
* SA_RESTART flag to get restarting signals (which were the default long ago)
* SA_SHIRQ flag is for shared interrupt support on PCI and EISA.
*/
#define SA_NOCLDSTOP 1
#define SA_SHIRQ 0x04000000
#define SA_STACK 0x08000000
#define SA_RESTART 0x10000000
#define SA_INTERRUPT 0x20000000
#define SA_NOMASK 0x40000000
#define SA_ONESHOT 0x80000000
 
#ifdef __KERNEL__
/*
* These values of sa_flags are used only by the kernel as part of the
* irq handling routines.
*
* SA_INTERRUPT is also used by the irq handling routines.
*/
#define SA_PROBE SA_ONESHOT
#define SA_SAMPLE_RANDOM SA_RESTART
#endif
 
#define SIG_BLOCK 0 /* for blocking signals */
#define SIG_UNBLOCK 1 /* for unblocking signals */
#define SIG_SETMASK 2 /* for setting the signal mask */
 
/* Type of a signal handler. */
typedef void (*__sighandler_t)(int);
 
#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
 
struct sigaction {
__sighandler_t sa_handler;
sigset_t sa_mask;
unsigned long sa_flags;
void (*sa_restorer)(void);
};
 
#ifdef __KERNEL__
#include <asm/sigcontext.h>
#endif
 
#endif /* _M68K_SIGNAL_H */
/ptrace.h
0,0 → 1,84
#ifndef _M68K_PTRACE_H
#define _M68K_PTRACE_H
 
#include <linux/config.h> /* get configuration macros */
 
#define PT_D1 0
#define PT_D2 1
#define PT_D3 2
#define PT_D4 3
#define PT_D5 4
#define PT_D6 5
#define PT_D7 6
#define PT_A0 7
#define PT_A1 8
#define PT_A2 9
#define PT_A3 10
#define PT_A4 11
#define PT_A5 12
#define PT_A6 13
#define PT_D0 14
#define PT_USP 15
#define PT_ORIG_D0 16
#define PT_SR 17
#define PT_PC 18
 
#ifndef __ASSEMBLY__
 
/* this struct defines the way the registers are stored on the
stack during a system call. */
 
struct pt_regs {
long d1;
long d2;
long d3;
long d4;
long d5;
long a0;
long a1;
long d0;
long orig_d0;
long stkadj;
#ifdef CONFIG_COLDFIRE
unsigned format : 4; /* frame format specifier */
unsigned vector : 12; /* vector offset */
unsigned short sr;
unsigned long pc;
#else
unsigned short sr;
unsigned long pc;
#ifndef NO_FORMAT_VEC
unsigned format : 4; /* frame format specifier */
unsigned vector : 12; /* vector offset */
#endif
#endif
};
 
/*
* This is the extended stack used by signal handlers and the context
* switcher: it's pushed after the normal "struct pt_regs".
*/
struct switch_stack {
unsigned long d6;
unsigned long d7;
unsigned long a2;
unsigned long a3;
unsigned long a4;
unsigned long a5;
unsigned long a6;
unsigned long retpc;
};
 
#ifdef __KERNEL__
 
#ifndef PS_S
#define PS_S (0x2000)
#define PS_M (0x1000)
#endif
 
#define user_mode(regs) (!((regs)->sr & PS_S))
#define instruction_pointer(regs) ((regs)->pc)
extern void show_regs(struct pt_regs *);
#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
#endif /* _M68K_PTRACE_H */
/errno.h
0,0 → 1,132
#ifndef _M68K_ERRNO_H
#define _M68K_ERRNO_H
 
#define EPERM 1 /* Operation not permitted */
#define ENOENT 2 /* No such file or directory */
#define ESRCH 3 /* No such process */
#define EINTR 4 /* Interrupted system call */
#define EIO 5 /* I/O error */
#define ENXIO 6 /* No such device or address */
#define E2BIG 7 /* Arg list too long */
#define ENOEXEC 8 /* Exec format error */
#define EBADF 9 /* Bad file number */
#define ECHILD 10 /* No child processes */
#define EAGAIN 11 /* Try again */
#define ENOMEM 12 /* Out of memory */
#define EACCES 13 /* Permission denied */
#define EFAULT 14 /* Bad address */
#define ENOTBLK 15 /* Block device required */
#define EBUSY 16 /* Device or resource busy */
#define EEXIST 17 /* File exists */
#define EXDEV 18 /* Cross-device link */
#define ENODEV 19 /* No such device */
#define ENOTDIR 20 /* Not a directory */
#define EISDIR 21 /* Is a directory */
#define EINVAL 22 /* Invalid argument */
#define ENFILE 23 /* File table overflow */
#define EMFILE 24 /* Too many open files */
#define ENOTTY 25 /* Not a typewriter */
#define ETXTBSY 26 /* Text file busy */
#define EFBIG 27 /* File too large */
#define ENOSPC 28 /* No space left on device */
#define ESPIPE 29 /* Illegal seek */
#define EROFS 30 /* Read-only file system */
#define EMLINK 31 /* Too many links */
#define EPIPE 32 /* Broken pipe */
#define EDOM 33 /* Math argument out of domain of func */
#define ERANGE 34 /* Math result not representable */
#define EDEADLK 35 /* Resource deadlock would occur */
#define ENAMETOOLONG 36 /* File name too long */
#define ENOLCK 37 /* No record locks available */
#define ENOSYS 38 /* Function not implemented */
#define ENOTEMPTY 39 /* Directory not empty */
#define ELOOP 40 /* Too many symbolic links encountered */
#define EWOULDBLOCK EAGAIN /* Operation would block */
#define ENOMSG 42 /* No message of desired type */
#define EIDRM 43 /* Identifier removed */
#define ECHRNG 44 /* Channel number out of range */
#define EL2NSYNC 45 /* Level 2 not synchronized */
#define EL3HLT 46 /* Level 3 halted */
#define EL3RST 47 /* Level 3 reset */
#define ELNRNG 48 /* Link number out of range */
#define EUNATCH 49 /* Protocol driver not attached */
#define ENOCSI 50 /* No CSI structure available */
#define EL2HLT 51 /* Level 2 halted */
#define EBADE 52 /* Invalid exchange */
#define EBADR 53 /* Invalid request descriptor */
#define EXFULL 54 /* Exchange full */
#define ENOANO 55 /* No anode */
#define EBADRQC 56 /* Invalid request code */
#define EBADSLT 57 /* Invalid slot */
 
#define EDEADLOCK EDEADLK
 
#define EBFONT 59 /* Bad font file format */
#define ENOSTR 60 /* Device not a stream */
#define ENODATA 61 /* No data available */
#define ETIME 62 /* Timer expired */
#define ENOSR 63 /* Out of streams resources */
#define ENONET 64 /* Machine is not on the network */
#define ENOPKG 65 /* Package not installed */
#define EREMOTE 66 /* Object is remote */
#define ENOLINK 67 /* Link has been severed */
#define EADV 68 /* Advertise error */
#define ESRMNT 69 /* Srmount error */
#define ECOMM 70 /* Communication error on send */
#define EPROTO 71 /* Protocol error */
#define EMULTIHOP 72 /* Multihop attempted */
#define EDOTDOT 73 /* RFS specific error */
#define EBADMSG 74 /* Not a data message */
#define EOVERFLOW 75 /* Value too large for defined data type */
#define ENOTUNIQ 76 /* Name not unique on network */
#define EBADFD 77 /* File descriptor in bad state */
#define EREMCHG 78 /* Remote address changed */
#define ELIBACC 79 /* Can not access a needed shared library */
#define ELIBBAD 80 /* Accessing a corrupted shared library */
#define ELIBSCN 81 /* .lib section in a.out corrupted */
#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
#define ELIBEXEC 83 /* Cannot exec a shared library directly */
#define EILSEQ 84 /* Illegal byte sequence */
#define ERESTART 85 /* Interrupted system call should be restarted */
#define ESTRPIPE 86 /* Streams pipe error */
#define EUSERS 87 /* Too many users */
#define ENOTSOCK 88 /* Socket operation on non-socket */
#define EDESTADDRREQ 89 /* Destination address required */
#define EMSGSIZE 90 /* Message too long */
#define EPROTOTYPE 91 /* Protocol wrong type for socket */
#define ENOPROTOOPT 92 /* Protocol not available */
#define EPROTONOSUPPORT 93 /* Protocol not supported */
#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
#define EPFNOSUPPORT 96 /* Protocol family not supported */
#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
#define EADDRINUSE 98 /* Address already in use */
#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
#define ENETDOWN 100 /* Network is down */
#define ENETUNREACH 101 /* Network is unreachable */
#define ENETRESET 102 /* Network dropped connection because of reset */
#define ECONNABORTED 103 /* Software caused connection abort */
#define ECONNRESET 104 /* Connection reset by peer */
#define ENOBUFS 105 /* No buffer space available */
#define EISCONN 106 /* Transport endpoint is already connected */
#define ENOTCONN 107 /* Transport endpoint is not connected */
#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
#define ETOOMANYREFS 109 /* Too many references: cannot splice */
#define ETIMEDOUT 110 /* Connection timed out */
#define ECONNREFUSED 111 /* Connection refused */
#define EHOSTDOWN 112 /* Host is down */
#define EHOSTUNREACH 113 /* No route to host */
#define EALREADY 114 /* Operation already in progress */
#define EINPROGRESS 115 /* Operation now in progress */
#define ESTALE 116 /* Stale NFS file handle */
#define EUCLEAN 117 /* Structure needs cleaning */
#define ENOTNAM 118 /* Not a XENIX named type file */
#define ENAVAIL 119 /* No XENIX semaphores available */
#define EISNAM 120 /* Is a named type file */
#define EREMOTEIO 121 /* Remote I/O error */
#define EDQUOT 122 /* Quota exceeded */
 
#define ENOMEDIUM 123 /* No medium found */
#define EMEDIUMTYPE 124 /* Wrong medium type */
 
#endif /* _M68K_ERRNO_H */
/posix_types.h
0,0 → 1,50
#ifndef __ARCH_M68K_POSIX_TYPES_H
#define __ARCH_M68K_POSIX_TYPES_H
 
/*
* This file is generally used by user-level software, so you need to
* be a little careful about namespace pollution etc. Also, we cannot
* assume GCC is being used.
*/
 
typedef unsigned short __kernel_dev_t;
typedef unsigned long __kernel_ino_t;
typedef unsigned short __kernel_mode_t;
typedef unsigned short __kernel_nlink_t;
typedef long __kernel_off_t;
typedef int __kernel_pid_t;
typedef unsigned short __kernel_uid_t;
typedef unsigned short __kernel_gid_t;
typedef unsigned long __kernel_size_t;
typedef int __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
typedef long __kernel_time_t;
typedef long __kernel_clock_t;
typedef int __kernel_daddr_t;
typedef char * __kernel_caddr_t;
 
#ifdef __GNUC__
typedef long long __kernel_loff_t;
#endif
 
typedef struct {
#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
int __val[2];
#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
 
#undef __FD_SET
#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
 
#undef __FD_CLR
#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
 
#undef __FD_ISSET
#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
 
#undef __FD_ZERO
#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
 
#endif
/sigcontext.h
0,0 → 1,16
#ifndef _ASMm68k_SIGCONTEXT_H
#define _ASMm68k_SIGCONTEXT_H
 
struct sigcontext_struct {
unsigned long sc_mask; /* old sigmask */
unsigned long sc_usp; /* old user stack pointer */
unsigned long sc_d0;
unsigned long sc_d1;
unsigned long sc_a0;
unsigned long sc_a1;
unsigned short sc_sr;
unsigned long sc_pc;
unsigned short sc_formatvec;
};
 
#endif
/socket.h
0,0 → 1,27
#ifndef _ASM_SOCKET_H
#define _ASM_SOCKET_H
 
#include <asm/sockios.h>
 
/* For setsockoptions(2) */
#define SOL_SOCKET 1
 
#define SO_DEBUG 1
#define SO_REUSEADDR 2
#define SO_TYPE 3
#define SO_ERROR 4
#define SO_DONTROUTE 5
#define SO_BROADCAST 6
#define SO_SNDBUF 7
#define SO_RCVBUF 8
#define SO_KEEPALIVE 9
#define SO_OOBINLINE 10
#define SO_NO_CHECK 11
#define SO_PRIORITY 12
#define SO_LINGER 13
#define SO_BSDCOMPAT 14
/* To add :#define SO_REUSEPORT 15 */
 
#define SO_BINDTODEVICE 25
 
#endif /* _ASM_SOCKET_H */
/mman.h
0,0 → 1,31
#ifndef __M68K_MMAN_H__
#define __M68K_MMAN_H__
 
#define PROT_READ 0x1 /* page can be read */
#define PROT_WRITE 0x2 /* page can be written */
#define PROT_EXEC 0x4 /* page can be executed */
#define PROT_NONE 0x0 /* page can not be accessed */
 
#define MAP_SHARED 0x01 /* Share changes */
#define MAP_PRIVATE 0x02 /* Changes are private */
#define MAP_TYPE 0x0f /* Mask for type of mapping */
#define MAP_FIXED 0x10 /* Interpret addr exactly */
#define MAP_ANONYMOUS 0x20 /* don't use a file */
 
#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
#define MAP_EXECUTABLE 0x1000 /* mark it as a executable */
#define MAP_LOCKED 0x2000 /* pages are locked */
 
#define MS_ASYNC 1 /* sync memory asynchronously */
#define MS_INVALIDATE 2 /* invalidate the caches */
#define MS_SYNC 4 /* synchronous memory sync */
 
#define MCL_CURRENT 1 /* lock all current mappings */
#define MCL_FUTURE 2 /* lock all future mappings */
 
/* compatibility flags */
#define MAP_ANON MAP_ANONYMOUS
#define MAP_FILE 0
 
#endif /* __M68K_MMAN_H__ */
/mcfne.h
0,0 → 1,246
/****************************************************************************/
 
/*
* mcfne.h -- NE2000 in ColdFire eval boards.
*
* (C) Copyright 1999-2000, Greg Ungerer (gerg@moreton.com.au)
*
* 19990409 David W. Miller Converted from m5206ne.h for 5307 eval board
*
* Hacked support for m5206e Cadre III evaluation board
* Fred Stevens (fred.stevens@pemstar.com) 13 April 1999
*/
 
/****************************************************************************/
#ifndef mcfne_h
#define mcfne_h
/****************************************************************************/
 
#include <linux/config.h>
 
/*
* Everything in here is to remap the standard PC style
* ISA bus access to eval board style ISA bus access.
*/
 
/*
* Define the basic hardware resources of NE2000 board.
* The ISA bus is memory mapped on the eval board, with a
* really funky method for accessing odd addresses.
*/
 
#if defined(CONFIG_M5206)
/*
* Defines specific to the 5206 eval boards.
*/
#define NE2000_ADDR 0x40000000
#define NE2000_ODDOFFSET 0x00010000
#define NE2000_IRQ_VECTOR 0xf0
#define NE2000_IRQ_PRIORITY 2
#define NE2000_IRQ_LEVEL 4
#endif
 
#if defined(CONFIG_CADRE3) && defined(CONFIG_M5307)
#define NE2000_ADDR 0x40000000
#define NE2000_ODDOFFSET 0x00010000
#define NE2000_IRQ_VECTOR 0x1b
 
#elif defined(CONFIG_CADRE3)
#define NE2000_ADDR 0x40000000
#define NE2000_ODDOFFSET 0x00010000
#define NE2000_IRQ_VECTOR 0x1c
#define NE2000_IRQ_PRIORITY 2
#define NE2000_IRQ_LEVEL 4
 
#elif defined(CONFIG_NETtel)
#define NE2000_ADDR 0x30000000
#define NE2000_IRQ_VECTOR 25
#define NE2000_IRQ_PRIORITY 1
#define NE2000_IRQ_LEVEL 3
 
#elif defined(CONFIG_M5307)
/*
* Defines for addressing setup of the 5307 eval board.
*/
#define NE2000_ADDR 0xfe600000
#define NE2000_ODDOFFSET 0x00010000
#define NE2000_IRQ_VECTOR 0x1b
#define NE2000_IRQ_PRIORITY 2
#define NE2000_IRQ_LEVEL 3
#endif
 
/*
* Define the PC type resources that the NE2000 board thinks
* it is using.
*/
#define NE2000_ISA_IO 0x300
#if defined(CONFIG_CADRE3) && defined(CONFIG_M5206e)
#define NE2000_ISA_IRQ 4
#else
#define NE2000_ISA_IRQ 3
#endif
 
/*
* The NETtel NE2000 part is mapped in a very strait forward
* way. The standard memory versions of inb/outb will do the
* job.
*/
#ifdef CONFIG_NETtel
 
#ifdef COLDFIRE_NE2000_FUNCS
void ne2000_irqsetup(void)
{
mcf_autovector(NE2000_IRQ_VECTOR);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT1);
}
#endif /* COLDFIRE_NE2000_FUNCS */
 
 
#else
/*
* Re-defines for ColdFire environment... The ne2000 board is
* mapped in sorta strangely, make adjustments for it.
*/
#undef outb
#undef outb_p
#undef inb
#undef inb_p
 
#define outb ne2000_outb
#define inb ne2000_inb
#define outb_p ne2000_outb
#define inb_p ne2000_inb
#define outsb ne2000_outsb
#define outsw ne2000_outsw
#define insb ne2000_insb
#define insw ne2000_insw
 
 
#ifndef COLDFIRE_NE2000_FUNCS
 
void ne2000_outb(unsigned int val, unsigned int addr);
int ne2000_inb(unsigned int addr);
void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len);
void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len);
void ne2000_outsb(unsigned int addr, void *vbuf, unsigned long len);
void ne2000_outsw(unsigned int addr, void *vbuf, unsigned long len);
 
#else
 
/*
* This macro converts a conventional register address into the
* real memory pointer on the SBC5206 eval board...
* This is only needed if the address can be odd!
*/
#define NE2000_PTR(addr) \
((volatile unsigned short *) ((addr & 0x1) ? \
(NE2000_ADDR + NE2000_ODDOFFSET + addr - 1) : \
(NE2000_ADDR + addr)))
 
 
void ne2000_outb(unsigned int val, unsigned int addr)
{
volatile unsigned short *rp;
 
rp = NE2000_PTR(addr);
*rp = val;
}
 
int ne2000_inb(unsigned int addr)
{
volatile unsigned short *rp;
 
rp = NE2000_PTR(addr);
return(*rp);
}
 
void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len)
{
volatile unsigned short *rp;
unsigned char *buf;
 
buf = (unsigned char *) vbuf;
rp = NE2000_PTR(addr);
for (; (len > 0); len--)
*buf++ = *rp;
}
 
void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len)
{
volatile unsigned short *rp;
unsigned short w, *buf;
 
buf = (unsigned short *) vbuf;
rp = (volatile unsigned short *) (NE2000_ADDR + addr);
for (; (len > 0); len--) {
w = *rp;
*buf++ = ((w & 0xff) << 8) | ((w >> 8) & 0xff);
}
}
 
void ne2000_outsb(unsigned int addr, const void *vbuf, unsigned long len)
{
volatile unsigned short *rp;
unsigned char *buf;
 
buf = (unsigned char *) vbuf;
rp = NE2000_PTR(addr);
for (; (len > 0); len--)
*rp = *buf++;
}
 
void ne2000_outsw(unsigned int addr, const void *vbuf, unsigned long len)
{
volatile unsigned short *rp;
unsigned short w, *buf;
 
buf = (unsigned short *) vbuf;
/*rp = NE2000_PTR(addr);*/
rp = (volatile unsigned short *) (NE2000_ADDR + addr);
for (; (len > 0); len--) {
w = *buf++;
*rp = ((w & 0xff) << 8) | ((w >> 8) & 0xff);
}
}
 
 
/*
* Lastly the interrupt set up code...
* Minor diferences between the different board types.
*/
 
#if defined(CONFIG_M5206)
void ne2000_irqsetup(void)
{
volatile unsigned char *icrp;
 
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_ICR4);
*icrp = MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI2;
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT4);
}
#endif
 
#if defined(CONFIG_CADRE3) && !defined(CONFIG_M5307)
void ne2000_irqsetup(void)
{
volatile unsigned char *icrp;
 
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_ICR4);
*icrp = MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI2 | MCFSIM_ICR_AUTOVEC;
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT4);
}
#endif
 
#if defined(CONFIG_M5307)
void ne2000_irqsetup(void)
{
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT3);
printk("\nSIM: %08lx\n", mcf_getimr());
}
#endif
 
#endif /* COLDFIRE_NE2000_FUNCS */
#endif /* CONFIG_NETtel */
 
/****************************************************************************/
#endif /* mcfne_h */

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