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URL https://opencores.org/ocsvn/or2k/or2k/trunk

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    /or2k/trunk/analysis-bin
    from Rev 13 to Rev 16
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  •

Rev 13 → Rev 16

/insnanalysis/test.S
0,0 → 1,225
/* Assembly source, with one of every instruction for the or1k
instruction set */
 
l.j 0
l.jal 0
l.bnf 0
l.bf 0
l.nop 0
l.movhi r0, 0
l.macrc r3
l.sys 4
l.trap 54
l.msync
l.psync
l.csync
l.rfe
/*
lv.all_eq.b r0, r1, r2
lv.all_eq.h r0, r1, r2
lv.all_ge.b r0, r1, r2
lv.all_ge.h r0, r1, r2
lv.all_gt.b r0, r1, r2
lv.all_gt.h r0, r1, r2
lv.all_le.b r0, r1, r2
lv.all_le.h r0, r1, r2
lv.all_lt.b r0, r1, r2
lv.all_lt.h r0, r1, r2
lv.all_ne.b r0, r1, r2
lv.all_ne.h r0, r1, r2
lv.any_eq.b r0, r1, r2
lv.any_eq.h r0, r1, r2
lv.any_ge.b r0, r1, r2
lv.any_ge.h r0, r1, r2
lv.any_gt.b r0, r1, r2
lv.any_gt.h r0, r1, r2
lv.any_le.b r0, r1, r2
lv.any_le.h r0, r1, r2
lv.any_lt.b r0, r1, r2
lv.any_lt.h r0, r1, r2
lv.any_ne.b r0, r1, r2
lv.any_ne.h r0, r1, r2
lv.add.b r0, r1, r2
lv.add.h r0, r1, r2
lv.adds.b r0, r1, r2
lv.adds.h r0, r1, r2
lv.addu.b r0, r1, r2
lv.addu.h r0, r1, r2
lv.addus.b r0, r1, r2
lv.addus.h r0, r1, r2
lv.and r0, r1, r2
lv.avg.b r0, r1, r2
lv.avg.h r0, r1, r2
lv.cmp_eq.b r0, r1, r2
lv.cmp_eq.h r0, r1, r2
lv.cmp_ge.b r0, r1, r2
lv.cmp_ge.h r0, r1, r2
lv.cmp_gt.b r0, r1, r2
lv.cmp_gt.h r0, r1, r2
lv.cmp_le.b r0, r1, r2
lv.cmp_le.h r0, r1, r2
lv.cmp_lt.b r0, r1, r2
lv.cmp_lt.h r0, r1, r2
lv.cmp_ne.b r0, r1, r2
lv.cmp_ne.h r0, r1, r2
lv.madds.h r0, r1, r2
lv.max.b r0, r1, r2
lv.max.h r0, r1, r2
lv.merge.b r0, r1, r2
lv.merge.h r0, r1, r2
lv.min.b r0, r1, r2
lv.min.h r0, r1, r2
lv.msubs.h r0, r1, r2
lv.muls.h r0, r1, r2
lv.nand r0, r1, r2
lv.nor r0, r1, r2
lv.or r0, r1, r2
lv.pack.b r0, r1, r2
lv.pack.h r0, r1, r2
lv.packs.b r0, r1, r2
lv.packs.h r0, r1, r2
lv.packus.b r0, r1, r2
lv.packus.h r0, r1, r2
lv.perm.n r0, r1, r2
lv.rl.b r0, r1, r2
lv.rl.h r0, r1, r2
lv.sll.b r0, r1, r2
lv.sll.h r0, r1, r2
lv.sll r0, r1, r2
lv.srl.b r0, r1, r2
lv.srl.h r0, r1, r2
lv.sra.b r0, r1, r2
lv.sra.h r0, r1, r2
lv.srl r0, r1, r2
lv.sub.b r0, r1, r2
lv.sub.h r0, r1, r2
lv.subs.b r0, r1, r2
lv.subs.h r0, r1, r2
lv.subu.b r0, r1, r2
lv.subu.h r0, r1, r2
lv.subus.b r0, r1, r2
lv.subus.h r0, r1, r2
lv.unpack.b r0, r1, r2
lv.unpack.h r0, r1, r2
lv.xor r0, r1, r2
lv.cust1
lv.cust2
lv.cust3
lv.cust4
*/
l.jr r0
l.jalr r0
l.maci r0, 4
l.cust1
l.cust2
l.cust3
l.cust4
 
l.ld r0, 0(r0)
l.lwz r0, 0(r0)
l.lws r0, 0(r0)
l.lbz r0, 0(r0)
l.lbs r0, 0(r0)
l.lhz r0, 0(r0)
l.lhs r0, 0(r0)
 
l.addi r0, r1, 5
l.addic r0, r1, 5
l.andi r0, r1, 5
l.ori r0, r1, 5
l.xori r0, r1, 5
l.muli r0, r1, 5
l.mfspr r0, r1, 5
l.slli r0, r1, 5
l.srli r0, r1, 5
l.srai r0, r1, 5
l.rori r0, r1, 5
 
l.sfeqi r0, 0
l.sfnei r0, 0
l.sfgtui r0, 0
l.sfgeui r0, 0
l.sfltui r0, 0
l.sfleui r0, 0
l.sfgtsi r0, 0
l.sfgesi r0, 0
l.sfltsi r0, 0
l.sflesi r0, 0
 
l.mtspr r0, r1, 4
l.mac r0, r1
l.msb r0, r1
 
lf.add.s r0, r1, r2
lf.sub.s r0, r1, r2
lf.mul.s r0, r1, r2
lf.div.s r0, r1, r2
lf.itof.s r0, r1
lf.ftoi.s r0, r1
lf.rem.s r0, r1, r1
lf.madd.s r0, r1, r1
lf.sfeq.s r0, r1
lf.sfne.s r0, r1
lf.sfgt.s r0, r1
lf.sfge.s r0, r1
lf.sflt.s r0, r1
lf.sfle.s r0, r1
lf.cust1.s r0, r1
 
lf.add.d r0, r1, r2
lf.sub.d r0, r1, r2
lf.mul.d r0, r1, r2
lf.div.d r0, r1, r2
lf.itof.d r0, r1
lf.ftoi.d r0, r1
lf.rem.d r0, r1, r2
lf.madd.d r0, r1, r2
lf.sfeq.d r0, r1
lf.sfne.d r0, r1
lf.sfgt.d r0, r1
lf.sfge.d r0, r1
lf.sflt.d r0, r1
lf.sfle.d r0, r1
lf.cust1.d r0, r1
 
l.sd 0(r0), r1
l.sw 0(r0), r1
l.sb 0(r0), r1
l.sh 0(r0), r1
 
l.add r0, r1, r2
l.addc r0, r1, r2
l.sub r0, r1, r2
l.and r0, r1, r2
l.or r0, r1, r2
l.xor r0, r1, r2
l.mul r0, r1, r2
 
l.sll r0, r1, r2
l.srl r0, r1, r2
l.sra r0, r1, r2
l.ror r0, r1, r2
l.div r0, r1, r2
l.divu r0, r1, r2
l.mulu r0, r1, r2
l.extbs r0, r1
l.exths r0, r1
l.extws r0, r1
l.extbz r0, r1
l.exthz r0, r1
l.extwz r0, r1
l.cmov r0, r1, r2
l.ff1 r0, r1
l.fl1 r0, r1
 
l.sfeq r0, r1
l.sfne r0, r1
l.sfgtu r0, r1
l.sfgeu r0, r1
l.sfltu r0, r1
l.sfleu r0, r1
l.sfgts r0, r1
l.sfges r0, r1
l.sflts r0, r1
l.sfles r0, r1
 
/insnanalysis/insnanalysis.h
0,0 → 1,20
/*
Header for instruction analysis program.
 
Define instruction sets here
 
*/
 
// Settings for or1k 32-bit instruction analysis
#include "stdint.h"
#include "or1k-32-insn.h"
 
// 4 bytes per instruction
#define INSN_SIZE_BYTES 4
 
typedef uint32_t instruction;
 
typedef struct or1k_32_instruction_properties instruction_properties ;
 
#define reset_instruction_properties(x) memset(x, 0, sizeof(instruction_properties))
 
/insnanalysis/insn-lists.c
0,0 → 1,39
/*
Instruction list-keeping functions, aiding analysis
 
*/
 
 
#include "insnanalysis.h"
#include "insn-lists.h"
 
 
void insn_lists_init(void)
{
or1k_32_insn_lists_init();
}
int insn_lists_check(instruction insn,
instruction_properties *insn_props)
{
return or1k_32_insn_lists_check(insn, insn_props);
}
 
 
int insn_lists_add_unique_insn(instruction insn,
instruction_properties *insn_props)
{
 
return or1k_32_insn_lists_add_unique_insn(insn, insn_props);
}
 
void insn_lists_add(int index, instruction insn,
instruction_properties *insn_props)
{
or1k_32_insn_lists_add_unique_insn(insn, insn_props);
}
 
void insn_lists_free(void)
{
or1k_32_insn_lists_free();
}
/insnanalysis/or1k-32-insn.c
0,0 → 1,1048
#include "stdio.h"
#include "stdint.h"
#include "stdlib.h"
#include "string.h"
#include "or1k-32-insn.h"
 
// These should also be in insnanalysis.h insnanalysis.h
typedef uint32_t instruction;
typedef struct or1k_32_instruction_properties instruction_properties ;
 
#include "insn-lists.h"
 
 
int or1k_32_analyse_insn(uint32_t insn,
struct or1k_32_instruction_properties * insn_props)
{
switch(insn_or1k_opcode(insn))
{
case 0x00:
insn_props->insn_string="l.j";
insn_props->has_jumptarg = 1;
break;
case 0x01:
insn_props->insn_string="l.jal";
insn_props->has_jumptarg = 1;
break;
 
case 0x03:
insn_props->insn_string="l.bnf";
insn_props->has_branchtarg = 1;
break;
 
case 0x04:
insn_props->insn_string="l.bf";
insn_props->has_branchtarg = 1;
break;
 
case 0x05:
insn_props->insn_string="l.nop";
break;
 
case 0x06:
if((insn_or1k_opcode_0x06_get_id(insn)))
insn_props->insn_string="l.macrc";
else
{
insn_props->insn_string="l.movhi";
insn_props->has_rD = 1;
insn_props->has_imm = 1;
}
break;
case 0x08:
switch(insn_or1k_opcode_0x08_get_id(insn))
{
case 0x0:
insn_props->insn_string="l.sys";
break;
case 0x2:
insn_props->insn_string="l.trap";
break;
case 0x4:
insn_props->insn_string="l.msync";
break;
case 0x5:
insn_props->insn_string="l.psync";
break;
case 0x6:
insn_props->insn_string="l.csync";
break;
default:
printf("Unknown id (0x%x) in opcode 0x8",
insn_or1k_opcode_0x08_get_id(insn) );
return 1;
break;
}
break;
 
case 0x09:
insn_props->insn_string="l.rfe";
break;
case 0x0a:
switch(insn_or1k_opcode_0x0a_get_op_hi(insn))
{
case 0x1:
switch(insn_or1k_opcode_0x0a_get_op_lo(insn))
{
case 0x0:
break;
case 0x1:
break;
case 0x2:
break;
case 0x3:
break;
case 0x4:
break;
case 0x5:
break;
case 0x6:
break;
case 0x7:
break;
case 0x8:
break;
case 0x9:
break;
case 0xa:
break;
case 0xb:
break;
default:
printf("Unknown lv.all_xx insn");
}
case 0x2:
switch(insn_or1k_opcode_0x0a_get_op_lo(insn))
{
case 0x0:
break;
case 0x1:
break;
case 0x2:
break;
case 0x3:
break;
case 0x4:
break;
case 0x5:
break;
case 0x6:
break;
case 0x7:
break;
case 0x8:
break;
case 0x9:
break;
case 0xa:
break;
case 0xb:
break;
default:
printf("Unknown lv.any_xx insn");
}
break;
case 0x3:
switch(insn_or1k_opcode_0x0a_get_op_lo(insn))
{
case 0x0:
break;
case 0x1:
break;
case 0x2:
break;
case 0x3:
break;
case 0x4:
break;
case 0x5:
break;
case 0x6:
break;
case 0x7:
break;
case 0x8:
break;
case 0x9:
break;
case 0xa:
break;
default:
printf("Unknown lv.add/and/avg_xx insn");
}
break;
case 0x4:
switch(insn_or1k_opcode_0x0a_get_op_lo(insn))
{
case 0x0:
break;
case 0x1:
break;
case 0x2:
break;
case 0x3:
break;
case 0x4:
break;
case 0x5:
break;
case 0x6:
break;
case 0x7:
break;
case 0x8:
break;
case 0x9:
break;
case 0xa:
break;
case 0xb:
break;
default:
printf("Unknown lv.cmp_xx insn");
}
break;
case 0x5:
switch(insn_or1k_opcode_0x0a_get_op_lo(insn))
{
case 0x4:
break;
case 0x5:
break;
case 0x6:
break;
case 0x7:
break;
case 0x8:
break;
case 0x9:
break;
case 0xa:
break;
case 0xb:
break;
case 0xc:
break;
case 0xd:
break;
case 0xe:
break;
case 0xf:
break;
default:
printf("Unknown lv.alu_xx insn");
}
break;
case 0x6:
switch(insn_or1k_opcode_0x0a_get_op_lo(insn))
{
case 0x0:
break;
case 0x1:
break;
case 0x2:
break;
case 0x3:
break;
case 0x4:
break;
case 0x5:
break;
case 0x6:
break;
case 0x7:
break;
case 0x8:
break;
case 0x9:
break;
case 0xa:
break;
case 0xb:
break;
case 0xc:
break;
case 0xd:
break;
case 0xe:
break;
case 0xf:
break;
default:
printf("Unknown lv.pack_xx insn");
}
break;
case 0x7:
switch(insn_or1k_opcode_0x0a_get_op_lo(insn))
{
case 0x0:
break;
case 0x1:
break;
case 0x2:
break;
case 0x3:
break;
case 0x4:
break;
case 0x5:
break;
case 0x6:
break;
case 0x7:
break;
case 0x8:
break;
case 0x9:
break;
case 0xa:
break;
case 0xb:
break;
default:
printf("Unknown lv.sub/unpack/xor_xx insn");
}
break;
case 0xc:
break;
case 0xd:
break;
case 0xe:
break;
case 0xf:
break;
default:
printf("Unknown lv.xxx insn hi op");
break;
}
break;
case 0x11:
insn_props->insn_string="l.jr";
insn_props->has_rB = 1;
break;
 
case 0x12:
insn_props->insn_string="l.jalr";
insn_props->has_rB = 1;
break;
case 0x13:
insn_props->insn_string="l.maci";
break;
 
case 0x1c:
insn_props->insn_string="l.cust1";
break;
 
case 0x1d:
insn_props->insn_string="l.cust2";
break;
 
case 0x1e:
insn_props->insn_string="l.cust3";
break;
 
case 0x1f:
insn_props->insn_string="l.cust4";
break;
 
case 0x20:
insn_props->insn_string="l.ld";
insn_props->has_rD = 1;
insn_props->has_rA = 1;
insn_props->has_imm = 1;
break;
 
case 0x21:
insn_props->insn_string="l.lwz";
insn_props->has_rD = 1;
insn_props->has_rA = 1;
insn_props->has_imm = 1;
break;
 
case 0x22:
insn_props->insn_string="l.lws";
insn_props->has_rD = 1;
insn_props->has_rA = 1;
insn_props->has_imm = 1;
break;
 
case 0x23:
insn_props->insn_string="l.lbz";
insn_props->has_rD = 1;
insn_props->has_rA = 1;
insn_props->has_imm = 1;
break;
 
case 0x24:
insn_props->insn_string="l.lbs";
insn_props->has_rD = 1;
insn_props->has_rA = 1;
insn_props->has_imm = 1;
break;
 
case 0x25:
insn_props->insn_string="l.lhz";
insn_props->has_rD = 1;
insn_props->has_rA = 1;
insn_props->has_imm = 1;
break;
 
case 0x26:
insn_props->insn_string="l.lhs";
insn_props->has_rD = 1;
insn_props->has_rA = 1;
insn_props->has_imm = 1;
break;
 
 
case 0x27:
insn_props->insn_string="l.addi";
insn_props->has_rD = 1;
insn_props->has_rA = 1;
insn_props->has_imm = 1;
break;
 
case 0x28:
insn_props->insn_string="l.addic";
insn_props->has_rD = 1;
insn_props->has_rA = 1;
insn_props->has_imm = 1;
break;
 
case 0x29:
insn_props->insn_string="l.andi";
insn_props->has_rD = 1;
insn_props->has_rA = 1;
insn_props->has_imm = 1;
break;
 
case 0x2a:
insn_props->insn_string="l.ori";
insn_props->has_rD = 1;
insn_props->has_rA = 1;
insn_props->has_imm = 1;
break;
 
case 0x2b:
insn_props->insn_string="l.xori";
insn_props->has_rD = 1;
insn_props->has_rA = 1;
insn_props->has_imm = 1;
break;
 
case 0x2c:
insn_props->insn_string="l.muli";
insn_props->has_rD = 1;
insn_props->has_rA = 1;
insn_props->has_imm = 1;
break;
 
case 0x2d:
insn_props->insn_string="l.mfspr";
insn_props->has_rD = 1;
insn_props->has_rA = 1;
insn_props->has_imm = 1;
break;
 
case 0x2e:
switch(insn_or1k_opcode_0x2e_get_op(insn))
{
case 0x0:
insn_props->insn_string="l.slli";
break;
case 0x1:
insn_props->insn_string="l.srli";
break;
case 0x2:
insn_props->insn_string="l.srai";
break;
case 0x3:
insn_props->insn_string="l.rori";
break;
default:
printf("Unknown shift op (0x%x)",
insn_or1k_opcode_0x2e_get_op(insn));
break;
}
break;
case 0x2f:
switch(insn_or1k_opcode_0x2f_get_op(insn))
{
case 0x0:
insn_props->insn_string="l.sfeqi";
break;
case 0x1:
insn_props->insn_string="l.sfnei";
break;
case 0x2:
insn_props->insn_string="l.sfgtui";
break;
case 0x3:
insn_props->insn_string="l.sfgeui";
break;
case 0x4:
insn_props->insn_string="l.sfltui";
break;
case 0x5:
insn_props->insn_string="l.sfleui";
break;
case 0xa:
insn_props->insn_string="l.sfgtsi";
break;
case 0xb:
insn_props->insn_string="l.sfgesi";
break;
case 0xc:
insn_props->insn_string="l.sfltsi";
break;
case 0xd:
insn_props->insn_string="l.sflesi";
break;
default:
printf("Unknown set flag op (0x%x)",
insn_or1k_opcode_0x2f_get_op(insn));
break;
}
insn_props->has_rA = 1;
insn_props->has_imm = 1;
break;
 
case 0x30:
insn_props->insn_string="l.mtspr";
break;
 
case 0x31:
switch (insn_or1k_opcode_0x31_get_op(insn))
{
case 0x1:
insn_props->insn_string="l.mac";
break;
case 0x2:
insn_props->insn_string="l.msb";
break;
default:
printf("Unknown mac op (0x%x)",
insn_or1k_opcode_0x31_get_op(insn));
}
break;
 
case 0x32:
switch(insn_or1k_opcode_0x32_get_op_hi(insn))
{
case 0x0:
switch(insn_or1k_opcode_0x32_get_op_lo(insn))
{
case 0x0:
insn_props->insn_string="lf.add.s";
break;
case 0x1:
insn_props->insn_string="lf.sub.s";
break;
case 0x2:
insn_props->insn_string="lf.mul.s";
break;
case 0x3:
insn_props->insn_string="lf.div.s";
break;
case 0x4:
insn_props->insn_string="lf.itof.s";
break;
case 0x5:
insn_props->insn_string="lf.ftoi.s";
break;
case 0x6:
insn_props->insn_string="lf.rem.s";
break;
case 0x7:
insn_props->insn_string="lf.madd.s";
break;
case 0x8:
insn_props->insn_string="lf.sfeq.s";
break;
case 0x9:
insn_props->insn_string="lf.sfne.s";
break;
case 0xa:
insn_props->insn_string="lf.sfgt.s";
break;
case 0xb:
insn_props->insn_string="lf.sfge.s";
break;
case 0xc:
insn_props->insn_string="lf.sflt.s";
break;
case 0xd:
insn_props->insn_string="lf.sfle.s";
break;
default:
printf("Unknown lf.xxx.s op (0x%x)",
insn_or1k_opcode_0x32_get_op_lo(insn));
break;
}
break;
case 0x1:
switch(insn_or1k_opcode_0x32_get_op_lo(insn))
{
case 0x0:
insn_props->insn_string="lf.add.d";
break;
case 0x1:
insn_props->insn_string="lf.sub.d";
break;
case 0x2:
insn_props->insn_string="lf.mul.d";
break;
case 0x3:
insn_props->insn_string="lf.div.d";
break;
case 0x4:
insn_props->insn_string="lf.itof.d";
break;
case 0x5:
insn_props->insn_string="lf.ftoi.d";
break;
case 0x6:
insn_props->insn_string="lf.rem.d";
break;
case 0x7:
insn_props->insn_string="lf.madd.d";
break;
case 0x8:
insn_props->insn_string="lf.sfeq.d";
break;
case 0x9:
insn_props->insn_string="lf.sfne.d";
break;
case 0xa:
insn_props->insn_string="lf.sfgt.d";
break;
case 0xb:
insn_props->insn_string="lf.sfge.d";
break;
case 0xc:
insn_props->insn_string="lf.sflt.d";
break;
case 0xd:
insn_props->insn_string="lf.sfle.d";
break;
default:
printf("Unknown lf.xxx.d op (0x%x)",
insn_or1k_opcode_0x32_get_op_lo(insn));
break;
}
break;
case 0xd:
insn_props->insn_string="lf.cust1.s";
break;
 
case 0xe:
insn_props->insn_string="lf.cust1.d";
break;
default:
printf("Unknown lf.xxx opcode hi (0x%x)",
insn_or1k_opcode_0x32_get_op_hi(insn));
break;
}
break;
 
case 0x34:
insn_props->insn_string="l.sd";
break;
case 0x35:
insn_props->insn_string="l.sw";
break;
case 0x36:
insn_props->insn_string="l.sb";
break;
case 0x37:
insn_props->insn_string="l.sh";
break;
 
case 0x38:
switch(insn_or1k_opcode_0x38_get_op_lo(insn))
{
insn_props->has_rD = 1;
insn_props->has_rA = 1;
insn_props->has_rB = 1;
case 0x0:
insn_props->insn_string="l.add";
break;
case 0x1:
insn_props->insn_string="l.addc";
break;
case 0x2:
insn_props->insn_string="l.sub";
break;
case 0x3:
insn_props->insn_string="l.and";
break;
case 0x4:
insn_props->insn_string="l.or";
break;
case 0x5:
insn_props->insn_string="l.xor";
break;
case 0x6:
insn_props->insn_string="l.mul";
break;
case 0x8:
switch (insn_or1k_opcode_0x38_get_op_hi_4bit(insn))
{
case 0x0:
insn_props->insn_string="l.sll";
break;
case 0x1:
insn_props->insn_string="l.srl";
break;
case 0x2:
insn_props->insn_string="l.sra";
break;
case 0x3:
insn_props->insn_string="l.ror";
break;
default:
printf("Unknown ALU op 0x8 hi op (0x%x)",
insn_or1k_opcode_0x38_get_op_hi_4bit(insn));
break;
}
break;
case 0x9:
insn_props->insn_string="l.div";
break;
case 0xa:
insn_props->insn_string="l.divu";
break;
case 0xb:
insn_props->insn_string="l.mulu";
break;
case 0xc:
switch(insn_or1k_opcode_0x38_get_op_hi_4bit(insn))
{
case 0x0:
insn_props->insn_string="l.exths";
break;
case 0x1:
insn_props->insn_string="l.extbs";
break;
case 0x2:
insn_props->insn_string="l.exthz";
break;
case 0x3:
insn_props->insn_string="l.extbz";
break;
}
insn_props->has_rB = 0;
break;
case 0xd:
insn_props->insn_string="l.extws";
insn_props->has_rB = 0;
break;
case 0xe:
insn_props->insn_string="l.cmov";
break;
 
case 0xf:
if (insn_or1k_opcode_0x38_get_op_hi_2bit(insn) & 0x1)
insn_props->insn_string="l.fl1";
else
insn_props->insn_string="l.ff1";
insn_props->has_rB = 0;
break;
 
default:
printf("Unknown ALU lo op (0x%x)",
insn_or1k_opcode_0x38_get_op_lo(insn));
break;
}
break;
 
case 0x39:
switch (insn_or1k_opcode_0x39_get_op(insn))
{
insn_props->has_rA = 0;
insn_props->has_rB = 0;
case 0x0:
insn_props->insn_string="l.sfeq";
break;
case 0x1:
insn_props->insn_string="l.sfne";
break;
case 0x2:
insn_props->insn_string="l.sfgtu";
break;
case 0x3:
insn_props->insn_string="l.sfgeu";
break;
case 0x4:
insn_props->insn_string="l.sfltu";
break;
case 0x5:
insn_props->insn_string="l.sfleu";
break;
case 0xa:
insn_props->insn_string="l.sfgts";
break;
case 0xb:
insn_props->insn_string="l.sfges";
break;
case 0xc:
insn_props->insn_string="l.sflts";
break;
case 0xd:
insn_props->insn_string="l.sfles";
break;
default:
printf("Unknown opcode for l.sfxxx opcode (0x%x)",
insn_or1k_opcode_0x39_get_op(insn));
break;
}
break;
default:
printf("Unknown opcode 0x%x",insn_or1k_opcode(insn));
return 1;
break;
}
 
return 0;
}
 
 
 
void or1k_32_collect_stats(uint32_t insn,
struct or1k_32_instruction_properties * insn_props)
{
// First calculate frequency
int index = insn_lists_check(insn, insn_props);
// Create new entry in list
if (index == IS_UNIQUE)
index = insn_lists_add_unique_insn(insn, insn_props);
// Now count it
insn_lists_add(index, insn, insn_props);
 
}
 
 
 
struct or1k_value_list
{
 
#define OR1K_VALUE_MAX_ENTRIES 64
int count;
// [value][occurances_of_value]
int values[OR1K_VALUE_MAX_ENTRIES][2];
};
 
struct or1k_insn_info
{
char* insn_string;
 
int count;
int has_branchtarg;
struct or1k_value_list branch_info;
 
int has_imm;
 
struct or1k_value_list imm_info;
 
int has_rD;
int rD_use_freq[32];
int has_rA;
int rA_use_freq[32];
int has_rB;
int rB_use_freq[32];
 
};
 
#define OR1K_32_MAX_INSNS 120
struct or1k_insn_info * or1k_32_insns[OR1K_32_MAX_INSNS];
 
 
// List management/analysis functions - accessed through insn_lists() set of
// functions
 
// Variable to keep track of unique instructions we have
int num_unique_insns;
int num_seen_insns;
 
 
void or1k_32_insn_lists_init(void)
{
num_unique_insns = 0;
num_seen_insns = 0;
}
 
// List management/analysis functions
int or1k_32_insn_lists_check(uint32_t insn,
struct or1k_32_instruction_properties *insn_props)
{
int num_to_check = num_unique_insns;
int insn_strlen = strlen(insn_props->insn_string);
while (num_to_check)
{
--num_to_check;
if ((strncmp(insn_props->insn_string,
or1k_32_insns[num_to_check]->insn_string, insn_strlen) == 0)
&& (insn_strlen == strlen(or1k_32_insns[num_to_check]->insn_string)))
{
// Found match by string
return num_to_check;
}
}
 
return IS_UNIQUE;
}
 
// Add a unique instruction
int or1k_32_insn_lists_add_unique_insn(uint32_t insn,
struct or1k_32_instruction_properties *insn_props)
{
// Add an instruction in or1k_32_insns[num_unique_instructions];
// use calloc() so it clears it all first (hopefully!).. assumption!
struct or1k_insn_info * new_insn
= (struct or1k_insn_info *) calloc (sizeof(struct or1k_insn_info), 1);
 
// Calloc() space for the string
new_insn->insn_string = (char *) calloc(strlen(insn_props->insn_string), 1);
 
// Copy in the instruction string
strncpy(new_insn->insn_string, insn_props->insn_string,
strlen(insn_props->insn_string));
 
// Install the pointer for this new instruction in the list
or1k_32_insns[num_unique_insns] = new_insn;;
 
// Increment number of instructions we have
num_unique_insns++;
 
// Return index of newly created instruction
return (num_unique_insns - 1);
 
}
 
// Add to, or increment incidences of, value in the value list
void or1k_add_in_list(struct or1k_value_list * list, int value)
{
int i;
// See if it's already in the list
i=list->count;
 
while(i)
{
i--;
if(list->values[i][0] == value)
{
(list->values[i][1])++;
return;
}
}
// Not found, add it to the list
list->values[(list->count)][0] = value;
list->values[(list->count)][1] = 1;
}
 
 
// Add stats for this instruction
void or1k_32_insn_lists_add(int index, uint32_t insn,
struct or1k_32_instruction_properties *insn_props)
{
// Add stats for this instruction
// Increment count
((or1k_32_insns[index])->count)++;
 
// Add branch target value information, if instruction has it
if (insn_props->has_branchtarg)
{
(or1k_32_insns[index])->has_branchtarg = 1;
or1k_add_in_list(&((or1k_32_insns[index])->branch_info),
(int)insn_or1k_opcode_0x03_get_branchoff(insn));
}
// Add immediate value if it's got one
if (insn_props->has_imm)
{
(or1k_32_insns[index])->has_imm = 1;
or1k_add_in_list(&((or1k_32_insns[index])->imm_info),
(int)insn_or1k_32_imm(insn));
}
// Add split immediate value if it's got one
if (insn_props->has_split_imm)
{
(or1k_32_insns[index])->has_imm = 1;
or1k_add_in_list(&((or1k_32_insns[index])->imm_info),
(int)insn_or1k_32_split_imm(insn));
}
 
 
// Increment count of use for particular rD
if (insn_props->has_rD)
{
(or1k_32_insns[index])->has_rD = 1;
((or1k_32_insns[index])->rD_use_freq[insn_or1k_32_rD(insn)])++;
}
 
// Increment count of use for particular rA
if (insn_props->has_rA)
{
(or1k_32_insns[index])->has_rA = 1;
((or1k_32_insns[index])->rA_use_freq[insn_or1k_32_rA(insn)])++;
}
// Increment count of use for particular rB
if (insn_props->has_rB)
{
(or1k_32_insns[index])->has_rB = 1;
((or1k_32_insns[index])->rB_use_freq[insn_or1k_32_rB(insn)])++;
}
 
// Finished adding to stats for this instruction
// Increment overall instructions "seen" counter
num_seen_insns++;
 
}
 
 
// Free up all added instruction statistic tracking structs
void or1k_32_insn_lists_free(void)
{
while (num_unique_insns)
{
 
num_unique_insns--;
free(or1k_32_insns[num_unique_insns]);
}
}
/insnanalysis/insn-lists.h
0,0 → 1,20
 
#define IS_UNIQUE -1
 
 
// Function prototypes
//
// Reset the variables/counters
void insn_lists_init(void);
// Check if an instruction is in the list already
int insn_lists_check(instruction insn,
instruction_properties *insn_props);
// Add a new instruction to the list, return its index
int insn_lists_add_unique_insn(instruction insn,
instruction_properties *insn_props);
// Report a new incidence of an instruction
void insn_lists_add(int index, instruction insn,
instruction_properties *insn_props);
 
// Free, clean up, anything we need to
void insn_lists_free(void);
/insnanalysis/or1k-32-insn.h
0,0 → 1,230
 
// OpenRISC 1000 32-bit instruction defines, helping us
// extract fields of the instructions
 
 
 
// Struct for information about the register to be confugred
// Set to 1 to enable
struct or1k_32_instruction_properties
{
int has_jumptarg;
int has_branchtarg;
 
int has_imm;
int has_split_imm;
 
int has_rD;
int has_rA;
int has_rB;
 
char *insn_string;
 
};
 
// Instruction decode/set its options
int or1k_32_analyse_insn(uint32_t insn,
struct or1k_32_instruction_properties *insn_props);
 
 
// Stat collection entry-oint
void or1k_32_collect_stats(uint32_t insn,
struct or1k_32_instruction_properties * insn_props);
 
 
// List management/analysis functions
// Reset lists
void or1k_32_insn_lists_init(void);
 
// Check for an instruction
int or1k_32_insn_lists_check(uint32_t insn,
struct or1k_32_instruction_properties *insn_props);
 
// Add a unique instruction
int or1k_32_insn_lists_add_unique_insn(uint32_t insn,
struct or1k_32_instruction_properties *insn_props);
 
// Add the stats for this one
void or1k_32_insn_lists_add(int index, uint32_t insn,
struct or1k_32_instruction_properties *insn_props);
 
// Free lists
void or1k_32_insn_lists_free(void);
 
#define JUMPTARG_MASK 0x3ffffff
 
#define insn_or1k_opcode(x) (x>>26 & 0x3f)
 
#define insn_or1k_32_rD(x) (((x>>21)&0x1f))
#define insn_or1k_32_rA(x) (((x>>16)&0x1f))
#define insn_or1k_32_rB(x) (((x>>11)&0x1f))
#define insn_or1k_32_imm(x) (x&0xffff)
#define insn_or1k_32_split_imm(x) ((((x>>21)&0x1f)<<11)|(x&0x7ff))
 
#define insn_or1k_opcode_0x00_get_jumptarg(x) (x&JUMPTARG_MASK)
 
#define insn_or1k_opcode_0x01_get_jumptarg(x) (x&JUMPTARG_MASK)
 
#define insn_or1k_opcode_0x03_get_branchoff(x) (x&JUMPTARG_MASK)
 
#define insn_or1k_opcode_0x04_get_branchoff(x) (x&JUMPTARG_MASK)
 
#define insn_or1k_opcode_0x05_get_noop_id(x) ((x>>24) & 0x3)
#define insn_or1k_opcode_0x05_get_imm(x) insn_or1k_32_imm(x)
 
#define insn_or1k_opcode_0x06_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x06_get_id(x) ((x>>16) & 0x1)
#define insn_or1k_opcode_0x06_get_imm(x) insn_or1k_32_imm(x)
 
/* N/A: opcode 0x7 */
 
#define insn_or1k_opcode_0x08_get_id(x) ((x>>23)&0x7)
#define insn_or1k_opcode_0x08_get_imm(x) insn_or1k_32_imm(x)
 
#define insn_or1k_opcode_0x0a_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x0a_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x0a_get_rB(x) insn_or1k_32_rB(x)
#define insn_or1k_opcode_0x0a_get_op_hi(x) ((x>>4)&0xf)
#define insn_or1k_opcode_0x0a_get_op_lo(x) (x&0xf)
 
/* N/A: opcodes 0xb,c,d,e,f,10 */
 
#define insn_or1k_opcode_0x11_get_rB(x) insn_or1k_32_rB(x)
 
#define insn_or1k_opcode_0x12_get_rB(x) insn_or1k_32_rB(x)
 
#define insn_or1k_opcode_0x13_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x13_get_imm(x) insn_or1k_32_split_imm(x)
 
/* N/A: opcodes 0x14,15, 16, 17, 18, 19, 1a, 1b */
 
#define insn_or1k_opcode_0x20_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x20_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x20_get_imm(x) insn_or1k_32_imm(x)
 
 
#define insn_or1k_opcode_0x21_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x21_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x21_get_imm(x) insn_or1k_32_imm(x)
 
 
#define insn_or1k_opcode_0x22_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x22_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x22_get_imm(x) insn_or1k_32_imm(x)
 
 
#define insn_or1k_opcode_0x23_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x23_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x23_get_imm(x) insn_or1k_32_imm(x)
 
 
#define insn_or1k_opcode_0x24_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x24_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x24_get_imm(x) insn_or1k_32_imm(x)
 
 
#define insn_or1k_opcode_0x25_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x25_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x25_get_imm(x) insn_or1k_32_imm(x)
 
 
#define insn_or1k_opcode_0x26_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x26_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x26_get_imm(x) insn_or1k_32_imm(x)
 
 
#define insn_or1k_opcode_0x27_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x27_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x27_get_imm(x) insn_or1k_32_imm(x)
 
#define insn_or1k_opcode_0x28_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x28_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x28_get_imm(x) insn_or1k_32_imm(x)
 
 
#define insn_or1k_opcode_0x29_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x29_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x29_get_imm(x) insn_or1k_32_imm(x)
 
 
#define insn_or1k_opcode_0x2a_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x2a_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x2a_get_imm(x) insn_or1k_32_imm(x)
 
 
#define insn_or1k_opcode_0x2b_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x2b_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x2b_get_imm(x) insn_or1k_32_imm(x)
 
 
#define insn_or1k_opcode_0x2c_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x2c_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x2c_get_imm(x) insn_or1k_32_imm(x)
 
 
#define insn_or1k_opcode_0x2d_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x2d_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x2d_get_imm(x) insn_or1k_32_imm(x)
 
 
#define insn_or1k_opcode_0x2e_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x2e_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x2e_get_op(x) ((x>>6)&0x3)
#define insn_or1k_opcode_0x2e_get_imm(x) ((x&3f))
 
 
#define insn_or1k_opcode_0x2f_get_op(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x2f_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x2f_get_imm(x) insn_or1k_32_imm(x)
 
 
#define insn_or1k_opcode_0x30_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x30_get_rB(x) insn_or1k_32_rB(x)
#define insn_or1k_opcode_0x30_get_imm(x) insn_or1k_32_split_imm(x)
 
 
#define insn_or1k_opcode_0x31_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x31_get_rB(x) insn_or1k_32_rB(x)
#define insn_or1k_opcode_0x31_get_op(x) (x&0xf)
 
 
#define insn_or1k_opcode_0x32_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x32_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x32_get_rB(x) insn_or1k_32_rB(x)
#define insn_or1k_opcode_0x32_get_op_hi(x) ((x>>4)&0xf)
#define insn_or1k_opcode_0x32_get_op_lo(x) ((x&0xf))
 
/* N/A: opcodes 0x33 */
 
#define insn_or1k_opcode_0x34_get_rD(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x34_get_rB(x) insn_or1k_32_rB(x)
#define insn_or1k_opcode_0x34_get_imm(x) insn_or1k_32_split_imm(x)
 
 
#define insn_or1k_opcode_0x35_get_rD(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x35_get_rB(x) insn_or1k_32_rB(x)
#define insn_or1k_opcode_0x35_get_imm(x) insn_or1k_32_split_imm(x)
 
 
#define insn_or1k_opcode_0x36_get_rD(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x36_get_rB(x) insn_or1k_32_rB(x)
#define insn_or1k_opcode_0x36_get_imm(x) insn_or1k_32_split_imm(x)
 
 
#define insn_or1k_opcode_0x37_get_rD(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x37_get_rB(x) insn_or1k_32_rB(x)
#define insn_or1k_opcode_0x37_get_imm(x) insn_or1k_32_split_imm(x)
 
 
#define insn_or1k_opcode_0x38_get_rD(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x38_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x38_get_rB(x) insn_or1k_32_rB(x)
#define insn_or1k_opcode_0x38_get_op_hi_2bit(x) ((x>>8)&0x3)
#define insn_or1k_opcode_0x38_get_op_hi_4bit(x) ((x>>6)&0xf)
#define insn_or1k_opcode_0x38_get_op_lo(x) ((x&0xf))
 
#define insn_or1k_opcode_0x39_get_op(x) insn_or1k_32_rD(x)
#define insn_or1k_opcode_0x39_get_rA(x) insn_or1k_32_rA(x)
#define insn_or1k_opcode_0x39_get_rB(x) insn_or1k_32_rB(x)
 
/* N/A: opcodes 0x3a,3b */
/insnanalysis/insnanalysis.c
0,0 → 1,91
/*
File for analysis of an architecture's instructions in binary format
 
Julius Baxter, julius.baxter@orsoc.se
 
*/
 
#include<stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include <arpa/inet.h> // for htonl()
 
#include "insnanalysis.h"
 
// Access to list management functions
#include "insn-lists.h"
 
int analyse_insn(instruction insn,
instruction_properties *insn_props)
{
// For now no other instruction sets supported
return or1k_32_analyse_insn(insn, insn_props);
}
 
 
void print_insn(instruction_properties *insn_props)
{
if (insn_props->insn_string != NULL)
printf("%s", insn_props->insn_string);
}
 
void collect_stats(instruction insn,
instruction_properties *insn_props)
{
or1k_32_collect_stats(insn, insn_props);
}
 
int main(int argc, char *argv[])
{
FILE *fp;
 
char insn_buff[INSN_SIZE_BYTES]; // Buffer for instruction data
 
int insns_seen_total = 0; // Keep track of total number of instructions read
 
// Try to open the file passed as first parameter
if((fp = fopen(argv[ 1 ], "rb"))==NULL) {
printf("Cannot open file.\n");
exit(1);
}
 
instruction * insn = (instruction *)insn_buff;
 
instruction_properties insn_props;
// Do initial analysis - frequency of each instruction
insn_lists_init();
 
while(!feof(fp)) {
if (fread(insn_buff, INSN_SIZE_BYTES, 1, fp) != 1)
break;
// Endianness is little when read in from binary file created with
// or32-elf-objcopy, so swap;
*insn = htonl(*insn);
reset_instruction_properties(&insn_props);
 
analyse_insn(*insn, &insn_props);
print_insn(&insn_props);
printf("\n");
 
insns_seen_total++;
collect_stats(*insn, &insn_props);
}
 
insn_lists_free();
 
fclose(fp);
 
printf("Saw %d instructions\n", insns_seen_total);
return 0;
 
}
/insnanalysis/Makefile
0,0 → 1,24
 
APP=insnanalysis
 
all: $(APP)
 
SRC=insnanalysis.c or1k-32-insn.c insn-lists.c
HDRS=insnanalysis.h or1k-32-insn.h insn-lists.h
 
 
insnanalysis: $(SRC) $(HDRS)
gcc -O2 $(SRC) -o $@
 
 
test: test.bin $(APP)
./$(APP) $<
 
test.bin: test.o
or32-elf-objcopy -O binary $< $@
 
test.o: test.S
or32-elf-as $< -o $@
 
clean:
rm $(APP) *.o *.bin

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