OpenCores
URL https://opencores.org/ocsvn/orsoc_graphics_accelerator/orsoc_graphics_accelerator/trunk

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  • This comparison shows the changes necessary to convert path 
    /orsoc_graphics_accelerator/tags/version1.0/bench/verilog
    from Rev 2 to Rev 3
    ↔ Reverse comparison
  •

Rev 2 → Rev 3

/gfx/line.sav
0,0 → 1,44
[*]
[*] GTKWave Analyzer v3.3.32 (w)1999-2012 BSI
[*] Tue Mar 13 13:52:33 2012
[*]
[dumpfile] "/home/maiden/Creative/Svn/orgfx/bench/verilog/gfx/line.vcd"
[dumpfile_mtime] "Tue Mar 13 13:52:05 2012"
[dumpfile_size] 14931
[savefile] "/home/maiden/Creative/Svn/orgfx/bench/verilog/gfx/line.sav"
[timestart] 0
[size] 1278 715
[pos] -1 -1
*-6.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] line_bench.
[sst_width] 225
[signals_width] 206
[sst_expanded] 1
[sst_vpaned_height] 301
@28
line_bench.bresenham.busy_o
line_bench.bresenham.clk_i
@22
line_bench.bresenham.delta_major_i[15:0]
line_bench.bresenham.delta_minor_i[15:0]
@28
line_bench.bresenham.draw_line_i
@22
line_bench.bresenham.eps[31:0]
line_bench.bresenham.eps_delta_minor[31:0]
line_bench.bresenham.major_goal[15:0]
line_bench.bresenham.major_o[15:0]
line_bench.bresenham.minor_o[15:0]
@28
line_bench.bresenham.minor_slope_positive_i
@22
line_bench.bresenham.pixel0_x_i[15:0]
line_bench.bresenham.pixel0_y_i[15:0]
line_bench.bresenham.pixel1_x_i[15:0]
line_bench.bresenham.pixel1_y_i[15:0]
@28
line_bench.bresenham.read_pixel_i
line_bench.bresenham.rst_i
line_bench.bresenham.x_major_i
[pattern_trace] 1
[pattern_trace] 0
/gfx/gtkwave_raster.sav
0,0 → 1,102
[timestart] 0
[size] 1366 744
[pos] -1 -1
*-5.018312 23 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] raster_bench.
[treeopen] raster_bench.raster.
@200
-sync
@28
raster_bench.raster.clk_i
raster_bench.raster.rst_i
@200
-input
@22
raster_bench.raster.clip_pixel0_x_i[15:0]
raster_bench.raster.clip_pixel0_y_i[15:0]
raster_bench.raster.clip_pixel1_x_i[15:0]
raster_bench.raster.clip_pixel1_y_i[15:0]
raster_bench.raster.dest_pixel0_x_i[15:0]
raster_bench.raster.dest_pixel0_y_i[15:0]
raster_bench.raster.dest_pixel1_x_i[15:0]
raster_bench.raster.dest_pixel1_y_i[15:0]
raster_bench.raster.src_pixel0_x_i[15:0]
raster_bench.raster.src_pixel0_y_i[15:0]
raster_bench.raster.src_pixel1_x_i[15:0]
raster_bench.raster.src_pixel1_y_i[15:0]
raster_bench.raster.target_size_x_i[15:0]
raster_bench.raster.target_size_y_i[15:0]
@28
raster_bench.raster.texture_enable_i
@200
-rect
@28
raster_bench.raster.rect_write_i
raster_bench.raster.empty_raster
raster_bench.raster.raster_rect_done
raster_bench.raster.raster_rect_line_done
@c00022
raster_bench.raster.p0_x[15:0]
@28
(0)raster_bench.raster.p0_x[15:0]
(1)raster_bench.raster.p0_x[15:0]
(2)raster_bench.raster.p0_x[15:0]
(3)raster_bench.raster.p0_x[15:0]
(4)raster_bench.raster.p0_x[15:0]
(5)raster_bench.raster.p0_x[15:0]
(6)raster_bench.raster.p0_x[15:0]
(7)raster_bench.raster.p0_x[15:0]
(8)raster_bench.raster.p0_x[15:0]
(9)raster_bench.raster.p0_x[15:0]
(10)raster_bench.raster.p0_x[15:0]
(11)raster_bench.raster.p0_x[15:0]
(12)raster_bench.raster.p0_x[15:0]
(13)raster_bench.raster.p0_x[15:0]
(14)raster_bench.raster.p0_x[15:0]
(15)raster_bench.raster.p0_x[15:0]
@1401200
-group_end
@22
raster_bench.raster.p0_y[15:0]
raster_bench.raster.p1_x[15:0]
raster_bench.raster.p1_y[15:0]
@200
-line
@28
raster_bench.raster.line_write_i
raster_bench.raster.draw_line
@22
raster_bench.raster.delta_major[15:0]
raster_bench.raster.delta_minor[15:0]
raster_bench.raster.left_pixel_x[15:0]
raster_bench.raster.left_pixel_y[15:0]
raster_bench.raster.right_pixel_x[15:0]
raster_bench.raster.right_pixel_y[15:0]
@28
raster_bench.raster.raster_line_busy
@22
raster_bench.raster.major_out[15:0]
raster_bench.raster.minor_out[15:0]
@28
raster_bench.raster.minor_slope_positive
raster_bench.raster.x_major_axis
@22
raster_bench.raster.ydiff[15:0]
raster_bench.raster.xdiff[15:0]
@200
-pipeline
@28
raster_bench.raster.state[2:0]
raster_bench.raster.ready_i
raster_bench.raster.ready_o
@200
-output
@22
raster_bench.raster.x_counter_o[15:0]
raster_bench.raster.y_counter_o[15:0]
raster_bench.raster.u_o[15:0]
raster_bench.raster.v_o[15:0]
@28
raster_bench.raster.write_o
[pattern_trace] 1
[pattern_trace] 0
/gfx/color_bench.v
0,0 → 1,83
`include "../../../rtl/verilog/gfx/gfx_color.v"
 
module color_bench();
 
reg clk_i;
 
reg [1:0] color_depth_i;
 
reg [31:0] color_i;
reg [1:0] x_lsb_i;
wire [31:0] mem_o;
wire [3:0] mem_sel_o;
 
reg [31:0] mem_i;
wire [31:0] color_o;
wire [3:0] col_sel_o;
 
initial begin
$dumpfile("color.vcd");
$dumpvars(0,color_bench);
 
// init values
clk_i = 0;
color_depth_i = 0;
color_i = 0;
x_lsb_i = 0;
mem_i = 0;
 
// 8 bit tests
#10 color_i = 32'h12345678;
mem_i = 32'habcd1234;
#10 x_lsb_i = 1;
#10 x_lsb_i = 2;
#10 x_lsb_i = 3;
 
 
 
// 16 bit tests
#10 color_depth_i = 1;
x_lsb_i = 0;
#10 x_lsb_i = 1;
#10 x_lsb_i = 2;
#10 x_lsb_i = 3;
 
// 24 bit tests (not supported!)
#10 color_depth_i = 2;
x_lsb_i = 0;
#10 x_lsb_i = 1;
#10 x_lsb_i = 2;
#10 x_lsb_i = 3;
 
// 32 bit tests
#10 color_depth_i = 3;
x_lsb_i = 0;
#10 x_lsb_i = 1;
#10 x_lsb_i = 2;
#10 x_lsb_i = 3;
 
// end sim
#100 $finish;
end
 
always begin
#1 clk_i = ~clk_i;
end
 
color_to_memory color_proc(
.color_depth_i (color_depth_i),
.color_i (color_i),
.x_lsb_i (x_lsb_i),
.mem_o (mem_o),
.sel_o (mem_sel_o)
);
 
memory_to_color memory_proc(
.color_depth_i (color_depth_i),
.mem_i (mem_i),
.mem_lsb_i (x_lsb_i),
.color_o (color_o),
.sel_o (col_sel_o)
);
 
endmodule
/gfx/gtkwave_fragment.sav
0,0 → 1,57
[timestart] 0
[size] 1366 744
[pos] -1 -1
*-5.518517 105 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] fragment_bench.
[treeopen] fragment_bench.fragment.
@200
-sync
@28
fragment_bench.fragment.clk_i
fragment_bench.fragment.rst_i
@200
-input
@28
fragment_bench.fragment.color_depth_i[1:0]
@22
fragment_bench.fragment.global_alpha_i[7:0]
fragment_bench.fragment.pixel_color_i[31:0]
@28
fragment_bench.fragment.texture_enable_i
@22
fragment_bench.fragment.tex0_base_i[31:2]
fragment_bench.fragment.tex0_size_x_i[15:0]
fragment_bench.fragment.tex0_size_y_i[15:0]
fragment_bench.fragment.u_i[15:0]
fragment_bench.fragment.v_i[15:0]
fragment_bench.fragment.x_counter_i[15:0]
fragment_bench.fragment.y_counter_i[15:0]
@200
-output
@22
fragment_bench.fragment.pixel_alpha_o[7:0]
fragment_bench.fragment.pixel_color_o[31:0]
fragment_bench.fragment.pixel_x_o[15:0]
fragment_bench.fragment.pixel_y_o[15:0]
@200
-wbm
@28
fragment_bench.fragment.texture_ack_i
@22
fragment_bench.fragment.texture_addr_o[31:2]
fragment_bench.fragment.texture_data_i[31:0]
@28
fragment_bench.fragment.texture_request_o
@22
fragment_bench.fragment.texture_sel_o[3:0]
@200
-pipeline
@28
fragment_bench.fragment.state[1:0]
fragment_bench.fragment.write_i
fragment_bench.fragment.write_request
fragment_bench.fragment.ready_i
fragment_bench.fragment.ready_o
fragment_bench.fragment.write_o
[pattern_trace] 1
[pattern_trace] 0
/gfx/gtkwave_wbm_r.sav
0,0 → 1,38
[timestart] 0
[size] 1024 744
[pos] -1 -1
*-14.000000 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] wbm_r_bench.
@28
wbm_r_bench.wbm_r.ack_i
@22
wbm_r_bench.wbm_r.adr_o[31:0]
@28
wbm_r_bench.wbm_r.arst_i
wbm_r_bench.wbm_r.bte_o[1:0]
wbm_r_bench.wbm_r.busy
wbm_r_bench.wbm_r.clk_i
wbm_r_bench.wbm_r.cti_o[2:0]
wbm_r_bench.wbm_r.cyc_o
@22
wbm_r_bench.wbm_r.dat_i[31:0]
@28
wbm_r_bench.wbm_r.err_i
wbm_r_bench.wbm_r.read_request_i
wbm_r_bench.wbm_r.rst_i
@22
wbm_r_bench.wbm_r.sel_o[3:0]
@28
wbm_r_bench.wbm_r.sint_o
wbm_r_bench.wbm_r.stb_o
@22
wbm_r_bench.wbm_r.texture_addr_i[31:2]
wbm_r_bench.wbm_r.texture_dat_o[31:0]
@28
wbm_r_bench.wbm_r.texture_data_ack
@22
wbm_r_bench.wbm_r.texture_sel_i[3:0]
@28
wbm_r_bench.wbm_r.we_o
[pattern_trace] 1
[pattern_trace] 0
/gfx/gfx_bench.v
0,0 → 1,440
`include "../../../rtl/verilog/gfx/gfx_wbs.v"
`include "../../../rtl/verilog/gfx/gfx_wbm_write.v"
`include "../../../rtl/verilog/gfx/gfx_wbm_read.v"
`include "../../../rtl/verilog/gfx/gfx_vector_processor.v"
`include "../../../rtl/verilog/gfx/gfx_rasterizer.v"
`include "../../../rtl/verilog/gfx/gfx_fragment_processor.v"
`include "../../../rtl/verilog/gfx/gfx_blender.v"
`include "../../../rtl/verilog/gfx/gfx_renderer.v"
`include "../../../rtl/verilog/gfx/gfx_top.v"
`include "../../../rtl/verilog/gfx/basic_fifo.v"
`include "../../../rtl/verilog/gfx/gfx_color.v"
`include "../../../rtl/verilog/gfx/gfx_wbm_read_arbiter.v"
`include "../../../rtl/verilog/gfx/gfx_line.v"
 
module gfx_bench();
 
// Common wishbone signals
reg wb_clk_i; // master clock reg
reg wb_rst_i; // Asynchronous active high reset
wire wb_inta_o; // interrupt
 
// Wishbone master signals (write)
wire wbm_write_cyc_o; // cycle wire
wire wbm_write_stb_o; // strobe wire
wire [ 2:0] wbm_write_cti_o; // cycle type id
wire [ 1:0] wbm_write_bte_o; // burst type extension
wire wbm_write_we_o; // write enable wire
wire [31:0] wbm_write_adr_o; // address wire
wire [ 3:0] wbm_write_sel_o; // byte select wires (only 32bits accesses are supported)
reg wbm_write_ack_i; // wishbone cycle acknowledge
reg wbm_write_err_i; // wishbone cycle error
wire [31:0] wbm_write_dat_o; // wishbone data out
 
// Wishbone master signals (read)
wire wbm_read_cyc_o; // cycle wire
wire wbm_read_stb_o; // strobe wire
wire [ 2:0] wbm_read_cti_o; // cycle type id
wire [ 1:0] wbm_read_bte_o; // burst type extension
wire wbm_read_we_o; // write enable wire
wire [31:0] wbm_read_adr_o; // address wire
wire [ 3:0] wbm_read_sel_o; // byte select wires (only 32bits accesses are supported)
reg wbm_read_ack_i; // wishbone cycle acknowledge
reg wbm_read_err_i; // wishbone cycle error
reg [31:0] wbm_read_dat_i; // wishbone data in
 
// Wishbone slave signals
reg wbs_cyc_i; // cycle reg
reg wbs_stb_i; // strobe reg
reg [ 2:0] wbs_cti_i; // cycle type id
reg [ 1:0] wbs_bte_i; // burst type extension
reg wbs_we_i; // write enable reg
reg [31:0] wbs_adr_i; // address reg
reg [ 3:0] wbs_sel_i; // byte select reg (only 32bits accesses are supported)
wire wbs_ack_o; // wishbone cycle acknowledge
wire wbs_err_o; // wishbone cycle error
reg [31:0] wbs_dat_i; // wishbone data in
wire [31:0] wbs_dat_o; // wishbone data out
 
parameter GFX_VMEM = 32'h00800000;
 
parameter GFX_CTRL = 32'h000;
parameter GFX_STATUS = 32'h004;
parameter GFX_SRC_PIXEL0 = 32'h008;
parameter GFX_SRC_PIXEL1 = 32'h00c;
parameter GFX_DEST_PIXEL0 = 32'h010;
parameter GFX_DEST_PIXEL1 = 32'h014;
parameter GFX_CLIP_PIXEL0 = 32'h018;
parameter GFX_CLIP_PIXEL1 = 32'h01c;
parameter GFX_COLOR = 32'h020;
parameter GFX_TARGET_BASE = 32'h024;
parameter GFX_TARGET_SIZE = 32'h028;
parameter GFX_TEX0_BASE = 32'h02c;
parameter GFX_TEX0_SIZE = 32'h030;
parameter GFX_ALPHA = 32'h034;
parameter GFX_COLORKEY = 32'h038;
 
parameter GFX_CTRL_CD8 = 32'h00000000; /* Color Depth 8 */
parameter GFX_CTRL_CD16 = 32'h00000001; /* Color Depth 16 */
parameter GFX_CTRL_CD24 = 32'h00000002; /* Color Depth 24 */ // Not supported!
parameter GFX_CTRL_CD32 = 32'h00000003; /* Color Depth 32 */
parameter GFX_CTRL_CDMASK = 32'h00000003; /* All color depth bits */
parameter GFX_TEXTURE_ENABLE = 32'h00000004; /* Enable Texture Reads */
parameter GFX_BLEND_ENABLE = 32'h00000008; /* Enable Alpha Blending */
parameter GFX_COLORKEY_ENABLE = 32'h00000010; /* Enable Colorkeying */
 
parameter GFX_CTRL_RECT = 32'h00000100; /* Put rect */
parameter GFX_CTRL_LINE = 32'h00000200; /* Put line */
 
 
initial begin
$dumpfile("gfx.vcd");
$dumpvars(0,gfx_bench);
 
// init values
wb_clk_i = 0;
wb_rst_i = 1;
wbm_write_ack_i = 0;
wbm_read_ack_i = 0;
wbm_write_err_i = 0;
wbm_read_err_i = 0;
wbs_cyc_i = 0;
wbs_cti_i = 0;
wbs_bte_i = 0;
wbs_adr_i = 0;
wbs_sel_i = 4'b1111;
wbs_dat_i = 0;
 
// Can be high all the time
wbs_we_i = 1;
wbs_stb_i = 1;
 
// wbm_read_dat_i = 32'hf18ff18f;
 
// Set the texture read pixel
wbm_read_dat_i = 32'h00000000;
 
// Finish the reset of the component
#2 wb_rst_i = 0;
 
 
// Initialize color register
#2 wbs_cyc_i = 1;
wbs_adr_i = GFX_COLOR;
wbs_dat_i = 32'h12345671;
#4 wbs_cyc_i = 0;
 
// Initialize traget base
#2 wbs_cyc_i = 1;
wbs_dat_i = GFX_VMEM;
wbs_adr_i = GFX_TARGET_BASE;
#4 wbs_cyc_i = 0;
 
// oc_gfx_set_videomode(640, 480, 16);
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h028001e0; // (640 << 16) | 480
wbs_adr_i = GFX_TEX0_SIZE;
#4 wbs_cyc_i = 0;
 
// Set 16 bit color depth
#2 wbs_cyc_i = 1;
wbs_dat_i = GFX_CTRL_CD16;
wbs_adr_i = GFX_CTRL;
#4 wbs_cyc_i = 0;
 
// Enable colorkey
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h0000F18F; // pink color
wbs_adr_i = GFX_COLORKEY;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = GFX_COLORKEY_ENABLE | GFX_CTRL_CD16;
wbs_adr_i = GFX_CTRL;
#4 wbs_cyc_i = 0;
 
// set cliparea
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h00000000; // (0 << 16) | 0
wbs_adr_i = GFX_CLIP_PIXEL0; // Clip Pixel 0
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h028001e0; // (640 << 16) | 480
wbs_adr_i = GFX_CLIP_PIXEL1; // Clip Pixel 1
#4 wbs_cyc_i = 0;
 
// oc_gfx_enable_tex0(1)
#2 wbs_cyc_i = 1;
wbs_dat_i = GFX_TEXTURE_ENABLE | GFX_COLORKEY_ENABLE | GFX_CTRL_CD16;
wbs_adr_i = GFX_CTRL;
#4 wbs_cyc_i = 0;
 
// oc_gfx_bind_tex0(0x01f00000, 10, 10)
#2 wbs_cyc_i = 1;
wbs_dat_i = GFX_VMEM;
wbs_adr_i = GFX_TEX0_BASE;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h000a000a; // (10 << 16) | 10
wbs_adr_i = GFX_TEX0_SIZE;
#4 wbs_cyc_i = 0;
 
// oc_gfx_rect(110, 110, 115, 115, 0xf800f800);
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h006e006e; // (110 << 16) | 110
wbs_adr_i = GFX_DEST_PIXEL0;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h00780073; // (115 << 16) | 115
wbs_adr_i = GFX_DEST_PIXEL1;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'hf800f800; // Red
wbs_adr_i = GFX_COLOR;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = GFX_CTRL_RECT | GFX_TEXTURE_ENABLE | GFX_COLORKEY_ENABLE | GFX_CTRL_CD16;
wbs_adr_i = GFX_CTRL;
#4 wbs_cyc_i = 0;
 
// After a while, set every pixel read to the color key (demonstrates that colorkeyed pixels are not written)
#200 wbm_read_dat_i = 32'hf18ff18f;
 
// TODO: Demonstrate alpha blending
 
/*
 
wbm_read_dat_i = #40 32'hffffffff;
 
 
// oc_gfx_rect(110, 110, 115, 115, 0xf800f800);
#200 wbs_cyc_i = 1;
wbs_dat_i = 32'h006e006e; // (110 << 16) | 110
wbs_adr_i = GFX_DEST_PIXEL0;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h00730073; // (115 << 16) | 115
wbs_adr_i = GFX_DEST_PIXEL1;
#4 wbs_cyc_i = 0;
 
 
// set cliparea
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h00700070; // (112 << 16) | 112
wbs_adr_i = GFX_CLIP_PIXEL0;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h00720072; // (114 << 16) | 114
wbs_adr_i = GFX_CLIP_PIXEL1;
#4 wbs_cyc_i = 0;
 
 
#2 wbs_cyc_i = 1;
wbs_dat_i = GFX_CTRL_RECT | GFX_TEXTURE_ENABLE | GFX_CTRL_CD16;
wbs_adr_i = GFX_CTRL;
#4 wbs_cyc_i = 0;
 
*/
 
// Draw a bunch of lines
 
//draw line ############### 1
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h00040004; // (110 << 16) | 110
wbs_adr_i = GFX_DEST_PIXEL0;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h00080006; // (115 << 16) | 115
wbs_adr_i = GFX_DEST_PIXEL1;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
wbs_adr_i = GFX_CTRL;
#4 wbs_cyc_i = 0;
//#########################
 
//draw line ############### 2
#10 wbs_cyc_i = 1;
wbs_dat_i = 32'h00040004; // (110 << 16) | 110
wbs_adr_i = GFX_DEST_PIXEL0;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h00060008; // (115 << 16) | 115
wbs_adr_i = GFX_DEST_PIXEL1;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
wbs_adr_i = GFX_CTRL;
#4 wbs_cyc_i = 0;
//#########################
 
//draw line ############### 3
#10 wbs_cyc_i = 1;
wbs_dat_i = 32'h00040004; // (110 << 16) | 110
wbs_adr_i = GFX_DEST_PIXEL0;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h00020008; // (115 << 16) | 115
wbs_adr_i = GFX_DEST_PIXEL1;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
wbs_adr_i = GFX_CTRL;
#4 wbs_cyc_i = 0;
//#########################
 
//draw line ############### 4
#10 wbs_cyc_i = 1;
wbs_dat_i = 32'h00040004; // (110 << 16) | 110
wbs_adr_i = GFX_DEST_PIXEL0;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h00000006; // (115 << 16) | 115
wbs_adr_i = GFX_DEST_PIXEL1;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
wbs_adr_i = GFX_CTRL;
#4 wbs_cyc_i = 0;
//#########################
 
//draw line ############### 5
#10 wbs_cyc_i = 1;
wbs_dat_i = 32'h00040004; // (110 << 16) | 110
wbs_adr_i = GFX_DEST_PIXEL0;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h00000002; // (115 << 16) | 115
wbs_adr_i = GFX_DEST_PIXEL1;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
wbs_adr_i = GFX_CTRL;
#4 wbs_cyc_i = 0;
//#########################
 
//draw line ############### 6
#10 wbs_cyc_i = 1;
wbs_dat_i = 32'h00040004; // (110 << 16) | 110
wbs_adr_i = GFX_DEST_PIXEL0;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h00020000; // (115 << 16) | 115
wbs_adr_i = GFX_DEST_PIXEL1;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
wbs_adr_i = GFX_CTRL;
#4 wbs_cyc_i = 0;
//#########################
 
//draw line ############### 7
#10 wbs_cyc_i = 1;
wbs_dat_i = 32'h00040004; // (110 << 16) | 110
wbs_adr_i = GFX_DEST_PIXEL0;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h00060000; // (115 << 16) | 115
wbs_adr_i = GFX_DEST_PIXEL1;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
wbs_adr_i = GFX_CTRL;
#4 wbs_cyc_i = 0;
//#########################
 
//draw line ############### 8
#10 wbs_cyc_i = 1;
wbs_dat_i = 32'h00040004; // (110 << 16) | 110
wbs_adr_i = GFX_DEST_PIXEL0;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = 32'h00080002; // (115 << 16) | 115
wbs_adr_i = GFX_DEST_PIXEL1;
#4 wbs_cyc_i = 0;
 
#2 wbs_cyc_i = 1;
wbs_dat_i = GFX_CTRL_LINE | GFX_CTRL_CD16;
wbs_adr_i = GFX_CTRL;
#4 wbs_cyc_i = 0;
//#########################
 
#10000 $finish;
end
 
// Set up ack behaviour from memory circuits
always @(posedge wb_clk_i)
begin
wbm_write_ack_i <= #1 wbm_write_cyc_o & !wbm_write_ack_i;
wbm_read_ack_i <= #1 wbm_read_cyc_o & !wbm_read_ack_i;
end
 
// Set up clock
always begin
#1 wb_clk_i = ~wb_clk_i;
end
 
// Instansiate module
gfx_top top(
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_inta_o (wb_inta_o),
// Wishbone master signals (interfaces with video memory)
.wbm_write_cyc_o (wbm_write_cyc_o),
.wbm_write_stb_o (wbm_write_stb_o),
.wbm_write_cti_o (wbm_write_cti_o),
.wbm_write_bte_o (wbm_write_bte_o),
.wbm_write_we_o (wbm_write_we_o),
.wbm_write_adr_o (wbm_write_adr_o),
.wbm_write_sel_o (wbm_write_sel_o),
.wbm_write_ack_i (wbm_write_ack_i),
.wbm_write_err_i (wbm_write_err_i),
.wbm_write_dat_o (wbm_write_dat_o),
// Wishbone master signals (interfaces with video memory)
.wbm_read_cyc_o (wbm_read_cyc_o),
.wbm_read_stb_o (wbm_read_stb_o),
.wbm_read_cti_o (wbm_read_cti_o),
.wbm_read_bte_o (wbm_read_bte_o),
.wbm_read_we_o (wbm_read_we_o),
.wbm_read_adr_o (wbm_read_adr_o),
.wbm_read_sel_o (wbm_read_sel_o),
.wbm_read_ack_i (wbm_read_ack_i),
.wbm_read_err_i (wbm_read_err_i),
.wbm_read_dat_i (wbm_read_dat_i),
// Wishbone slave signals (interfaces with main bus/CPU)
.wbs_cyc_i (wbs_cyc_i),
.wbs_stb_i (wbs_stb_i),
.wbs_cti_i (wbs_cti_i),
.wbs_bte_i (wbs_bte_i),
.wbs_we_i (wbs_we_i),
.wbs_adr_i (wbs_adr_i),
.wbs_sel_i (wbs_sel_i),
.wbs_ack_o (wbs_ack_o),
.wbs_err_o (wbs_err_o),
.wbs_dat_i (wbs_dat_i),
.wbs_dat_o (wbs_dat_o)
);
 
endmodule
/gfx/line_bench.v
0,0 → 1,114
`include "../../../rtl/verilog/gfx/gfx_line.v"
 
module line_bench();
 
reg clk_i;
reg rst_i;
 
reg [15:0] pixel0_x_i;
reg [15:0] pixel1_x_i;
reg [15:0] pixel0_y_i;
reg [15:0] pixel1_y_i;
 
reg [15:0] delta_major_i;
reg [15:0] delta_minor_i;
 
reg draw_line_i;
reg read_pixel_i;
reg x_major_i;
reg minor_slope_positive_i;
 
wire busy_o;
 
wire [15:0] major_o;
wire [15:0] minor_o;
 
initial begin
$dumpfile("line.vcd");
$dumpvars(0,line_bench);
draw_line_i = 0;
clk_i = 0;
rst_i = 1;
 
// timing
#2 rst_i = 0;
 
pixel0_x_i = 10;
pixel0_y_i = 10;
pixel1_x_i = 20;
delta_major_i = 2;
delta_minor_i = 2;
#2 draw_line_i = 1;
#2 draw_line_i = 0;
 
#30 rst_i = 1;
#2 rst_i = 0;
pixel0_x_i = 10;
pixel0_y_i = 10;
pixel1_x_i = 20;
delta_major_i = 4;
delta_minor_i = 2;
#2 draw_line_i = 1;
#2 draw_line_i = 0;
 
#30 pixel0_x_i = 10;
pixel0_y_i = 10;
pixel1_x_i = 20;
delta_major_i = 6;
delta_minor_i = 2;
#2 draw_line_i = 1;
#2 draw_line_i = 0;
 
 
#30 pixel0_x_i = 10;
pixel0_y_i = 10;
pixel1_x_i = 20;
delta_major_i = 8;
delta_minor_i = 2;
#2 draw_line_i = 1;
#2 draw_line_i = 0;
 
#30 pixel0_x_i = 10;
pixel0_y_i = 10;
pixel1_x_i = 20;
delta_major_i = 16;
delta_minor_i = 2;
#2 draw_line_i = 1;
#2 draw_line_i = 0;
 
#30 pixel0_x_i = 10;
pixel0_y_i = 10;
pixel1_x_i = 20;
delta_major_i = 32;
delta_minor_i = 2;
#2 draw_line_i = 1;
#2 draw_line_i = 0;
 
#1000 $finish;
end
 
 
always begin
#1 clk_i = ~clk_i;
end
 
bresenham_line bresenham(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.pixel0_x_i ( pixel0_x_i ),
.pixel0_y_i ( pixel0_y_i ),
.pixel1_x_i ( pixel1_x_i ),
.pixel1_y_i ( pixel1_y_i ),
.x_major_i ( x_major_i ),
.minor_slope_positive_i ( minor_slope_positive_i ),
.delta_minor_i ( delta_minor_i ),
.delta_major_i ( delta_major_i ),
.draw_line_i ( draw_line_i ),
.read_pixel_i ( read_pixel_i ),
.busy_o ( busy_o ),
.major_o ( major_o ),
.minor_o ( minor_o )
);
 
endmodule
/gfx/gtkwave_blender.sav
0,0 → 1,69
[timestart] 0
[size] 1024 744
[pos] -1 -1
*-5.018312 36 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] blender_bench.
@200
-sync
@28
blender_bench.clk_i
blender_bench.rst_i
@200
-input
@28
blender_bench.color_depth_i[1:0]
blender_bench.blending_enable_i
@22
blender_bench.alpha_i[7:0]
blender_bench.target_base_i[31:2]
blender_bench.target_size_x_i[15:0]
blender_bench.target_size_y_i[15:0]
blender_bench.x_counter_i[15:0]
@c00022
blender_bench.y_counter_i[15:0]
@28
(0)blender_bench.y_counter_i[15:0]
(1)blender_bench.y_counter_i[15:0]
(2)blender_bench.y_counter_i[15:0]
(3)blender_bench.y_counter_i[15:0]
(4)blender_bench.y_counter_i[15:0]
(5)blender_bench.y_counter_i[15:0]
(6)blender_bench.y_counter_i[15:0]
(7)blender_bench.y_counter_i[15:0]
(8)blender_bench.y_counter_i[15:0]
(9)blender_bench.y_counter_i[15:0]
(10)blender_bench.y_counter_i[15:0]
(11)blender_bench.y_counter_i[15:0]
(12)blender_bench.y_counter_i[15:0]
(13)blender_bench.y_counter_i[15:0]
(14)blender_bench.y_counter_i[15:0]
(15)blender_bench.y_counter_i[15:0]
@1401200
-group_end
@28
blender_bench.pixel_write_enable_i
blender_bench.ack_i
@200
-output
@22
blender_bench.pixel_color_i[31:0]
blender_bench.pixel_color_o[31:0]
blender_bench.pixel_x_o[15:0]
blender_bench.pixel_y_o[15:0]
@28
blender_bench.pixel_write_enable_o
blender_bench.ack_o
@200
-wbm
@22
blender_bench.target_data_i[31:0]
@28
blender_bench.target_request_o
blender_bench.target_ack_i
@22
blender_bench.target_addr_o[31:2]
blender_bench.target_sel_o[3:0]
@28
blender_bench.wbm_busy_i
[pattern_trace] 1
[pattern_trace] 0
/gfx/gtkwave_wbm_w.sav
0,0 → 1,25
[timestart] 0
[size] 1366 744
[pos] -1 -1
*-14.000000 26370 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] wbm_w_bench.
@28
wbm_w_bench.wbm_w.clk_i
wbm_w_bench.wbm_w.rst_i
@200
-input
@28
wbm_w_bench.wbm_w.write_i
@200
-regs
@29
wbm_w_bench.wbm_w.ready_r
@28
wbm_w_bench.wbm_w.ready_o
@200
-wbm
@28
wbm_w_bench.wbm_w.cyc_o
wbm_w_bench.wbm_w.ack_i
[pattern_trace] 1
[pattern_trace] 0
/gfx/gtkwave_color.sav
0,0 → 1,27
[timestart] 0
[size] 1024 744
[pos] -1 -1
*-4.882107 37 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] color_bench.
@28
color_bench.clk_i
color_bench.color_depth_i[1:0]
@200
-Color to mem
@22
color_bench.color_i[31:0]
@28
color_bench.x_lsb_i[1:0]
@22
color_bench.mem_sel_o[3:0]
color_bench.mem_o[31:0]
@200
-Mem to color
@29
color_bench.x_lsb_i[1:0]
@22
color_bench.mem_i[31:0]
color_bench.col_sel_o[3:0]
color_bench.color_o[31:0]
[pattern_trace] 1
[pattern_trace] 0
/gfx/gtkwave_render.sav
0,0 → 1,38
[timestart] 0
[size] 1366 744
[pos] -1 -1
*-5.235123 39 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] render_bench.
[treeopen] render_bench.render.
@28
render_bench.clk_i
render_bench.rst_i
@200
-input
@28
render_bench.color_depth_i[1:0]
@22
render_bench.color_i[31:0]
render_bench.pixel_x_i[15:0]
render_bench.pixel_y_i[15:0]
render_bench.target_base_i[31:2]
render_bench.target_size_x_i[15:0]
render_bench.target_size_y_i[15:0]
@200
-pipeline
@28
render_bench.write_i
render_bench.render.write_request
@29
render_bench.ready_i
@28
render_bench.ready_o
render_bench.write_o
@200
-output
@22
render_bench.render_addr_o[31:2]
render_bench.render_dat_o[31:0]
render_bench.render_sel_o[3:0]
[pattern_trace] 1
[pattern_trace] 0
/gfx/wbm_arbiter_bench.v
0,0 → 1,89
`include "../../../rtl/verilog/gfx/gfx_wbm_read_arbiter.v"
 
module arbiter_bench();
 
// Clock
reg clk_i; // master clock reg
 
// Interface against the wbm read module
wire master_busy_o;
wire read_request_o;
wire [31:2] addr_o;
wire [3:0] sel_o;
reg [31:0] dat_i;
reg ack_i;
// Interface against masters (fragment processor)
reg m0_read_request_i;
reg [31:2] m0_addr_i;
reg [3:0] m0_sel_i;
wire [31:0] m0_dat_o;
wire m0_ack_o;
// Interface against masters (blender)
reg m1_read_request_i;
reg [31:2] m1_addr_i;
reg [3:0] m1_sel_i;
wire [31:0] m1_dat_o;
wire m1_ack_o;
 
initial begin
$dumpfile("arbiter.vcd");
$dumpvars(0,arbiter_bench);
 
// init values
clk_i = 0;
dat_i = 32'h12345678;
ack_i = 0;
m0_read_request_i = 0;
m0_addr_i = 10;
m0_sel_i = 0;
m1_read_request_i = 0;
m1_addr_i = 20;
m1_sel_i = 8;
 
#10 m0_read_request_i = 1;
#10 m0_read_request_i = 0;
#10 m1_read_request_i = 1;
#10 m1_read_request_i = 0;
 
#10 m1_read_request_i = 1;
m0_read_request_i = 1;
#10 m1_read_request_i = 0;
#10 m0_read_request_i = 0;
 
//timing
 
#100 $finish;
end
 
always @(posedge clk_i)
begin
ack_i <= #1 read_request_o;
end
 
always begin
#1 clk_i = ~clk_i;
end
 
gfx_wbm_read_arbiter arbiter(
.master_busy_o (master_busy_o),
// Interface against the wbm read module
.read_request_o (read_request_o),
.addr_o (addr_o),
.sel_o (sel_o),
.dat_i (dat_i),
.ack_i (ack_i),
// Interface against masters (fragment processor)
.m0_read_request_i (m0_read_request_i),
.m0_addr_i (m0_addr_i),
.m0_sel_i (m0_sel_i),
.m0_dat_o (m0_dat_o),
.m0_ack_o (m0_ack_o),
// Interface against masters (blender)
.m1_read_request_i (m1_read_request_i),
.m1_addr_i (m1_addr_i),
.m1_sel_i (m1_sel_i),
.m1_dat_o (m1_dat_o),
.m1_ack_o (m1_ack_o)
);
 
endmodule
/gfx/raster_bench.v
0,0 → 1,116
`include "../../../rtl/verilog/gfx/gfx_rasterizer.v"
`include "../../../rtl/verilog/gfx/gfx_line.v"
 
module raster_bench();
 
reg clk_i;
reg rst_i;
 
reg ack_i;
wire ack_o;
 
reg rect_write_i;
reg line_write_i;
reg texture_enable_i;
 
reg [15:0] src_pixel0_x_i;
reg [15:0] src_pixel0_y_i;
reg [15:0] src_pixel1_x_i;
reg [15:0] src_pixel1_y_i;
reg [15:0] dest_pixel0_x_i;
reg [15:0] dest_pixel0_y_i;
reg [15:0] dest_pixel1_x_i;
reg [15:0] dest_pixel1_y_i;
reg [15:0] clip_pixel0_x_i;
reg [15:0] clip_pixel0_y_i;
reg [15:0] clip_pixel1_x_i;
reg [15:0] clip_pixel1_y_i;
 
 
reg [15:0] target_size_x_i;
reg [15:0] target_size_y_i;
 
wire [15:0] x_counter_o;
wire [15:0] y_counter_o;
wire [15:0] u_o;
wire [15:0] v_o;
wire write_o;
 
 
initial begin
$dumpfile("raster.vcd");
$dumpvars(0,raster_bench);
 
// init values
clk_i = 0;
rst_i = 1;
ack_i = 0;
rect_write_i = 0;
line_write_i = 0;
dest_pixel0_x_i = 5;
dest_pixel0_y_i = 5;
dest_pixel1_x_i = 10;
dest_pixel1_y_i = 8;
src_pixel0_x_i = 5;
src_pixel0_y_i = 5;
src_pixel1_x_i = 10;
src_pixel1_y_i = 10;
clip_pixel0_x_i = 5;
clip_pixel0_y_i = 5;
clip_pixel1_x_i = 10;
clip_pixel1_y_i = 10;
target_size_x_i = 640;
target_size_y_i = 480;
texture_enable_i = 0;
 
 
//timing
#4 rst_i = 0;
#2 rect_write_i = 1;
#2 rect_write_i = 0;
 
#10 line_write_i = 1;
#2 line_write_i = 0;
// end sim
 
#100 $finish;
end
 
always begin
#1 clk_i = ~clk_i;
end
 
always @(posedge clk_i)
begin
ack_i <= #1 write_o;
end
 
gfx_rasterizer raster(
.clk_i (clk_i),
.rst_i (rst_i),
.ack_i (ack_i),
.ack_o (ack_o),
.rect_write_i (rect_write_i),
.line_write_i (line_write_i),
.texture_enable_i (texture_enable_i),
.src_pixel0_x_i (src_pixel0_x_i),
.src_pixel0_y_i (src_pixel0_y_i),
.src_pixel1_x_i (src_pixel1_x_i),
.src_pixel1_y_i (src_pixel1_y_i),
.dest_pixel0_x_i (dest_pixel0_x_i),
.dest_pixel0_y_i (dest_pixel0_y_i),
.dest_pixel1_x_i (dest_pixel1_x_i),
.dest_pixel1_y_i (dest_pixel1_y_i),
.clip_pixel0_x_i (clip_pixel0_x_i),
.clip_pixel0_y_i (clip_pixel0_y_i),
.clip_pixel1_x_i (clip_pixel1_x_i),
.clip_pixel1_y_i (clip_pixel1_y_i),
.target_size_x_i (target_size_x_i),
.target_size_y_i (target_size_y_i),
.x_counter_o (x_counter_o),
.y_counter_o (y_counter_o),
.u_o (u_o),
.v_o (v_o),
.write_o (write_o)
);
endmodule
/gfx/gtkwave_gfx.sav
0,0 → 1,219
[*]
[*] GTKWave Analyzer v3.3.33 (w)1999-2012 BSI
[*] Wed Mar 21 10:38:17 2012
[*]
[dumpfile] "/home/maiden/Creative/Svn/orgfx/bench/verilog/gfx/gfx.vcd"
[dumpfile_mtime] "Wed Mar 21 10:34:44 2012"
[dumpfile_size] 371596
[savefile] "/home/maiden/Creative/Svn/orgfx/bench/verilog/gfx/gtkwave_gfx.sav"
[timestart] 0
[size] 1280 1000
[pos] -1 -1
*-17.000000 98900 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] gfx_bench.
[treeopen] gfx_bench.top.
[treeopen] gfx_bench.top.fp0.
[treeopen] gfx_bench.top.rasterizer0.
[treeopen] gfx_bench.top.wb_databus.
[sst_width] 225
[signals_width] 270
[sst_expanded] 1
[sst_vpaned_height] 301
@200
-colorkey
@22
gfx_bench.top.colorkey_reg[31:0]
@28
gfx_bench.top.colorkey_enable_reg
gfx_bench.top.fp0.transparent_pixel
gfx_bench.top.fp0.write_o
gfx_bench.top.fp0.state[1:0]
@200
-ack
@28
gfx_bench.top.wbm_write_ack_i
gfx_bench.top.wbm_writer.cyc_o
gfx_bench.top.wbmwriter_render_ack
gfx_bench.top.render_blender_ack
gfx_bench.top.renderer.write_o
gfx_bench.top.blender_fragment_ack
gfx_bench.top.blender0.write_o
gfx_bench.top.blender0.state[1:0]
gfx_bench.top.fragment_raster_ack
gfx_bench.top.fp0.write_o
gfx_bench.top.raster_wbs_pipeline_ack
gfx_bench.top.rasterizer0.write_o
@200
-Wishbone
@28
gfx_bench.wb_clk_i
gfx_bench.wb_rst_i
@200
-Wishbone slave
@22
gfx_bench.top.wb_databus.status_reg[31:0]
@28
gfx_bench.top.wb_databus.instruction_fifo_rreq
gfx_bench.top.wb_databus.instruction_fifo_wreq
gfx_bench.top.wb_databus.state
@22
gfx_bench.top.wb_databus.instruction_fifo_q_data[31:0]
gfx_bench.top.wb_databus.control_reg[31:0]
@28
gfx_bench.wbs_cyc_i
@22
gfx_bench.wbs_adr_i[31:0]
gfx_bench.wbs_dat_i[31:0]
@200
-REGS
@22
gfx_bench.top.renderer.target_base_i[31:2]
@200
-fifo
@22
gfx_bench.top.wb_databus.instruction_fifo.data_in[41:0]
gfx_bench.top.wb_databus.instruction_fifo.data_out[41:0]
@28
gfx_bench.top.wb_databus.instruction_fifo.deq
gfx_bench.top.wb_databus.instruction_fifo.enq
gfx_bench.top.wb_databus.instruction_fifo.full
gfx_bench.top.wb_databus.instruction_fifo.is_empty
gfx_bench.top.wb_databus.instruction_fifo.is_full
gfx_bench.top.wb_databus.instruction_fifo.next_full
gfx_bench.top.wb_databus.instruction_fifo.reset
gfx_bench.top.wb_databus.instruction_fifo.valid_out
@200
-Wishbone reader
@28
gfx_bench.wbm_read_cyc_o
gfx_bench.wbm_read_ack_i
@22
gfx_bench.wbm_read_adr_o[31:0]
gfx_bench.wbm_read_dat_i[31:0]
gfx_bench.wbm_read_sel_o[3:0]
@28
gfx_bench.top.wbm_reader.read_request_i
@200
-Rasterizer
@24
gfx_bench.top.rasterizer0.clip_pixel0_x_i[15:0]
gfx_bench.top.rasterizer0.clip_pixel0_y_i[15:0]
@c00024
gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
@28
(0)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
(1)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
(2)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
(3)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
(4)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
(5)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
(6)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
(7)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
(8)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
(9)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
(10)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
(11)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
(12)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
(13)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
(14)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
(15)gfx_bench.top.rasterizer0.clip_pixel1_x_i[15:0]
@1401200
-group_end
@24
gfx_bench.top.rasterizer0.clip_pixel1_y_i[15:0]
gfx_bench.top.rasterizer0.dest_pixel0_x_i[15:0]
gfx_bench.top.rasterizer0.dest_pixel0_y_i[15:0]
gfx_bench.top.rasterizer0.dest_pixel1_x_i[15:0]
gfx_bench.top.rasterizer0.dest_pixel1_y_i[15:0]
gfx_bench.top.rasterizer0.x_counter_o[15:0]
gfx_bench.top.rasterizer0.y_counter_o[15:0]
@28
gfx_bench.top.rasterizer0.state[2:0]
gfx_bench.top.rasterizer0.bresenham.minor_slope_positive_i
gfx_bench.top.rasterizer0.request_next_pixel
@200
-line
@28
gfx_bench.top.rasterizer0.bresenham.busy_o
gfx_bench.top.rasterizer0.bresenham.draw_line_i
@420
gfx_bench.top.rasterizer0.bresenham.eps[31:0]
@24
gfx_bench.top.rasterizer0.bresenham.eps_delta_minor[31:0]
gfx_bench.top.rasterizer0.bresenham.pixel0_x_i[15:0]
gfx_bench.top.rasterizer0.bresenham.pixel0_y_i[15:0]
gfx_bench.top.rasterizer0.bresenham.pixel1_x_i[15:0]
gfx_bench.top.rasterizer0.bresenham.pixel1_y_i[15:0]
@28
gfx_bench.top.rasterizer0.bresenham.x_major_i
gfx_bench.top.rasterizer0.bresenham.minor_slope_positive_i
@24
gfx_bench.top.rasterizer0.bresenham.major_goal[15:0]
gfx_bench.top.rasterizer0.bresenham.major_o[15:0]
gfx_bench.top.rasterizer0.bresenham.minor_o[15:0]
@28
gfx_bench.top.rasterizer0.bresenham.read_pixel_i
gfx_bench.top.rasterizer0.bresenham.rst_i
@200
-Fragment
@28
gfx_bench.top.fp0.write_i
@22
gfx_bench.top.fp0.pixel_x_o[15:0]
gfx_bench.top.fp0.pixel_y_o[15:0]
@200
-Blender
@22
gfx_bench.top.blender0.pixel_x_o[15:0]
gfx_bench.top.blender0.pixel_y_o[15:0]
@200
-Renderer
@22
gfx_bench.top.renderer.pixel_x_i[15:0]
gfx_bench.top.renderer.pixel_y_i[15:0]
gfx_bench.top.wbs_raster_clip_pixel0_x[15:0]
gfx_bench.top.wbs_raster_clip_pixel0_y[15:0]
@24
gfx_bench.top.wbs_raster_clip_pixel1_x[15:0]
gfx_bench.top.wbs_raster_clip_pixel1_y[15:0]
@200
-Wishbone writer
@28
gfx_bench.wbm_write_cyc_o
gfx_bench.wbm_write_ack_i
gfx_bench.top.wbm_writer.write_i
@24
gfx_bench.wbm_write_adr_o[31:0]
@22
gfx_bench.wbm_write_dat_o[31:0]
gfx_bench.wbm_write_sel_o[3:0]
@200
-arbiter
@28
gfx_bench.top.wbm_arbiter.ack_i
gfx_bench.top.wbm_arbiter.m0_ack_o
@29
gfx_bench.top.wbm_arbiter.m1_ack_o
@22
gfx_bench.top.wbm_arbiter.addr_o[31:2]
gfx_bench.top.wbm_arbiter.dat_i[31:0]
gfx_bench.top.wbm_arbiter.m0_addr_i[31:2]
gfx_bench.top.wbm_arbiter.m0_dat_o[31:0]
@28
gfx_bench.top.wbm_arbiter.m0_read_request_i
@22
gfx_bench.top.wbm_arbiter.m0_sel_i[3:0]
gfx_bench.top.wbm_arbiter.m1_addr_i[31:2]
gfx_bench.top.wbm_arbiter.m1_dat_o[31:0]
@28
gfx_bench.top.wbm_arbiter.m1_read_request_i
@22
gfx_bench.top.wbm_arbiter.m1_sel_i[3:0]
@28
gfx_bench.top.wbm_arbiter.master_busy_o
gfx_bench.top.wbm_arbiter.master_sel[1:0]
gfx_bench.top.wbm_arbiter.read_request_o
@22
gfx_bench.top.wbm_arbiter.sel_o[3:0]
[pattern_trace] 1
[pattern_trace] 0
/gfx/fragment_bench.v
0,0 → 1,123
`include "../../../rtl/verilog/gfx/gfx_fragment_processor.v"
`include "../../../rtl/verilog/gfx/gfx_color.v"
 
module fragment_bench();
reg clk_i;
reg rst_i;
 
reg [7:0] global_alpha_i;
 
// from raster
reg [15:0] x_counter_i;
reg [15:0] y_counter_i;
reg [15:0] u_i;
reg [15:0] v_i;
reg [31:0] pixel_color_i;
reg write_i;
reg ack_i;
 
//to blender
wire [15:0] pixel_x_o;
wire [15:0] pixel_y_o;
wire [31:0] pixel_color_o;
wire [7:0] pixel_alpha_o;
wire write_o;
wire ack_o;
 
// to/from wishbone master read
reg texture_ack_i;
reg [31:0] texture_data_i;
wire [31:2] texture_addr_o;
wire [3:0] texture_sel_o;
wire texture_request_o;
 
// from wishbone slave
reg texture_enable_i;
reg [31:2] tex0_base_i;
reg [15:0] tex0_size_x_i;
reg [15:0] tex0_size_y_i;
reg [1:0] color_depth_i;
reg colorkey_enable_i;
reg [31:0] colorkey_i;
 
initial begin
$dumpfile("fragment.vcd");
$dumpvars(0,fragment_bench);
 
// init values
clk_i = 0;
rst_i = 1;
write_i = 0;
texture_enable_i = 0;
color_depth_i = 2'b01;
ack_i = 0;
global_alpha_i = 8'hff;
pixel_color_i = 32'h12345678;
tex0_base_i = 32'h12341234;
tex0_size_x_i = 12;
tex0_size_y_i = 10;
u_i = 0;
v_i = 0;
x_counter_i = 0;
y_counter_i = 0;
texture_data_i = 32'hf800ffff;
colorkey_enable_i = 0;
colorkey_i = 32'h00000000;
// texture_ack_i = 0;
 
//timing
#4 rst_i = 0;
#2 write_i = 1;
#2 write_i = 0;
#6 texture_enable_i = 1;
// #4 texture_ack_i = 1;
// #2 texture_ack_i = 0;
#40 write_i = 1;
#2 write_i = 0;
// #8 ack_i = 0;
// #16 ack_i = 1;
// end sim
#100 $finish;
end
 
always @(posedge clk_i)
begin
ack_i <= #1 write_o;
texture_ack_i <= #1 texture_request_o;
end
 
always begin
#1 clk_i = ~clk_i;
end
 
gfx_fragment_processor fragment(
.clk_i (clk_i),
.rst_i (rst_i),
.global_alpha_i (global_alpha_i),
.x_counter_i (x_counter_i),
.y_counter_i (y_counter_i),
.u_i (u_i),
.v_i (v_i),
.pixel_color_i (pixel_color_i),
.write_i (write_i),
.ack_i (ack_i),
.pixel_x_o (pixel_x_o),
.pixel_y_o (pixel_y_o),
.pixel_color_o (pixel_color_o),
.pixel_alpha_o (pixel_alpha_o),
.write_o (write_o),
.ack_o (ack_o),
.texture_ack_i (texture_ack_i),
.texture_data_i (texture_data_i),
.texture_addr_o (texture_addr_o),
.texture_sel_o (texture_sel_o),
.texture_request_o(texture_request_o),
.texture_enable_i (texture_enable_i),
.tex0_base_i (tex0_base_i),
.tex0_size_x_i (tex0_size_x_i),
.tex0_size_y_i (tex0_size_y_i),
.color_depth_i (color_depth_i),
.colorkey_enable_i(colorkey_enable_i),
.colorkey_i (colorkey_i)
);
endmodule
/gfx/renderer_bench.v
0,0 → 1,89
`include "../../../rtl/verilog/gfx/gfx_renderer.v"
`include "../../../rtl/verilog/gfx/gfx_color.v"
 
module render_bench();
reg clk_i;
reg rst_i;
 
// Render target information, used for checking out of bounds and stride when writing pixels
reg [31:2] target_base_i;
reg [15:0] target_size_x_i;
reg [15:0] target_size_y_i;
 
reg [1:0] color_depth_i;
 
reg [15:0] pixel_x_i;
reg [15:0] pixel_y_i;
reg [31:0] color_i;
 
reg write_i;
wire write_o;
 
// wire registers connected to the wbm
wire [31:2] render_addr_o;
wire [3:0] render_sel_o;
wire [31:0] render_dat_o;
 
// TODO add ack signals
wire ack_o;
reg ack_i;
 
 
initial begin
$dumpfile("render.vcd");
$dumpvars(0,render_bench);
 
// init values
clk_i = 1;
rst_i = 1;
target_base_i = 0;
target_size_x_i = 640;
target_size_y_i = 480;
color_depth_i = 2'b01;
pixel_x_i = 4;
pixel_y_i = 2;
color_i = 0;
write_i = 0;
ack_i = 0;
 
//timing
#4 rst_i =0;
#16 write_i = 1;
#2 write_i = 0;
 
 
#2 write_i = 1;
#2 write_i = 0;
 
// end sim
#100 $finish;
end
 
always begin
#1 clk_i = ~clk_i;
end
 
always @(posedge clk_i)
begin
ack_i <= #1 write_o;
end
 
gfx_renderer render(
.clk_i (clk_i),
.rst_i (rst_i),
.target_base_i (target_base_i),
.target_size_x_i (target_size_x_i),
.target_size_y_i (target_size_y_i),
.color_depth_i (color_depth_i),
.pixel_x_i (pixel_x_i),
.pixel_y_i (pixel_y_i),
.color_i (color_i),
.render_addr_o (render_addr_o),
.render_sel_o (render_sel_o),
.render_dat_o (render_dat_o),
.ack_o (ack_o),
.ack_i (ack_i),
.write_i (write_i),
.write_o (write_o)
);
endmodule
/gfx/wbm_r_bench.v
0,0 → 1,81
`include "../../../rtl/verilog/gfx/gfx_wbm_read.v"
 
module wbm_r_bench();
// wishbone signals
reg clk_i; // master clock reg
reg rst_i; // synchronous active high reset
wire cyc_o; // cycle wire
wire stb_o; // strobe output
wire [ 2:0] cti_o; // cycle type id
wire [ 1:0] bte_o; // burst type extension
wire we_o; // write enable wire
wire [31:0] adr_o; // address wire
wire [ 3:0] sel_o; // byte select wires (only 32bits accesses are supported)
reg ack_i; // wishbone cycle acknowledge
reg err_i; // wishbone cycle error
reg [31:0] dat_i; // wishbone data in
 
wire sint_o; // non recoverable error, interrupt host
 
// Renderer stuff
reg read_request_i;
 
reg [31:2] texture_addr_i;
reg [3:0] texture_sel_i;
wire [31:0] texture_dat_o;
wire texture_data_ack;
 
initial begin
$dumpfile("wbm_r.vcd");
$dumpvars(0,wbm_r_bench);
 
// init values
ack_i = 0;
clk_i = 1;
rst_i = 1;
read_request_i = 0;
err_i = 0;
texture_sel_i = 4'hf;
dat_i = 0;
texture_addr_i = 0;
 
//timing
#4 rst_i =0;
#2 read_request_i = 1;
#2 read_request_i = 0;
 
// end sim
#100 $finish;
end
 
always begin
#1 ack_i = !ack_i & cyc_o;
end
 
always begin
#1 clk_i = ~clk_i;
end
 
gfx_wbm_read wbm_r(
// WB signals
.clk_i (clk_i),
.rst_i (rst_i),
.cyc_o (cyc_o),
.stb_o (stb_o),
.cti_o (cti_o),
.bte_o (bte_o),
.we_o (we_o),
.adr_o (adr_o),
.sel_o (sel_o),
.ack_i (ack_i),
.err_i (err_i),
.dat_i (dat_i),
.sint_o (sint_o),
// Control signals
.read_request_i (read_request_i),
.texture_addr_i (texture_addr_i),
.texture_sel_i (texture_sel_i),
.texture_dat_o (texture_dat_o),
.texture_data_ack (texture_data_ack)
);
endmodule
/gfx/timescale.v
0,0 → 1,2
`timescale 1ns / 10ps
 
/gfx/Makefile
0,0 → 1,76
WFLAGS = -Wall -Wno-timescale
 
all: gfx
 
update:
iverilog $(WFLAGS) gfx_bench.v
./a.out
iverilog $(WFLAGS) raster_bench.v
./a.out
iverilog $(WFLAGS) renderer_bench.v
./a.out
iverilog $(WFLAGS) fragment_bench.v
./a.out
iverilog $(WFLAGS) blender_bench.v
./a.out
iverilog $(WFLAGS) wbm_w_bench.v
./a.out
iverilog $(WFLAGS) wbm_r_bench.v
./a.out
iverilog $(WFLAGS) color_bench.v
./a.out
iverilog $(WFLAGS) wbm_arbiter_bench.v
./a.out
iverilog $(WFLAGS) line_bench.v
./a.out
 
gfx:
iverilog $(WFLAGS) gfx_bench.v
./a.out
gtkwave gfx.vcd gtkwave_gfx.sav
 
raster:
iverilog $(WFLAGS) raster_bench.v
./a.out
gtkwave raster.vcd gtkwave_raster.sav
 
render:
iverilog $(WFLAGS) renderer_bench.v
./a.out
gtkwave render.vcd gtkwave_render.sav
 
fragment:
iverilog $(WFLAGS) fragment_bench.v
./a.out
gtkwave fragment.vcd gtkwave_fragment.sav
 
blender:
iverilog $(WFLAGS) blender_bench.v
./a.out
gtkwave blender.vcd gtkwave_blender.sav
 
wbm_w:
iverilog $(WFLAGS) wbm_w_bench.v
./a.out
gtkwave wbm_w.vcd gtkwave_wbm_w.sav
 
wbm_r:
iverilog $(WFLAGS) wbm_r_bench.v
./a.out
gtkwave wbm_r.vcd gtkwave_wbm_r.sav
 
color:
iverilog $(WFLAGS) color_bench.v
./a.out
gtkwave color.vcd gtkwave_color.sav
 
arbiter:
iverilog $(WFLAGS) wbm_arbiter_bench.v
./a.out
gtkwave arbiter.vcd
 
line:
iverilog $(WFLAGS) line_bench.v
./a.out
gtkwave line.vcd line.sav
 
/gfx/blender_bench.v
0,0 → 1,106
`include "../../../rtl/verilog/gfx/gfx_blender.v"
`include "../../../rtl/verilog/gfx/gfx_color.v"
 
module blender_bench();
reg clk_i;
reg rst_i;
 
reg blending_enable_i;
reg [31:2] target_base_i;
reg [15:0] target_size_x_i;
reg [15:0] target_size_y_i;
reg [1:0] color_depth_i;
 
// from fragment
reg [15:0] x_counter_i;
reg [15:0] y_counter_i;
reg [7:0] alpha_i;
reg [31:0] pixel_color_i;
reg write_i;
reg ack_i;
 
// Wbm
reg target_ack_i;
wire [31:2] target_addr_o;
reg [31:0] target_data_i;
wire [3:0] target_sel_o;
wire target_request_o;
reg wbm_busy_i;
 
//to render
wire [15:0] pixel_x_o;
wire [15:0] pixel_y_o;
wire [31:0] pixel_color_o;
wire write_o;
wire ack_o;
 
initial begin
$dumpfile("blender.vcd");
$dumpvars(0,blender_bench);
 
// init values
clk_i = 0;
rst_i = 1;
write_i = 0;
blending_enable_i = 0;
alpha_i = 8'h80;
x_counter_i = 0;
y_counter_i = 0;
wbm_busy_i = 0;
color_depth_i = 2'b01; // 16 bit
target_base_i = 32'h01f00000;
target_size_x_i = 12;
target_size_y_i = 10;
pixel_color_i = 32'h00001234;
target_data_i = 32'h00000000;
ack_i = 0;
 
//timing
#4 rst_i = 0;
#4 write_i = 1;
#2 write_i = 0;
 
#10 pixel_color_i = 32'h00005678;
#10 pixel_color_i = 32'h00009abc;
#10 pixel_color_i = 32'h0000f800;
// end sim
#100 $finish;
end
 
always @(posedge clk_i)
begin
ack_i <= #1 write_o;
target_ack_i <= #1 target_request_o;
end
 
always begin
#1 clk_i = ~clk_i;
end
 
gfx_blender blender(
.clk_i (clk_i),
.rst_i (rst_i),
.blending_enable_i(blending_enable_i),
.target_base_i (target_base_i),
.target_size_x_i (target_size_x_i),
.target_size_y_i (target_size_y_i),
.color_depth_i (color_depth_i),
.x_counter_i (x_counter_i),
.y_counter_i (y_counter_i),
.alpha_i (alpha_i),
.pixel_color_i (pixel_color_i),
.write_i (write_i),
.ack_i (ack_i),
.target_ack_i (target_ack_i),
.target_addr_o (target_addr_o),
.target_data_i (target_data_i),
.target_sel_o (target_sel_o),
.target_request_o (target_request_o),
.wbm_busy_i (wbm_busy_i),
.pixel_x_o (pixel_x_o),
.pixel_y_o (pixel_y_o),
.pixel_color_o (pixel_color_o),
.write_o (write_o),
.ack_o (ack_o)
);
endmodule
/gfx/wbm_w_bench.v
0,0 → 1,85
`include "../../../rtl/verilog/gfx/gfx_wbm_write.v"
`include "../../../rtl/verilog/gfx/basic_fifo.v"
 
module wbm_w_bench();
// wishbone signals
reg clk_i; // master clock reg
reg rst_i; // synchronous active high reset
wire cyc_o; // cycle wire
wire stb_o; // strobe output
wire [ 2:0] cti_o; // cycle type id
wire [ 1:0] bte_o; // burst type extension
wire we_o; // write enable wire
wire [31:0] adr_o; // address wire
wire [ 3:0] sel_o; // byte select wires (only 32bits accesses are supported)
reg ack_i; // wishbone cycle acknowledge
reg err_i; // wishbone cycle error
wire [31:0] dat_o; // wishbone data out
 
wire sint_o; // non recoverable error, interrupt host
 
// Renderer stuff
reg write_i;
wire ack_o;
 
reg [31:2] render_addr_i;
reg [3:0] render_sel_i;
reg [31:0] render_dat_i;
 
initial begin
$dumpfile("wbm_w.vcd");
$dumpvars(0,wbm_w_bench);
 
// init values
clk_i = 0;
rst_i = 1;
err_i = 0;
write_i = 0;
render_addr_i = 0;
render_sel_i = 4'b1111;
render_dat_i = 32'h12345678;
 
#2 rst_i = 0;
//timing
# 10 write_i = 1;
# 2 write_i = 0;
# 4 write_i = 1;
# 2 write_i = 0;
 
// end sim
#100 $finish;
end
 
always @(posedge clk_i)
begin
ack_i <= #1 cyc_o & !ack_i;
end
 
 
always begin
#1 clk_i = ~clk_i;
end
 
gfx_wbm_write wbm_w(
// WB signals
.clk_i (clk_i),
.rst_i (rst_i),
.cyc_o (cyc_o),
.stb_o (stb_o),
.cti_o (cti_o),
.bte_o (bte_o),
.we_o (we_o),
.adr_o (adr_o),
.sel_o (sel_o),
.ack_i (ack_i),
.err_i (err_i),
.dat_o (dat_o),
.sint_o (sint_o),
// Control signals
.write_i (write_i),
.ack_o (ack_o),
.render_addr_i (render_addr_i),
.render_sel_i (render_sel_i),
.render_dat_i (render_dat_i)
);
endmodule

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