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  • This comparison shows the changes necessary to convert path 
    /ourisc/trunk/rtl
    from Rev 5 to Rev 6
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Rev 5 → Rev 6

/common/mux2x1.vhd
21,21 → 21,22
use ieee.std_logic_1164.all;
 
entity mux2x1 is
Generic ( WIDTH : integer := 16 );
Port ( in_a : in std_logic_vector (WIDTH-1 downto 0);
in_b : in std_logic_vector (WIDTH-1 downto 0);
sel : in std_logic_vector (0 downto 0); -- FIXME
dataout : out std_logic_vector (WIDTH-1 downto 0));
generic ( WIDTH : integer := 16 );
port ( sink_a : in std_logic_vector (WIDTH-1 downto 0);
sink_b : in std_logic_vector (WIDTH-1 downto 0);
sink_sel : in std_logic_vector (0 downto 0); -- FIXME
src_data : out std_logic_vector (WIDTH-1 downto 0)
);
end mux2x1;
 
architecture Primitive of mux2x1 is
begin
process(sel, in_a, in_b)
process(sink_sel, sink_a, sink_b)
begin
case sel is
when "0" => dataout <= in_a;
when "1" => dataout <= in_b;
when others => dataout <= (others => '0');
case sink_sel is
when "0" => src_data <= sink_a;
when "1" => src_data <= sink_b;
when others => src_data <= (others => '0');
end case;
end process;
/common/mux3x1.vhd
4,7 → 4,7
--
-- Create Date: 15:02:04 04/19/2012
-- Design Name: Multiplexer 3 x 1
-- Module Name: mux3x1 - Multiplex
-- Module Name: mux3x1 - behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
21,25 → 21,25
use ieee.std_logic_1164.all;
 
entity mux3x1 is
Generic ( WIDTH : integer := 16 );
Port ( in_a : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
in_b : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
in_c : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
dataout : out STD_LOGIC_VECTOR (WIDTH-1 downto 0));
generic ( WIDTH : integer := 16 );
port ( sink_a : in std_logic_vector (WIDTH-1 downto 0);
sink_b : in std_logic_vector (WIDTH-1 downto 0);
sink_c : in std_logic_vector (WIDTH-1 downto 0);
sink_sel : in std_logic_vector (1 downto 0);
src_data : out std_logic_vector (WIDTH-1 downto 0));
end mux3x1;
 
architecture Multiplex of mux3x1 is
architecture behavioral of mux3x1 is
begin
process(sel, in_a, in_b, in_c)
process(sink_sel, sink_a, sink_b, sink_c)
begin
case sel is
when "00" => dataout <= in_a;
when "01" => dataout <= in_b;
when "10" => dataout <= in_c;
when others => dataout <= (others => '0');
case sink_sel is
when "00" => src_data <= sink_a;
when "01" => src_data <= sink_b;
when "10" => src_data <= sink_c;
when others => src_data <= (others => '0');
end case;
end process;
 
end Multiplex;
end behavioral;
 
/common/mux4x1.vhd
24,24 → 24,24
generic (
WIDTH : integer := 16 );
port (
in_a : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
in_b : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
in_c : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
in_d : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
dataout : out STD_LOGIC_VECTOR (WIDTH-1 downto 0) );
sink_a : in std_logic_vector (WIDTH-1 downto 0);
sink_b : in std_logic_vector (WIDTH-1 downto 0);
sink_c : in std_logic_vector (WIDTH-1 downto 0);
sink_d : in std_logic_vector (WIDTH-1 downto 0);
sink_sel : in std_logic_vector (1 downto 0);
src_data : out std_logic_vector (WIDTH-1 downto 0) );
end mux4x1;
 
architecture Multiplex of mux4x1 is
begin
process(sel, in_a, in_b, in_c)
process(sink_sel, sink_a, sink_b, sink_c)
begin
case sel is
when "00" => dataout <= in_a;
when "01" => dataout <= in_b;
when "10" => dataout <= in_c;
when "11" => dataout <= in_d;
when others => dataout <= (others => '0');
case sink_sel is
when "00" => src_data <= sink_a;
when "01" => src_data <= sink_b;
when "10" => src_data <= sink_c;
when "11" => src_data <= sink_d;
when others => src_data <= (others => '0');
end case;
end process;
 

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