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  • This comparison shows the changes necessary to convert path
    /pairing/trunk/rtl
    from Rev 9 to Rev 10
    Reverse comparison

Rev 9 → Rev 10

/f36m.v
21,6 → 21,7
wire [`W2:0] in0, in1;
wire [`W2:0] o;
reg mult_reset, delay1, delay2;
reg [`W2:0] in0d,in1d;
 
assign {e0,e1,e2,e3,e4,e5} = K[6:1];
assign {a2,a1,a0} = a;
33,7 → 34,7
ins1 (a2,v1,a1,v3,v5,a0,e0,e1,e2,e3,e4,e5,in0), // $in0$ is the first input
ins2 (b2,v2,b1,v4,v6,b0,e0,e1,e2,e3,e4,e5,in1); // $in1$ is the second input
f32m_mult
ins3 (clk, mult_reset, in0, in1, o, mult_done); // o == in0 * in1
ins3 (clk, mult_reset, in0d, in1d, o, mult_done); // o == in0 * in1
func6
ins4 (clk, reset, mult_done, p);
f32m_add
58,6 → 59,11
 
always @ (posedge clk)
begin
in0d <= in0; in1d <= in1;
end
 
always @ (posedge clk)
begin
if (reset) K <= 7'b1000000;
else if (p | K[0]) K <= {1'b0,K[6:1]};
end
/tate_pairing.v
90,7 → 90,7
module tate_pairing(clk, reset, x1, y1, x2, y2, done, sel, out);
input clk, reset;
input [`WIDTH:0] x1, y1, x2, y2;
input [2:0] sel;
input [7:0] sel;
output reg done;
output reg [149:0] out;
127,15 → 127,13
else if (K[0]) begin done <= 1; o <= out2; end
 
always @ (o, sel)
case (sel)
3'd0: out = o[150-1:0];
3'd1: out = o[300-1:150];
3'd2: out = o[450-1:300];
3'd3: out = o[600-1:450];
3'd4: out = o[750-1:600];
3'd5: out = o[900-1:750];
3'd6: out = o[1050-1:900];
3'd7: out = o[`W6-1:1050];
default: out = 0;
endcase
out = (sel[0] ? o[150-1:0] : 0) |
(sel[1] ? o[300-1:150] : 0) |
(sel[2] ? o[450-1:300] : 0) |
(sel[3] ? o[600-1:450] : 0) |
(sel[4] ? o[750-1:600] : 0) |
(sel[5] ? o[900-1:750] : 0) |
(sel[6] ? o[1050-1:900] : 0) |
(sel[7] ? o[`W6-1:1050] : 0) ;
 
endmodule

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