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https://opencores.org/ocsvn/pairing/pairing/trunk
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- This comparison shows the changes necessary to convert path
/pairing/trunk/rtl
- from Rev 17 to Rev 22
- ↔ Reverse comparison
Rev 17 → Rev 22
/f3m.v
464,48 → 464,48
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// inversion in GF(3^m). C = A^(-1) |
module f3m_inv(clk, reset, A, C, done); |
input [`WIDTH:0] A; |
input clk; |
input reset; |
output reg [`WIDTH:0] C; |
input [`WIDTH:0] A; |
input clk; |
input reset; |
output reg [`WIDTH:0] C; |
output reg done; |
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reg [`WIDTH+2:0] S, R, U, V, d; |
reg [2*`M:0] i; |
wire [1:0] q; |
wire [`WIDTH+2:0] S1, S2, |
R1, |
U1, U2, U3, |
V1, V2, |
d1, d2; |
wire don; |
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reg [`WIDTH+2:0] S, R, U, V, d; |
reg [2*`M:0] i; |
wire [1:0] q; |
wire [`WIDTH+2:0] S1, S2, |
R1, |
U1, U2, U3, |
V1, V2, |
d1, d2; |
wire don; |
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assign d1 = {d[`WIDTH+1:0], 1'b1}; // d1 == d+1 |
assign d2 = {1'b0, d[`WIDTH+2:1]}; // d2 == d-1 |
assign don = i[0]; |
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f3_mult |
q1(S[`MOST], R[`MOST], q); // q = s_m / r_m |
func1 |
ins1(S, R, q, S1), // S1 = S - q*R |
ins2(V, U, q, V1); // V1 = V - q*U |
func2 |
ins3(S1, S2), // S2 = x*S1 = x*(S-q*R) |
ins4(R, R1); // R1 = x*R |
func3 |
ins5(U, U1), // U1 = x*U mod p |
ins6(V1, V2); // V2 = x*V1 mod p = x*(V-qU) mod p |
assign d1 = {d[`WIDTH+1:0], 1'b1}; // d1 == d+1 |
assign d2 = {1'b0, d[`WIDTH+2:1]}; // d2 == d-1 |
assign don = i[0]; |
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f3_mult |
q1(S[`MOST], R[`MOST], q); // q = s_m / r_m |
func1 |
ins1(S, R, q, S1), // S1 = S - q*R |
ins2(V, U, q, V1); // V1 = V - q*U |
func2 |
ins3(S1, S2), // S2 = x*S1 = x*(S-q*R) |
ins4(R, R1); // R1 = x*R |
func3 |
ins5(U, U1), // U1 = x*U mod p |
ins6(V1, V2); // V2 = x*V1 mod p = x*(V-qU) mod p |
func4 |
ins7(U, R[`MOST], U2); // U2 = U/r_m |
func5 |
ins8(U, U3); // U3 = (U/x) mod p |
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always @ (posedge clk) |
always @ (posedge clk) |
if (reset) |
done <= 0; |
else if (don) |
else if (don) |
begin |
done <= 1; C <= U2[`WIDTH:0]; |
done <= 1; C <= U2[`WIDTH:0]; |
end |
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always @ (posedge clk) |
/f3.v
23,14 → 23,14
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// f3_mult: C = A*B (mod 3) |
module f3_mult(A, B, C); |
input [1:0] A; |
input [1:0] B; |
output [1:0] C; |
wire a0, a1, b0, b1; |
assign {a1, a0} = A; |
assign {b1, b0} = B; |
assign C[0] = (~a1 & a0 & ~b1 & b0) | (a1 & ~a0 & b1 & ~b0); |
assign C[1] = (~a1 & a0 & b1 & ~b0) | (a1 & ~a0 & ~b1 & b0); |
input [1:0] A; |
input [1:0] B; |
output [1:0] C; |
wire a0, a1, b0, b1; |
assign {a1, a0} = A; |
assign {b1, b0} = B; |
assign C[0] = (~a1 & a0 & ~b1 & b0) | (a1 & ~a0 & b1 & ~b0); |
assign C[1] = (~a1 & a0 & b1 & ~b0) | (a1 & ~a0 & ~b1 & b0); |
endmodule |
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// c == a+1 (mod 3) |