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URL https://opencores.org/ocsvn/pairing/pairing/trunk

Subversion Repositories pairing

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /pairing/trunk/synthesis/xilinx
    from Rev 13 to Rev 16
    Reverse comparison

Rev 13 → Rev 16

/tate_pairing.prj
0,0 → 1,7
verilog work "rtl/fun.v"
verilog work "rtl/f3.v"
verilog work "rtl/f3m.v"
verilog work "rtl/f33m.v"
verilog work "rtl/f32m.v"
verilog work "rtl/f36m.v"
verilog work "rtl/tate_pairing.v"
/tate_pairing.xst
0,0 → 1,59
set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn tate_pairing.prj
-ifmt mixed
-ofn tate_pairing
-ofmt NGC
-p xc4vlx200-11-ff1513
-top tate_pairing
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract Yes
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract Yes
-resource_sharing YES
-async_to_sync NO
-use_dsp48 Auto
-iobuf YES
-max_fanout 500
-bufg 32
-bufr 48
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5

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