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/pavr_hwres_rf_rd1_01.gif
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pavr_hwres_rf_rd1_01.gif
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Index: restart.do
===================================================================
--- restart.do (nonexistent)
+++ restart.do (revision 6)
@@ -0,0 +1,16 @@
+;# This is a Modelsim PE/Plus 5.3a_p1 macro file.
+;#
+
+;# Compile pAVR test architectures.
+do test_pavr_compile.do
+
+;# Restart simulation
+restart -f
+
+;# General test 1
+run 150000
+
+;# General test 2
+;#run 15000
+
+
Index: group__pavr__pipeline__calls.html
===================================================================
--- group__pavr__pipeline__calls.html (nonexistent)
+++ group__pavr__pipeline__calls.html (revision 6)
@@ -0,0 +1,45 @@
+
+
+Calls
+
+
+
+
+Main Page Modules Related Pages
+
Calls
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: test_pavr_register_file.vhd
===================================================================
--- test_pavr_register_file.vhd (nonexistent)
+++ test_pavr_register_file.vhd (revision 6)
@@ -0,0 +1,454 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This tests pAVR's Register File.
+-- The following tests are done:
+-- - read all ports, one at a time
+-- - read port 1 (RFRD1)
+-- - read port 2 (RFRD2)
+-- - write port (RFWR)
+-- - write pointer register X (RFXWR)
+-- - write pointer register Y (RFYWR)
+-- - write pointer register Z (RFZWR)
+-- - combined RFRD1, RFRD2, RFWR
+-- They should work simultaneousely.
+-- - combined RFXWR, RFYWR, RFZWR
+-- They should work simultaneousely.
+-- - combined RFRD1, RFRD2, RFWR, RFXWR, RFYWR, RFZWR
+-- That is, all RF ports are accessed simultaneousely. They should work do
+-- their job.
+-- However, note that the pointer registers are accessible for writting by
+-- their own ports but also by the RF write port. Writing them via pointer
+-- register write ports overwrites writing via general write port.
+-- Even though concurrent writing could happen in a perfectly legal AVR
+-- implementation, AVR's behavior is unpredictible (what write port has
+-- priority). We have chosen for pAVR the priority as mentioned above.
+--
+
+
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+library work;
+use work.std_util.all;
+use work.pavr_util.all;
+use work.pavr_constants.all;
+
+
+entity test_pavr_rf is
+end;
+
+
+architecture test_pavr_rf_arch of test_pavr_rf is
+ signal clk, res, syncres: std_logic;
+
+ -- Clock counter
+ signal cnt: std_logic_vector(7 downto 0);
+
+ -- RF read port 1
+ signal pavr_rf_rd1_addr : std_logic_vector(4 downto 0);
+ signal pavr_rf_rd1_rd : std_logic;
+ signal pavr_rf_rd1_do : std_logic_vector(7 downto 0);
+
+ -- RF read port 2
+ signal pavr_rf_rd2_addr : std_logic_vector(4 downto 0);
+ signal pavr_rf_rd2_rd : std_logic;
+ signal pavr_rf_rd2_do : std_logic_vector(7 downto 0);
+
+ -- RF write port
+ signal pavr_rf_wr_addr : std_logic_vector(4 downto 0);
+ signal pavr_rf_wr_wr : std_logic;
+ signal pavr_rf_wr_di : std_logic_vector(7 downto 0);
+
+ -- X pointer port
+ signal pavr_rf_x : std_logic_vector(15 downto 0);
+ signal pavr_rf_x_wr : std_logic;
+ signal pavr_rf_x_di : std_logic_vector(15 downto 0);
+
+ -- Y pointer port
+ signal pavr_rf_y : std_logic_vector(15 downto 0);
+ signal pavr_rf_y_wr : std_logic;
+ signal pavr_rf_y_di : std_logic_vector(15 downto 0);
+
+ -- Z pointer port
+ signal pavr_rf_z : std_logic_vector(15 downto 0);
+ signal pavr_rf_z_wr : std_logic;
+ signal pavr_rf_z_di : std_logic_vector(15 downto 0);
+
+ -- Declare the Register File.
+ component pavr_rf
+ port(
+ pavr_rf_clk: in std_logic;
+ pavr_rf_res: in std_logic;
+ pavr_rf_syncres: in std_logic;
+
+ -- Read port #1
+ pavr_rf_rd1_addr: in std_logic_vector(4 downto 0);
+ pavr_rf_rd1_rd: in std_logic;
+ pavr_rf_rd1_do: out std_logic_vector(7 downto 0);
+
+ -- Read port #2
+ pavr_rf_rd2_addr: in std_logic_vector(4 downto 0);
+ pavr_rf_rd2_rd: in std_logic;
+ pavr_rf_rd2_do: out std_logic_vector(7 downto 0);
+
+ -- Write port
+ pavr_rf_wr_addr: in std_logic_vector(4 downto 0);
+ pavr_rf_wr_wr: in std_logic;
+ pavr_rf_wr_di: in std_logic_vector(7 downto 0);
+
+ -- Pointer registers
+ pavr_rf_x: out std_logic_vector(15 downto 0);
+ pavr_rf_x_wr: in std_logic;
+ pavr_rf_x_di: in std_logic_vector(15 downto 0);
+
+ pavr_rf_y: out std_logic_vector(15 downto 0);
+ pavr_rf_y_wr: in std_logic;
+ pavr_rf_y_di: in std_logic_vector(15 downto 0);
+
+ pavr_rf_z: out std_logic_vector(15 downto 0);
+ pavr_rf_z_wr: in std_logic;
+ pavr_rf_z_di: in std_logic_vector(15 downto 0)
+ );
+ end component;
+ for all: pavr_rf use entity work.pavr_rf(pavr_rf_arch);
+
+begin
+
+ -- Instantiate a the Register File.
+ pavr_rf_instance1: pavr_rf
+ port map(
+ clk,
+ res,
+ syncres,
+
+ -- Read port #1
+ pavr_rf_rd1_addr,
+ pavr_rf_rd1_rd,
+ pavr_rf_rd1_do,
+
+ -- Read port #2
+ pavr_rf_rd2_addr,
+ pavr_rf_rd2_rd,
+ pavr_rf_rd2_do,
+
+ -- Write port
+ pavr_rf_wr_addr,
+ pavr_rf_wr_wr,
+ pavr_rf_wr_di,
+
+ -- Pointer registers
+ pavr_rf_x,
+ pavr_rf_x_wr,
+ pavr_rf_x_di,
+
+ pavr_rf_y,
+ pavr_rf_y_wr,
+ pavr_rf_y_di,
+
+ pavr_rf_z,
+ pavr_rf_z_wr,
+ pavr_rf_z_di
+ );
+
+
+ generate_clock:
+ process
+ begin
+ clk <= '1';
+ wait for 50 ns;
+ clk <= '0';
+ wait for 50 ns;
+ end process generate_clock;
+
+
+ generate_reset:
+ process
+ begin
+ res <= '0';
+ wait for 100 ns;
+ res <= '1';
+ wait for 110 ns;
+ res <= '0';
+ wait for 1 ms;
+ end process generate_reset;
+
+
+ generate_sync_reset:
+ process
+ begin
+ syncres <= '0';
+ wait for 300 ns;
+ syncres <= '1';
+ wait for 110 ns;
+ syncres <= '0';
+ wait for 1 ms;
+ end process generate_sync_reset;
+
+
+ test_main:
+ process(clk, res, syncres,
+ cnt,
+ pavr_rf_rd1_addr,
+ pavr_rf_rd2_addr,
+ pavr_rf_wr_addr, pavr_rf_wr_di,
+ pavr_rf_x_di,
+ pavr_rf_y_di,
+ pavr_rf_z_di
+ )
+ begin
+ if res='1' then
+ -- Async reset
+ -- The Register File should take care of reseting its registers. Check
+ -- this too.
+ cnt <= int_to_std_logic_vector(0, cnt'length);
+ elsif clk'event and clk='1' then
+ -- Clock counter
+ cnt <= cnt+1;
+
+ -- Initialize inputs.
+ pavr_rf_rd1_addr <= int_to_std_logic_vector(3, pavr_rf_rd1_addr'length);
+ pavr_rf_rd1_rd <= '0';
+ pavr_rf_rd2_addr <= int_to_std_logic_vector(4, pavr_rf_rd2_addr'length);
+ pavr_rf_rd2_rd <= '0';
+ pavr_rf_wr_addr <= int_to_std_logic_vector(5, pavr_rf_wr_addr'length);
+ pavr_rf_wr_wr <= '0';
+ pavr_rf_wr_di <= int_to_std_logic_vector(6, pavr_rf_wr_di'length);
+
+ pavr_rf_x_wr <= '0';
+ pavr_rf_x_di <= int_to_std_logic_vector(7, pavr_rf_x_di'length);
+ pavr_rf_y_wr <= '0';
+ pavr_rf_y_di <= int_to_std_logic_vector(8, pavr_rf_y_di'length);
+ pavr_rf_z_wr <= '0';
+ pavr_rf_z_di <= int_to_std_logic_vector(9, pavr_rf_z_di'length);
+
+ case std_logic_vector_to_nat(cnt) is
+
+ -- TEST 1
+ -- Test RFWR, RFRD1 and RFRD1, one port at a time. Access RF registers
+ -- others than pointer registers.
+ -- RFWR
+ when 5 =>
+ pavr_rf_wr_addr <= int_to_std_logic_vector(10, pavr_rf_wr_addr'length);
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= int_to_std_logic_vector(50, pavr_rf_wr_di'length);
+ -- RFWR
+ when 6 =>
+ pavr_rf_wr_addr <= int_to_std_logic_vector(11, pavr_rf_wr_addr'length);
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= int_to_std_logic_vector(51, pavr_rf_wr_di'length);
+ -- RFRD1
+ when 7 =>
+ pavr_rf_rd1_addr <= int_to_std_logic_vector(10, pavr_rf_rd1_addr'length);
+ pavr_rf_rd1_rd <= '1';
+ -- RFRD2
+ when 8 =>
+ pavr_rf_rd2_addr <= int_to_std_logic_vector(11, pavr_rf_rd2_addr'length);
+ pavr_rf_rd2_rd <= '1';
+
+
+
+ -- TEST 2
+ -- Test RFWR, RFRD1 and RFRD1, one port at a time. Access RF pointer
+ -- registers.
+ -- RFWR
+ when 12 =>
+ pavr_rf_wr_addr <= int_to_std_logic_vector(26, pavr_rf_wr_addr'length);
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= int_to_std_logic_vector(60, pavr_rf_wr_di'length);
+ when 13 =>
+ pavr_rf_wr_addr <= int_to_std_logic_vector(27, pavr_rf_wr_addr'length);
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= int_to_std_logic_vector(61, pavr_rf_wr_di'length);
+ when 14 =>
+ pavr_rf_wr_addr <= int_to_std_logic_vector(28, pavr_rf_wr_addr'length);
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= int_to_std_logic_vector(62, pavr_rf_wr_di'length);
+ when 15 =>
+ pavr_rf_wr_addr <= int_to_std_logic_vector(29, pavr_rf_wr_addr'length);
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= int_to_std_logic_vector(63, pavr_rf_wr_di'length);
+ when 16 =>
+ pavr_rf_wr_addr <= int_to_std_logic_vector(30, pavr_rf_wr_addr'length);
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= int_to_std_logic_vector(64, pavr_rf_wr_di'length);
+ when 17 =>
+ pavr_rf_wr_addr <= int_to_std_logic_vector(31, pavr_rf_wr_addr'length);
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= int_to_std_logic_vector(65, pavr_rf_wr_di'length);
+ -- RFRD1
+ when 18 =>
+ pavr_rf_rd1_addr <= int_to_std_logic_vector(26, pavr_rf_rd1_addr'length);
+ pavr_rf_rd1_rd <= '1';
+ -- RFRD2
+ when 19 =>
+ pavr_rf_rd2_addr <= int_to_std_logic_vector(27, pavr_rf_rd2_addr'length);
+ pavr_rf_rd2_rd <= '1';
+ -- RFRD1
+ when 20 =>
+ pavr_rf_rd1_addr <= int_to_std_logic_vector(28, pavr_rf_rd1_addr'length);
+ pavr_rf_rd1_rd <= '1';
+ -- RFRD1
+ when 21 =>
+ pavr_rf_rd1_addr <= int_to_std_logic_vector(29, pavr_rf_rd1_addr'length);
+ pavr_rf_rd1_rd <= '1';
+ -- RFRD2
+ when 22 =>
+ pavr_rf_rd2_addr <= int_to_std_logic_vector(30, pavr_rf_rd2_addr'length);
+ pavr_rf_rd2_rd <= '1';
+ -- RFRD2
+ when 23 =>
+ pavr_rf_rd2_addr <= int_to_std_logic_vector(31, pavr_rf_rd2_addr'length);
+ pavr_rf_rd2_rd <= '1';
+
+
+
+ -- TEST 3
+ -- Test RFWR, RFRD1 and RFRD1, combined accesses. Write RF registers
+ -- others than pointer registers.
+ -- Note: RFWR and RFRD1 access the same location.
+ when 26 =>
+ pavr_rf_wr_addr <= int_to_std_logic_vector(10, pavr_rf_wr_addr'length);
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= int_to_std_logic_vector(70, pavr_rf_wr_di'length);
+ pavr_rf_rd1_addr <= int_to_std_logic_vector(10, pavr_rf_rd1_addr'length);
+ pavr_rf_rd1_rd <= '1';
+ pavr_rf_rd2_addr <= int_to_std_logic_vector(11, pavr_rf_rd2_addr'length);
+ pavr_rf_rd2_rd <= '1';
+
+
+
+ -- TEST 4
+ -- Test RFWR, RFRD1 and RFRD1, combined accesses. Write RF pointer
+ -- registers.
+ -- Note: RFWR, RFRD1 and RFRD2 access the same location.
+ when 29 =>
+ pavr_rf_wr_addr <= int_to_std_logic_vector(26, pavr_rf_wr_addr'length);
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= int_to_std_logic_vector(80, pavr_rf_wr_di'length);
+ pavr_rf_rd1_addr <= int_to_std_logic_vector(26, pavr_rf_rd1_addr'length);
+ pavr_rf_rd1_rd <= '1';
+ pavr_rf_rd2_addr <= int_to_std_logic_vector(26, pavr_rf_rd2_addr'length);
+ pavr_rf_rd2_rd <= '1';
+
+
+
+ -- TEST 5
+ -- Test RFWR, RFRD1 and RFRD1, combined accesses. Write RF pointer
+ -- registers.
+ -- Note: RFWR, RFRD1 and RFRD2 each access a different location.
+ -- RFWR
+ when 32 =>
+ pavr_rf_wr_addr <= int_to_std_logic_vector(27, pavr_rf_wr_addr'length);
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= int_to_std_logic_vector(90, pavr_rf_wr_di'length);
+ pavr_rf_rd1_addr <= int_to_std_logic_vector(28, pavr_rf_rd1_addr'length);
+ pavr_rf_rd1_rd <= '1';
+ pavr_rf_rd2_addr <= int_to_std_logic_vector(31, pavr_rf_rd2_addr'length);
+ pavr_rf_rd2_rd <= '1';
+
+
+
+ -- TEST 6
+ -- Test pointer register write ports.
+ when 35 =>
+ pavr_rf_x_wr <= '1';
+ pavr_rf_x_di <= int_to_std_logic_vector(16#1111#, pavr_rf_x_di'length);
+ pavr_rf_y_wr <= '1';
+ pavr_rf_y_di <= int_to_std_logic_vector(16#2222#, pavr_rf_y_di'length);
+ pavr_rf_z_wr <= '1';
+ pavr_rf_z_di <= int_to_std_logic_vector(16#3333#, pavr_rf_z_di'length);
+
+
+
+ -- TEST 7
+ -- Test RFWR, RFRD1, RFRD2 and pointer register write ports, all at
+ -- the same time. No writes compete for the same location.
+ when 38 =>
+ pavr_rf_wr_addr <= int_to_std_logic_vector(10, pavr_rf_wr_addr'length);
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= int_to_std_logic_vector(110, pavr_rf_wr_di'length);
+ pavr_rf_rd1_addr <= int_to_std_logic_vector(10, pavr_rf_rd1_addr'length);
+ pavr_rf_rd1_rd <= '1';
+ pavr_rf_rd2_addr <= int_to_std_logic_vector(11, pavr_rf_rd2_addr'length);
+ pavr_rf_rd2_rd <= '1';
+ pavr_rf_x_wr <= '1';
+ pavr_rf_x_di <= int_to_std_logic_vector(111, pavr_rf_x_di'length);
+ pavr_rf_y_wr <= '1';
+ pavr_rf_y_di <= int_to_std_logic_vector(112, pavr_rf_y_di'length);
+ pavr_rf_z_wr <= '1';
+ pavr_rf_z_di <= int_to_std_logic_vector(113, pavr_rf_z_di'length);
+
+
+
+ -- TEST 8
+ -- Test RFWR, RFRD1, RFRD2 and pointer register write ports, all at
+ -- the same time. RFWR and RFZWR try to write the same location.
+ -- RFZWR should win.
+ when 41 =>
+ pavr_rf_wr_addr <= int_to_std_logic_vector(31, pavr_rf_wr_addr'length);
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= int_to_std_logic_vector(120, pavr_rf_wr_di'length);
+ pavr_rf_rd1_addr <= int_to_std_logic_vector(30, pavr_rf_rd1_addr'length);
+ pavr_rf_rd1_rd <= '1';
+ pavr_rf_rd2_addr <= int_to_std_logic_vector(31, pavr_rf_rd2_addr'length);
+ pavr_rf_rd2_rd <= '1';
+ pavr_rf_x_wr <= '1';
+ pavr_rf_x_di <= int_to_std_logic_vector(121, pavr_rf_x_di'length);
+ pavr_rf_y_wr <= '1';
+ pavr_rf_y_di <= int_to_std_logic_vector(122, pavr_rf_y_di'length);
+ pavr_rf_z_wr <= '1';
+ pavr_rf_z_di <= int_to_std_logic_vector(123, pavr_rf_z_di'length);
+
+
+
+ when others =>
+ null;
+ end case;
+
+ if syncres='1' then
+ -- Sync reset
+ -- The Register File should take care of reseting its registers. Check
+ -- this too.
+ cnt <= int_to_std_logic_vector(0, cnt'length);
+ end if;
+ end if;
+ end process test_main;
+
+
+end;
+--
Index: group__pavr__avrarch.html
===================================================================
--- group__pavr__avrarch.html (nonexistent)
+++ group__pavr__avrarch.html (revision 6)
@@ -0,0 +1,51 @@
+
+
+AVR architecture
+
+
+
+
+Main Page Modules Related Pages
+
+
+
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__hwres__iof__perif__pa.html
===================================================================
--- group__pavr__hwres__iof__perif__pa.html (nonexistent)
+++ group__pavr__hwres__iof__perif__pa.html (revision 6)
@@ -0,0 +1,40 @@
+
+
+Port A
+
+
+
+
+Main Page Modules Related Pages
+
Port A
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__hwres.html
===================================================================
--- group__pavr__hwres.html (nonexistent)
+++ group__pavr__hwres.html (revision 6)
@@ -0,0 +1,28 @@
+
+
+Hardware resources
+
+
+
+
+Main Page Modules Related Pages
+
Hardware resources
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: treeview.js
===================================================================
--- treeview.js (nonexistent)
+++ treeview.js (revision 6)
@@ -0,0 +1,500 @@
+//****************************************************************
+// You are free to copy the "Folder-Tree" script as long as you
+// keep this copyright notice:
+// Script found in: http://www.geocities.com/Paris/LeftBank/2178/
+// Author: Marcelino Alves Martins (martins@hks.com) December '97.
+//****************************************************************
+
+//Log of changes:
+// 17 Feb 98 - Fix initialization flashing problem with Netscape
+//
+// 27 Jan 98 - Root folder starts open; support for USETEXTLINKS;
+// make the ftien4 a js file
+//
+// DvH: Dec 2000 - Made some minor changes to support external
+// references
+
+// Definition of class Folder
+// *****************************************************************
+
+function Folder(folderDescription, tagName, hreference) //constructor
+{
+ //constant data
+ this.desc = folderDescription
+ this.tagName = tagName
+ this.hreference = hreference
+ this.id = -1
+ this.navObj = 0
+ this.iconImg = 0
+ this.nodeImg = 0
+ this.isLastNode = 0
+
+ //dynamic data
+ this.isOpen = true
+ this.iconSrc = "ftv2folderopen.png"
+ this.children = new Array
+ this.nChildren = 0
+
+ //methods
+ this.initialize = initializeFolder
+ this.setState = setStateFolder
+ this.addChild = addChild
+ this.createIndex = createEntryIndex
+ this.hide = hideFolder
+ this.display = display
+ this.renderOb = drawFolder
+ this.totalHeight = totalHeight
+ this.subEntries = folderSubEntries
+ this.outputLink = outputFolderLink
+}
+
+function setStateFolder(isOpen)
+{
+ var subEntries
+ var totalHeight
+ var fIt = 0
+ var i=0
+
+ if (isOpen == this.isOpen)
+ return
+
+ if (browserVersion == 2)
+ {
+ totalHeight = 0
+ for (i=0; i < this.nChildren; i++)
+ totalHeight = totalHeight + this.children[i].navObj.clip.height
+ subEntries = this.subEntries()
+ if (this.isOpen)
+ totalHeight = 0 - totalHeight
+ for (fIt = this.id + subEntries + 1; fIt < nEntries; fIt++)
+ indexOfEntries[fIt].navObj.moveBy(0, totalHeight)
+ }
+ this.isOpen = isOpen
+ propagateChangesInState(this)
+}
+
+function propagateChangesInState(folder)
+{
+ var i=0
+
+ if (folder.isOpen)
+ {
+ if (folder.nodeImg)
+ if (folder.isLastNode)
+ folder.nodeImg.src = "ftv2mlastnode.png"
+ else
+ folder.nodeImg.src = "ftv2mnode.png"
+ folder.iconImg.src = "ftv2folderopen.png"
+ for (i=0; i 0)
+ auxEv = ""
+ else
+ auxEv = ""
+
+ if (level>0)
+ if (lastNode) //the last 'brother' in the children array
+ {
+ this.renderOb(leftSide + auxEv + "
")
+ leftSide = leftSide + "
"
+ this.isLastNode = 1
+ }
+ else
+ {
+ this.renderOb(leftSide + auxEv + "
")
+ leftSide = leftSide + "
"
+ this.isLastNode = 0
+ }
+ else
+ this.renderOb("")
+
+ if (nc > 0)
+ {
+ level = level + 1
+ for (i=0 ; i < this.nChildren; i++)
+ {
+ if (i == this.nChildren-1)
+ this.children[i].initialize(level, 1, leftSide)
+ else
+ this.children[i].initialize(level, 0, leftSide)
+ }
+ }
+}
+
+function drawFolder(leftSide)
+{
+ if (browserVersion == 2) {
+ if (!doc.yPos)
+ doc.yPos=8
+ doc.write("")
+ }
+ if (browserVersion == 3)
+ {
+ doc.write("
")
+ leftSide = leftSide + ""
+ }
+ else
+ {
+ this.renderOb(leftSide + "
")
+ leftSide = leftSide + ""
+ }
+ else
+ this.renderOb("")
+}
+
+function drawItem(leftSide)
+{
+ if (browserVersion == 2)
+ doc.write("")
+ if (browserVersion == 3)
+ doc.write(" ")
+
+ // close the whole tree
+ clickOnNode(0)
+ // open the root folder
+ clickOnNode(0)
+ }
+}
+
+// Auxiliary Functions for Folder-Treee backward compatibility
+// *********************************************************
+
+function gFld(description, tagName, hreference)
+{
+ folder = new Folder(description, tagName, hreference)
+ return folder
+}
+
+function gLnk(description, tagName, linkData)
+{
+ fullLink = ""
+
+ if (linkData!="")
+ {
+ fullLink = "'"+linkData+"' target=\"basefrm\""
+ }
+
+ linkItem = new Item(description, tagName, fullLink)
+ return linkItem
+}
+
+function insFld(parentFolder, childFolder)
+{
+ return parentFolder.addChild(childFolder)
+}
+
+function insDoc(parentFolder, document)
+{
+ parentFolder.addChild(document)
+}
+
+// Global variables
+// ****************
+
+USETEXTLINKS = 1
+indexOfEntries = new Array
+nEntries = 0
+doc = document
+browserVersion = 0
+selectedFolder=0
Index: group__pavr__hwres__sfu.html
===================================================================
--- group__pavr__hwres__sfu.html (nonexistent)
+++ group__pavr__hwres__sfu.html (revision 6)
@@ -0,0 +1,79 @@
+
+
+Stall and Flush Unit
+
+
+
+
+Main Page Modules Related Pages
+
Stall and Flush Unit
+
+The pipeline controls its own stall and flush status, through specific stall and flush-related request signals. These requests are sent to the Stall and Flush Unit (SFU). The output of the SFU is a set of signals that directly control pipeline stages (a stall and flush control signals pair for each stage):
+
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: ftv2node.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: ftv2node.png
===================================================================
--- ftv2node.png (nonexistent)
+++ ftv2node.png (revision 6)
Calls
+
+[Pipeline details]
+
- +A few details
-
+There are 4 call instructions, analogue to the jump instructions:
-
+
- RCALL (relative call)
+ The call address is obtained by adding to the current Program Counter a 12 bit signed offset obtained from the instruction word. - ICALL (indirect call)
+ The call address is read from the Z pointer register.
+ The destination resides in the lower 64 Kwords of Program Memory.
+ - EICALL (extended indirect call)
+ The call address is read from EIND:Z (higher 6 bis from EIND register in IOF, and lower 16 bits from Z pointer in RF).
+ This call accesses the whole 22 bit addressing space of the Program Memory.
+ - CALL (far call)
+ The call address is read from two consecutive instruction words.
+ This call accesses the whole 22 bit addressing space of the Program Memory.
+
+ Apart from these, there is another kind of call, automatically inserted into the pipeline when an interrupt is processed. In addition to the regular calls, the implicit interrupt call also clears the general interrupt flag (flag I in the Status Register). This way, nested interrupts are disabled by default. However, they can be enabled explicitely. This behavior is questionable, but is implemented for the sake of AVR compatibility.
+ After an interrupt generates an implicit call, further interrupts are disabled for 4 clocks. This way, at least one instruction will be executed fron the called subroutine. Only after that, another interrupt can change the instruction flow.
+
+ All calls take 4 clocks.
+ - RCALL (relative call)
- +Call state machine
-
+
+++
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: test_pavr_register_file.vhd
===================================================================
--- test_pavr_register_file.vhd (nonexistent)
+++ test_pavr_register_file.vhd (revision 6)
@@ -0,0 +1,454 @@
+-- AVR architecture
- +AVR features
-
+
-
+
- Load-store RISC machine
- Harvard architecture, with separate program/data buses
- 2 level pipeline: fetch and execute
- Most instructions execute in 1 clock.
- Variable instruction word width: 16 or 32 bits. Most instructions are 16 bits wide
- Register File (RF) with 32 registers
- IO File (IOF) with 64 registers
- Loads and stores operate in the Unified Memory space.
+ The Unified Memory (UM) is the space formed by concatenating the RF, IOF and the Data Memory (DM), in this order. Thus, the RF begins at address 0 in the UM, the IOF at address 32 and the DM at address 96. - Register File mapped pointer registers X, Y, Z, 16 bits each, for indirect addressing the Data Memory and the Program Memory (PM).
+ Pointer registers have pre-decrement and post-increment capabilities.
+
- +Todo:
-
+Add some AVR kernel schematics.
+ Add some AVR general considerations.
- +Notes on AVR downsides
-
+Among other 8 bit microcontrollers, the AVR architecture is relatively clean and fast. Of course, it is not perfect. In the following, I will expand on some of the drawbacks of the AVR architecture.
+
+ Pipeline-friendliness issues:-
+
- The register file, IO file and data memory have a unified addressing space.
+ The Register File, IO file and Data Memory are very different entities, from the point of view of the AVR instruction set. It's an obvious decision to physically implement them as different memory-like entities. Pipelining such a structure is straightforward. A simple and fast pipeline can be built naturally. Every memory-like entity can be assigned a fixed pipe stage during which it is accessed for writing or for reading, with no more than one such elementary operation needed during any instruction.
+ However, the AVR architecture has a unified addressing space for Register File - IO file - Data Memory. Accessing this Unified Memory space can be done through indirect loads and stores, via dedicated pointer registers. Depending upon the contents of a pointer register, an access to the Register File or the IO file or the Data Memory is needed. This completely messes up the simple pipeline structure above, because instructions' execution is data driven. As a result, for example, the Register File must now be accessed, let's say for reading, in more than one pipe stage. This is most pipeline-destructive, because different instructions will compete on the same hardware resources.
+ Arbitration/stall schemes are required. Also, new data hazards must be dealt with. All these are pretty complex, and come with a cost, in terms of both power consumption and speed.
+ The unified address space does bring new addressing capabilities. However, they are unnatural and basically useless. Who will ever place the stack in the Register File or in the IO File? That would make some sense for low-end controllers that don't have Data Memory at all, and rely on a Register File mapped stack. However, the price paid for that is big.
+ As a result, pAVR's loads and stores take 2 cycles. If the pointer registers would have pointed only in the Data Memory space, loads and stores would have naturally taken a single clock. - The Register File/IO file operand's addresses don't have fixed positions in the instruction opcodes.
+ That would have allowed reducing the number of pipe stages from 6 to 5. As a result, a lower CPI would have been obtained, because of less cycles penalty on the instructions that modify the instruction flow (branches, jumps, calls etc). Also, that would have ment lower power consumption because of less registers and combinational logic. - The instruction has variable width: 16 or 32 bits.
+ That is not pipeline-friendly.
+ Each 32 bit instruction could have easily been replaced by two 16 bit instructions.
+ Instruction set orthogonalithy issues:-
+
- Pointer registers X, Y, Z have addressing capabilities that are different from each other.
- Register File locations 0...15 have different addressing capabilities than RF locations 16...31.
- IO locations 0 to 31 support more addressing modes than IO locations 32 to 63.
- There are instructions that work on 16 bit words (for example, 16 bit register-to-register moves).
+ The existance of such instructions on a 8 bit RISC controller is questionable. That's not because such operations are not needed, but because the raise in complexity and irregularity is not justifiable.
+ The cost/performance balance is negative for these instructions (we're still talking about a controller claimed to be RISC). - opcodes 0x95C8 and 0x9004 do exactly the same thing (LPM).
+ Other such examples might exist.
+ The instruction bits could have been used more carefully. - CLR affects flags, while SER does not, even though they seem to be complementary intructions.
+ This might be a design flaw in the original core or designed on (a hidden) purpose by whoever designed the AVR core. By the way, if I remember well some ancient news, AVR was designed not by Atmel, but by a Scandinavian company that was aquired later by Atmel.
- The register file, IO file and data memory have a unified addressing space.
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__hwres__iof__perif__pa.html
===================================================================
--- group__pavr__hwres__iof__perif__pa.html (nonexistent)
+++ group__pavr__hwres__iof__perif__pa.html (revision 6)
@@ -0,0 +1,40 @@
+
+
+Port A
+
+[Peripherals]
+
- +Port A structure
-
+The port A offers 8 bidirectional general purpose IO lines.
+ Lines 0 and 1 also have alternate functions:-
+
- line 0 can be used as external interrupt 0 input
- line 1 can be used as timer 0 clock input.
+ Port A is managed through 3 IO File locations: PORTA, DDRA and PINA.
+ DDRA sets each pin's direction: DDRA(i)=0 means that line i is input, DDRA(i)=1 means that line i is output.
+ When writing a value to the port, that value goes into PORTA. If DDRA configures the corresponding lines as outputs, the contents of PORTA will be available on external pins. However, if DDRA configures the lines as inputs (DDRA(i)=0), then:-
+
- if PORTA(i)=0, the line i is `pure' input (High Z).
+ - if PORTA(i)=1, the line i is an input weakly pulled high.
+
+
- +Port A schematics
-
+
+++
+
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__hwres.html
===================================================================
--- group__pavr__hwres.html (nonexistent)
+++ group__pavr__hwres.html (revision 6)
@@ -0,0 +1,28 @@
+
+
+Hardware resources
+
+[Implementation]
+
Modules | |
| Register File | |
| Bypass Unit | |
| IO File | |
| ALU | |
| DACU | |
| Data Memory | |
| Program Memory | |
| Stall and Flush Unit | |
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: treeview.js
===================================================================
--- treeview.js (nonexistent)
+++ treeview.js (revision 6)
@@ -0,0 +1,500 @@
+//****************************************************************
+// You are free to copy the "Folder-Tree" script as long as you
+// keep this copyright notice:
+// Script found in: http://www.geocities.com/Paris/LeftBank/2178/
+// Author: Marcelino Alves Martins (martins@hks.com) December '97.
+//****************************************************************
+
+//Log of changes:
+// 17 Feb 98 - Fix initialization flashing problem with Netscape
+//
+// 27 Jan 98 - Root folder starts open; support for USETEXTLINKS;
+// make the ftien4 a js file
+//
+// DvH: Dec 2000 - Made some minor changes to support external
+// references
+
+// Definition of class Folder
+// *****************************************************************
+
+function Folder(folderDescription, tagName, hreference) //constructor
+{
+ //constant data
+ this.desc = folderDescription
+ this.tagName = tagName
+ this.hreference = hreference
+ this.id = -1
+ this.navObj = 0
+ this.iconImg = 0
+ this.nodeImg = 0
+ this.isLastNode = 0
+
+ //dynamic data
+ this.isOpen = true
+ this.iconSrc = "ftv2folderopen.png"
+ this.children = new Array
+ this.nChildren = 0
+
+ //methods
+ this.initialize = initializeFolder
+ this.setState = setStateFolder
+ this.addChild = addChild
+ this.createIndex = createEntryIndex
+ this.hide = hideFolder
+ this.display = display
+ this.renderOb = drawFolder
+ this.totalHeight = totalHeight
+ this.subEntries = folderSubEntries
+ this.outputLink = outputFolderLink
+}
+
+function setStateFolder(isOpen)
+{
+ var subEntries
+ var totalHeight
+ var fIt = 0
+ var i=0
+
+ if (isOpen == this.isOpen)
+ return
+
+ if (browserVersion == 2)
+ {
+ totalHeight = 0
+ for (i=0; i < this.nChildren; i++)
+ totalHeight = totalHeight + this.children[i].navObj.clip.height
+ subEntries = this.subEntries()
+ if (this.isOpen)
+ totalHeight = 0 - totalHeight
+ for (fIt = this.id + subEntries + 1; fIt < nEntries; fIt++)
+ indexOfEntries[fIt].navObj.moveBy(0, totalHeight)
+ }
+ this.isOpen = isOpen
+ propagateChangesInState(this)
+}
+
+function propagateChangesInState(folder)
+{
+ var i=0
+
+ if (folder.isOpen)
+ {
+ if (folder.nodeImg)
+ if (folder.isLastNode)
+ folder.nodeImg.src = "ftv2mlastnode.png"
+ else
+ folder.nodeImg.src = "ftv2mnode.png"
+ folder.iconImg.src = "ftv2folderopen.png"
+ for (i=0; i")
+ leftSide = leftSide + ""
+ this.isLastNode = 1
+ }
+ else
+ {
+ this.renderOb(leftSide + auxEv + "")
+ leftSide = leftSide + ""
+ this.isLastNode = 0
+ }
+ else
+ this.renderOb("")
+
+ if (nc > 0)
+ {
+ level = level + 1
+ for (i=0 ; i < this.nChildren; i++)
+ {
+ if (i == this.nChildren-1)
+ this.children[i].initialize(level, 1, leftSide)
+ else
+ this.children[i].initialize(level, 0, leftSide)
+ }
+ }
+}
+
+function drawFolder(leftSide)
+{
+ if (browserVersion == 2) {
+ if (!doc.yPos)
+ doc.yPos=8
+ doc.write("")
+ }
+
+ doc.write("\n")
+ doc.write("\n
\n")
+
+ if (browserVersion == 2) {
+ doc.write("")
+ }
+ if (browserVersion == 3) {
+ doc.write("
")
+ }
+
+ if (browserVersion == 1) {
+ this.navObj = doc.all["folder"+this.id]
+ this.iconImg = doc.all["folderIcon"+this.id]
+ this.nodeImg = doc.all["nodeIcon"+this.id]
+ } else if (browserVersion == 2) {
+ this.navObj = doc.layers["folder"+this.id]
+ this.iconImg = this.navObj.document.images["folderIcon"+this.id]
+ this.nodeImg = this.navObj.document.images["nodeIcon"+this.id]
+ doc.yPos=doc.yPos+this.navObj.clip.height
+ } else if (browserVersion == 3) {
+ this.navObj = doc.getElementById("folder"+this.id)
+ this.iconImg = doc.images.namedItem("folderIcon"+this.id)
+ this.nodeImg = doc.images.namedItem("nodeIcon"+this.id)
+ }
+}
+
+function outputFolderLink()
+{
+ if (this.hreference)
+ {
+ doc.write(" 0)
+ doc.write("onClick='javascript:clickOnFolder("+this.id+")'")
+ doc.write(">")
+ }
+ else
+ doc.write("")
+}
+
+function addChild(childNode)
+{
+ this.children[this.nChildren] = childNode
+ this.nChildren++
+ return childNode
+}
+
+function folderSubEntries()
+{
+ var i = 0
+ var se = this.nChildren
+
+ for (i=0; i < this.nChildren; i++){
+ if (this.children[i].children) //is a folder
+ se = se + this.children[i].subEntries()
+ }
+
+ return se
+}
+
+
+// Definition of class Item (a document or link inside a Folder)
+// *************************************************************
+
+function Item(itemDescription, tagName, itemLink) // Constructor
+{
+ // constant data
+ this.desc = itemDescription
+ this.tagName = tagName
+ this.link = itemLink
+ this.id = -1 //initialized in initalize()
+ this.navObj = 0 //initialized in render()
+ this.iconImg = 0 //initialized in render()
+ this.iconSrc = "ftv2doc.png"
+
+ // methods
+ this.initialize = initializeItem
+ this.createIndex = createEntryIndex
+ this.hide = hideItem
+ this.display = display
+ this.renderOb = drawItem
+ this.totalHeight = totalHeight
+}
+
+function hideItem()
+{
+ if (browserVersion == 1 || browserVersion == 3) {
+ if (this.navObj.style.display == "none")
+ return
+ this.navObj.style.display = "none"
+ } else {
+ if (this.navObj.visibility == "hidden")
+ return
+ this.navObj.visibility = "hidden"
+ }
+}
+
+function initializeItem(level, lastNode, leftSide)
+{
+ this.createIndex()
+
+ if (level>0)
+ if (lastNode) //the last 'brother' in the children array
+ {
+ this.renderOb(leftSide + "| ")
+ doc.write(leftSide)
+ this.outputLink()
+ doc.write(" | \n") + if (USETEXTLINKS) + { + this.outputLink() + doc.write(this.desc + "") + } + else + doc.write(this.desc) + if (this.tagName!="") + { + doc.write(" [external]") + } + doc.write(" | ") + doc.write("\n
")
+ leftSide = leftSide + ""
+ }
+ else
+ {
+ this.renderOb(leftSide + "")
+ leftSide = leftSide + ""
+ }
+ else
+ this.renderOb("")
+}
+
+function drawItem(leftSide)
+{
+ if (browserVersion == 2)
+ doc.write("")
+
+ doc.write("\n\n")
+ doc.write("
\n")
+
+ if (browserVersion == 2)
+ doc.write("")
+ if (browserVersion == 3)
+ doc.write("
")
+
+ if (browserVersion == 1) {
+ this.navObj = doc.all["item"+this.id]
+ this.iconImg = doc.all["itemIcon"+this.id]
+ } else if (browserVersion == 2) {
+ this.navObj = doc.layers["item"+this.id]
+ this.iconImg = this.navObj.document.images["itemIcon"+this.id]
+ doc.yPos=doc.yPos+this.navObj.clip.height
+ } else if (browserVersion == 3) {
+ this.navObj = doc.getElementById("item"+this.id)
+ this.iconImg = doc.images.namedItem("itemIcon"+this.id)
+ }
+}
+
+
+// Methods common to both objects (pseudo-inheritance)
+// ********************************************************
+
+function display()
+{
+ if (browserVersion == 1 || browserVersion == 3)
+ this.navObj.style.display = "block"
+ else
+ this.navObj.visibility = "show"
+}
+
+function createEntryIndex()
+{
+ this.id = nEntries
+ indexOfEntries[nEntries] = this
+ nEntries++
+}
+
+// total height of subEntries open
+function totalHeight() //used with browserVersion == 2
+{
+ var h = this.navObj.clip.height
+ var i = 0
+
+ if (this.isOpen) //is a folder and _is_ open
+ for (i=0 ; i < this.nChildren; i++)
+ h = h + this.children[i].totalHeight()
+
+ return h
+}
+
+
+// Events
+// *********************************************************
+
+function clickOnFolder(folderId)
+{
+ var clicked = indexOfEntries[folderId]
+
+ if (!clicked.isOpen)
+ clickOnNode(folderId)
+
+ return
+
+ if (clicked.isSelected)
+ return
+}
+
+function clickOnNode(folderId)
+{
+ var clickedFolder = 0
+ var state = 0
+
+ clickedFolder = indexOfEntries[folderId]
+ state = clickedFolder.isOpen
+
+ clickedFolder.setState(!state) //open<->close
+}
+
+function initializeDocument()
+{
+ doc = document;
+ if (doc.all)
+ browserVersion = 1 //IE4
+ else
+ if (doc.layers)
+ browserVersion = 2 //NS4
+ else if(navigator.userAgent.toLowerCase().indexOf('gecko') != -1)
+ browserVersion = 3 //mozilla
+ else
+ browserVersion = 0 //other
+
+ foldersTree.initialize(0, 1, "")
+ foldersTree.display()
+
+ if (browserVersion > 0)
+ {
+ if(browserVersion != 3)
+ doc.write("| ")
+ doc.write(leftSide)
+ if (this.link!="")
+ {
+ doc.write("")
+ }
+ doc.write(" | \n") + if (USETEXTLINKS && this.link!="") + doc.write("" + this.desc + "") + else + doc.write(this.desc) + if (this.tagName!="") + { + doc.write(" [external]"); + } + doc.write("\n |
Stall and Flush Unit
+
+[Hardware resources]
+
+
+
+
+
+
++
- +Requests to SFU
-
+
-
+
- stall requests
+ The SFU stalls all younger stages. However, by stalling-only, the current instruction is spawned into 2 instances. One of them must be killed (flushed). The the younger instance is killed (the previous stage is flushed).
+ Thus, a nop is introduced in the pipeline before the instruction wavefront.
+ If more than one stage request a stall at the same time, the older one has priority (the younger one will be stalled along with the others). Only after that, the younger one will be ackowledged its stall by means of appropriate stall and flush control signals.
+ Stall requests:-
+
- pavr_s3_stall_rq
+ - pavr_s5_stall_rq
+ - pavr_s6_stall_rq
- pavr_s3_stall_rq
- flush requests
+ The SFU simply flushes that stage.
+ More than one flush could be acknolewdged at the same time, without competition. However, all flush requests happen to request to flush the same pipeline stage, s2.
+ Flush requests:-
+
- pavr_s3_flush_s2_rq
+ - pavr_s4_flush_s2_rq
+ - pavr_s4_ret_flush_s2_rq
+ - pavr_s5_ret_flush_s2_rq
+ - pavr_s51_ret_flush_s2_rq
+ - pavr_s52_ret_flush_s2_rq
+ - pavr_s53_ret_flush_s2_rq
+ - pavr_s54_ret_flush_s2_rq
+ - pavr_s55_ret_flush_s2_rq
+
- pavr_s3_flush_s2_rq
- branch requests
+ The SFU flushes stages s2...s5, because the corresponding instructions were already uselessly fetched, and requests the PC to be loaded with the branch relative jump address.
+ Branch requests:-
+
- pavr_s6_branch_rq
+
- pavr_s6_branch_rq
- skip requests
+ The SFU treats skips as branches that have the relative jump address equal to 0, 1 or 2, depending on the skip condition and on next instruction's length (16/32 bits).
+ Skip requests:-
+
- pavr_s6_skip_rq
+ - pavr_s61_skip_rq
- pavr_s6_skip_rq
- nop requests
+ The SFU stalls all younger instructions. The current instruction is spawned into 2 instances. The older instance is killed (the very same stage that requested the nop stage is flushed).
+ Thus, a nop is introduced in the pipeline after the instruction wavefront.
+ In order to do that, a micro-state machine is needed outside the pipeline, because otherwise that stage would undefinitely stall itself.
+ Nop requests:
+-
+
- pavr_s4_nop_rq
+
- pavr_s4_nop_rq
- stall requests
- +SFU control signals
-
+Each main pipeline stage (s1-s6) has 2 kinds of control signals, that are generated by the SFU:
-
+
- stall control
+ All registers in this stage are instructed to remain unchanged All possible requests to hardware resources (such as RF, IOF, BPU, DACU, SREG, etc) are reseted (to 0). - flush control
+ All registers in this stage are reseted (to 0), to a most "benign" state (a nop). Also, all requests to hardware resources are reseted.
+ Each main pipeline stage has an associated flag that determines whether or not that stage has the right to access hardware resources. These flags are also managed by the SFU.
+ Hardware resources enabling flags:-
+
- pavr_s1_hwrq_en
- pavr_s2_hwrq_en
- pavr_s3_hwrq_en
- pavr_s4_hwrq_en
- pavr_s5_hwrq_en
- pavr_s6_hwrq_en
- stall control
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: ftv2node.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: ftv2node.png
===================================================================
--- ftv2node.png (nonexistent)
+++ ftv2node.png (revision 6)
ftv2node.png
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: group__pavr__hwres__iof__rampzwr.html
===================================================================
--- group__pavr__hwres__iof__rampzwr.html (nonexistent)
+++ group__pavr__hwres__iof__rampzwr.html (revision 6)
@@ -0,0 +1,36 @@
+
+
+RAMPZ port
+
+
+
+
+Main Page Modules Related Pages
+
RAMPZ port
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__pipeline.html
===================================================================
--- group__pavr__pipeline.html (nonexistent)
+++ group__pavr__pipeline.html (revision 6)
@@ -0,0 +1,30 @@
+
+
+Pipeline details
+
+
+
+
+Main Page Modules Related Pages
+
Pipeline details
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: tree.js
===================================================================
--- tree.js (nonexistent)
+++ tree.js (revision 6)
@@ -0,0 +1,58 @@
+foldersTree = gFld("Pipelined AVR microcontroller", "", "")
+ insDoc(foldersTree, gLnk("Main Page", "", "main.html"))
+aux1 = insFld(foldersTree, gFld("Modules", "", "modules.html"))
+ insDoc(aux1, gLnk("Introduction", "", "group__pavr__intro.html"))
+ insDoc(aux1, gLnk("AVR architecture", "", "group__pavr__avrarch.html"))
+ insDoc(aux1, gLnk("AVR instruction set", "", "group__pavr__avris.html"))
+ aux2 = insFld(aux1, gFld("Implementation", "", "group__pavr__implementation.html"))
+ insDoc(aux2, gLnk("Pipeline structure", "", "group__pavr__control.html"))
+ aux3 = insFld(aux2, gFld("Hardware resources", "", "group__pavr__hwres.html"))
+ aux4 = insFld(aux3, gFld("Register File", "", "group__pavr__hwres__rf.html"))
+ insDoc(aux4, gLnk("Read port 1", "", "group__pavr__hwres__rf__rd1.html"))
+ insDoc(aux4, gLnk("Read port 2", "", "group__pavr__hwres__rf__rd2.html"))
+ insDoc(aux4, gLnk("Write port", "", "group__pavr__hwres__rf__wr.html"))
+ insDoc(aux4, gLnk("X port", "", "group__pavr__hwres__rf__xwr.html"))
+ insDoc(aux4, gLnk("Y port", "", "group__pavr__hwres__rf__ywr.html"))
+ insDoc(aux4, gLnk("Z port", "", "group__pavr__hwres__rf__zwr.html"))
+ aux4 = insFld(aux3, gFld("Bypass Unit", "", "group__pavr__hwres__bpu.html"))
+ insDoc(aux4, gLnk("Bypass chain 0", "", "group__pavr__hwres__bpr0.html"))
+ insDoc(aux4, gLnk("Bypass chain 1", "", "group__pavr__hwres__bpr1.html"))
+ insDoc(aux4, gLnk("Bypass chain 2", "", "group__pavr__hwres__bpr2.html"))
+ aux4 = insFld(aux3, gFld("IO File", "", "group__pavr__hwres__iof.html"))
+ insDoc(aux4, gLnk("General IO port", "", "group__pavr__hwres__iof__gen.html"))
+ insDoc(aux4, gLnk("SREG port", "", "group__pavr__hwres__iof__sregwr.html"))
+ insDoc(aux4, gLnk("SP port", "", "group__pavr__hwres__iof__spwr.html"))
+ insDoc(aux4, gLnk("RAMPX port", "", "group__pavr__hwres__iof__rampxwr.html"))
+ insDoc(aux4, gLnk("RAMPY port", "", "group__pavr__hwres__iof__rampywr.html"))
+ insDoc(aux4, gLnk("RAMPZ port", "", "group__pavr__hwres__iof__rampzwr.html"))
+ insDoc(aux4, gLnk("RAMPD port", "", "group__pavr__hwres__iof__rampdwr.html"))
+ insDoc(aux4, gLnk("EIND port", "", "group__pavr__hwres__iof__eindwr.html"))
+ aux5 = insFld(aux4, gFld("Peripherals", "", "group__pavr__hwres__iof__perif.html"))
+ insDoc(aux5, gLnk("Port A", "", "group__pavr__hwres__iof__perif__pa.html"))
+ insDoc(aux5, gLnk("External interrupt 0", "", "group__pavr__hwres__iof__perif__int0.html"))
+ insDoc(aux5, gLnk("Timer 0", "", "group__pavr__hwres__iof__perif__t0.html"))
+ insDoc(aux3, gLnk("ALU", "", "group__pavr__hwres__alu.html"))
+ insDoc(aux3, gLnk("DACU", "", "group__pavr__hwres__dacu.html"))
+ insDoc(aux3, gLnk("Data Memory", "", "group__pavr__hwres__dm.html"))
+ insDoc(aux3, gLnk("Program Memory", "", "group__pavr__hwres__pm.html"))
+ insDoc(aux3, gLnk("Stall and Flush Unit", "", "group__pavr__hwres__sfu.html"))
+ aux3 = insFld(aux2, gFld("Pipeline details", "", "group__pavr__pipeline.html"))
+ insDoc(aux3, gLnk("ALU", "", "group__pavr__pipeline__alu.html"))
+ insDoc(aux3, gLnk("IOF access", "", "group__pavr__pipeline__iof.html"))
+ insDoc(aux3, gLnk("DACU access", "", "group__pavr__pipeline__dacu.html"))
+ insDoc(aux3, gLnk("Jumps", "", "group__pavr__pipeline__jumps.html"))
+ insDoc(aux3, gLnk("Branches", "", "group__pavr__pipeline__branches.html"))
+ insDoc(aux3, gLnk("Skips", "", "group__pavr__pipeline__skips.html"))
+ insDoc(aux3, gLnk("Calls", "", "group__pavr__pipeline__calls.html"))
+ insDoc(aux3, gLnk("Returns", "", "group__pavr__pipeline__returns.html"))
+ insDoc(aux3, gLnk("Interrupts", "", "group__pavr__pipeline__int.html"))
+ insDoc(aux3, gLnk("Others", "", "group__pavr__pipeline__others.html"))
+ aux2 = insFld(aux1, gFld("Testing", "", "group__pavr__test.html"))
+ insDoc(aux2, gLnk("Bugs", "", "group__pavr__test__bugs.html"))
+ insDoc(aux2, gLnk("FPGA prototyping", "", "group__pavr__fpga.html"))
+ insDoc(aux1, gLnk("Sources", "", "group__pavr__src.html"))
+ insDoc(aux1, gLnk("References", "", "group__pavr__ref.html"))
+ insDoc(aux1, gLnk("Some final thoughts", "", "group__pavr__thoughts.html"))
+ insDoc(aux1, gLnk("About ...", "", "group__pavr__about.html"))
+aux1 = insFld(foldersTree, gFld("Related Pages", "", "pages.html"))
+ insDoc(aux1, gLnk("Todo List", "", "todo.html"))
Index: ftv2mlastnode.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: ftv2mlastnode.png
===================================================================
--- ftv2mlastnode.png (nonexistent)
+++ ftv2mlastnode.png (revision 6)
RAMPZ port
+
+[IO File]
+
- +RAMPZ port connectivity
-
+
+++
+
+
- +Requests to this port
-
+
-
+
- pavr_s5_ldstincrampz_xwr_rq
+ Needed by loads and stores with postincrement.
+ Only modify RAMPZ if the controller has more than 64 KB of Data Mamory. - pavr_s5_ldstdecrampz_xwr_rq
+ Needed by loads and stores with predecrement.
+ Only modify RAMPZ if the controller has more than 64 KB of Data Mamory.
+
+
- pavr_s5_ldstincrampz_xwr_rq
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__pipeline.html
===================================================================
--- group__pavr__pipeline.html (nonexistent)
+++ group__pavr__pipeline.html (revision 6)
@@ -0,0 +1,30 @@
+
+
+Pipeline details
+
+[Implementation]
+
Modules | |
| ALU | |
| IOF access | |
| DACU access | |
| Jumps | |
| Branches | |
| Skips | |
| Calls | |
| Returns | |
| Interrupts | |
| Others | |
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: tree.js
===================================================================
--- tree.js (nonexistent)
+++ tree.js (revision 6)
@@ -0,0 +1,58 @@
+foldersTree = gFld("Pipelined AVR microcontroller", "", "")
+ insDoc(foldersTree, gLnk("Main Page", "", "main.html"))
+aux1 = insFld(foldersTree, gFld("Modules", "", "modules.html"))
+ insDoc(aux1, gLnk("Introduction", "", "group__pavr__intro.html"))
+ insDoc(aux1, gLnk("AVR architecture", "", "group__pavr__avrarch.html"))
+ insDoc(aux1, gLnk("AVR instruction set", "", "group__pavr__avris.html"))
+ aux2 = insFld(aux1, gFld("Implementation", "", "group__pavr__implementation.html"))
+ insDoc(aux2, gLnk("Pipeline structure", "", "group__pavr__control.html"))
+ aux3 = insFld(aux2, gFld("Hardware resources", "", "group__pavr__hwres.html"))
+ aux4 = insFld(aux3, gFld("Register File", "", "group__pavr__hwres__rf.html"))
+ insDoc(aux4, gLnk("Read port 1", "", "group__pavr__hwres__rf__rd1.html"))
+ insDoc(aux4, gLnk("Read port 2", "", "group__pavr__hwres__rf__rd2.html"))
+ insDoc(aux4, gLnk("Write port", "", "group__pavr__hwres__rf__wr.html"))
+ insDoc(aux4, gLnk("X port", "", "group__pavr__hwres__rf__xwr.html"))
+ insDoc(aux4, gLnk("Y port", "", "group__pavr__hwres__rf__ywr.html"))
+ insDoc(aux4, gLnk("Z port", "", "group__pavr__hwres__rf__zwr.html"))
+ aux4 = insFld(aux3, gFld("Bypass Unit", "", "group__pavr__hwres__bpu.html"))
+ insDoc(aux4, gLnk("Bypass chain 0", "", "group__pavr__hwres__bpr0.html"))
+ insDoc(aux4, gLnk("Bypass chain 1", "", "group__pavr__hwres__bpr1.html"))
+ insDoc(aux4, gLnk("Bypass chain 2", "", "group__pavr__hwres__bpr2.html"))
+ aux4 = insFld(aux3, gFld("IO File", "", "group__pavr__hwres__iof.html"))
+ insDoc(aux4, gLnk("General IO port", "", "group__pavr__hwres__iof__gen.html"))
+ insDoc(aux4, gLnk("SREG port", "", "group__pavr__hwres__iof__sregwr.html"))
+ insDoc(aux4, gLnk("SP port", "", "group__pavr__hwres__iof__spwr.html"))
+ insDoc(aux4, gLnk("RAMPX port", "", "group__pavr__hwres__iof__rampxwr.html"))
+ insDoc(aux4, gLnk("RAMPY port", "", "group__pavr__hwres__iof__rampywr.html"))
+ insDoc(aux4, gLnk("RAMPZ port", "", "group__pavr__hwres__iof__rampzwr.html"))
+ insDoc(aux4, gLnk("RAMPD port", "", "group__pavr__hwres__iof__rampdwr.html"))
+ insDoc(aux4, gLnk("EIND port", "", "group__pavr__hwres__iof__eindwr.html"))
+ aux5 = insFld(aux4, gFld("Peripherals", "", "group__pavr__hwres__iof__perif.html"))
+ insDoc(aux5, gLnk("Port A", "", "group__pavr__hwres__iof__perif__pa.html"))
+ insDoc(aux5, gLnk("External interrupt 0", "", "group__pavr__hwres__iof__perif__int0.html"))
+ insDoc(aux5, gLnk("Timer 0", "", "group__pavr__hwres__iof__perif__t0.html"))
+ insDoc(aux3, gLnk("ALU", "", "group__pavr__hwres__alu.html"))
+ insDoc(aux3, gLnk("DACU", "", "group__pavr__hwres__dacu.html"))
+ insDoc(aux3, gLnk("Data Memory", "", "group__pavr__hwres__dm.html"))
+ insDoc(aux3, gLnk("Program Memory", "", "group__pavr__hwres__pm.html"))
+ insDoc(aux3, gLnk("Stall and Flush Unit", "", "group__pavr__hwres__sfu.html"))
+ aux3 = insFld(aux2, gFld("Pipeline details", "", "group__pavr__pipeline.html"))
+ insDoc(aux3, gLnk("ALU", "", "group__pavr__pipeline__alu.html"))
+ insDoc(aux3, gLnk("IOF access", "", "group__pavr__pipeline__iof.html"))
+ insDoc(aux3, gLnk("DACU access", "", "group__pavr__pipeline__dacu.html"))
+ insDoc(aux3, gLnk("Jumps", "", "group__pavr__pipeline__jumps.html"))
+ insDoc(aux3, gLnk("Branches", "", "group__pavr__pipeline__branches.html"))
+ insDoc(aux3, gLnk("Skips", "", "group__pavr__pipeline__skips.html"))
+ insDoc(aux3, gLnk("Calls", "", "group__pavr__pipeline__calls.html"))
+ insDoc(aux3, gLnk("Returns", "", "group__pavr__pipeline__returns.html"))
+ insDoc(aux3, gLnk("Interrupts", "", "group__pavr__pipeline__int.html"))
+ insDoc(aux3, gLnk("Others", "", "group__pavr__pipeline__others.html"))
+ aux2 = insFld(aux1, gFld("Testing", "", "group__pavr__test.html"))
+ insDoc(aux2, gLnk("Bugs", "", "group__pavr__test__bugs.html"))
+ insDoc(aux2, gLnk("FPGA prototyping", "", "group__pavr__fpga.html"))
+ insDoc(aux1, gLnk("Sources", "", "group__pavr__src.html"))
+ insDoc(aux1, gLnk("References", "", "group__pavr__ref.html"))
+ insDoc(aux1, gLnk("Some final thoughts", "", "group__pavr__thoughts.html"))
+ insDoc(aux1, gLnk("About ...", "", "group__pavr__about.html"))
+aux1 = insFld(foldersTree, gFld("Related Pages", "", "pages.html"))
+ insDoc(aux1, gLnk("Todo List", "", "todo.html"))
Index: ftv2mlastnode.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: ftv2mlastnode.png
===================================================================
--- ftv2mlastnode.png (nonexistent)
+++ ftv2mlastnode.png (revision 6)
ftv2mlastnode.png
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: pavr_hwres_rf_ywr_01.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: pavr_hwres_rf_ywr_01.gif
===================================================================
--- pavr_hwres_rf_ywr_01.gif (nonexistent)
+++ pavr_hwres_rf_ywr_01.gif (revision 6)
pavr_hwres_rf_ywr_01.gif
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: group__pavr__pipeline__branches.html
===================================================================
--- group__pavr__pipeline__branches.html (nonexistent)
+++ group__pavr__pipeline__branches.html (revision 6)
@@ -0,0 +1,33 @@
+
+
+Branches
+
+
+
+
+Main Page Modules Related Pages
+
Branches
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__about.html
===================================================================
--- group__pavr__about.html (nonexistent)
+++ group__pavr__about.html (revision 6)
@@ -0,0 +1,34 @@
+
+
+About ...
+
+
+
+
+Main Page Modules Related Pages
+
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: ftv2link.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: ftv2link.png
===================================================================
--- ftv2link.png (nonexistent)
+++ ftv2link.png (revision 6)
Branches
+
+[Pipeline details]
+
- +A few details
-
+The branches condition a 7 bit relative jump by the value of a bit in the Status Register.
+ If the branch condition is not met, no further action is taken. However, if the branch condition is evaluated as true, then all previous stages are flushed and the Stall and Flush Unit is requestd a branch. The SFU, in turn, asks the PM manager permission to access the Program Memory and modify the program flow.
+ Branches take place in stage s6.
+
+ Not taken branches take 2 clocks, while taken branches take 4 clocks.
+
- +Branch state machine
-
+
+++
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__about.html
===================================================================
--- group__pavr__about.html (nonexistent)
+++ group__pavr__about.html (revision 6)
@@ -0,0 +1,34 @@
+
+
+About ...
- +Project
-
+pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+ The increase in speed comes from a relatively deep pipeline.
- +Version
- +0.32
- +Date
- +2002 August 07
- +Author
-
+Doru Cuturela, doruu@yahoo.com
+
- +Licensing
-
+This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
+ This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- +Note
-
+The design effort for this project was about 6 months (2002, Feb-Aug), one man working.
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: ftv2link.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: ftv2link.png
===================================================================
--- ftv2link.png (nonexistent)
+++ ftv2link.png (revision 6)
ftv2link.png
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: group__pavr__test.html
===================================================================
--- group__pavr__test.html (nonexistent)
+++ group__pavr__test.html (revision 6)
@@ -0,0 +1,199 @@
+
+
+Testing
+
+
+
+
+Main Page Modules Related Pages
+
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__control.html
===================================================================
--- group__pavr__control.html (nonexistent)
+++ group__pavr__control.html (revision 6)
@@ -0,0 +1,123 @@
+
+
+Pipeline structure
+
+
+
+
+Main Page Modules Related Pages
+
Pipeline structure
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_util.vhd
===================================================================
--- pavr_util.vhd (nonexistent)
+++ pavr_util.vhd (revision 6)
@@ -0,0 +1,363 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This file defines utilities used throughout pAVR sources:
+-- - Bypass Unit access function
+-- The input address is compared to all bypass entries flagged as active
+-- (actually holding data). If match, read data from that entry, and
+-- output it rather than the input data.
+-- Multiple match can occur on an address.
+-- If multiple match, the newest entry wins.
+-- If 2 simultaneous entries match, the one in bypass chain having lower
+-- index wins (that is, chain 0 beats chain 1 that beats chain 2). However,
+-- this shouldn't happen (the controller should never fill the Bypass
+-- registers with such data). That would indicate a design bug.
+-- - Interrupt arbitrer function
+-- This function prioritizes the interrupts.
+-- Interfaces signals:
+-- - input vector
+-- This holds all interrupt flags. Interrupts trying to `come out'
+-- are in 1 logic.
+-- - output vector
+-- All losing interrupts from input are disabled (0 logic). The winer
+-- takes it all (1 logic).
+-- The winner is the rightmost line that is in 1 logic.
+--
+
+
+
+--
+library work;
+use work.std_util.all;
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+
+package pavr_util is
+
+ -- Reading through Bypass Unit
+ function read_through_bpu(vin: std_logic_vector; vin_addr: std_logic_vector;
+ -- Bypass chain 0
+ bpr00: std_logic_vector; bpr00_addr: std_logic_vector; bpr00_active: std_logic;
+ bpr01: std_logic_vector; bpr01_addr: std_logic_vector; bpr01_active: std_logic;
+ bpr02: std_logic_vector; bpr02_addr: std_logic_vector; bpr02_active: std_logic;
+ bpr03: std_logic_vector; bpr03_addr: std_logic_vector; bpr03_active: std_logic;
+ -- Bypass chain 1
+ bpr10: std_logic_vector; bpr10_addr: std_logic_vector; bpr10_active: std_logic;
+ bpr11: std_logic_vector; bpr11_addr: std_logic_vector; bpr11_active: std_logic;
+ bpr12: std_logic_vector; bpr12_addr: std_logic_vector; bpr12_active: std_logic;
+ bpr13: std_logic_vector; bpr13_addr: std_logic_vector; bpr13_active: std_logic;
+ -- Bypass chain 2
+ bpr20: std_logic_vector; bpr20_addr: std_logic_vector; bpr20_active: std_logic;
+ bpr21: std_logic_vector; bpr21_addr: std_logic_vector; bpr21_active: std_logic;
+ bpr22: std_logic_vector; bpr22_addr: std_logic_vector; bpr22_active: std_logic;
+ bpr23: std_logic_vector; bpr23_addr: std_logic_vector; bpr23_active: std_logic
+ )
+ return std_logic_vector;
+
+ -- Prioritize interrupts
+ function prioritize_int(vin: std_logic_vector) return std_logic_vector;
+
+end;
+
+
+
+package body pavr_util is
+
+ -- Here, all data is expected to be 8 bits wide, and all addresses 5 bits wide.
+ -- Even though this could have been done length independent, pAVR will never
+ -- need that.
+ function read_through_bpu(vin: std_logic_vector; vin_addr: std_logic_vector;
+ bpr00: std_logic_vector; bpr00_addr: std_logic_vector; bpr00_active: std_logic;
+ bpr01: std_logic_vector; bpr01_addr: std_logic_vector; bpr01_active: std_logic;
+ bpr02: std_logic_vector; bpr02_addr: std_logic_vector; bpr02_active: std_logic;
+ bpr03: std_logic_vector; bpr03_addr: std_logic_vector; bpr03_active: std_logic;
+ bpr10: std_logic_vector; bpr10_addr: std_logic_vector; bpr10_active: std_logic;
+ bpr11: std_logic_vector; bpr11_addr: std_logic_vector; bpr11_active: std_logic;
+ bpr12: std_logic_vector; bpr12_addr: std_logic_vector; bpr12_active: std_logic;
+ bpr13: std_logic_vector; bpr13_addr: std_logic_vector; bpr13_active: std_logic;
+ bpr20: std_logic_vector; bpr20_addr: std_logic_vector; bpr20_active: std_logic;
+ bpr21: std_logic_vector; bpr21_addr: std_logic_vector; bpr21_active: std_logic;
+ bpr22: std_logic_vector; bpr22_addr: std_logic_vector; bpr22_active: std_logic;
+ bpr23: std_logic_vector; bpr23_addr: std_logic_vector; bpr23_active: std_logic
+ )
+ return std_logic_vector is
+ variable bpr00_match, bpr01_match, bpr02_match, bpr03_match,
+ bpr10_match, bpr11_match, bpr12_match, bpr13_match,
+ bpr20_match, bpr21_match, bpr22_match, bpr23_match : std_logic;
+ variable tmpv1, tmpv2, tmpv3, tmpv4: std_logic_vector(2 downto 0);
+ variable r: std_logic_vector(7 downto 0);
+ begin
+ r := vin;
+
+ bpr00_match := cmp_std_logic_vector(bpr00_addr, vin_addr);
+ bpr01_match := cmp_std_logic_vector(bpr01_addr, vin_addr);
+ bpr02_match := cmp_std_logic_vector(bpr02_addr, vin_addr);
+ bpr03_match := cmp_std_logic_vector(bpr03_addr, vin_addr);
+ bpr10_match := cmp_std_logic_vector(bpr10_addr, vin_addr);
+ bpr11_match := cmp_std_logic_vector(bpr11_addr, vin_addr);
+ bpr12_match := cmp_std_logic_vector(bpr12_addr, vin_addr);
+ bpr13_match := cmp_std_logic_vector(bpr13_addr, vin_addr);
+ bpr20_match := cmp_std_logic_vector(bpr20_addr, vin_addr);
+ bpr21_match := cmp_std_logic_vector(bpr21_addr, vin_addr);
+ bpr22_match := cmp_std_logic_vector(bpr22_addr, vin_addr);
+ bpr23_match := cmp_std_logic_vector(bpr23_addr, vin_addr);
+
+ tmpv1 := (bpr00_match and bpr00_active) & (bpr10_match and bpr10_active) & (bpr20_match and bpr20_active);
+ tmpv2 := (bpr01_match and bpr01_active) & (bpr11_match and bpr11_active) & (bpr21_match and bpr21_active);
+ tmpv3 := (bpr02_match and bpr02_active) & (bpr12_match and bpr12_active) & (bpr22_match and bpr22_active);
+ tmpv4 := (bpr03_match and bpr03_active) & (bpr13_match and bpr13_active) & (bpr23_match and bpr23_active);
+
+ case tmpv1 is
+ when "000" =>
+ case tmpv2 is
+ when "000" =>
+ case tmpv3 is
+ when "000" =>
+ case tmpv4 is
+ when "000" =>
+ null;
+ when "001" =>
+ r := bpr23;
+ when "010" =>
+ r := bpr13;
+ when others =>
+ r := bpr03;
+ end case;
+ when "001" =>
+ r := bpr22;
+ when "010" =>
+ r := bpr12;
+ when others =>
+ r := bpr02;
+ end case;
+ when "001" =>
+ r := bpr21;
+ when "010" =>
+ r := bpr11;
+ when others =>
+ r := bpr01;
+ end case;
+ when "001" =>
+ r := bpr20;
+ when "010" =>
+ r := bpr10;
+ when others =>
+ r := bpr00;
+ end case;
+
+ return r;
+ end;
+
+
+
+ -- Input: a vector that is built by interrupt flags.
+ -- Output: a vector derived from input, that has all elements zero, except for
+ -- the rightmost position where a 1 occurs in the input.
+ -- Both input and output have the width 32. That is, maximum 32 interrupt
+ -- sources are supported.
+ -- This should synthesize into an asynchronous device with about 5-6 elemetary
+ -- gates delay.
+ function prioritize_int(vin: std_logic_vector) return std_logic_vector is
+ variable vout: std_logic_vector(31 downto 0);
+ variable or16: std_logic;
+ variable or8: std_logic_vector(1 downto 0);
+ variable or4: std_logic_vector(3 downto 0);
+ variable or2: std_logic_vector(7 downto 0);
+ begin
+
+ or16 := vin( 0) or
+ vin( 1) or
+ vin( 2) or
+ vin( 3) or
+ vin( 4) or
+ vin( 5) or
+ vin( 6) or
+ vin( 7) or
+ vin( 8) or
+ vin( 9) or
+ vin(10) or
+ vin(11) or
+ vin(12) or
+ vin(13) or
+ vin(14) or
+ vin(15);
+
+ or8(0) := vin( 0) or
+ vin( 1) or
+ vin( 2) or
+ vin( 3) or
+ vin( 4) or
+ vin( 5) or
+ vin( 6) or
+ vin( 7);
+
+ or8(1) := vin(16) or
+ vin(17) or
+ vin(18) or
+ vin(19) or
+ vin(20) or
+ vin(21) or
+ vin(22) or
+ vin(23);
+
+ or4(0) := vin( 0) or
+ vin( 1) or
+ vin( 2) or
+ vin( 3);
+
+ or4(1) := vin( 8) or
+ vin( 9) or
+ vin(10) or
+ vin(11);
+
+ or4(2) := vin(16) or
+ vin(17) or
+ vin(18) or
+ vin(19);
+
+ or4(3) := vin(24) or
+ vin(25) or
+ vin(26) or
+ vin(27);
+
+ or2(0) := vin( 0) or
+ vin( 1);
+
+ or2(1) := vin( 4) or
+ vin( 5);
+
+ or2(2) := vin( 8) or
+ vin( 9);
+
+ or2(3) := vin(12) or
+ vin(13);
+
+ or2(4) := vin(16) or
+ vin(17);
+
+ or2(5) := vin(20) or
+ vin(21);
+
+ or2(6) := vin(24) or
+ vin(25);
+
+ or2(7) := vin(28) or
+ vin(29);
+
+ for i in 0 to 15 loop
+ vout(2*i) := vin(2*i);
+ vout(2*i+1) := vin(2*i+1) and (not vin(2*i));
+ end loop;
+
+ for i in 0 to 7 loop
+ vout(4*i) := vout(4*i) and ( or2(i));
+ vout(4*i+1) := vout(4*i+1) and ( or2(i));
+ vout(4*i+2) := vout(4*i+2) and (not or2(i));
+ vout(4*i+3) := vout(4*i+3) and (not or2(i));
+ end loop;
+
+ for i in 0 to 3 loop
+ vout(8*i) := vout(8*i) and ( or4(i));
+ vout(8*i+1) := vout(8*i+1) and ( or4(i));
+ vout(8*i+2) := vout(8*i+2) and ( or4(i));
+ vout(8*i+3) := vout(8*i+3) and ( or4(i));
+ vout(8*i+4) := vout(8*i+4) and (not or4(i));
+ vout(8*i+5) := vout(8*i+5) and (not or4(i));
+ vout(8*i+6) := vout(8*i+6) and (not or4(i));
+ vout(8*i+7) := vout(8*i+7) and (not or4(i));
+ end loop;
+
+ for i in 0 to 1 loop
+ vout(16*i ) := vout(16*i ) and ( or8(i));
+ vout(16*i+ 1) := vout(16*i+ 1) and ( or8(i));
+ vout(16*i+ 2) := vout(16*i+ 2) and ( or8(i));
+ vout(16*i+ 3) := vout(16*i+ 3) and ( or8(i));
+ vout(16*i+ 4) := vout(16*i+ 4) and ( or8(i));
+ vout(16*i+ 5) := vout(16*i+ 5) and ( or8(i));
+ vout(16*i+ 6) := vout(16*i+ 6) and ( or8(i));
+ vout(16*i+ 7) := vout(16*i+ 7) and ( or8(i));
+ vout(16*i+ 8) := vout(16*i+ 8) and (not or8(i));
+ vout(16*i+ 9) := vout(16*i+ 9) and (not or8(i));
+ vout(16*i+10) := vout(16*i+10) and (not or8(i));
+ vout(16*i+11) := vout(16*i+11) and (not or8(i));
+ vout(16*i+12) := vout(16*i+12) and (not or8(i));
+ vout(16*i+13) := vout(16*i+13) and (not or8(i));
+ vout(16*i+14) := vout(16*i+14) and (not or8(i));
+ vout(16*i+15) := vout(16*i+15) and (not or8(i));
+ end loop;
+
+ vout( 0) := vout( 0) and ( or16) ;
+ vout( 1) := vout( 1) and ( or16) ;
+ vout( 2) := vout( 2) and ( or16) ;
+ vout( 3) := vout( 3) and ( or16) ;
+ vout( 4) := vout( 4) and ( or16) ;
+ vout( 5) := vout( 5) and ( or16) ;
+ vout( 6) := vout( 6) and ( or16) ;
+ vout( 7) := vout( 7) and ( or16) ;
+ vout( 8) := vout( 8) and ( or16) ;
+ vout( 9) := vout( 9) and ( or16) ;
+ vout(10) := vout(10) and ( or16) ;
+ vout(11) := vout(11) and ( or16) ;
+ vout(12) := vout(12) and ( or16) ;
+ vout(13) := vout(13) and ( or16) ;
+ vout(14) := vout(14) and ( or16) ;
+ vout(15) := vout(15) and ( or16) ;
+ vout(16) := vout(16) and (not or16) ;
+ vout(17) := vout(17) and (not or16) ;
+ vout(18) := vout(18) and (not or16) ;
+ vout(19) := vout(19) and (not or16) ;
+ vout(20) := vout(20) and (not or16) ;
+ vout(21) := vout(21) and (not or16) ;
+ vout(22) := vout(22) and (not or16) ;
+ vout(23) := vout(23) and (not or16) ;
+ vout(24) := vout(24) and (not or16) ;
+ vout(25) := vout(25) and (not or16) ;
+ vout(26) := vout(26) and (not or16) ;
+ vout(27) := vout(27) and (not or16) ;
+ vout(28) := vout(28) and (not or16) ;
+ vout(29) := vout(29) and (not or16) ;
+ vout(30) := vout(30) and (not or16) ;
+ vout(31) := vout(31) and (not or16) ;
+
+ return vout;
+
+ end;
+
+
+end;
+--
Index: pavr_pipe_iof_01.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: pavr_pipe_iof_01.gif
===================================================================
--- pavr_pipe_iof_01.gif (nonexistent)
+++ pavr_pipe_iof_01.gif (revision 6)
Testing
Modules | |
| Bugs | |
| FPGA prototyping | |
Detailed Description
+- +Testing strategy
-
+When testing a certain entity, the following testing strategy was adopted:
-
+
- embed that entity into a larger one that also includes all other ingredients needed for a real-life simulation of the tested entity. Typical such `other ingredients' are RAMs and multiplexers.
- run custom VHDL tests that test as much as possible of the functionality of the device under test. Extreme cases are the first situations to be tested.
+ Two kinds of tests were conducted on pAVR:-
+
- every module of pAVR was separately tested as described in the testing strategy above.
- pAVR as whole was tested as described in the testing strategy above.
+
- +Testing pAVR modules
-
+Each pAVR module was separately tested.
+ The particular tests carried out are presented below, grouped by the entities under test:-
+
- utilities defined in `std_util.vhd'
+ The associated test file is `test_std_util.vhd'.
+ The utilities defined in `std_util.vhd' here are:-
+
- type conversion routines often used throughout the other source files in this project
- basic arithmetic functions
- sign and zero-extend functions
+ Both are tested in `test_std_util.vhd'.
+ Extreme cases and typical cases are considered.
+ - vector comparision function
+ Tested in `test_std_util.vhd'.
+ Extreme cases and typical cases are considered.
+
- ALU
+ The associated tests are defined in `test_pavr_alu.vhd'. They consist of checking the ALU output and flags output for all ALU opcodes, one by one, for all of these situations:-
+
- carry in = 0
- carry in = 1
- additions generate overflow
- substractions generate overflow
- Register File
+ The associated tests are defined in `test_pavr_register_file.vhd'.
+ The following tests are done:-
+
- read all ports, one at a time
-
+
- read port 1 (RFRD1)
- read port 2 (RFRD2)
- write port (RFWR)
- write pointer register X (RFXWR)
- write pointer register Y (RFYWR)
- write pointer register Z (RFZWR)
- combined RFRD1, RFRD2, RFWR
+ They should work simultaneousely. - combined RFXWR, RFYWR, RFZWR
+ They should work simultaneousely. - combined RFRD1, RFRD2, RFWR, RFXWR, RFYWR, RFZWR
+ That is, all RF ports are accessed simultaneousely. They should do their job.
+ However, note that the pointer registers are accessible for writting by their own ports but also by the RF write port. Writing them via pointer register write ports overwrites writing via general write port. Even though concurrent writing could happen in a perfectly legal AVR implementation, AVR's behavior is unpredictible (what write port has priority). We have chosen for pAVR the priority as mentioned above.
- read all ports, one at a time
- IO File
+ The associated tests are defined in `test_pavr_io_file.vhd'.
+ The following tests are performed on the IOF:-
+
- test the IOF general write/read/bit processing port.
+ Test all opcodes that this port is capable of:-
+
- wrbyte
- rdbyte
- clrbit
- setbit
- stbit
- ldbit
- test the IOF port A.
+ Port A is intended to offer to pAVR pin-level IO connectivity with the outside world.
+ Test reading from and writing to Port A.
+ Test that Port A pins correctly take the appropriate logic values (high, low, high Z or weak high). - test Timer 0.
-
+
- test Timer 0 prescaler.
- test Timer 0 overflow.
- test Timer 0 interrupt.
- test External Interrupt 0.
+ Test if each possible configuration (activation on low level, rising edge or falling edge) correctly triggers External Interrupt 0 flag.
- test the IOF general write/read/bit processing port.
- Data Memory
+ The tests defined in `test_pavr_dm.vhd' are simple read-write confirmations that the Data Memory does its job.
- utilities defined in `std_util.vhd'
- +Testing the pAVR entity
-
+pAVR as a whole was tested by building an upper entity that embedds a pAVR, its Program Memory and some multiplexers. Those multiplexers are meant to give Program Memory control to the test entity (for properly setting up Program Memory contents) or to pAVR (while pAVR is actually being monitored as it executes intructions from the Program Memory).
+
+ The binary file that will be executed by pAVR during the test is automatically loaded into the Program Memory using an ANSI C utility, TagScan. The test entity has a number of tags spread over the source code, as comments. The TagScan utility reads the binary file to be loaded, scans the test file, and inserts VHDL statements into the properly tagged places. These statements load the Program Memory using its own write port. This way of initializing the Program Memory seems more general (and surely more interesting) than using file IO VHDL functions.
+ The TagScan utility is also used for other purposes. For example, for inserting a certain header in all source files. It is heavily used as a general preprocessor.
+
+ Testing pAVR as a whole actually means designing and running binaries that put pAVR on extreme situations.
+ The following tests are done: +-
+
- Interrupts
+ This exercises pAVR interrupt handling.
+ All interrupts are tested.
+ The associated peripherals (Port A, Timer 0 and External Interrupt 0) are + put in a variety of conditions.
+ Results:
+ tbd + - General test
+ This is a hand-written assembler source that is meant to be assembled and + run on pAVR.
+ It exercises each of pAVR instructions, one by one.
+ It tries to put pAVR in most difficult situations, for each instruction. For + example, it exercises: +-
+
- concurrent stalls +
- stalls combined with 32 bit instructions +
- stalls combined with intructions that change the instruction flow +
- control hazard candidates (stress the Program Memory Manager and + the Stall and Flush Unit) +
- data hazard candidates (stress the Bypass Unit) +
+ Passed OK. The verification consisted of checking each instruction, each + intermediate result and each relevant intermediate internal state. ++
++ Assembler + Clocks + Instructions + CPI + + avrasm32, by Atmel + 667 + 361 + 1.85 + - Sieve
+ Sieve of Eratosthenes; finds the the first 100 prime numbers.
+ Written in ANSI C.
+ Results: ++
++ Compiler + Clocks + Instructions + CPI + + avr-gcc, O0 + 12170 + 8851 + 1.37 + + avr-gcc, O3 + 11946 + 8824 + 1.35 + - TagScan
+ Exercises string manipulating routines.
+ Written in ANSI C.
+ Results: ++
++ Compiler + Clocks + Instructions + CPI + + tbd + tbd + tbd + tbd + - C compiler
+ Written in ANSI C.
+ Results: ++
++ Compiler + Clocks + Instructions + CPI + + tbd + tbd + tbd + tbd + - Waves
+ Simulates waves on the surface of a liquid.
+ Written in ANSI C.
+ Uses floating point numbers (observation: the avr-gcc compiler seems to + take about 200 pAVR clocks per floating point operation).
+ A mesh of only 5x5 points is considered, and only 5 iterations + are done. Bigger values make the simulation unacceptably long on + the available computer.
+ + Checking the result is done by converting the array of 25 floats + into a scaled array of 25 chars, copying these chars from Data + Memory (by hand), constructing a 3D image of the result, and + comparing it to a reference 3D image.
+ + Results:
+ Passed OK. As expected, the chars array to be tested exactly matches + the reference array. ++
++ Compiler + Clocks + Instructions + CPI + + avr-gcc + 209,175 + 122,236 + 1.71 +
+ - Interrupts
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__control.html
===================================================================
--- group__pavr__control.html (nonexistent)
+++ group__pavr__control.html (revision 6)
@@ -0,0 +1,123 @@
+
+
+Pipeline structure
+
+[Implementation]
+
- +Shift-like flow
-
+pAVR has a pipeline with 6 stages:
-
+
- 1. read Program Memory (PM)
- 2. strobe Program Memory output into instruction register (INSTR)
- 3. decode instruction and read Register File (RFRD)
- 4. strobe Register File output (OPS)
- 5. execution or Unified Memory access (ALU)
- 6. write Register File (RFWR)
+++
+
+ Each pipeline stage is pretty much of an independent state machine.
+
+ Basically, each pipeline stage receives values from the previous one, in a shift-like flow. Only the `terminal' registers contain data actually used, the previous ones are used just for synchronization.
+ For example, this is how a particular hardware resource request flows through pipeline stages s3, s4 until it is processed in s5:
+
+++
+
+ Exceptions from this `normal' flow are the stall and flush actions, which can basically independently stall or reset to zero (force a nop into) any stage. Other exceptions are when several registers in such a chain are actually used, not only the terminal one.
+
+ Apart from the (main) pipeline stages above (stages s1-s6), there are a number of pipeline stages only needed by a few instructions (such as 16 bit arithmetic, some of the skips, returns): s61, s51, s52, s53 and s54. During these pipeline stages, the main stages are stalled.
+
+ Stages s1, s2 are common to all instructions. They bring the instruction from Program Memory (PM) into the instruction register (instruction fetch stages).
+ During stage s3, the instruction just read from PM is decoded. That is, the following pipeline stages (s4, s5, s6, s61, s51, s52, s53, s54) are instructed what to do, by means of dedicated registers.
+
+ At a given moment, a pipe stage stage can do one of the following actions:-
+
- execute normally
+ The registers in that stage are loaded with:-
+
- Values from the previous stage, if that stage is different from s1 or s2 or s3
- Some particular values if that stage is s1 or s2 (those values are set by the Program Memory manager)
- Values from the instruction decoder, if that stage is s3
- flush (execute nop)
+ All registers in that stage are reseted to zero. - stall
+ All registers in that stage are kept unchanged.
+
- +Hardware resource managing
-
+Pipeline stages can request access to hardware resources. Access to hardware resources is done via dedicated hardware resource managers (one manager per hardware resource; one VHDL process per manager).
+
+ Main hardware resources:-
+
- Register File (RF)
- Bypass Unit (BPU)
-
+
- Bypass Register 0 (Bypass chain 0) (BPR0)
- Bypass Register 1 (Bypass chain 1) (BPR1)
- Bypass Register 2 (Bypass chain 2) (BPR2)
- IO File (IOF)
- Status Register (SREG)
- Stack Pointer (SP)
- Arithmetic and Logic Unit (ALU)
- Data Access Control Unit (DACU)
- Program Memory (PM)
- Stall and Flush Unit (SFU)
+ Only one such request can be received by a given resource at a time. If multiple accesses are requested from a resource, its access manager will assert an error during simulation; that would indicate a design bug.
+ The pipeline is built so that each resource is normally accessed during a fixed pipeline stage:-
+
- RF is normally read in s3 and written in s6.
- IOF is normally read/written in s5.
- DM is normally read/written in s5.
- DACU is normally read/written in s5.
- PM is normally read in s1.
+ Exceptions are handled at the hardware resource managers level.
+
- +Stall and Flush Unit
-
+Because of the exceptions above, different pipeline stages can compete for a given hardware resource. A mechanism must be provided to handle hardware resource conflicts. The SFU implements this function, by arbitring hardware resource requests. The SFU stalls some instructions (some pipeline stages), while allowing others to execute.
+
+ Stall handling is done through two sets of signals:-
+
- SFU requests (SFU inputs)
-
+
- stall requests
- flush requests
- branch requests
- skip requests
- nop requests
- SFU control signals (SFU outputs)
-
+
- stall control
- flush control
+++
+
+ Each instruction has an embedded stall behavior, that is decoded by the instruction decoder.
+ Various instructions in the pipeline, in different execution phases, access the SFU exactly the same way they access any other hardware resources, through SFU access requests.
+ The SFU prioritizes stall/flush/branch/skip/nop requests and postpones younger instructions until older instructions free the hardware resources (SFU hardware resource including). The postponing process is done through the stall-flush controls, on a per-pipeline stage basis.
+ The `SFU rule': when a resource conflict appears, the older instruction wins.
+
+ Some instructions need to insert a nop before the instruction `wave front', for freeing hardware resources normally used by younger instructions. For example, loads must `steal' the Register File read port 1 from younger instructions.
+ Nops are inserted by stalling certain pipe stages and flushing other, or possibly the same, stages.
+ Other instructions need a nop after the instruction wave front, for the previous instruction to complete and free hardware resources. For example, stores must wait a clock, until the previous instruction frees the Register File write port.
+ The two situations differ pretty much from the point of view of the control structure. In the second situation, the instruction is required to stall and flush itself, which adds additional problems. These problems are solved by introducing a dedicated noping state machine in stage s4, whose only purpose is to introduce at most one nop after any instruction. On the other hand, introducing nops before an instruction wave front is straightforward, as any instruction can stall/flush younger instructions by means of SFU requests.
+
+ The specific SFU requests can be found here.
+ - SFU requests (SFU inputs)
- +Shadowing
-
+Let's consider the following situation: a load instruction reads the Data Memory during pipe stage s5. Suppose that next clock, an older instruction stalls s6, during which Data Memory output was supposed to be written into the Register File. After another clock, the stall is removed, and s6 requests to write the Register File, but the Data Memory output has changed during the stall. Corrupted data will be written into the Register File. With the shadow protocol, the Data Memory output is saved during the stall. When the stall is removed, the Register File is written with the saved data.
+
+ The shadow protocol
+ If a pipe stage is not permitted to place hardware resource requests, then mark every memory-like entity in that stage as having its output `shadowed', and write its associated shadow register with the corresponding data output. Else, mark it as `unshadowed'.
+ As long as the memory-like enity is marked `shadowed', it will be read (by whatever entity needs that) from its associated shadow register, rather than directly from its data output.
+ In order to enable shadowing during multiple, successive stalls, shadow memory-like entities only if they aren't already shadowed.
+
+ Basically, the condition that shadows a memory-like entity's output is `hardware resources are disabled during that stage'. However, there are exceptions. For example, LPM family instructions steal Program Memory access by stalling the instruction that would normally be fetched that time. By stalling, hardware resource requests become disabled in that pipe stage. Still, LPM family instructions must be able to access directly Program Memory output. Here, the PM must not be shadowed even though during its pipe stage s2 (during which PM is normally accessed) all hardware requests are disabled by default.
+ Fortunately, there are only a few such exceptions (holes through the shadow protocol). Overall, the shadow protocol is still a good idea, as it permits natural & automatic handling of a bunch of registers placed in delicate areas.
+
+
+
- +Todo:
-
+
-
+
- Branch prediction with hashed branch prediction table and 2 bit predictor.
- Super-RAM interfacing to Program Memory.
+ A super-RAM is a classic RAM with two supplemental lines: a mem_rq input and a mem_ack output. The device that writes/reads the super-RAM knows that it can place an access request when the memory signalizes it's ready via mem_ack. Only then, it can place an access request via mem_rq.
+ A super-RAM is a super-class for classic RAM. That is, a super-RAM becomes classic RAM if the RAM ignores mem_rq and keeps continousely mem_ack to 1.
+ The super-RAM protocol is so flexible that, as an extreme example, it can serially (!) interface the Program Memory to the controller. That is, about 2-3 wires instead of 38 wires, without needing to modify anything in the controller. Of course, that would come with a very large speed penalty, but it allows choosing the most advantageous compromise between the number of wires and speed. The only thing to be done is to add a serial to parallel converter, that complies to the super-RAM protocol.
+ After pAVR is made super-RAM compatible, it can run anyway from a regular RAM, as it runs now, by ignoring the two extra lines. Thus, nothing is removed, it's only added. No speed penalty should be payed.
+ A simple way to add the super-RAM interface is to force nops into the pipeline as long as the serial-to-parallel converter works on an instruction word.
+ - Modify stall handling so that no nops are required after the instruction wavefront. The instructions could take care of themselves. The idea is that a request to a hardware resource that is already in use by an older instruction, could automatically generate a stall.
+ That would:-
+
- generally simplify instruction handling
- make average instruction execution slightly faster.
+
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_util.vhd
===================================================================
--- pavr_util.vhd (nonexistent)
+++ pavr_util.vhd (revision 6)
@@ -0,0 +1,363 @@
+--
pavr_pipe_iof_01.gif
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+application/octet-stream
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Index: test_pavr_alu.vhd
===================================================================
--- test_pavr_alu.vhd (nonexistent)
+++ test_pavr_alu.vhd (revision 6)
@@ -0,0 +1,159 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- Test pAVR's ALU.
+-- Note that the ALU is an asynchronous device.
+-- Check ALU output and flags output for all ALU opcodes, one by one, for all of
+-- these situations:
+-- - carry in = 0
+-- - carry in = 1
+-- - additions generate overflow
+-- - substractions generate overflow
+-- There are 26 ALU opcodes to be checked for each situation.
+--
+
+
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+library work;
+use work.std_util.all;
+use work.pavr_util.all;
+use work.pavr_constants.all;
+
+
+entity test_alu is
+end;
+
+
+architecture test_alu_arch of test_alu is
+ signal clk: std_logic;
+ -- ALU inputs
+ signal alu_op1: std_logic_vector(15 downto 0);
+ signal alu_op2: std_logic_vector(7 downto 0);
+ signal alu_opcode: std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
+ signal alu_flagsin: std_logic_vector(5 downto 0);
+ -- ALU outputs
+ signal alu_out: std_logic_vector(15 downto 0);
+ signal alu_flagsout: std_logic_vector(5 downto 0);
+
+ -- Declare the ALU.
+ component pavr_alu
+ port(
+ pavr_alu_op1: in std_logic_vector(15 downto 0);
+ pavr_alu_op2: in std_logic_vector(7 downto 0);
+ pavr_alu_out: out std_logic_vector(15 downto 0);
+ pavr_alu_opcode: in std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
+ pavr_alu_flagsin: in std_logic_vector(5 downto 0);
+ pavr_alu_flagsout: out std_logic_vector(5 downto 0)
+ );
+ end component;
+ for all: pavr_alu use entity work.pavr_alu(pavr_alu_arch);
+
+begin
+
+ -- Instantiate the ALU.
+ pavr_alu_instance1: pavr_alu
+ port map(
+ alu_op1,
+ alu_op2,
+ alu_out,
+ alu_opcode,
+ alu_flagsin,
+ alu_flagsout
+ );
+
+
+ generate_clock:
+ process
+ begin
+ clk <= '1';
+ wait for 50 ns;
+ clk <= '0';
+ wait for 50 ns;
+ end process generate_clock;
+
+
+ test_main:
+ process
+ begin
+ wait for 10 ns;
+
+ -- For each of the following test patterns, check each of:
+ -- - input 1, input 2, flags input
+ -- - output, flags output
+
+ -- Test ALU output, for all ALU opcodes; carry in = 1.
+ for i in 0 to 25 loop
+ alu_op1 <= int_to_std_logic_vector(16#44F9#, alu_op1'length);
+ alu_op2 <= int_to_std_logic_vector(16#0A#, alu_op2'length);
+ alu_opcode <= int_to_std_logic_vector(i, alu_opcode'length);
+ alu_flagsin <= "000001";
+ wait until clk'event and clk='1';
+ end loop;
+
+ -- Test ALU output, for all ALU opcodes; carry in = 0.
+ for i in 0 to 25 loop
+ alu_op1 <= int_to_std_logic_vector(16#44F5#, alu_op1'length);
+ alu_op2 <= int_to_std_logic_vector(16#03#, alu_op2'length);
+ alu_opcode <= int_to_std_logic_vector(i, alu_opcode'length);
+ alu_flagsin <= "000000";
+ wait until clk'event and clk='1';
+ end loop;
+
+ -- Test ALU output, for all ALU opcodes; carry in = 1. Additions (on both 8 bits and 16 bits) will generate carry out = 1.
+ for i in 0 to 25 loop
+ alu_op1 <= int_to_std_logic_vector(16#FFF8#, alu_op1'length);
+ alu_op2 <= int_to_std_logic_vector(16#0C#, alu_op2'length);
+ alu_opcode <= int_to_std_logic_vector(i, alu_opcode'length);
+ alu_flagsin <= "000001";
+ wait until clk'event and clk='1';
+ end loop;
+
+ -- Test ALU output, for all ALU opcodes; carry in = 1. Substractions (on both 8 bits and 16 bits) will generate carry out = 1.
+ for i in 0 to 25 loop
+ alu_op1 <= int_to_std_logic_vector(16#0005#, alu_op1'length);
+ alu_op2 <= int_to_std_logic_vector(16#0C#, alu_op2'length);
+ alu_opcode <= int_to_std_logic_vector(i, alu_opcode'length);
+ alu_flagsin <= "000001";
+ wait until clk'event and clk='1';
+ end loop;
+
+ end process test_main;
+
+end;
+--
Index: group__pavr__hwres__rf__rd1.html
===================================================================
--- group__pavr__hwres__rf__rd1.html (nonexistent)
+++ group__pavr__hwres__rf__rd1.html (revision 6)
@@ -0,0 +1,36 @@
+
+
+Read port 1
+
+
+
+
+Main Page Modules Related Pages
+
Read port 1
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__avris.html
===================================================================
--- group__pavr__avris.html (nonexistent)
+++ group__pavr__avris.html (revision 6)
@@ -0,0 +1,170 @@
+
+
+AVR instruction set
+
+
+
+
+Main Page Modules Related Pages
+
+
+
+
+
+ * Multiplications are fully supported by the pipeline (in terms of timing, wires and registers). However, the multiplication module itself is null-defined in the ALU, and always returns zero for now. It will be defined and plugged into the ALU in a future version of pAVR.
+ ** Italicized instructions are currently not implemented in pAVR.
+ +
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
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===================================================================
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+++ ftv2folderclosed.png (revision 6)
Read port 1
+
+[Register File]
+
- +Register File read port 1 connectivity
-
+
+++
+
+
- +Requests to RF read port 1
-
+
-
+
- pavr_s3_rfrd1_rq
+ Most ALU-requiring instructions need to read an operand from RF read port 1 in the same clock as the instruction is decoded (here, "to read" = "to strobe the read input"). Activate the read signal if necessary, via RF read port 1 manager.
+ - pavr_s5_dacu_rfrd1_rq
+ Note 1: This a somehow `missplaced' RF read port 1 request. To keep the controller compatible with the AVR architecture, loads and stores must operate in the Unified Memory space, that includes Register File, IO File and Data Memory. Thus, it is possible for a LOAD to actually transfer, for example, data from RF to RF, rather than from DM to RF (depending on the addresses involved).
+ The DACU manager takes the decision which physical device has to be used, and places consequent calls to the appropriate hardware resource manager. This request is such a call.
+ Note 2: The same situation happens with `misplaced' RF writes in stores. The stores read from RF and can actually write any of RF, IOF or DM.
+
- pavr_s3_rfrd1_rq
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__avris.html
===================================================================
--- group__pavr__avris.html (nonexistent)
+++ group__pavr__avris.html (revision 6)
@@ -0,0 +1,170 @@
+
+
+AVR instruction set
| Arithmetic + | Bit & Others + | Transfer + | Jump + | Branch + | Call + |
|---|---|---|---|---|---|
|
+ ADD Rd, Rr + ADC Rd, Rr + ADIW Rd+1:Rd, K6 + + SUB Rd, Rr + SUBI Rd, K8 + SBC Rd, Rr + SBCI Rd, K8 + SBIW Rd+1:Rd, K6 + + INC Rd + DEC Rd + + AND Rd, Rr + ANDI Rd, K8 + OR Rd, Rr + ORI Rd, K8 + EOR Rd, Rr + + + + COM Rd + NEG Rd + CP Rd, Rr + CPC Rd, Rr + CPI Rd, K8 + SWAP Rd + + + LSR Rd + + ROR Rd + ASR Rd + + + MUL Rd, Rr* + MULS Rd, Rr + MULSU Rd, Rr + FMUL Rd, Rr + FMULS Rd, Rr + FMULSU Rd, Rr + + + |
+ BSET s + BCLR s + SBI A, b + CBI A, b + BST Rd, b + BLD Rd, b + + NOP + + BREAK** + SLEEP + WDR + + + |
+ MOV Rd, Rr + MOVW Rd+1:Rd, Rr+1:Rr + + IN Rd, A + OUT A, Rr + + PUSH Rr + POP Rr + + LDI Rd, K8 + LDS Rd, K16 + + LD Rd, X + LD Rd, -X + LD Rd, X+ + + LDD Rd, Y+K6 + LD Rd, -Y + LD Rd, Y+ + + LDD Rd, Z+K6 + LD Rd, -Z + LD Rd, Z+ + + STS K16, Rr + + ST X, Rr + ST -X, Rr + ST X+, Rr + + STD Y+K6, Rr + ST -Y, Rr + ST Y+, Rr + + STD Z+K6, Rr + ST -Z, Rr + ST Z+, Rr + + LPM + LPM Rd, Z + LPM Rd, Z+ + ELPM + ELPM Rd, Z + ELPM Rd, Z+ + + + SPM + + + |
+ RJMP K12 + IJMP + EIJMP + JMP K22 + + |
+ CPSE Rd, Rr + + SBRC Rr, b + SBRS Rr, b + + SBIC A, b + SBIS A, b + + BRBC s, K7 + BRBS s, K7 + + |
+ RCALL K12 + ICALL + EICALL + CALL K22 + + RET + RETI + + |
+ ** Italicized instructions are currently not implemented in pAVR.
+ +
+
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: ftv2folderclosed.png
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ftv2folderclosed.png
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Index: pavr_hwres_iof_rampz_01.gif
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pavr_hwres_iof_rampz_01.gif
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+application/octet-stream
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Index: pavr_pipestruct_01.gif
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pavr_pipestruct_01.gif
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Index: group__pavr__intro.html
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+++ group__pavr__intro.html (revision 6)
@@ -0,0 +1,65 @@
+
+
+Introduction
+
+
+
+
+Main Page Modules Related Pages
+
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__test__bugs.html
===================================================================
--- group__pavr__test__bugs.html (nonexistent)
+++ group__pavr__test__bugs.html (revision 6)
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+
+
+Bugs
+
+
+
+
+Main Page Modules Related Pages
+
Bugs
+
+
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_pipe_jumps_01.gif
===================================================================
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+++ pavr_pipe_jumps_01.gif (revision 6)
Introduction
- +Goal
-
+This project implements an 8 bit controller that is compatible with Atmel's AVR architecture, using VHDL (Very High speed integrated circuits Hardware Definition Language).
+ The device built here is not a specific controller of the AVR family, but rather a maximally featured AVR controller. It is configurable enough to be able to simulate most AVR family controllers.
+ The goal is to obtain an AVR processor that is as powerful as possible (in terms of MIPS), with a work budget of about 6 months*man.
+
+
- +Approach
-
+Atmel's AVR core is reasonably fast, among the other 8 bit controllers on the market (year 2002). Most instructions take one clock. The instruction set is (almost) RISC. In real life applications, the average clocks per instruction (CPI) is typically 1.2...1.7, depending on the application. CPI=1.4 is a good average. The core has a short pipeline, with 2 stages (fetch and execute). With Atmel's 0.5um technology, the core runs at 10...15 MHz.
+
+ From the start were searched ways to improve original core's performance.
+ As the original core already executes most instructions in one clock, two ideas come quick in mind: a deeper pipeline and issuing more than one instruction per clock (multi-issue).
+ A deeper pipeline is relatively straightforward. A clock speed increase of about 3...4x is expected from a 5 or 6 stages pipeline. However, the resulted average CPI is expected to be slightly bigger than the original, mainly because of jumps, branches, calls and returns. They require the pipeline to be flushed, at least partially, thus some clocks are lost while refilling the pipeline.
+ The multi-issue approach was quickly rejected. The available time budget is too small for implementing both a deep pipeline and multi-issuing. On the other hand, multi-issue without a deeper pipeline wouldn't make much sense.
+
+
- +Result
-
+pAVR is a parameterizable and synthesizable VHDL design, AVR-compatible, that has:
+-
+
- 6 pipeline stages
- 1 instruction/clock for most instructions
- estimated clock frequency: ~50 MHz & 0.5 um; assuming that Atmel's core runs at 15 MHz & 0.5 um.
+ 3x Atmel original core's performance. - estimated MIPS at 50 MHz: 28 MIPS (typical), 50 MIPS (peak)
+ 3x Atmel original core's performance.. At 15 MHz, Atmel's core has 10 MIPS typical, and 15 MIPS peak. - CPI: 1.7 clocks/instruction (typical), 1 clock/instruction (peak)
+ 0.75x (typical), 1.00x (peak) Atmel original core's performance. - pAVR architecture is rather computational-friendly than control-friendly. Jumps, branches, skips, calls and returns are relatively expansive in terms of clocks. A branch prediction scheme and a smarter return procedure might be considered as upgrades.
+ The sources structure is modularized. The sources are written based on a set of common-sense conventions (the process splitting strategy, signals naming, etc). Thus, pAVR is quite an easily maintainable design.
+ Extensive testing was carried out.
+ pAVR is to be synthesized and burned into a FPGA.
+
+
- +Project structure
-
+This project is distributed in two forms: release and devel (development).
+
+ The devel distribution contains-
+
- pAVR documentation
- VHDL sources for pAVR and associated VHDL tests
- test programs
- some utilities (preprocessor, some useful scripts)
+ The documentation is generated via Doxygen. For those who don't know how to use this wonderful tool, please check www.doxygen.org .
+ In the "doc" directory can be found the sources of the documentation. Also, here are some scripts for compiling the documentation, cleaning it up, or running (viewing) it.
+ In the "doc/html" folder is placed the compilation result (HTML). The HTML documentation is further compiled into a .CHM (compressed HTML) file that is placed in the "doc/chm" folder. CHM is a very convenient file format, providing about all the features of HTML, plus that it's very small due to compression and very handy (a single file instead of a bunch of files and folders). However, this file format is still Windows-bound. There are neither compilers nor viewers for Linux (but things might change soon...).
+ The "src" folder contains pAVR VHDL sources, VHDL tests and some Modelsim macro files.
+ The "test" folder contains the test programs (ASM and ANSI C) with which pAVR was tested.
+ The "tools" folder contains some utilities. The most important utility is a text preprocessor. In the VHDL sources are placed XML-like tags, inserted as comments. The preprocessor parses these sources and interprets the XML-like tags. For example, some tags isolate non-synthesizable code that can easily removed when synthesizing pAVR. The preprocessor is also used to insert a common header into all VHDL sources.
+ Also, in the "tools" folder are some scripts that build devel or release packages.
+
+ The release distribution contains only the documentation. However, all the VHDL sources are embedded into the documentation, and are thus easily accessible.
+ The release distribution comes in two flavors: HTML or CHM. My favorite is CHM, because it's much more compact. However, for viewing the documentation under Linux, HTML is still needed.
+
+ Throughout this project are a few sub-projects that must be edited/compiled/run independently (for example, generating the documentation, or compiling test sources). For this purpose, I use a TCL console with stdin/stdout/stderr, and a few buttons: edit/compile/run/clean. Each button launches a script with the same name as the button, placed in the same folder as the console script. The stdout/stderr of the scripts are captured on the TCL console. I use this "project manager" (the TCL console) the very same way for, let's say, compiling a C source or generating Doxygen documentation.
+
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__test__bugs.html
===================================================================
--- group__pavr__test__bugs.html (nonexistent)
+++ group__pavr__test__bugs.html (revision 6)
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+
+
+Bugs
+
+[Testing]
+
- +Errata to Atmel's AVR documentation:
-
+The corrected versions of some paragraphs from Atmel's documentation are shown below.
+ Original, wrong, terms are strikelined, while corrected terms are bolded:
+-
+
- The following text can be found throughout the references.
+
+ + + "...
+ RAMPD
+
+ Register concatenated with theZ registerinstruction word + enabling direct addressing of the whole data space on MCUs with more than 64K + bytes data space.
+
+ EIND
+
+ Register concatenated with theinstruction wordZ register + enabling indirect jump and call to the whole program space on MCUs with more + than 64Kbyteswords program space.
+ ..."
+ +
+- In the `AVR Instruction Set' document, page 60:
+ + + "...
+ V: Rd7 */Rd7/Rr7 * /R7 + /Rd7 * Rr7 * R7
+ ..." + +
+ - In the `AVR Instruction Set' document, page 60:
- The following text can be found throughout the references.
- +Atmel's AVRStudio simulator bugs
-
+
-
+
- bug001
-
+
- symptom: NEG instruction computes the H flag via other formula than that given in the AVR Instruction Set (H=R3+Rd3).
+ Where is the bug, in the simulator or in the document, it's up to be seen.
+ Versions 3.53 and 4.04 of AVRStudio behave the same (weird) way.
+ Example: initially having SREG=0x01 and R10=0xD9, NEG R10 sets SREG to 0x01 instead of 0x21.
+ The AVRStudio formula for H seems to be R3*(not Rd3) rather than R3+Rd3.
- symptom: NEG instruction computes the H flag via other formula than that given in the AVR Instruction Set (H=R3+Rd3).
- bug002
-
+
- symptom: when trying to set/reset port A pins, there is a 1 clock delay between the moment PORTA receives the bits and the moment PINA gets updated. Those events should have been simultaneous (of course, port A direction was considered already configured as output, by setting DDRA(i)=1).
- bug001
+
+pAVR bugs history
- +28-31 July 2002
-
+
-
+
- The Program Memory and Program Counter are handled in different places, even though they share much functionality. Moreover, the Program Counter doesn't have associated an explicit manager. This makes PM and PC quite difficult to maintain.
+ Reorganized PM and PC handling. Now they are handled by a common manager, the PM manager.
+ - Every test runs smoothly so far.
- The Program Memory and Program Counter are handled in different places, even though they share much functionality. Moreover, the Program Counter doesn't have associated an explicit manager. This makes PM and PC quite difficult to maintain.
- +27 July 2002
-
+
-
+
- The Stall and Flush Unit and Shadow Manager are difficult to maintain because of too many rules and exceptions.
+ Reorganized the SFU so that its behavior follows only one rule, the so-called `SFU rule': older hardware resource requests have priority over younger ones.
+ Reorganized the Shadow Manager so that its behavior accurately implements the shadow protocol. However, a few exceptions still exist (such as LPM Program Memory handling or CPSE RF handling). - *** Modelsim 5.3 behaves strange again.
+ It asserts hardware managers warnings, but when the the local conditions are investigated, the situation is perfectly legal. It seems that at a moment when a signal has a 0-1 transition and another one has a 1-0 transition, there is a `small' (theoretically 0) amount of time that both signals are considered 1, and that transient triggers the warning. That shouldn't happen, it seems to be a Modelsim bug.
+ However, trying to reproduce that behavior was unsuccessfull. It only appears sometimes; the apparition rule is well hidden.
+ For now, it's best to ignore these warnings during simulation. However, it means that those assertions don't fullfill their purpose.
- The Stall and Flush Unit and Shadow Manager are difficult to maintain because of too many rules and exceptions.
- +25 July 2002
-
+
-
+
- bug023
-
+
- symptom: IJMP and EIJMP don't jump were they are supposed to, if the instruction before them modifies the Z pointer.
- remedy: IJMP and EIJMP actually jump before even the BPU gets updated by the previous instruction. As they use the Register File mapped Z pointer for finding target address, they need to be calmed down for a clock (Z pointer is modified in stage s5).
+ Just request a nop in pipe stage s4. Now IJMP and EIJMP take 4 clocks (RJMP and JMP still take 3). - status: corrected
- bug024
-
+
- symptom: loads don't work any more (!). They (sometimes) get garbage.
- remedy: when correcting bug 021, the shadow protocol was applied for all devices that could use it. It was wrong. The Data Address Calculation Unit must not use the shadow protocol, because it gets RF/IOF/DM exclusivity by means of stalling, and it must be granted access to these resources, even during stalls.
+ When trying to read from Unified Memory, loads got data from shadow registers, not directly from the RF/IOF/DM 's data out. - status: corrected DACU
- bug025
-
+
- symptom: JMP gets corrupted if the previous instruction is a load.
- remedy: JMP is a 32 bit instruction. The second word (a 16 bit constant) can get flushed by a previous instruction stall s5.
+ Flush s2 requested in s3 and s4 are more delicate than other flushes. They can interfere with stalls requested by older instructions. They must be stallable because older instructions might want that. If stall s2 requested in s3 or s4, then if older instructions require stall, don't blindly flush s2, but rather do nothing and wait for the stall to end. Only after that acknowledge the flush.
+ - status: corrected
- bug026
-
+
- symptom: CPSE doesn't skip the following instruction, when it should.
- remedy: the skip condition was picked as `not zero flag', instead of `zero flag'.
- status: corrected
- bug027
-
+
- symptom: SBIC and SBIS don't do their job.
- remedy: IOF read access was simply not requestd.
- status: corrected the Instruction Decoder by placing an IOF request in pipe stage s5, for SBIC and SBIS
- bug028
-
+
- symptom: RCALL doesn't work.
- remedy:
-
+
- the 12 bit relative offset wasn't initialized in the Instruction Decoder. Just do that (cut&paste the corresponding code line from RJMP, as the relative jump address is placed in the same bits in the instruction code).
- the return address was correct for CALL but bigger with one than needed for RCALL. Actually, CALL and RCALL need different return addresses, as CALL has 32 bits and RCALL only 16.
+ Modification: now, the current instruction's PC is conditionally incremented in pipe stage s4. A new set of wires and registers were introduced so that CALL can request to increment its return address. RCALL doesn't need to do that.
- status: corrected the Instruction Decoder, so that CALL requires to increment its return address.
- note: all instructions seem to work.
- bug023
- +24 July 2002
-
+
-
+
- bug020
-
+
- symptom: garbage got by loads placed immediately after stores that modify their pointer.
- remedy: loads and stores can modify their data pointer. However, the Bypass Unit must also be updated, because the pointer registers are placed in the Register File. The BPU wasn't updated.
- status: corrected
- note: the modularity of the design (separate hardware managers, small set of conventions regarding signal naming, grouping similar-function code) payed off. This bug required an intervention spread out over half megabyte of code. The Data Address Calculation Unit, Bypass Unit were modifed, new wires and registers were defined, some of them were renamed.
- bug021
-
+
- symptom: stores that modify their pointer make the following instruction unable to update the Bypass Unit. Moreover, the BPU is written with garbage.
- remedy: Stores and the instruction after them can require to simultaneousely write the BPU. That's because these stores make intensive use of BPU and eat all its write resources. They write 3 bytes: 2 of them in s5 (the modified pointer) and 1 in s6 (the data to be written into the Register File). The one written in s6 can be simultaneous with following instruction's s5 write BPU request.
+ To correct this bug, there are 2 options:-
+
- 1. add a stall in pipe stage s5 for all stores. That is, stores will take 3 clocks.
- 2. increase BPU width from 2 chains to 3 chains and modify the way stores make use of Bypass Unit (write all what has to be written - 3 bytes - in the same pipe stage, s5). This is more attractive because stores still need only 2 clocks. However, the Bypass Unit continues to grow (from initial depth/width of 2/2 to the present 4/3).
+ The Unified Memory architecture favorized this bug. Stores must be able to write the Register File and, consequently, write their data into BPU along with the pointer they have modified. - status: corrected
- bug022
-
+
- symptom: LPM always returns 0.
- remedy: multiple bug:
-
+
- The LPM stalled s2, then read s2 status. Seeing it `busy', gives up from reading what it needed and maintains pavr_pm_addr_int at its present value. The Program Memory Manager needs to be instructed to forcedly grant access to LPM instructions to s2, even if it is stalled. Also, the shadow protocol must be bypassed.
- LPM didn't update BPU.
- pointer registers were used directly in a few hardware managers, not via BPU. This enables subtle read before write hazards (they escaped until now).
- status: corrected
- note:
+ LD Rd, -X; LD Rd, X; LD Rd, X+;
+ LD Rd, -Y; LD Rd, Y; LD Rd, Y+; LDD Rd, Y+q;
+ LD Rd, -Z; LD Rd, Z; LD Rd, Z+; LDD Rd, Z+q;
+ ST -X, Rr; ST X, Rr; ST X+, Rr;
+ ST -Y, Rr; ST Y, Rr; ST Y+, Rr; STD Y+q, Rr;
+ ST -Z, Rr; ST Z, Rr; ST Z+, Rr; STD Z+q, Rr;
+ LPM; LPM Rd, Z; LPM Rd, Z+
+ seem to work.
- bug020
- +23 July 2002
-
+
-
+
- bug016
-
+
- symptom: read before write data hazards
- remedy: BLD instruction didn't update BPU.
- status: corrected
- bug017
-
+
- symptom: BLD doesn't modify the target register.
- remedy: while processing pavr_s5_iof_rq IOF request, the IOF Manager set IOF bit address to zero instead of pavr_s5_iof_bitaddr. Correct that.
- status: corrected
- bug018
-
+
- symptom: Even though they work fine separately, POP, PUSH and MOVW one after another (in various combinations) don't.
- remedy: This is a triple (!) bug:
-
+
- MOVW requires a stall in s6 while POP requires a stall in s5. The two stalls are simultaneous.
+ The Stall and Flush Unit doesn't handle properly multiple stalls.
+ Modify SFU so that the oldest stall doesn't kill the younger one(s), but only delays it (them). - The SP was incremented during a stall, and the DACU received after the stall a wrong pointer (the new SP).
+ All hardware resources must be stallable. Presently they are not. - The instruction after MOVW, PUSH is skipped. The PM data out shadow register doesn't do its job.
+ The shadow registers are updated every clock. That's not right.
+ Update them only if they don't already hold meaningful data (check the corresponding `shadow_active' flag). Otherwise, during successive stalls they get corrupted.
- MOVW requires a stall in s6 while POP requires a stall in s5. The two stalls are simultaneous.
- status: corrected
- bug019
-
+
- symptom: the sequence
+ LDI R17, 0xC3
+ ST Z+, R17
+ results in storing garbage into memory. - remedy: the nop requests (placed by ST) increase the needed BPU depth with one. Thus, BPU depth must be increased from 3 to 4.
- status: corrected
- symptom: the sequence
- note:
-
+
- CBI, SBI, BST, BLD, MOVW, IN, OUT, PUSH, POP, LDS, STS seem to work.
- bug016
- +22 July 2002
-
+
-
+
- bug011
-
+
- symptom: DEC does in fact INC
- remedy: ALU operand 2 is selected as -1 in pipe stage s5, and then, the DEC-related code does out=op1-op2, which results in out=op1+1.
+ Just make the ALU treat INC and DEC the same way (that is, out=op1+op2). - status: corrected
- bug012
-
+
- symptom: BPU doesn't do its job.
- remedy: stupid and time costly bug, generated by a (too) quick cut and paste in the BPU code.
- status: corrected
- note: Modelsim PE/Plus 5.3a_p1 has a cache problem. After correcting this bug, the same results came after recompiling and restarting the simultation. It was enough to close Modelsim and open the project again for things to go fine. It's not the first time Modelsim behaves this way.
- bug013
-
+
- symptom: Z flag is computed wrongly for ALU opcodes that need 8 bit substraction with carry.
- remedy: Z=Z*oldZ
- status: corrected
- bug014
-
+
- symptom: Z flag is computed wrongly for all ALU opcodes (!).
- remedy: instead of and-ing the negated bits of output, Z output was computed by and-ing output's bits.
- status: corrected
- bug15
-
+
- symptom: read before write data hazards related to IN instruction
- remedy: IN doesn't write the Bypass Unit. Do that. Nasty one, requiring new wires and registers.
- status: corrected
- note: the shadow manager was completed. Pretty much code, hopefully with no new bugs.
- notes:
-
+
- MOV, INC, DEC, AND, AND, OR, ORI, EOR, COM, NEG, CP, CPC, CPI, SWAP, LSR, ROR, ASR, multiplications (timing-only), BCLR, BSET seem to work.
- bug011
- +21 July 2002
-
+
-
+
- bug008
-
+
- symptom: read before write data hazards.
- remedy: the Bypass depth was increased from 2 to 3. Design bug.
+ To update the documentation! - status: corrected.
- bug009
-
+
- symptom: the 16 bit arithmetic instructions write only the lower byte of the result in the Register File if the next few instructions aren't nops.
- remedy: 16 bit arithmetic instructions stalled s6. During stalling s6, the Bypass flushed a value that was needed later. A signal was needed that can stall the BPU. Now, the stall s6 requests also stall the BPU.
+ Pretty triky design bug.
+ To update the documentation!
+ - status: corrected.
- bug010
-
+
- symptom: stalls needed by 16 bit arithmetic instructions induce the replacement of the instruction placed 4 clocks later by a nop
- remedy: shadow registers were assigned, but never used. PM data out, (and consequently, the instruction register) read a nop instead the correct data that was read during the stall. Now the pipeline uses shadow registers related by PM data out.
+ The other shadow registers (related to DM, RF, IOF and DACU data out) are still unused!
+ To update the documentation with shadow-related issues! - status: corrected.
+
- note:
-
+
- ADD, ADC, ADIW, SUB, SUBI, SBC, SBIW seem to work.
- bug008
- +15 July 2002
-
+
-
+
- bug004
-
+
- remedy: reporting this bug was a bug. The Register File works fine. This bug report was generated by modifying X register (RF addr 27:26) and expecting that RF bulk data (RF addr 0...25) to be modified, which won't happen.
- status: ok.
- bug005
-
+
- remedy: DACU data out was duplicated, with 2 different names: pavr_dacu_do and pavr_s6_dacudo. pavr_dacu_do was only writen, and pavr_s6_dacudo was only read. When RET tried to read the return address from DACU, it got garbage, because it read DACU data out from pavr_s6_dacudo, that was not assigned any value.
+ Cut out pavr_s6_dacudo. DACU data out is now unique, for both read an write (that is, pavr_dacu_do). Also, the documentation was updated. - status: corrected.
- remedy: DACU data out was duplicated, with 2 different names: pavr_dacu_do and pavr_s6_dacudo. pavr_dacu_do was only writen, and pavr_s6_dacudo was only read. When RET tried to read the return address from DACU, it got garbage, because it read DACU data out from pavr_s6_dacudo, that was not assigned any value.
- bug006
-
+
- symptom: CALL doesn't work.
- remedy: in the SP Manager, pavr_s5_calldec_spwr_rq was writen twice, and pavr_s52_calldec_spwr_rq wasn't writen at all, because of a less careful cut-and-paste. As a result, during CALL, PC's lsByte was not stored.
- status: corrected
- bug007
-
+
- symptom: ALU flags are not defined.
- remedy: ALU flags in was not connected to SREG (zero-level assignment)
- status: corrected
- notes:
-
+
- RET, CALL seem to work.
- pAVR runs its first complete program (12 instructions).
- bug004
- +13 July 2002
-
+
-
+
- bug003
-
+
- symptom: RET is a mess
- remedy: during nop requests, stall must have higher priority that flush in s2. The Stall Manager (the nop request-related lines) must take care of that.
- status: corrected
- bug004
-
+
- symptom: RF seems to be unable to write other registers than pointer registers.
- status: NOT corrected!
- bug005
-
+
- symptom: RET is still a mess.
- status: NOT corrected!
- bugs pool: 004, 005
- bug003
- +27 June 2002
-
+
-
+
- bug001
-
+
- symptom: read before write data hazards. Hmm, this kind of bugs shouldn't have occured.
- remedy: LDI didn't update BPU0. Just do that.
- status: corrected.
- bug002
-
+
- symptom: while reading the code, something was smelling bad.
- remedy: the code that computes the branch/skip conditions was not writen at all.
- status: corrected.
- notes:
-
+
- The controller has successfully executed its first instruction (a RJMP)! However, it was the only...
+ - The kernel seems to be easy to debug thanks to its regular structure.
- RJMP, LDI, NOP seem to work.
- The controller has successfully executed its first instruction (a RJMP)! However, it was the only...
- bug001
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_pipe_jumps_01.gif
===================================================================
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Index: pavr_pipe_jumps_01.gif
===================================================================
--- pavr_pipe_jumps_01.gif (nonexistent)
+++ pavr_pipe_jumps_01.gif (revision 6)
pavr_pipe_jumps_01.gif
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: std_util.vhd
===================================================================
--- std_util.vhd (nonexistent)
+++ std_util.vhd (revision 6)
@@ -0,0 +1,179 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This file contains:
+-- - Type conversion routines ofted used throughout the other source files in
+-- this project
+-- - Basic arithmetic functions
+-- *** Multiplication is not yet defined! It will be defined here.
+-- - Sign and zero-extend functions
+-- - Vector comparision function
+--
+
+
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_signed.all;
+
+
+
+package std_util is
+ function std_logic_vector_to_int(vec: std_logic_vector) return integer;
+ function std_logic_vector_to_nat(vec: std_logic_vector) return natural;
+ function int_to_std_logic_vector(i, len: integer) return std_logic_vector;
+
+ function "+"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector;
+ function "+"(a: std_logic_vector; b: integer) return std_logic_vector;
+ function "-"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector;
+ function "-"(a: std_logic_vector; b: integer) return std_logic_vector;
+
+ function sign_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector;
+ function zero_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector;
+
+ function cmp_std_logic_vector(a: std_logic_vector; b: std_logic_vector) return std_logic;
+end;
+
+
+
+package body std_util is
+
+ function std_logic_vector_to_int(vec: std_logic_vector) return integer is
+ variable i: integer;
+ begin
+ i := conv_integer(vec);
+ return(i);
+ end;
+
+
+ function std_logic_vector_to_nat(vec: std_logic_vector) return natural is
+ variable tmp: std_logic_vector(vec'length downto 0);
+ variable n: natural;
+ begin
+ assert (vec'length < 32)
+ report "Error: vector length > 31 in function `std_logic_vector_to_nat'."
+ severity failure;
+ tmp := '0' & vec;
+ n := conv_integer(tmp);
+ return(n);
+ end;
+
+
+ function int_to_std_logic_vector(i, len: integer) return std_logic_vector is
+ variable r: std_logic_vector(len - 1 downto 0);
+ variable r1: std_logic_vector(len downto 0);
+ begin
+ r1 := conv_std_logic_vector(i, len + 1);
+ r := r1(len - 1 downto 0);
+ return(r);
+ end;
+
+
+ function "+"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector is
+ begin
+ return(signed(a) + signed(b));
+ end;
+
+
+ function "+"(a: std_logic_vector; b: integer) return std_logic_vector is
+ begin
+ return(signed(a) + b);
+ end;
+
+
+ function "-"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector is
+ begin
+ return(signed(a) - signed(b));
+ end;
+
+
+ function "-"(a: std_logic_vector; b: integer) return std_logic_vector is
+ begin
+ return (signed(a) - b);
+ end;
+
+
+ function sign_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector is
+ variable r: std_logic_vector(wxtd - 1 downto 0);
+ begin
+ assert (a'length <= wxtd)
+ report "Error: vector length > extended vector length in function `sign_extend'."
+ severity failure;
+ for i in 0 to a'length-1 loop
+ r(i) := a(i);
+ end loop;
+ for i in a'length to wxtd - 1 loop
+ r(i) := a(a'length - 1);
+ end loop;
+ return r;
+ end;
+
+
+ function zero_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector is
+ variable r: std_logic_vector(wxtd - 1 downto 0);
+ begin
+ assert (a'length <= wxtd)
+ report "Error: vector length > extended vector length in function `sign_extend'."
+ severity failure;
+ for i in 0 to a'length-1 loop
+ r(i) := a(i);
+ end loop;
+ for i in a'length to wxtd - 1 loop
+ r(i) := '0';
+ end loop;
+ return r;
+ end;
+
+
+ function cmp_std_logic_vector(a: std_logic_vector; b: std_logic_vector) return std_logic is
+ variable r: std_logic;
+ begin
+ assert (a'length = b'length)
+ report "Error: vectors don't have the same length in function `cmp_std_logic_vector'."
+ severity failure;
+ r := '1';
+ for i in 0 to a'length - 1 loop
+ if (a(i) /= b(i)) then
+ r := '0';
+ end if;
+ end loop;
+ return r;
+ end;
+
+end;
+--
Index: group__pavr__hwres__iof__rampywr.html
===================================================================
--- group__pavr__hwres__iof__rampywr.html (nonexistent)
+++ group__pavr__hwres__iof__rampywr.html (revision 6)
@@ -0,0 +1,36 @@
+
+
+RAMPY port
+
+
+
+
+Main Page Modules Related Pages
+
RAMPY port
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_pipe_others_01.gif
===================================================================
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Index: pavr_pipe_others_01.gif
===================================================================
--- pavr_pipe_others_01.gif (nonexistent)
+++ pavr_pipe_others_01.gif (revision 6)
RAMPY port
+
+[IO File]
+
- +RAMPY port connectivity
-
+
+++
+
+
- +Requests to this port
-
+
-
+
- pavr_s5_ldstincrampy_xwr_rq
+ Needed by loads and stores with postincrement.
+ Only modify RAMPY if the controller has more than 64 KB of Data Mamory. - pavr_s5_ldstdecrampy_xwr_rq
+ Needed by loads and stores with predecrement.
+ Only modify RAMPY if the controller has more than 64 KB of Data Mamory.
+
+
- pavr_s5_ldstincrampy_xwr_rq
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_pipe_others_01.gif
===================================================================
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Index: pavr_pipe_others_01.gif
===================================================================
--- pavr_pipe_others_01.gif (nonexistent)
+++ pavr_pipe_others_01.gif (revision 6)
pavr_pipe_others_01.gif
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+application/octet-stream
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Index: pavr_hwres_rf_zwr_01.gif
===================================================================
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Index: pavr_hwres_rf_zwr_01.gif
===================================================================
--- pavr_hwres_rf_zwr_01.gif (nonexistent)
+++ pavr_hwres_rf_zwr_01.gif (revision 6)
pavr_hwres_rf_zwr_01.gif
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Index: group__pavr__hwres__iof__perif.html
===================================================================
--- group__pavr__hwres__iof__perif.html (nonexistent)
+++ group__pavr__hwres__iof__perif.html (revision 6)
@@ -0,0 +1,28 @@
+
+
+Peripherals
+
+
+
+
+Main Page Modules Related Pages
+
Peripherals
+
+
+ However, an IO port, an external interrupt and an 8 bit timer are implemented, to properly test the interrupt system.
+ Peripherals have been designed to be decoupled from the kernel. They are easily upgradable, without needing to touch the kernel.
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__hwres__iof__perif__t0.html
===================================================================
--- group__pavr__hwres__iof__perif__t0.html (nonexistent)
+++ group__pavr__hwres__iof__perif__t0.html (revision 6)
@@ -0,0 +1,44 @@
+
+
+Timer 0
+
+
+
+
+Main Page Modules Related Pages
+
Timer 0
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__hwres__bpr1.html
===================================================================
--- group__pavr__hwres__bpr1.html (nonexistent)
+++ group__pavr__hwres__bpr1.html (revision 6)
@@ -0,0 +1,37 @@
+
+
+Bypass chain 1
+
+
+
+
+Main Page Modules Related Pages
+
Bypass chain 1
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_hwres_iof_01.gif
===================================================================
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Index: pavr_hwres_iof_01.gif
===================================================================
--- pavr_hwres_iof_01.gif (nonexistent)
+++ pavr_hwres_iof_01.gif (revision 6)
Peripherals
+
+[IO File]
+
Modules | |
| Port A | |
| External interrupt 0 | |
| Timer 0 | |
Detailed Description
+Peripherals are only of secondary importance for this project.+ However, an IO port, an external interrupt and an 8 bit timer are implemented, to properly test the interrupt system.
+ Peripherals have been designed to be decoupled from the kernel. They are easily upgradable, without needing to touch the kernel.
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__hwres__iof__perif__t0.html
===================================================================
--- group__pavr__hwres__iof__perif__t0.html (nonexistent)
+++ group__pavr__hwres__iof__perif__t0.html (revision 6)
@@ -0,0 +1,44 @@
+
+
+Timer 0
+
+[Peripherals]
+
- +Features
-
+The IO File register that holds the current count is TCNT0.
+ Its behavior is controlled by a set of other IO File registers:-
+
- TIFR (Timer Interrupt Flag Register) holds the Timer 0 interrupt flag:
+
+++
+
+ - TIMSK (Timer Interrupt Mask) contains the flag that enables/disables Timer 0 interrupt:
+
+++
+
+ - TCCR0 (Timer 0 Control Register) register defines the prescaling source of Timer 0.
+ When external input pin is selected, Timer 0 clock source will be the line 0 of port A:
+
+++
+
+
+
- TIFR (Timer Interrupt Flag Register) holds the Timer 0 interrupt flag:
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__hwres__bpr1.html
===================================================================
--- group__pavr__hwres__bpr1.html (nonexistent)
+++ group__pavr__hwres__bpr1.html (revision 6)
@@ -0,0 +1,37 @@
+
+
+Bypass chain 1
+
+[Bypass Unit]
+
- +Bypass chain 1 (BPR1) write port connectivity
-
+
+++
+
+
- +Requests to BPR1 write port
-
+
-
+
- pavr_s5_alu_bpr1wr_rq
+ Need by regular ALU instructions that have a 16 bit result (ADIW, SBIW, MUL, MULS, MULSU, FMUL, FMULS, FMULSU, MOVW). - pavr_s5_dacux_bpr12wr_rq
+ Needed by loads and stores with pre(post) decrement(increment).
+ Lower byte of X pointer will be written into BPR1. - pavr_s5_dacuy_bpr12wr_rq
+ Needed by loads and stores with pre(post) decrement(increment).
+ Lower byte of Y pointer will be written into BPR1. - pavr_s5_dacuz_bpr12wr_rq
+ Needed by loads and stores with pre(post) decrement(increment).
+ Lower byte of Z pointer will be written into BPR1.
- pavr_s5_alu_bpr1wr_rq
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_hwres_iof_01.gif
===================================================================
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Index: pavr_hwres_iof_01.gif
===================================================================
--- pavr_hwres_iof_01.gif (nonexistent)
+++ pavr_hwres_iof_01.gif (revision 6)
pavr_hwres_iof_01.gif
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: pavr_hwres_dacu_02.gif
===================================================================
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Index: pavr_hwres_dacu_02.gif
===================================================================
--- pavr_hwres_dacu_02.gif (nonexistent)
+++ pavr_hwres_dacu_02.gif (revision 6)
pavr_hwres_dacu_02.gif
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Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: ftv2folderopen.png
===================================================================
Cannot display: file marked as a binary type.
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Index: ftv2folderopen.png
===================================================================
--- ftv2folderopen.png (nonexistent)
+++ ftv2folderopen.png (revision 6)
ftv2folderopen.png
Property changes :
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: pavr_pipe_dacu_01.gif
===================================================================
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Index: pavr_pipe_dacu_01.gif
===================================================================
--- pavr_pipe_dacu_01.gif (nonexistent)
+++ pavr_pipe_dacu_01.gif (revision 6)
pavr_pipe_dacu_01.gif
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: pavr_hwres_iof_rampy_01.gif
===================================================================
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Index: pavr_hwres_iof_rampy_01.gif
===================================================================
--- pavr_hwres_iof_rampy_01.gif (nonexistent)
+++ pavr_hwres_iof_rampy_01.gif (revision 6)
pavr_hwres_iof_rampy_01.gif
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: pavr_pipe_alu_01.gif
===================================================================
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Index: pavr_pipe_alu_01.gif
===================================================================
--- pavr_pipe_alu_01.gif (nonexistent)
+++ pavr_pipe_alu_01.gif (revision 6)
pavr_pipe_alu_01.gif
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Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: group__pavr__hwres__rf__wr.html
===================================================================
--- group__pavr__hwres__rf__wr.html (nonexistent)
+++ group__pavr__hwres__rf__wr.html (revision 6)
@@ -0,0 +1,44 @@
+
+
+Write port
+
+
+
+
+Main Page Modules Related Pages
+
Write port
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__src.html
===================================================================
--- group__pavr__src.html (nonexistent)
+++ group__pavr__src.html (revision 6)
@@ -0,0 +1,58 @@
+
+
+Sources
+
+
+
+
+Main Page Modules Related Pages
+
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: gpl.txt
===================================================================
--- gpl.txt (nonexistent)
+++ gpl.txt (revision 6)
@@ -0,0 +1,341 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users. This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it. (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.) You can apply it to
+your programs, too.
+
+ When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+ To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+ For example, if you distribute copies of such a program, whether
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+you have. You must make sure that they, too, receive or can get the
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+ We protect your rights with two steps: (1) copyright the software, and
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+
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+ The precise terms and conditions for copying, distribution and
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+ GNU GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+ 0. This License applies to any program or other work which contains
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+ 9. The Free Software Foundation may publish revised and/or new versions
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+ 10. If you wish to incorporate parts of the Program into other free
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+ NO WARRANTY
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+ 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
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+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
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+
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+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+
+ Copyright (C)
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+ Gnomovision version 69, Copyright (C) year name of author
+ Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+ `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+ , 1 April 1989
+ Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs. If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library. If this is what you want to do, use the GNU Library General
+Public License instead of this License.
+
Index: pavr_hwres_iof_perif_int0_02.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: pavr_hwres_iof_perif_int0_02.gif
===================================================================
--- pavr_hwres_iof_perif_int0_02.gif (nonexistent)
+++ pavr_hwres_iof_perif_int0_02.gif (revision 6)
Write port
+
+[Register File]
+
- +Register File write port connectivity
-
+
+++
+
+
- +Requests to RF write port
-
+
-
+
- pavr_s6_aluoutlo8_rfwr_rq
+ Request to write the lower 8 bits of the ALU result into the Register File.
+ - pavr_s61_aluouthi8_rfwr_rq
+ Request to write the higher 8 bits of the ALU result into RF.
+ - pavr_s6_iof_rfwr_rq
+ Request to write IOF data out into RF.
+ Needed by IN, BLD. - pavr_s6_dacu_rfwr_rq
+ Request to write Unified Memory data out (DACU data out) into RF.
+ Needed by loads and POP. - pavr_s6_pm_rfwr_rq
+ Request to write Program Memory data out into RF.
+ Needed by LPM, ELPM. - pavr_s5_dacu_rfwr_rq
+ Request to write RF out into RF.
+ Needed by stores and PUSH.
+ See Note 2.
+
- pavr_s6_aluoutlo8_rfwr_rq
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__src.html
===================================================================
--- group__pavr__src.html (nonexistent)
+++ group__pavr__src.html (revision 6)
@@ -0,0 +1,58 @@
+
+
+Sources
- +Sources
-
+The source package contains the following files, in the compiling order:
-
+
- std_util.vhd
-
+
- Type conversion routines ofted used throughout the other source files in this project
- Basic arithmetic functions
- Sign and zero-extend functions
- Vector comparision function
- pavr_util.vhd
-
+
- Bypass Unit access function
- Interrupt arbitrer function
- pavr_constants.vhd
-
+
- Constants needed by pAVR
- When costumizing pAVR, look and modify (seek-and-destroy) here.
- pavr_data_mem.vhd
- pavr_alu.vhd
- pavr_register_file.vhd
- pavr_io_file.vhd
- pavr_control.vhd
-
+
- pAVR pipeline (pAVR kernel)
- std_util.vhd
- +Test sources
-
+The test sources in this package implement all the tests presented above.
+ The test source package contains the following files:-
+
- test_pavr_alu.vhd
+ Tests the ALU. - test_pavr_control_interrupts.vhd
+ This test is yet to be done. - test_std_util.vhd
+ Tests the utilities defined in `std_util.vhd'. - test_pavr_data_mem.vhd
+ Tests the Data Memory. - test_pavr_register_file.vhd
+ Tests the Register File. - test_pavr_io_file.vhd
+ Tests the IO File. - test_pavr_constants.vhd
+ Defines constants needed by the main test entity. - test_pavr_util.vhd
+ Defines utilities needed by the main test entity. - test_pavr_pm.vhd
+ Defines the Program Memory that is needed by the main test entity. - test_pavr.vhd
+ Defines the main test entity.
+ Tests pAVR as a whole.
- test_pavr_alu.vhd
- +Conventions used when writting the VHDL sources
-
+The terminology used reflects the data flow.
+ For example, `pavr_s4_s6_rfwr_addr1' is assigned in s3 (by the instruction decoder), shifts into `pavr_s5_s6_rfwr_addr1', that finally shifts into `pavr_s6_rfwr_addr1' (terminal register). Only this one carries information actually used by hardware resource managers. This particualr one signalizes an access request to the Register File write port manager.
+
+ Process splitting strategy:-
+
- requests to hardware resources are managed by dedicated processes, one VHDL process per hardware resource.
- a main asynchronous process (instruction decoder) computes values that initialize the pipeline in s3.
- a main synchronous process assings new values to pipeline registers.
+
- +Todo:
- +Replace `next_...' signals family with a (pretty wide) state decoder.
- +Licensing
-
+Please read the licensing terms.
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: gpl.txt
===================================================================
--- gpl.txt (nonexistent)
+++ gpl.txt (revision 6)
@@ -0,0 +1,341 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users. This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it. (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.) You can apply it to
+your programs, too.
+
+ When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
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+
+ How to Apply These Terms to Your New Programs
+
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+
+ To do so, attach the following notices to the program. It is safest
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+
+
pavr_hwres_iof_perif_int0_02.gif
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+application/octet-stream
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===================================================================
--- pages.html (nonexistent)
+++ pages.html (revision 6)
@@ -0,0 +1,18 @@
+
+
+Page Index
+
+
+
+
+Main Page Modules Related Pages
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__pipeline__dacu.html
===================================================================
--- group__pavr__pipeline__dacu.html (nonexistent)
+++ group__pavr__pipeline__dacu.html (revision 6)
@@ -0,0 +1,31 @@
+
+
+DACU access
+
+
+
+
+Main Page Modules Related Pages
+
DACU access
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_pipe_calls_01.gif
===================================================================
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Index: pavr_pipe_calls_01.gif
===================================================================
--- pavr_pipe_calls_01.gif (nonexistent)
+++ pavr_pipe_calls_01.gif (revision 6)
Pipelined AVR microcontroller Related Pages
Here is a list of all related documentation pages:-
+
- Todo List + +
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__pipeline__dacu.html
===================================================================
--- group__pavr__pipeline__dacu.html (nonexistent)
+++ group__pavr__pipeline__dacu.html (revision 6)
@@ -0,0 +1,31 @@
+
+
+DACU access
+
+[Pipeline details]
+
- +A few details
-
+The Data Address Calculation Unit (DACU) handles the Unified Memory, by mapping Unified Memory addresses into Register File, IO File or Data Memory addresses.
+ It also transparently places access requests to RF, IOF or DM, as response to UM access requests.
+ More details on DACU requests can be found here.
+
- +Plugging the DACU into the pipeline
-
+
+++
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_pipe_calls_01.gif
===================================================================
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===================================================================
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+++ pavr_pipe_calls_01.gif (revision 6)
pavr_pipe_calls_01.gif
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Index: group__pavr__hwres__iof__rampxwr.html
===================================================================
--- group__pavr__hwres__iof__rampxwr.html (nonexistent)
+++ group__pavr__hwres__iof__rampxwr.html (revision 6)
@@ -0,0 +1,36 @@
+
+
+RAMPX port
+
+
+
+
+Main Page Modules Related Pages
+
RAMPX port
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_hwres_bpr2_01.gif
===================================================================
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Index: pavr_hwres_bpr2_01.gif
===================================================================
--- pavr_hwres_bpr2_01.gif (nonexistent)
+++ pavr_hwres_bpr2_01.gif (revision 6)
RAMPX port
+
+[IO File]
+
- +RAMPX port connectivity
-
+
+++
+
+
- +Requests to this port
-
+
-
+
- pavr_s5_ldstincrampx_xwr_rq
+ Needed by loads and stores with postincrement.
+ Only modify RAMPX if the controller has more than 64 KB of Data Mamory. - pavr_s5_ldstdecrampx_xwr_rq
+ Needed by loads and stores with predecrement.
+ Only modify RAMPX if the controller has more than 64 KB of Data Mamory.
+
+
- pavr_s5_ldstincrampx_xwr_rq
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_hwres_bpr2_01.gif
===================================================================
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===================================================================
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+++ pavr_hwres_bpr2_01.gif (revision 6)
pavr_hwres_bpr2_01.gif
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+application/octet-stream
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Index: group__pavr__hwres__dm.html
===================================================================
--- group__pavr__hwres__dm.html (nonexistent)
+++ group__pavr__hwres__dm.html (revision 6)
@@ -0,0 +1,38 @@
+
+
+Data Memory
+
+
+
+
+Main Page Modules Related Pages
+
Data Memory
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_io_file.vhd
===================================================================
--- pavr_io_file.vhd (nonexistent)
+++ pavr_io_file.vhd (revision 6)
@@ -0,0 +1,585 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This defines pAVR's IO File.
+-- The IO File is composed of a set of discrete registers, that are grouped
+-- in a memory-like entity. The IO File has a general write/read port that is
+-- byte-oriented, and separate read and write ports for each register in the
+-- IO File.
+-- The general IO File port is a little bit more elaborated than a simple
+-- read/write port. It can read bytes from IO registers to output and write
+-- bytes from input to IO registers. Also, it can do some bit processing: load
+-- bits (from SREG to output), store bits (from input to SREG), set IO bits,
+-- clear IO bits. Bit loading/storing is done through the T bit in SREG.
+-- An opcode has to be provided to specify one of the actions that this port
+-- is capable of. The following opcodes are implemented for the IO File general
+-- port:
+-- - read byte (needed by instructions IN, SBIC, SBIS)
+-- - write byte (OUT)
+-- - clear bit (CBI)
+-- - set bit (SBI)
+-- - load bit (BLD)
+-- - store bit (BST)
+--
+
+
+
+--
+library work;
+use work.std_util.all;
+use work.pavr_util.all;
+use work.pavr_constants.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+
+entity pavr_iof is
+ port(
+ pavr_iof_clk : in std_logic;
+ pavr_iof_res : in std_logic;
+ pavr_iof_syncres : in std_logic;
+
+ -- General IO file port
+ pavr_iof_opcode : in std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
+ pavr_iof_addr : in std_logic_vector(5 downto 0);
+ pavr_iof_di : in std_logic_vector(7 downto 0);
+ pavr_iof_do : out std_logic_vector(7 downto 0);
+ pavr_iof_bitout : out std_logic;
+ pavr_iof_bitaddr : in std_logic_vector(2 downto 0);
+
+ -- AVR kernel register ports
+ -- Status register (SREG)
+ pavr_iof_sreg : out std_logic_vector(7 downto 0);
+ pavr_iof_sreg_wr : in std_logic;
+ pavr_iof_sreg_di : in std_logic_vector(7 downto 0);
+
+ -- Stack pointer (SP = SPH&SPL)
+ pavr_iof_sph : out std_logic_vector(7 downto 0);
+ pavr_iof_sph_wr : in std_logic;
+ pavr_iof_sph_di : in std_logic_vector(7 downto 0);
+ pavr_iof_spl : out std_logic_vector(7 downto 0);
+ pavr_iof_spl_wr : in std_logic;
+ pavr_iof_spl_di : in std_logic_vector(7 downto 0);
+
+ -- Pointer registers extensions (RAMPX, RAMPY, RAMPZ)
+ pavr_iof_rampx : out std_logic_vector(7 downto 0);
+ pavr_iof_rampx_wr : in std_logic;
+ pavr_iof_rampx_di : in std_logic_vector(7 downto 0);
+
+ pavr_iof_rampy : out std_logic_vector(7 downto 0);
+ pavr_iof_rampy_wr : in std_logic;
+ pavr_iof_rampy_di : in std_logic_vector(7 downto 0);
+
+ pavr_iof_rampz : out std_logic_vector(7 downto 0);
+ pavr_iof_rampz_wr : in std_logic;
+ pavr_iof_rampz_di : in std_logic_vector(7 downto 0);
+
+ -- Data Memory extension address register (RAMPD)
+ pavr_iof_rampd : out std_logic_vector(7 downto 0);
+ pavr_iof_rampd_wr : in std_logic;
+ pavr_iof_rampd_di : in std_logic_vector(7 downto 0);
+
+ -- Program Memory extension address register (EIND)
+ pavr_iof_eind : out std_logic_vector(7 downto 0);
+ pavr_iof_eind_wr : in std_logic;
+ pavr_iof_eind_di : in std_logic_vector(7 downto 0);
+
+ -- AVR non-kernel (feature) register ports
+ -- Port A
+ pavr_iof_pa: inout std_logic_vector(7 downto 0);
+
+ -- Interrupt-related interface signals to control module (to the pipeline).
+ pavr_disable_int : in std_logic; -- Is the pipeline ready to process a new interrupt?
+ pavr_int_rq : out std_logic; -- Ask the pipeline to process an interrupt.
+ pavr_int_vec : out std_logic_vector(21 downto 0) -- Tell the pipeline what is the interrupt vector.
+ );
+end;
+
+
+
+architecture pavr_iof_arch of pavr_iof is
+ -- Kernel registers
+ signal pavr_iof_sreg_int: std_logic_vector(7 downto 0);
+ signal pavr_iof_sph_int: std_logic_vector(7 downto 0);
+ signal pavr_iof_spl_int: std_logic_vector(7 downto 0);
+ signal pavr_iof_rampx_int: std_logic_vector(7 downto 0);
+ signal pavr_iof_rampy_int: std_logic_vector(7 downto 0);
+ signal pavr_iof_rampz_int: std_logic_vector(7 downto 0);
+ signal pavr_iof_rampd_int: std_logic_vector(7 downto 0);
+ signal pavr_iof_eind_int: std_logic_vector(7 downto 0);
+
+ -- Feature registers
+ -- Microcontroller control
+ signal pavr_iof_mcucr: std_logic_vector(7 downto 0);
+ -- General interrupt mask
+ signal pavr_iof_gimsk: std_logic_vector(7 downto 0);
+ -- General interrupt flags
+ signal pavr_iof_gifr: std_logic_vector(7 downto 0);
+ -- Timer 0
+ signal pavr_iof_tcnt0: std_logic_vector(8 downto 0); -- *** 9 bits wide, to manage overflow.
+ signal pavr_iof_tccr0: std_logic_vector(7 downto 0);
+ signal pavr_iof_tifr: std_logic_vector(7 downto 0);
+ signal pavr_iof_timsk: std_logic_vector(7 downto 0);
+ -- Port A
+ signal pavr_iof_porta: std_logic_vector(7 downto 0);
+ signal pavr_iof_ddra: std_logic_vector(7 downto 0);
+ signal pavr_iof_pina: std_logic_vector(7 downto 0); -- *** This is not a register; these are just wires.
+
+ -- Local wires
+ signal pavr_tmpdi: std_logic_vector(7 downto 0);
+ signal pavr_int_flgs: std_logic_vector(31 downto 0); -- !!! Can it be introduced into process as var?
+ signal pavr_int_flgs_dcd: std_logic_vector(31 downto 0); -- -"-
+
+ signal pavr_int0_clk: std_logic;
+
+ signal pavr_t0_clk, next_pavr_t0_clk: std_logic;
+ signal clk_t0_cnt: std_logic_vector(9 downto 0);
+
+begin
+
+ -- Build interrupt flags vector and decode that vector. That is, prioritize
+ -- interrupts and find what interrupt has to be processed.
+ process(pavr_disable_int,
+ pavr_int_flgs,
+ pavr_iof_sreg_int,
+ pavr_iof_gifr, pavr_iof_gimsk,
+ pavr_iof_tifr, pavr_iof_timsk)
+ begin
+ pavr_int_flgs <= int_to_std_logic_vector(0, pavr_int_flgs'length);
+ pavr_int_flgs_dcd <= int_to_std_logic_vector(0, pavr_int_flgs'length);
+
+ -- Build active interrupts flags vector
+ -- First, check if the pipeline is ready to process an interrupt.
+ if (pavr_disable_int = '0') then
+ -- Check if interrupts are globally enabled.
+ if (pavr_iof_sreg_int(7) = '1') then
+ -- Check all interrupts sources if active and enabled.
+ pavr_int_flgs(pavr_int0_int_pri) <= pavr_iof_gifr(6) and pavr_iof_gimsk(6);
+ pavr_int_flgs(pavr_tov0_int_pri) <= pavr_iof_tifr(1) and pavr_iof_timsk(1);
+ end if;
+ end if;
+
+ -- Prioritize interrupts
+ pavr_int_flgs_dcd <= prioritize_int(pavr_int_flgs);
+ end process;
+
+
+
+ -- Build Timer 0 clock.
+ t0_clk:
+ process(pavr_iof_clk, clk_t0_cnt, pavr_iof_pina, pavr_iof_tccr0)
+ begin
+ next_pavr_t0_clk <= '0';
+ case pavr_iof_tccr0(2 downto 0) is
+ when "000" =>
+ null;
+ when "001" =>
+ next_pavr_t0_clk <= pavr_iof_clk;
+ when "010" =>
+ next_pavr_t0_clk <= clk_t0_cnt(2);
+ when "011" =>
+ next_pavr_t0_clk <= clk_t0_cnt(5);
+ when "100" =>
+ next_pavr_t0_clk <= clk_t0_cnt(7);
+ when "101" =>
+ next_pavr_t0_clk <= clk_t0_cnt(9);
+ when "110" =>
+ next_pavr_t0_clk <= not pavr_iof_pina(1);
+ when others =>
+ next_pavr_t0_clk <= pavr_iof_pina(1);
+ end case;
+ end process t0_clk;
+
+
+
+ -- Manage IOF data in.
+ manage_iof_di:
+ process(pavr_iof_opcode, pavr_iof_bitaddr, pavr_iof_di)
+ begin
+ pavr_tmpdi <= int_to_std_logic_vector(0, 8);
+
+ case pavr_iof_opcode is
+ when pavr_iof_opcode_wrbyte =>
+ pavr_tmpdi <= pavr_iof_di;
+ when pavr_iof_opcode_clrbit =>
+ pavr_tmpdi <= pavr_iof_di;
+ pavr_tmpdi(std_logic_vector_to_nat(pavr_iof_bitaddr)) <= '0';
+ when pavr_iof_opcode_setbit =>
+ pavr_tmpdi <= pavr_iof_di;
+ pavr_tmpdi(std_logic_vector_to_nat(pavr_iof_bitaddr)) <= '1';
+ when others =>
+ null;
+ end case;
+ end process manage_iof_di;
+
+
+
+ -- Managing IOF registers
+ manage_iof_regs:
+ process(pavr_iof_clk, pavr_iof_res, pavr_iof_syncres,
+ pavr_iof_opcode, pavr_iof_addr, pavr_iof_di, pavr_iof_bitaddr,
+ pavr_tmpdi,
+ pavr_iof_sreg_wr, pavr_iof_sreg_di,
+ pavr_iof_sph_wr, pavr_iof_sph_di,
+ pavr_iof_spl_wr, pavr_iof_spl_di,
+ pavr_iof_rampx_wr, pavr_iof_rampx_di,
+ pavr_iof_rampy_wr, pavr_iof_rampy_di,
+ pavr_iof_rampz_wr, pavr_iof_rampz_di,
+ pavr_iof_rampd_wr, pavr_iof_rampd_di,
+ pavr_iof_eind_wr, pavr_iof_eind_di,
+ pavr_int_flgs_dcd,
+ pavr_t0_clk, next_pavr_t0_clk, clk_t0_cnt,
+ pavr_int0_clk,
+ pavr_iof_sreg_int,
+ pavr_iof_sph_int, pavr_iof_spl_int,
+ pavr_iof_rampx_int, pavr_iof_rampy_int, pavr_iof_rampz_int,
+ pavr_iof_rampd_int,
+ pavr_iof_eind_int,
+ pavr_iof_mcucr,
+ pavr_iof_gimsk, pavr_iof_gifr,
+ pavr_iof_timsk, pavr_iof_tifr,
+ pavr_iof_tcnt0, pavr_iof_tccr0,
+ pavr_iof_porta, pavr_iof_ddra, pavr_iof_pina, pavr_iof_pa
+ )
+ variable pavr_iof_portaz: std_logic_vector(pavr_iof_porta'length - 1 downto 0);
+ begin
+
+ -- Port A asynchronous circuitry.
+ for i in 0 to 7 loop
+ if pavr_iof_ddra(i)='1' then
+ pavr_iof_portaz(i) := pavr_iof_porta(i);
+ else
+ -- *** When synthesizing, to check if the technology permits weak
+ -- pull-ups and high Z. If it doesn't, workaround these lines.
+ if pavr_iof_porta(i)='1' then
+ -- Weak pull-ups
+ pavr_iof_portaz(i) := 'H';
+ else
+ -- High Z
+ pavr_iof_portaz(i) := 'Z';
+ end if;
+ end if;
+ end loop;
+ pavr_iof_pa <= pavr_iof_portaz;
+ pavr_iof_pina <= pavr_iof_pa;
+
+ if (pavr_iof_res = '1') then
+ -- Reset
+ -- IOF registers
+ pavr_iof_sreg_int <= int_to_std_logic_vector(0, 8);
+ pavr_iof_sph_int <= int_to_std_logic_vector(0, 8);
+ pavr_iof_spl_int <= int_to_std_logic_vector(0, 8);
+ pavr_iof_rampx_int <= int_to_std_logic_vector(0, 8);
+ pavr_iof_rampy_int <= int_to_std_logic_vector(0, 8);
+ pavr_iof_rampz_int <= int_to_std_logic_vector(0, 8);
+ pavr_iof_rampd_int <= int_to_std_logic_vector(0, 8);
+ pavr_iof_eind_int <= int_to_std_logic_vector(0, 8);
+
+ pavr_iof_mcucr <= int_to_std_logic_vector(0, 8);
+ pavr_iof_gimsk <= int_to_std_logic_vector(0, 8);
+ pavr_iof_gifr <= int_to_std_logic_vector(0, 8);
+
+ pavr_iof_tcnt0 <= int_to_std_logic_vector(0, 9);
+ pavr_iof_tccr0 <= int_to_std_logic_vector(0, 8);
+ pavr_iof_tifr <= int_to_std_logic_vector(0, 8);
+ pavr_iof_timsk <= int_to_std_logic_vector(0, 8);
+
+ pavr_iof_porta <= int_to_std_logic_vector(0, 8);
+ pavr_iof_ddra <= int_to_std_logic_vector(0, 8);
+
+ -- Local registers
+ clk_t0_cnt <= int_to_std_logic_vector(0, clk_t0_cnt'length);
+ pavr_t0_clk <= '0';
+ pavr_int0_clk <= '0';
+ elsif pavr_iof_clk'event and pavr_iof_clk = '1' then
+
+ pavr_iof_bitout <= '0';
+ pavr_int_rq <= '0';
+ pavr_int_vec <= int_to_std_logic_vector(0, 22);
+
+
+ -- Feature registers-related circuitry -------------------------------
+ -- External interrupt 0
+ case pavr_iof_mcucr(1 downto 0) is
+ when "00" =>
+ -- Trigger external interrupt 0 on low level.
+ if pavr_iof_pa(0)='0' then
+ pavr_iof_gifr(6) <= '1';
+ end if;
+ when "01" =>
+ -- Not used.
+ null;
+ when "10" =>
+ -- Trigger external interrupt 0 on negative edge.
+ if pavr_int0_clk='1' and pavr_iof_pa(0)='0' then
+ pavr_iof_gifr(6) <= '1';
+ end if;
+ when others =>
+ -- Trigger external interrupt 0 on positive edge.
+ if pavr_int0_clk='0' and pavr_iof_pa(0)='1' then
+ pavr_iof_gifr(6) <= '1';
+ end if;
+ end case;
+ pavr_int0_clk <= pavr_iof_pa(0);
+
+ -- Timer 0
+ -- Build timer 0's clock.
+ -- Update counter 0.
+ case pavr_iof_tccr0(2 downto 0) is
+ when "000" =>
+ null;
+ when "001" =>
+ pavr_iof_tcnt0 <= pavr_iof_tcnt0 + 1;
+ when others =>
+ if pavr_t0_clk='0' and next_pavr_t0_clk='1' then
+ pavr_iof_tcnt0 <= pavr_iof_tcnt0 + 1;
+ end if;
+ end case;
+ -- Capture timer 0 overflow event.
+ if pavr_iof_tcnt0(8) = '1' then
+ -- Set timer 0 overflow flag in TIFR register.
+ pavr_iof_tifr(1) <= '1';
+ -- Reset overflow (MSBit) in TCNT0 register, because we don't want to
+ -- set overflow flag over and over again from now on.
+ pavr_iof_tcnt0(8) <= '0';
+ end if;
+ pavr_t0_clk <= next_pavr_t0_clk;
+ clk_t0_cnt <= clk_t0_cnt+1;
+
+
+ -- Interrupt Manager -------------------------------------------------
+ -- If interrupt 0 is decoded as a winner interrupt, then acknowledge it.
+ if pavr_int_flgs_dcd(pavr_int0_int_pri) = '1' then
+ pavr_iof_gifr(6) <= '0';
+ pavr_int_rq <= '1';
+ pavr_int_vec <= int_to_std_logic_vector(pavr_int0_int_vec, 22);
+ end if;
+
+ -- If timer 0 overflow interrupt is decoded as a winner interrupt, then
+ -- acknowledge it.
+ if pavr_int_flgs_dcd(pavr_tov0_int_pri) = '1' then
+ pavr_iof_tifr(1) <= '0';
+ pavr_int_rq <= '1';
+ pavr_int_vec <= int_to_std_logic_vector(pavr_tov0_int_vec, 22);
+ end if;
+
+
+ -- Check IOF opcode and process it. ----------------------------------
+ case pavr_iof_opcode is
+ -- Read byte.
+ when pavr_iof_opcode_rdbyte =>
+ case std_logic_vector_to_nat(pavr_iof_addr) is
+ when pavr_sreg_addr =>
+ pavr_iof_do <= pavr_iof_sreg_int;
+ when pavr_sph_addr =>
+ pavr_iof_do <= pavr_iof_sph_int;
+ when pavr_spl_addr =>
+ pavr_iof_do <= pavr_iof_spl_int;
+ when pavr_rampx_addr =>
+ pavr_iof_do <= pavr_iof_rampx_int;
+ when pavr_rampy_addr =>
+ pavr_iof_do <= pavr_iof_rampy_int;
+ when pavr_rampz_addr =>
+ pavr_iof_do <= pavr_iof_rampz_int;
+ when pavr_rampd_addr =>
+ pavr_iof_do <= pavr_iof_rampd_int;
+ when pavr_eind_addr =>
+ pavr_iof_do <= pavr_iof_eind_int;
+ when pavr_mcucr_addr =>
+ pavr_iof_do <= pavr_iof_mcucr;
+ when pavr_gimsk_addr =>
+ pavr_iof_do <= pavr_iof_gimsk;
+ when pavr_gifr_addr =>
+ pavr_iof_do <= pavr_iof_gifr;
+ when pavr_tcnt0_addr =>
+ pavr_iof_do <= pavr_iof_tcnt0(7 downto 0);
+ when pavr_tccr0_addr =>
+ pavr_iof_do <= pavr_iof_tccr0;
+ when pavr_tifr_addr =>
+ pavr_iof_do <= pavr_iof_tifr;
+ when pavr_timsk_addr =>
+ pavr_iof_do <= pavr_iof_timsk;
+ when pavr_porta_addr =>
+ pavr_iof_do <= pavr_iof_porta;
+ when pavr_ddra_addr =>
+ pavr_iof_do <= pavr_iof_ddra;
+ when pavr_pina_addr =>
+ pavr_iof_do <= pavr_iof_pina;
+ when others =>
+ null;
+ end case;
+ -- Write byte | clear bit | set bit.
+ when pavr_iof_opcode_wrbyte | pavr_iof_opcode_clrbit | pavr_iof_opcode_setbit =>
+ case std_logic_vector_to_nat(pavr_iof_addr) is
+ when pavr_sreg_addr =>
+ pavr_iof_sreg_int <= pavr_tmpdi;
+ when pavr_sph_addr =>
+ pavr_iof_sph_int <= pavr_tmpdi;
+ when pavr_spl_addr =>
+ pavr_iof_spl_int <= pavr_tmpdi;
+ when pavr_rampx_addr =>
+ pavr_iof_rampx_int <= pavr_tmpdi;
+ when pavr_rampy_addr =>
+ pavr_iof_rampy_int <= pavr_tmpdi;
+ when pavr_rampz_addr =>
+ pavr_iof_rampz_int <= pavr_tmpdi;
+ when pavr_rampd_addr =>
+ pavr_iof_rampd_int <= pavr_tmpdi;
+ when pavr_eind_addr =>
+ pavr_iof_eind_int <= pavr_tmpdi;
+ when pavr_mcucr_addr =>
+ pavr_iof_mcucr <= pavr_tmpdi;
+ when pavr_gimsk_addr =>
+ pavr_iof_gimsk <= pavr_tmpdi;
+ when pavr_gifr_addr =>
+ pavr_iof_gifr <= pavr_tmpdi;
+ when pavr_tcnt0_addr =>
+ pavr_iof_tcnt0( 8) <= '0';
+ pavr_iof_tcnt0(7 downto 0) <= pavr_tmpdi;
+ when pavr_tccr0_addr =>
+ pavr_iof_tccr0 <= pavr_tmpdi;
+ when pavr_tifr_addr =>
+ pavr_iof_tifr <= pavr_tmpdi;
+ when pavr_timsk_addr =>
+ pavr_iof_timsk <= pavr_tmpdi;
+ when pavr_porta_addr =>
+ pavr_iof_porta <= pavr_tmpdi;
+ when pavr_ddra_addr =>
+ pavr_iof_ddra <= pavr_tmpdi;
+ when pavr_pina_addr =>
+ -- PinA is just a read-only wire.
+ null;
+ when others =>
+ null;
+ end case;
+ -- Load bit.
+ when pavr_iof_opcode_ldbit =>
+ pavr_iof_do <= pavr_iof_di;
+ pavr_iof_do(std_logic_vector_to_nat(pavr_iof_bitaddr)) <= pavr_iof_sreg_int(6);
+ -- Store bit.
+ when pavr_iof_opcode_stbit =>
+ pavr_iof_sreg_int(6) <= pavr_iof_di(std_logic_vector_to_nat(pavr_iof_bitaddr));
+ -- pavr_iof_opcode_nop
+ when others =>
+ null;
+ end case;
+
+ -- Kernel registers ports --------------------------------------------
+ -- Status register (SREG) port
+ if (pavr_iof_sreg_wr = '1') then
+ pavr_iof_sreg_int <= pavr_iof_sreg_di;
+ end if;
+
+ -- Stack pointer (SPH&SPL) ports
+ if (pavr_iof_sph_wr = '1') then
+ pavr_iof_sph_int <= pavr_iof_sph_di;
+ end if;
+ if (pavr_iof_spl_wr = '1') then
+ pavr_iof_spl_int <= pavr_iof_spl_di;
+ end if;
+
+ -- Pointer registers X extension (RAMPX) port
+ if (pavr_iof_rampx_wr = '1') then
+ pavr_iof_rampx_int <= pavr_iof_rampx_di;
+ end if;
+
+ -- Pointer registers Y extension (RAMPY) port
+ if (pavr_iof_rampy_wr = '1') then
+ pavr_iof_rampy_int <= pavr_iof_rampy_di;
+ end if;
+
+ -- Pointer registers Z extension (RAMPZ) port
+ if (pavr_iof_rampz_wr = '1') then
+ pavr_iof_rampz_int <= pavr_iof_rampz_di;
+ end if;
+
+ -- Data Memory extension address (RAMPD) register
+ if (pavr_iof_rampd_wr = '1') then
+ pavr_iof_rampd_int <= pavr_iof_rampd_di;
+ end if;
+
+ -- Program Memory extension address (EIND) register
+ if (pavr_iof_eind_wr = '1') then
+ pavr_iof_eind_int <= pavr_iof_eind_di;
+ end if;
+
+ if (pavr_iof_syncres = '1') then
+ -- Synchronous reset
+ -- IOF registers
+ pavr_iof_sreg_int <= int_to_std_logic_vector(0, 8);
+ pavr_iof_sph_int <= int_to_std_logic_vector(0, 8);
+ pavr_iof_spl_int <= int_to_std_logic_vector(0, 8);
+ pavr_iof_rampx_int <= int_to_std_logic_vector(0, 8);
+ pavr_iof_rampy_int <= int_to_std_logic_vector(0, 8);
+ pavr_iof_rampz_int <= int_to_std_logic_vector(0, 8);
+ pavr_iof_rampd_int <= int_to_std_logic_vector(0, 8);
+ pavr_iof_eind_int <= int_to_std_logic_vector(0, 8);
+
+ pavr_iof_mcucr <= int_to_std_logic_vector(0, 8);
+ pavr_iof_gimsk <= int_to_std_logic_vector(0, 8);
+ pavr_iof_gifr <= int_to_std_logic_vector(0, 8);
+
+ pavr_iof_tcnt0 <= int_to_std_logic_vector(0, 9);
+ pavr_iof_tccr0 <= int_to_std_logic_vector(0, 8);
+ pavr_iof_tifr <= int_to_std_logic_vector(0, 8);
+ pavr_iof_timsk <= int_to_std_logic_vector(0, 8);
+
+ pavr_iof_porta <= int_to_std_logic_vector(0, 8);
+ pavr_iof_ddra <= int_to_std_logic_vector(0, 8);
+
+ -- Local registers
+ clk_t0_cnt <= int_to_std_logic_vector(0, clk_t0_cnt'length);
+ pavr_t0_clk <= '0';
+ pavr_int0_clk <= '0';
+ end if;
+ end if;
+ end process manage_iof_regs;
+
+
+
+ -- Zero-level assignments.
+ pavr_iof_sreg <= pavr_iof_sreg_int;
+ pavr_iof_sph <= pavr_iof_sph_int;
+ pavr_iof_spl <= pavr_iof_spl_int;
+ pavr_iof_rampx <= pavr_iof_rampx_int;
+ pavr_iof_rampy <= pavr_iof_rampy_int;
+ pavr_iof_rampz <= pavr_iof_rampz_int;
+ pavr_iof_rampd <= pavr_iof_rampd_int;
+ pavr_iof_eind <= pavr_iof_eind_int;
+
+end;
+--
Index: pavr_data_mem.vhd
===================================================================
--- pavr_data_mem.vhd (nonexistent)
+++ pavr_data_mem.vhd (revision 6)
@@ -0,0 +1,79 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This is the Data Memory.
+-- DM is a single port RAM, accessible for read and write.
+--
+
+
+
+--
+library work;
+use work.std_util.all;
+use work.pavr_util.all;
+use work.pavr_constants.all;
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+
+entity pavr_dm is
+ port(
+ pavr_dm_clk: in std_logic;
+ pavr_dm_wr: in std_logic;
+ pavr_dm_addr: in std_logic_vector(pavr_dm_addr_w - 1 downto 0);
+ pavr_dm_di: in std_logic_vector(7 downto 0);
+ pavr_dm_do: out std_logic_vector(7 downto 0)
+ );
+end;
+
+
+
+architecture pavr_dm_arch of pavr_dm is
+ type tdata_array is array (0 to pavr_dm_len - 1) of std_logic_vector(7 downto 0);
+ signal data_array: tdata_array;
+begin
+ process
+ begin
+ wait until pavr_dm_clk'event and pavr_dm_clk='1';
+ if (pavr_dm_wr = '0') then
+ pavr_dm_do <= data_array(std_logic_vector_to_nat(pavr_dm_addr));
+ else
+ data_array(std_logic_vector_to_nat(pavr_dm_addr)) <= pavr_dm_di;
+ end if;
+ end process;
+end;
+--
Index: pavr_compile.do
===================================================================
--- pavr_compile.do (nonexistent)
+++ pavr_compile.do (revision 6)
@@ -0,0 +1,12 @@
+;# This is a Modelsim PE/Plus 5.3a_p1 macro file.
+;# It can be seen here what's the compiling order for pAVR's VHDL sources.
+
+;# Compile all pAVR sources
+vcom -reportprogress 300 -work work {std_util.vhd}
+vcom -reportprogress 300 -work work {pavr_util.vhd}
+vcom -reportprogress 300 -work work {pavr_constants.vhd}
+vcom -reportprogress 300 -work work {pavr_alu.vhd}
+vcom -reportprogress 300 -work work {pavr_data_mem.vhd}
+vcom -reportprogress 300 -work work {pavr_register_file.vhd}
+vcom -reportprogress 300 -work work {pavr_io_file.vhd}
+vcom -reportprogress 300 -work work {pavr_control.vhd}
Index: group__pavr__hwres__rf__zwr.html
===================================================================
--- group__pavr__hwres__rf__zwr.html (nonexistent)
+++ group__pavr__hwres__rf__zwr.html (revision 6)
@@ -0,0 +1,44 @@
+
+
+Z port
+
+
+
+
+Main Page Modules Related Pages
+
Z port
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_hwres_alu_01.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: pavr_hwres_alu_01.gif
===================================================================
--- pavr_hwres_alu_01.gif (nonexistent)
+++ pavr_hwres_alu_01.gif (revision 6)
Data Memory
+
+[Hardware resources]
+
- +Data Memory connectivity
-
+
+++
+
+ The Data Memory is a single port RAM.
+ That port provides both read and write DM accesses.
+ The DM is organized on bytes, and has the length set by a constant in the constants definition file (`pavr-constants.vhd').
+
+
- +Requests to DM
-
+Requests to access DM come only from the DACU:
+-
+
- pavr_s5_dacu_dmrd_rq
+ - pavr_s5_dacu_dmwr_rq
+
+
- pavr_s5_dacu_dmrd_rq
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_io_file.vhd
===================================================================
--- pavr_io_file.vhd (nonexistent)
+++ pavr_io_file.vhd (revision 6)
@@ -0,0 +1,585 @@
+-- Z port
+
+[Register File]
+
- +Z port connectivity
-
+
+++
+
+ This is a read and write port.
+
- +Requests to Z write port
-
+
-
+
- pavr_s5_ldstincrampz_zwr_rq
+ Increment Z or RAMPZ:Z.
+ Needed by loads and stores with postincrement.
+ - pavr_s5_ldstdecrampz_zwr_rq
+ Decrement Z or RAMPZ:Z.
+ Needed by loads and stores with predecrement.
+ - pavr_s5_lpminc_zwr_rq
+ Increment Z.
+ Needed by LPM with postincrement.
+ - pavr_s5_elpmincrampz_zwr_rq
+ Increment RAMPZ:Z.
+ Needed by ELPM with postincrement.
+
+
- pavr_s5_ldstincrampz_zwr_rq
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_hwres_alu_01.gif
===================================================================
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svn:mime-type = application/octet-stream
Index: pavr_hwres_alu_01.gif
===================================================================
--- pavr_hwres_alu_01.gif (nonexistent)
+++ pavr_hwres_alu_01.gif (revision 6)
pavr_hwres_alu_01.gif
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+application/octet-stream
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Index: pavr_hwres_iof_rampx_01.gif
===================================================================
Cannot display: file marked as a binary type.
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Index: pavr_hwres_iof_rampx_01.gif
===================================================================
--- pavr_hwres_iof_rampx_01.gif (nonexistent)
+++ pavr_hwres_iof_rampx_01.gif (revision 6)
pavr_hwres_iof_rampx_01.gif
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Index: pavr_control.vhd
===================================================================
--- pavr_control.vhd (nonexistent)
+++ pavr_control.vhd (revision 6)
@@ -0,0 +1,6562 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This file contains the control structure of the pAVR controller. That is, the
+-- pipeline.
+-- The pipeline stages are pretty much decoupled from each other. The pipeline is
+-- initialized in stage 3 (s3) with values from the instruction decoder.
+-- Basically, each pipeline stage receives values from the previous one, in a
+-- shift-like flow. The `terminal' registers contain data actually used, the
+-- previous ones are just used for synchronization. Exceptions from this
+-- `normal' flow are the stall and flush actions, which can basically
+-- independently stall or reset to zero (force a nop into) any stage. Other
+-- exceptions are when several registers in such a chain are actually used,
+-- not only the terminal one.
+-- The terminology used reflects the data flow. For example,
+-- `pavr_s4_s6_rfwr_addr1' is assigned in s3 (by the instruction decoder),
+-- shifts into `pavr_s5_s6_rfwr_addr1', that finally shifts into
+-- `pavr_s6_rfwr_addr1' (terminal register). Only this one carries information
+-- actually used by hardware resource managers. This particualr one signalizes
+-- an access request to the Register File write port manager.
+-- Process splitting strategy:
+-- - requests to hardware resources are managed by dedicated processes, one
+-- process per hardware resource.
+-- Main hardware resources:
+-- - Register File (RF)
+-- - Bypass Unit (BPU)
+-- - ByPass Register 0 (ByPass chain 0) (BPR0)
+-- - ByPass Register 1 (ByPass chain 1) (BPR1)
+-- - ByPass Register 2 (ByPass chain 2) (BPR2)
+-- - IO File (IOF)
+-- - Status Register (SREG)
+-- - Stack Pointer (SP)
+-- - Arithmetic and Logic Unit (ALU)
+-- - Data Access Control Unit (DACU)
+-- - Program Memory (PM)
+-- - Stall and Flush Unit (SFU)
+-- - an asynchronous main process (instruction decoder) computes values that
+-- initialize the pipeline in s3.
+-- - a main synchronous process assings new values to pipeline registers.
+-- - loading a register that belongs to the pipeline is conditioned by 2
+-- stage-specific signals (written here in descending priority order):
+-- - if stage_flush=1 then the register is reseted to zero.
+-- - if stage_stall=1 then the register is not modified.
+-- - if neither stall nor flush are requested, load the register with:
+-- - the values from the instruction decoder, if stage = 3 (s3)
+-- - some particular values if stage = s1 or s2 (values set by the PM
+-- manager)
+-- - the values from the previous stage, if stage != s1 or s2 or s3
+-- To do
+-- - Define multiplication in ALU.
+-- For now, the ALU returns 0 when provided a multiplication ALU opcode.
+-- However, the pAVR pipeline does its job. Multiplication instructions
+-- are decoded and executed OK.
+-- - Replace all those wires named `next...' with a (pretty wide) state
+-- decoder.
+-- - Branch prediction with hashed branch prediction table and 2 bit predictor.
+--
+
+
+
+--
+library work;
+use work.std_util.all;
+use work.pavr_util.all;
+use work.pavr_constants.all;
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+
+
+
+
+entity pavr is
+ port(
+ pavr_clk: in std_logic;
+ pavr_res: in std_logic;
+ pavr_syncres: in std_logic;
+
+ -- Program Memory interface
+ pavr_pm_addr: out std_logic_vector(21 downto 0);
+ pavr_pm_do: in std_logic_vector(15 downto 0);
+ pavr_pm_wr: out std_logic;
+
+ -- IO interface
+ -- A single 8 bit port is implemented. It has, as alternate functions,
+ -- external interrupt 0 on pin 0, and timer 0 clock input on pin 1.
+ pavr_pa: inout std_logic_vector(7 downto 0);
+
+ --
+ -- This is used for testing purposes only, for instruction counting.
+ pavr_inc_instr_cnt: out std_logic_vector(1 downto 0)
+ --
+ );
+end;
+
+
+
+
+
+
+architecture pavr_arch of pavr is
+
+ -- Wires -------------------------------------------------------------------
+
+ -- RF read port 1-related
+ signal pavr_s3_rfrd1_rq : std_logic;
+ signal pavr_s5_dacu_rfrd1_rq : std_logic; -- Note 1: outside pipeline
+
+ signal pavr_s3_rfrd1_addr : std_logic_vector(4 downto 0);
+
+ -- RF read port 2-related
+ signal pavr_s3_rfrd2_rq : std_logic;
+
+ signal pavr_s3_rfrd2_addr : std_logic_vector(4 downto 0);
+
+ -- RF write port-related
+ signal next_pavr_s4_s6_aluoutlo8_rfwr_rq : std_logic;
+ signal next_pavr_s4_s61_aluouthi8_rfwr_rq : std_logic;
+ signal next_pavr_s4_s6_iof_rfwr_rq : std_logic;
+ signal next_pavr_s4_s6_dacu_rfwr_rq : std_logic;
+ signal next_pavr_s4_s6_pm_rfwr_rq : std_logic;
+ signal pavr_s5_dacu_rfwr_rq : std_logic; -- Note 1
+
+ signal next_pavr_s4_s6_rfwr_addr1 : std_logic_vector(4 downto 0);
+ signal next_pavr_s4_s61_rfwr_addr2 : std_logic_vector(4 downto 0);
+ signal pavr_s5_dacu_rfwr_di : std_logic_vector(7 downto 0); -- Note 1
+
+ -- Pointer registers-related
+ signal next_pavr_s4_s5_ldstincrampx_xwr_rq : std_logic;
+ signal next_pavr_s4_s5_ldstdecrampx_xwr_rq : std_logic;
+
+ signal next_pavr_s4_s5_ldstincrampy_ywr_rq : std_logic;
+ signal next_pavr_s4_s5_ldstdecrampy_ywr_rq : std_logic;
+
+ signal next_pavr_s4_s5_ldstincrampz_zwr_rq : std_logic;
+ signal next_pavr_s4_s5_ldstdecrampz_zwr_rq : std_logic;
+ signal next_pavr_s4_s5_elpmincrampz_zwr_rq : std_logic;
+ signal next_pavr_s4_s5_lpminc_zwr_rq : std_logic;
+
+ -- BPU read
+ signal pavr_xbpu: std_logic_vector(15 downto 0);
+ signal pavr_ybpu: std_logic_vector(15 downto 0);
+ signal pavr_zbpu: std_logic_vector(15 downto 0);
+
+ -- BPU write, BPR0-related
+ signal next_pavr_s4_s5_alu_bpr0wr_rq : std_logic;
+ signal next_pavr_s4_s6_iof_bpr0wr_rq : std_logic;
+ signal next_pavr_s4_s6_daculd_bpr0wr_rq : std_logic;
+ signal pavr_s5_dacust_bpr0wr_rq : std_logic; -- Note 1
+ signal next_pavr_s4_s6_pmdo_bpr0wr_rq : std_logic;
+
+ signal next_pavr_bpr0 : std_logic_vector(7 downto 0);
+ signal next_pavr_bpr0_addr : std_logic_vector(4 downto 0);
+ signal next_pavr_bpr0_active : std_logic;
+
+ -- BPU write, BPR1-related
+ signal next_pavr_s4_s5_dacux_bpr12wr_rq : std_logic;
+ signal next_pavr_s4_s5_dacuy_bpr12wr_rq : std_logic;
+ signal next_pavr_s4_s5_dacuz_bpr12wr_rq : std_logic;
+ signal next_pavr_s4_s5_alu_bpr1wr_rq : std_logic;
+
+ signal next_pavr_bpr1 : std_logic_vector(7 downto 0);
+ signal next_pavr_bpr1_addr : std_logic_vector(4 downto 0);
+ signal next_pavr_bpr1_active : std_logic;
+
+ -- BPU write, BPR2-related
+
+ signal next_pavr_bpr2 : std_logic_vector(7 downto 0);
+ signal next_pavr_bpr2_addr : std_logic_vector(4 downto 0);
+ signal next_pavr_bpr2_active : std_logic;
+
+ -- IOF port-related
+ signal next_pavr_s4_s5_iof_rq : std_logic;
+ signal next_pavr_s4_s6_iof_rq : std_logic;
+ signal pavr_s5_dacu_iof_rq : std_logic; -- Note 1
+
+ signal next_pavr_s4_s5_iof_opcode : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
+ signal next_pavr_s4_s6_iof_opcode : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
+ signal next_pavr_s4_s5s6_iof_addr : std_logic_vector(5 downto 0);
+ signal next_pavr_s4_s5s6_iof_bitaddr : std_logic_vector(2 downto 0);
+ signal pavr_s5_dacu_iofwr_di : std_logic_vector(7 downto 0); -- Note 1
+
+ -- SREG-related
+ signal next_pavr_s4_s5_alu_sregwr_rq : std_logic;
+ signal next_pavr_s4_s5_clriflag_sregwr_rq : std_logic;
+ signal next_pavr_s4_s5_setiflag_sregwr_rq : std_logic;
+
+ -- SP-related
+ signal next_pavr_s4_s5_inc_spwr_rq : std_logic;
+ signal next_pavr_s4_s5_dec_spwr_rq : std_logic;
+ signal next_pavr_s4_s5s51s52_calldec_spwr_rq : std_logic;
+ signal next_pavr_s4_s5s51_retinc_spwr_rq : std_logic;
+
+ -- ALU-related
+ signal next_pavr_s4_s5_alu_opcode : std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
+ signal next_pavr_s4_s5_alu_op1_hi8_sel : std_logic;
+ signal next_pavr_s4_s5_alu_op2_sel : std_logic_vector(pavr_alu_op2_sel_w - 1 downto 0);
+ signal next_pavr_s4_s5_k8 : std_logic_vector(7 downto 0);
+ signal pavr_s5_op1bpu : std_logic_vector(7 downto 0); -- Note 1
+ signal pavr_s5_op2bpu : std_logic_vector(7 downto 0); -- Note 1
+ signal pavr_s5_alu_op1 : std_logic_vector(15 downto 0); -- Note 1
+ signal pavr_s5_alu_op2 : std_logic_vector( 7 downto 0); -- Note 1
+ signal pavr_s5_alu_flagsin : std_logic_vector(5 downto 0); -- Note 1
+ signal pavr_s5_alu_flagsout : std_logic_vector(5 downto 0); -- Note 1
+ signal pavr_s5_alu_out : std_logic_vector(15 downto 0); -- Note 1
+
+ -- DACU setup-related
+ signal next_pavr_s4_dacu_q : std_logic_vector(7 downto 0);
+ signal pavr_s4_iof_dacu_q : std_logic_vector(7 downto 0); -- Note 1
+ signal pavr_s4_dm_dacu_q : std_logic_vector(7 downto 0); -- Note 1
+ signal pavr_s5_dacudo_sel : std_logic_vector(1 downto 0); -- Note 1
+ signal pavr_dacu_do : std_logic_vector(7 downto 0); -- Note 1
+ signal pavr_s5_dacust_rf_addr : std_logic_vector(4 downto 0); -- Note 1
+ signal pavr_s5_dacu_iof_addr : std_logic_vector(5 downto 0); -- Note 1
+ signal pavr_s5_dacu_dm_addr : std_logic_vector(23 downto 0); -- Note 1
+ signal pavr_s5_dacu_iof_opcode : std_logic_vector(pavr_iof_opcode_w - 1 downto 0); -- Note 1
+
+ -- DACU read-related
+ signal next_pavr_s4_s5_x_dacurd_rq : std_logic;
+ signal next_pavr_s4_s5_y_dacurd_rq : std_logic;
+ signal next_pavr_s4_s5_z_dacurd_rq : std_logic;
+ signal next_pavr_s4_s5_sp_dacurd_rq : std_logic;
+ signal next_pavr_s4_s5_k16_dacurd_rq : std_logic;
+ signal next_pavr_s4_s5s51s52_pc_dacurd_rq : std_logic;
+
+ -- DACU write-related
+ signal next_pavr_s4_s5_sp_dacuwr_rq : std_logic;
+ signal next_pavr_s4_s5_k16_dacuwr_rq : std_logic;
+ signal next_pavr_s4_s5_x_dacuwr_rq : std_logic;
+ signal next_pavr_s4_s5_y_dacuwr_rq : std_logic;
+ signal next_pavr_s4_s5_z_dacuwr_rq : std_logic;
+ signal next_pavr_s4_s5s51s52_pc_dacuwr_rq : std_logic;
+
+ -- DM-related
+ signal pavr_s5_dacu_dmrd_rq : std_logic; -- Note 1
+ signal pavr_s5_dacu_dmwr_rq : std_logic; -- Note 1
+
+ signal pavr_s5_dacu_dmwr_di : std_logic_vector(7 downto 0); -- Note 1
+
+ -- PM access-related
+ signal next_pavr_s4_s5_lpm_pm_rq : std_logic;
+ signal next_pavr_s4_s5_elpm_pm_rq : std_logic;
+ signal next_pavr_s4_z_pm_rq : std_logic;
+ signal next_pavr_s4_zeind_pm_rq : std_logic;
+ signal next_pavr_s4_k22abs_pm_rq : std_logic;
+ signal next_pavr_s4_k12rel_pm_rq : std_logic;
+ signal next_pavr_s4_k22int_pm_rq : std_logic;
+ signal next_pavr_s4_s54_ret_pm_rq : std_logic;
+ signal pavr_s6_branch_pm_rq : std_logic; -- Note 1
+ signal pavr_s6_skip_pm_rq : std_logic; -- Note 1
+ signal pavr_s61_skip_pm_rq : std_logic; -- Note 1
+
+ signal next_pavr_s4_k6 : std_logic_vector(5 downto 0);
+ signal next_pavr_s4_k12 : std_logic_vector(11 downto 0);
+ signal next_pavr_s4_k22int : std_logic_vector(21 downto 0);
+ signal next_pavr_s4_s51s52s53_retpc_ld : std_logic;
+ signal next_pavr_s4_pcinc : std_logic;
+
+ -- PC handling-related
+ signal next_pavr_s1_pc : std_logic_vector(21 downto 0); -- Note 1
+ signal next_pavr_s2_pc : std_logic_vector(21 downto 0); -- Note 1
+ signal next_pavr_s3_pc : std_logic_vector(21 downto 0); -- Note 1
+ signal pavr_pm_addr_int : std_logic_vector(21 downto 0); -- Note 1
+ signal next_pavr_s2_pmdo_valid : std_logic; -- Note 1
+ signal next_pavr_s3_instr : std_logic_vector(15 downto 0); -- Note 1
+ signal pavr_grant_control_flow_access : std_logic; -- Note 1
+
+ -- SFU requests-related
+ signal pavr_s3_stall_rq : std_logic; -- *** Note 1
+ signal next_pavr_s4_stall_rq : std_logic;
+ signal next_pavr_s4_s5_stall_rq : std_logic;
+ signal next_pavr_s4_s6_stall_rq : std_logic;
+ signal pavr_s3_flush_s2_rq : std_logic;
+ signal next_pavr_s4_flush_s2_rq : std_logic;
+ signal next_pavr_s4_ret_flush_s2_rq : std_logic;
+ signal next_pavr_s6_skip_rq : std_logic; -- Note 1
+ signal next_pavr_s61_skip_rq : std_logic; -- Note 1
+ signal next_pavr_s6_branch_rq : std_logic; -- Note 1
+ signal next_pavr_s4_nop_rq : std_logic;
+
+ signal next_pavr_s4_s5_skip_cond_sel : std_logic_vector(pavr_s5_skip_cond_sel_w - 1 downto 0);
+ signal next_pavr_s4_s6_skip_cond_sel : std_logic;
+ signal next_pavr_s4_s5_skip_en : std_logic;
+ signal next_pavr_s4_s6_skip_en : std_logic;
+ signal next_pavr_s4_s5_skip_bitrf_sel : std_logic_vector(2 downto 0);
+ signal next_pavr_s4_s6_skip_bitiof_sel : std_logic_vector(2 downto 0);
+ signal next_pavr_s4_s5_k7_branch_offset : std_logic_vector(6 downto 0);
+ signal next_pavr_s4_s5_branch_cond_sel : std_logic;
+ signal next_pavr_s4_s5_branch_en : std_logic;
+ signal next_pavr_s4_s5_branch_bitsreg_sel : std_logic_vector(2 downto 0);
+
+ -- SFU outputs
+ signal pavr_stall_s1: std_logic; -- Note 1
+ signal pavr_stall_s2: std_logic; -- Note 1
+ signal pavr_stall_s3: std_logic; -- Note 1
+ signal pavr_stall_s4: std_logic; -- Note 1
+ signal pavr_stall_s5: std_logic; -- Note 1
+ signal pavr_stall_s6: std_logic; -- Note 1
+ signal pavr_flush_s1: std_logic; -- Note 1
+ signal pavr_flush_s2: std_logic; -- Note 1
+ signal pavr_flush_s3: std_logic; -- Note 1
+ signal pavr_flush_s4: std_logic; -- Note 1
+ signal pavr_flush_s5: std_logic; -- Note 1
+ signal pavr_flush_s6: std_logic; -- Note 1
+ signal pavr_stall_bpu: std_logic; -- Note 1
+ signal pavr_s61_hwrq_en: std_logic; -- Note 1 These signals signalize whether or not hardware resource requests can safely be acknowledged.
+ signal pavr_s6_hwrq_en: std_logic; -- Note 1
+ signal pavr_s5_hwrq_en: std_logic; -- Note 1
+ signal pavr_s4_hwrq_en: std_logic; -- Note 1
+ signal pavr_s3_hwrq_en: std_logic; -- Note 1
+ signal pavr_s2_hwrq_en: std_logic; -- Note 1
+ signal pavr_s1_hwrq_en: std_logic; -- Note 1
+
+ -- Others
+ signal next_pavr_s4_instr32bits : std_logic;
+ signal next_pavr_s4_disable_int : std_logic;
+ signal pavr_disable_int : std_logic;
+ signal pavr_int_rq : std_logic; -- Note 1
+ signal pavr_int_vec : std_logic_vector(21 downto 0); -- Note 1
+
+
+
+ -- Wires for RF, IOF and DM connectivity
+
+ -- RF read port 1
+ signal pavr_rf_rd1_addr : std_logic_vector(4 downto 0);
+ signal pavr_rf_rd1_rd : std_logic;
+ signal pavr_rf_rd1_do : std_logic_vector(7 downto 0);
+
+ -- RF read port 2
+ signal pavr_rf_rd2_addr : std_logic_vector(4 downto 0);
+ signal pavr_rf_rd2_rd : std_logic;
+ signal pavr_rf_rd2_do : std_logic_vector(7 downto 0);
+
+ -- RF write port
+ signal pavr_rf_wr_addr : std_logic_vector(4 downto 0);
+ signal pavr_rf_wr_wr : std_logic;
+ signal pavr_rf_wr_di : std_logic_vector(7 downto 0);
+
+ -- X pointer port
+ signal pavr_rf_x : std_logic_vector(15 downto 0);
+ signal pavr_rf_x_wr : std_logic;
+ signal pavr_rf_x_di : std_logic_vector(15 downto 0);
+
+ -- Y pointer port
+ signal pavr_rf_y : std_logic_vector(15 downto 0);
+ signal pavr_rf_y_wr : std_logic;
+ signal pavr_rf_y_di : std_logic_vector(15 downto 0);
+
+ -- Z pointer port
+ signal pavr_rf_z : std_logic_vector(15 downto 0);
+ signal pavr_rf_z_wr : std_logic;
+ signal pavr_rf_z_di : std_logic_vector(15 downto 0);
+
+ -- IOF general read and write port
+ signal pavr_iof_opcode : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
+ signal pavr_iof_addr : std_logic_vector(5 downto 0);
+ signal pavr_iof_di : std_logic_vector(7 downto 0);
+ signal pavr_iof_do : std_logic_vector(7 downto 0);
+ signal pavr_iof_bitaddr : std_logic_vector(2 downto 0);
+ signal pavr_iof_bitout : std_logic;
+
+ -- SREG port
+ signal pavr_iof_sreg : std_logic_vector(7 downto 0);
+ signal pavr_iof_sreg_wr : std_logic;
+ signal pavr_iof_sreg_di : std_logic_vector(7 downto 0);
+
+ -- SP port
+ signal pavr_iof_spl : std_logic_vector(7 downto 0);
+ signal pavr_iof_spl_wr : std_logic;
+ signal pavr_iof_spl_di : std_logic_vector(7 downto 0);
+
+ signal pavr_iof_sph : std_logic_vector(7 downto 0);
+ signal pavr_iof_sph_wr : std_logic;
+ signal pavr_iof_sph_di : std_logic_vector(7 downto 0);
+
+ -- RAMPX port
+ signal pavr_iof_rampx : std_logic_vector(7 downto 0);
+ signal pavr_iof_rampx_wr : std_logic;
+ signal pavr_iof_rampx_di : std_logic_vector(7 downto 0);
+
+ -- RAMPY port
+ signal pavr_iof_rampy : std_logic_vector(7 downto 0);
+ signal pavr_iof_rampy_wr : std_logic;
+ signal pavr_iof_rampy_di : std_logic_vector(7 downto 0);
+
+ -- RAMPZ port
+ signal pavr_iof_rampz : std_logic_vector(7 downto 0);
+ signal pavr_iof_rampz_wr : std_logic;
+ signal pavr_iof_rampz_di : std_logic_vector(7 downto 0);
+
+ -- RAMPD port
+ signal pavr_iof_rampd : std_logic_vector(7 downto 0);
+ signal pavr_iof_rampd_wr : std_logic;
+ signal pavr_iof_rampd_di : std_logic_vector(7 downto 0);
+
+ -- EIND port
+ signal pavr_iof_eind : std_logic_vector(7 downto 0);
+ signal pavr_iof_eind_wr : std_logic;
+ signal pavr_iof_eind_di : std_logic_vector(7 downto 0);
+
+ -- DM port
+ signal pavr_dm_do : std_logic_vector(7 downto 0);
+ signal pavr_dm_wr : std_logic;
+ signal pavr_dm_addr : std_logic_vector(pavr_dm_addr_w - 1 downto 0);
+ signal pavr_dm_di : std_logic_vector(7 downto 0);
+
+ -- Registers ---------------------------------------------------------------
+
+ -- RF read port 1-related
+ -- No registers related to requests to RF read port 1.
+
+ signal pavr_s5_op1 : std_logic_vector(7 downto 0);
+
+ -- RF read port 2-related
+ -- No registers related to requests to RF read port 2.
+
+ signal pavr_s5_op2 : std_logic_vector(7 downto 0);
+
+ -- RF write port-related
+ signal pavr_s4_s6_aluoutlo8_rfwr_rq : std_logic;
+ signal pavr_s5_s6_aluoutlo8_rfwr_rq : std_logic;
+ signal pavr_s6_aluoutlo8_rfwr_rq : std_logic;
+ signal pavr_s4_s61_aluouthi8_rfwr_rq : std_logic;
+ signal pavr_s5_s61_aluouthi8_rfwr_rq : std_logic;
+ signal pavr_s6_s61_aluouthi8_rfwr_rq : std_logic;
+ signal pavr_s61_aluouthi8_rfwr_rq : std_logic;
+ signal pavr_s4_s6_iof_rfwr_rq : std_logic;
+ signal pavr_s5_s6_iof_rfwr_rq : std_logic;
+ signal pavr_s6_iof_rfwr_rq : std_logic;
+ signal pavr_s4_s6_dacu_rfwr_rq : std_logic;
+ signal pavr_s5_s6_dacu_rfwr_rq : std_logic;
+ signal pavr_s6_dacu_rfwr_rq : std_logic;
+ signal pavr_s4_s6_pm_rfwr_rq : std_logic;
+ signal pavr_s5_s6_pm_rfwr_rq : std_logic;
+ signal pavr_s6_pm_rfwr_rq : std_logic;
+
+ signal pavr_s4_s6_rfwr_addr1 : std_logic_vector(4 downto 0);
+ signal pavr_s5_s6_rfwr_addr1 : std_logic_vector(4 downto 0);
+ signal pavr_s6_rfwr_addr1 : std_logic_vector(4 downto 0);
+ signal pavr_s4_s61_rfwr_addr2 : std_logic_vector(4 downto 0);
+ signal pavr_s5_s61_rfwr_addr2 : std_logic_vector(4 downto 0);
+ signal pavr_s6_s61_rfwr_addr2 : std_logic_vector(4 downto 0);
+ signal pavr_s61_rfwr_addr2 : std_logic_vector(4 downto 0);
+
+ -- Pointer registers-related
+ signal pavr_s4_s5_ldstincrampx_xwr_rq : std_logic;
+ signal pavr_s5_ldstincrampx_xwr_rq : std_logic;
+ signal pavr_s4_s5_ldstdecrampx_xwr_rq : std_logic;
+ signal pavr_s5_ldstdecrampx_xwr_rq : std_logic;
+
+ signal pavr_s4_s5_ldstincrampy_ywr_rq : std_logic;
+ signal pavr_s5_ldstincrampy_ywr_rq : std_logic;
+ signal pavr_s4_s5_ldstdecrampy_ywr_rq : std_logic;
+ signal pavr_s5_ldstdecrampy_ywr_rq : std_logic;
+
+ signal pavr_s4_s5_ldstincrampz_zwr_rq : std_logic;
+ signal pavr_s5_ldstincrampz_zwr_rq : std_logic;
+ signal pavr_s4_s5_ldstdecrampz_zwr_rq : std_logic;
+ signal pavr_s5_ldstdecrampz_zwr_rq : std_logic;
+ signal pavr_s4_s5_elpmincrampz_zwr_rq : std_logic;
+ signal pavr_s5_elpmincrampz_zwr_rq : std_logic;
+ signal pavr_s4_s5_lpminc_zwr_rq : std_logic;
+ signal pavr_s5_lpminc_zwr_rq : std_logic;
+
+ -- BPU write, BPR0-related
+ signal pavr_s4_s5_alu_bpr0wr_rq : std_logic;
+ signal pavr_s5_alu_bpr0wr_rq : std_logic;
+ signal pavr_s4_s6_iof_bpr0wr_rq : std_logic;
+ signal pavr_s5_s6_iof_bpr0wr_rq : std_logic;
+ signal pavr_s6_iof_bpr0wr_rq : std_logic;
+ signal pavr_s4_s6_daculd_bpr0wr_rq : std_logic;
+ signal pavr_s5_s6_daculd_bpr0wr_rq : std_logic;
+ signal pavr_s6_daculd_bpr0wr_rq : std_logic;
+ signal pavr_s4_s6_pmdo_bpr0wr_rq : std_logic;
+ signal pavr_s5_s6_pmdo_bpr0wr_rq : std_logic;
+ signal pavr_s6_pmdo_bpr0wr_rq : std_logic;
+
+ signal pavr_bpr00 : std_logic_vector(7 downto 0); -- Bypass chain 0 and associated registers. Note 1
+ signal pavr_bpr00_addr : std_logic_vector(4 downto 0);
+ signal pavr_bpr00_active : std_logic;
+ signal pavr_bpr01 : std_logic_vector(7 downto 0);
+ signal pavr_bpr01_addr : std_logic_vector(4 downto 0);
+ signal pavr_bpr01_active : std_logic;
+ signal pavr_bpr02 : std_logic_vector(7 downto 0);
+ signal pavr_bpr02_addr : std_logic_vector(4 downto 0);
+ signal pavr_bpr02_active : std_logic;
+ signal pavr_bpr03 : std_logic_vector(7 downto 0);
+ signal pavr_bpr03_addr : std_logic_vector(4 downto 0);
+ signal pavr_bpr03_active : std_logic;
+
+ -- BPU write, BPR1-related
+ signal pavr_s4_s5_dacux_bpr12wr_rq : std_logic;
+ signal pavr_s5_dacux_bpr12wr_rq : std_logic;
+ signal pavr_s4_s5_dacuy_bpr12wr_rq : std_logic;
+ signal pavr_s5_dacuy_bpr12wr_rq : std_logic;
+ signal pavr_s4_s5_dacuz_bpr12wr_rq : std_logic;
+ signal pavr_s5_dacuz_bpr12wr_rq : std_logic;
+ signal pavr_s4_s5_alu_bpr1wr_rq : std_logic;
+ signal pavr_s5_alu_bpr1wr_rq : std_logic;
+
+ signal pavr_bpr10 : std_logic_vector(7 downto 0); -- Bypass chain 1 and associated registers. Note 1
+ signal pavr_bpr10_addr : std_logic_vector(4 downto 0);
+ signal pavr_bpr10_active : std_logic;
+ signal pavr_bpr11 : std_logic_vector(7 downto 0);
+ signal pavr_bpr11_addr : std_logic_vector(4 downto 0);
+ signal pavr_bpr11_active : std_logic;
+ signal pavr_bpr12 : std_logic_vector(7 downto 0);
+ signal pavr_bpr12_addr : std_logic_vector(4 downto 0);
+ signal pavr_bpr12_active : std_logic;
+ signal pavr_bpr13 : std_logic_vector(7 downto 0);
+ signal pavr_bpr13_addr : std_logic_vector(4 downto 0);
+ signal pavr_bpr13_active : std_logic;
+
+ -- BPU write, BPR2-related
+
+ signal pavr_bpr20 : std_logic_vector(7 downto 0); -- Bypass chain 2 and associated registers. Note 1
+ signal pavr_bpr20_addr : std_logic_vector(4 downto 0);
+ signal pavr_bpr20_active : std_logic;
+ signal pavr_bpr21 : std_logic_vector(7 downto 0);
+ signal pavr_bpr21_addr : std_logic_vector(4 downto 0);
+ signal pavr_bpr21_active : std_logic;
+ signal pavr_bpr22 : std_logic_vector(7 downto 0);
+ signal pavr_bpr22_addr : std_logic_vector(4 downto 0);
+ signal pavr_bpr22_active : std_logic;
+ signal pavr_bpr23 : std_logic_vector(7 downto 0);
+ signal pavr_bpr23_addr : std_logic_vector(4 downto 0);
+ signal pavr_bpr23_active : std_logic;
+
+ -- IOF port-related
+ signal pavr_s4_s5_iof_rq : std_logic;
+ signal pavr_s5_iof_rq : std_logic;
+ signal pavr_s4_s6_iof_rq : std_logic;
+ signal pavr_s5_s6_iof_rq : std_logic;
+ signal pavr_s6_iof_rq : std_logic;
+
+ signal pavr_s4_s5_iof_opcode : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
+ signal pavr_s5_iof_opcode : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
+ signal pavr_s4_s6_iof_opcode : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
+ signal pavr_s5_s6_iof_opcode : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
+ signal pavr_s6_iof_opcode : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
+ signal pavr_s4_s5s6_iof_addr : std_logic_vector(5 downto 0);
+ signal pavr_s5_iof_addr : std_logic_vector(5 downto 0);
+ signal pavr_s6_iof_addr : std_logic_vector(5 downto 0);
+ signal pavr_s4_s5s6_iof_bitaddr : std_logic_vector(2 downto 0);
+ signal pavr_s5_iof_bitaddr : std_logic_vector(2 downto 0);
+ signal pavr_s6_iof_bitaddr : std_logic_vector(2 downto 0);
+
+ -- SREG-related
+ signal pavr_s4_s5_alu_sregwr_rq : std_logic;
+ signal pavr_s5_alu_sregwr_rq : std_logic;
+ signal pavr_s4_s5_clriflag_sregwr_rq : std_logic;
+ signal pavr_s5_clriflag_sregwr_rq : std_logic;
+ signal pavr_s4_s5_setiflag_sregwr_rq : std_logic;
+ signal pavr_s5_setiflag_sregwr_rq : std_logic;
+
+ -- SP-related
+ signal pavr_s4_s5_inc_spwr_rq : std_logic;
+ signal pavr_s5_inc_spwr_rq : std_logic;
+ signal pavr_s4_s5_dec_spwr_rq : std_logic;
+ signal pavr_s5_dec_spwr_rq : std_logic;
+ signal pavr_s4_s5s51s52_calldec_spwr_rq : std_logic;
+ signal pavr_s5_calldec_spwr_rq : std_logic;
+ signal pavr_s51_calldec_spwr_rq : std_logic;
+ signal pavr_s52_calldec_spwr_rq : std_logic;
+ signal pavr_s4_s5s51_retinc_spwr_rq : std_logic;
+ signal pavr_s5_retinc2_spwr_rq : std_logic;
+ signal pavr_s51_retinc_spwr_rq : std_logic;
+
+ -- ALU-related
+ signal pavr_s4_s5_alu_opcode : std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
+ signal pavr_s5_alu_opcode : std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
+ signal pavr_s4_s5_alu_op1_hi8_sel : std_logic;
+ signal pavr_s5_alu_op1_hi8_sel : std_logic;
+ signal pavr_s4_s5_alu_op2_sel : std_logic_vector(pavr_alu_op2_sel_w - 1 downto 0);
+ signal pavr_s5_alu_op2_sel : std_logic_vector(pavr_alu_op2_sel_w - 1 downto 0);
+ signal pavr_s4_s5_op1_addr : std_logic_vector(4 downto 0);
+ signal pavr_s5_op1_addr : std_logic_vector(4 downto 0);
+ signal pavr_s4_s5_op2_addr : std_logic_vector(4 downto 0);
+ signal pavr_s5_op2_addr : std_logic_vector(4 downto 0);
+ signal pavr_s4_s5_k8 : std_logic_vector(7 downto 0);
+ signal pavr_s5_k8 : std_logic_vector(7 downto 0);
+ signal pavr_s6_alu_out : std_logic_vector(15 downto 0);
+ signal pavr_s61_alu_out_hi8 : std_logic_vector( 7 downto 0);
+
+ -- DACU setup-related
+ signal pavr_s4_dacu_q : std_logic_vector(7 downto 0);
+ signal pavr_s5_rf_dacu_q : std_logic_vector(7 downto 0);
+ signal pavr_s5_iof_dacu_q : std_logic_vector(7 downto 0);
+ signal pavr_s5_dm_dacu_q : std_logic_vector(7 downto 0);
+ signal pavr_s6_dacudo_sel : std_logic_vector(1 downto 0);
+ signal pavr_s5_k16 : std_logic_vector(15 downto 0); -- *** Attention: no `pavr_s4_s5_k16'. `pavr_s5_k16' is fed directly from stage s3.
+
+ -- DACU read-related
+ signal pavr_s4_s5_x_dacurd_rq : std_logic;
+ signal pavr_s5_x_dacurd_rq : std_logic;
+ signal pavr_s4_s5_y_dacurd_rq : std_logic;
+ signal pavr_s5_y_dacurd_rq : std_logic;
+ signal pavr_s4_s5_z_dacurd_rq : std_logic;
+ signal pavr_s5_z_dacurd_rq : std_logic;
+ signal pavr_s4_s5_sp_dacurd_rq : std_logic;
+ signal pavr_s5_sp_dacurd_rq : std_logic;
+ signal pavr_s4_s5_k16_dacurd_rq : std_logic;
+ signal pavr_s5_k16_dacurd_rq : std_logic;
+ signal pavr_s4_s5s51s52_pc_dacurd_rq : std_logic;
+ signal pavr_s5_pchi8_dacurd_rq : std_logic;
+ signal pavr_s51_pcmid8_dacurd_rq : std_logic;
+ signal pavr_s52_pclo8_dacurd_rq : std_logic;
+
+ -- DACU write-related
+ signal pavr_s4_s5_sp_dacuwr_rq : std_logic;
+ signal pavr_s5_sp_dacuwr_rq : std_logic;
+ signal pavr_s4_s5_k16_dacuwr_rq : std_logic;
+ signal pavr_s5_k16_dacuwr_rq : std_logic;
+ signal pavr_s4_s5_x_dacuwr_rq : std_logic;
+ signal pavr_s5_x_dacuwr_rq : std_logic;
+ signal pavr_s4_s5_y_dacuwr_rq : std_logic;
+ signal pavr_s5_y_dacuwr_rq : std_logic;
+ signal pavr_s4_s5_z_dacuwr_rq : std_logic;
+ signal pavr_s5_z_dacuwr_rq : std_logic;
+ signal pavr_s4_s5s51s52_pc_dacuwr_rq : std_logic;
+ signal pavr_s5_pclo8_dacuwr_rq : std_logic;
+ signal pavr_s51_pcmid8_dacuwr_rq : std_logic;
+ signal pavr_s52_pchi8_dacuwr_rq : std_logic;
+
+ -- DM-related
+
+ -- PM access-related
+ signal pavr_s4_s5_lpm_pm_rq : std_logic;
+ signal pavr_s5_lpm_pm_rq : std_logic;
+ signal pavr_s4_s5_elpm_pm_rq : std_logic;
+ signal pavr_s5_elpm_pm_rq : std_logic;
+ signal pavr_s4_z_pm_rq : std_logic;
+ signal pavr_s4_zeind_pm_rq : std_logic;
+ signal pavr_s4_k22abs_pm_rq : std_logic;
+ signal pavr_s4_k12rel_pm_rq : std_logic;
+ signal pavr_s4_k22int_pm_rq : std_logic;
+ signal pavr_s4_s54_ret_pm_rq : std_logic;
+ signal pavr_s5_s54_ret_pm_rq : std_logic;
+ signal pavr_s51_s54_ret_pm_rq : std_logic;
+ signal pavr_s52_s54_ret_pm_rq : std_logic;
+ signal pavr_s53_s54_ret_pm_rq : std_logic;
+ signal pavr_s54_ret_pm_rq : std_logic;
+
+ signal pavr_s4_k6 : std_logic_vector(5 downto 0);
+ signal pavr_s4_k12 : std_logic_vector(11 downto 0);
+ signal pavr_s4_k22int : std_logic_vector(21 downto 0);
+ signal pavr_s2_pc : std_logic_vector(21 downto 0);
+ signal pavr_s3_pc : std_logic_vector(21 downto 0);
+ signal pavr_s4_pc : std_logic_vector(21 downto 0);
+ signal pavr_s5_pc : std_logic_vector(21 downto 0);
+ signal pavr_s51_pc : std_logic_vector(21 downto 0);
+ signal pavr_s52_pc : std_logic_vector(21 downto 0);
+ signal pavr_s4_pcinc : std_logic;
+ signal pavr_s4_s51s52s53_retpc_ld : std_logic;
+ signal pavr_s5_s51s52s53_retpc_ld : std_logic;
+ signal pavr_s51_retpchi8_ld : std_logic;
+ signal pavr_s52_retpcmid8_ld : std_logic;
+ signal pavr_s53_retpclo8_ld : std_logic;
+ signal pavr_s52_retpchi8 : std_logic_vector(7 downto 0);
+ signal pavr_s53_retpcmid8 : std_logic_vector(7 downto 0);
+ signal pavr_s54_retpclo8 : std_logic_vector(7 downto 0);
+ signal pavr_s1_pc : std_logic_vector(21 downto 0);
+ signal pavr_s2_pmdo_valid : std_logic;
+
+ signal pavr_s6_zlsb : std_logic; -- Needed by LPM instructions to select low/high byte read.
+
+ -- SFU requests-related
+ signal pavr_s4_stall_rq : std_logic;
+ signal pavr_s4_s5_stall_rq : std_logic;
+ signal pavr_s5_stall_rq : std_logic;
+ signal pavr_s4_s6_stall_rq : std_logic;
+ signal pavr_s5_s6_stall_rq : std_logic;
+ signal pavr_s6_stall_rq : std_logic;
+ signal pavr_s4_flush_s2_rq : std_logic;
+ signal pavr_s4_ret_flush_s2_rq : std_logic;
+ signal pavr_s5_ret_flush_s2_rq : std_logic;
+ signal pavr_s51_ret_flush_s2_rq : std_logic;
+ signal pavr_s52_ret_flush_s2_rq : std_logic;
+ signal pavr_s53_ret_flush_s2_rq : std_logic;
+ signal pavr_s54_ret_flush_s2_rq : std_logic;
+ signal pavr_s55_ret_flush_s2_rq : std_logic;
+ signal pavr_s6_skip_rq : std_logic;
+ signal pavr_s61_skip_rq : std_logic;
+ signal pavr_s6_branch_rq : std_logic;
+ signal pavr_s4_nop_rq : std_logic;
+
+ signal pavr_s4_s5_skip_cond_sel : std_logic_vector(pavr_s5_skip_cond_sel_w - 1 downto 0);
+ signal pavr_s5_skip_cond_sel : std_logic_vector(pavr_s5_skip_cond_sel_w - 1 downto 0);
+ signal pavr_s4_s6_skip_cond_sel : std_logic;
+ signal pavr_s5_s6_skip_cond_sel : std_logic;
+ signal pavr_s6_skip_cond_sel : std_logic;
+ signal pavr_s4_s5_skip_en : std_logic;
+ signal pavr_s5_skip_en : std_logic;
+ signal pavr_s4_s6_skip_en : std_logic;
+ signal pavr_s5_s6_skip_en : std_logic;
+ signal pavr_s6_skip_en : std_logic;
+ signal pavr_s4_s5_skip_bitrf_sel : std_logic_vector(2 downto 0);
+ signal pavr_s5_skip_bitrf_sel : std_logic_vector(2 downto 0);
+ signal pavr_s4_s6_skip_bitiof_sel : std_logic_vector(2 downto 0);
+ signal pavr_s5_s6_skip_bitiof_sel : std_logic_vector(2 downto 0);
+ signal pavr_s6_skip_bitiof_sel : std_logic_vector(2 downto 0);
+
+ signal pavr_s4_s5_k7_branch_offset : std_logic_vector(6 downto 0);
+ signal pavr_s5_k7_branch_offset : std_logic_vector(6 downto 0);
+ signal pavr_s6_branch_pc : std_logic_vector(21 downto 0);
+ signal pavr_s4_s5_branch_cond_sel : std_logic;
+ signal pavr_s5_branch_cond_sel : std_logic;
+ signal pavr_s4_s5_branch_en : std_logic;
+ signal pavr_s5_branch_en : std_logic;
+ signal pavr_s4_s5_branch_bitsreg_sel : std_logic_vector(2 downto 0);
+ signal pavr_s5_branch_bitsreg_sel : std_logic_vector(2 downto 0);
+
+ -- Others
+ signal pavr_nop_ack : std_logic; -- Nop state machine's memory. The nop state machine is outside the pipeline.
+ signal pavr_s3_instr : std_logic_vector(15 downto 0); -- Instruction register
+ signal pavr_s4_instr32bits : std_logic; -- Signalizes that this instruction is 32 bits wide. Next word (16 bits) will be ignored by the instruction decoder (nop). It's a constant that will be extracted directly by s5.
+ signal pavr_s4_disable_int : std_logic;
+ signal pavr_s5_disable_int : std_logic;
+ signal pavr_s51_disable_int : std_logic;
+ signal pavr_s52_disable_int : std_logic;
+
+ -- Shadow-related
+ -- Shadow registers hold temporary values already read from memories but not
+ -- yet used because of a stall. See comments at Shadow Manager process.
+ -- RF-related shadow registers
+ signal pavr_rf_rd1_do_shadow : std_logic_vector(7 downto 0);
+ signal pavr_rf_rd2_do_shadow : std_logic_vector(7 downto 0);
+ -- IOF-related shadow registers
+ signal pavr_iof_do_shadow : std_logic_vector(7 downto 0);
+ -- DM-related shadow registers
+ signal pavr_dm_do_shadow : std_logic_vector(7 downto 0);
+ -- DACU-related shadow registers
+ signal pavr_dacu_do_shadow : std_logic_vector(7 downto 0);
+ -- PM-related shadow registers
+ signal pavr_pm_do_shadow : std_logic_vector(15 downto 0);
+ signal pavr_s2_pmdo_valid_shadow : std_logic;
+
+ signal pavr_rf_do_shadow_active : std_logic;
+ signal pavr_iof_do_shadow_active : std_logic;
+ signal pavr_dm_do_shadow_active : std_logic;
+ signal pavr_dacu_do_shadow_active : std_logic;
+ signal pavr_pm_do_shadow_active : std_logic;
+
+
+
+
+
+
+ -- Declare components ------------------------------------------------------
+
+ -- Declare the Register File.
+ component pavr_rf
+ port(
+ pavr_rf_clk: in std_logic;
+ pavr_rf_res: in std_logic;
+ pavr_rf_syncres: in std_logic;
+
+ -- Read port #1
+ pavr_rf_rd1_addr: in std_logic_vector(4 downto 0);
+ pavr_rf_rd1_rd: in std_logic;
+ pavr_rf_rd1_do: out std_logic_vector(7 downto 0);
+
+ -- Read port #2
+ pavr_rf_rd2_addr: in std_logic_vector(4 downto 0);
+ pavr_rf_rd2_rd: in std_logic;
+ pavr_rf_rd2_do: out std_logic_vector(7 downto 0);
+
+ -- Write port
+ pavr_rf_wr_addr: in std_logic_vector(4 downto 0);
+ pavr_rf_wr_wr: in std_logic;
+ pavr_rf_wr_di: in std_logic_vector(7 downto 0);
+
+ -- Pointer registers
+ pavr_rf_x: out std_logic_vector(15 downto 0);
+ pavr_rf_x_wr: in std_logic;
+ pavr_rf_x_di: in std_logic_vector(15 downto 0);
+
+ pavr_rf_y: out std_logic_vector(15 downto 0);
+ pavr_rf_y_wr: in std_logic;
+ pavr_rf_y_di: in std_logic_vector(15 downto 0);
+
+ pavr_rf_z: out std_logic_vector(15 downto 0);
+ pavr_rf_z_wr: in std_logic;
+ pavr_rf_z_di: in std_logic_vector(15 downto 0)
+ );
+ end component;
+ for all: pavr_rf use entity work.pavr_rf(pavr_rf_arch);
+
+ -- Declare the IO File.
+ component pavr_iof
+ port(
+ pavr_iof_clk : in std_logic;
+ pavr_iof_res : in std_logic;
+ pavr_iof_syncres : in std_logic;
+
+ -- General IO file port
+ pavr_iof_opcode : in std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
+ pavr_iof_addr : in std_logic_vector(5 downto 0);
+ pavr_iof_di : in std_logic_vector(7 downto 0);
+ pavr_iof_do : out std_logic_vector(7 downto 0);
+ pavr_iof_bitout : out std_logic;
+ pavr_iof_bitaddr : in std_logic_vector(2 downto 0);
+
+ -- AVR kernel register ports
+ -- Status register (SREG)
+ pavr_iof_sreg : out std_logic_vector(7 downto 0);
+ pavr_iof_sreg_wr : in std_logic;
+ pavr_iof_sreg_di : in std_logic_vector(7 downto 0);
+
+ -- Stack pointer (SP = SPH&SPL)
+ pavr_iof_sph : out std_logic_vector(7 downto 0);
+ pavr_iof_sph_wr : in std_logic;
+ pavr_iof_sph_di : in std_logic_vector(7 downto 0);
+ pavr_iof_spl : out std_logic_vector(7 downto 0);
+ pavr_iof_spl_wr : in std_logic;
+ pavr_iof_spl_di : in std_logic_vector(7 downto 0);
+
+ -- Pointer registers extensions (RAMPX, RAMPY, RAMPZ)
+ pavr_iof_rampx : out std_logic_vector(7 downto 0);
+ pavr_iof_rampx_wr : in std_logic;
+ pavr_iof_rampx_di : in std_logic_vector(7 downto 0);
+
+ pavr_iof_rampy : out std_logic_vector(7 downto 0);
+ pavr_iof_rampy_wr : in std_logic;
+ pavr_iof_rampy_di : in std_logic_vector(7 downto 0);
+
+ pavr_iof_rampz : out std_logic_vector(7 downto 0);
+ pavr_iof_rampz_wr : in std_logic;
+ pavr_iof_rampz_di : in std_logic_vector(7 downto 0);
+
+ -- Data Memory extension address register (RAMPD)
+ pavr_iof_rampd : out std_logic_vector(7 downto 0);
+ pavr_iof_rampd_wr : in std_logic;
+ pavr_iof_rampd_di : in std_logic_vector(7 downto 0);
+
+ -- Program Memory extension address register (EIND)
+ pavr_iof_eind : out std_logic_vector(7 downto 0);
+ pavr_iof_eind_wr : in std_logic;
+ pavr_iof_eind_di : in std_logic_vector(7 downto 0);
+
+ -- AVR non-kernel (feature) register ports
+ -- Port A
+ pavr_iof_pa : inout std_logic_vector(7 downto 0);
+
+ -- Interrupt-related interface signals to control module (to the pipeline).
+ pavr_disable_int : in std_logic;
+ pavr_int_rq : out std_logic;
+ pavr_int_vec : out std_logic_vector(21 downto 0)
+ );
+ end component;
+ for all: pavr_iof use entity work.pavr_iof(pavr_iof_arch);
+
+ -- Declare the Data Memory
+ component pavr_dm
+ port(
+ pavr_dm_clk: in std_logic;
+ pavr_dm_wr: in std_logic;
+ pavr_dm_addr: in std_logic_vector(pavr_dm_addr_w - 1 downto 0);
+ pavr_dm_di: in std_logic_vector(7 downto 0);
+ pavr_dm_do: out std_logic_vector(7 downto 0)
+ );
+ end component;
+ for all: pavr_dm use entity work.pavr_dm(pavr_dm_arch);
+
+ -- Declare the ALU.
+ component pavr_alu
+ port(
+ pavr_alu_op1: in std_logic_vector(15 downto 0);
+ pavr_alu_op2: in std_logic_vector(7 downto 0);
+ pavr_alu_out: out std_logic_vector(15 downto 0);
+ pavr_alu_opcode: in std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
+ pavr_alu_flagsin: in std_logic_vector(5 downto 0);
+ pavr_alu_flagsout: out std_logic_vector(5 downto 0)
+ );
+ end component;
+ for all: pavr_alu use entity work.pavr_alu(pavr_alu_arch);
+
+
+
+begin
+
+ -- Instantiate Components --------------------------------------------------
+
+ -- Instantiate the Register File.
+ pavr_rf_instance1: pavr_rf
+ port map(
+ pavr_clk,
+ pavr_res,
+ pavr_syncres,
+
+ -- Read port #1
+ pavr_rf_rd1_addr,
+ pavr_rf_rd1_rd,
+ pavr_rf_rd1_do,
+
+ -- Read port #2
+ pavr_rf_rd2_addr,
+ pavr_rf_rd2_rd,
+ pavr_rf_rd2_do,
+
+ -- Write port
+ pavr_rf_wr_addr,
+ pavr_rf_wr_wr,
+ pavr_rf_wr_di,
+
+ -- Pointer registers
+ pavr_rf_x,
+ pavr_rf_x_wr,
+ pavr_rf_x_di,
+
+ pavr_rf_y,
+ pavr_rf_y_wr,
+ pavr_rf_y_di,
+
+ pavr_rf_z,
+ pavr_rf_z_wr,
+ pavr_rf_z_di
+ );
+
+ -- Instantiate the IO File.
+ pavr_iof_instance1: pavr_iof
+ port map(
+ pavr_clk,
+ pavr_res,
+ pavr_syncres,
+
+ -- General IO file port
+ pavr_iof_opcode,
+ pavr_iof_addr,
+ pavr_iof_di,
+ pavr_iof_do,
+ pavr_iof_bitout,
+ pavr_iof_bitaddr,
+
+ -- AVR kernel register ports
+ -- Status register (SREG)
+ pavr_iof_sreg,
+ pavr_iof_sreg_wr,
+ pavr_iof_sreg_di,
+
+ -- Stack pointer (SP = SPH&SPL)
+ pavr_iof_sph,
+ pavr_iof_sph_wr,
+ pavr_iof_sph_di,
+ pavr_iof_spl,
+ pavr_iof_spl_wr,
+ pavr_iof_spl_di,
+
+ -- Pointer registers extensions (RAMPX, RAMPY, RAMPZ)
+ pavr_iof_rampx,
+ pavr_iof_rampx_wr,
+ pavr_iof_rampx_di,
+
+ pavr_iof_rampy,
+ pavr_iof_rampy_wr,
+ pavr_iof_rampy_di,
+
+ pavr_iof_rampz,
+ pavr_iof_rampz_wr,
+ pavr_iof_rampz_di,
+
+ -- Data Memory extension address register (RAMPD)
+ pavr_iof_rampd,
+ pavr_iof_rampd_wr,
+ pavr_iof_rampd_di,
+
+ -- Program Memory extension address register (EIND)
+ pavr_iof_eind,
+ pavr_iof_eind_wr,
+ pavr_iof_eind_di,
+
+ -- AVR non-kernel (feature) register ports
+ -- Port A
+ pavr_pa,
+
+ -- Interrupt-related interface signals to control module (to the pipeline).
+ pavr_disable_int,
+ pavr_int_rq,
+ pavr_int_vec
+ );
+
+ -- Instantiate the Data Memory.
+ pavr_dm_instance1: pavr_dm
+ port map(
+ pavr_clk,
+ pavr_dm_wr,
+ pavr_dm_addr,
+ pavr_dm_di,
+ pavr_dm_do
+ );
+
+ -- Instantiate the ALU.
+ pavr_alu_instance1: pavr_alu
+ port map(
+ pavr_s5_alu_op1,
+ pavr_s5_alu_op2,
+ pavr_s5_alu_out,
+ pavr_s5_alu_opcode,
+ pavr_s5_alu_flagsin,
+ pavr_s5_alu_flagsout
+ );
+
+
+
+ -- Main synchronous process ------------------------------------------------
+ -- Basically, assign registers (whether they are inside or outside the pipeline)
+ -- with the values generated by the instruction decoder, from the previous
+ -- stage or other sources outside the pipeline.
+ control_sync:
+ process(pavr_clk, pavr_res, pavr_syncres,
+ pavr_s5_op1, pavr_s5_op2, pavr_s4_s6_rfwr_addr1, pavr_s5_s6_rfwr_addr1, pavr_s6_rfwr_addr1,
+ pavr_s4_s61_rfwr_addr2, pavr_s5_s61_rfwr_addr2, pavr_s6_s61_rfwr_addr2, pavr_s61_rfwr_addr2,
+ pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active, pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active, pavr_bpr02, pavr_bpr02_addr,
+ pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active, pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active, pavr_bpr12, pavr_bpr12_addr,
+ pavr_s4_s5_iof_opcode, pavr_s5_iof_opcode, pavr_s4_s6_iof_opcode, pavr_s5_s6_iof_opcode, pavr_s6_iof_opcode,
+ pavr_s4_s5s6_iof_addr, pavr_s5_iof_addr, pavr_s6_iof_addr, pavr_s4_s5s6_iof_bitaddr, pavr_s5_iof_bitaddr, pavr_s6_iof_bitaddr,
+ pavr_s4_s5_alu_opcode, pavr_s5_alu_opcode, pavr_s4_s5_alu_op2_sel, pavr_s5_alu_op2_sel, pavr_s4_s5_op1_addr, pavr_s5_op1_addr,
+ pavr_s4_s5_op2_addr, pavr_s5_op2_addr, pavr_s4_s5_k8, pavr_s5_k8, pavr_s6_alu_out, pavr_s61_alu_out_hi8, pavr_s4_dacu_q,
+ pavr_s5_rf_dacu_q, pavr_s5_iof_dacu_q, pavr_s5_dm_dacu_q, pavr_s6_dacudo_sel, pavr_s5_k16, pavr_s4_k6, pavr_s4_k12, pavr_s4_k22int,
+ pavr_s1_pc, pavr_s2_pc, pavr_s3_pc, pavr_s4_pc, pavr_s5_pc, pavr_s51_pc, pavr_s52_pc, pavr_s52_retpchi8, pavr_s53_retpcmid8,
+ pavr_s54_retpclo8, pavr_s4_s5_skip_cond_sel, pavr_s5_skip_cond_sel, pavr_s4_s6_skip_cond_sel, pavr_s5_s6_skip_cond_sel,
+ pavr_s4_s5_skip_bitrf_sel, pavr_s5_skip_bitrf_sel, pavr_s4_s6_skip_bitiof_sel, pavr_s5_s6_skip_bitiof_sel,
+ pavr_s6_skip_bitiof_sel, pavr_s4_s5_k7_branch_offset, pavr_s5_k7_branch_offset, pavr_s6_branch_pc, pavr_s4_s5_branch_bitsreg_sel,
+ pavr_s5_branch_bitsreg_sel, pavr_s3_instr, pavr_flush_s3, pavr_flush_s4, pavr_flush_s5,
+ pavr_flush_s6, pavr_stall_s3, next_pavr_s4_s6_aluoutlo8_rfwr_rq,
+ next_pavr_s4_s61_aluouthi8_rfwr_rq, next_pavr_s4_s6_iof_rfwr_rq, next_pavr_s4_s6_dacu_rfwr_rq, next_pavr_s4_s6_pm_rfwr_rq,
+ next_pavr_s4_s6_rfwr_addr1, next_pavr_s4_s61_rfwr_addr2, next_pavr_s4_s5_ldstincrampx_xwr_rq, next_pavr_s4_s5_ldstdecrampx_xwr_rq,
+ next_pavr_s4_s5_ldstincrampy_ywr_rq, next_pavr_s4_s5_ldstdecrampy_ywr_rq, next_pavr_s4_s5_ldstincrampz_zwr_rq, next_pavr_s4_s5_ldstdecrampz_zwr_rq,
+ next_pavr_s4_s5_lpminc_zwr_rq, next_pavr_s4_s5_alu_bpr0wr_rq, next_pavr_s4_s6_daculd_bpr0wr_rq, next_pavr_s4_s5_alu_bpr1wr_rq,
+ next_pavr_s4_s5_iof_rq, next_pavr_s4_s6_iof_rq, next_pavr_s4_s5_iof_opcode, next_pavr_s4_s6_iof_opcode, next_pavr_s4_s5s6_iof_addr,
+ next_pavr_s4_s5s6_iof_bitaddr, next_pavr_s4_s5_alu_sregwr_rq, next_pavr_s4_s5_clriflag_sregwr_rq, next_pavr_s4_s5_setiflag_sregwr_rq,
+ next_pavr_s4_s5_inc_spwr_rq, next_pavr_s4_s5_dec_spwr_rq, next_pavr_s4_s5s51s52_calldec_spwr_rq, next_pavr_s4_s5s51_retinc_spwr_rq,
+ next_pavr_s4_s5_alu_opcode, next_pavr_s4_s5_alu_op1_hi8_sel, next_pavr_s4_s5_alu_op2_sel, pavr_s3_rfrd1_addr, pavr_s3_rfrd2_addr,
+ next_pavr_s4_s5_k8, next_pavr_s4_dacu_q, next_pavr_s4_s5_x_dacurd_rq, next_pavr_s4_s5_y_dacurd_rq, next_pavr_s4_s5_z_dacurd_rq,
+ next_pavr_s4_s5_sp_dacurd_rq, next_pavr_s4_s5_k16_dacurd_rq, next_pavr_s4_s5s51s52_pc_dacurd_rq, next_pavr_s4_s5_sp_dacuwr_rq,
+ next_pavr_s4_s5_x_dacuwr_rq, next_pavr_s4_s5_y_dacuwr_rq, next_pavr_s4_s5_z_dacuwr_rq, next_pavr_s4_s5s51s52_pc_dacuwr_rq,
+ next_pavr_s4_s5_lpm_pm_rq, next_pavr_s4_s5_elpm_pm_rq, next_pavr_s4_z_pm_rq, next_pavr_s4_zeind_pm_rq, next_pavr_s4_k22abs_pm_rq,
+ next_pavr_s4_k12rel_pm_rq, next_pavr_s4_k22int_pm_rq, next_pavr_s4_s54_ret_pm_rq, next_pavr_s4_k6, next_pavr_s4_k12,
+ next_pavr_s4_k22int, next_pavr_s4_s51s52s53_retpc_ld, next_pavr_s4_s5_stall_rq, next_pavr_s4_s6_stall_rq, next_pavr_s4_flush_s2_rq,
+ next_pavr_s4_ret_flush_s2_rq, next_pavr_s4_nop_rq, next_pavr_s4_s5_skip_cond_sel, next_pavr_s4_s6_skip_cond_sel,
+ next_pavr_s4_s5_skip_en, next_pavr_s4_s6_skip_en, next_pavr_s4_s5_skip_bitrf_sel, next_pavr_s4_s6_skip_bitiof_sel,
+ next_pavr_s4_s5_k7_branch_offset, next_pavr_s4_s5_branch_cond_sel, next_pavr_s4_s5_branch_en, next_pavr_s4_s5_branch_bitsreg_sel,
+ next_pavr_s4_instr32bits, next_pavr_s4_disable_int, pavr_stall_s4, pavr_rf_rd1_do, pavr_rf_rd2_do, pavr_s4_s6_aluoutlo8_rfwr_rq,
+ pavr_s4_s61_aluouthi8_rfwr_rq, pavr_s4_s6_iof_rfwr_rq, pavr_s4_s6_dacu_rfwr_rq, pavr_s4_s6_pm_rfwr_rq, pavr_s4_s5_ldstincrampx_xwr_rq,
+ pavr_s4_s5_ldstdecrampx_xwr_rq, pavr_s4_s5_ldstincrampy_ywr_rq, pavr_s4_s5_ldstdecrampy_ywr_rq, pavr_s4_s5_ldstincrampz_zwr_rq,
+ pavr_s4_s5_ldstdecrampz_zwr_rq, pavr_s4_s5_lpminc_zwr_rq, pavr_s4_s5_alu_bpr0wr_rq, pavr_s4_s6_daculd_bpr0wr_rq, pavr_s4_s5_alu_bpr1wr_rq,
+ pavr_s4_s5_iof_rq, pavr_s4_s6_iof_rq, pavr_s4_s5_alu_sregwr_rq, pavr_s4_s5_clriflag_sregwr_rq, pavr_s4_s5_setiflag_sregwr_rq,
+ pavr_s4_s5_inc_spwr_rq, pavr_s4_s5_dec_spwr_rq, pavr_s4_s5s51s52_calldec_spwr_rq, pavr_s4_s5s51_retinc_spwr_rq,
+ pavr_s4_s5_alu_op1_hi8_sel, pavr_s4_iof_dacu_q, pavr_s4_dm_dacu_q, pavr_s4_instr32bits, pavr_s4_s5_x_dacurd_rq,
+ pavr_s4_s5_y_dacurd_rq, pavr_s4_s5_z_dacurd_rq, pavr_s4_s5_sp_dacurd_rq, pavr_s4_s5_k16_dacurd_rq, pavr_s4_s5s51s52_pc_dacurd_rq,
+ pavr_s4_s5_sp_dacuwr_rq, pavr_s4_s5_x_dacuwr_rq, pavr_s4_s5_y_dacuwr_rq, pavr_s4_s5_z_dacuwr_rq, pavr_s4_s5s51s52_pc_dacuwr_rq,
+ pavr_s4_s5_lpm_pm_rq, pavr_s4_s5_elpm_pm_rq, pavr_s4_s54_ret_pm_rq, pavr_s4_s51s52s53_retpc_ld, pavr_s4_s5_stall_rq,
+ pavr_s4_s6_stall_rq, pavr_s4_ret_flush_s2_rq, pavr_s4_s5_skip_en, pavr_s4_s6_skip_en, pavr_s4_s5_branch_cond_sel,
+ pavr_s4_s5_branch_en, pavr_s4_disable_int, pavr_stall_s5, pavr_s5_s6_aluoutlo8_rfwr_rq, pavr_s5_s61_aluouthi8_rfwr_rq,
+ pavr_s5_s6_iof_rfwr_rq, pavr_s5_s6_dacu_rfwr_rq, pavr_s5_s6_pm_rfwr_rq, pavr_s5_s6_daculd_bpr0wr_rq, pavr_s5_s6_iof_rq,
+ pavr_s5_calldec_spwr_rq, pavr_s5_retinc2_spwr_rq, pavr_s5_alu_out, pavr_s5_pchi8_dacurd_rq, pavr_s5_pclo8_dacuwr_rq,
+ pavr_s5_s54_ret_pm_rq, pavr_s5_s51s52s53_retpc_ld, pavr_s5_s6_stall_rq, pavr_s5_ret_flush_s2_rq, next_pavr_s6_skip_rq,
+ next_pavr_s6_branch_rq, pavr_s5_s6_skip_en, pavr_s5_disable_int, pavr_stall_s6, next_pavr_s61_skip_rq, pavr_s51_ret_flush_s2_rq,
+ pavr_s51_pcmid8_dacuwr_rq, pavr_s51_calldec_spwr_rq, pavr_s51_disable_int, pavr_s51_retpchi8_ld, pavr_s51_pcmid8_dacurd_rq,
+ pavr_s51_s54_ret_pm_rq, pavr_s52_ret_flush_s2_rq, pavr_s52_retpcmid8_ld, pavr_s52_s54_ret_pm_rq, pavr_s53_ret_flush_s2_rq,
+ pavr_s53_s54_ret_pm_rq, pavr_s54_ret_flush_s2_rq, pavr_s4_nop_rq, pavr_nop_ack, pavr_s51_retpchi8_ld, pavr_dacu_do,
+ pavr_s52_retpcmid8_ld, pavr_s53_retpclo8_ld, next_pavr_s1_pc, next_pavr_bpr0, next_pavr_bpr0_addr, next_pavr_bpr0_active,
+ next_pavr_bpr1, next_pavr_bpr1_addr, next_pavr_bpr1_active, pavr_s5_dacudo_sel, next_pavr_s4_s5_k16_dacuwr_rq,
+ pavr_s4_s5_k16_dacuwr_rq, next_pavr_s2_pmdo_valid, pavr_s6_s61_aluouthi8_rfwr_rq, pavr_stall_bpu,
+ pavr_rf_do_shadow_active, pavr_rf_rd1_do_shadow, pavr_rf_rd2_do_shadow, next_pavr_s4_s6_iof_bpr0wr_rq,
+ pavr_s4_s6_iof_bpr0wr_rq, pavr_s5_s6_iof_bpr0wr_rq, pavr_dacu_do_shadow_active, pavr_dacu_do_shadow,
+ pavr_bpr13, pavr_bpr13_addr, pavr_bpr02_active, pavr_bpr03, pavr_bpr03_addr, pavr_bpr12_active,
+ pavr_bpr20, pavr_bpr20_addr, pavr_bpr21, pavr_bpr21_addr, pavr_bpr22, pavr_bpr22_addr, pavr_bpr23,
+ pavr_bpr23_addr, next_pavr_bpr2, next_pavr_bpr2_addr, next_pavr_bpr2_active, pavr_bpr20_active,
+ pavr_bpr21_active, pavr_bpr22_active, pavr_zbpu, pavr_s4_pcinc, next_pavr_s4_pcinc,
+ next_pavr_s4_s6_pmdo_bpr0wr_rq, pavr_s4_s6_pmdo_bpr0wr_rq, pavr_s5_s6_pmdo_bpr0wr_rq,
+ next_pavr_s4_s5_elpmincrampz_zwr_rq, next_pavr_s4_s5_dacux_bpr12wr_rq, next_pavr_s4_s5_dacuy_bpr12wr_rq,
+ next_pavr_s4_s5_dacuz_bpr12wr_rq, pavr_s4_s5_elpmincrampz_zwr_rq, pavr_s4_s5_dacux_bpr12wr_rq,
+ pavr_s4_s5_dacuy_bpr12wr_rq, pavr_s4_s5_dacuz_bpr12wr_rq, next_pavr_s4_stall_rq, next_pavr_s3_instr,
+ next_pavr_s3_pc, next_pavr_s2_pc)
+ begin
+ if pavr_res='1' then
+ -- Asynchronous reset
+
+ -- RF read port 1-related
+
+ pavr_s5_op1 <= int_to_std_logic_vector(0, pavr_s5_op1'length);
+
+ -- RF read port 2-related
+
+ pavr_s5_op2 <= int_to_std_logic_vector(0, pavr_s5_op2'length);
+
+ -- RF write port-related
+ pavr_s4_s6_aluoutlo8_rfwr_rq <= '0';
+ pavr_s5_s6_aluoutlo8_rfwr_rq <= '0';
+ pavr_s6_aluoutlo8_rfwr_rq <= '0';
+ pavr_s4_s61_aluouthi8_rfwr_rq <= '0';
+ pavr_s5_s61_aluouthi8_rfwr_rq <= '0';
+ pavr_s6_s61_aluouthi8_rfwr_rq <= '0';
+ pavr_s61_aluouthi8_rfwr_rq <= '0';
+ pavr_s4_s6_iof_rfwr_rq <= '0';
+ pavr_s5_s6_iof_rfwr_rq <= '0';
+ pavr_s6_iof_rfwr_rq <= '0';
+ pavr_s4_s6_dacu_rfwr_rq <= '0';
+ pavr_s5_s6_dacu_rfwr_rq <= '0';
+ pavr_s6_dacu_rfwr_rq <= '0';
+ pavr_s4_s6_pm_rfwr_rq <= '0';
+ pavr_s5_s6_pm_rfwr_rq <= '0';
+ pavr_s6_pm_rfwr_rq <= '0';
+
+ pavr_s4_s6_rfwr_addr1 <= int_to_std_logic_vector(0, pavr_s4_s6_rfwr_addr1'length);
+ pavr_s5_s6_rfwr_addr1 <= int_to_std_logic_vector(0, pavr_s5_s6_rfwr_addr1'length);
+ pavr_s6_rfwr_addr1 <= int_to_std_logic_vector(0, pavr_s6_rfwr_addr1'length);
+ pavr_s4_s61_rfwr_addr2 <= int_to_std_logic_vector(0, pavr_s4_s61_rfwr_addr2'length);
+ pavr_s5_s61_rfwr_addr2 <= int_to_std_logic_vector(0, pavr_s5_s61_rfwr_addr2'length);
+ pavr_s6_s61_rfwr_addr2 <= int_to_std_logic_vector(0, pavr_s6_s61_rfwr_addr2'length);
+ pavr_s61_rfwr_addr2 <= int_to_std_logic_vector(0, pavr_s61_rfwr_addr2'length);
+
+ -- Pointer registers-related
+ pavr_s4_s5_ldstincrampx_xwr_rq <= '0';
+ pavr_s5_ldstincrampx_xwr_rq <= '0';
+ pavr_s4_s5_ldstdecrampx_xwr_rq <= '0';
+ pavr_s5_ldstdecrampx_xwr_rq <= '0';
+
+ pavr_s4_s5_ldstincrampy_ywr_rq <= '0';
+ pavr_s5_ldstincrampy_ywr_rq <= '0';
+ pavr_s4_s5_ldstdecrampy_ywr_rq <= '0';
+ pavr_s5_ldstdecrampy_ywr_rq <= '0';
+
+ pavr_s4_s5_ldstincrampz_zwr_rq <= '0';
+ pavr_s5_ldstincrampz_zwr_rq <= '0';
+ pavr_s4_s5_ldstdecrampz_zwr_rq <= '0';
+ pavr_s5_ldstdecrampz_zwr_rq <= '0';
+ pavr_s4_s5_elpmincrampz_zwr_rq <= '0';
+ pavr_s5_elpmincrampz_zwr_rq <= '0';
+ pavr_s4_s5_lpminc_zwr_rq <= '0';
+ pavr_s5_lpminc_zwr_rq <= '0';
+
+ -- BPU write, BPR0-related
+ pavr_s4_s5_alu_bpr0wr_rq <= '0';
+ pavr_s5_alu_bpr0wr_rq <= '0';
+ pavr_s4_s6_iof_bpr0wr_rq <= '0';
+ pavr_s5_s6_iof_bpr0wr_rq <= '0';
+ pavr_s6_iof_bpr0wr_rq <= '0';
+ pavr_s4_s6_daculd_bpr0wr_rq <= '0';
+ pavr_s5_s6_daculd_bpr0wr_rq <= '0';
+ pavr_s6_daculd_bpr0wr_rq <= '0';
+ pavr_s4_s6_pmdo_bpr0wr_rq <= '0';
+ pavr_s5_s6_pmdo_bpr0wr_rq <= '0';
+ pavr_s6_pmdo_bpr0wr_rq <= '0';
+
+ pavr_bpr00 <= int_to_std_logic_vector(0, pavr_bpr00'length);
+ pavr_bpr00_addr <= int_to_std_logic_vector(0, pavr_bpr00_addr'length);
+ pavr_bpr00_active <= '0';
+ pavr_bpr01 <= int_to_std_logic_vector(0, pavr_bpr01'length);
+ pavr_bpr01_addr <= int_to_std_logic_vector(0, pavr_bpr01_addr'length);
+ pavr_bpr01_active <= '0';
+ pavr_bpr02 <= int_to_std_logic_vector(0, pavr_bpr02'length);
+ pavr_bpr02_addr <= int_to_std_logic_vector(0, pavr_bpr02_addr'length);
+ pavr_bpr02_active <= '0';
+ pavr_bpr03 <= int_to_std_logic_vector(0, pavr_bpr03'length);
+ pavr_bpr03_addr <= int_to_std_logic_vector(0, pavr_bpr03_addr'length);
+ pavr_bpr03_active <= '0';
+
+ -- BPU write, BPR1-related
+ pavr_s4_s5_dacux_bpr12wr_rq <= '0';
+ pavr_s5_dacux_bpr12wr_rq <= '0';
+ pavr_s4_s5_dacuy_bpr12wr_rq <= '0';
+ pavr_s5_dacuy_bpr12wr_rq <= '0';
+ pavr_s4_s5_dacuz_bpr12wr_rq <= '0';
+ pavr_s5_dacuz_bpr12wr_rq <= '0';
+ pavr_s4_s5_alu_bpr1wr_rq <= '0';
+ pavr_s5_alu_bpr1wr_rq <= '0';
+
+ pavr_bpr10 <= int_to_std_logic_vector(0, pavr_bpr10'length);
+ pavr_bpr10_addr <= int_to_std_logic_vector(0, pavr_bpr10_addr'length);
+ pavr_bpr10_active <= '0';
+ pavr_bpr11 <= int_to_std_logic_vector(0, pavr_bpr11'length);
+ pavr_bpr11_addr <= int_to_std_logic_vector(0, pavr_bpr11_addr'length);
+ pavr_bpr11_active <= '0';
+ pavr_bpr12 <= int_to_std_logic_vector(0, pavr_bpr12'length);
+ pavr_bpr12_addr <= int_to_std_logic_vector(0, pavr_bpr12_addr'length);
+ pavr_bpr12_active <= '0';
+ pavr_bpr13 <= int_to_std_logic_vector(0, pavr_bpr13'length);
+ pavr_bpr13_addr <= int_to_std_logic_vector(0, pavr_bpr13_addr'length);
+ pavr_bpr13_active <= '0';
+
+ -- BPU write, BPR2-related
+
+ pavr_bpr20 <= int_to_std_logic_vector(0, pavr_bpr20'length);
+ pavr_bpr20_addr <= int_to_std_logic_vector(0, pavr_bpr20_addr'length);
+ pavr_bpr20_active <= '0';
+ pavr_bpr21 <= int_to_std_logic_vector(0, pavr_bpr21'length);
+ pavr_bpr21_addr <= int_to_std_logic_vector(0, pavr_bpr21_addr'length);
+ pavr_bpr21_active <= '0';
+ pavr_bpr22 <= int_to_std_logic_vector(0, pavr_bpr22'length);
+ pavr_bpr22_addr <= int_to_std_logic_vector(0, pavr_bpr22_addr'length);
+ pavr_bpr22_active <= '0';
+ pavr_bpr23 <= int_to_std_logic_vector(0, pavr_bpr23'length);
+ pavr_bpr23_addr <= int_to_std_logic_vector(0, pavr_bpr23_addr'length);
+ pavr_bpr23_active <= '0';
+
+ -- IOF port-related
+ pavr_s4_s5_iof_rq <= '0';
+ pavr_s5_iof_rq <= '0';
+ pavr_s4_s6_iof_rq <= '0';
+ pavr_s5_s6_iof_rq <= '0';
+ pavr_s6_iof_rq <= '0';
+
+ pavr_s4_s5_iof_opcode <= int_to_std_logic_vector(0, pavr_s4_s5_iof_opcode'length);
+ pavr_s5_iof_opcode <= int_to_std_logic_vector(0, pavr_s5_iof_opcode'length);
+ pavr_s4_s6_iof_opcode <= int_to_std_logic_vector(0, pavr_s4_s6_iof_opcode'length);
+ pavr_s5_s6_iof_opcode <= int_to_std_logic_vector(0, pavr_s5_s6_iof_opcode'length);
+ pavr_s6_iof_opcode <= int_to_std_logic_vector(0, pavr_s6_iof_opcode'length);
+ pavr_s4_s5s6_iof_addr <= int_to_std_logic_vector(0, pavr_s4_s5s6_iof_addr'length);
+ pavr_s5_iof_addr <= int_to_std_logic_vector(0, pavr_s5_iof_addr'length);
+ pavr_s6_iof_addr <= int_to_std_logic_vector(0, pavr_s6_iof_addr'length);
+ pavr_s4_s5s6_iof_bitaddr <= int_to_std_logic_vector(0, pavr_s4_s5s6_iof_bitaddr'length);
+ pavr_s5_iof_bitaddr <= int_to_std_logic_vector(0, pavr_s5_iof_bitaddr'length);
+ pavr_s6_iof_bitaddr <= int_to_std_logic_vector(0, pavr_s6_iof_bitaddr'length);
+
+ -- SREG-related
+ pavr_s4_s5_alu_sregwr_rq <= '0';
+ pavr_s5_alu_sregwr_rq <= '0';
+ pavr_s4_s5_clriflag_sregwr_rq <= '0';
+ pavr_s5_clriflag_sregwr_rq <= '0';
+ pavr_s4_s5_setiflag_sregwr_rq <= '0';
+ pavr_s5_setiflag_sregwr_rq <= '0';
+
+ -- SP-related
+ pavr_s4_s5_inc_spwr_rq <= '0';
+ pavr_s5_inc_spwr_rq <= '0';
+ pavr_s4_s5_dec_spwr_rq <= '0';
+ pavr_s5_dec_spwr_rq <= '0';
+ pavr_s4_s5s51s52_calldec_spwr_rq <= '0';
+ pavr_s5_calldec_spwr_rq <= '0';
+ pavr_s51_calldec_spwr_rq <= '0';
+ pavr_s52_calldec_spwr_rq <= '0';
+ pavr_s4_s5s51_retinc_spwr_rq <= '0';
+ pavr_s5_retinc2_spwr_rq <= '0';
+ pavr_s51_retinc_spwr_rq <= '0';
+
+ -- ALU-related
+ pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(0, pavr_s4_s5_alu_opcode'length);
+ pavr_s5_alu_opcode <= int_to_std_logic_vector(0, pavr_s5_alu_opcode'length);
+ pavr_s4_s5_alu_op1_hi8_sel <= '0';
+ pavr_s5_alu_op1_hi8_sel <= '0';
+ pavr_s4_s5_alu_op2_sel <= int_to_std_logic_vector(0, pavr_s4_s5_alu_op2_sel'length);
+ pavr_s5_alu_op2_sel <= int_to_std_logic_vector(0, pavr_s5_alu_op2_sel'length);
+ pavr_s4_s5_op1_addr <= int_to_std_logic_vector(0, pavr_s4_s5_op1_addr'length);
+ pavr_s5_op1_addr <= int_to_std_logic_vector(0, pavr_s5_op1_addr'length);
+ pavr_s4_s5_op2_addr <= int_to_std_logic_vector(0, pavr_s4_s5_op2_addr'length);
+ pavr_s5_op2_addr <= int_to_std_logic_vector(0, pavr_s5_op2_addr'length);
+ pavr_s4_s5_k8 <= int_to_std_logic_vector(0, pavr_s4_s5_k8'length);
+ pavr_s5_k8 <= int_to_std_logic_vector(0, pavr_s5_k8'length);
+ pavr_s6_alu_out <= int_to_std_logic_vector(0, pavr_s6_alu_out'length);
+ pavr_s61_alu_out_hi8 <= int_to_std_logic_vector(0, pavr_s61_alu_out_hi8'length);
+
+ -- DACU setup-related
+ pavr_s4_dacu_q <= int_to_std_logic_vector(0, pavr_s4_dacu_q'length);
+ pavr_s5_rf_dacu_q <= int_to_std_logic_vector(0, pavr_s5_rf_dacu_q'length);
+ pavr_s5_iof_dacu_q <= int_to_std_logic_vector(0, pavr_s5_iof_dacu_q'length);
+ pavr_s5_dm_dacu_q <= int_to_std_logic_vector(0, pavr_s5_dm_dacu_q'length);
+ pavr_s6_dacudo_sel <= int_to_std_logic_vector(0, pavr_s6_dacudo_sel'length);
+ pavr_s5_k16 <= int_to_std_logic_vector(0, pavr_s5_k16'length);
+
+ -- DACU read-related
+ pavr_s4_s5_x_dacurd_rq <= '0';
+ pavr_s5_x_dacurd_rq <= '0';
+ pavr_s4_s5_y_dacurd_rq <= '0';
+ pavr_s5_y_dacurd_rq <= '0';
+ pavr_s4_s5_z_dacurd_rq <= '0';
+ pavr_s5_z_dacurd_rq <= '0';
+ pavr_s4_s5_sp_dacurd_rq <= '0';
+ pavr_s5_sp_dacurd_rq <= '0';
+ pavr_s4_s5_k16_dacurd_rq <= '0';
+ pavr_s5_k16_dacurd_rq <= '0';
+ pavr_s4_s5s51s52_pc_dacurd_rq <= '0';
+ pavr_s5_pchi8_dacurd_rq <= '0';
+ pavr_s51_pcmid8_dacurd_rq <= '0';
+ pavr_s52_pclo8_dacurd_rq <= '0';
+
+ -- DACU write-related
+ pavr_s4_s5_sp_dacuwr_rq <= '0';
+ pavr_s5_sp_dacuwr_rq <= '0';
+ pavr_s4_s5_k16_dacuwr_rq <= '0';
+ pavr_s5_k16_dacuwr_rq <= '0';
+ pavr_s4_s5_x_dacuwr_rq <= '0';
+ pavr_s5_x_dacuwr_rq <= '0';
+ pavr_s4_s5_y_dacuwr_rq <= '0';
+ pavr_s5_y_dacuwr_rq <= '0';
+ pavr_s4_s5_z_dacuwr_rq <= '0';
+ pavr_s5_z_dacuwr_rq <= '0';
+ pavr_s4_s5s51s52_pc_dacuwr_rq <= '0';
+ pavr_s5_pclo8_dacuwr_rq <= '0';
+ pavr_s51_pcmid8_dacuwr_rq <= '0';
+ pavr_s52_pchi8_dacuwr_rq <= '0';
+
+ -- DM-related
+
+ -- PM access-related
+ pavr_s4_s5_lpm_pm_rq <= '0';
+ pavr_s5_lpm_pm_rq <= '0';
+ pavr_s4_s5_elpm_pm_rq <= '0';
+ pavr_s5_elpm_pm_rq <= '0';
+ pavr_s4_z_pm_rq <= '0';
+ pavr_s4_zeind_pm_rq <= '0';
+ pavr_s4_k22abs_pm_rq <= '0';
+ pavr_s4_k12rel_pm_rq <= '0';
+ pavr_s4_k22int_pm_rq <= '0';
+ pavr_s4_s54_ret_pm_rq <= '0';
+ pavr_s5_s54_ret_pm_rq <= '0';
+ pavr_s51_s54_ret_pm_rq <= '0';
+ pavr_s52_s54_ret_pm_rq <= '0';
+ pavr_s53_s54_ret_pm_rq <= '0';
+ pavr_s54_ret_pm_rq <= '0';
+
+ pavr_s4_k6 <= int_to_std_logic_vector(0, pavr_s4_k6'length);
+ pavr_s4_k12 <= int_to_std_logic_vector(0, pavr_s4_k12'length);
+ pavr_s4_k22int <= int_to_std_logic_vector(0, pavr_s4_k22int'length);
+ pavr_s2_pc <= int_to_std_logic_vector(0, pavr_s2_pc'length);
+ pavr_s3_pc <= int_to_std_logic_vector(0, pavr_s3_pc'length);
+ pavr_s4_pc <= int_to_std_logic_vector(0, pavr_s4_pc'length);
+ pavr_s5_pc <= int_to_std_logic_vector(0, pavr_s5_pc'length);
+ pavr_s51_pc <= int_to_std_logic_vector(0, pavr_s51_pc'length);
+ pavr_s52_pc <= int_to_std_logic_vector(0, pavr_s52_pc'length);
+ pavr_s4_pcinc <= '0';
+ pavr_s4_s51s52s53_retpc_ld <= '0';
+ pavr_s5_s51s52s53_retpc_ld <= '0';
+ pavr_s51_retpchi8_ld <= '0';
+ pavr_s52_retpcmid8_ld <= '0';
+ pavr_s53_retpclo8_ld <= '0';
+ pavr_s52_retpchi8 <= int_to_std_logic_vector(0, pavr_s52_retpchi8'length);
+ pavr_s53_retpcmid8 <= int_to_std_logic_vector(0, pavr_s53_retpcmid8'length);
+ pavr_s54_retpclo8 <= int_to_std_logic_vector(0, pavr_s54_retpclo8'length);
+ pavr_s1_pc <= int_to_std_logic_vector(0, pavr_s1_pc'length); -- Note 1
+ pavr_s2_pmdo_valid <= '0';
+
+ pavr_s6_zlsb <= '0';
+
+ -- SFU requests-related
+ pavr_s4_stall_rq <= '0';
+ pavr_s4_s5_stall_rq <= '0';
+ pavr_s5_stall_rq <= '0';
+ pavr_s4_s6_stall_rq <= '0';
+ pavr_s5_s6_stall_rq <= '0';
+ pavr_s6_stall_rq <= '0';
+ pavr_s4_flush_s2_rq <= '0';
+ pavr_s4_ret_flush_s2_rq <= '0';
+ pavr_s5_ret_flush_s2_rq <= '0';
+ pavr_s51_ret_flush_s2_rq <= '0';
+ pavr_s52_ret_flush_s2_rq <= '0';
+ pavr_s53_ret_flush_s2_rq <= '0';
+ pavr_s54_ret_flush_s2_rq <= '0';
+ pavr_s55_ret_flush_s2_rq <= '0';
+ pavr_s6_skip_rq <= '0';
+ pavr_s61_skip_rq <= '0';
+ pavr_s6_branch_rq <= '0';
+ pavr_s4_nop_rq <= '0';
+
+ pavr_s4_s5_skip_cond_sel <= int_to_std_logic_vector(0, pavr_s4_s5_skip_cond_sel'length);
+ pavr_s5_skip_cond_sel <= int_to_std_logic_vector(0, pavr_s5_skip_cond_sel'length);
+ pavr_s4_s6_skip_cond_sel <= '0';
+ pavr_s5_s6_skip_cond_sel <= '0';
+ pavr_s6_skip_cond_sel <= '0';
+ pavr_s4_s5_skip_en <= '0';
+ pavr_s5_skip_en <= '0';
+ pavr_s4_s6_skip_en <= '0';
+ pavr_s5_s6_skip_en <= '0';
+ pavr_s6_skip_en <= '0';
+ pavr_s4_s5_skip_bitrf_sel <= int_to_std_logic_vector(0, pavr_s4_s5_skip_bitrf_sel'length);
+ pavr_s5_skip_bitrf_sel <= int_to_std_logic_vector(0, pavr_s5_skip_bitrf_sel'length);
+ pavr_s4_s6_skip_bitiof_sel <= int_to_std_logic_vector(0, pavr_s4_s6_skip_bitiof_sel'length);
+ pavr_s5_s6_skip_bitiof_sel <= int_to_std_logic_vector(0, pavr_s5_s6_skip_bitiof_sel'length);
+ pavr_s6_skip_bitiof_sel <= int_to_std_logic_vector(0, pavr_s6_skip_bitiof_sel'length);
+
+ pavr_s4_s5_k7_branch_offset <= int_to_std_logic_vector(0, pavr_s4_s5_k7_branch_offset'length);
+ pavr_s5_k7_branch_offset <= int_to_std_logic_vector(0, pavr_s5_k7_branch_offset'length);
+ pavr_s6_branch_pc <= int_to_std_logic_vector(0, pavr_s6_branch_pc'length);
+ pavr_s4_s5_branch_cond_sel <= '0';
+ pavr_s5_branch_cond_sel <= '0';
+ pavr_s4_s5_branch_en <= '0';
+ pavr_s5_branch_en <= '0';
+ pavr_s4_s5_branch_bitsreg_sel <= int_to_std_logic_vector(0, pavr_s4_s5_branch_bitsreg_sel'length);
+ pavr_s5_branch_bitsreg_sel <= int_to_std_logic_vector(0, pavr_s5_branch_bitsreg_sel'length);
+
+ -- Others
+ pavr_nop_ack <= '0';
+ pavr_s3_instr <= int_to_std_logic_vector(0, pavr_s3_instr'length);
+ pavr_s4_instr32bits <= '0';
+ pavr_s4_disable_int <= '0';
+ pavr_s5_disable_int <= '0';
+ pavr_s51_disable_int <= '0';
+ pavr_s52_disable_int <= '0';
+
+ elsif pavr_clk'event and pavr_clk='1' then
+ -- Load registers ----------------------------------------------------
+
+ -- Stage s1 ----------------------------------------------------------
+ pavr_s2_pmdo_valid <= next_pavr_s2_pmdo_valid;
+ pavr_s2_pc <= next_pavr_s2_pc;
+
+ -- Stage s2 ----------------------------------------------------------
+ pavr_s3_instr <= next_pavr_s3_instr;
+ pavr_s3_pc <= next_pavr_s3_pc;
+
+ -- Stage s3 ----------------------------------------------------------
+ if pavr_flush_s3='1' then
+ -- RF read port 1-related
+
+ -- RF read port 2-related
+
+ -- RF write port-related
+ pavr_s4_s6_aluoutlo8_rfwr_rq <= '0';
+ pavr_s4_s61_aluouthi8_rfwr_rq <= '0';
+ pavr_s4_s6_iof_rfwr_rq <= '0';
+ pavr_s4_s6_dacu_rfwr_rq <= '0';
+ pavr_s4_s6_pm_rfwr_rq <= '0';
+
+ pavr_s4_s6_rfwr_addr1 <= int_to_std_logic_vector(0, pavr_s4_s6_rfwr_addr1'length);
+ pavr_s4_s61_rfwr_addr2 <= int_to_std_logic_vector(0, pavr_s4_s61_rfwr_addr2'length);
+
+ -- Pointer registers-related
+ pavr_s4_s5_ldstincrampx_xwr_rq <= '0';
+ pavr_s4_s5_ldstdecrampx_xwr_rq <= '0';
+
+ pavr_s4_s5_ldstincrampy_ywr_rq <= '0';
+ pavr_s4_s5_ldstdecrampy_ywr_rq <= '0';
+
+ pavr_s4_s5_ldstincrampz_zwr_rq <= '0';
+ pavr_s4_s5_ldstdecrampz_zwr_rq <= '0';
+ pavr_s4_s5_elpmincrampz_zwr_rq <= '0';
+ pavr_s4_s5_lpminc_zwr_rq <= '0';
+
+ -- BPU write, BPR0-related
+ pavr_s4_s5_alu_bpr0wr_rq <= '0';
+ pavr_s4_s6_iof_bpr0wr_rq <= '0';
+ pavr_s4_s6_daculd_bpr0wr_rq <= '0';
+ pavr_s4_s6_pmdo_bpr0wr_rq <= '0';
+
+ -- BPU write, BPR1-related
+ pavr_s4_s5_dacux_bpr12wr_rq <= '0';
+ pavr_s4_s5_dacuy_bpr12wr_rq <= '0';
+ pavr_s4_s5_dacuz_bpr12wr_rq <= '0';
+ pavr_s4_s5_alu_bpr1wr_rq <= '0';
+
+ -- IOF port-related
+ pavr_s4_s5_iof_rq <= '0';
+ pavr_s4_s6_iof_rq <= '0';
+
+ pavr_s4_s5_iof_opcode <= int_to_std_logic_vector(0, pavr_s4_s5_iof_opcode'length);
+ pavr_s4_s6_iof_opcode <= int_to_std_logic_vector(0, pavr_s4_s6_iof_opcode'length);
+ pavr_s4_s5s6_iof_addr <= int_to_std_logic_vector(0, pavr_s4_s5s6_iof_addr'length);
+ pavr_s4_s5s6_iof_bitaddr <= int_to_std_logic_vector(0, pavr_s4_s5s6_iof_bitaddr'length);
+
+ -- SREG-related
+ pavr_s4_s5_alu_sregwr_rq <= '0';
+ pavr_s4_s5_clriflag_sregwr_rq <= '0';
+ pavr_s4_s5_setiflag_sregwr_rq <= '0';
+
+ -- SP-related
+ pavr_s4_s5_inc_spwr_rq <= '0';
+ pavr_s4_s5_dec_spwr_rq <= '0';
+ pavr_s4_s5s51s52_calldec_spwr_rq <= '0';
+ pavr_s4_s5s51_retinc_spwr_rq <= '0';
+
+ -- ALU-related
+ pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(0, pavr_s4_s5_alu_opcode'length);
+ pavr_s4_s5_alu_op1_hi8_sel <= '0';
+ pavr_s4_s5_alu_op2_sel <= int_to_std_logic_vector(0, pavr_s4_s5_alu_op2_sel'length);
+ pavr_s4_s5_op1_addr <= int_to_std_logic_vector(0, pavr_s4_s5_op1_addr'length);
+ pavr_s4_s5_op2_addr <= int_to_std_logic_vector(0, pavr_s4_s5_op2_addr'length);
+ pavr_s4_s5_k8 <= int_to_std_logic_vector(0, pavr_s4_s5_k8'length);
+
+ -- DACU setup-related
+ pavr_s4_dacu_q <= int_to_std_logic_vector(0, pavr_s4_dacu_q'length);
+
+ -- DACU read-related
+ pavr_s4_s5_x_dacurd_rq <= '0';
+ pavr_s4_s5_y_dacurd_rq <= '0';
+ pavr_s4_s5_z_dacurd_rq <= '0';
+ pavr_s4_s5_sp_dacurd_rq <= '0';
+ pavr_s4_s5_k16_dacurd_rq <= '0';
+ pavr_s4_s5s51s52_pc_dacurd_rq <= '0';
+
+ -- DACU write-related
+ pavr_s4_s5_sp_dacuwr_rq <= '0';
+ pavr_s4_s5_k16_dacuwr_rq <= '0';
+ pavr_s4_s5_x_dacuwr_rq <= '0';
+ pavr_s4_s5_y_dacuwr_rq <= '0';
+ pavr_s4_s5_z_dacuwr_rq <= '0';
+ pavr_s4_s5s51s52_pc_dacuwr_rq <= '0';
+
+ -- DM-related
+
+ -- PM access-related
+ pavr_s4_s5_lpm_pm_rq <= '0';
+ pavr_s4_s5_elpm_pm_rq <= '0';
+ pavr_s4_z_pm_rq <= '0';
+ pavr_s4_zeind_pm_rq <= '0';
+ pavr_s4_k22abs_pm_rq <= '0';
+ pavr_s4_k12rel_pm_rq <= '0';
+ pavr_s4_k22int_pm_rq <= '0';
+ pavr_s4_s54_ret_pm_rq <= '0';
+
+ pavr_s4_k6 <= int_to_std_logic_vector(0, pavr_s4_k6'length);
+ pavr_s4_k12 <= int_to_std_logic_vector(0, pavr_s4_k12'length);
+ pavr_s4_k22int <= int_to_std_logic_vector(0, pavr_s4_k22int'length);
+ --pavr_s4_pc <= int_to_std_logic_vector(0, pavr_s4_pc'length); -- *** Comment this. The flush lines shouldn't interfere with PC temporary storage. Otherwise, 32 bit intructions are messed up.
+ pavr_s4_pcinc <= '0';
+ pavr_s4_s51s52s53_retpc_ld <= '0';
+
+ -- SFU requests-related
+ pavr_s4_stall_rq <= '0';
+ pavr_s4_s5_stall_rq <= '0';
+ pavr_s4_s6_stall_rq <= '0';
+ pavr_s4_flush_s2_rq <= '0';
+ pavr_s4_ret_flush_s2_rq <= '0';
+ pavr_s4_nop_rq <= '0';
+
+ pavr_s4_s5_skip_cond_sel <= int_to_std_logic_vector(0, pavr_s4_s5_skip_cond_sel'length);
+ pavr_s4_s6_skip_cond_sel <= '0';
+ pavr_s4_s5_skip_en <= '0';
+ pavr_s4_s6_skip_en <= '0';
+ pavr_s4_s5_skip_bitrf_sel <= int_to_std_logic_vector(0, pavr_s4_s5_skip_bitrf_sel'length);
+ pavr_s4_s6_skip_bitiof_sel <= int_to_std_logic_vector(0, pavr_s4_s6_skip_bitiof_sel'length);
+
+ pavr_s4_s5_k7_branch_offset <= int_to_std_logic_vector(0, pavr_s4_s5_k7_branch_offset'length);
+ pavr_s4_s5_branch_cond_sel <= '0';
+ pavr_s4_s5_branch_en <= '0';
+ pavr_s4_s5_branch_bitsreg_sel <= int_to_std_logic_vector(0, pavr_s4_s5_branch_bitsreg_sel'length);
+
+ -- Others
+ pavr_s4_instr32bits <= '0';
+ pavr_s4_disable_int <= '0';
+ elsif pavr_stall_s3='0' then
+ -- RF read port 1-related
+
+ -- RF read port 2-related
+
+ -- RF write port-related
+ pavr_s4_s6_aluoutlo8_rfwr_rq <= next_pavr_s4_s6_aluoutlo8_rfwr_rq;
+ pavr_s4_s61_aluouthi8_rfwr_rq <= next_pavr_s4_s61_aluouthi8_rfwr_rq;
+ pavr_s4_s6_iof_rfwr_rq <= next_pavr_s4_s6_iof_rfwr_rq;
+ pavr_s4_s6_dacu_rfwr_rq <= next_pavr_s4_s6_dacu_rfwr_rq;
+ pavr_s4_s6_pm_rfwr_rq <= next_pavr_s4_s6_pm_rfwr_rq;
+
+ pavr_s4_s6_rfwr_addr1 <= next_pavr_s4_s6_rfwr_addr1;
+ pavr_s4_s61_rfwr_addr2 <= next_pavr_s4_s61_rfwr_addr2;
+
+ -- Pointer registers-related
+ pavr_s4_s5_ldstincrampx_xwr_rq <= next_pavr_s4_s5_ldstincrampx_xwr_rq;
+ pavr_s4_s5_ldstdecrampx_xwr_rq <= next_pavr_s4_s5_ldstdecrampx_xwr_rq;
+
+ pavr_s4_s5_ldstincrampy_ywr_rq <= next_pavr_s4_s5_ldstincrampy_ywr_rq;
+ pavr_s4_s5_ldstdecrampy_ywr_rq <= next_pavr_s4_s5_ldstdecrampy_ywr_rq;
+
+ pavr_s4_s5_ldstincrampz_zwr_rq <= next_pavr_s4_s5_ldstincrampz_zwr_rq;
+ pavr_s4_s5_ldstdecrampz_zwr_rq <= next_pavr_s4_s5_ldstdecrampz_zwr_rq;
+ pavr_s4_s5_elpmincrampz_zwr_rq <= next_pavr_s4_s5_elpmincrampz_zwr_rq;
+ pavr_s4_s5_lpminc_zwr_rq <= next_pavr_s4_s5_lpminc_zwr_rq;
+
+ -- BPU write, BPR0-related
+ pavr_s4_s5_alu_bpr0wr_rq <= next_pavr_s4_s5_alu_bpr0wr_rq;
+ pavr_s4_s6_iof_bpr0wr_rq <= next_pavr_s4_s6_iof_bpr0wr_rq;
+ pavr_s4_s6_daculd_bpr0wr_rq <= next_pavr_s4_s6_daculd_bpr0wr_rq;
+ pavr_s4_s6_pmdo_bpr0wr_rq <= next_pavr_s4_s6_pmdo_bpr0wr_rq;
+
+ -- BPU write, BPR1-related
+ pavr_s4_s5_dacux_bpr12wr_rq <= next_pavr_s4_s5_dacux_bpr12wr_rq;
+ pavr_s4_s5_dacuy_bpr12wr_rq <= next_pavr_s4_s5_dacuy_bpr12wr_rq;
+ pavr_s4_s5_dacuz_bpr12wr_rq <= next_pavr_s4_s5_dacuz_bpr12wr_rq;
+ pavr_s4_s5_alu_bpr1wr_rq <= next_pavr_s4_s5_alu_bpr1wr_rq;
+
+ -- IOF port-related
+ pavr_s4_s5_iof_rq <= next_pavr_s4_s5_iof_rq;
+ pavr_s4_s6_iof_rq <= next_pavr_s4_s6_iof_rq;
+
+ pavr_s4_s5_iof_opcode <= next_pavr_s4_s5_iof_opcode;
+ pavr_s4_s6_iof_opcode <= next_pavr_s4_s6_iof_opcode;
+ pavr_s4_s5s6_iof_addr <= next_pavr_s4_s5s6_iof_addr;
+ pavr_s4_s5s6_iof_bitaddr <= next_pavr_s4_s5s6_iof_bitaddr;
+
+ -- SREG-related
+ pavr_s4_s5_alu_sregwr_rq <= next_pavr_s4_s5_alu_sregwr_rq;
+ pavr_s4_s5_clriflag_sregwr_rq <= next_pavr_s4_s5_clriflag_sregwr_rq;
+ pavr_s4_s5_setiflag_sregwr_rq <= next_pavr_s4_s5_setiflag_sregwr_rq;
+
+ -- SP-related
+ pavr_s4_s5_inc_spwr_rq <= next_pavr_s4_s5_inc_spwr_rq;
+ pavr_s4_s5_dec_spwr_rq <= next_pavr_s4_s5_dec_spwr_rq;
+ pavr_s4_s5s51s52_calldec_spwr_rq <= next_pavr_s4_s5s51s52_calldec_spwr_rq;
+ pavr_s4_s5s51_retinc_spwr_rq <= next_pavr_s4_s5s51_retinc_spwr_rq;
+
+ -- ALU-related
+ pavr_s4_s5_alu_opcode <= next_pavr_s4_s5_alu_opcode;
+ pavr_s4_s5_alu_op1_hi8_sel <= next_pavr_s4_s5_alu_op1_hi8_sel;
+ pavr_s4_s5_alu_op2_sel <= next_pavr_s4_s5_alu_op2_sel;
+ pavr_s4_s5_op1_addr <= pavr_s3_rfrd1_addr; -- *** Attention here; unusual notation.
+ pavr_s4_s5_op2_addr <= pavr_s3_rfrd2_addr; --
+ pavr_s4_s5_k8 <= next_pavr_s4_s5_k8;
+
+ -- DACU setup-related
+ pavr_s4_dacu_q <= next_pavr_s4_dacu_q;
+
+ -- DACU read-related
+ pavr_s4_s5_x_dacurd_rq <= next_pavr_s4_s5_x_dacurd_rq;
+ pavr_s4_s5_y_dacurd_rq <= next_pavr_s4_s5_y_dacurd_rq;
+ pavr_s4_s5_z_dacurd_rq <= next_pavr_s4_s5_z_dacurd_rq;
+ pavr_s4_s5_sp_dacurd_rq <= next_pavr_s4_s5_sp_dacurd_rq;
+ pavr_s4_s5_k16_dacurd_rq <= next_pavr_s4_s5_k16_dacurd_rq;
+ pavr_s4_s5s51s52_pc_dacurd_rq <= next_pavr_s4_s5s51s52_pc_dacurd_rq;
+
+ -- DACU write-related
+ pavr_s4_s5_sp_dacuwr_rq <= next_pavr_s4_s5_sp_dacuwr_rq;
+ pavr_s4_s5_k16_dacuwr_rq <= next_pavr_s4_s5_k16_dacuwr_rq;
+ pavr_s4_s5_x_dacuwr_rq <= next_pavr_s4_s5_x_dacuwr_rq;
+ pavr_s4_s5_y_dacuwr_rq <= next_pavr_s4_s5_y_dacuwr_rq;
+ pavr_s4_s5_z_dacuwr_rq <= next_pavr_s4_s5_z_dacuwr_rq;
+ pavr_s4_s5s51s52_pc_dacuwr_rq <= next_pavr_s4_s5s51s52_pc_dacuwr_rq;
+
+ -- DM-related
+
+ -- PM access-related
+ pavr_s4_s5_lpm_pm_rq <= next_pavr_s4_s5_lpm_pm_rq;
+ pavr_s4_s5_elpm_pm_rq <= next_pavr_s4_s5_elpm_pm_rq;
+ pavr_s4_z_pm_rq <= next_pavr_s4_z_pm_rq;
+ pavr_s4_zeind_pm_rq <= next_pavr_s4_zeind_pm_rq;
+ pavr_s4_k22abs_pm_rq <= next_pavr_s4_k22abs_pm_rq;
+ pavr_s4_k12rel_pm_rq <= next_pavr_s4_k12rel_pm_rq;
+ pavr_s4_k22int_pm_rq <= next_pavr_s4_k22int_pm_rq;
+ pavr_s4_s54_ret_pm_rq <= next_pavr_s4_s54_ret_pm_rq;
+
+ pavr_s4_k6 <= next_pavr_s4_k6;
+ pavr_s4_k12 <= next_pavr_s4_k12;
+ pavr_s4_k22int <= next_pavr_s4_k22int;
+ pavr_s4_pc <= pavr_s3_pc;
+ pavr_s4_pcinc <= next_pavr_s4_pcinc;
+ pavr_s4_s51s52s53_retpc_ld <= next_pavr_s4_s51s52s53_retpc_ld;
+
+ -- SFU requests-related
+ pavr_s4_stall_rq <= next_pavr_s4_stall_rq;
+ pavr_s4_s5_stall_rq <= next_pavr_s4_s5_stall_rq;
+ pavr_s4_s6_stall_rq <= next_pavr_s4_s6_stall_rq;
+ pavr_s4_flush_s2_rq <= next_pavr_s4_flush_s2_rq;
+ pavr_s4_ret_flush_s2_rq <= next_pavr_s4_ret_flush_s2_rq;
+ pavr_s4_nop_rq <= next_pavr_s4_nop_rq;
+
+ pavr_s4_s5_skip_cond_sel <= next_pavr_s4_s5_skip_cond_sel;
+ pavr_s4_s6_skip_cond_sel <= next_pavr_s4_s6_skip_cond_sel;
+ pavr_s4_s5_skip_en <= next_pavr_s4_s5_skip_en;
+ pavr_s4_s6_skip_en <= next_pavr_s4_s6_skip_en;
+ pavr_s4_s5_skip_bitrf_sel <= next_pavr_s4_s5_skip_bitrf_sel;
+ pavr_s4_s6_skip_bitiof_sel <= next_pavr_s4_s6_skip_bitiof_sel;
+ pavr_s4_s5_k7_branch_offset <= next_pavr_s4_s5_k7_branch_offset;
+ pavr_s4_s5_branch_cond_sel <= next_pavr_s4_s5_branch_cond_sel;
+ pavr_s4_s5_branch_en <= next_pavr_s4_s5_branch_en;
+ pavr_s4_s5_branch_bitsreg_sel <= next_pavr_s4_s5_branch_bitsreg_sel;
+
+ -- Others
+ pavr_s4_instr32bits <= next_pavr_s4_instr32bits;
+ pavr_s4_disable_int <= next_pavr_s4_disable_int;
+ end if;
+
+ -- Stage s4 ----------------------------------------------------------
+ if pavr_flush_s4='1' then
+ -- RF read port 1-related
+
+ pavr_s5_op1 <= int_to_std_logic_vector(0, pavr_s5_op1'length);
+
+ -- RF read port 2-related
+
+ pavr_s5_op2 <= int_to_std_logic_vector(0, pavr_s5_op2'length);
+
+ -- RF write port-related
+ pavr_s5_s6_aluoutlo8_rfwr_rq <= '0';
+ pavr_s5_s61_aluouthi8_rfwr_rq <= '0';
+ pavr_s5_s6_iof_rfwr_rq <= '0';
+ pavr_s5_s6_dacu_rfwr_rq <= '0';
+ pavr_s5_s6_pm_rfwr_rq <= '0';
+
+ pavr_s5_s6_rfwr_addr1 <= int_to_std_logic_vector(0, pavr_s5_s6_rfwr_addr1'length);
+ pavr_s5_s61_rfwr_addr2 <= int_to_std_logic_vector(0, pavr_s5_s61_rfwr_addr2'length);
+
+ -- Pointer registers-related
+ pavr_s5_ldstincrampx_xwr_rq <= '0';
+ pavr_s5_ldstdecrampx_xwr_rq <= '0';
+
+ pavr_s5_ldstincrampy_ywr_rq <= '0';
+ pavr_s5_ldstdecrampy_ywr_rq <= '0';
+
+ pavr_s5_ldstincrampz_zwr_rq <= '0';
+ pavr_s5_ldstdecrampz_zwr_rq <= '0';
+ pavr_s5_elpmincrampz_zwr_rq <= '0';
+ pavr_s5_lpminc_zwr_rq <= '0';
+
+ -- BPU write, BPR0-related
+ pavr_s5_alu_bpr0wr_rq <= '0';
+ pavr_s5_s6_iof_bpr0wr_rq <= '0';
+ pavr_s5_s6_daculd_bpr0wr_rq <= '0';
+ pavr_s5_s6_pmdo_bpr0wr_rq <= '0';
+
+ -- BPU write, BPR1-related
+ pavr_s5_dacux_bpr12wr_rq <= '0';
+ pavr_s5_dacuy_bpr12wr_rq <= '0';
+ pavr_s5_dacuz_bpr12wr_rq <= '0';
+ pavr_s5_alu_bpr1wr_rq <= '0';
+
+ -- IOF port-related
+ pavr_s5_iof_rq <= '0';
+ pavr_s5_s6_iof_rq <= '0';
+
+ pavr_s5_iof_opcode <= int_to_std_logic_vector(0, pavr_s5_iof_opcode'length);
+ pavr_s5_s6_iof_opcode <= int_to_std_logic_vector(0, pavr_s5_s6_iof_opcode'length);
+ pavr_s5_iof_addr <= int_to_std_logic_vector(0, pavr_s5_iof_addr'length);
+ pavr_s5_iof_bitaddr <= int_to_std_logic_vector(0, pavr_s5_iof_bitaddr'length);
+
+ -- SREG-related
+ pavr_s5_alu_sregwr_rq <= '0';
+ pavr_s5_clriflag_sregwr_rq <= '0';
+ pavr_s5_setiflag_sregwr_rq <= '0';
+
+ -- SP-related
+ pavr_s5_inc_spwr_rq <= '0';
+ pavr_s5_dec_spwr_rq <= '0';
+ pavr_s5_calldec_spwr_rq <= '0';
+ pavr_s5_retinc2_spwr_rq <= '0';
+
+ -- ALU-related
+ pavr_s5_alu_opcode <= int_to_std_logic_vector(0, pavr_s5_alu_opcode'length);
+ pavr_s5_alu_op1_hi8_sel <= '0';
+ pavr_s5_alu_op2_sel <= int_to_std_logic_vector(0, pavr_s5_alu_op2_sel'length);
+ pavr_s5_op1_addr <= int_to_std_logic_vector(0, pavr_s5_op1_addr'length);
+ pavr_s5_op2_addr <= int_to_std_logic_vector(0, pavr_s5_op2_addr'length);
+ pavr_s5_k8 <= int_to_std_logic_vector(0, pavr_s5_k8'length);
+
+ -- DACU setup-related
+ pavr_s5_rf_dacu_q <= int_to_std_logic_vector(0, pavr_s5_rf_dacu_q'length);
+ pavr_s5_iof_dacu_q <= int_to_std_logic_vector(0, pavr_s5_iof_dacu_q'length);
+ pavr_s5_dm_dacu_q <= int_to_std_logic_vector(0, pavr_s5_dm_dacu_q'length);
+ pavr_s5_k16 <= int_to_std_logic_vector(0, pavr_s5_k16'length);
+
+ -- DACU read-related
+ pavr_s5_x_dacurd_rq <= '0';
+ pavr_s5_y_dacurd_rq <= '0';
+ pavr_s5_z_dacurd_rq <= '0';
+ pavr_s5_sp_dacurd_rq <= '0';
+ pavr_s5_k16_dacurd_rq <= '0';
+ pavr_s5_pchi8_dacurd_rq <= '0';
+
+ -- DACU write-related
+ pavr_s5_sp_dacuwr_rq <= '0';
+ pavr_s5_k16_dacuwr_rq <= '0';
+ pavr_s5_x_dacuwr_rq <= '0';
+ pavr_s5_y_dacuwr_rq <= '0';
+ pavr_s5_z_dacuwr_rq <= '0';
+ pavr_s5_pclo8_dacuwr_rq <= '0';
+
+ -- DM-related
+
+ -- PM access-related
+ pavr_s5_lpm_pm_rq <= '0';
+ pavr_s5_elpm_pm_rq <= '0';
+ pavr_s5_s54_ret_pm_rq <= '0';
+
+ --pavr_s5_pc <= int_to_std_logic_vector(0, pavr_s5_pc'length); -- *** Comment this. The flush lines shouldn't interfere with PC temporary storage. Otherwise, 32 bit intructions are messed up.
+ pavr_s5_s51s52s53_retpc_ld <= '0';
+
+ -- SFU requests-related
+ pavr_s5_stall_rq <= '0';
+ pavr_s5_s6_stall_rq <= '0';
+ pavr_s5_ret_flush_s2_rq <= '0';
+
+ pavr_s5_skip_cond_sel <= int_to_std_logic_vector(0, pavr_s5_skip_cond_sel'length);
+ pavr_s5_s6_skip_cond_sel <= '0';
+ pavr_s5_skip_en <= '0';
+ pavr_s5_s6_skip_en <= '0';
+ pavr_s5_skip_bitrf_sel <= int_to_std_logic_vector(0, pavr_s5_skip_bitrf_sel'length);
+ pavr_s5_s6_skip_bitiof_sel <= int_to_std_logic_vector(0, pavr_s5_s6_skip_bitiof_sel'length);
+ pavr_s5_k7_branch_offset <= int_to_std_logic_vector(0, pavr_s5_k7_branch_offset'length);
+ pavr_s5_branch_cond_sel <= '0';
+ pavr_s5_branch_en <= '0';
+ pavr_s5_branch_bitsreg_sel <= int_to_std_logic_vector(0, pavr_s5_branch_bitsreg_sel'length);
+
+ -- Others
+ pavr_s5_disable_int <= '0';
+ elsif pavr_stall_s4='0' then
+ -- RF read port 1-related
+
+ if pavr_rf_do_shadow_active='0' then
+ pavr_s5_op1 <= pavr_rf_rd1_do;
+ else
+ pavr_s5_op1 <= pavr_rf_rd1_do_shadow;
+ end if;
+
+ -- RF read port 2-related
+
+ if pavr_rf_do_shadow_active='0' then
+ pavr_s5_op2 <= pavr_rf_rd2_do;
+ else
+ pavr_s5_op2 <= pavr_rf_rd2_do_shadow;
+ end if;
+
+ -- RF write port-related
+ pavr_s5_s6_aluoutlo8_rfwr_rq <= pavr_s4_s6_aluoutlo8_rfwr_rq;
+ pavr_s5_s61_aluouthi8_rfwr_rq <= pavr_s4_s61_aluouthi8_rfwr_rq;
+ pavr_s5_s6_iof_rfwr_rq <= pavr_s4_s6_iof_rfwr_rq;
+ pavr_s5_s6_dacu_rfwr_rq <= pavr_s4_s6_dacu_rfwr_rq;
+ pavr_s5_s6_pm_rfwr_rq <= pavr_s4_s6_pm_rfwr_rq;
+
+ pavr_s5_s6_rfwr_addr1 <= pavr_s4_s6_rfwr_addr1;
+ pavr_s5_s61_rfwr_addr2 <= pavr_s4_s61_rfwr_addr2;
+
+ -- Pointer registers-related
+ pavr_s5_ldstincrampx_xwr_rq <= pavr_s4_s5_ldstincrampx_xwr_rq;
+ pavr_s5_ldstdecrampx_xwr_rq <= pavr_s4_s5_ldstdecrampx_xwr_rq;
+
+ pavr_s5_ldstincrampy_ywr_rq <= pavr_s4_s5_ldstincrampy_ywr_rq;
+ pavr_s5_ldstdecrampy_ywr_rq <= pavr_s4_s5_ldstdecrampy_ywr_rq;
+
+ pavr_s5_ldstincrampz_zwr_rq <= pavr_s4_s5_ldstincrampz_zwr_rq;
+ pavr_s5_ldstdecrampz_zwr_rq <= pavr_s4_s5_ldstdecrampz_zwr_rq;
+ pavr_s5_elpmincrampz_zwr_rq <= pavr_s4_s5_elpmincrampz_zwr_rq;
+ pavr_s5_lpminc_zwr_rq <= pavr_s4_s5_lpminc_zwr_rq;
+
+ -- BPU write, BPR0-related
+ pavr_s5_alu_bpr0wr_rq <= pavr_s4_s5_alu_bpr0wr_rq;
+ pavr_s5_s6_iof_bpr0wr_rq <= pavr_s4_s6_iof_bpr0wr_rq;
+ pavr_s5_s6_daculd_bpr0wr_rq <= pavr_s4_s6_daculd_bpr0wr_rq;
+ pavr_s5_s6_pmdo_bpr0wr_rq <= pavr_s4_s6_pmdo_bpr0wr_rq;
+
+ -- BPU write, BPR1-related
+ pavr_s5_dacux_bpr12wr_rq <= pavr_s4_s5_dacux_bpr12wr_rq;
+ pavr_s5_dacuy_bpr12wr_rq <= pavr_s4_s5_dacuy_bpr12wr_rq;
+ pavr_s5_dacuz_bpr12wr_rq <= pavr_s4_s5_dacuz_bpr12wr_rq;
+ pavr_s5_alu_bpr1wr_rq <= pavr_s4_s5_alu_bpr1wr_rq;
+
+ -- IOF port-related
+ pavr_s5_iof_rq <= pavr_s4_s5_iof_rq;
+ pavr_s5_s6_iof_rq <= pavr_s4_s6_iof_rq;
+
+ pavr_s5_iof_opcode <= pavr_s4_s5_iof_opcode;
+ pavr_s5_s6_iof_opcode <= pavr_s4_s6_iof_opcode;
+ pavr_s5_iof_addr <= pavr_s4_s5s6_iof_addr;
+ pavr_s5_iof_bitaddr <= pavr_s4_s5s6_iof_bitaddr;
+
+ -- SREG-related
+ pavr_s5_alu_sregwr_rq <= pavr_s4_s5_alu_sregwr_rq;
+ pavr_s5_clriflag_sregwr_rq <= pavr_s4_s5_clriflag_sregwr_rq;
+ pavr_s5_setiflag_sregwr_rq <= pavr_s4_s5_setiflag_sregwr_rq;
+
+ -- SP-related
+ pavr_s5_inc_spwr_rq <= pavr_s4_s5_inc_spwr_rq;
+ pavr_s5_dec_spwr_rq <= pavr_s4_s5_dec_spwr_rq;
+ pavr_s5_calldec_spwr_rq <= pavr_s4_s5s51s52_calldec_spwr_rq;
+ pavr_s5_retinc2_spwr_rq <= pavr_s4_s5s51_retinc_spwr_rq;
+
+ -- ALU-related
+ pavr_s5_alu_opcode <= pavr_s4_s5_alu_opcode;
+ pavr_s5_alu_op1_hi8_sel <= pavr_s4_s5_alu_op1_hi8_sel;
+ pavr_s5_alu_op2_sel <= pavr_s4_s5_alu_op2_sel;
+ pavr_s5_op1_addr <= pavr_s4_s5_op1_addr;
+ pavr_s5_op2_addr <= pavr_s4_s5_op2_addr;
+ pavr_s5_k8 <= pavr_s4_s5_k8;
+
+ -- DACU setup-related
+ pavr_s5_rf_dacu_q <= pavr_s4_dacu_q;
+ pavr_s5_iof_dacu_q <= pavr_s4_iof_dacu_q;
+ pavr_s5_dm_dacu_q <= pavr_s4_dm_dacu_q;
+ if pavr_s4_instr32bits='1' then
+ pavr_s5_k16 <= pavr_s3_instr;
+ end if;
+
+ -- DACU read-related
+ pavr_s5_x_dacurd_rq <= pavr_s4_s5_x_dacurd_rq;
+ pavr_s5_y_dacurd_rq <= pavr_s4_s5_y_dacurd_rq;
+ pavr_s5_z_dacurd_rq <= pavr_s4_s5_z_dacurd_rq;
+ pavr_s5_sp_dacurd_rq <= pavr_s4_s5_sp_dacurd_rq;
+ pavr_s5_k16_dacurd_rq <= pavr_s4_s5_k16_dacurd_rq;
+ pavr_s5_pchi8_dacurd_rq <= pavr_s4_s5s51s52_pc_dacurd_rq;
+
+ -- DACU write-related
+ pavr_s5_sp_dacuwr_rq <= pavr_s4_s5_sp_dacuwr_rq;
+ pavr_s5_k16_dacuwr_rq <= pavr_s4_s5_k16_dacuwr_rq;
+ pavr_s5_x_dacuwr_rq <= pavr_s4_s5_x_dacuwr_rq;
+ pavr_s5_y_dacuwr_rq <= pavr_s4_s5_y_dacuwr_rq;
+ pavr_s5_z_dacuwr_rq <= pavr_s4_s5_z_dacuwr_rq;
+ pavr_s5_pclo8_dacuwr_rq <= pavr_s4_s5s51s52_pc_dacuwr_rq;
+
+ -- DM-related
+
+ -- PM access-related
+ pavr_s5_lpm_pm_rq <= pavr_s4_s5_lpm_pm_rq;
+ pavr_s5_elpm_pm_rq <= pavr_s4_s5_elpm_pm_rq;
+ pavr_s5_s54_ret_pm_rq <= pavr_s4_s54_ret_pm_rq;
+
+ if pavr_s4_pcinc='1' then
+ pavr_s5_pc <= pavr_s4_pc + 1;
+ else
+ pavr_s5_pc <= pavr_s4_pc;
+ end if;
+ pavr_s5_s51s52s53_retpc_ld <= pavr_s4_s51s52s53_retpc_ld;
+
+ -- SFU requests-related
+ pavr_s5_stall_rq <= pavr_s4_s5_stall_rq;
+ pavr_s5_s6_stall_rq <= pavr_s4_s6_stall_rq;
+ pavr_s5_ret_flush_s2_rq <= pavr_s4_ret_flush_s2_rq;
+
+ pavr_s5_skip_cond_sel <= pavr_s4_s5_skip_cond_sel;
+ pavr_s5_s6_skip_cond_sel <= pavr_s4_s6_skip_cond_sel;
+ pavr_s5_skip_en <= pavr_s4_s5_skip_en;
+ pavr_s5_s6_skip_en <= pavr_s4_s6_skip_en;
+ pavr_s5_skip_bitrf_sel <= pavr_s4_s5_skip_bitrf_sel;
+ pavr_s5_s6_skip_bitiof_sel <= pavr_s4_s6_skip_bitiof_sel;
+ pavr_s5_k7_branch_offset <= pavr_s4_s5_k7_branch_offset;
+ pavr_s5_branch_cond_sel <= pavr_s4_s5_branch_cond_sel;
+ pavr_s5_branch_en <= pavr_s4_s5_branch_en;
+ pavr_s5_branch_bitsreg_sel <= pavr_s4_s5_branch_bitsreg_sel;
+
+ -- Others
+ pavr_s5_disable_int <= pavr_s4_disable_int;
+ end if;
+
+ -- Stage s5 ----------------------------------------------------------
+ if pavr_flush_s5='1' then
+ -- RF read port 1-related
+
+ -- RF read port 2-related
+
+ -- RF write port-related
+ pavr_s6_aluoutlo8_rfwr_rq <= '0';
+ pavr_s6_s61_aluouthi8_rfwr_rq <= '0';
+ pavr_s6_iof_rfwr_rq <= '0';
+ pavr_s6_dacu_rfwr_rq <= '0';
+ pavr_s6_pm_rfwr_rq <= '0';
+
+ pavr_s6_rfwr_addr1 <= int_to_std_logic_vector(0, pavr_s6_rfwr_addr1'length);
+ pavr_s6_s61_rfwr_addr2 <= int_to_std_logic_vector(0, pavr_s6_s61_rfwr_addr2'length);
+
+ -- Pointer registers-related
+
+ -- BPU write, BPR0-related
+ pavr_s6_iof_bpr0wr_rq <= '0';
+ pavr_s6_daculd_bpr0wr_rq <= '0';
+ pavr_s6_pmdo_bpr0wr_rq <= '0';
+
+ -- BPU write, BPR1-related
+
+ -- IOF port-related
+ pavr_s6_iof_rq <= '0';
+
+ pavr_s6_iof_opcode <= int_to_std_logic_vector(0, pavr_s6_iof_opcode'length);
+ pavr_s6_iof_addr <= int_to_std_logic_vector(0, pavr_s6_iof_addr'length);
+ pavr_s6_iof_bitaddr <= int_to_std_logic_vector(0, pavr_s6_iof_bitaddr'length);
+
+ -- SREG-related
+
+ -- SP-related
+ pavr_s51_calldec_spwr_rq <= '0';
+ pavr_s51_retinc_spwr_rq <= '0';
+
+ -- ALU-related
+ pavr_s6_alu_out <= int_to_std_logic_vector(0, pavr_s6_alu_out'length);
+
+ -- DACU setup-related
+
+ -- DACU read-related
+ pavr_s51_pcmid8_dacurd_rq <= '0';
+
+ -- DACU write-related
+ pavr_s51_pcmid8_dacuwr_rq <= '0';
+
+ -- DM-related
+
+ -- PM access-related
+ pavr_s51_s54_ret_pm_rq <= '0';
+
+ --pavr_s51_pc <= int_to_std_logic_vector(0, pavr_s51_pc'length); -- *** Comment this. The flush lines shouldn't interfere with PC temporary storage. Otherwise, 32 bit intructions are messed up.
+ pavr_s51_retpchi8_ld <= '0';
+ pavr_s6_zlsb <= '0';
+
+ -- SFU requests-related
+ pavr_s6_stall_rq <= '0';
+ pavr_s51_ret_flush_s2_rq <= '0';
+ pavr_s6_skip_rq <= '0';
+ pavr_s6_branch_rq <= '0';
+
+ pavr_s6_skip_cond_sel <= '0';
+ pavr_s6_skip_en <= '0';
+ pavr_s6_skip_bitiof_sel <= int_to_std_logic_vector(0, pavr_s6_skip_bitiof_sel'length);
+ pavr_s6_branch_pc <= int_to_std_logic_vector(0, pavr_s6_branch_pc'length);
+
+ -- Others
+ pavr_s51_disable_int <= '0';
+ elsif pavr_stall_s5='0' then
+ -- RF read port 1-related
+
+ -- RF read port 2-related
+
+ -- RF write port-related
+ pavr_s6_aluoutlo8_rfwr_rq <= pavr_s5_s6_aluoutlo8_rfwr_rq;
+ pavr_s6_s61_aluouthi8_rfwr_rq <= pavr_s5_s61_aluouthi8_rfwr_rq;
+ pavr_s6_iof_rfwr_rq <= pavr_s5_s6_iof_rfwr_rq;
+ pavr_s6_dacu_rfwr_rq <= pavr_s5_s6_dacu_rfwr_rq;
+ pavr_s6_pm_rfwr_rq <= pavr_s5_s6_pm_rfwr_rq;
+
+ pavr_s6_rfwr_addr1 <= pavr_s5_s6_rfwr_addr1;
+ pavr_s6_s61_rfwr_addr2 <= pavr_s5_s61_rfwr_addr2;
+
+ -- Pointer registers-related
+
+ -- BPU write, BPR0-related
+ pavr_s6_iof_bpr0wr_rq <= pavr_s5_s6_iof_bpr0wr_rq;
+ pavr_s6_daculd_bpr0wr_rq <= pavr_s5_s6_daculd_bpr0wr_rq;
+ pavr_s6_pmdo_bpr0wr_rq <= pavr_s5_s6_pmdo_bpr0wr_rq;
+
+ -- BPU write, BPR1-related
+
+ -- IOF port-related
+ pavr_s6_iof_rq <= pavr_s5_s6_iof_rq;
+
+ pavr_s6_iof_opcode <= pavr_s5_s6_iof_opcode;
+ pavr_s6_iof_addr <= pavr_s5_iof_addr;
+ pavr_s6_iof_bitaddr <= pavr_s5_iof_bitaddr;
+
+ -- SREG-related
+
+ -- SP-related
+ pavr_s51_calldec_spwr_rq <= pavr_s5_calldec_spwr_rq;
+ pavr_s51_retinc_spwr_rq <= pavr_s5_retinc2_spwr_rq;
+
+ -- ALU-related
+ pavr_s6_alu_out <= pavr_s5_alu_out;
+
+ -- DACU setup-related
+ pavr_s51_pcmid8_dacurd_rq <= pavr_s5_pchi8_dacurd_rq;
+
+ -- DACU read-related
+
+ -- DACU write-related
+ pavr_s51_pcmid8_dacuwr_rq <= pavr_s5_pclo8_dacuwr_rq;
+
+ -- DM-related
+
+ -- PM access-related
+ pavr_s51_s54_ret_pm_rq <= pavr_s5_s54_ret_pm_rq;
+
+ pavr_s51_pc <= pavr_s5_pc;
+ pavr_s51_retpchi8_ld <= pavr_s5_s51s52s53_retpc_ld;
+ pavr_s6_zlsb <= pavr_zbpu(0);
+
+ -- SFU requests-related
+ pavr_s6_stall_rq <= pavr_s5_s6_stall_rq;
+ pavr_s51_ret_flush_s2_rq <= pavr_s5_ret_flush_s2_rq;
+ pavr_s6_skip_rq <= next_pavr_s6_skip_rq;
+ pavr_s6_branch_rq <= next_pavr_s6_branch_rq;
+
+ pavr_s6_skip_cond_sel <= pavr_s5_s6_skip_cond_sel;
+ pavr_s6_skip_en <= pavr_s5_s6_skip_en;
+ pavr_s6_skip_bitiof_sel <= pavr_s5_s6_skip_bitiof_sel;
+ pavr_s6_branch_pc <= sign_extend(pavr_s5_k7_branch_offset, 22) + pavr_s5_pc;
+
+ -- Others
+ pavr_s51_disable_int <= pavr_s5_disable_int;
+ end if;
+
+ -- Stage s6 ----------------------------------------------------------
+ if pavr_flush_s6='1' then
+ -- RF read port 1-related
+
+ -- RF read port 2-related
+
+ -- RF write port-related
+
+ pavr_s61_rfwr_addr2 <= int_to_std_logic_vector(0, pavr_s61_rfwr_addr2'length);
+ pavr_s61_aluouthi8_rfwr_rq <= '0';
+
+ -- Pointer registers-related
+
+ -- BPU write, BPR0-related
+
+ -- BPU write, BPR1-related
+
+ -- IOF port-related
+
+ -- SREG-related
+
+ -- SP-related
+
+ -- ALU-related
+ pavr_s61_alu_out_hi8 <= int_to_std_logic_vector(0, pavr_s61_alu_out_hi8'length);
+
+ -- DACU setup-related
+
+ -- DACU read-related
+
+ -- DACU write-related
+
+ -- DM-related
+
+ -- PM access-related
+
+ -- SFU requests-related
+ pavr_s61_skip_rq <= '0';
+
+ -- Others
+ elsif pavr_stall_s6='0' then
+ -- RF read port 1-related
+
+ -- RF read port 2-related
+
+ -- RF write port-related
+
+ pavr_s61_rfwr_addr2 <= pavr_s6_s61_rfwr_addr2;
+ pavr_s61_aluouthi8_rfwr_rq <= pavr_s6_s61_aluouthi8_rfwr_rq;
+
+ -- Pointer registers-related
+
+ -- BPU write, BPR0-related
+
+ -- BPU write, BPR1-related
+
+ -- IOF port-related
+
+ -- SREG-related
+
+ -- SP-related
+
+ -- ALU-related
+ pavr_s61_alu_out_hi8 <= pavr_s6_alu_out(15 downto 8);
+
+ -- DACU setup-related
+
+ -- DACU read-related
+
+ -- DACU write-related
+
+ -- DM-related
+
+ -- PM access-related
+
+ -- SFU requests-related
+ pavr_s61_skip_rq <= next_pavr_s61_skip_rq;
+
+ -- Others
+ end if;
+
+ -- Stage s51 ---------------------------------------------------------
+ pavr_s52_ret_flush_s2_rq <= pavr_s51_ret_flush_s2_rq;
+ pavr_s52_pc <= pavr_s51_pc;
+ pavr_s52_pchi8_dacuwr_rq <= pavr_s51_pcmid8_dacuwr_rq;
+ pavr_s52_calldec_spwr_rq <= pavr_s51_calldec_spwr_rq;
+ pavr_s52_disable_int <= pavr_s51_disable_int;
+ pavr_s52_retpcmid8_ld <= pavr_s51_retpchi8_ld;
+ pavr_s52_pclo8_dacurd_rq <= pavr_s51_pcmid8_dacurd_rq;
+ pavr_s52_s54_ret_pm_rq <= pavr_s51_s54_ret_pm_rq;
+
+ -- Stage s52 ---------------------------------------------------------
+ pavr_s53_ret_flush_s2_rq <= pavr_s52_ret_flush_s2_rq;
+ pavr_s53_retpclo8_ld <= pavr_s52_retpcmid8_ld;
+ pavr_s53_s54_ret_pm_rq <= pavr_s52_s54_ret_pm_rq;
+
+ -- Stage s53 ---------------------------------------------------------
+ pavr_s54_ret_flush_s2_rq <= pavr_s53_ret_flush_s2_rq;
+ pavr_s54_ret_pm_rq <= pavr_s53_s54_ret_pm_rq;
+
+ -- Stage s54 ---------------------------------------------------------
+ pavr_s55_ret_flush_s2_rq <= pavr_s54_ret_flush_s2_rq;
+
+ -- Others ------------------------------------------------------------
+ if pavr_s4_nop_rq='1' and pavr_nop_ack='0' then
+ pavr_nop_ack <= '1';
+ else
+ pavr_nop_ack <= '0';
+ end if;
+
+ if pavr_s51_retpchi8_ld='1' then
+ if pavr_dacu_do_shadow_active='0' then
+ pavr_s52_retpchi8 <= pavr_dacu_do;
+ else
+ pavr_s52_retpchi8 <= pavr_dacu_do_shadow;
+ end if;
+ end if;
+ if pavr_s52_retpcmid8_ld='1' then
+ if pavr_dacu_do_shadow_active='0' then
+ pavr_s53_retpcmid8 <= pavr_dacu_do;
+ else
+ pavr_s53_retpcmid8 <= pavr_dacu_do_shadow;
+ end if;
+ end if;
+ if pavr_s53_retpclo8_ld='1' then
+ if pavr_dacu_do_shadow_active='0' then
+ pavr_s54_retpclo8 <= pavr_dacu_do;
+ else
+ pavr_s54_retpclo8 <= pavr_dacu_do_shadow;
+ end if;
+ end if;
+
+ pavr_s1_pc <= next_pavr_s1_pc;
+
+ if pavr_stall_bpu='0' then
+ pavr_bpr00 <= next_pavr_bpr0;
+ pavr_bpr00_addr <= next_pavr_bpr0_addr;
+ pavr_bpr00_active <= next_pavr_bpr0_active;
+ pavr_bpr01 <= pavr_bpr00;
+ pavr_bpr01_addr <= pavr_bpr00_addr;
+ pavr_bpr01_active <= pavr_bpr00_active;
+ pavr_bpr02 <= pavr_bpr01;
+ pavr_bpr02_addr <= pavr_bpr01_addr;
+ pavr_bpr02_active <= pavr_bpr01_active;
+ pavr_bpr03 <= pavr_bpr02;
+ pavr_bpr03_addr <= pavr_bpr02_addr;
+ pavr_bpr03_active <= pavr_bpr02_active;
+
+ pavr_bpr10 <= next_pavr_bpr1;
+ pavr_bpr10_addr <= next_pavr_bpr1_addr;
+ pavr_bpr10_active <= next_pavr_bpr1_active;
+ pavr_bpr11 <= pavr_bpr10;
+ pavr_bpr11_addr <= pavr_bpr10_addr;
+ pavr_bpr11_active <= pavr_bpr10_active;
+ pavr_bpr12 <= pavr_bpr11;
+ pavr_bpr12_addr <= pavr_bpr11_addr;
+ pavr_bpr12_active <= pavr_bpr11_active;
+ pavr_bpr13 <= pavr_bpr12;
+ pavr_bpr13_addr <= pavr_bpr12_addr;
+ pavr_bpr13_active <= pavr_bpr12_active;
+
+ pavr_bpr20 <= next_pavr_bpr2;
+ pavr_bpr20_addr <= next_pavr_bpr2_addr;
+ pavr_bpr20_active <= next_pavr_bpr2_active;
+ pavr_bpr21 <= pavr_bpr20;
+ pavr_bpr21_addr <= pavr_bpr20_addr;
+ pavr_bpr21_active <= pavr_bpr20_active;
+ pavr_bpr22 <= pavr_bpr21;
+ pavr_bpr22_addr <= pavr_bpr21_addr;
+ pavr_bpr22_active <= pavr_bpr21_active;
+ pavr_bpr23 <= pavr_bpr22;
+ pavr_bpr23_addr <= pavr_bpr22_addr;
+ pavr_bpr23_active <= pavr_bpr22_active;
+ end if;
+
+ pavr_s6_dacudo_sel <= pavr_s5_dacudo_sel;
+
+ if pavr_syncres='1' then
+ -- Synchronous reset ----------------------------------------------
+
+ -- RF read port 1-related
+
+ pavr_s5_op1 <= int_to_std_logic_vector(0, pavr_s5_op1'length);
+
+ -- RF read port 2-related
+
+ pavr_s5_op2 <= int_to_std_logic_vector(0, pavr_s5_op2'length);
+
+ -- RF write port-related
+ pavr_s4_s6_aluoutlo8_rfwr_rq <= '0';
+ pavr_s5_s6_aluoutlo8_rfwr_rq <= '0';
+ pavr_s6_aluoutlo8_rfwr_rq <= '0';
+ pavr_s4_s61_aluouthi8_rfwr_rq <= '0';
+ pavr_s5_s61_aluouthi8_rfwr_rq <= '0';
+ pavr_s6_s61_aluouthi8_rfwr_rq <= '0';
+ pavr_s61_aluouthi8_rfwr_rq <= '0';
+ pavr_s4_s6_iof_rfwr_rq <= '0';
+ pavr_s5_s6_iof_rfwr_rq <= '0';
+ pavr_s6_iof_rfwr_rq <= '0';
+ pavr_s4_s6_dacu_rfwr_rq <= '0';
+ pavr_s5_s6_dacu_rfwr_rq <= '0';
+ pavr_s6_dacu_rfwr_rq <= '0';
+ pavr_s4_s6_pm_rfwr_rq <= '0';
+ pavr_s5_s6_pm_rfwr_rq <= '0';
+ pavr_s6_pm_rfwr_rq <= '0';
+
+ pavr_s4_s6_rfwr_addr1 <= int_to_std_logic_vector(0, pavr_s4_s6_rfwr_addr1'length);
+ pavr_s5_s6_rfwr_addr1 <= int_to_std_logic_vector(0, pavr_s5_s6_rfwr_addr1'length);
+ pavr_s6_rfwr_addr1 <= int_to_std_logic_vector(0, pavr_s6_rfwr_addr1'length);
+ pavr_s4_s61_rfwr_addr2 <= int_to_std_logic_vector(0, pavr_s4_s61_rfwr_addr2'length);
+ pavr_s5_s61_rfwr_addr2 <= int_to_std_logic_vector(0, pavr_s5_s61_rfwr_addr2'length);
+ pavr_s6_s61_rfwr_addr2 <= int_to_std_logic_vector(0, pavr_s6_s61_rfwr_addr2'length);
+ pavr_s61_rfwr_addr2 <= int_to_std_logic_vector(0, pavr_s61_rfwr_addr2'length);
+
+ -- Pointer registers-related
+ pavr_s4_s5_ldstincrampx_xwr_rq <= '0';
+ pavr_s5_ldstincrampx_xwr_rq <= '0';
+ pavr_s4_s5_ldstdecrampx_xwr_rq <= '0';
+ pavr_s5_ldstdecrampx_xwr_rq <= '0';
+
+ pavr_s4_s5_ldstincrampy_ywr_rq <= '0';
+ pavr_s5_ldstincrampy_ywr_rq <= '0';
+ pavr_s4_s5_ldstdecrampy_ywr_rq <= '0';
+ pavr_s5_ldstdecrampy_ywr_rq <= '0';
+
+ pavr_s4_s5_ldstincrampz_zwr_rq <= '0';
+ pavr_s5_ldstincrampz_zwr_rq <= '0';
+ pavr_s4_s5_ldstdecrampz_zwr_rq <= '0';
+ pavr_s5_ldstdecrampz_zwr_rq <= '0';
+ pavr_s4_s5_elpmincrampz_zwr_rq <= '0';
+ pavr_s5_elpmincrampz_zwr_rq <= '0';
+ pavr_s4_s5_lpminc_zwr_rq <= '0';
+ pavr_s5_lpminc_zwr_rq <= '0';
+
+ -- BPU write, BPR0-related
+ pavr_s4_s5_alu_bpr0wr_rq <= '0';
+ pavr_s5_alu_bpr0wr_rq <= '0';
+ pavr_s4_s6_iof_bpr0wr_rq <= '0';
+ pavr_s5_s6_iof_bpr0wr_rq <= '0';
+ pavr_s6_iof_bpr0wr_rq <= '0';
+ pavr_s4_s6_daculd_bpr0wr_rq <= '0';
+ pavr_s5_s6_daculd_bpr0wr_rq <= '0';
+ pavr_s6_daculd_bpr0wr_rq <= '0';
+ pavr_s4_s6_pmdo_bpr0wr_rq <= '0';
+ pavr_s5_s6_pmdo_bpr0wr_rq <= '0';
+ pavr_s6_pmdo_bpr0wr_rq <= '0';
+
+ pavr_bpr00 <= int_to_std_logic_vector(0, pavr_bpr00'length);
+ pavr_bpr00_addr <= int_to_std_logic_vector(0, pavr_bpr00_addr'length);
+ pavr_bpr00_active <= '0';
+ pavr_bpr01 <= int_to_std_logic_vector(0, pavr_bpr01'length);
+ pavr_bpr01_addr <= int_to_std_logic_vector(0, pavr_bpr01_addr'length);
+ pavr_bpr01_active <= '0';
+ pavr_bpr02 <= int_to_std_logic_vector(0, pavr_bpr02'length);
+ pavr_bpr02_addr <= int_to_std_logic_vector(0, pavr_bpr02_addr'length);
+ pavr_bpr02_active <= '0';
+ pavr_bpr03 <= int_to_std_logic_vector(0, pavr_bpr03'length);
+ pavr_bpr03_addr <= int_to_std_logic_vector(0, pavr_bpr03_addr'length);
+ pavr_bpr03_active <= '0';
+
+ -- BPU write, BPR1-related
+ pavr_s4_s5_dacux_bpr12wr_rq <= '0';
+ pavr_s5_dacux_bpr12wr_rq <= '0';
+ pavr_s4_s5_dacuy_bpr12wr_rq <= '0';
+ pavr_s5_dacuy_bpr12wr_rq <= '0';
+ pavr_s4_s5_dacuz_bpr12wr_rq <= '0';
+ pavr_s5_dacuz_bpr12wr_rq <= '0';
+ pavr_s4_s5_alu_bpr1wr_rq <= '0';
+ pavr_s5_alu_bpr1wr_rq <= '0';
+
+ pavr_bpr10 <= int_to_std_logic_vector(0, pavr_bpr10'length);
+ pavr_bpr10_addr <= int_to_std_logic_vector(0, pavr_bpr10_addr'length);
+ pavr_bpr10_active <= '0';
+ pavr_bpr11 <= int_to_std_logic_vector(0, pavr_bpr11'length);
+ pavr_bpr11_addr <= int_to_std_logic_vector(0, pavr_bpr11_addr'length);
+ pavr_bpr11_active <= '0';
+ pavr_bpr12 <= int_to_std_logic_vector(0, pavr_bpr12'length);
+ pavr_bpr12_addr <= int_to_std_logic_vector(0, pavr_bpr12_addr'length);
+ pavr_bpr12_active <= '0';
+ pavr_bpr13 <= int_to_std_logic_vector(0, pavr_bpr13'length);
+ pavr_bpr13_addr <= int_to_std_logic_vector(0, pavr_bpr13_addr'length);
+ pavr_bpr13_active <= '0';
+
+ -- BPU write, BPR2-related
+
+ pavr_bpr20 <= int_to_std_logic_vector(0, pavr_bpr20'length);
+ pavr_bpr20_addr <= int_to_std_logic_vector(0, pavr_bpr20_addr'length);
+ pavr_bpr20_active <= '0';
+ pavr_bpr21 <= int_to_std_logic_vector(0, pavr_bpr21'length);
+ pavr_bpr21_addr <= int_to_std_logic_vector(0, pavr_bpr21_addr'length);
+ pavr_bpr21_active <= '0';
+ pavr_bpr22 <= int_to_std_logic_vector(0, pavr_bpr22'length);
+ pavr_bpr22_addr <= int_to_std_logic_vector(0, pavr_bpr22_addr'length);
+ pavr_bpr22_active <= '0';
+ pavr_bpr23 <= int_to_std_logic_vector(0, pavr_bpr23'length);
+ pavr_bpr23_addr <= int_to_std_logic_vector(0, pavr_bpr23_addr'length);
+ pavr_bpr23_active <= '0';
+
+ -- IOF port-related
+ pavr_s4_s5_iof_rq <= '0';
+ pavr_s5_iof_rq <= '0';
+ pavr_s4_s6_iof_rq <= '0';
+ pavr_s5_s6_iof_rq <= '0';
+ pavr_s6_iof_rq <= '0';
+
+ pavr_s4_s5_iof_opcode <= int_to_std_logic_vector(0, pavr_s4_s5_iof_opcode'length);
+ pavr_s5_iof_opcode <= int_to_std_logic_vector(0, pavr_s5_iof_opcode'length);
+ pavr_s4_s6_iof_opcode <= int_to_std_logic_vector(0, pavr_s4_s6_iof_opcode'length);
+ pavr_s5_s6_iof_opcode <= int_to_std_logic_vector(0, pavr_s5_s6_iof_opcode'length);
+ pavr_s6_iof_opcode <= int_to_std_logic_vector(0, pavr_s6_iof_opcode'length);
+ pavr_s4_s5s6_iof_addr <= int_to_std_logic_vector(0, pavr_s4_s5s6_iof_addr'length);
+ pavr_s5_iof_addr <= int_to_std_logic_vector(0, pavr_s5_iof_addr'length);
+ pavr_s6_iof_addr <= int_to_std_logic_vector(0, pavr_s6_iof_addr'length);
+ pavr_s4_s5s6_iof_bitaddr <= int_to_std_logic_vector(0, pavr_s4_s5s6_iof_bitaddr'length);
+ pavr_s5_iof_bitaddr <= int_to_std_logic_vector(0, pavr_s5_iof_bitaddr'length);
+ pavr_s6_iof_bitaddr <= int_to_std_logic_vector(0, pavr_s6_iof_bitaddr'length);
+
+ -- SREG-related
+ pavr_s4_s5_alu_sregwr_rq <= '0';
+ pavr_s5_alu_sregwr_rq <= '0';
+ pavr_s4_s5_clriflag_sregwr_rq <= '0';
+ pavr_s5_clriflag_sregwr_rq <= '0';
+ pavr_s4_s5_setiflag_sregwr_rq <= '0';
+ pavr_s5_setiflag_sregwr_rq <= '0';
+
+ -- SP-related
+ pavr_s4_s5_inc_spwr_rq <= '0';
+ pavr_s5_inc_spwr_rq <= '0';
+ pavr_s4_s5_dec_spwr_rq <= '0';
+ pavr_s5_dec_spwr_rq <= '0';
+ pavr_s4_s5s51s52_calldec_spwr_rq <= '0';
+ pavr_s5_calldec_spwr_rq <= '0';
+ pavr_s51_calldec_spwr_rq <= '0';
+ pavr_s52_calldec_spwr_rq <= '0';
+ pavr_s4_s5s51_retinc_spwr_rq <= '0';
+ pavr_s5_retinc2_spwr_rq <= '0';
+ pavr_s51_retinc_spwr_rq <= '0';
+
+ -- ALU-related
+ pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(0, pavr_s4_s5_alu_opcode'length);
+ pavr_s5_alu_opcode <= int_to_std_logic_vector(0, pavr_s5_alu_opcode'length);
+ pavr_s4_s5_alu_op1_hi8_sel <= '0';
+ pavr_s5_alu_op1_hi8_sel <= '0';
+ pavr_s4_s5_alu_op2_sel <= int_to_std_logic_vector(0, pavr_s4_s5_alu_op2_sel'length);
+ pavr_s5_alu_op2_sel <= int_to_std_logic_vector(0, pavr_s5_alu_op2_sel'length);
+ pavr_s4_s5_op1_addr <= int_to_std_logic_vector(0, pavr_s4_s5_op1_addr'length);
+ pavr_s5_op1_addr <= int_to_std_logic_vector(0, pavr_s5_op1_addr'length);
+ pavr_s4_s5_op2_addr <= int_to_std_logic_vector(0, pavr_s4_s5_op2_addr'length);
+ pavr_s5_op2_addr <= int_to_std_logic_vector(0, pavr_s5_op2_addr'length);
+ pavr_s4_s5_k8 <= int_to_std_logic_vector(0, pavr_s4_s5_k8'length);
+ pavr_s5_k8 <= int_to_std_logic_vector(0, pavr_s5_k8'length);
+ pavr_s6_alu_out <= int_to_std_logic_vector(0, pavr_s6_alu_out'length);
+ pavr_s61_alu_out_hi8 <= int_to_std_logic_vector(0, pavr_s61_alu_out_hi8'length);
+
+ -- DACU setup-related
+ pavr_s4_dacu_q <= int_to_std_logic_vector(0, pavr_s4_dacu_q'length);
+ pavr_s5_rf_dacu_q <= int_to_std_logic_vector(0, pavr_s5_rf_dacu_q'length);
+ pavr_s5_iof_dacu_q <= int_to_std_logic_vector(0, pavr_s5_iof_dacu_q'length);
+ pavr_s5_dm_dacu_q <= int_to_std_logic_vector(0, pavr_s5_dm_dacu_q'length);
+ pavr_s6_dacudo_sel <= int_to_std_logic_vector(0, pavr_s6_dacudo_sel'length);
+ pavr_s5_k16 <= int_to_std_logic_vector(0, pavr_s5_k16'length);
+
+ -- DACU read-related
+ pavr_s4_s5_x_dacurd_rq <= '0';
+ pavr_s5_x_dacurd_rq <= '0';
+ pavr_s4_s5_y_dacurd_rq <= '0';
+ pavr_s5_y_dacurd_rq <= '0';
+ pavr_s4_s5_z_dacurd_rq <= '0';
+ pavr_s5_z_dacurd_rq <= '0';
+ pavr_s4_s5_sp_dacurd_rq <= '0';
+ pavr_s5_sp_dacurd_rq <= '0';
+ pavr_s4_s5_k16_dacurd_rq <= '0';
+ pavr_s5_k16_dacurd_rq <= '0';
+ pavr_s4_s5s51s52_pc_dacurd_rq <= '0';
+ pavr_s5_pchi8_dacurd_rq <= '0';
+ pavr_s51_pcmid8_dacurd_rq <= '0';
+ pavr_s52_pclo8_dacurd_rq <= '0';
+
+ -- DACU write-related
+ pavr_s4_s5_sp_dacuwr_rq <= '0';
+ pavr_s5_sp_dacuwr_rq <= '0';
+ pavr_s4_s5_x_dacuwr_rq <= '0';
+ pavr_s5_x_dacuwr_rq <= '0';
+ pavr_s4_s5_y_dacuwr_rq <= '0';
+ pavr_s5_y_dacuwr_rq <= '0';
+ pavr_s4_s5_z_dacuwr_rq <= '0';
+ pavr_s5_z_dacuwr_rq <= '0';
+ pavr_s4_s5s51s52_pc_dacuwr_rq <= '0';
+ pavr_s5_pclo8_dacuwr_rq <= '0';
+ pavr_s51_pcmid8_dacuwr_rq <= '0';
+ pavr_s52_pchi8_dacuwr_rq <= '0';
+
+ -- DM-related
+
+ -- PM access-related
+ pavr_s4_s5_lpm_pm_rq <= '0';
+ pavr_s5_lpm_pm_rq <= '0';
+ pavr_s4_s5_elpm_pm_rq <= '0';
+ pavr_s5_elpm_pm_rq <= '0';
+ pavr_s4_z_pm_rq <= '0';
+ pavr_s4_zeind_pm_rq <= '0';
+ pavr_s4_k22abs_pm_rq <= '0';
+ pavr_s4_k12rel_pm_rq <= '0';
+ pavr_s4_k22int_pm_rq <= '0';
+ pavr_s4_s54_ret_pm_rq <= '0';
+ pavr_s5_s54_ret_pm_rq <= '0';
+ pavr_s51_s54_ret_pm_rq <= '0';
+ pavr_s52_s54_ret_pm_rq <= '0';
+ pavr_s53_s54_ret_pm_rq <= '0';
+ pavr_s54_ret_pm_rq <= '0';
+
+ pavr_s4_k6 <= int_to_std_logic_vector(0, pavr_s4_k6'length);
+ pavr_s4_k12 <= int_to_std_logic_vector(0, pavr_s4_k12'length);
+ pavr_s4_k22int <= int_to_std_logic_vector(0, pavr_s4_k22int'length);
+ pavr_s2_pc <= int_to_std_logic_vector(0, pavr_s2_pc'length);
+ pavr_s3_pc <= int_to_std_logic_vector(0, pavr_s3_pc'length);
+ pavr_s4_pc <= int_to_std_logic_vector(0, pavr_s4_pc'length);
+ pavr_s5_pc <= int_to_std_logic_vector(0, pavr_s5_pc'length);
+ pavr_s51_pc <= int_to_std_logic_vector(0, pavr_s51_pc'length);
+ pavr_s52_pc <= int_to_std_logic_vector(0, pavr_s52_pc'length);
+ pavr_s4_pcinc <= '0';
+ pavr_s4_s51s52s53_retpc_ld <= '0';
+ pavr_s5_s51s52s53_retpc_ld <= '0';
+ pavr_s51_retpchi8_ld <= '0';
+ pavr_s52_retpcmid8_ld <= '0';
+ pavr_s53_retpclo8_ld <= '0';
+ pavr_s52_retpchi8 <= int_to_std_logic_vector(0, pavr_s52_retpchi8'length);
+ pavr_s53_retpcmid8 <= int_to_std_logic_vector(0, pavr_s53_retpcmid8'length);
+ pavr_s54_retpclo8 <= int_to_std_logic_vector(0, pavr_s54_retpclo8'length);
+ pavr_s1_pc <= int_to_std_logic_vector(0, pavr_s1_pc'length); -- Note 1
+ pavr_s2_pmdo_valid <= '0';
+
+ pavr_s6_zlsb <= '0';
+
+ -- SFU requests-related
+ pavr_s4_stall_rq <= '0';
+ pavr_s4_s5_stall_rq <= '0';
+ pavr_s5_stall_rq <= '0';
+ pavr_s4_s6_stall_rq <= '0';
+ pavr_s5_s6_stall_rq <= '0';
+ pavr_s6_stall_rq <= '0';
+ pavr_s4_flush_s2_rq <= '0';
+ pavr_s4_ret_flush_s2_rq <= '0';
+ pavr_s5_ret_flush_s2_rq <= '0';
+ pavr_s51_ret_flush_s2_rq <= '0';
+ pavr_s52_ret_flush_s2_rq <= '0';
+ pavr_s53_ret_flush_s2_rq <= '0';
+ pavr_s54_ret_flush_s2_rq <= '0';
+ pavr_s55_ret_flush_s2_rq <= '0';
+ pavr_s6_skip_rq <= '0';
+ pavr_s61_skip_rq <= '0';
+ pavr_s6_branch_rq <= '0';
+ pavr_s4_nop_rq <= '0';
+
+ pavr_s4_s5_skip_cond_sel <= int_to_std_logic_vector(0, pavr_s4_s5_skip_cond_sel'length);
+ pavr_s5_skip_cond_sel <= int_to_std_logic_vector(0, pavr_s5_skip_cond_sel'length);
+ pavr_s4_s6_skip_cond_sel <= '0';
+ pavr_s5_s6_skip_cond_sel <= '0';
+ pavr_s6_skip_cond_sel <= '0';
+ pavr_s4_s5_skip_en <= '0';
+ pavr_s5_skip_en <= '0';
+ pavr_s4_s6_skip_en <= '0';
+ pavr_s5_s6_skip_en <= '0';
+ pavr_s6_skip_en <= '0';
+ pavr_s4_s5_skip_bitrf_sel <= int_to_std_logic_vector(0, pavr_s4_s5_skip_bitrf_sel'length);
+ pavr_s5_skip_bitrf_sel <= int_to_std_logic_vector(0, pavr_s5_skip_bitrf_sel'length);
+ pavr_s4_s6_skip_bitiof_sel <= int_to_std_logic_vector(0, pavr_s4_s6_skip_bitiof_sel'length);
+ pavr_s5_s6_skip_bitiof_sel <= int_to_std_logic_vector(0, pavr_s5_s6_skip_bitiof_sel'length);
+ pavr_s6_skip_bitiof_sel <= int_to_std_logic_vector(0, pavr_s6_skip_bitiof_sel'length);
+
+ pavr_s4_s5_k7_branch_offset <= int_to_std_logic_vector(0, pavr_s4_s5_k7_branch_offset'length);
+ pavr_s5_k7_branch_offset <= int_to_std_logic_vector(0, pavr_s5_k7_branch_offset'length);
+ pavr_s6_branch_pc <= int_to_std_logic_vector(0, pavr_s6_branch_pc'length);
+ pavr_s4_s5_branch_cond_sel <= '0';
+ pavr_s5_branch_cond_sel <= '0';
+ pavr_s4_s5_branch_en <= '0';
+ pavr_s5_branch_en <= '0';
+ pavr_s4_s5_branch_bitsreg_sel <= int_to_std_logic_vector(0, pavr_s4_s5_branch_bitsreg_sel'length);
+ pavr_s5_branch_bitsreg_sel <= int_to_std_logic_vector(0, pavr_s5_branch_bitsreg_sel'length);
+
+ -- Others
+ pavr_nop_ack <= '0';
+ pavr_s3_instr <= int_to_std_logic_vector(0, pavr_s3_instr'length);
+ pavr_s4_instr32bits <= '0';
+ pavr_s4_disable_int <= '0';
+ pavr_s5_disable_int <= '0';
+ pavr_s51_disable_int <= '0';
+ pavr_s52_disable_int <= '0';
+
+ end if;
+ end if;
+ end process control_sync;
+
+
+
+
+
+
+
+
+ -- Intruction decoder ------------------------------------------------------
+ instr_decoder:
+ process(pavr_s3_rfrd1_addr,
+ pavr_s3_rfrd2_addr,
+ next_pavr_s4_s6_rfwr_addr1,
+ next_pavr_s4_s61_rfwr_addr2,
+ next_pavr_s4_s5_iof_opcode,
+ next_pavr_s4_s6_iof_opcode,
+ next_pavr_s4_s5s6_iof_addr,
+ next_pavr_s4_s5s6_iof_bitaddr,
+ next_pavr_s4_s5_alu_opcode,
+ next_pavr_s4_s5_alu_op2_sel,
+ next_pavr_s4_s5_k8,
+ next_pavr_s4_dacu_q,
+ next_pavr_s4_k6,
+ next_pavr_s4_k12,
+ next_pavr_s4_k22int,
+ next_pavr_s4_s5_skip_cond_sel,
+ next_pavr_s4_s5_skip_bitrf_sel,
+ next_pavr_s4_s6_skip_bitiof_sel,
+ next_pavr_s4_s5_k7_branch_offset,
+ next_pavr_s4_s5_branch_bitsreg_sel,
+ pavr_int_rq,
+ pavr_stall_s3,
+ pavr_flush_s3,
+ pavr_s4_instr32bits,
+ pavr_s3_instr,
+ next_pavr_s4_dacu_q,
+ pavr_int_vec
+ )
+ variable tmp2_1, tmp2_2, tmp2_3, tmp2_4, tmp2_5, tmp2_6, tmp2_7, tmp2_8, tmp2_9, tmp2_a, tmp2_b, tmp2_c: std_logic_vector(1 downto 0);
+ variable tmp3_1, tmp3_2: std_logic_vector(2 downto 0);
+ variable tmp4_1, tmp4_2, tmp4_3, tmp4_4, tmp4_5 : std_logic_vector(3 downto 0);
+ begin
+ -- Default wires to benign values.
+
+ -- RF read port 1-related
+ pavr_s3_rfrd1_rq <= '0';
+ pavr_s3_rfrd1_addr <= int_to_std_logic_vector(0, pavr_s3_rfrd1_addr'length);
+
+ -- RF read port 2-related
+ pavr_s3_rfrd2_rq <= '0';
+ pavr_s3_rfrd2_addr <= int_to_std_logic_vector(0, pavr_s3_rfrd2_addr'length);
+
+ -- RF write port-related
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '0';
+ next_pavr_s4_s61_aluouthi8_rfwr_rq <= '0';
+ next_pavr_s4_s6_iof_rfwr_rq <= '0';
+ next_pavr_s4_s6_dacu_rfwr_rq <= '0';
+ next_pavr_s4_s6_pm_rfwr_rq <= '0';
+
+ next_pavr_s4_s6_rfwr_addr1 <= int_to_std_logic_vector(0, next_pavr_s4_s6_rfwr_addr1'length);
+ next_pavr_s4_s61_rfwr_addr2 <= int_to_std_logic_vector(0, next_pavr_s4_s61_rfwr_addr2'length);
+
+ -- Pointer registers-related
+ next_pavr_s4_s5_ldstincrampx_xwr_rq <= '0';
+ next_pavr_s4_s5_ldstdecrampx_xwr_rq <= '0';
+
+ next_pavr_s4_s5_ldstincrampy_ywr_rq <= '0';
+ next_pavr_s4_s5_ldstdecrampy_ywr_rq <= '0';
+
+ next_pavr_s4_s5_ldstincrampz_zwr_rq <= '0';
+ next_pavr_s4_s5_ldstdecrampz_zwr_rq <= '0';
+ next_pavr_s4_s5_elpmincrampz_zwr_rq <= '0';
+ next_pavr_s4_s5_lpminc_zwr_rq <= '0';
+
+ -- BPU write, BPR0-related
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '0';
+ next_pavr_s4_s6_iof_bpr0wr_rq <= '0';
+ next_pavr_s4_s6_daculd_bpr0wr_rq <= '0';
+ next_pavr_s4_s6_pmdo_bpr0wr_rq <= '0';
+
+ -- BPU write, BPR1-related
+ next_pavr_s4_s5_dacux_bpr12wr_rq <= '0';
+ next_pavr_s4_s5_dacuy_bpr12wr_rq <= '0';
+ next_pavr_s4_s5_dacuz_bpr12wr_rq <= '0';
+ next_pavr_s4_s5_alu_bpr1wr_rq <= '0';
+
+ -- IOF port-related
+ next_pavr_s4_s5_iof_rq <= '0';
+ next_pavr_s4_s6_iof_rq <= '0';
+
+ next_pavr_s4_s5_iof_opcode <= int_to_std_logic_vector(0, next_pavr_s4_s5_iof_opcode'length);
+ next_pavr_s4_s6_iof_opcode <= int_to_std_logic_vector(0, next_pavr_s4_s6_iof_opcode'length);
+ next_pavr_s4_s5s6_iof_addr <= int_to_std_logic_vector(0, next_pavr_s4_s5s6_iof_addr'length);
+ next_pavr_s4_s5s6_iof_bitaddr <= int_to_std_logic_vector(0, next_pavr_s4_s5s6_iof_bitaddr'length);
+
+ -- SREG-related
+ next_pavr_s4_s5_alu_sregwr_rq <= '0';
+ next_pavr_s4_s5_clriflag_sregwr_rq <= '0';
+ next_pavr_s4_s5_setiflag_sregwr_rq <= '0';
+
+ -- SP-related
+ next_pavr_s4_s5_inc_spwr_rq <= '0';
+ next_pavr_s4_s5_dec_spwr_rq <= '0';
+ next_pavr_s4_s5s51s52_calldec_spwr_rq <= '0';
+ next_pavr_s4_s5s51_retinc_spwr_rq <= '0';
+
+ -- ALU-related
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(0, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= '0';
+ next_pavr_s4_s5_alu_op2_sel <= int_to_std_logic_vector(0, next_pavr_s4_s5_alu_op2_sel'length);
+ next_pavr_s4_s5_k8 <= int_to_std_logic_vector(0, next_pavr_s4_s5_k8'length);
+
+ -- DACU setup-related
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
+
+ -- DACU read-related
+ next_pavr_s4_s5_x_dacurd_rq <= '0';
+ next_pavr_s4_s5_y_dacurd_rq <= '0';
+ next_pavr_s4_s5_z_dacurd_rq <= '0';
+ next_pavr_s4_s5_sp_dacurd_rq <= '0';
+ next_pavr_s4_s5_k16_dacurd_rq <= '0';
+ next_pavr_s4_s5s51s52_pc_dacurd_rq <= '0';
+
+ -- DACU write-related
+ next_pavr_s4_s5_sp_dacuwr_rq <= '0';
+ next_pavr_s4_s5_k16_dacuwr_rq <= '0';
+ next_pavr_s4_s5_x_dacuwr_rq <= '0';
+ next_pavr_s4_s5_y_dacuwr_rq <= '0';
+ next_pavr_s4_s5_z_dacuwr_rq <= '0';
+ next_pavr_s4_s5s51s52_pc_dacuwr_rq <= '0';
+
+ -- DM-related
+
+ -- PM access-related
+ next_pavr_s4_s5_lpm_pm_rq <= '0';
+ next_pavr_s4_s5_elpm_pm_rq <= '0';
+ next_pavr_s4_z_pm_rq <= '0';
+ next_pavr_s4_zeind_pm_rq <= '0';
+ next_pavr_s4_k22abs_pm_rq <= '0';
+ next_pavr_s4_k12rel_pm_rq <= '0';
+ next_pavr_s4_k22int_pm_rq <= '0';
+ next_pavr_s4_s54_ret_pm_rq <= '0';
+
+ next_pavr_s4_k6 <= int_to_std_logic_vector(0, next_pavr_s4_k6'length);
+ next_pavr_s4_k12 <= int_to_std_logic_vector(0, next_pavr_s4_k12'length);
+ next_pavr_s4_k22int <= int_to_std_logic_vector(0, next_pavr_s4_k22int'length);
+ next_pavr_s4_s51s52s53_retpc_ld <= '0';
+ next_pavr_s4_pcinc <= '0';
+
+ -- SFU requests-related
+ pavr_s3_stall_rq <= '0';
+ next_pavr_s4_stall_rq <= '0';
+ next_pavr_s4_s5_stall_rq <= '0';
+ next_pavr_s4_s6_stall_rq <= '0';
+ pavr_s3_flush_s2_rq <= '0';
+ next_pavr_s4_flush_s2_rq <= '0';
+ next_pavr_s4_ret_flush_s2_rq <= '0';
+ next_pavr_s4_nop_rq <= '0';
+
+ next_pavr_s4_s5_skip_cond_sel <= int_to_std_logic_vector(0, next_pavr_s4_s5_skip_cond_sel'length);
+ next_pavr_s4_s6_skip_cond_sel <= '0';
+ next_pavr_s4_s5_skip_en <= '0';
+ next_pavr_s4_s6_skip_en <= '0';
+ next_pavr_s4_s5_skip_bitrf_sel <= int_to_std_logic_vector(0, next_pavr_s4_s5_skip_bitrf_sel'length);
+ next_pavr_s4_s6_skip_bitiof_sel <= int_to_std_logic_vector(0, next_pavr_s4_s6_skip_bitiof_sel'length);
+
+ next_pavr_s4_s5_k7_branch_offset <= int_to_std_logic_vector(0, next_pavr_s4_s5_k7_branch_offset'length);
+ next_pavr_s4_s5_branch_cond_sel <= '0';
+ next_pavr_s4_s5_branch_en <= '0';
+ next_pavr_s4_s5_branch_bitsreg_sel <= int_to_std_logic_vector(0, next_pavr_s4_s5_branch_bitsreg_sel'length);
+
+ -- Others
+ next_pavr_s4_disable_int <= '0';
+ next_pavr_s4_instr32bits <= '0';
+
+ tmp2_1 := int_to_std_logic_vector(0, tmp2_1'length);
+ tmp2_2 := int_to_std_logic_vector(0, tmp2_2'length);
+ tmp2_3 := int_to_std_logic_vector(0, tmp2_3'length);
+ tmp2_4 := int_to_std_logic_vector(0, tmp2_4'length);
+ tmp2_5 := int_to_std_logic_vector(0, tmp2_5'length);
+ tmp2_6 := int_to_std_logic_vector(0, tmp2_6'length);
+ tmp2_7 := int_to_std_logic_vector(0, tmp2_7'length);
+ tmp2_8 := int_to_std_logic_vector(0, tmp2_8'length);
+ tmp2_9 := int_to_std_logic_vector(0, tmp2_9'length);
+ tmp2_a := int_to_std_logic_vector(0, tmp2_a'length);
+ tmp2_b := int_to_std_logic_vector(0, tmp2_b'length);
+ tmp2_c := int_to_std_logic_vector(0, tmp2_c'length);
+
+ tmp3_1 := int_to_std_logic_vector(0, tmp3_1'length);
+ tmp3_2 := int_to_std_logic_vector(0, tmp3_2'length);
+
+ tmp4_1 := int_to_std_logic_vector(0, tmp4_1'length);
+ tmp4_2 := int_to_std_logic_vector(0, tmp4_2'length);
+ tmp4_3 := int_to_std_logic_vector(0, tmp4_3'length);
+ tmp4_4 := int_to_std_logic_vector(0, tmp4_4'length);
+ tmp4_5 := int_to_std_logic_vector(0, tmp4_5'length);
+
+ -- Pipeline stage s3
+ -- Instruction decoder
+ if pavr_int_rq='0' then
+ if pavr_stall_s3='0' and pavr_flush_s3='0' and pavr_s4_instr32bits='0' then
+ tmp3_1 := pavr_s3_instr(15 downto 14)&pavr_s3_instr(12);
+ case tmp3_1 is
+ when "000" =>
+ if pavr_s3_instr(13)='0' then
+ tmp2_1 := pavr_s3_instr(11 downto 10);
+ case tmp2_1 is
+ when "00" =>
+ tmp2_2 := pavr_s3_instr(9 downto 8);
+ case tmp2_2 is
+ when "01" =>
+ -- MOVW Rd+1:Rd, Rr+1:Rr (Move word)
+ pavr_s3_rfrd1_rq <= '1'; -- Request Register File (RF) read port 1 access, for reading operand 1.
+ pavr_s3_rfrd2_rq <= '1'; -- Request RF read port 2 access, for reading operand 2.
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(3 downto 0)&'0'; -- Address of operand 1 in the RF.
+ pavr_s3_rfrd2_addr <= pavr_s3_instr(3 downto 0)&'1'; -- Address of operand 2 in the RF.
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_op1, next_pavr_s4_s5_alu_opcode'length); -- ALU opcode
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_op1bpu; -- Select the high byte of operand 1 from RF - read port 1, via Bypass Unit.
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1'; -- Request Bypass Unit, bypass register 1 (bpr1) write access.
+ next_pavr_s4_s5_alu_bpr1wr_rq <= '1'; -- Request Bypass Unit, bypass register 2 (bpr2) write access.
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(7 downto 4)&'0'; -- Write-back address. 2 successive writes are needed here.
+ next_pavr_s4_s61_rfwr_addr2 <= pavr_s3_instr(7 downto 4)&'1';
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1'; -- Request RF write port access for writing the result.
+ next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
+ next_pavr_s4_s6_stall_rq <= '1'; -- In s6, request pipeline stall and s5 flush, to `steal' RF write access from next instruction.
+ when "10" =>
+ -- MULS Rd, Rr (Multiply unsigned)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= '1'&pavr_s3_instr(7 downto 4); -- Only registers 16...31 can be used.
+ pavr_s3_rfrd2_addr <= '1'&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_muls8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= "00000"; -- Write result in R1:R0.
+ next_pavr_s4_s61_rfwr_addr2 <= "00001";
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
+ next_pavr_s4_s6_stall_rq <= '1';
+ when "11" =>
+ tmp2_3 := pavr_s3_instr(7)&pavr_s3_instr(3);
+ case tmp2_3 is
+ when "00" =>
+ -- MULSU Rd, Rr (Multiply signed with unsigned)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= "10"&pavr_s3_instr(6 downto 4);
+ pavr_s3_rfrd2_addr <= "10"&pavr_s3_instr(2 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_mulsu8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= "00000";
+ next_pavr_s4_s61_rfwr_addr2 <= "00001";
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
+ next_pavr_s4_s6_stall_rq <= '1';
+ when "01" =>
+ -- FMUL Rd, Rr (Fractional multiply unsigned)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= "10"&pavr_s3_instr(6 downto 4);
+ pavr_s3_rfrd2_addr <= "10"&pavr_s3_instr(2 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_fmul8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= "00000";
+ next_pavr_s4_s61_rfwr_addr2 <= "00001";
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
+ next_pavr_s4_s6_stall_rq <= '1';
+ when "10" =>
+ -- FMULS Rd, Rr (Fractional multiply signed)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= "10"&pavr_s3_instr(6 downto 4);
+ pavr_s3_rfrd2_addr <= "10"&pavr_s3_instr(2 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_fmuls8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= "00000";
+ next_pavr_s4_s61_rfwr_addr2 <= "00001";
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
+ next_pavr_s4_s6_stall_rq <= '1';
+ when others =>
+ -- FMULSU Rd, Rr (Fractional multiply signed with unsigned)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= "10"&pavr_s3_instr(6 downto 4);
+ pavr_s3_rfrd2_addr <= "10"&pavr_s3_instr(2 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_fmulsu8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= "00000";
+ next_pavr_s4_s61_rfwr_addr2 <= "00001";
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
+ next_pavr_s4_s6_stall_rq <= '1';
+ end case;
+ when others =>
+ -- NOP (0000_0000_0000_0000) or invalid opcode (0000_0000_xxxx_xxxx, with xxxx_xxxx != 0000_0000)
+ null;
+ end case;
+ when "01" =>
+ -- CPC Rd, Rr (Compare with carry)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sbc8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ when "10" =>
+ -- SBC Rd, Rr (Substract with carry)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sbc8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ when others =>
+ -- ADD Rd, Rr
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_add8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ end case;
+ else
+ tmp2_4 := pavr_s3_instr(11 downto 10);
+ case tmp2_4 is
+ when "00" =>
+ -- AND Rd, Rr
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_and8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ when "01" =>
+ -- EOR Rd, Rr (Logical or exclusive)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_eor8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ when "10" =>
+ -- OR Rd, Rr
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_or8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ when others =>
+ -- MOV Rd, Rr
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_op1, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ end case;
+ end if;
+ when "001" =>
+ if pavr_s3_instr(13)='0' then
+ tmp2_5 := pavr_s3_instr(11 downto 10);
+ case tmp2_5 is
+ when "00" =>
+ -- CPSE Rd, Rr (Compare and skip if equal)
+ pavr_s3_rfrd1_rq <= '1'; -- Read two operands from RF, substract them, and use the zero aluout_flag as skip condition to be checked.
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sub8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_skip_cond_sel <= pavr_s5_skip_cond_sel_zflag;
+ next_pavr_s4_s5_skip_en <= '1'; -- Enable skip request in s5. If skip condition true, then: 1) stall (s6) and flush s5, 2) flush s3, 3) if instr32bits then flush s2
+ pavr_s3_stall_rq <= '1';
+ --next_pavr_s4_s5_stall_rq <= '1'; -- Request stall in s5. That's to have next two instruction words in s2 and s3, and be able to easely skip (flush) any or both of them.
+ when "01" =>
+ -- CP Rd, Rr (Compare)
+ pavr_s3_rfrd1_rq <= '1'; -- Set up the same signals as for CPC.
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sub8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ when "10" =>
+ -- SUB Rd, Rr
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sub8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ when others =>
+ -- ADC Rd, Rr (Add with carry)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_adc8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ end case;
+ else
+ -- CPI Rd, k8 (Compare with immediate)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= '1'&pavr_s3_instr(7 downto 4); -- Only registers 16...31 can be used.
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sub8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
+ next_pavr_s4_s5_k8 <= pavr_s3_instr(11 downto 8)&pavr_s3_instr(3 downto 0); -- Load 8 bit constant from instruction opcode.
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ end if;
+ when "010" =>
+ if pavr_s3_instr(13)='0' then
+ -- SBCI Rd, k8 (Substract immediate with carry)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= '1'&pavr_s3_instr(7 downto 4); -- Only registers 16...31 can be used.
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sbc8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
+ next_pavr_s4_s5_k8 <= pavr_s3_instr(11 downto 8)&pavr_s3_instr(3 downto 0); -- Load 8 bit constant from instruction opcode.
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= '1'&pavr_s3_instr(7 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ else
+ -- ORI Rd, k8 (Logical or with immediate)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= '1'&pavr_s3_instr(7 downto 4); -- Only registers 16...31 can be used.
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_or8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
+ next_pavr_s4_s5_k8 <= pavr_s3_instr(11 downto 8)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= '1'&pavr_s3_instr(7 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ end if;
+ when "011" =>
+ if pavr_s3_instr(13)='0' then
+ -- SUBI Rd, k8 (Substract immediate)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= '1'&pavr_s3_instr(7 downto 4); -- Only registers 16...31 can be used.
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sub8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
+ next_pavr_s4_s5_k8 <= pavr_s3_instr(11 downto 8)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= '1'&pavr_s3_instr(7 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ else
+ -- ANDI Rd, k8 (Logical or with immediate)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= '1'&pavr_s3_instr(7 downto 4); -- Only registers 16...31 can be used.
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_and8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
+ next_pavr_s4_s5_k8 <= pavr_s3_instr(11 downto 8)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= '1'&pavr_s3_instr(7 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ end if;
+ when "100" =>
+ tmp2_6 := pavr_s3_instr(9)&pavr_s3_instr(3);
+ case tmp2_6 is
+ when "00" =>
+ -- LDD Rd, Z+q (Load indirect with displacement, via Z register)
+ next_pavr_s4_dacu_q <= "00"&pavr_s3_instr(13)&pavr_s3_instr(11 downto 10)&pavr_s3_instr(2 downto 0); -- Load DACU displacement constant from instruction opcode.
+ next_pavr_s4_s5_z_dacurd_rq <= '1'; -- Request DACU read access in s5.
+ next_pavr_s4_s6_dacu_rfwr_rq <= '1'; -- Request RF write access.
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4); -- Write-back address.
+ next_pavr_s4_s6_daculd_bpr0wr_rq <= '1'; -- Request BPR0 write access.
+ next_pavr_s4_s5_stall_rq <= '1'; -- Stall the pipeline in s5, to `steal' RF read access from s3. A nop will be inserted before the load.
+ when "01" =>
+ -- LDD Rd, Y+q (Load indirect with displacement, via Y register)
+ next_pavr_s4_dacu_q <= "00"&pavr_s3_instr(13)&pavr_s3_instr(11 downto 10)&pavr_s3_instr(2 downto 0);
+ next_pavr_s4_s5_y_dacurd_rq <= '1';
+ next_pavr_s4_s6_dacu_rfwr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_stall_rq <= '1';
+ when "10" =>
+ -- STD Z+q, Rr (Store indirect with displacement, via Z register)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_dacu_q <= "00"&pavr_s3_instr(13)&pavr_s3_instr(11 downto 10)&pavr_s3_instr(2 downto 0);
+ next_pavr_s4_s5_z_dacuwr_rq <= '1';
+ next_pavr_s4_nop_rq <= '1';
+ when others =>
+ -- STD Y+q, Rr (Store indirect with displacement, via Y register)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_dacu_q <= "00"&pavr_s3_instr(13)&pavr_s3_instr(11 downto 10)&pavr_s3_instr(2 downto 0);
+ next_pavr_s4_s5_y_dacuwr_rq <= '1';
+ next_pavr_s4_nop_rq <= '1';
+ end case;
+ when "101" =>
+ if pavr_s3_instr(13)='0' then
+ tmp2_7 := pavr_s3_instr(11 downto 10);
+ case tmp2_7 is
+ when "11" =>
+ -- MUL Rd, Rr (Multiply unsigned)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ pavr_s3_rfrd2_addr <= pavr_s3_instr(9)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_mul8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_op2bpu;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= "00000"; -- Write result in R1:R0.
+ next_pavr_s4_s61_rfwr_addr2 <= "00001";
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
+ next_pavr_s4_s6_stall_rq <= '1'; -- Request stall in stage 6.
+ when "10" =>
+ tmp2_8 := pavr_s3_instr(9 downto 8);
+ case tmp2_8 is
+ when "00" =>
+ -- CBI A, b (Clear bit in IO register)
+ next_pavr_s4_s5_iof_rq <= '1'; -- Request IO file access in s5.
+ next_pavr_s4_s6_iof_rq <= '1'; -- Request IO file access in s6
+ next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_rdbyte; -- Set IOF opcode in s5 to `read byte'.
+ next_pavr_s4_s6_iof_opcode <= pavr_iof_opcode_clrbit; -- Set IOF opcode in s6 to `clear bit'.
+ next_pavr_s4_s5s6_iof_addr <= '0'&pavr_s3_instr(7 downto 3); -- Set IOF address (s5, s6). Only lower 32 bytes of IOF can be used.
+ next_pavr_s4_s5s6_iof_bitaddr <= pavr_s3_instr(2 downto 0); -- Set IOF bit address (s6).
+ next_pavr_s4_s5_stall_rq <= '1'; -- Request stall in s5.
+ when "01" =>
+ -- SBIC A, b (Skip if bit in IO register is cleared)
+ next_pavr_s4_s5_iof_rq <= '1'; -- Request IO file access in s5.
+ next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_rdbyte;
+ next_pavr_s4_s5s6_iof_addr <= '0'&pavr_s3_instr(7 downto 3); -- Only lower 32 bytes of IOF can be used.
+ next_pavr_s4_s6_skip_bitiof_sel <= pavr_s3_instr(2 downto 0);
+ next_pavr_s4_s6_skip_cond_sel <= pavr_s6_skip_cond_sel_notbitiof;
+ next_pavr_s4_s6_skip_en <= '1'; -- Enable skip request in s61. If skip condition true, then: 1) stall rq (s61) and flush s6, 2) flush s3, 3) if instr32bits then flush s2
+ pavr_s3_stall_rq <= '1';
+ next_pavr_s4_s5_stall_rq <= '1';
+ --next_pavr_s4_s6_stall_rq <= '1';
+ when "10" =>
+ -- SBI A, b (Set bit in IO register)
+ next_pavr_s4_s5_iof_rq <= '1';
+ next_pavr_s4_s6_iof_rq <= '1';
+ next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_rdbyte;
+ next_pavr_s4_s6_iof_opcode <= pavr_iof_opcode_setbit;
+ next_pavr_s4_s5s6_iof_addr <= '0'&pavr_s3_instr(7 downto 3);
+ next_pavr_s4_s5s6_iof_bitaddr <= pavr_s3_instr(2 downto 0);
+ next_pavr_s4_s5_stall_rq <= '1';
+ when others =>
+ -- SBIS A, b (Skip if bit in IO register is set)
+ next_pavr_s4_s5_iof_rq <= '1'; -- Request IO file access in s5.
+ next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_rdbyte;
+ next_pavr_s4_s5s6_iof_addr <= '0'&pavr_s3_instr(7 downto 3); -- Only lower 32 bytes of IOF can be used.
+ next_pavr_s4_s6_skip_bitiof_sel <= pavr_s3_instr(2 downto 0);
+ next_pavr_s4_s6_skip_cond_sel <= pavr_s6_skip_cond_sel_bitiof;
+ next_pavr_s4_s6_skip_en <= '1'; -- Enable skip request in s61. If skip condition true, then: 1) stall rq (s61) and flush s6, 2) flush s3, 3) if instr32bits then flush s2
+ pavr_s3_stall_rq <= '1';
+ next_pavr_s4_s5_stall_rq <= '1';
+ --next_pavr_s4_s6_stall_rq <= '1';
+ end case;
+ when "01" =>
+ if pavr_s3_instr(9)='1' then
+ if pavr_s3_instr(8)='0' then
+ -- ADIW Rd+1:Rd, k6 (Add immediate to word)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= "11"&pavr_s3_instr(5 downto 4)&'0';
+ pavr_s3_rfrd2_addr <= "11"&pavr_s3_instr(5 downto 4)&'1';
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_add16, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_op1bpu;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
+ next_pavr_s4_s5_k8 <= "00"&pavr_s3_instr(7 downto 6)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= "11"&pavr_s3_instr(5 downto 4)&'0';
+ next_pavr_s4_s61_rfwr_addr2 <= "11"&pavr_s3_instr(5 downto 4)&'1';
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
+ next_pavr_s4_s6_stall_rq <= '1'; -- Request stall in stage 6.
+ else
+ -- SBIW Rd+1:Rd, k6 (Substract immediate from word)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd2_rq <= '1';
+ pavr_s3_rfrd1_addr <= "11"&pavr_s3_instr(5 downto 4)&'0';
+ pavr_s3_rfrd2_addr <= "11"&pavr_s3_instr(5 downto 4)&'1';
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_sub16, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_op1bpu;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
+ next_pavr_s4_s5_k8 <= "00"&pavr_s3_instr(7 downto 6)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr1wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= "11"&pavr_s3_instr(5 downto 4)&'0';
+ next_pavr_s4_s61_rfwr_addr2 <= "11"&pavr_s3_instr(5 downto 4)&'1';
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ next_pavr_s4_s61_aluouthi8_rfwr_rq <= '1';
+ next_pavr_s4_s6_stall_rq <= '1';
+ end if;
+ else
+ tmp3_2 := pavr_s3_instr(3 downto 1);
+ case tmp3_2 is
+ when "000" =>
+ if pavr_s3_instr(0)='0' then
+ -- COM Rd (One's complement)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_com8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ else
+ -- NEG Rd (Two's complement)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_neg8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ end if;
+ when "001" =>
+ if pavr_s3_instr(0)='0' then
+ -- SWAP Rd (Swap nibbles)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_swap8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ else
+ -- INC Rd
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_inc8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_1;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ end if;
+ when "010" =>
+ if pavr_s3_instr(0)='0' then
+ -- Invalid opcode (1001_010x_xxxx_0100)
+ null;
+ else
+ -- ASR Rd (Arithmetic shift right)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_asr8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ end if;
+ when "011" =>
+ if pavr_s3_instr(0)='0' then
+ -- LSR Rd (Logical shift right)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_lsr8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ else
+ -- ROR Rd (Rotate right through carry)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_ror8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ end if;
+ when "100" =>
+ tmp2_9 := pavr_s3_instr(8)&pavr_s3_instr(0);
+ case tmp2_9 is
+ when "00" =>
+ if pavr_s3_instr(7)='0' then
+ -- BSET s (Bit set in SREG (Status Register))
+ next_pavr_s4_s5_iof_rq <= '1'; -- Request IO file access in s5.
+ next_pavr_s4_s6_iof_rq <= '1'; -- Request IO file access in s6
+ next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_rdbyte; -- Set IOF opcode in s5 to `read byte'.
+ next_pavr_s4_s6_iof_opcode <= pavr_iof_opcode_setbit; -- Set IOF opcode in s6 to `set bit'.
+ next_pavr_s4_s5s6_iof_addr <= int_to_std_logic_vector(pavr_sreg_addr, next_pavr_s4_s5s6_iof_addr'length); -- Set IOF address to SREG's address (s5, s6).
+ next_pavr_s4_s5s6_iof_bitaddr <= pavr_s3_instr(6 downto 4); -- Set IOF bit address (s6).
+ next_pavr_s4_s5_stall_rq <= '1'; -- Request stall in s5.
+ else
+ -- BCLR s (Bit clear in SREG)
+ next_pavr_s4_s5_iof_rq <= '1';
+ next_pavr_s4_s6_iof_rq <= '1';
+ next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_rdbyte;
+ next_pavr_s4_s6_iof_opcode <= pavr_iof_opcode_clrbit;
+ next_pavr_s4_s5s6_iof_addr <= int_to_std_logic_vector(pavr_sreg_addr, next_pavr_s4_s5s6_iof_addr'length);
+ next_pavr_s4_s5s6_iof_bitaddr <= pavr_s3_instr(6 downto 4);
+ next_pavr_s4_s5_stall_rq <= '1';
+ end if;
+ when "01" =>
+ tmp4_1 := pavr_s3_instr(7 downto 4);
+ case tmp4_1 is
+ when "0000" =>
+ -- IJMP (Indirect jump (16 bit absolute address), via Z register)
+ next_pavr_s4_z_pm_rq <= '1'; -- Request PM access. Also, update PC. Next PC will be the present Z register.
+ pavr_s3_flush_s2_rq <= '1'; -- Request flush s2 during s3 (next instruction is out of normal instruction flow).
+ next_pavr_s4_flush_s2_rq <= '1'; -- Request flush s2 during s4 (next 2 instructions are out of normal instruction flow).
+ next_pavr_s4_nop_rq <= '1'; -- Insert a nop *after* the instruction wavefront.
+ when "0001" =>
+ -- EIJMP (Extended indirect jump (24 bit absolute address), via Z and EIND registers)
+ next_pavr_s4_zeind_pm_rq <= '1'; -- Request PM access. Also, update PC. Next PC will be the present Z:EIND registers.
+ pavr_s3_flush_s2_rq <= '1'; -- Request flush s2 during s3 (next instruction is out of normal instruction flow).
+ next_pavr_s4_flush_s2_rq <= '1'; -- Request flush s2 during s4 (next 2 instructions are out of normal instruction flow).
+ next_pavr_s4_nop_rq <= '1'; -- Insert a nop *after* the instruction wavefront.
+ when others =>
+ -- Invalid opcode (1001_0100_xxxx_1001, with xxxx != 0000, 0001)
+ null;
+ end case;
+ when "10" =>
+ tmp4_2 := pavr_s3_instr(7 downto 4);
+ case tmp4_2 is
+ when "0000" =>
+ -- RET (Return from subroutine)
+ next_pavr_s4_s51s52s53_retpc_ld <= '1'; -- Load return PC from stack in stages s51, s52 and s53.
+ next_pavr_s4_s5s51s52_pc_dacurd_rq <= '1'; -- Request DACU read for reading PC from stack, in stages s5, s51 and s52.
+ next_pavr_s4_s54_ret_pm_rq <= '1'; -- Request PM access. Also, update PC.
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(1, next_pavr_s4_dacu_q'length); -- Simulate pre-increment SP with a `1' initial displacement and post-increment.
+ next_pavr_s4_s5s51_retinc_spwr_rq <= '1'; -- Request SP write access. SP will be (post-) incremented.
+ pavr_s3_flush_s2_rq <= '1'; -- Request flush s2 in s3.
+ next_pavr_s4_ret_flush_s2_rq <= '1'; -- Many, many flushes here (7 flushes; they shift from one stage into another, from s4 till s55).
+ --next_pavr_s4_stall_rq <= '1';
+ when "0001" =>
+ -- RETI (Return from interrupt)
+ next_pavr_s4_s51s52s53_retpc_ld <= '1';
+ next_pavr_s4_s5s51s52_pc_dacurd_rq <= '1';
+ next_pavr_s4_s54_ret_pm_rq <= '1';
+ next_pavr_s4_s5_setiflag_sregwr_rq <= '1'; -- Request SREG write access, to set I (global interrupt enable) flag.
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(1, next_pavr_s4_dacu_q'length);
+ next_pavr_s4_s5s51_retinc_spwr_rq <= '1';
+ pavr_s3_flush_s2_rq <= '1';
+ next_pavr_s4_ret_flush_s2_rq <= '1';
+ --next_pavr_s4_stall_rq <= '1';
+ when "1000" =>
+ -- SLEEP (Low power mode, not implemented)
+ null;
+ when "1001" =>
+ -- BREAK (not implemented)
+ null;
+ when "1010" =>
+ -- WDR (Reset watchdog timer, not implemented)
+ null;
+ when "1100" =>
+ -- LPM (Load indirect Program Memory into R0, via Z register)
+ next_pavr_s4_s5_lpm_pm_rq <= '1'; -- Request Program Memory (read; PM is read-only) access. Indirectly read PM via Z register.
+ next_pavr_s4_s6_pm_rfwr_rq <= '1'; -- Request RF write access. Write PM data out into the RF.
+ next_pavr_s4_s6_rfwr_addr1 <= "00000"; -- Write-back address.
+ next_pavr_s4_s6_pmdo_bpr0wr_rq <= '1'; -- Request BPU write access.
+ next_pavr_s4_s5_stall_rq <= '1';
+ when "1101" =>
+ -- ELPM (Load extended Program Memory into R0, via Z and RAMPZ registers)
+ next_pavr_s4_s5_elpm_pm_rq <= '1'; -- Request Program Memory (read; PM is read-only) access. Indirectly read PM via Z and RAMPZ registers.
+ next_pavr_s4_s6_pm_rfwr_rq <= '1'; -- Request RF write access. Write PM data out into the RF.
+ next_pavr_s4_s6_rfwr_addr1 <= "00000"; -- Write-back address.
+ next_pavr_s4_s6_pmdo_bpr0wr_rq <= '1'; -- Request BPU write access.
+ next_pavr_s4_s5_stall_rq <= '1';
+ when "1110" =>
+ -- SPM (Store Program Memory, not implemented)
+ null;
+ when others =>
+ -- Invalid opcode (1001_0101_xxxx_1000, with xxxx != 0000, 0001, 1000, 1001, 1010, 1100, 1101, 1110)
+ null;
+ end case;
+ when others =>
+ tmp4_3 := pavr_s3_instr(7 downto 4);
+ case tmp4_3 is
+ when "0000" =>
+ -- ICALL (Indirect call (16 bit absolute address), via Z register)
+ pavr_s3_flush_s2_rq <= '1'; -- Flush the instructions that were already fetched but don't follow the normal instruction flow.
+ next_pavr_s4_flush_s2_rq <= '1';
+ next_pavr_s4_nop_rq <= '1'; -- Insert a nop *after* the instruction wavefront.
+ next_pavr_s4_z_pm_rq <= '1'; -- Request PM access. Also, update PC.
+ next_pavr_s4_s5s51s52_pc_dacuwr_rq <= '1'; -- Request DACU write access in s5, s51 and s52.
+ next_pavr_s4_s5s51s52_calldec_spwr_rq <= '1'; -- Decrement SP.
+ --next_pavr_s4_stall_rq <= '1';
+ when "0001" =>
+ -- EICALL (Extended indirect call (24 bit absolute address), via Z and EIND registers)
+ pavr_s3_flush_s2_rq <= '1'; -- Flush the instructions that were already fetched but don't follow the normal instruction flow.
+ next_pavr_s4_flush_s2_rq <= '1';
+ next_pavr_s4_nop_rq <= '1'; -- Insert a nop *after* the instruction wavefront.
+ next_pavr_s4_zeind_pm_rq <= '1'; -- Request PM access. Also, update PC.
+ next_pavr_s4_s5s51s52_pc_dacuwr_rq <= '1'; -- Request DACU write access in s5, s51 and s52.
+ next_pavr_s4_s5s51s52_calldec_spwr_rq <= '1'; -- Decrement SP.
+ --next_pavr_s4_stall_rq <= '1';
+ when others =>
+ -- Invalid opcode (1001_0101_xxxx_1001, with xxxx != 0000, 0001)
+ null;
+ end case;
+ end case;
+ when "101" =>
+ if pavr_s3_instr(0)='0' then
+ -- DEC Rd
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_dec8, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_alu_op1_hi8_sel <= pavr_alu_op1_hi8_sel_zero;
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_minus1;
+ next_pavr_s4_s5_alu_sregwr_rq <= '1';
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ else
+ -- Invalid opcode (1001_010x_xxxx_1011)
+ null;
+ end if;
+ when "110" =>
+ -- JMP k16 (Long jump (22 bit absolute address); 32 bit instruction)
+ next_pavr_s4_instr32bits <= '1'; -- Signalize 32 bit instruction
+ next_pavr_s4_k6 <= pavr_s3_instr(8 downto 4)&pavr_s3_instr(0); -- Load lower 6 bits of the absolute jump address from instruction opcode.
+ next_pavr_s4_k22abs_pm_rq <= '1'; -- Request PM access. (***) Attention, this also updates the PC.
+ next_pavr_s4_flush_s2_rq <= '1'; -- Request flush s2 during s4 (next 2 instructions are out of normal instruction flow).
+ when others =>
+ -- CALL k16 (Long call (22 bit absolute address); 32 bit instruction)
+ next_pavr_s4_instr32bits <= '1'; -- Signalize 32 bit instruction
+ next_pavr_s4_pcinc <= '1'; -- Increment return address to take into account that CALL has 32 bits.
+ next_pavr_s4_flush_s2_rq <= '1';
+ next_pavr_s4_nop_rq <= '1'; -- Insert a nop *after* the instruction wavefront.
+ next_pavr_s4_k22abs_pm_rq <= '1'; -- Request PM access. Also, update PC.
+ next_pavr_s4_s5s51s52_pc_dacuwr_rq <= '1'; -- Request DACU write access in s5, s51 and s52.
+ next_pavr_s4_s5s51s52_calldec_spwr_rq <= '1'; -- Decrement SP.
+ --next_pavr_s4_stall_rq <= '1';
+ end case;
+ end if;
+ when others =>
+ if pavr_s3_instr(9)='0' then
+ tmp4_4 := pavr_s3_instr(3 downto 0);
+ case tmp4_4 is
+ when "1111" =>
+ -- POP Rd
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(1, next_pavr_s4_dacu_q'length); -- Simulate pre-increment with a `1' initial displacement and post-increment.
+ next_pavr_s4_s5_sp_dacurd_rq <= '1'; -- Request DACU read access. Read UM via SP.
+ next_pavr_s4_s6_dacu_rfwr_rq <= '1';
+ next_pavr_s4_s5_inc_spwr_rq <= '1'; -- Request SP write access. SP will be (post-)incremented.
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_stall_rq <= '1';
+ when "0000" =>
+ -- LDS Rd, k16 (Load direct from data space; 32 bit instruction)
+ next_pavr_s4_instr32bits <= '1'; -- Signalize that this instruction is 32 bits wide. Next word (16 bits) will be ignored by the instruction decoder (nop). It's a constant that will be extracted by s5.
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
+ next_pavr_s4_s5_k16_dacurd_rq <= '1'; -- Request DACU read access. Read from dedicated 16 bit instruction constant register (s4).
+ next_pavr_s4_s6_dacu_rfwr_rq <= '1'; -- Request RF write access.
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4); -- Write-back address.
+ next_pavr_s4_s6_daculd_bpr0wr_rq <= '1'; -- Request Bypass Unit (BPU) write access in s6.
+ next_pavr_s4_s5_stall_rq <= '1'; -- Stall the pipeline in s5, to `steal' RF read access from s3. A nop will be inserted after the load.
+ when "1100" =>
+ -- LD Rd, X (Load indirect via X register)
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length); -- Load Data Address Calculation Unit (DACU) displacement constant (q).
+ next_pavr_s4_s5_x_dacurd_rq <= '1'; -- Request DACU read access in s5. Indirectly read Unified Memory (UM) via X register.
+ next_pavr_s4_s6_dacu_rfwr_rq <= '1'; -- Request RF write access.
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4); -- Write-back address.
+ next_pavr_s4_s6_daculd_bpr0wr_rq <= '1'; -- Request Bypass Unit (BPU) write access in s6.
+ next_pavr_s4_s5_stall_rq <= '1'; -- Stall the pipeline in s5, to `steal' RF read access from s3. A nop will be inserted after the load.
+ when "1101" =>
+ -- LD Rd, X+ (Load indirect with post-increment via X register)
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
+ next_pavr_s4_s5_x_dacurd_rq <= '1';
+ next_pavr_s4_s5_ldstincrampx_xwr_rq <= '1'; -- Request X pointer write access. The X pointer will be (post-)incremented.
+ next_pavr_s4_s6_dacu_rfwr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_dacux_bpr12wr_rq <='1';
+ next_pavr_s4_s5_stall_rq <= '1';
+ when "1110" =>
+ -- LD Rd, -X (Load indirect with pre-decrement via X register)
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(-1, next_pavr_s4_dacu_q'length); -- Simulate pre-decrement with a `-1' initial displacement and post-decrement.
+ next_pavr_s4_s5_x_dacurd_rq <= '1';
+ next_pavr_s4_s5_ldstdecrampx_xwr_rq <= '1'; -- Request X pointer write access. The X pointer will be (post-)decremented.
+ next_pavr_s4_s6_dacu_rfwr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_dacux_bpr12wr_rq <='1';
+ next_pavr_s4_s5_stall_rq <= '1';
+ when "1001" =>
+ -- LD Rd, Y+ (Load indirect with post-increment via Y register)
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
+ next_pavr_s4_s5_y_dacurd_rq <= '1';
+ next_pavr_s4_s5_ldstincrampy_ywr_rq <= '1'; -- Request Y pointer write access. The Y pointer will be (post-)incremented.
+ next_pavr_s4_s6_dacu_rfwr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_dacuy_bpr12wr_rq <='1';
+ next_pavr_s4_s5_stall_rq <= '1';
+ when "1010" =>
+ -- LD Rd, -Y (Load indirect with pre-decrement via Y register)
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(-1, next_pavr_s4_dacu_q'length); -- Simulate pre-decrement with a `-1' initial displacement and post-decrement.
+ next_pavr_s4_s5_y_dacurd_rq <= '1';
+ next_pavr_s4_s5_ldstdecrampy_ywr_rq <= '1'; -- Request Y pointer write access. The Y pointer will be (post-)decremented.
+ next_pavr_s4_s6_dacu_rfwr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_dacuy_bpr12wr_rq <='1';
+ next_pavr_s4_s5_stall_rq <= '1';
+ when "0001" =>
+ -- LD Rd, Z+ (Load indirect with post-decrement via Z register)
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
+ next_pavr_s4_s5_z_dacurd_rq <= '1';
+ next_pavr_s4_s5_ldstincrampz_zwr_rq <= '1'; -- Request Z pointer write access. The Z pointer will be (post-)incremented.
+ next_pavr_s4_s6_dacu_rfwr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_dacuz_bpr12wr_rq <='1';
+ next_pavr_s4_s5_stall_rq <= '1';
+ when "0010" =>
+ -- LD Rd, -Z (Load indirect with pre-decrement via Z register)
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(-1, next_pavr_s4_dacu_q'length); -- Simulate pre-decrement with a `-1' initial displacement and post-decrement.
+ next_pavr_s4_s5_z_dacurd_rq <= '1';
+ next_pavr_s4_s5_ldstdecrampz_zwr_rq <= '1'; -- Request Z pointer write access. The Z pointer will be (post-)decremented.
+ next_pavr_s4_s6_dacu_rfwr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s6_daculd_bpr0wr_rq <= '1';
+ next_pavr_s4_s5_dacuy_bpr12wr_rq <='1';
+ next_pavr_s4_s5_stall_rq <= '1';
+ when "0100" =>
+ -- LPM Rd, Z (Load indirect Program Memory)
+ next_pavr_s4_s5_lpm_pm_rq <= '1'; -- Request Program Memory (read; PM is read-only) access. Indirectly read PM via Z register.
+ next_pavr_s4_s6_pm_rfwr_rq <= '1'; -- Request RF write access. Write PM data out into the RF.
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4); -- Write-back address.
+ next_pavr_s4_s6_pmdo_bpr0wr_rq <= '1'; -- Request BPU write access.
+ next_pavr_s4_s5_stall_rq <= '1';
+ when "0101" =>
+ -- LPM Rd, Z+ (Load indirect Program Memory with post-increment)
+ next_pavr_s4_s5_lpm_pm_rq <= '1'; -- Request Program Memory (read; PM is read-only) access. Indirectly read PM via Z register.
+ next_pavr_s4_s5_lpminc_zwr_rq <= '1'; -- Request Z pointer write access. Z will be (post-)incremented.
+ next_pavr_s4_s6_pm_rfwr_rq <= '1'; -- Request RF write access. Write PM data out into the RF.
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4); -- Write-back address.
+ next_pavr_s4_s6_pmdo_bpr0wr_rq <= '1'; -- Request BPU write access.
+ next_pavr_s4_s5_stall_rq <= '1';
+ when "0110" =>
+ -- ELPM Rd, Z (Load extended indirect Program Memory)
+ next_pavr_s4_s5_elpm_pm_rq <= '1'; -- Request Program Memory (read; PM is read-only) access. Indirectly read PM via Z and RAMPZ registers.
+ next_pavr_s4_s6_pm_rfwr_rq <= '1'; -- Request RF write access. Write PM data out into the RF.
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4); -- Write-back address.
+ next_pavr_s4_s6_pmdo_bpr0wr_rq <= '1'; -- Request BPU write access.
+ next_pavr_s4_s5_stall_rq <= '1';
+ when "0111" =>
+ -- ELPM Rd, Z+ (Load extended indirect Program Memory with post-increment)
+ next_pavr_s4_s5_elpm_pm_rq <= '1'; -- Request Program Memory (read; PM is read-only) access. Indirectly read PM via Z and RAMPZ registers.
+ next_pavr_s4_s5_elpmincrampz_zwr_rq <= '1'; -- Request Z pointer write access. RAMPZ:Z will be (post-)incremented.
+ next_pavr_s4_s6_pm_rfwr_rq <= '1'; -- Request RF write access. Write PM data out into the RF.
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4); -- Write-back address.
+ next_pavr_s4_s6_pmdo_bpr0wr_rq <= '1'; -- Request BPU write access.
+ next_pavr_s4_s5_stall_rq <= '1';
+ when others =>
+ -- Invalid opcode (1001_000x_xxxx_yyyy, with yyyy = 0011, 1000, 1011)
+ null;
+ end case;
+ else
+ tmp4_5 := pavr_s3_instr(3 downto 0);
+ case tmp4_5 is
+ when "1111" =>
+ -- PUSH Rr
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
+ next_pavr_s4_s5_sp_dacuwr_rq <= '1'; -- Request DACU write access, at address given by Stack Pointer (SP).
+ next_pavr_s4_s5_dec_spwr_rq <= '1'; -- Request SP write access. SP will be (post-)decremented.
+ next_pavr_s4_s5_stall_rq <= '1'; -- Request stall in s5.
+ next_pavr_s4_nop_rq <= '1'; -- Request nop after the instrction wavefront.
+ when "0000" =>
+ -- STS k16, Rr (Store direct to data space; 32 bit instruction)
+ next_pavr_s4_instr32bits <= '1'; -- Signalize 32 bit instruction.
+ pavr_s3_rfrd1_rq <= '1'; -- Request RF read port 1 access.
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4); -- Address of RF operand to be read.
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
+ next_pavr_s4_s5_k16_dacuwr_rq <= '1'; -- Request DACU write access. Write UM at address given by 16 bit instruction constant (pavr_s5_k16).
+ next_pavr_s4_nop_rq <= '1'; -- Request a nop *after* the instruction wavefront. Do that for the store to wait its turn for RF write port access.
+ when "1100" =>
+ -- ST X, Rr (Store indirect via X register)
+ pavr_s3_rfrd1_rq <= '1'; -- Request RF read port 1 access.
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4); -- Address of RF operand to be read.
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
+ next_pavr_s4_s5_x_dacuwr_rq <= '1';
+ next_pavr_s4_nop_rq <= '1'; -- Request a nop *after* the instruction wavefront. Do that for the store to wait its turn for RF write port access.
+ when "1101" =>
+ -- ST X+, Rr (Store indirect with post-increment via X register)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
+ next_pavr_s4_s5_x_dacuwr_rq <= '1';
+ next_pavr_s4_s5_ldstincrampx_xwr_rq <= '1'; -- Request X pointer write access. The X pointer will be (post-)incremented.
+ next_pavr_s4_s5_dacux_bpr12wr_rq <='1';
+ next_pavr_s4_nop_rq <= '1';
+ when "1110" =>
+ -- ST -X, Rr (Store indirect with pre-decrement via X register)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(-1, next_pavr_s4_dacu_q'length);
+ next_pavr_s4_s5_x_dacuwr_rq <= '1';
+ next_pavr_s4_s5_ldstdecrampx_xwr_rq <= '1'; -- Request X pointer write access. The X pointer will be (post-)decremented.
+ next_pavr_s4_s5_dacux_bpr12wr_rq <='1';
+ next_pavr_s4_nop_rq <= '1';
+ when "1001" =>
+ -- ST Y+, Rr (Store indirect with post-increment via Y register)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
+ next_pavr_s4_s5_y_dacuwr_rq <= '1';
+ next_pavr_s4_s5_ldstincrampy_ywr_rq <= '1'; -- Request Y pointer write access. The Y pointer will be (post-)incremented.
+ next_pavr_s4_s5_dacuy_bpr12wr_rq <='1';
+ next_pavr_s4_nop_rq <= '1';
+ when "1010" =>
+ -- ST -Y, Rr (Store indirect with pre-decrement via Y register)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(-1, next_pavr_s4_dacu_q'length);
+ next_pavr_s4_s5_y_dacuwr_rq <= '1';
+ next_pavr_s4_s5_ldstdecrampy_ywr_rq <= '1'; -- Request Y pointer write access. The Y pointer will be (post-)decremented.
+ next_pavr_s4_s5_dacuy_bpr12wr_rq <='1';
+ next_pavr_s4_nop_rq <= '1';
+ when "0001" =>
+ -- ST Z+, Rr (Store indirect with post-increment via Z register)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(0, next_pavr_s4_dacu_q'length);
+ next_pavr_s4_s5_z_dacuwr_rq <= '1';
+ next_pavr_s4_s5_ldstincrampz_zwr_rq <= '1'; -- Request Z pointer write access. The Z pointer will be (post-)incremented.
+ next_pavr_s4_s5_dacuz_bpr12wr_rq <='1';
+ next_pavr_s4_nop_rq <= '1';
+ when "0010" =>
+ -- ST -Z, Rr (Store indirect with pre-decrement via Z register)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_dacu_q <= int_to_std_logic_vector(-1, next_pavr_s4_dacu_q'length);
+ next_pavr_s4_s5_z_dacuwr_rq <= '1';
+ next_pavr_s4_s5_ldstdecrampz_zwr_rq <= '1'; -- Request Z pointer write access. The Z pointer will be (post-)decremented.
+ next_pavr_s4_s5_dacuz_bpr12wr_rq <='1';
+ next_pavr_s4_nop_rq <= '1';
+ when others =>
+ -- Invalid opcode (1001_001x_xxxx_yyyy, with yyyy = 0011, 0100, 0101, 0110, 0111, 1000, 1110)
+ null;
+ end case;
+ end if;
+ end case;
+ else
+ if pavr_s3_instr(11)='0' then
+ -- IN Rd, A (Load IO location to register)
+ next_pavr_s4_s5_iof_rq <= '1';
+ next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_rdbyte;
+ next_pavr_s4_s5s6_iof_addr <= pavr_s3_instr(10 downto 9)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s6_iof_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_iof_rfwr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s5_stall_rq <= '1'; -- Steal BPU0 write access from next instruction.
+ else
+ -- OUT A, Rr (Store register into IO location)
+ pavr_s3_rfrd1_rq <= '1';
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s5_iof_rq <= '1';
+ next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_wrbyte;
+ next_pavr_s4_s5s6_iof_addr <= pavr_s3_instr(10 downto 9)&pavr_s3_instr(3 downto 0);
+ end if;
+ end if;
+ when "110" =>
+ if pavr_s3_instr(13)='0' then
+ -- RJMP k12 (Relative jump (12 bit relative address))
+ next_pavr_s4_k12 <= pavr_s3_instr(11 downto 0); -- Load 12 bit relative jump address from instruction opcode.
+ next_pavr_s4_k12rel_pm_rq <= '1'; -- Request PM access.
+ pavr_s3_flush_s2_rq <= '1'; -- Request flush s2 during s3 (next instruction is out of normal instruction flow).
+ next_pavr_s4_flush_s2_rq <= '1'; -- Request flush s2 during s4 (next 2 instructions are out of normal instruction flow).
+ else
+ -- LDI k8 (Load immediate)
+ next_pavr_s4_s5_alu_opcode <= int_to_std_logic_vector(pavr_alu_opcode_op2, next_pavr_s4_s5_alu_opcode'length);
+ next_pavr_s4_s5_k8 <= pavr_s3_instr(11 downto 8)&pavr_s3_instr(3 downto 0);
+ next_pavr_s4_s5_alu_op2_sel <= pavr_alu_op2_sel_k8;
+ next_pavr_s4_s5_alu_bpr0wr_rq <= '1';
+ next_pavr_s4_s6_aluoutlo8_rfwr_rq <= '1';
+ next_pavr_s4_s6_rfwr_addr1 <= '1'&pavr_s3_instr(7 downto 4); -- Only the higher 16 registers can be immediately loaded.
+ end if;
+ when others =>
+ if pavr_s3_instr(13)='0' then
+ -- RCALL (Relative call (12 bit relative address))
+ next_pavr_s4_k12 <= pavr_s3_instr(11 downto 0); -- Load 12 bit relative jump address from instruction opcode.
+ pavr_s3_flush_s2_rq <= '1'; -- Flush the instructions that were already fetched but don't follow the normal instruction flow.
+ next_pavr_s4_flush_s2_rq <= '1';
+ next_pavr_s4_nop_rq <= '1'; -- Insert a nop *after* the instruction wavefront.
+ next_pavr_s4_k12rel_pm_rq <= '1'; -- Request PM access. Also, update PC.
+ next_pavr_s4_s5s51s52_pc_dacuwr_rq <= '1'; -- Request DACU write access in s5, s51 and s52.
+ next_pavr_s4_s5s51s52_calldec_spwr_rq <= '1'; -- Decrement SP.
+ --next_pavr_s4_stall_rq <= '1';
+ else
+ tmp2_a := pavr_s3_instr(11 downto 10);
+ case tmp2_a is
+ when "00" =>
+ -- BRBS s, k7 (Branch if bit in SREG is set (7 bit relative address))
+ next_pavr_s4_s5_k7_branch_offset <= pavr_s3_instr(9 downto 3); -- 7 bit relative jump address
+ next_pavr_s4_pcinc <= '1';
+ next_pavr_s4_s5_branch_cond_sel <= pavr_s5_branch_cond_sel_bitsreg; -- Select jump condition.
+ next_pavr_s4_s5_branch_en <= '1'; -- Enable branch request.
+ next_pavr_s4_s5_branch_bitsreg_sel <= pavr_s3_instr(2 downto 0); -- Select which bit in SREG will be checked as branch condition.
+ pavr_s3_stall_rq <= '1';
+ when "01" =>
+ -- BRBC s, k7 (Branch if bit in SREG is cleared (7 bit relative address))
+ next_pavr_s4_s5_k7_branch_offset <= pavr_s3_instr(9 downto 3);
+ next_pavr_s4_pcinc <= '1';
+ next_pavr_s4_s5_branch_cond_sel <= pavr_s5_branch_cond_sel_notbitsreg;
+ next_pavr_s4_s5_branch_en <= '1';
+ next_pavr_s4_s5_branch_bitsreg_sel <= pavr_s3_instr(2 downto 0);
+ pavr_s3_stall_rq <= '1';
+ when "10" =>
+ tmp2_b := pavr_s3_instr(9)&pavr_s3_instr(3);
+ case tmp2_b is
+ when "00" =>
+ -- BLD Rd, b (Bit load from T flag in SREG into a bit in register)
+ pavr_s3_rfrd1_rq <= '1'; -- Request RF read port 1 access in s3.
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4); -- Set address of operand to be read from RF read port 1.
+ next_pavr_s4_s5_iof_rq <= '1'; -- Request IOF access in s5 for loading the T flag in SREG into a bit in register.
+ next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_ldbit; -- Set IOF opcode in s5 to `load bit'.
+ next_pavr_s4_s5s6_iof_bitaddr <= pavr_s3_instr(2 downto 0); -- Set IOF bit address (s6).
+ next_pavr_s4_s6_iof_bpr0wr_rq <= '1'; -- Update BPU.
+ next_pavr_s4_s6_iof_rfwr_rq <= '1'; -- Request RF write port access.
+ next_pavr_s4_s6_rfwr_addr1 <= pavr_s3_instr(8 downto 4); -- Set RF write-back address.
+ next_pavr_s4_s5_stall_rq <= '1'; -- Steal BPU0 write access from next instruction.
+ when "10" =>
+ -- BST Rd, b (Bit store from a bit in register into T flag in SREG)
+ pavr_s3_rfrd1_rq <= '1'; -- Request RF read port 1 access in s3.
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4); -- Set address of operand in RF.
+ next_pavr_s4_s5_iof_rq <= '1'; -- Request IOF access in s5 for storing the bit into T flag in SREG.
+ next_pavr_s4_s5_iof_opcode <= pavr_iof_opcode_stbit; -- Set IOF opcode in s5 to `store bit'.
+ next_pavr_s4_s5s6_iof_bitaddr <= pavr_s3_instr(2 downto 0); -- Set IOF bit address (s6).
+ when others =>
+ -- Invalid opcode (1111_10xy_yyyy_xyyy, with xx = 01, 11)
+ null;
+ end case;
+ when others =>
+ tmp2_c := pavr_s3_instr(9)&pavr_s3_instr(3);
+ case tmp2_c is
+ when "00" =>
+ -- SBRC Rr, b (Skip if bit in register is cleared)
+ pavr_s3_rfrd1_rq <= '1'; -- Read an operand from RF and use a specific bit of it (negated) as skip condition to be checked.
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s5_skip_bitrf_sel <= pavr_s3_instr(2 downto 0);
+ next_pavr_s4_s5_skip_cond_sel <= pavr_s5_skip_cond_sel_notbitrf;
+ next_pavr_s4_s5_skip_en <= '1'; -- Enable skip request in s5. If skip condition true, then: 1) stall (s6) and flush s5, 2) flush s3, 3) if instr32bits then flush s2
+ pavr_s3_stall_rq <= '1';
+ --next_pavr_s4_s5_stall_rq <= '1'; -- Request stall in s5. That's to have next two instruction words in s2 and s3, and be able to easely skip (flush) any or both of them.
+ when "10" =>
+ -- SBRS Rr, b (Skip if bit in register is set)
+ pavr_s3_rfrd1_rq <= '1'; -- Read an operand from RF and use a specific bit of it as skip condition to be checked.
+ pavr_s3_rfrd1_addr <= pavr_s3_instr(8 downto 4);
+ next_pavr_s4_s5_skip_bitrf_sel <= pavr_s3_instr(2 downto 0);
+ next_pavr_s4_s5_skip_cond_sel <= pavr_s5_skip_cond_sel_bitrf;
+ next_pavr_s4_s5_skip_en <= '1';
+ pavr_s3_stall_rq <= '1';
+ --next_pavr_s4_s5_stall_rq <= '1';
+ when others =>
+ -- Invalid opcode (1111_11xy_yyyy_xyyy, with xx = 01, 11)
+ null;
+ end case;
+ end case;
+ end if;
+ end case;
+ end if;
+ else
+
+ -- Interrupt request
+ -- Forcedly place a call into the pipeline.
+ next_pavr_s4_instr32bits <= '1'; -- Signalize 32 bit instruction (quite redundant here; kept for the regularity of the code).
+ pavr_s3_flush_s2_rq <= '1';
+ next_pavr_s4_flush_s2_rq <= '1';
+ next_pavr_s4_nop_rq <= '1'; -- Insert a nop *after* the instruction wavefront.
+ next_pavr_s4_k22int_pm_rq <= '1'; -- Request PM access. Also, update PC.
+ next_pavr_s4_s5s51s52_pc_dacuwr_rq <= '1'; -- Request DACU write access in s5, s51 and s52, to save the PC.
+ next_pavr_s4_s5s51s52_calldec_spwr_rq <= '1'; -- Decrement SP.
+ next_pavr_s4_k22int <= pavr_int_vec; -- Get absolute call address from interrupt vector.
+ next_pavr_s4_s5_clriflag_sregwr_rq <= '1'; -- Request clear I flag (general interrupt enable flag).
+ next_pavr_s4_disable_int <= '1'; -- Disable interrupts in the next 4 clocks, so that at least an instruction is executed in the current interrupt routine.
+ --next_pavr_s4_stall_rq <= '1'; -- !!! Needed?
+
+ end if;
+ end process instr_decoder;
+
+
+
+
+
+
+
+
+
+
+ -- Hardware resources managers ---------------------------------------------
+
+ -- RF read port 1
+ -- Set the signals:
+ -- - pavr_rf_rd1_addr
+ -- - pavr_rf_rd1_rd
+ rfrd1_manager:
+ process(pavr_s3_rfrd1_rq,
+ pavr_s5_dacu_rfrd1_rq,
+
+ pavr_s3_hwrq_en,
+ pavr_s5_hwrq_en,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_rf_rd1_addr,
+ pavr_s3_rfrd1_addr,
+ pavr_s5_dacust_rf_addr)
+ variable v_rfrd1rq_sel : std_logic_vector(1 downto 0);
+ begin
+ pavr_rf_rd1_addr <= int_to_std_logic_vector(0, pavr_rf_rd1_addr'length);
+ pavr_rf_rd1_rd <= '0';
+
+ v_rfrd1rq_sel := pavr_s3_rfrd1_rq & pavr_s5_dacu_rfrd1_rq;
+ case v_rfrd1rq_sel is
+ when "00" =>
+ -- No read requests.
+ null;
+ when "10" =>
+ -- Instruction decoder RFRD1 request
+ -- Only take action if permitted by older instructions.
+ if pavr_s3_hwrq_en='1' then
+ pavr_rf_rd1_addr <= pavr_s3_rfrd1_addr;
+ pavr_rf_rd1_rd <= '1';
+ end if;
+ when "01" =>
+ -- DACU RFRD1 request, placed by loads and POP that decode UM as RF
+ -- Only take action if permitted by older instructions.
+ if pavr_s5_hwrq_en='1' then
+ pavr_rf_rd1_addr <= pavr_s5_dacust_rf_addr;
+ pavr_rf_rd1_rd <= '1';
+ end if;
+ when others =>
+ -- Multiple requests shouldn't happen.
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "Register File read port 1 error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+ end process rfrd1_manager;
+
+
+
+ -- RF read port 2
+ -- Set the signals:
+ -- - pavr_rf_rd2_addr
+ -- - pavr_rf_rd2_rd
+ rfrd2_manager:
+ process(pavr_s3_rfrd2_rq,
+
+ pavr_s3_hwrq_en,
+
+ pavr_rf_rd2_addr,
+ pavr_s3_rfrd2_addr
+ )
+ begin
+ pavr_rf_rd2_addr <= int_to_std_logic_vector(0, pavr_rf_rd2_addr'length);
+ pavr_rf_rd2_rd <= '0';
+
+ if pavr_s3_rfrd2_rq='0' then
+ -- No read requests.
+ null;
+ else
+ -- Instruction decoder RFRD2 request
+ -- Only take action if permitted by older instructions.
+ if pavr_s3_hwrq_en='1' then
+ pavr_rf_rd2_addr <= pavr_s3_rfrd2_addr;
+ pavr_rf_rd2_rd <= '1';
+ end if;
+ end if;
+ end process rfrd2_manager;
+
+
+
+ -- RF write port
+ -- Set the signals:
+ -- - pavr_rf_wr_addr
+ -- - pavr_rf_wr_wr
+ -- - pavr_rf_wr_di
+ rfwr_manager:
+ process(pavr_s6_aluoutlo8_rfwr_rq,
+ pavr_s61_aluouthi8_rfwr_rq,
+ pavr_s6_iof_rfwr_rq,
+ pavr_s6_dacu_rfwr_rq,
+ pavr_s6_pm_rfwr_rq,
+ pavr_s5_dacu_rfwr_rq,
+
+ pavr_s5_hwrq_en,
+ pavr_s6_hwrq_en,
+ pavr_s61_hwrq_en,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_s6_zlsb,
+ pavr_pm_do,
+ pavr_rf_wr_addr,
+ pavr_rf_wr_di,
+ pavr_s6_rfwr_addr1,
+ pavr_s61_rfwr_addr2,
+ pavr_s6_alu_out,
+ pavr_s61_alu_out_hi8,
+ pavr_s5_dacust_rf_addr,
+ pavr_s5_dacu_rfwr_di,
+ pavr_iof_do_shadow_active,
+ pavr_iof_do_shadow,
+ pavr_iof_do,
+ pavr_dacu_do_shadow_active,
+ pavr_dacu_do_shadow,
+ pavr_dacu_do,
+ pavr_pm_do
+ )
+ variable v_rfwrrq_sel : std_logic_vector(5 downto 0);
+ begin
+ pavr_rf_wr_addr <= int_to_std_logic_vector(0, pavr_rf_wr_addr'length);
+ pavr_rf_wr_wr <= '0';
+ pavr_rf_wr_di <= int_to_std_logic_vector(0, pavr_rf_wr_di'length);
+
+ v_rfwrrq_sel := pavr_s6_aluoutlo8_rfwr_rq &
+ pavr_s61_aluouthi8_rfwr_rq &
+ pavr_s6_iof_rfwr_rq &
+ pavr_s6_dacu_rfwr_rq &
+ pavr_s6_pm_rfwr_rq &
+ pavr_s5_dacu_rfwr_rq;
+ case v_rfwrrq_sel is
+ when "000000" =>
+ -- No write requests.
+ null;
+ when "100000" =>
+ -- ALU out lower 8 bits RFWR request
+ -- Only take action if permitted by older instructions.
+ if pavr_s6_hwrq_en='1' then
+ pavr_rf_wr_addr <= pavr_s6_rfwr_addr1;
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= pavr_s6_alu_out(7 downto 0);
+ end if;
+ when "010000" =>
+ -- ALU out higher 8 bits RFWR request
+ -- Only take action if permitted by older instructions.
+ if pavr_s61_hwrq_en='1' then
+ pavr_rf_wr_addr <= pavr_s61_rfwr_addr2;
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= pavr_s61_alu_out_hi8;
+ end if;
+ when "001000" =>
+ -- IOF out RFWR request
+ -- Only take action if permitted by older instructions.
+ if pavr_s6_hwrq_en='1' then
+ pavr_rf_wr_addr <= pavr_s6_rfwr_addr1;
+ pavr_rf_wr_wr <= '1';
+ if pavr_iof_do_shadow_active='0' then
+ pavr_rf_wr_di <= pavr_iof_do;
+ else
+ pavr_rf_wr_di <= pavr_iof_do_shadow;
+ end if;
+ end if;
+ when "000100" =>
+ -- DACU out RFWR request, placed by loads and POP
+ -- Only take action if permitted by older instructions.
+ if pavr_s6_hwrq_en='1' then
+ pavr_rf_wr_addr <= pavr_s6_rfwr_addr1;
+ pavr_rf_wr_wr <= '1';
+ if pavr_dacu_do_shadow_active='0' then
+ pavr_rf_wr_di <= pavr_dacu_do;
+ else
+ pavr_rf_wr_di <= pavr_dacu_do_shadow;
+ end if;
+ end if;
+ when "000010" =>
+ -- PM out RFWR request, placed by LPMs
+ -- Only take action if permitted by older instructions.
+ if pavr_s6_hwrq_en='1' then
+ pavr_rf_wr_addr <= pavr_s6_rfwr_addr1;
+ pavr_rf_wr_wr <= '1';
+ if pavr_s6_zlsb='0' then
+ -- *** Break a hole through the shadow protocol for this
+ -- off-placed PM read request.
+ -- Fortunately, there's no danger for PM data out to get
+ -- corrupted by a stall from older instructions, because this
+ -- request takes place so late in the pipeline, that no other
+ -- older instruction could stall it.
+ --if pavr_pm_do_shadow_active='0' then
+ pavr_rf_wr_di <= pavr_pm_do(7 downto 0);
+ --else
+ -- pavr_rf_wr_di <= pavr_pm_do_shadow(7 downto 0);
+ --end if;
+ else
+ --if pavr_pm_do_shadow_active='0' then
+ pavr_rf_wr_di <= pavr_pm_do(15 downto 8);
+ --else
+ -- pavr_rf_wr_di <= pavr_pm_do_shadow(15 downto 8);
+ --end if;
+ end if;
+ end if;
+ when "000001" =>
+ -- DACU out RFWR request, placed by stores and PUSH
+ -- Only take action if permitted by older instructions.
+ if pavr_s5_hwrq_en='1' then
+ pavr_rf_wr_addr <= pavr_s5_dacust_rf_addr;
+ pavr_rf_wr_wr <= '1';
+ pavr_rf_wr_di <= pavr_s5_dacu_rfwr_di;
+ end if;
+ when others =>
+ -- Multiple requests shouldn't happen.
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "Register File write port error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+ end process rfwr_manager;
+
+
+
+ -- X pointer write port
+ -- Set the signals:
+ -- - pavr_rf_x_wr
+ -- - pavr_rf_x_di
+ xwr_manager:
+ process(pavr_s5_ldstincrampx_xwr_rq,
+ pavr_s5_ldstdecrampx_xwr_rq,
+
+ pavr_s5_hwrq_en,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_rf_x_di,
+ pavr_iof_rampx,
+ pavr_xbpu
+ )
+ variable v_xwrrq_sel: std_logic_vector(1 downto 0);
+ variable v_xrampx_inc: std_logic_vector(23 downto 0);
+ variable v_xrampx_dec: std_logic_vector(23 downto 0);
+ begin
+ pavr_rf_x_wr <= '0';
+ pavr_rf_x_di <= int_to_std_logic_vector(0, pavr_rf_x_di'length);
+
+ v_xrampx_inc := (pavr_iof_rampx & pavr_xbpu) + 1;
+ v_xrampx_dec := (pavr_iof_rampx & pavr_xbpu) - 1;
+
+ v_xwrrq_sel := pavr_s5_ldstincrampx_xwr_rq & pavr_s5_ldstdecrampx_xwr_rq;
+ case v_xwrrq_sel is
+ when "00" =>
+ -- No X write requests
+ null;
+ when "10" =>
+ -- Increment X request, placed by loads and stores with post increment.
+ -- Note that RAMPX is modified, if needed, by its own write manager.
+ -- Only take action if permitted by older instructions.
+ if pavr_s5_hwrq_en='1' then
+ pavr_rf_x_wr <= '1';
+ if pavr_dm_bigger_than_64K='1' then
+ pavr_rf_x_di <= v_xrampx_inc(15 downto 0);
+ else
+ pavr_rf_x_di <= pavr_xbpu + 1;
+ end if;
+ end if;
+ when "01" =>
+ -- Decrement X request, placed by loads and stores with pre decrement.
+ -- Only take action if permitted by older instructions.
+ if pavr_s5_hwrq_en='1' then
+ pavr_rf_x_wr <= '1';
+ if pavr_dm_bigger_than_64K='1' then
+ pavr_rf_x_di <= v_xrampx_dec(15 downto 0);
+ else
+ pavr_rf_x_di <= pavr_xbpu - 1;
+ end if;
+ end if;
+ when others =>
+ -- Multiple requests shouldn't happen.
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "X pointer error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+ end process xwr_manager;
+
+
+
+ -- Y pointer write port
+ -- Set the signals:
+ -- - pavr_rf_y_wr
+ -- - pavr_rf_y_di
+ ywr_manager:
+ process(pavr_s5_ldstincrampy_ywr_rq,
+ pavr_s5_ldstdecrampy_ywr_rq,
+
+ pavr_s5_hwrq_en,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_rf_y_di,
+ pavr_iof_rampy,
+ pavr_ybpu,
+ pavr_iof_rampy
+ )
+ variable v_ywrrq_sel: std_logic_vector(1 downto 0);
+ variable v_yrampy_inc: std_logic_vector(23 downto 0);
+ variable v_yrampy_dec: std_logic_vector(23 downto 0);
+ begin
+ pavr_rf_y_wr <= '0';
+ pavr_rf_y_di <= int_to_std_logic_vector(0, pavr_rf_y_di'length);
+
+ v_yrampy_inc := (pavr_iof_rampy & pavr_ybpu) + 1;
+ v_yrampy_dec := (pavr_iof_rampy & pavr_ybpu) - 1;
+
+ v_ywrrq_sel := pavr_s5_ldstincrampy_ywr_rq & pavr_s5_ldstdecrampy_ywr_rq;
+ case v_ywrrq_sel is
+ when "00" =>
+ null;
+ when "10" =>
+ -- Increment Y request, placed by loads and stores with post increment.
+ -- Note that RAMPY is modified, if needed, by its own write manager.
+ -- Only take action if permitted by older instructions.
+ if pavr_s5_hwrq_en='1' then
+ pavr_rf_y_wr <= '1';
+ if pavr_dm_bigger_than_64K='1' then
+ pavr_rf_y_di <= v_yrampy_inc(15 downto 0);
+ else
+ pavr_rf_y_di <= pavr_ybpu + 1;
+ end if;
+ end if;
+ when "01" =>
+ -- Decrement Y request, placed by loads and stores with pre decrement.
+ -- Only take action if permitted by older instructions.
+ if pavr_s5_hwrq_en='1' then
+ pavr_rf_y_wr <= '1';
+ if pavr_dm_bigger_than_64K='1' then
+ pavr_rf_y_di <= v_yrampy_dec(15 downto 0);
+ else
+ pavr_rf_y_di <= pavr_ybpu - 1;
+ end if;
+ end if;
+ when others =>
+ -- Multiple requests shouldn't happen.
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "Y pointer error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+ end process ywr_manager;
+
+
+
+ -- Z pointer write port
+ -- Set the signals:
+ -- - pavr_rf_z_wr
+ -- - pavr_rf_z_di
+ zwr_manager:
+ process(pavr_s5_ldstincrampz_zwr_rq,
+ pavr_s5_ldstdecrampz_zwr_rq,
+ pavr_s5_lpminc_zwr_rq,
+ pavr_s5_elpmincrampz_zwr_rq,
+
+ pavr_s5_hwrq_en,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_zbpu,
+ pavr_iof_rampz,
+ pavr_rf_z_di
+ )
+ variable v_zwrrq_sel: std_logic_vector(3 downto 0);
+ variable v_zrampz_inc: std_logic_vector(23 downto 0);
+ variable v_zrampz_dec: std_logic_vector(23 downto 0);
+ begin
+ pavr_rf_z_wr <= '0';
+ pavr_rf_z_di <= int_to_std_logic_vector(0, pavr_rf_z_di'length);
+
+ v_zrampz_inc := (pavr_iof_rampz & pavr_zbpu) + 1;
+ v_zrampz_dec := (pavr_iof_rampz & pavr_zbpu) - 1;
+
+ v_zwrrq_sel := pavr_s5_ldstincrampz_zwr_rq &
+ pavr_s5_ldstdecrampz_zwr_rq &
+ pavr_s5_lpminc_zwr_rq &
+ pavr_s5_elpmincrampz_zwr_rq;
+ case v_zwrrq_sel is
+ when "0000" =>
+ null;
+ when "1000" | "0001" =>
+ -- Increment Z request, placed by loads, stores and ELPM with post increment.
+ -- Note that RAMPZ is modified, if needed, by its own write manager.
+ -- Only take action if permitted by older instructions.
+ if pavr_s5_hwrq_en='1' then
+ pavr_rf_z_wr <= '1';
+ if pavr_dm_bigger_than_64K='1' then
+ pavr_rf_z_di <= v_zrampz_inc(15 downto 0);
+ else
+ pavr_rf_z_di <= pavr_zbpu + 1;
+ end if;
+ end if;
+ when "0100" =>
+ -- Decrement Z request, placed by loads and stores with pre decrement.
+ -- Only take action if permitted by older instructions.
+ if pavr_s5_hwrq_en='1' then
+ pavr_rf_z_wr <= '1';
+ if pavr_dm_bigger_than_64K='1' then
+ pavr_rf_z_di <= v_zrampz_dec(15 downto 0);
+ else
+ pavr_rf_z_di <= pavr_zbpu - 1;
+ end if;
+ end if;
+ when "0010" =>
+ -- Increment Z request, placed by LPM with post increment.
+ -- Only take action if permitted by older instructions.
+ if pavr_s5_hwrq_en='1' then
+ pavr_rf_z_wr <= '1';
+ pavr_rf_z_di <= pavr_zbpu + 1;
+ end if;
+ when others =>
+ -- Multiple requests shouldn't happen.
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "Z pointer error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+ end process zwr_manager;
+
+
+
+ -- BPU write, BPR0-related
+ -- Set the signals:
+ -- - next_pavr_bpr0
+ -- - next_pavr_bpr0_addr
+ -- - next_pavr_bpr0_active
+ bpr0wr_manager:
+ process(pavr_s5_alu_bpr0wr_rq,
+ pavr_s6_iof_bpr0wr_rq,
+ pavr_s6_daculd_bpr0wr_rq,
+ pavr_s5_dacust_bpr0wr_rq,
+ pavr_s6_pmdo_bpr0wr_rq,
+
+ pavr_stall_s5,
+ pavr_flush_s5,
+ pavr_stall_s6,
+ pavr_flush_s6,
+
+ pavr_s6_zlsb,
+ next_pavr_bpr0,
+ next_pavr_bpr0_addr,
+ pavr_s5_alu_out,
+ pavr_s5_op1bpu,
+ pavr_s6_rfwr_addr1,
+ pavr_s5_s6_rfwr_addr1,
+ pavr_s5_dacust_rf_addr,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_iof_do_shadow_active,
+ pavr_iof_do_shadow,
+ pavr_dacu_do_shadow_active,
+ pavr_dacu_do_shadow,
+ pavr_dacu_do,
+ pavr_iof_do,
+ --pavr_pm_do_shadow_active,
+ --pavr_pm_do_shadow,
+ pavr_pm_do
+ )
+ variable v_bpr0wrrq_sel: std_logic_vector(4 downto 0);
+ begin
+ next_pavr_bpr0 <= int_to_std_logic_vector(0, next_pavr_bpr0'length);
+ next_pavr_bpr0_addr <= int_to_std_logic_vector(0, next_pavr_bpr0_addr'length);
+ next_pavr_bpr0_active <= '0';
+
+ v_bpr0wrrq_sel := pavr_s5_alu_bpr0wr_rq &
+ pavr_s6_iof_bpr0wr_rq &
+ pavr_s6_daculd_bpr0wr_rq &
+ pavr_s5_dacust_bpr0wr_rq &
+ pavr_s6_pmdo_bpr0wr_rq;
+
+ case v_bpr0wrrq_sel is
+ when "00000" =>
+ null;
+ when "10000" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ next_pavr_bpr0 <= pavr_s5_alu_out(7 downto 0);
+ next_pavr_bpr0_addr <= pavr_s5_s6_rfwr_addr1;
+ next_pavr_bpr0_active <= '1';
+ end if;
+ when "01000" =>
+ if pavr_stall_s6='0' and pavr_flush_s6='0' then
+ if pavr_iof_do_shadow_active='0' then
+ next_pavr_bpr0 <= pavr_iof_do;
+ else
+ next_pavr_bpr0 <= pavr_iof_do_shadow;
+ end if;
+ next_pavr_bpr0_addr <= pavr_s6_rfwr_addr1;
+ next_pavr_bpr0_active <= '1';
+ end if;
+ when "00100" =>
+ if pavr_stall_s6='0' and pavr_flush_s6='0' then
+ if pavr_dacu_do_shadow_active='0' then
+ next_pavr_bpr0 <= pavr_dacu_do;
+ else
+ next_pavr_bpr0 <= pavr_dacu_do_shadow;
+ end if;
+ next_pavr_bpr0_addr <= pavr_s6_rfwr_addr1;
+ next_pavr_bpr0_active <= '1';
+ end if;
+ when "00010" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ next_pavr_bpr0 <= pavr_s5_op1bpu;
+ next_pavr_bpr0_addr <= pavr_s5_dacust_rf_addr;
+ next_pavr_bpr0_active <= '1';
+ end if;
+ when "00001" =>
+ if pavr_stall_s6='0' and pavr_flush_s6='0' then
+ if pavr_s6_zlsb='0' then
+ -- *** Break a hole through the shadow protocol.
+ --if pavr_pm_do_shadow_active='0' then
+ next_pavr_bpr0 <= pavr_pm_do(7 downto 0);
+ --else
+ -- next_pavr_bpr0 <= pavr_pm_do_shadow(7 downto 0);
+ --end if;
+ else
+ --if pavr_pm_do_shadow_active='0' then
+ next_pavr_bpr0 <= pavr_pm_do(15 downto 8);
+ --else
+ -- next_pavr_bpr0 <= pavr_pm_do_shadow(15 downto 8);
+ --end if;
+ end if;
+ next_pavr_bpr0_addr <= pavr_s6_rfwr_addr1;
+ next_pavr_bpr0_active <= '1';
+ end if;
+ when others =>
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "Bypass Unit, chain 0 error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+ end process bpr0wr_manager;
+
+
+
+ -- BPU write, BPR1-related
+ -- Set the signals:
+ -- - next_pavr_bpr1
+ -- - next_pavr_bpr1_addr
+ -- - next_pavr_bpr1_active
+ bpr1wr_manager:
+ process(pavr_s5_alu_bpr1wr_rq,
+ pavr_s5_dacux_bpr12wr_rq,
+ pavr_s5_dacuy_bpr12wr_rq,
+ pavr_s5_dacuz_bpr12wr_rq,
+
+ pavr_rf_x_di,
+ pavr_rf_y_di,
+ pavr_rf_z_di,
+
+ pavr_stall_s5,
+ pavr_flush_s5,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ next_pavr_bpr1,
+ pavr_s5_alu_out,
+ pavr_s5_s61_rfwr_addr2,
+ next_pavr_bpr1_addr
+ )
+ variable v_bpr1wrrq_sel: std_logic_vector(3 downto 0);
+ begin
+ next_pavr_bpr1 <= int_to_std_logic_vector(0, next_pavr_bpr1'length);
+ next_pavr_bpr1_addr <= int_to_std_logic_vector(0, next_pavr_bpr1_addr'length);
+ next_pavr_bpr1_active <= '0';
+
+ v_bpr1wrrq_sel := pavr_s5_alu_bpr1wr_rq &
+ pavr_s5_dacux_bpr12wr_rq &
+ pavr_s5_dacuy_bpr12wr_rq &
+ pavr_s5_dacuz_bpr12wr_rq;
+
+ case v_bpr1wrrq_sel is
+ when "0000" =>
+ null;
+ when "1000" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ next_pavr_bpr1 <= pavr_s5_alu_out(15 downto 8);
+ next_pavr_bpr1_addr <= pavr_s5_s61_rfwr_addr2;
+ next_pavr_bpr1_active <= '1';
+ end if;
+ when "0100" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ next_pavr_bpr1 <= pavr_rf_x_di(7 downto 0);
+ next_pavr_bpr1_addr <= int_to_std_logic_vector(26, next_pavr_bpr1_addr'length);
+ next_pavr_bpr1_active <= '1';
+ end if;
+ when "0010" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ next_pavr_bpr1 <= pavr_rf_y_di(7 downto 0);
+ next_pavr_bpr1_addr <= int_to_std_logic_vector(28, next_pavr_bpr1_addr'length);
+ next_pavr_bpr1_active <= '1';
+ end if;
+ when "0001" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ next_pavr_bpr1 <= pavr_rf_z_di(7 downto 0);
+ next_pavr_bpr1_addr <= int_to_std_logic_vector(30, next_pavr_bpr1_addr'length);
+ next_pavr_bpr1_active <= '1';
+ end if;
+ when others =>
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "Bypass Unit, chain 1 error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+ end process bpr1wr_manager;
+
+
+
+ -- BPU write, BPR2-related
+ -- Set the signals:
+ -- - next_pavr_bpr2
+ -- - next_pavr_bpr2_addr
+ -- - next_pavr_bpr2_active
+ bpr2wr_manager:
+ process(pavr_s5_dacux_bpr12wr_rq,
+ pavr_s5_dacuy_bpr12wr_rq,
+ pavr_s5_dacuz_bpr12wr_rq,
+
+ next_pavr_bpr2,
+ next_pavr_bpr2_addr,
+
+ pavr_rf_x_di,
+ pavr_rf_y_di,
+ pavr_rf_z_di,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_stall_s5,
+ pavr_flush_s5
+ )
+ variable v_bpr2wrrq_sel: std_logic_vector(2 downto 0);
+ begin
+ next_pavr_bpr2 <= int_to_std_logic_vector(0, next_pavr_bpr2'length);
+ next_pavr_bpr2_addr <= int_to_std_logic_vector(0, next_pavr_bpr2_addr'length);
+ next_pavr_bpr2_active <= '0';
+
+ v_bpr2wrrq_sel := pavr_s5_dacux_bpr12wr_rq &
+ pavr_s5_dacuy_bpr12wr_rq &
+ pavr_s5_dacuz_bpr12wr_rq;
+
+ case v_bpr2wrrq_sel is
+ when "000" =>
+ null;
+ when "100" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ next_pavr_bpr2 <= pavr_rf_x_di(15 downto 8);
+ next_pavr_bpr2_addr <= int_to_std_logic_vector(27, next_pavr_bpr2_addr'length);
+ next_pavr_bpr2_active <= '1';
+ end if;
+ when "010" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ next_pavr_bpr2 <= pavr_rf_y_di(15 downto 8);
+ next_pavr_bpr2_addr <= int_to_std_logic_vector(29, next_pavr_bpr2_addr'length);
+ next_pavr_bpr2_active <= '1';
+ end if;
+ when "001" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ next_pavr_bpr2 <= pavr_rf_z_di(15 downto 8);
+ next_pavr_bpr2_addr <= int_to_std_logic_vector(31, next_pavr_bpr2_addr'length);
+ next_pavr_bpr2_active <= '1';
+ end if;
+ when others =>
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "Bypass Unit, chain 2 error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+ end process bpr2wr_manager;
+
+
+
+ -- IOF general port-related (write/read)
+ -- Set the signals:
+ -- - pavr_iof_di
+ -- - pavr_iof_opcode
+ -- - pavr_iof_addr
+ -- - pavr_iof_bitaddr
+ iof_manager:
+ process(pavr_s5_iof_rq,
+ pavr_s6_iof_rq,
+ pavr_s5_dacu_iof_rq,
+
+ pavr_stall_s5,
+ pavr_flush_s5,
+ pavr_stall_s6,
+ pavr_flush_s6,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_s5_op1bpu,
+ pavr_s5_iof_opcode,
+ pavr_s5_iof_addr,
+ pavr_s5_iof_bitaddr,
+ pavr_s6_iof_opcode,
+ pavr_s6_iof_addr,
+ pavr_s6_iof_bitaddr,
+ pavr_s5_dacu_iof_opcode,
+ pavr_s5_dacu_iof_addr,
+ pavr_s5_dacu_iofwr_di,
+ pavr_iof_di,
+ pavr_iof_opcode,
+ pavr_iof_addr,
+ pavr_iof_bitaddr,
+ pavr_iof_do,
+ pavr_iof_do_shadow,
+ pavr_iof_do_shadow_active
+ )
+ variable v_iofrq_sel: std_logic_vector(2 downto 0);
+ begin
+ pavr_iof_di <= int_to_std_logic_vector(0, pavr_iof_di'length);
+ pavr_iof_opcode <= int_to_std_logic_vector(0, pavr_iof_opcode'length);
+ pavr_iof_addr <= int_to_std_logic_vector(0, pavr_iof_addr'length);
+ pavr_iof_bitaddr <= int_to_std_logic_vector(0, pavr_iof_bitaddr'length);
+
+ v_iofrq_sel := pavr_s5_iof_rq & pavr_s6_iof_rq & pavr_s5_dacu_iof_rq;
+ case v_iofrq_sel is
+ when "000" =>
+ pavr_iof_di <= int_to_std_logic_vector(0, pavr_iof_di'length);
+ pavr_iof_opcode <= int_to_std_logic_vector(0, pavr_iof_opcode'length);
+ pavr_iof_addr <= int_to_std_logic_vector(0, pavr_iof_addr'length);
+ pavr_iof_bitaddr <= int_to_std_logic_vector(0, pavr_iof_bitaddr'length);
+ when "100" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ pavr_iof_di <= pavr_s5_op1bpu;
+ pavr_iof_opcode <= pavr_s5_iof_opcode;
+ pavr_iof_addr <= pavr_s5_iof_addr;
+ pavr_iof_bitaddr <= pavr_s5_iof_bitaddr;
+ end if;
+ when "010" =>
+ if pavr_stall_s6='0' and pavr_flush_s6='0' then
+ if pavr_s6_iof_opcode=pavr_iof_opcode_ldbit then
+ pavr_iof_di <= pavr_s5_op1bpu;
+ else
+ if pavr_iof_do_shadow_active='0' then
+ pavr_iof_di <= pavr_iof_do;
+ else
+ pavr_iof_di <= pavr_iof_do_shadow;
+ end if;
+ end if;
+ pavr_iof_opcode <= pavr_s6_iof_opcode;
+ pavr_iof_addr <= pavr_s6_iof_addr;
+ pavr_iof_bitaddr <= pavr_s6_iof_bitaddr;
+ end if;
+ when "001" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ pavr_iof_di <= pavr_s5_dacu_iofwr_di;
+ pavr_iof_opcode <= pavr_s5_dacu_iof_opcode;
+ pavr_iof_addr <= pavr_s5_dacu_iof_addr;
+ pavr_iof_bitaddr <= int_to_std_logic_vector(0, pavr_iof_bitaddr'length);
+ end if;
+ when others =>
+ -- Multiple requests shouldn't happen.
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "IO File error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+ end process iof_manager;
+
+
+
+ -- SREG-related
+ -- Set the signals:
+ -- - pavr_iof_sreg_wr
+ -- - pavr_iof_sreg_di
+ sregwr_manager:
+ process(pavr_s5_alu_sregwr_rq,
+ pavr_s5_clriflag_sregwr_rq,
+ pavr_s5_setiflag_sregwr_rq,
+
+ pavr_stall_s5,
+ pavr_flush_s5,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_iof_sreg,
+ pavr_iof_sreg_di,
+ pavr_s5_alu_flagsout
+ )
+ variable v_sregwrrq_sel: std_logic_vector(2 downto 0);
+ begin
+ pavr_iof_sreg_wr <= '0';
+ pavr_iof_sreg_di <= int_to_std_logic_vector(0, pavr_iof_sreg_di'length);
+
+ v_sregwrrq_sel := pavr_s5_alu_sregwr_rq & pavr_s5_clriflag_sregwr_rq & pavr_s5_setiflag_sregwr_rq;
+ case v_sregwrrq_sel is
+ when "000" =>
+ pavr_iof_sreg_wr <= '0';
+ pavr_iof_sreg_di <= int_to_std_logic_vector(0, pavr_iof_sreg_di'length);
+ when "100" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ pavr_iof_sreg_wr <= '1';
+ pavr_iof_sreg_di <= pavr_iof_sreg(7 downto 6) & pavr_s5_alu_flagsout;
+ end if;
+ when "010" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ pavr_iof_sreg_wr <= '1';
+ pavr_iof_sreg_di <= '0' & pavr_iof_sreg(6 downto 0);
+ end if;
+ when "001" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ pavr_iof_sreg_wr <= '1';
+ pavr_iof_sreg_di <= '1' & pavr_iof_sreg(6 downto 0);
+ end if;
+ when others =>
+ -- Multiple requests shouldn't happen.
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "SREG error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+ end process sregwr_manager;
+
+
+
+ -- SP-related
+ -- Set the signals:
+ -- - pavr_iof_spl_wr
+ -- - pavr_iof_spl_di
+ -- - pavr_iof_sph_wr
+ -- - pavr_iof_sph_di
+ spwr_manager:
+ process(pavr_s5_inc_spwr_rq, pavr_s5_dec_spwr_rq,
+ pavr_s5_calldec_spwr_rq, pavr_s51_calldec_spwr_rq, pavr_s52_calldec_spwr_rq,
+ pavr_s5_retinc2_spwr_rq, pavr_s51_retinc_spwr_rq,
+
+ pavr_stall_s5,
+ pavr_flush_s5,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_iof_spl_di,
+ pavr_iof_sph_di,
+ pavr_iof_sph,
+ pavr_iof_spl
+ )
+ variable v_spwrrq_sel: std_logic_vector(6 downto 0);
+ variable v_sp_inc : std_logic_vector(15 downto 0);
+ variable v_sp_inc2 : std_logic_vector(15 downto 0);
+ variable v_sp_dec : std_logic_vector(15 downto 0);
+ begin
+ pavr_iof_spl_wr <= '0';
+ pavr_iof_spl_di <= int_to_std_logic_vector(0, pavr_iof_spl_di'length);
+ pavr_iof_sph_wr <= '0';
+ pavr_iof_sph_di <= int_to_std_logic_vector(0, pavr_iof_sph_di'length);
+
+ v_sp_inc := (pavr_iof_sph & pavr_iof_spl) + 1;
+ v_sp_inc2 := (pavr_iof_sph & pavr_iof_spl) + 2;
+ v_sp_dec := (pavr_iof_sph & pavr_iof_spl) - 1;
+ v_spwrrq_sel := pavr_s5_inc_spwr_rq & pavr_s5_dec_spwr_rq &
+ pavr_s5_calldec_spwr_rq & pavr_s51_calldec_spwr_rq & pavr_s52_calldec_spwr_rq &
+ pavr_s5_retinc2_spwr_rq & pavr_s51_retinc_spwr_rq;
+
+ case v_spwrrq_sel is
+ -- No SP write requests. Set SP inputs to a most benign state. Only change inputs when write is requested, to minimize power consumption.
+ when "0000000" =>
+ pavr_iof_spl_wr <= '0';
+ pavr_iof_spl_di <= int_to_std_logic_vector(0, pavr_iof_spl_di'length);
+ pavr_iof_sph_wr <= '0';
+ pavr_iof_sph_di <= int_to_std_logic_vector(0, pavr_iof_sph_di'length);
+ -- Increment SP request. For devices with 256B or less of Unified Memory, only update lower byte of SP. For the other devices, modify all 16 bits of SP.
+ when "1000000" =>
+ -- Stall capability in s5.
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ if pavr_dm_bigger_than_256='0' then
+ pavr_iof_spl_wr <= '1';
+ pavr_iof_spl_di <= v_sp_inc(7 downto 0);
+ pavr_iof_sph_wr <= '0';
+ pavr_iof_sph_di <= int_to_std_logic_vector(0, pavr_iof_sph_di'length);
+ else
+ pavr_iof_spl_wr <= '1';
+ pavr_iof_spl_di <= v_sp_inc(7 downto 0);
+ pavr_iof_sph_wr <= '1';
+ pavr_iof_sph_di <= v_sp_inc(15 downto 8);
+ end if;
+ end if;
+ -- Increment SP request. For devices with 256B or less of Unified Memory, only update lower byte of SP. For the other devices, modify all 16 bits of SP.
+ when "0000001" =>
+ if pavr_dm_bigger_than_256='0' then
+ pavr_iof_spl_wr <= '1';
+ pavr_iof_spl_di <= v_sp_inc(7 downto 0);
+ pavr_iof_sph_wr <= '0';
+ pavr_iof_sph_di <= int_to_std_logic_vector(0, pavr_iof_sph_di'length);
+ else
+ pavr_iof_spl_wr <= '1';
+ pavr_iof_spl_di <= v_sp_inc(7 downto 0);
+ pavr_iof_sph_wr <= '1';
+ pavr_iof_sph_di <= v_sp_inc(15 downto 8);
+ end if;
+ -- Increment by 2 SP request.
+ when "0000010" =>
+ -- Stall capability in s5.
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ if pavr_dm_bigger_than_256='0' then
+ pavr_iof_spl_wr <= '1';
+ pavr_iof_spl_di <= v_sp_inc2(7 downto 0);
+ pavr_iof_sph_wr <= '0';
+ pavr_iof_sph_di <= int_to_std_logic_vector(0, pavr_iof_sph_di'length);
+ else
+ pavr_iof_spl_wr <= '1';
+ pavr_iof_spl_di <= v_sp_inc2(7 downto 0);
+ pavr_iof_sph_wr <= '1';
+ pavr_iof_sph_di <= v_sp_inc2(15 downto 8);
+ end if;
+ end if;
+ -- Decrement SP request.
+ when "0100000" | "0010000" =>
+ -- Stall capability in s5.
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ if pavr_dm_bigger_than_256='0' then
+ pavr_iof_spl_wr <= '1';
+ pavr_iof_spl_di <= v_sp_dec(7 downto 0);
+ pavr_iof_sph_wr <= '0';
+ pavr_iof_sph_di <= int_to_std_logic_vector(0, pavr_iof_sph_di'length);
+ else
+ pavr_iof_spl_wr <= '1';
+ pavr_iof_spl_di <= v_sp_dec(7 downto 0);
+ pavr_iof_sph_wr <= '1';
+ pavr_iof_sph_di <= v_sp_dec(15 downto 8);
+ end if;
+ end if;
+ -- Decrement SP request.
+ when "0000100" | "0001000" =>
+ if pavr_dm_bigger_than_256='0' then
+ pavr_iof_spl_wr <= '1';
+ pavr_iof_spl_di <= v_sp_dec(7 downto 0);
+ pavr_iof_sph_wr <= '0';
+ pavr_iof_sph_di <= int_to_std_logic_vector(0, pavr_iof_sph_di'length);
+ else
+ pavr_iof_spl_wr <= '1';
+ pavr_iof_spl_di <= v_sp_dec(7 downto 0);
+ pavr_iof_sph_wr <= '1';
+ pavr_iof_sph_di <= v_sp_dec(15 downto 8);
+ end if;
+ when others =>
+ -- Multiple requests shouldn't happen.
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "SP error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+ end process spwr_manager;
+
+
+
+ -- RAMPX-related
+ -- Set the signals:
+ -- - pavr_iof_rampx_wr
+ -- - pavr_iof_rampx_di
+ rampxwr_manager:
+ process(pavr_s5_ldstincrampx_xwr_rq,
+ pavr_s5_ldstdecrampx_xwr_rq,
+
+ pavr_stall_s5,
+ pavr_flush_s5,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_iof_rampx_di,
+ pavr_iof_rampx,
+ pavr_xbpu
+ )
+ variable v_rampxwrrq_sel: std_logic_vector(1 downto 0);
+ variable v_xrampx_inc : std_logic_vector(23 downto 0);
+ variable v_xrampx_dec : std_logic_vector(23 downto 0);
+ begin
+ pavr_iof_rampx_wr <= '0';
+ pavr_iof_rampx_di <= int_to_std_logic_vector(0, pavr_iof_rampx_di'length);
+
+ v_xrampx_inc := (pavr_iof_rampx & pavr_xbpu) + 1;
+ v_xrampx_dec := (pavr_iof_rampx & pavr_xbpu) - 1;
+
+ v_rampxwrrq_sel := pavr_s5_ldstincrampx_xwr_rq & pavr_s5_ldstdecrampx_xwr_rq;
+ case v_rampxwrrq_sel is
+ -- No RAMPX write requests. Nothing to be done.
+ when "00" =>
+ null;
+ -- Increment RAMPX:X request.
+ when "10" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ if pavr_dm_bigger_than_64K='1' then
+ pavr_iof_rampx_wr <= '1';
+ pavr_iof_rampx_di <= v_xrampx_inc(23 downto 16);
+ end if;
+ end if;
+ -- Decrement RAMPX:X request.
+ when "01" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ if pavr_dm_bigger_than_64K='1' then
+ pavr_iof_rampx_wr <= '1';
+ pavr_iof_rampx_di <= v_xrampx_dec(23 downto 16);
+ end if;
+ end if;
+ when others =>
+ -- Multiple requests shouldn't happen.
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "RAMPX error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+ end process rampxwr_manager;
+
+
+
+ -- RAMPY-related
+ -- Set the signals:
+ -- - pavr_iof_rampy_wr
+ -- - pavr_iof_rampy_di
+ rampywr_manager:
+ process(pavr_s5_ldstincrampy_ywr_rq,
+ pavr_s5_ldstdecrampy_ywr_rq,
+
+ pavr_stall_s5,
+ pavr_flush_s5,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_iof_rampy_di,
+ pavr_iof_rampy,
+ pavr_ybpu
+ )
+ variable v_rampywrrq_sel: std_logic_vector(1 downto 0);
+ variable v_yrampy_inc : std_logic_vector(23 downto 0);
+ variable v_yrampy_dec : std_logic_vector(23 downto 0);
+ begin
+ pavr_iof_rampy_wr <= '0';
+ pavr_iof_rampy_di <= int_to_std_logic_vector(0, pavr_iof_rampy_di'length);
+
+ v_yrampy_inc := (pavr_iof_rampy & pavr_ybpu) + 1;
+ v_yrampy_dec := (pavr_iof_rampy & pavr_ybpu) - 1;
+
+ v_rampywrrq_sel := pavr_s5_ldstincrampy_ywr_rq & pavr_s5_ldstdecrampy_ywr_rq;
+ case v_rampywrrq_sel is
+ -- No RAMPY write requests. Nothing to be done.
+ when "00" =>
+ null;
+ -- Increment RAMPY:Y request.
+ when "10" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ if pavr_dm_bigger_than_64K='1' then
+ pavr_iof_rampy_wr <= '1';
+ pavr_iof_rampy_di <= v_yrampy_inc(23 downto 16);
+ end if;
+ end if;
+ -- Decrement RAMPY:Y request.
+ when "01" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ if pavr_dm_bigger_than_64K='1' then
+ pavr_iof_rampy_wr <= '1';
+ pavr_iof_rampy_di <= v_yrampy_dec(23 downto 16);
+ end if;
+ end if;
+ when others =>
+ -- Multiple requests shouldn't happen.
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "RAMPY error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+ end process rampywr_manager;
+
+
+
+ -- RAMPZ-related
+ -- Set the signals:
+ -- - pavr_iof_rampz_wr
+ -- - pavr_iof_rampz_di
+ rampzwr_manager:
+ process(pavr_s5_ldstincrampz_zwr_rq,
+ pavr_s5_ldstdecrampz_zwr_rq,
+ pavr_s5_elpmincrampz_zwr_rq,
+
+ pavr_stall_s5,
+ pavr_flush_s5,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_iof_rampz_di,
+ pavr_iof_rampz,
+ pavr_zbpu
+ )
+ variable v_rampzwrrq_sel: std_logic_vector(2 downto 0);
+ variable v_zrampz_inc : std_logic_vector(23 downto 0);
+ variable v_zrampz_dec : std_logic_vector(23 downto 0);
+ begin
+ pavr_iof_rampz_wr <= '0';
+ pavr_iof_rampz_di <= int_to_std_logic_vector(0, pavr_iof_rampz_di'length);
+
+ v_zrampz_inc := (pavr_iof_rampz & pavr_zbpu) + 1;
+ v_zrampz_dec := (pavr_iof_rampz & pavr_zbpu) - 1;
+
+ v_rampzwrrq_sel := pavr_s5_ldstincrampz_zwr_rq & pavr_s5_ldstdecrampz_zwr_rq & pavr_s5_elpmincrampz_zwr_rq;
+ case v_rampzwrrq_sel is
+ -- No RAMPZ write requests. Nothing to be done.
+ when "000" =>
+ null;
+ -- Increment RAMPZ:Z request.
+ when "100" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ if pavr_dm_bigger_than_64K='1' then
+ pavr_iof_rampz_wr <= '1';
+ pavr_iof_rampz_di <= v_zrampz_inc(23 downto 16);
+ end if;
+ end if;
+ -- Decrement RAMPZ:Z request.
+ when "010" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ if pavr_dm_bigger_than_64K='1' then
+ pavr_iof_rampz_wr <= '1';
+ pavr_iof_rampz_di <= v_zrampz_dec(23 downto 16);
+ end if;
+ end if;
+ -- Increment RAMPZ:Z request from ELPM instruction.
+ when "001" =>
+ if pavr_stall_s5='0' and pavr_flush_s5='0' then
+ pavr_iof_rampz_wr <= '1';
+ pavr_iof_rampz_di <= v_zrampz_inc(23 downto 16);
+ end if;
+ when others =>
+ -- Multiple requests shouldn't happen.
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "RAMPZ error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+ end process rampzwr_manager;
+
+
+
+ -- RAMPD-related
+ -- *** Void manager. No instruction needs to write RAMPD.
+ rampdwr_manager:
+ process(pavr_iof_rampd_di)
+ begin
+ pavr_iof_rampd_wr <= '0';
+ pavr_iof_rampd_di <= int_to_std_logic_vector(0, pavr_iof_rampd_di'length);
+ end process rampdwr_manager;
+
+
+
+ -- EIND-related
+ -- *** Void manager. No instruction needs to write EIND.
+ eindwr_manager:
+ process(pavr_iof_eind_di)
+ begin
+ pavr_iof_eind_wr <= '0';
+ pavr_iof_eind_di <= int_to_std_logic_vector(0, pavr_iof_eind_di'length);
+ end process eindwr_manager;
+
+
+
+ -- ALU-related
+ -- The ALU is not a potentially conflicting resource. There's no need to
+ -- arbitrate requests to ALU. This section only takes care of setting ALU-
+ -- related signals, that feed ALU inputs and connect its outputs to other
+ -- modules.
+ -- Set the signals:
+ -- - pavr_s5_alu_op1
+ -- - pavr_s5_alu_op2
+ alu_manager:
+ process(pavr_s5_alu_op1,
+ pavr_s5_alu_op2,
+ pavr_s5_alu_op1_hi8_sel,
+ pavr_s5_op2bpu,
+ pavr_s5_op1bpu,
+ pavr_s5_alu_op2_sel,
+ pavr_s5_op2bpu,
+ pavr_s5_k8
+ )
+ begin
+ pavr_s5_alu_op1 <= int_to_std_logic_vector(0, pavr_s5_alu_op1'length);
+ pavr_s5_alu_op2 <= int_to_std_logic_vector(0, pavr_s5_alu_op2'length);
+
+ case pavr_s5_alu_op1_hi8_sel is
+ when pavr_alu_op1_hi8_sel_zero =>
+ pavr_s5_alu_op1(15 downto 8) <= int_to_std_logic_vector(0, 8);
+ when others =>
+ pavr_s5_alu_op1(15 downto 8) <= pavr_s5_op2bpu;
+ end case;
+
+ pavr_s5_alu_op1( 7 downto 0) <= pavr_s5_op1bpu;
+
+ case pavr_s5_alu_op2_sel is
+ when pavr_alu_op2_sel_op2bpu =>
+ pavr_s5_alu_op2 <= pavr_s5_op2bpu;
+ when pavr_alu_op2_sel_k8 =>
+ pavr_s5_alu_op2 <= pavr_s5_k8;
+ when pavr_alu_op2_sel_1 =>
+ pavr_s5_alu_op2 <= int_to_std_logic_vector(1, 8);
+ when others =>
+ pavr_s5_alu_op2 <= int_to_std_logic_vector(-1, 8);
+ end case;
+
+ end process alu_manager;
+
+
+
+ -- DACU read and write-related
+ -- Set the signals:
+ -- - pavr_s5_dacu_rfrd1_rq
+ -- - pavr_s5_dacust_rf_addr
+ -- - pavr_s5_dacu_rfwr_rq
+ -- - pavr_s5_dacu_rfwr_di
+ --
+ -- - pavr_s5_dacu_iof_rq
+ -- - pavr_s5_dacu_iof_addr
+ -- - pavr_s5_dacu_iof_opcode
+ -- - pavr_s5_dacu_iofwr_di
+ --
+ -- - pavr_s5_dacu_dmrd_rq
+ -- - pavr_s5_dacu_dm_addr
+ -- - pavr_s5_dacu_dmwr_rq
+ -- - pavr_s5_dacu_dmwr_di
+ --
+ -- - pavr_s5_dacust_bpr0wr_rq
+ --
+ -- - pavr_s5_dacudo_sel
+ -- - pavr_s6_dacudo_sel
+ --
+ -- - pavr_dacu_do
+ dacu_manager:
+ process(
+ -- DACU read-related requests
+ pavr_s5_x_dacurd_rq, pavr_s5_y_dacurd_rq, pavr_s5_z_dacurd_rq,
+ pavr_s5_sp_dacurd_rq,
+ pavr_s5_k16_dacurd_rq,
+ pavr_s5_pchi8_dacurd_rq, pavr_s51_pcmid8_dacurd_rq, pavr_s52_pclo8_dacurd_rq,
+
+ -- DACU write-related requests
+ pavr_s5_x_dacuwr_rq, pavr_s5_y_dacuwr_rq, pavr_s5_z_dacuwr_rq,
+ pavr_s5_sp_dacuwr_rq,
+ pavr_s5_k16_dacuwr_rq,
+ pavr_s5_pclo8_dacuwr_rq, pavr_s51_pcmid8_dacuwr_rq, pavr_s52_pchi8_dacuwr_rq,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_xbpu,
+ pavr_ybpu,
+ pavr_zbpu,
+ pavr_s5_dacust_rf_addr,
+ pavr_s5_dacu_rfwr_di,
+ pavr_s5_dacu_iof_addr,
+ pavr_s5_dacu_iofwr_di,
+ pavr_s5_dacu_dm_addr,
+ pavr_s5_dacu_dmwr_di,
+ pavr_s5_dacu_iof_opcode,
+ pavr_s5_dacudo_sel,
+ pavr_dacu_do,
+ pavr_s4_dacu_q,
+ pavr_iof_rampx,
+ pavr_iof_rampy,
+ pavr_iof_rampz,
+ pavr_iof_spl,
+ pavr_iof_sph,
+ pavr_s5_k16,
+ pavr_iof_rampd,
+ pavr_s5_rf_dacu_q,
+ pavr_s5_iof_dacu_q,
+ pavr_s5_dm_dacu_q,
+ pavr_s6_dacudo_sel,
+ pavr_s5_op1bpu,
+ pavr_s5_pc,
+ pavr_rf_rd1_do,
+ pavr_iof_do,
+ pavr_dm_do
+ )
+ variable tmpv_rd : std_logic_vector(7 downto 0);
+ variable tmpv_wr : std_logic_vector(7 downto 0);
+ variable tmpv_rdwr : std_logic_vector(7 downto 0);
+ variable v_dacu_wr_di: std_logic_vector(7 downto 0);
+ variable v_pavr_s5_dacu_ptr : std_logic_vector(23 downto 0);
+ variable v_pavr_s5_rf_dacu_addrtest : std_logic_vector(24 downto 0);
+ variable v_pavr_s5_iof_dacu_addrtest : std_logic_vector(24 downto 0);
+ variable v_pavr_s5_dm_dacu_addrtest : std_logic_vector(24 downto 0);
+ variable v_pavr_dacu_device_sel : std_logic_vector(pavr_dacu_device_sel_w - 1 downto 0);
+ begin
+ pavr_s5_dacu_rfrd1_rq <= '0';
+ pavr_s5_dacu_rfwr_rq <= '0';
+ pavr_s5_dacu_rfwr_di <= int_to_std_logic_vector(0, pavr_s5_dacu_rfwr_di'length);
+ pavr_s5_dacu_iof_rq <= '0';
+ pavr_s5_dacu_iofwr_di <= int_to_std_logic_vector(0, pavr_s5_dacu_iofwr_di'length);
+ pavr_s5_dacu_dmrd_rq <= '0';
+ pavr_s5_dacu_dmwr_rq <= '0';
+ pavr_s5_dacu_dmwr_di <= int_to_std_logic_vector(0, pavr_s5_dacu_dmwr_di'length);
+ pavr_s5_dacust_bpr0wr_rq <= '0';
+ pavr_s5_dacust_rf_addr <= int_to_std_logic_vector(0, pavr_s5_dacust_rf_addr'length);
+ pavr_s5_dacu_iof_addr <= int_to_std_logic_vector(0, pavr_s5_dacu_iof_addr'length);
+ pavr_s5_dacu_dm_addr <= int_to_std_logic_vector(0, pavr_s5_dacu_dm_addr'length);
+ pavr_s5_dacu_iof_opcode <= int_to_std_logic_vector(0, pavr_s5_dacu_iof_opcode'length);
+ pavr_s5_dacudo_sel <= int_to_std_logic_vector(0, pavr_s5_dacudo_sel'length);
+ pavr_dacu_do <= int_to_std_logic_vector(0, pavr_dacu_do'length);
+
+ pavr_s4_iof_dacu_q <= pavr_s4_dacu_q - 32;
+ pavr_s4_dm_dacu_q <= pavr_s4_dacu_q - 96;
+
+ tmpv_rd := int_to_std_logic_vector(0, tmpv_rd'length);
+ tmpv_wr := int_to_std_logic_vector(0, tmpv_wr'length);
+ tmpv_rdwr := int_to_std_logic_vector(0, tmpv_rdwr'length);
+ v_dacu_wr_di := int_to_std_logic_vector(0, v_dacu_wr_di'length);
+ v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, v_pavr_s5_dacu_ptr'length);
+ v_pavr_s5_rf_dacu_addrtest := int_to_std_logic_vector(0, v_pavr_s5_rf_dacu_addrtest'length);
+ v_pavr_s5_iof_dacu_addrtest := int_to_std_logic_vector(0, v_pavr_s5_iof_dacu_addrtest'length);
+ v_pavr_s5_dm_dacu_addrtest := int_to_std_logic_vector(0, v_pavr_s5_dm_dacu_addrtest'length);
+ v_pavr_dacu_device_sel := int_to_std_logic_vector(0, v_pavr_dacu_device_sel'length);
+
+ -- This vector holds the DACU read requests.
+ tmpv_rd := pavr_s5_x_dacurd_rq & pavr_s5_y_dacurd_rq & pavr_s5_z_dacurd_rq &
+ pavr_s5_sp_dacurd_rq &
+ pavr_s5_k16_dacurd_rq &
+ pavr_s5_pchi8_dacurd_rq & pavr_s51_pcmid8_dacurd_rq & pavr_s52_pclo8_dacurd_rq;
+ -- This vector holds the DACU write requests.
+ tmpv_wr := pavr_s5_x_dacuwr_rq & pavr_s5_y_dacuwr_rq & pavr_s5_z_dacuwr_rq &
+ pavr_s5_sp_dacuwr_rq &
+ pavr_s5_k16_dacuwr_rq &
+ pavr_s5_pclo8_dacuwr_rq & pavr_s51_pcmid8_dacuwr_rq & pavr_s52_pchi8_dacuwr_rq;
+ -- This vector holds the requests to DACU access (for write or read). Note
+ -- that (coincidentaly or not) all the DACU access requests for read have
+ -- a mirror pair for write access. OR-ing read with write access requests
+ -- (taking care to pair correctly read and write mirror images) will
+ -- result in a pattern that can be used to select the proper source for
+ -- the DACU address, when computing the Unified Memory address.
+ tmpv_rdwr := tmpv_rd or tmpv_wr;
+ case tmpv_rdwr is
+ -- No DACU access requests.
+ when "00000000" =>
+ v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, v_pavr_s5_dacu_ptr'length);
+ -- DACU access requests from/to Unified Memory address given by X (and RAMPX) pointer register.
+ when "10000000" =>
+ if pavr_dm_bigger_than_256='0' then
+ v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 16) & pavr_xbpu(7 downto 0);
+ elsif pavr_dm_bigger_than_64K='0' then
+ v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 8) & pavr_xbpu;
+ else
+ v_pavr_s5_dacu_ptr := pavr_iof_rampx & pavr_xbpu;
+ end if;
+ -- DACU access requests from/to Unified Memory address given by Y (and RAMPY) pointer register.
+ when "01000000" =>
+ if pavr_dm_bigger_than_256='0' then
+ v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 16) & pavr_ybpu(7 downto 0);
+ elsif pavr_dm_bigger_than_64K='0' then
+ v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 8) & pavr_ybpu;
+ else
+ v_pavr_s5_dacu_ptr := pavr_iof_rampy & pavr_ybpu;
+ end if;
+ -- DACU access requests from/to Unified Memory address given by Z (and RAMPZ) pointer register.
+ when "00100000" =>
+ if pavr_dm_bigger_than_256='0' then
+ v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 16) & pavr_zbpu(7 downto 0);
+ elsif pavr_dm_bigger_than_64K='0' then
+ v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 8) & pavr_zbpu;
+ else
+ v_pavr_s5_dacu_ptr := pavr_iof_rampz & pavr_zbpu;
+ end if;
+ -- DACU access requests from/to Unified Memory address given by SP.
+ when "00010000" |
+ "00000100" | "00000010" | "00000001" =>
+ if pavr_dm_bigger_than_256='0' then
+ v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 16) & pavr_iof_spl;
+ else
+ v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 8) & pavr_iof_sph & pavr_iof_spl;
+ end if;
+ -- DACU access requests from/to Unified Memory address given by a 16 bit constant (pavr_s5_k16).
+ when "00001000" =>
+ if pavr_dm_bigger_than_256='0' then
+ v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 16) & pavr_s5_k16(7 downto 0);
+ elsif pavr_dm_bigger_than_64K='0' then
+ v_pavr_s5_dacu_ptr := int_to_std_logic_vector(0, 8) & pavr_s5_k16;
+ else
+ v_pavr_s5_dacu_ptr := pavr_iof_rampd & pavr_s5_k16;
+ end if;
+ when others =>
+ -- Multiple requests shouldn't happen.
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "DACU error."
+ severity warning;
+ end if;
+ --
+ null;
+
+ end case;
+
+ v_pavr_s5_rf_dacu_addrtest := v_pavr_s5_dacu_ptr + sign_extend(pavr_s5_rf_dacu_q, 25);
+ v_pavr_s5_iof_dacu_addrtest := v_pavr_s5_dacu_ptr + sign_extend(pavr_s5_iof_dacu_q, 25);
+ v_pavr_s5_dm_dacu_addrtest := v_pavr_s5_dacu_ptr + sign_extend(pavr_s5_dm_dacu_q, 25);
+
+ -- If none of the 3 tests below results in positive addresses, use DM.
+ v_pavr_dacu_device_sel := pavr_dacu_device_sel_dm;
+ -- Test which device to use, RF/IOF/DM. Remember that the Unified Memory is composed of these 3 entities.
+ if v_pavr_s5_rf_dacu_addrtest(24)='0' then
+ v_pavr_dacu_device_sel := pavr_dacu_device_sel_rf;
+ end if;
+ if v_pavr_s5_iof_dacu_addrtest(24)='0' then
+ v_pavr_dacu_device_sel := pavr_dacu_device_sel_iof;
+ end if;
+ if v_pavr_s5_dm_dacu_addrtest(24)='0' then
+ v_pavr_dacu_device_sel := pavr_dacu_device_sel_dm;
+ end if;
+ -- Now we know what device to access during UM requests. That info is stored in `v_pavr_dacu_device_sel'.
+
+ -- Manage DACU read requests.
+ if tmpv_rd/="00000000" then
+ case v_pavr_dacu_device_sel is
+ -- UM read request is decoded into RF read port 1 access request.
+ when pavr_dacu_device_sel_rf =>
+ pavr_s5_dacu_rfrd1_rq <= '1';
+ pavr_s5_dacust_rf_addr <= v_pavr_s5_rf_dacu_addrtest(4 downto 0);
+ pavr_s5_dacudo_sel <= pavr_dacudo_sel_rfrd1do;
+ -- UM read request is decoded into IOF port access request.
+ when pavr_dacu_device_sel_iof =>
+ pavr_s5_dacu_iof_rq <= '1';
+ pavr_s5_dacu_iof_addr <= v_pavr_s5_iof_dacu_addrtest(5 downto 0);
+ pavr_s5_dacu_iof_opcode <= pavr_iof_opcode_rdbyte;
+ pavr_s5_dacudo_sel <= pavr_dacudo_sel_iofdo;
+ -- UM read request is decoded into DM port access request.
+ when others =>
+ pavr_s5_dacu_dmrd_rq <= '1';
+ pavr_s5_dacu_dm_addr <= v_pavr_s5_dm_dacu_addrtest(23 downto 0);
+ pavr_s5_dacudo_sel <= pavr_dacudo_sel_dmdo;
+ end case;
+ end if;
+
+ -- DACU data out. Select data out from proper device (RF/IOF/DM).
+ case pavr_s6_dacudo_sel is
+ -- *** Bypass shadow protocol.
+ when pavr_dacudo_sel_rfrd1do =>
+ --if pavr_rf_do_shadow_active='0' then
+ pavr_dacu_do <= pavr_rf_rd1_do;
+ --else
+ -- pavr_dacu_do <= pavr_rf_rd1_do_shadow;
+ --end if;
+ when pavr_dacudo_sel_iofdo =>
+ --if pavr_iof_do_shadow_active='0' then
+ pavr_dacu_do <= pavr_iof_do;
+ --else
+ -- pavr_dacu_do <= pavr_iof_do_shadow;
+ --end if;
+ -- When pavr_dacudo_sel_dmdo
+ when others =>
+ --if pavr_dm_do_shadow_active='0' then
+ pavr_dacu_do <= pavr_dm_do;
+ --else
+ -- pavr_dacu_do <= pavr_dm_do_shadow;
+ --end if;
+ end case;
+
+ -- Manage DACU write requests.
+ case tmpv_wr is
+ -- Nothing to be done.
+ when "00000000" =>
+ null;
+ -- X, Y, Z, SP or k16 DACUWR request
+ when "10000000" | "01000000" | "00100000" | "00010000" | "00001000"=>
+ v_dacu_wr_di := pavr_s5_op1bpu;
+ -- SP DACUWR request, data in = pclo8
+ when "00000100" =>
+ v_dacu_wr_di := pavr_s5_pc(7 downto 0);
+ -- SP DACUWR request, data in = pcmid8
+ when "00000010" =>
+ v_dacu_wr_di := pavr_s5_pc(15 downto 8);
+ -- SP DACUWR request, data in = pchi8
+ when others =>
+ v_dacu_wr_di := "00" & pavr_s5_pc(21 downto 16);
+ end case;
+ if tmpv_wr/="00000000" then
+ case v_pavr_dacu_device_sel is
+ -- UM write request is decoded into RF write port access request.
+ when pavr_dacu_device_sel_rf =>
+ pavr_s5_dacu_rfwr_rq <= '1';
+ pavr_s5_dacust_rf_addr <= v_pavr_s5_rf_dacu_addrtest(4 downto 0);
+ pavr_s5_dacust_bpr0wr_rq <= '1'; -- *** Take care to also update BPU. Note that it will happen next clock.
+ pavr_s5_dacu_rfwr_di <= v_dacu_wr_di;
+ -- UM write request is decoded into IOF port access request.
+ when pavr_dacu_device_sel_iof =>
+ pavr_s5_dacu_iof_rq <= '1';
+ pavr_s5_dacu_iof_addr <= v_pavr_s5_iof_dacu_addrtest(5 downto 0);
+ pavr_s5_dacu_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_s5_dacu_iofwr_di <= v_dacu_wr_di;
+ -- UM write request is decoded into DM port access request.
+ when others =>
+ pavr_s5_dacu_dmwr_rq <= '1';
+ pavr_s5_dacu_dm_addr <= v_pavr_s5_dm_dacu_addrtest(23 downto 0);
+ pavr_s5_dacu_dmwr_di <= v_dacu_wr_di;
+ end case;
+ end if;
+ end process dacu_manager;
+
+
+
+ -- DM-related
+ -- Set the signals:
+ -- - pavr_dm_wr
+ -- - pavr_dm_addr
+ -- - pavr_dm_di
+ dm_manager:
+ process(pavr_s5_dacu_dmrd_rq,
+ pavr_s5_dacu_dmwr_rq,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_dm_addr,
+ pavr_dm_di,
+ pavr_s5_dacu_dm_addr,
+ pavr_s5_dacu_dmwr_di
+ )
+ variable v_dmrq_sel: std_logic_vector(1 downto 0);
+ begin
+ pavr_dm_wr <= '0';
+ pavr_dm_addr <= int_to_std_logic_vector(0, pavr_dm_addr'length);
+ pavr_dm_di <= int_to_std_logic_vector(0, pavr_dm_di'length);
+
+ -- Note that DACU is the only unit that requests read/write accesses to DM.
+ v_dmrq_sel := pavr_s5_dacu_dmrd_rq & pavr_s5_dacu_dmwr_rq;
+ case v_dmrq_sel is
+ -- No DM access requests. Nothing to be done.
+ when "00" =>
+ null;
+ -- Read DM request
+ when "10" =>
+ pavr_dm_wr <= '0';
+ pavr_dm_addr <= pavr_s5_dacu_dm_addr(pavr_dm_addr'length - 1 downto 0);
+ pavr_dm_di <= int_to_std_logic_vector(0, pavr_dm_di'length);
+ -- Write DM request
+ when "01" =>
+ pavr_dm_wr <= '1';
+ pavr_dm_addr <= pavr_s5_dacu_dm_addr(pavr_dm_addr'length - 1 downto 0);
+ pavr_dm_di <= pavr_s5_dacu_dmwr_di;
+ when others =>
+ -- Multiple requests shouldn't happen.
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "Data Memory error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+ end process dm_manager;
+
+
+
+ -- PM access-related
+ -- Load PC here. Some PM access requests modify the PC, others don't. The only
+ -- PM requests that don't modify the PC are the loads from PM (LPM and ELPM
+ -- instructions). The other requests correspond to instructions that
+ -- want to modify the instruction flow, thus modify the PC (jumps, branches
+ -- calls, returns).
+ -- Set the signals:
+ -- - pavr_pm_addr_int
+ -- - next_pavr_s1_pc
+ -- - next_pavr_s2_pmdo_valid
+ pm_manager:
+ process(pavr_s5_lpm_pm_rq,
+ pavr_s5_elpm_pm_rq,
+ pavr_s4_z_pm_rq,
+ pavr_s4_zeind_pm_rq,
+ pavr_s4_k22abs_pm_rq,
+ pavr_s4_k12rel_pm_rq,
+ pavr_s6_branch_pm_rq,
+ pavr_s6_skip_pm_rq,
+ pavr_s61_skip_pm_rq,
+ pavr_s4_k22int_pm_rq,
+ pavr_s54_ret_pm_rq,
+
+ pavr_s4_hwrq_en,
+ pavr_s5_hwrq_en,
+ pavr_s6_hwrq_en,
+ pavr_s61_hwrq_en,
+
+ pavr_stall_s1,
+ pavr_stall_s2,
+ pavr_flush_s2,
+ pavr_s2_pc,
+ pavr_s3_pc,
+
+ --
+ pavr_s2_pmdo_valid,
+ --
+
+ pavr_grant_control_flow_access,
+ pavr_pm_do_shadow_active,
+ pavr_pm_do_shadow,
+ pavr_pm_do,
+
+ pavr_zbpu,
+ pavr_s1_pc,
+ pavr_s4_k12,
+ pavr_s4_pc,
+ pavr_iof_rampz,
+ pavr_iof_eind,
+ pavr_s4_k6,
+ pavr_s3_instr,
+ pavr_s6_branch_pc,
+ pavr_s4_k22int,
+ pavr_s52_retpchi8,
+ pavr_s53_retpcmid8,
+ pavr_s54_retpclo8,
+ pavr_pm_addr_int
+ )
+ variable v_pmrq_sel: std_logic_vector(10 downto 0);
+ variable v_pavr_pc_sel: std_logic;
+
+ variable v_22b_op1: std_logic_vector(22 downto 0);
+ variable v_22b_op2: std_logic_vector(22 downto 0);
+ variable v_pavr_pc_k12rel_23b: std_logic_vector(22 downto 0);
+ variable v_grant_s2_pm_access: std_logic;
+ --variable pavr_grant_control_flow_access: std_logic;
+ variable v_freeze_control_flow: std_logic;
+ variable v_instr32bits_tmp1: std_logic_vector(9 downto 0);
+ variable v_instr32bits_tmp2: std_logic_vector(8 downto 0);
+ variable v_instr32bits: std_logic;
+
+ begin
+ -- Default values:
+ -- - PM addr = PC
+ -- - next PC = crt PC + 1.
+ -- - don't grant access to control flow (enabled later if requested)
+ -- - grant PM access (disabled later if the instruction doesn't
+ -- explicitely requests it)
+ -- - don't freeze control flow (enabled later if a LPM family
+ -- requests PM access)
+ pavr_pm_addr_int <= pavr_s1_pc;
+ v_pavr_pc_sel := pavr_pc_sel_inc;
+ v_grant_s2_pm_access := '1';
+ v_freeze_control_flow := '0';
+ pavr_grant_control_flow_access <= '0';
+
+ -- Detect if the instruction to stall is 16 bits or 32 bits wide.
+ -- Is it a LDS or a STS?
+ v_instr32bits_tmp1 := pavr_s3_instr(15 downto 10) & pavr_s3_instr(3 downto 0);
+ -- Is it a JMP or a CALL?
+ v_instr32bits_tmp2 := pavr_s3_instr(15 downto 9) & pavr_s3_instr(3 downto 2);
+ if v_instr32bits_tmp1="1001000000" or v_instr32bits_tmp2="100101011" then
+ v_instr32bits := '1';
+ else
+ v_instr32bits := '0';
+ end if;
+
+ -- Add 12 bits offset with current instruction's PC and with 1. The result
+ -- is the relative address needed by intructions RJMP/RCALL.
+ v_22b_op1(0) := '1';
+ v_22b_op2(0) := '1';
+ if pavr_s6_branch_pm_rq='1' then
+ if v_instr32bits ='0' then
+ v_22b_op1(22 downto 1) := sign_extend("01", 22);
+ v_22b_op2(22 downto 1) := pavr_s4_pc;
+ else
+ v_22b_op1(22 downto 1) := sign_extend("00", 22);
+ v_22b_op2(22 downto 1) := pavr_s4_pc;
+ end if;
+ else
+ v_22b_op1(22 downto 1) := sign_extend(pavr_s4_k12, 22);
+ v_22b_op2(22 downto 1) := pavr_s4_pc;
+ end if;
+ v_pavr_pc_k12rel_23b := v_22b_op1 + v_22b_op2;
+
+ v_pmrq_sel := (pavr_s5_lpm_pm_rq and pavr_s5_hwrq_en) &
+ (pavr_s5_elpm_pm_rq and pavr_s5_hwrq_en) &
+ (pavr_s4_z_pm_rq and pavr_s4_hwrq_en) &
+ (pavr_s4_zeind_pm_rq and pavr_s4_hwrq_en) &
+ (pavr_s4_k22abs_pm_rq and pavr_s4_hwrq_en) &
+ (pavr_s4_k12rel_pm_rq and pavr_s4_hwrq_en) &
+ (pavr_s6_branch_pm_rq and pavr_s6_hwrq_en) &
+ (pavr_s6_skip_pm_rq and pavr_s6_hwrq_en) &
+ pavr_s61_skip_pm_rq &
+ (pavr_s4_k22int_pm_rq and pavr_s4_hwrq_en) &
+ pavr_s54_ret_pm_rq;
+ case v_pmrq_sel is
+ -- No PM access requests. Don't grant access to PM.
+ when "00000000000" =>
+ v_grant_s2_pm_access := '0';
+ -- LPM PM request. Freeze PC.
+ when "10000000000" =>
+ -- Only take action if permitted by older instructions.
+ -- *** Note that the condition is stall enabled in s6, not s5. That's
+ -- because LPM stalls s5 at the same time it tries to read PM.
+ if pavr_s6_hwrq_en='1' then
+ pavr_pm_addr_int <= int_to_std_logic_vector(0, 6) & '0' & pavr_zbpu(15 downto 1);
+ v_pavr_pc_sel := pavr_pc_sel_same;
+ v_freeze_control_flow := '1';
+ end if;
+ -- ELPM PM request. Freeze PC.
+ when "01000000000" =>
+ -- *** Note that the condition is stall enabled in s6, not s5. That's
+ -- because ELPM stalls s5 at the same time it tries to read PM.
+ if pavr_s6_hwrq_en='1' then
+ pavr_pm_addr_int <= '0' & pavr_iof_rampz(5 downto 0) & pavr_zbpu(15 downto 1);
+ v_pavr_pc_sel := pavr_pc_sel_same;
+ v_freeze_control_flow := '1';
+ end if;
+ -- IJMP/ICALL PM request.
+ when "00100000000" =>
+ if pavr_s4_hwrq_en='1' then
+ pavr_pm_addr_int <= int_to_std_logic_vector(0, 6) & pavr_zbpu;
+ pavr_grant_control_flow_access <= '1';
+ end if;
+ -- EIJMP/EICALL PM request.
+ when "00010000000" =>
+ if pavr_s4_hwrq_en='1' then
+ pavr_pm_addr_int <= pavr_iof_eind(5 downto 0) & pavr_zbpu;
+ pavr_grant_control_flow_access <= '1';
+ end if;
+ -- JMP/CALL PM request.
+ when "00001000000" =>
+ if pavr_s4_hwrq_en='1' then
+ pavr_pm_addr_int <= pavr_s4_k6 & pavr_s3_instr;
+ pavr_grant_control_flow_access <= '1';
+ end if;
+ -- RJMP/RCALL PM request.
+ when "00000100000" =>
+ if pavr_s4_hwrq_en='1' then
+ pavr_pm_addr_int <= v_pavr_pc_k12rel_23b(22 downto 1);
+ pavr_grant_control_flow_access <= '1';
+ end if;
+ -- Branch PM requests (SBRC, SBRS instructions).
+ when "00000010000" =>
+ if pavr_s6_hwrq_en='1' then
+ pavr_pm_addr_int <= pavr_s6_branch_pc;
+ pavr_grant_control_flow_access <= '1';
+ end if;
+ -- Skip PM requests (CPSE, SBRC, SBRS instructions).
+ when "00000001000" =>
+ if pavr_s6_hwrq_en='1' then
+ pavr_pm_addr_int <= v_pavr_pc_k12rel_23b(22 downto 1);
+ pavr_grant_control_flow_access <= '1';
+ end if;
+ -- Skip PM requests (SBIC, SBIS instructions).
+ when "00000000100" =>
+ if pavr_s61_hwrq_en='1' then
+ pavr_pm_addr_int <= v_pavr_pc_k12rel_23b(22 downto 1);
+ pavr_grant_control_flow_access <= '1';
+ end if;
+ -- Interrupt PM requests. No instruction requests this. Only the
+ -- Interrupt Manager can request this.
+ when "00000000010" =>
+ -- !!! Any condition here?
+ pavr_pm_addr_int <= pavr_s4_k22int;
+ pavr_grant_control_flow_access <= '1';
+ -- RET/RETI PM requests.
+ when "00000000001" =>
+ pavr_pm_addr_int <= pavr_s52_retpchi8(5 downto 0) & pavr_s53_retpcmid8 & pavr_s54_retpclo8;
+ pavr_grant_control_flow_access <= '1';
+ when others =>
+ --
+ if pavr_s2_pmdo_valid='1' then
+ assert false
+ report "Program Memory error."
+ severity warning;
+ end if;
+ --
+ null;
+ end case;
+
+ -- Set PM address.
+ -- Take care of potential direct PM access requests placed by control or LPM
+ -- instructions.
+ if v_grant_s2_pm_access='0' and pavr_stall_s1='1' then
+ pavr_pm_addr_int <= pavr_s1_pc;
+ end if;
+
+ -- Here is an instruction register-related code that's a workaround on an
+ -- after-reset false instruction register initializing.
+ -- During reset, PM was read. When reset lines are released, the controller
+ -- didn't wait to read the first instruction (at address 0). It
+ -- considered it already read during reset. Wrong. This corrects this
+ -- behavior.
+ if pavr_stall_s1='0' then
+ next_pavr_s2_pmdo_valid <= '1';
+ else
+ next_pavr_s2_pmdo_valid <= pavr_s2_pmdo_valid;
+ end if;
+
+ -- Now we know what to do with the PC. Do it.
+ if pavr_grant_control_flow_access='1' then
+ next_pavr_s1_pc <= pavr_pm_addr_int + 1;
+ else
+ if pavr_stall_s1='1' then
+ next_pavr_s1_pc <= pavr_s1_pc;
+ else
+ if v_pavr_pc_sel=pavr_pc_sel_same then
+ next_pavr_s1_pc <= pavr_s1_pc;
+ else
+ next_pavr_s1_pc <= pavr_pm_addr_int + 1;
+ end if;
+ end if;
+ end if;
+
+ -- pavr_s2_pc
+ if pavr_grant_control_flow_access='1' then
+ next_pavr_s2_pc <= pavr_pm_addr_int;
+ else
+ if pavr_stall_s1='1' then
+ next_pavr_s2_pc <= pavr_s2_pc;
+ else
+ next_pavr_s2_pc <= pavr_s1_pc;
+ end if;
+ end if;
+
+ -- pavr_s3_pc
+ if pavr_stall_s2='1' then
+ next_pavr_s3_pc <= pavr_s3_pc;
+ else
+ next_pavr_s3_pc <= pavr_s2_pc;
+ end if;
+
+ -- pavr_s3_instr (instruction register)
+ if pavr_flush_s2='1' or pavr_s2_pmdo_valid='0' then
+ next_pavr_s3_instr <= int_to_std_logic_vector(0, pavr_s3_instr'length);
+ else
+ if pavr_stall_s2='1' then
+ next_pavr_s3_instr <= pavr_s3_instr;
+ else
+ if pavr_pm_do_shadow_active='0' then
+ next_pavr_s3_instr <= pavr_pm_do;
+ else
+ next_pavr_s3_instr <= pavr_pm_do_shadow;
+ end if;
+ end if;
+ end if;
+
+ end process pm_manager;
+
+
+
+ -- Stall and Flush Unit (SFU)
+ -- The pipeline controls its own stall and flush status, through specific
+ -- stall and flush-related request signals. These requests are sent to
+ -- the SFU. The output of the SFU is a set of signals that directly
+ -- control pipeline stages (a stall and flush control signals pair for
+ -- each stage).
+ -- The pipeline sets up 5 kinds of stall and flush-related requests:
+ -- - stall request
+ -- The SFU stalls *all* younger stages. However, by stalling-only, the
+ -- current instruction is spawned into 2 instances. One of them must
+ -- be killed (flushed). The the younger instance is killed (the
+ -- previous stage is flushed).
+ -- Thus, a nop is introduced in the pipeline *before* the instruction
+ -- wavefront.
+ -- If more than one stage requests a stall at the same time, the older
+ -- one has priority (the younger one will be stalled along with the
+ -- others). Only after that, the younger one will be ackowledged its
+ -- stall by means of appropriate stall and flush control signals.
+ -- - flush request
+ -- The SFU simply flushes that stage.
+ -- More than one flush can be acknolewdged at the same time, without
+ -- competition.
+ -- - branch request
+ -- The SFU flushes about all stags (s2...s5) and requests
+ -- the PC to be loaded with the relative jump address.
+ -- - skip request
+ -- Skips are processed the same way as branches. However, there are 2
+ -- kinds of skips: one in stage s6 (requested by instructions CPSE,
+ -- SBRC, SBRS) and one in stage s61 (SBIC, SBIS). Those active in s6
+ -- also supplementary request stall and flush s6.
+ -- - nop request
+ -- The SFU stalls all younger instructions. The current instruction is
+ -- spawned into 2 instances. The older instance is killed (the very
+ -- same stage that requested the nop stage is flushed).
+ -- Thus, a nop is introduced in the pipeline *after* the instruction
+ -- wavefront.
+ -- In order to do that, a micro-state machine is needed outside the
+ -- pipeline, because otherwise that stage will undefinitely stall
+ -- itself.
+ -- Each pipeline stage has 2 kinds of control signals, that are generated by
+ -- the SFU:
+ -- - stall control
+ -- All registers in this stage are instructed to remain unchanged
+ -- (ignore `next...' signals that feed the registers in that
+ -- stage, or mirror registers in previous stages). Also, all
+ -- possible requests to hardware resources (such as RF, IOF, BPU,
+ -- DACU, SREG, etc) are reseted (to 0).
+ -- - flush control
+ -- All registers in this stage are reseted (to 0), to a most "benign"
+ -- state (a nop). Also, all requests to hardware resources are
+ -- reseted.
+ --
+ -- SFU requests:
+ -- - stall
+ -- - flush
+ -- - skip
+ -- - branch
+ -- - nop
+ -- SFU requests influence the way that hardware resources are granted to
+ -- pipeline stages. That way is given by the SFU rule below.
+ -- The SFU rule: older SFU hardware resource requests have priority over
+ -- younger ones.
+ --
+ -- The SFU manager sets the signals:
+ -- - pavr_stall_s1
+ -- - pavr_stall_s2
+ -- - pavr_stall_s3
+ -- - pavr_stall_s4
+ -- - pavr_stall_s5
+ -- - pavr_stall_s6
+ -- - pavr_flush_s1
+ -- - pavr_flush_s2
+ -- - pavr_flush_s3
+ -- - pavr_flush_s4
+ -- - pavr_flush_s5
+ -- - pavr_flush_s6
+ -- - pavr_s6_branch_pm_rq
+ -- - pavr_s6_skip_pm_rq
+ -- - pavr_s61_skip_pm_rq
+ -- - pavr_stall_bpu
+ -- - pavr_s61_hwrq_en
+ -- - pavr_s6_hwrq_en
+ -- - pavr_s5_hwrq_en
+ -- - pavr_s4_hwrq_en
+ -- - pavr_s3_hwrq_en
+ -- - pavr_s2_hwrq_en
+ -- - pavr_s1_hwrq_en
+ --
+ sfu_manager:
+ process(pavr_s3_stall_rq, pavr_s4_stall_rq, pavr_s5_stall_rq, pavr_s6_stall_rq,
+ pavr_s3_flush_s2_rq, pavr_s4_flush_s2_rq,
+ pavr_s4_ret_flush_s2_rq, pavr_s5_ret_flush_s2_rq, pavr_s51_ret_flush_s2_rq, pavr_s52_ret_flush_s2_rq,
+ pavr_s53_ret_flush_s2_rq, pavr_s54_ret_flush_s2_rq, pavr_s55_ret_flush_s2_rq,
+ pavr_s6_skip_rq, pavr_s61_skip_rq,
+ pavr_s6_branch_rq,
+ pavr_s4_nop_rq,
+
+ pavr_s6_hwrq_en,
+ pavr_s5_hwrq_en,
+ pavr_s4_hwrq_en,
+ pavr_s3_hwrq_en,
+
+ pavr_nop_ack
+ )
+ begin
+ -- By default:
+ -- - don't stall any pipe stage.
+ -- - grant to all pipe stages access to hardware resources.
+ pavr_stall_s1 <= '0';
+ pavr_stall_s2 <= '0';
+ pavr_stall_s3 <= '0';
+ pavr_stall_s4 <= '0';
+ pavr_stall_s5 <= '0';
+ pavr_stall_s6 <= '0';
+ pavr_flush_s1 <= '0';
+ pavr_flush_s2 <= '0';
+ pavr_flush_s3 <= '0';
+ pavr_flush_s4 <= '0';
+ pavr_flush_s5 <= '0';
+ pavr_flush_s6 <= '0';
+ pavr_s6_branch_pm_rq <= '0';
+ pavr_s6_skip_pm_rq <= '0';
+ pavr_s61_skip_pm_rq <= '0';
+ pavr_stall_bpu <= '0';
+ pavr_s61_hwrq_en <= '1';
+ pavr_s6_hwrq_en <= '1';
+ pavr_s5_hwrq_en <= '1';
+ pavr_s4_hwrq_en <= '1';
+ pavr_s3_hwrq_en <= '1';
+ pavr_s2_hwrq_en <= '1';
+ pavr_s1_hwrq_en <= '1';
+
+ -- Prioritize hardware resource requests.
+ -- Only one such request can be received by a given resource at a time. If
+ -- multiple accesses are requested from a resource, its access manager
+ -- will assert an error; that would indicate a design bug.
+ -- The pipeline is built so that each resource is normally accessed during a
+ -- fixed pipeline stage:
+ -- - RF is normally read in s2 and written in s6.
+ -- - IOF is normally read/written in s5.
+ -- - DM is normally read/written in s5.
+ -- - DACU is normally read/written in s5.
+ -- - PM is normally read in s1.
+ -- However, exceptions can occur. For example, LPM instructions need to read
+ -- PM in stage s5. Also, loads/stores must be able to read/write RF, IOF
+ -- or DM (depending on addresses involved) in stage s5. Exceptions are
+ -- handled in the hardware resource managers of those resources.
+ -- These are the stall/flush/skip/branch requests that matter when deciding
+ -- whether or not a pipe stage has the right to access hardware resources
+ -- (in priority order):
+ -- - pavr_s61_skip_rq
+ -- - pavr_s6_stall_rq
+ -- - pavr_s6_skip_rq
+ -- - pavr_s6_branch_rq
+ -- - pavr_s5_stall_rq
+ -- - pavr_s4_stall_rq
+ -- - pavr_s4_nop_rq & not pavr_nop_ack
+ -- - pavr_s3_stall_rq
+ -- - pavr_s3_flush_s2_rq
+ -- - pavr_s4_flush_s2_rq
+ -- - pavr_s4_ret_flush_s2_rq
+ -- - pavr_s5_ret_flush_s2_rq
+ -- - pavr_s51_ret_flush_s2_rq
+ -- - pavr_s52_ret_flush_s2_rq
+ -- - pavr_s53_ret_flush_s2_rq
+ -- - pavr_s54_ret_flush_s2_rq
+ -- - pavr_s55_ret_flush_s2_rq
+ -- Stage s61 is always permitted to access hardware resource requests, as
+ -- it is as old that a stage that can place hardware resource requests
+ -- can be.
+ -- Stages s6, s5, s4, s3, s2, s1 are conditionally permitted to do that.
+ if pavr_s61_skip_rq='1' then
+ pavr_s6_hwrq_en <= '0';
+ end if;
+ if pavr_s61_skip_rq ='1' or
+ pavr_s6_stall_rq ='1' or
+ pavr_s6_skip_rq ='1' or
+ pavr_s6_branch_rq ='1' then
+ pavr_s5_hwrq_en <= '0';
+ end if;
+ if pavr_s61_skip_rq ='1' or
+ pavr_s6_stall_rq ='1' or
+ pavr_s6_skip_rq ='1' or
+ pavr_s6_branch_rq ='1' or
+ pavr_s5_stall_rq ='1' or
+ -- *** Check nop requests too here, as nops are inserted *after* the
+ -- instruction wavefront.
+ (pavr_s4_nop_rq='1' and pavr_nop_ack='0') then
+ pavr_s4_hwrq_en <= '0';
+ end if;
+ if pavr_s61_skip_rq ='1' or
+ pavr_s6_stall_rq ='1' or
+ pavr_s6_skip_rq ='1' or
+ pavr_s6_branch_rq ='1' or
+ pavr_s5_stall_rq ='1' or
+ pavr_s4_stall_rq ='1' or
+ (pavr_s4_nop_rq='1' and pavr_nop_ack='0') then
+ pavr_s3_hwrq_en <= '0';
+ end if;
+ if pavr_s61_skip_rq ='1' or
+ pavr_s6_stall_rq ='1' or
+ pavr_s6_skip_rq ='1' or
+ pavr_s6_branch_rq ='1' or
+ pavr_s5_stall_rq ='1' or
+ pavr_s4_stall_rq ='1' or
+ pavr_s3_stall_rq ='1' or
+ (pavr_s4_nop_rq='1' and pavr_nop_ack='0')
+ --or
+ --pavr_s3_flush_s2_rq ='1' or
+ --pavr_s4_flush_s2_rq ='1' or
+ --pavr_s4_ret_flush_s2_rq ='1' or
+ --pavr_s5_ret_flush_s2_rq ='1' or
+ --pavr_s51_ret_flush_s2_rq ='1' or
+ --pavr_s52_ret_flush_s2_rq ='1' or
+ --pavr_s53_ret_flush_s2_rq ='1' or
+ --pavr_s54_ret_flush_s2_rq ='1' or
+ --pavr_s55_ret_flush_s2_rq ='1'
+ then
+ pavr_s2_hwrq_en <= '0';
+ end if;
+ if pavr_s61_skip_rq ='1' or
+ pavr_s6_stall_rq ='1' or
+ pavr_s6_skip_rq ='1' or
+ pavr_s6_branch_rq='1' or
+ pavr_s5_stall_rq ='1' or
+ pavr_s4_stall_rq ='1' or
+ pavr_s3_stall_rq ='1' or
+ (pavr_s4_nop_rq='1' and pavr_nop_ack='0')
+ then
+ pavr_s1_hwrq_en <= '0';
+ end if;
+
+ -- Process stall requests according to the SFU rule above.
+ -- Consequences of the SFU rule above:
+ -- - a stall request stalls in turn all younger pipe stages. By doing
+ -- that, the oldest instruction in the pipeline that needs a stall
+ -- wins, and gets its stall clock. All younger instructions are
+ -- postponed, their stall included. They will get their stall later,
+ -- after they resume execution.
+ -- - only a pipe stage that has resources access can win a stall (in
+ -- fact, winning a stall can be considered as winning access to the
+ -- Stall and Flush Unit hardware resource).
+ if pavr_s3_stall_rq='1' and pavr_s3_hwrq_en='1' then
+ pavr_stall_s1 <= '1';
+ pavr_stall_s2 <= '1';
+ pavr_flush_s2 <= '1';
+ end if;
+ if pavr_s4_stall_rq='1' and pavr_s4_hwrq_en='1' then
+ pavr_stall_s1 <= '1';
+ pavr_stall_s2 <= '1';
+ pavr_stall_s3 <= '1';
+ pavr_flush_s3 <= '1';
+ end if;
+ if pavr_s5_stall_rq='1' and pavr_s5_hwrq_en='1' then
+ pavr_stall_s1 <= '1';
+ pavr_stall_s2 <= '1';
+ pavr_stall_s3 <= '1';
+ pavr_stall_s4 <= '1';
+ pavr_flush_s4 <= '1';
+ end if;
+ if pavr_s6_stall_rq='1' and pavr_s6_hwrq_en='1' then
+ pavr_stall_s1 <= '1';
+ pavr_stall_s2 <= '1';
+ pavr_stall_s3 <= '1';
+ pavr_stall_s4 <= '1';
+ pavr_stall_s5 <= '1';
+ pavr_flush_s5 <= '1';
+ pavr_stall_bpu <= '1';
+ end if;
+
+ -- Process flush requests according to the SFU rule above.
+ -- Examples of the SFU rule above:
+ -- - flush s2 requested in s3, s4 and s5 won't be acknowledged if older
+ -- instructions require a stall, and, consequently, disable resources
+ -- access in s3, s4 respectively s5.
+ -- - s2 can't be flushed when nop is requested in s4.
+ if ((pavr_s3_flush_s2_rq and pavr_s3_hwrq_en) or
+ (pavr_s4_flush_s2_rq and pavr_s4_hwrq_en) or
+ (pavr_s4_ret_flush_s2_rq and pavr_s4_hwrq_en) or
+ (pavr_s5_ret_flush_s2_rq and pavr_s5_hwrq_en) or
+ pavr_s51_ret_flush_s2_rq or
+ pavr_s52_ret_flush_s2_rq or
+ pavr_s53_ret_flush_s2_rq or
+ pavr_s54_ret_flush_s2_rq or
+ pavr_s55_ret_flush_s2_rq)='1'
+ and
+ ((pavr_s4_nop_rq='0' and pavr_nop_ack='0') or (pavr_s4_nop_rq='1' and pavr_nop_ack='1')) then
+ pavr_flush_s2 <= '1';
+ end if;
+
+ -- Process skip requests according to the SFU rule above.
+ if pavr_s61_skip_rq='1' then
+ pavr_stall_s1 <= '1';
+ pavr_stall_s2 <= '1';
+ pavr_stall_s3 <= '1';
+ pavr_stall_s4 <= '1';
+ pavr_stall_s5 <= '1';
+ pavr_stall_s6 <= '1';
+ pavr_flush_s2 <= '1';
+ pavr_flush_s3 <= '1';
+ pavr_flush_s4 <= '1';
+ pavr_flush_s5 <= '1';
+ pavr_flush_s6 <= '1';
+ pavr_s61_skip_pm_rq <= '1';
+ pavr_stall_bpu <= '1';
+ end if;
+ if pavr_s6_skip_rq='1' and pavr_s6_hwrq_en='1' then
+ pavr_stall_s1 <= '1';
+ pavr_stall_s2 <= '1';
+ pavr_stall_s3 <= '1';
+ pavr_stall_s4 <= '1';
+ pavr_stall_s5 <= '1';
+ pavr_flush_s2 <= '1';
+ pavr_flush_s3 <= '1';
+ pavr_flush_s4 <= '1';
+ pavr_flush_s5 <= '1';
+ pavr_s6_skip_pm_rq <= '1';
+ pavr_stall_bpu <= '1';
+ end if;
+
+ -- Process branch requests according to the SFU rule above.
+ if pavr_s6_branch_rq='1' and pavr_s6_hwrq_en='1' then
+ pavr_stall_s1 <= '1';
+ pavr_stall_s2 <= '1';
+ pavr_stall_s3 <= '1';
+ pavr_stall_s4 <= '1';
+ pavr_stall_s5 <= '1';
+ pavr_flush_s2 <= '1';
+ pavr_flush_s3 <= '1';
+ pavr_flush_s4 <= '1';
+ pavr_flush_s5 <= '1';
+ pavr_s6_branch_pm_rq <= '1';
+ pavr_stall_bpu <= '1';
+ end if;
+
+ -- Process nop requests according to the SFU rule above.
+ -- *** Condition is hardware resource enabled in s5, not s4, because nop
+ -- request influences the very same pipe stage that placed the
+ -- request (s4).
+ if pavr_s4_nop_rq='1' and pavr_nop_ack='0' and pavr_s5_hwrq_en='1' then
+ pavr_stall_s1 <= '1';
+ pavr_stall_s2 <= '1';
+ pavr_stall_s3 <= '1';
+ pavr_stall_s4 <= '1';
+ pavr_flush_s4 <= '1';
+ end if;
+ end process sfu_manager;
+
+
+
+ -- Shadow manager (Synchronous)
+ -- To understand why the shadow protocol is needed, let's consider the
+ -- following example: a load instruction reads the Data Memory during pipe
+ -- stage s5. Suppose that next clock stalls s6, during which Data Memory
+ -- output was supposed to be written into the Register File. After another
+ -- clock, the stall is removed, and s6 requests to write the Register File,
+ -- but the Data Memory output has changed during the stall. Corrupted data
+ -- will be written into the Register File. With the shadow protocol, the
+ -- Data Memory output is saved during the stall, and the Register File is
+ -- written with the saved data.
+ -- Shadow protocol:
+ -- If a pipe stage is not permitted to place hardware resource requests,
+ -- then mark every memory-like entity in that stage as having its output
+ -- `shadowed'. That is, its output will be read (by whatever process
+ -- needs it) from the associated shadow register, rather than directly
+ -- from memory-like entity's output.
+ -- Basically, the condition that shadows a memory-like entity's output is
+ -- `hardware resource enabled during that stage'=0. However, there are
+ -- exceptions. For example, LPM family instructions steal Program Memory
+ -- access by stalling the instruction that would normally be fetched that
+ -- time. By stalling, hardware resource requests become disabled in that
+ -- pipe stage. Still, LPM family instructions must be able to request
+ -- Program Memory access. Here, the PM must not be shadowed even though
+ -- during its pipe stage s2 (during which PM is normally accessed) all
+ -- hardware requests are disabled by default.
+ -- In order to enable shadowing during multiple, successive stalls, shadow
+ -- memory-like entities outputs only if they aren't already shadowed.
+ -- Set the signals:
+ -- - !!!
+ shadow_manager:
+ process(pavr_res, pavr_syncres, pavr_clk,
+
+ pavr_s3_stall_rq,
+
+ pavr_s5_hwrq_en,
+ pavr_s2_hwrq_en,
+ pavr_s1_hwrq_en,
+
+ pavr_grant_control_flow_access,
+
+ pavr_rf_do_shadow_active,
+ pavr_rf_rd1_do_shadow,
+ pavr_rf_rd2_do_shadow,
+ pavr_iof_do_shadow_active,
+ pavr_iof_do_shadow,
+ pavr_dm_do_shadow_active,
+ pavr_dm_do_shadow,
+ pavr_dacu_do_shadow_active,
+ pavr_dacu_do_shadow,
+ pavr_pm_do_shadow_active,
+ pavr_pm_do_shadow,
+
+ pavr_pm_do,
+ pavr_s2_pmdo_valid,
+ pavr_rf_rd1_do,
+ pavr_rf_rd2_do,
+ pavr_iof_do,
+ pavr_dm_do,
+ pavr_dacu_do
+ )
+ begin
+ if pavr_res='1' then
+ -- Asynchronous reset
+ -- RF-related shadow registers
+ pavr_rf_rd1_do_shadow <= int_to_std_logic_vector(0, pavr_rf_rd1_do_shadow'length);
+ pavr_rf_rd2_do_shadow <= int_to_std_logic_vector(0, pavr_rf_rd2_do_shadow'length);
+ pavr_rf_do_shadow_active <= '0';
+ -- IOF-related shadow registers
+ pavr_iof_do_shadow <= int_to_std_logic_vector(0, pavr_iof_do_shadow'length);
+ pavr_iof_do_shadow_active <= '0';
+ -- DM-related shadow registers
+ pavr_dm_do_shadow <= int_to_std_logic_vector(0, pavr_dm_do_shadow'length);
+ pavr_dm_do_shadow_active <= '0';
+ -- DACU-related shadow registers
+ pavr_dacu_do_shadow <= int_to_std_logic_vector(0, pavr_dacu_do_shadow'length);
+ pavr_dacu_do_shadow_active <= '0';
+ -- PM-related shadow registers
+ pavr_pm_do_shadow <= int_to_std_logic_vector(0, pavr_pm_do_shadow'length);
+ pavr_s2_pmdo_valid_shadow <= '0';
+ pavr_pm_do_shadow_active <= '0';
+
+ elsif pavr_clk'event and pavr_clk='1' then
+ -- RF-related shadow registers
+ -- RF is normally read in pipe stage s2.
+ -- ** Don't shadow RF if s3 stall request (hole through shadow protocol).
+ -- That's because s3 stall requests are intended only to delay youger
+ -- instructions with one clock. During this stalls, the instruction
+ -- that requests s3 stall might need to read RF (for example, the
+ -- instruction CPSE). If RF is shadowed, that instruction will
+ -- incorrectly read from shadow register.
+ -- Note
+ -- Fortunately, there are only a few such exceptions (holes through
+ -- the shadow protocol). Overall, the shadow protocol is still a good
+ -- idea, as it permits natural & automatic handling of a bunch of
+ -- registers placed in delicated areas.
+ if pavr_s2_hwrq_en='0' and pavr_s3_stall_rq='0' then -- ... if `hardware resources are disabled' and 's3 doesn't request stall'
+ if pavr_rf_do_shadow_active='0' then -- and `shadow isn't already active'
+ pavr_rf_rd1_do_shadow <= pavr_rf_rd1_do; -- then `shadow Register File read ports 1 and 2'
+ pavr_rf_rd2_do_shadow <= pavr_rf_rd2_do;
+ pavr_rf_do_shadow_active <= '1';
+ end if;
+ else
+ pavr_rf_do_shadow_active <= '0'; -- else `unshadow Register File read ports 1 and 2'
+ end if;
+
+ -- IOF-related shadow registers
+ -- IOF is normally read in pipe stage s5.
+ if pavr_s5_hwrq_en='0' then
+ if pavr_iof_do_shadow_active='0' then
+ pavr_iof_do_shadow <= pavr_iof_do;
+ pavr_iof_do_shadow_active <= '1';
+ end if;
+ else
+ pavr_iof_do_shadow_active <= '0';
+ end if;
+
+ -- DM-related shadow registers
+ -- DM is normally read in pipe stage s5.
+ if pavr_s5_hwrq_en='0' then
+ if pavr_dm_do_shadow_active='0' then
+ pavr_dm_do_shadow <= pavr_dm_do;
+ pavr_dm_do_shadow_active <= '1';
+ end if;
+ else
+ pavr_dm_do_shadow_active <= '0';
+ end if;
+
+ -- DACU-related shadow registers
+ -- DACU is normally read in pipe stage s5.
+ if pavr_s5_hwrq_en='0' then
+ if pavr_dacu_do_shadow_active='0' then
+ pavr_dacu_do_shadow <= pavr_dacu_do;
+ pavr_dacu_do_shadow_active <= '1';
+ end if;
+ else
+ pavr_dacu_do_shadow_active <= '0';
+ end if;
+
+ -- Setting PM-related shadow registers
+ -- PM is normally read in pipe stage s1.
+ -- *** If a control instruction instruction wants flow control access,
+ -- don't shadow PM (hole through shadow protocol).
+ if pavr_s1_hwrq_en='0' and pavr_grant_control_flow_access='0' then
+ if pavr_pm_do_shadow_active='0' then
+ -- Shadow PM.
+ pavr_pm_do_shadow <= pavr_pm_do;
+ pavr_s2_pmdo_valid_shadow <= pavr_s2_pmdo_valid;
+ pavr_pm_do_shadow_active <= '1';
+ end if;
+ else
+ -- Unshadow PM.
+ pavr_pm_do_shadow_active <= '0';
+ end if;
+
+ if pavr_syncres='1' then
+ -- Synchronous reset
+ -- RF-related shadow registers
+ pavr_rf_rd1_do_shadow <= int_to_std_logic_vector(0, pavr_rf_rd1_do_shadow'length);
+ pavr_rf_rd2_do_shadow <= int_to_std_logic_vector(0, pavr_rf_rd2_do_shadow'length);
+ pavr_rf_do_shadow_active <= '0';
+ -- IOF-related shadow registers
+ pavr_iof_do_shadow <= int_to_std_logic_vector(0, pavr_iof_do_shadow'length);
+ pavr_iof_do_shadow_active <= '0';
+ -- DM-related shadow registers
+ pavr_dm_do_shadow <= int_to_std_logic_vector(0, pavr_dm_do_shadow'length);
+ pavr_dm_do_shadow_active <= '0';
+ -- DACU-related shadow registers
+ pavr_dacu_do_shadow <= int_to_std_logic_vector(0, pavr_dacu_do_shadow'length);
+ pavr_dacu_do_shadow_active <= '0';
+ -- PM-related shadow registers
+ pavr_pm_do_shadow <= int_to_std_logic_vector(0, pavr_pm_do_shadow'length);
+ pavr_s2_pmdo_valid_shadow <= '0';
+ pavr_pm_do_shadow_active <= '0';
+ end if;
+ end if;
+ end process shadow_manager;
+
+
+
+ -- Computing branch and skip conditions
+ -- Set signals:
+ -- - next_pavr_s6_branch_rq
+ -- - next_pavr_s6_skip_rq
+ -- - next_pavr_s61_skip_rq
+ br_skip_cond:
+ process(pavr_s5_branch_bitsreg_sel, pavr_s5_branch_cond_sel, pavr_s5_branch_en, pavr_iof_sreg,
+ pavr_s5_skip_bitrf_sel, pavr_s5_skip_cond_sel, pavr_s5_skip_en, pavr_s5_op1bpu, pavr_s5_alu_flagsout,
+ pavr_s6_skip_bitiof_sel, pavr_s6_skip_cond_sel, pavr_s6_skip_en, pavr_iof_do,
+ pavr_iof_do_shadow, pavr_iof_do_shadow_active
+ )
+ variable t_pavr_s5_branch_bitsreg, t_pavr_s5_branch_cond: std_logic;
+ variable t_pavr_s5_skip_bitrf, t_pavr_s5_skip_cond: std_logic;
+ variable t_pavr_s6_skip_bitiof, t_pavr_s6_skip_cond: std_logic;
+ variable t_pavr_iof_do: std_logic_vector(7 downto 0);
+ begin
+ -- Compute branch condition in stage s5.
+ case std_logic_vector_to_nat(pavr_s5_branch_bitsreg_sel) is
+ when 0 =>
+ t_pavr_s5_branch_bitsreg := pavr_iof_sreg(0);
+ when 1 =>
+ t_pavr_s5_branch_bitsreg := pavr_iof_sreg(1);
+ when 2 =>
+ t_pavr_s5_branch_bitsreg := pavr_iof_sreg(2);
+ when 3 =>
+ t_pavr_s5_branch_bitsreg := pavr_iof_sreg(3);
+ when 4 =>
+ t_pavr_s5_branch_bitsreg := pavr_iof_sreg(4);
+ when 5 =>
+ t_pavr_s5_branch_bitsreg := pavr_iof_sreg(5);
+ when 6 =>
+ t_pavr_s5_branch_bitsreg := pavr_iof_sreg(6);
+ when others =>
+ t_pavr_s5_branch_bitsreg := pavr_iof_sreg(7);
+ end case;
+ case pavr_s5_branch_cond_sel is
+ when pavr_s5_branch_cond_sel_bitsreg =>
+ t_pavr_s5_branch_cond := t_pavr_s5_branch_bitsreg;
+ -- When pavr_s5_branch_cond_sel_notbitsreg
+ when others =>
+ t_pavr_s5_branch_cond := not t_pavr_s5_branch_bitsreg;
+ end case;
+ next_pavr_s6_branch_rq <= t_pavr_s5_branch_cond and pavr_s5_branch_en;
+
+ -- Compute skip condition in stage s5.
+ case std_logic_vector_to_nat(pavr_s5_skip_bitrf_sel) is
+ when 0 =>
+ t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(0);
+ when 1 =>
+ t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(1);
+ when 2 =>
+ t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(2);
+ when 3 =>
+ t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(3);
+ when 4 =>
+ t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(4);
+ when 5 =>
+ t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(5);
+ when 6 =>
+ t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(6);
+ when others =>
+ t_pavr_s5_skip_bitrf := pavr_s5_op1bpu(7);
+ end case;
+ case pavr_s5_skip_cond_sel is
+ when pavr_s5_skip_cond_sel_zflag =>
+ t_pavr_s5_skip_cond := pavr_s5_alu_flagsout(1);
+ when pavr_s5_skip_cond_sel_bitrf =>
+ t_pavr_s5_skip_cond := t_pavr_s5_skip_bitrf;
+ -- When pavr_s5_skip_cond_sel_notbitrf
+ when others =>
+ t_pavr_s5_skip_cond := not t_pavr_s5_skip_bitrf;
+ end case;
+ next_pavr_s6_skip_rq <= t_pavr_s5_skip_cond and pavr_s5_skip_en;
+
+ -- Compute skip condition in stage s6.
+ if pavr_iof_do_shadow_active='0' then
+ t_pavr_iof_do := pavr_iof_do;
+ else
+ t_pavr_iof_do := pavr_iof_do_shadow;
+ end if;
+ case std_logic_vector_to_nat(pavr_s6_skip_bitiof_sel) is
+ when 0 =>
+ t_pavr_s6_skip_bitiof := t_pavr_iof_do(0);
+ when 1 =>
+ t_pavr_s6_skip_bitiof := t_pavr_iof_do(1);
+ when 2 =>
+ t_pavr_s6_skip_bitiof := t_pavr_iof_do(2);
+ when 3 =>
+ t_pavr_s6_skip_bitiof := t_pavr_iof_do(3);
+ when 4 =>
+ t_pavr_s6_skip_bitiof := t_pavr_iof_do(4);
+ when 5 =>
+ t_pavr_s6_skip_bitiof := t_pavr_iof_do(5);
+ when 6 =>
+ t_pavr_s6_skip_bitiof := t_pavr_iof_do(6);
+ when others =>
+ t_pavr_s6_skip_bitiof := t_pavr_iof_do(7);
+ end case;
+ case pavr_s6_skip_cond_sel is
+ when pavr_s6_skip_cond_sel_bitiof =>
+ t_pavr_s6_skip_cond := t_pavr_s6_skip_bitiof;
+ -- When pavr_s6_skip_cond_sel_notbitiof
+ when others =>
+ t_pavr_s6_skip_cond := not t_pavr_s6_skip_bitiof;
+ end case;
+ next_pavr_s61_skip_rq <= t_pavr_s6_skip_cond and pavr_s6_skip_en;
+
+ end process br_skip_cond;
+
+
+
+ -- Zero-level assignments --------------------------------------------------
+ -- Read Bypass Unit.
+ pavr_s5_op1bpu <= read_through_bpu(pavr_s5_op1, pavr_s5_op1_addr,
+ pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
+ pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
+ pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
+ pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
+ pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
+ pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
+ pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
+ pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
+ pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
+ pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
+ pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
+ pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
+ pavr_s5_op2bpu <= read_through_bpu(pavr_s5_op2, pavr_s5_op2_addr,
+ pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
+ pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
+ pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
+ pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
+ pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
+ pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
+ pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
+ pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
+ pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
+ pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
+ pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
+ pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
+ pavr_xbpu(7 downto 0) <= read_through_bpu(pavr_rf_x(7 downto 0), int_to_std_logic_vector(26, 5),
+ pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
+ pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
+ pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
+ pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
+ pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
+ pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
+ pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
+ pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
+ pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
+ pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
+ pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
+ pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
+ pavr_xbpu(15 downto 8) <= read_through_bpu(pavr_rf_x(15 downto 8), int_to_std_logic_vector(27, 5),
+ pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
+ pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
+ pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
+ pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
+ pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
+ pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
+ pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
+ pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
+ pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
+ pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
+ pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
+ pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
+ pavr_ybpu(7 downto 0) <= read_through_bpu(pavr_rf_y(7 downto 0), int_to_std_logic_vector(28, 5),
+ pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
+ pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
+ pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
+ pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
+ pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
+ pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
+ pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
+ pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
+ pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
+ pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
+ pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
+ pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
+ pavr_ybpu(15 downto 8) <= read_through_bpu(pavr_rf_y(15 downto 8), int_to_std_logic_vector(29, 5),
+ pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
+ pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
+ pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
+ pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
+ pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
+ pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
+ pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
+ pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
+ pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
+ pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
+ pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
+ pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
+ pavr_zbpu(7 downto 0) <= read_through_bpu(pavr_rf_z(7 downto 0), int_to_std_logic_vector(30, 5),
+ pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
+ pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
+ pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
+ pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
+ pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
+ pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
+ pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
+ pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
+ pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
+ pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
+ pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
+ pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
+ pavr_zbpu(15 downto 8) <= read_through_bpu(pavr_rf_z(15 downto 8), int_to_std_logic_vector(31, 5),
+ pavr_bpr00, pavr_bpr00_addr, pavr_bpr00_active,
+ pavr_bpr01, pavr_bpr01_addr, pavr_bpr01_active,
+ pavr_bpr02, pavr_bpr02_addr, pavr_bpr02_active,
+ pavr_bpr03, pavr_bpr03_addr, pavr_bpr03_active,
+ pavr_bpr10, pavr_bpr10_addr, pavr_bpr10_active,
+ pavr_bpr11, pavr_bpr11_addr, pavr_bpr11_active,
+ pavr_bpr12, pavr_bpr12_addr, pavr_bpr12_active,
+ pavr_bpr13, pavr_bpr13_addr, pavr_bpr13_active,
+ pavr_bpr20, pavr_bpr20_addr, pavr_bpr20_active,
+ pavr_bpr21, pavr_bpr21_addr, pavr_bpr21_active,
+ pavr_bpr22, pavr_bpr22_addr, pavr_bpr22_active,
+ pavr_bpr23, pavr_bpr23_addr, pavr_bpr23_active);
+ pavr_pm_addr <= pavr_pm_addr_int;
+ pavr_pm_wr <= '0';
+ pavr_s5_alu_flagsin <= pavr_iof_sreg(5 downto 0);
+ pavr_disable_int <= pavr_s4_disable_int or
+ pavr_s5_disable_int or
+ pavr_s51_disable_int or
+ pavr_s52_disable_int;
+
+ --
+ -- Instruction counting.
+ -- Note that the instruction count is not exact:
+ -- - explicit nops are not counted.
+ -- - skips/branches followed by a 32 bit instruction are counted twice.
+ instr_cnt:
+ process(pavr_stall_s2,
+ pavr_s5_branch_en, pavr_s5_skip_en, pavr_s6_skip_en,
+ pavr_s5_hwrq_en, pavr_s6_hwrq_en, pavr_s6_branch_rq, pavr_s6_skip_rq, pavr_s61_skip_rq,
+ pavr_s3_instr, pavr_s2_pmdo_valid, pavr_s4_instr32bits )
+ begin
+ pavr_inc_instr_cnt <= "00";
+ if (pavr_s2_pmdo_valid='1' and
+ pavr_stall_s2='0' and
+ pavr_s4_instr32bits='0' and
+ std_logic_vector_to_nat(pavr_s3_instr)/=0)
+ then
+ -- Add 1 to instruction counter.
+ pavr_inc_instr_cnt <= "01";
+ end if;
+ if (pavr_s5_hwrq_en='1' and pavr_s5_branch_en='1') or
+ (pavr_s5_hwrq_en='1' and pavr_s5_skip_en='1') or
+ (pavr_s6_hwrq_en='1' and pavr_s6_skip_en='1')
+ then
+ -- Add 2 to instruction counter.
+ pavr_inc_instr_cnt <= "10";
+ end if;
+ if (pavr_s6_hwrq_en='1' and pavr_s6_branch_rq='1') or
+ (pavr_s6_hwrq_en='1' and pavr_s6_skip_rq ='1') or
+ ( pavr_s61_skip_rq ='1')
+ then
+ -- Substract 1 from from instruction counter.
+ pavr_inc_instr_cnt <= "11";
+ end if;
+ end process instr_cnt;
+ --
+
+end;
+--
Index: group__pavr__hwres__pm.html
===================================================================
--- group__pavr__hwres__pm.html (nonexistent)
+++ group__pavr__hwres__pm.html (revision 6)
@@ -0,0 +1,68 @@
+
+
+Program Memory
+
+
+
+
+Main Page Modules Related Pages
+
Program Memory
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_alu.vhd
===================================================================
--- pavr_alu.vhd (nonexistent)
+++ pavr_alu.vhd (revision 6)
@@ -0,0 +1,443 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This is pAVR's ALU.
+-- The ALU asychronousely computes:
+-- - output
+-- - output flags,
+-- based on:
+-- - input 1
+-- - input 2
+-- - input flags
+-- Flags:
+-- - C (cary)
+-- - Z (zero)
+-- - N (negative)
+-- - V (two's complement overflow)
+-- - S (N xor V, for signed tests)
+-- - H (half carry)
+-- *** The half carry is computed as specified in the AVR instruction set.
+-- However, Atmel's AVRStudio computes it differently. To see where is the
+-- bug, in the AVR instruction set document or in AVRStudio.
+--
+
+
+
+--
+library work;
+use work.std_util.all;
+use work.pavr_util.all;
+use work.pavr_constants.all;
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+
+entity pavr_alu is
+ port(
+ pavr_alu_op1: in std_logic_vector(15 downto 0);
+ pavr_alu_op2: in std_logic_vector(7 downto 0);
+ pavr_alu_out: out std_logic_vector(15 downto 0);
+ pavr_alu_opcode: in std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
+ pavr_alu_flagsin: in std_logic_vector(5 downto 0);
+ pavr_alu_flagsout: out std_logic_vector(5 downto 0)
+ );
+end;
+
+
+
+architecture pavr_alu_arch of pavr_alu is
+ -- Wires
+ signal tmp10_1, tmp10_2, tmp10_3 : std_logic_vector(9 downto 0);
+ signal tmp18_1, tmp18_2, tmp18_3 : std_logic_vector(17 downto 0);
+
+ signal pavr_alu_h_sel: std_logic_vector(pavr_alu_h_sel_w - 1 downto 0);
+ signal pavr_alu_s_sel: std_logic;
+ signal pavr_alu_v_sel: std_logic_vector(pavr_alu_v_sel_w - 1 downto 0);
+ signal pavr_alu_n_sel: std_logic_vector(pavr_alu_n_sel_w - 1 downto 0);
+ signal pavr_alu_z_sel: std_logic_vector(pavr_alu_z_sel_w - 1 downto 0);
+ signal pavr_alu_c_sel: std_logic_vector(pavr_alu_c_sel_w - 1 downto 0);
+
+ signal pavr_alu_out_int: std_logic_vector(15 downto 0);
+ signal pavr_alu_flagsout_int: std_logic_vector(5 downto 0);
+
+ -- Registers
+ -- No registers
+begin
+
+ -- Compute ALU output and selectors for flags muxers.
+ alu_out:
+ process(pavr_alu_op1, pavr_alu_op2, pavr_alu_out_int, pavr_alu_opcode, pavr_alu_flagsin,
+ tmp10_1, tmp10_2, tmp10_3,
+ tmp18_1, tmp18_2, tmp18_3
+ )
+ begin
+ -- Default ALU output to 0.
+ pavr_alu_out_int <= int_to_std_logic_vector(0, pavr_alu_out_int'length);
+
+ -- Default 8 bit adders's operands to ls8bits(operand1), operand2, carry in and carry out to 0.
+ tmp10_1(0) <= '0';
+ tmp10_2(0) <= '0';
+ tmp10_1(8 downto 1) <= pavr_alu_op1(7 downto 0);
+ tmp10_2(8 downto 1) <= pavr_alu_op2(7 downto 0);
+ tmp10_1(9) <= '0';
+ tmp10_2(9) <= '0';
+
+ -- Default 16 bit adders's operands to operand1, signExtendTo16bits(operand2), carry in and carry out to 0.
+ tmp18_1(0) <= '0';
+ tmp18_2(0) <= '0';
+ tmp18_1(16 downto 1) <= pavr_alu_op1(15 downto 0);
+ tmp18_2(16 downto 1) <= sign_extend(pavr_alu_op2, 16);
+ tmp18_1(17) <= '0';
+ tmp18_2(17) <= '0';
+
+ -- Default adders's outputs
+ tmp10_3 <= int_to_std_logic_vector(0, tmp10_3'length);
+ tmp18_3 <= int_to_std_logic_vector(0, tmp18_3'length);
+
+ -- Default flags out to flags in.
+ pavr_alu_h_sel <= pavr_alu_h_sel_same;
+ pavr_alu_s_sel <= pavr_alu_s_sel_same;
+ pavr_alu_v_sel <= pavr_alu_v_sel_same;
+ pavr_alu_n_sel <= pavr_alu_n_sel_same;
+ pavr_alu_z_sel <= pavr_alu_z_sel_same;
+ pavr_alu_c_sel <= pavr_alu_c_sel_same;
+
+ -- Build ALU output.
+ case std_logic_vector_to_nat(pavr_alu_opcode) is
+ when pavr_alu_opcode_add8 =>
+ tmp10_3 <= tmp10_1 + tmp10_2;
+ pavr_alu_out_int(7 downto 0) <= tmp10_3(8 downto 1);
+ pavr_alu_h_sel <= pavr_alu_h_sel_add8;
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_add8;
+ pavr_alu_n_sel <= pavr_alu_n_sel_msb8;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z8;
+ pavr_alu_c_sel <= pavr_alu_c_sel_add8;
+ when pavr_alu_opcode_adc8 =>
+ tmp10_1(0) <= pavr_alu_flagsin(0);
+ tmp10_2(0) <= pavr_alu_flagsin(0);
+ tmp10_3 <= tmp10_1 + tmp10_2;
+ pavr_alu_out_int(7 downto 0) <= tmp10_3(8 downto 1);
+ pavr_alu_h_sel <= pavr_alu_h_sel_add8;
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_add8;
+ pavr_alu_n_sel <= pavr_alu_n_sel_msb8;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z8;
+ pavr_alu_c_sel <= pavr_alu_c_sel_add8;
+ when pavr_alu_opcode_sub8 =>
+ tmp10_1(0) <= '1';
+ tmp10_3 <= tmp10_1 + (not tmp10_2);
+ pavr_alu_out_int(7 downto 0) <= tmp10_3(8 downto 1);
+ pavr_alu_h_sel <= pavr_alu_h_sel_sub8;
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_sub8;
+ pavr_alu_n_sel <= pavr_alu_n_sel_msb8;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z8;
+ pavr_alu_c_sel <= pavr_alu_c_sel_sub8;
+ when pavr_alu_opcode_sbc8 =>
+ tmp10_1(0) <= not pavr_alu_flagsin(0);
+ tmp10_2(0) <= pavr_alu_flagsin(0);
+ tmp10_3 <= tmp10_1 + (not tmp10_2);
+ pavr_alu_out_int(7 downto 0) <= tmp10_3(8 downto 1);
+ pavr_alu_h_sel <= pavr_alu_h_sel_sub8;
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_sub8;
+ pavr_alu_n_sel <= pavr_alu_n_sel_msb8;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z8c;
+ pavr_alu_c_sel <= pavr_alu_c_sel_sub8;
+ when pavr_alu_opcode_and8 =>
+ pavr_alu_out_int(7 downto 0) <= pavr_alu_op1(7 downto 0) and pavr_alu_op2;
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_z;
+ pavr_alu_n_sel <= pavr_alu_n_sel_msb8;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z8;
+ when pavr_alu_opcode_eor8 =>
+ pavr_alu_out_int(7 downto 0) <= pavr_alu_op1(7 downto 0) xor pavr_alu_op2;
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_z;
+ pavr_alu_n_sel <= pavr_alu_n_sel_msb8;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z8;
+ when pavr_alu_opcode_or8 =>
+ pavr_alu_out_int(7 downto 0) <= pavr_alu_op1(7 downto 0) or pavr_alu_op2;
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_z;
+ pavr_alu_n_sel <= pavr_alu_n_sel_msb8;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z8;
+ when pavr_alu_opcode_op1 =>
+ pavr_alu_out_int <= pavr_alu_op1;
+ when pavr_alu_opcode_op2 =>
+ pavr_alu_out_int <= zero_extend(pavr_alu_op2, pavr_alu_out_int'length);
+ when pavr_alu_opcode_inc8 =>
+ tmp10_3 <= tmp10_1 + tmp10_2;
+ pavr_alu_out_int(7 downto 0) <= tmp10_3(8 downto 1);
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_inc8;
+ pavr_alu_n_sel <= pavr_alu_n_sel_msb8;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z8;
+ when pavr_alu_opcode_dec8 =>
+ tmp10_3 <= tmp10_1 + tmp10_2;
+ pavr_alu_out_int(7 downto 0) <= tmp10_3(8 downto 1);
+ pavr_alu_out_int(7 downto 0) <= tmp10_3(8 downto 1);
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_dec8;
+ pavr_alu_n_sel <= pavr_alu_n_sel_msb8;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z8;
+ when pavr_alu_opcode_com8 =>
+ pavr_alu_out_int(7 downto 0) <= not pavr_alu_op1(7 downto 0);
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_z;
+ pavr_alu_n_sel <= pavr_alu_n_sel_msb8;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z8;
+ pavr_alu_c_sel <= pavr_alu_c_sel_one;
+ when pavr_alu_opcode_neg8 =>
+ tmp10_1 <= int_to_std_logic_vector(1, tmp10_1'length);
+ tmp10_2(8 downto 1) <= pavr_alu_op1(7 downto 0);
+ tmp10_3 <= tmp10_1 + (not tmp10_2);
+ pavr_alu_out_int(7 downto 0) <= tmp10_3(8 downto 1);
+ pavr_alu_h_sel <= pavr_alu_h_sel_neg8;
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_neg8;
+ pavr_alu_n_sel <= pavr_alu_n_sel_msb8;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z8;
+ pavr_alu_c_sel <= pavr_alu_c_sel_neg8;
+ when pavr_alu_opcode_swap8 =>
+ pavr_alu_out_int(7 downto 4) <= pavr_alu_op1(3 downto 0);
+ pavr_alu_out_int(3 downto 0) <= pavr_alu_op1(7 downto 4);
+ when pavr_alu_opcode_lsr8 =>
+ pavr_alu_out_int(7) <= '0';
+ pavr_alu_out_int(6 downto 0) <= pavr_alu_op1(7 downto 1);
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_nxorc;
+ pavr_alu_n_sel <= pavr_alu_n_sel_z;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z8;
+ pavr_alu_c_sel <= pavr_alu_c_sel_lsbop1;
+ when pavr_alu_opcode_asr8 =>
+ pavr_alu_out_int(7) <= pavr_alu_op1(7);
+ pavr_alu_out_int(6 downto 0) <= pavr_alu_op1(7 downto 1);
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_nxorc;
+ pavr_alu_n_sel <= pavr_alu_n_sel_msb8;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z8;
+ pavr_alu_c_sel <= pavr_alu_c_sel_lsbop1;
+ when pavr_alu_opcode_ror8 =>
+ pavr_alu_out_int(7) <= pavr_alu_flagsin(0);
+ pavr_alu_out_int(6 downto 0) <= pavr_alu_op1(7 downto 1);
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_nxorc;
+ pavr_alu_n_sel <= pavr_alu_n_sel_msb8;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z8;
+ pavr_alu_c_sel <= pavr_alu_c_sel_lsbop1;
+ when pavr_alu_opcode_add16 =>
+ tmp18_3 <= tmp18_1 + tmp18_2;
+ pavr_alu_out_int(15 downto 0) <= tmp18_3(16 downto 1);
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_add16;
+ pavr_alu_n_sel <= pavr_alu_n_sel_msb16;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z16;
+ pavr_alu_c_sel <= pavr_alu_c_sel_add16;
+ when pavr_alu_opcode_sub16 =>
+ tmp18_1(0) <= '1';
+ tmp18_3 <= tmp18_1 + (not tmp18_2);
+ pavr_alu_out_int(15 downto 0) <= tmp18_3(16 downto 1);
+ pavr_alu_s_sel <= pavr_alu_s_sel_nxorv;
+ pavr_alu_v_sel <= pavr_alu_v_sel_sub16;
+ pavr_alu_n_sel <= pavr_alu_n_sel_msb16;
+ pavr_alu_z_sel <= pavr_alu_z_sel_z16;
+ pavr_alu_c_sel <= pavr_alu_c_sel_add16;
+ -- Multiplications are not implemented for now.
+ when pavr_alu_opcode_mul8 =>
+ null;
+ when pavr_alu_opcode_muls8 =>
+ null;
+ when pavr_alu_opcode_mulsu8 =>
+ null;
+ when pavr_alu_opcode_fmul8 =>
+ null;
+ when pavr_alu_opcode_fmuls8 =>
+ null;
+ when pavr_alu_opcode_fmulsu8 =>
+ null;
+ when others =>
+ null;
+ end case;
+ end process alu_out;
+
+
+
+ -- Select output flags based on the selectors computed in the process above.
+ alu_flags:
+ process(pavr_alu_op1, pavr_alu_op2, pavr_alu_out_int, pavr_alu_flagsin, pavr_alu_flagsout_int,
+ pavr_alu_c_sel, pavr_alu_z_sel, pavr_alu_n_sel, pavr_alu_v_sel, pavr_alu_s_sel, pavr_alu_h_sel,
+ tmp10_3, tmp18_3)
+ variable tmp1, tmp2, tmp3, tmp4 : std_logic;
+ begin
+ tmp1 := '0';
+ tmp2 := '0';
+ tmp3 := '0';
+ tmp4 := '0';
+
+ -- Default flags out to flags in.
+ pavr_alu_flagsout_int <= pavr_alu_flagsin;
+
+ -- Build C flag.
+ case pavr_alu_c_sel is
+ when pavr_alu_c_sel_same =>
+ pavr_alu_flagsout_int(0) <= pavr_alu_flagsin(0);
+ when pavr_alu_c_sel_add8 | pavr_alu_c_sel_sub8 =>
+ pavr_alu_flagsout_int(0) <= tmp10_3(9);
+ when pavr_alu_c_sel_one =>
+ pavr_alu_flagsout_int(0) <= '1';
+ when pavr_alu_c_sel_neg8 =>
+ -- Set carry if and only if input != 0 (equivalent to output != 0).
+ pavr_alu_flagsout_int(0) <= pavr_alu_op1(0);
+ for i in 1 to 7 loop
+ pavr_alu_flagsout_int(0) <= pavr_alu_flagsout_int(0) or pavr_alu_op1(i);
+ end loop;
+ when pavr_alu_c_sel_lsbop1 =>
+ pavr_alu_flagsout_int(0) <= pavr_alu_op1(0);
+ -- When pavr_alu_c_sel_add16 | pavr_alu_c_sel_sub16
+ when others =>
+ pavr_alu_flagsout_int(0) <= tmp18_3(17);
+ end case;
+
+ -- Build Z flag.
+ case pavr_alu_z_sel is
+ when pavr_alu_z_sel_same =>
+ pavr_alu_flagsout_int(1) <= pavr_alu_flagsin(1);
+ when pavr_alu_z_sel_z8 =>
+ tmp4 := pavr_alu_out_int(0);
+ for i in 1 to 7 loop
+ tmp4 := tmp4 or pavr_alu_out_int(i);
+ end loop;
+ pavr_alu_flagsout_int(1) <= not tmp4;
+ when pavr_alu_z_sel_z8c =>
+ tmp4 := pavr_alu_out_int(0);
+ for i in 1 to 7 loop
+ tmp4 := tmp4 or pavr_alu_out_int(i);
+ end loop;
+ pavr_alu_flagsout_int(1) <= (not tmp4) and pavr_alu_flagsin(1);
+ -- When pavr_alu_z_sel_z16
+ when others =>
+ tmp4 := pavr_alu_out_int(0);
+ for i in 1 to 15 loop
+ tmp4 := tmp4 or pavr_alu_out_int(i);
+ end loop;
+ pavr_alu_flagsout_int(1) <= not tmp4;
+ end case;
+
+ -- Build N flag.
+ case pavr_alu_n_sel is
+ when pavr_alu_n_sel_same =>
+ pavr_alu_flagsout_int(2) <= pavr_alu_flagsin(2);
+ when pavr_alu_n_sel_msb8 =>
+ pavr_alu_flagsout_int(2) <= pavr_alu_out_int(7);
+ -- When pavr_alu_n_sel_msb16
+ when others =>
+ pavr_alu_flagsout_int(2) <= pavr_alu_out_int(15);
+ end case;
+
+ -- Build V flag.
+ case pavr_alu_v_sel is
+ when pavr_alu_v_sel_same =>
+ pavr_alu_flagsout_int(3) <= pavr_alu_flagsin(3);
+ when pavr_alu_v_sel_add8 =>
+ tmp1 := pavr_alu_op1(7);
+ tmp2 := pavr_alu_op2(7);
+ tmp3 := pavr_alu_out_int(7);
+ pavr_alu_flagsout_int(3) <= (tmp1 and tmp2 and (not tmp3)) or ((not tmp1) and (not tmp2) and tmp3);
+ when pavr_alu_v_sel_sub8 =>
+ tmp1 := pavr_alu_op1(7);
+ tmp2 := pavr_alu_op2(7);
+ tmp3 := pavr_alu_out_int(7);
+ pavr_alu_flagsout_int(3) <= (tmp1 and (not tmp2) and (not tmp3)) or ((not tmp1) and tmp2 and tmp3);
+ when pavr_alu_v_sel_z =>
+ pavr_alu_flagsout_int(3) <= '0';
+ when pavr_alu_v_sel_inc8 | pavr_alu_v_sel_neg8 =>
+ pavr_alu_flagsout_int(3) <= not pavr_alu_out_int(0);
+ for i in 1 to 6 loop
+ pavr_alu_flagsout_int(3) <= pavr_alu_flagsout_int(3) and (not pavr_alu_out_int(i));
+ end loop;
+ pavr_alu_flagsout_int(3) <= pavr_alu_flagsout_int(3) and pavr_alu_out_int(7);
+ when pavr_alu_v_sel_dec8 =>
+ pavr_alu_flagsout_int(3) <= pavr_alu_out_int(0);
+ for i in 1 to 6 loop
+ pavr_alu_flagsout_int(3) <= pavr_alu_flagsout_int(3) and pavr_alu_out_int(i);
+ end loop;
+ pavr_alu_flagsout_int(3) <= pavr_alu_flagsout_int(3) and (not pavr_alu_out_int(7));
+ when pavr_alu_v_sel_nxorc =>
+ pavr_alu_flagsout_int(3) <= pavr_alu_flagsout_int(2) xor pavr_alu_flagsout_int(0);
+ when pavr_alu_v_sel_add16 =>
+ pavr_alu_flagsout_int(3) <= (not pavr_alu_op1(15)) and pavr_alu_out_int(15);
+ -- When pavr_alu_v_sel_sub16
+ when others =>
+ pavr_alu_flagsout_int(3) <= pavr_alu_op1(15) and (not pavr_alu_out_int(15));
+ end case;
+
+ -- Build S flag.
+ case pavr_alu_s_sel is
+ when pavr_alu_s_sel_same =>
+ pavr_alu_flagsout_int(4) <= pavr_alu_flagsin(4);
+ -- When pavr_alu_s_sel_nxorv
+ when others =>
+ pavr_alu_flagsout_int(4) <= pavr_alu_flagsout_int(2) xor pavr_alu_flagsout_int(3);
+ end case;
+
+ tmp1 := pavr_alu_op1(3);
+ tmp2 := pavr_alu_op2(3);
+ tmp3 := pavr_alu_out_int(3);
+ -- Build H flag.
+ case pavr_alu_h_sel is
+ when pavr_alu_h_sel_same =>
+ pavr_alu_flagsout_int(5) <= pavr_alu_flagsin(5);
+ when pavr_alu_h_sel_add8 =>
+ pavr_alu_flagsout_int(5) <= (tmp1 and tmp2) or (tmp2 and (not tmp3)) or ((not tmp3) and tmp1);
+ when pavr_alu_h_sel_sub8 =>
+ pavr_alu_flagsout_int(5) <= ((not tmp1) and tmp2) or (tmp2 and tmp3) or (tmp3 and (not tmp1));
+ -- When pavr_alu_h_sel_neg8 =>
+ when others =>
+ pavr_alu_flagsout_int(5) <= tmp1 or tmp3;
+ end case;
+ end process alu_flags;
+
+
+
+ -- Zero-level assignments
+ pavr_alu_out <= pavr_alu_out_int;
+ pavr_alu_flagsout <= pavr_alu_flagsout_int;
+
+end;
+--
Index: group__pavr__pipeline__returns.html
===================================================================
--- group__pavr__pipeline__returns.html (nonexistent)
+++ group__pavr__pipeline__returns.html (revision 6)
@@ -0,0 +1,34 @@
+
+
+Returns
+
+
+
+
+Main Page Modules Related Pages
+
Returns
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__hwres__iof__eindwr.html
===================================================================
--- group__pavr__hwres__iof__eindwr.html (nonexistent)
+++ group__pavr__hwres__iof__eindwr.html (revision 6)
@@ -0,0 +1,35 @@
+
+
+EIND port
+
+
+
+
+Main Page Modules Related Pages
+
EIND port
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: wave.do
===================================================================
--- wave.do (nonexistent)
+++ wave.do (revision 6)
@@ -0,0 +1,1093 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -radix unsigned /test_pavr/main_clk_cnt
+add wave -noupdate -radix default -format Logic /test_pavr/pm_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pm_di
+add wave -noupdate -radix default -format Logic /test_pavr/pm_wr
+add wave -noupdate -radix unsigned /test_pavr/pm_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_clk
+add wave -noupdate -radix unsigned /test_pavr/run_clk_cnt
+add wave -noupdate -radix unsigned /test_pavr/instr_cnt
+add wave -noupdate -radix default /test_pavr/pavr_pavr_inc_instr_cnt
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_res
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_syncres
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_pavr_res
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_pavr_syncres
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_addr_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s1_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s2_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s3_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_pavr_pm_do
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s3_instr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s3_instr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_instr32bits
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_pavr_pm_wr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_pcinc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_pcinc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_grant_s2_pm_access
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_grant_control_flow_access
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_freeze_control_flow
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_k12rel_23b
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_do
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_pm_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s1_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s1_pc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s2_pmdo_valid
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s2_pmdo_valid
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s2_pmdo_valid_shadow
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_pm_do_shadow_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd1_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd2_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_do_shadow
+add wave -noupdate -radix default /test_pavr/pavr_instance1/rfrd1_manager/v_rfrd1rq_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_rfrd1_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_rfrd2_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s3_rfrd1_addr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s3_rfrd2_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_rfrd1_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_rfwr_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/next_pavr_s4_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/next_pavr_s4_s61_rfwr_addr2
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_bpr0wr_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr0
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr0_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_bpr0_active
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_bpr1wr_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr1_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_bpr1_active
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_iof_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_s5s6_iof_addr
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5s6_iof_bitaddr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_clriflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_setiflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_inc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51s52_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51_retinc_spwr_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_opcode
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_op1_hi8_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_op2_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_s5_k8
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_do_shadow_active
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_dacu_do_shadow_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dacu_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd1_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd2_do_shadow
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_op1_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op1bpu
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_op2_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op2bpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_flagsin
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_flagsout
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_alu_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_out
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/next_pavr_s4_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_iof_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_dm_dacu_q
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_dacudo_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_dacu_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_dacu_dm_addr
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_dacu_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dacu_do
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp10_1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp10_2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp10_3
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp18_1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp18_2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp18_3
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s6_alu_out
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s61_alu_out_hi8
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_x_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_y_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_z_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_sp_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_k16_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51s52_pc_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_sp_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_k16_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_x_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_y_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_z_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51s52_pc_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_dmrd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_dmwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_lpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_elpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_z_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_zeind_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_k22abs_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_k12rel_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_k22int_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_branch_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_skip_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr00_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr00_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr00
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr01_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr01_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr01
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr02_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr02_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr02
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr03_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr03_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr03
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr10_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr10_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr10
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr11_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr11_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr11
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr12_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr12_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr12
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr13_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr13_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr13
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr20
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr20_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr20_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr21
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr21_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr21_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr22
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr22_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr22_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr23
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr23_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr23_active
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_k6
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_k12
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_k22int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_k12rel_23b
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_addr_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_zlsb
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s51s52s53_retpc_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s6_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s61_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s6_branch_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_nop_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_skip_en
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_skip_bitrf_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s6_skip_bitiof_sel
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/next_pavr_s4_s5_k7_branch_offset
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_branch_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_branch_en
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_branch_bitsreg_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_branch_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_nop_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s53_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s54_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s55_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s1_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s2_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s1
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s2
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s3
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s4
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s5
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s6
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s1
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s2
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s3
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s4
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s5
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s6
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_instr32bits
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_int_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_int_vec
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_rf_rd1_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_rd1_rd
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd1_do
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_rf_rd2_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_rd2_rd
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd2_do
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_rf_wr_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_wr_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_wr_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_x
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_x_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_x_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_y
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_y_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_y_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_z
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_z_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_z_di
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_do
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_bitaddr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_bitout
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sreg
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_sreg_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sreg_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_spl
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_spl_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_spl_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sph
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_sph_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sph_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampx
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampx_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampx_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampy
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampy_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampy_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampz
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampz_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampz_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampd
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampd_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampd_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_eind
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_eind_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_eind_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_do
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_dm_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_di
+add wave -noupdate -radix binary /test_pavr/pavr_instance1/dacu_manager/tmpv_rd
+add wave -noupdate -radix binary /test_pavr/pavr_instance1/dacu_manager/tmpv_wr
+add wave -noupdate -radix binary /test_pavr/pavr_instance1/dacu_manager/tmpv_rdwr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_dacu_wr_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_dacu_ptr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_rf_dacu_addrtest
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_iof_dacu_addrtest
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_dm_dacu_addrtest
+add wave -noupdate -radix default /test_pavr/pavr_instance1/dacu_manager/v_pavr_dacu_device_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_iof_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_iof_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_iof_rfwr_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s61_rfwr_addr2
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_s61_rfwr_addr2
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_s61_rfwr_addr2
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s61_rfwr_addr2
+add wave -noupdate -radix default /test_pavr/pavr_instance1/bpr0wr_manager/v_bpr0wrrq_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_alu_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_daculd_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_iof_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_iof_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_daculd_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_alu_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_iof_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_daculd_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacust_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_pmdo_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_alu_bpr1wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_alu_bpr1wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dacux_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dacuy_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dacuz_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dacux_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacux_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dacuy_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacuy_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dacuz_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacuz_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_iof_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s5_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s6_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_s6_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s6_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_s5s6_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s6_iof_addr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s5s6_iof_bitaddr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_iof_bitaddr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_iof_bitaddr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_alu_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_alu_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_clriflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_clriflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_setiflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_setiflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_inc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_inc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51s52_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51_retinc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_retinc2_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_retinc_spwr_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_k8
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s5_rf_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s5_iof_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s5_dm_dacu_q
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s6_dacudo_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_k16
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_x_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_x_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_y_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_y_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_z_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_z_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_sp_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_sp_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_k16_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_k16_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51s52_pc_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_pchi8_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_pcmid8_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_pclo8_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_sp_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_sp_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_k16_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_k16_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_x_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_x_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_y_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_y_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_z_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_z_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51s52_pc_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_pclo8_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_pcmid8_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_pchi8_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_lpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_lpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_elpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_elpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_z_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_zeind_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_k22abs_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_k12rel_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_k22int_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s53_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s54_ret_pm_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_k6
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_k12
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_k22int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s2_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s3_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s51_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s52_pc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s51s52s53_retpc_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s51s52s53_retpc_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_retpchi8_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_retpcmid8_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s53_retpclo8_ld
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s52_retpchi8
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s53_retpcmid8
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s54_retpclo8
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s5_skip_cond_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_en
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s5_skip_bitrf_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_skip_bitrf_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s6_skip_bitiof_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_s6_skip_bitiof_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_skip_bitiof_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_s5_k7_branch_offset
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_k7_branch_offset
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s6_branch_pc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_branch_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_branch_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_branch_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_branch_en
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s5_branch_bitsreg_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_clk
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_res
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_syncres
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_opcode
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_do
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_bitout
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_bitaddr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_pa
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_vec
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_branch_bitsreg_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_nop_ack
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_instr32bits
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_disable_int
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_instance1/clk_t0_cnt
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/next_pavr_t0_clk
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_t0_clk
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int0_clk
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_mcucr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_gimsk
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_gifr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_tcnt0
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_tccr0
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_tifr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_timsk
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_porta
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_ddra
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_pina
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_tmpdi
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_flgs
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_flgs_dcd
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sreg
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_xbpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_ybpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_zbpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_instance1/data_array
+add wave -noupdate -radix hexadecimal -expand /test_pavr/pavr_instance1/pavr_rf_instance1/pavr_rf_data_array
+add wave -noupdate -radix default -format Logic /test_pavr/pm_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pm_di
+add wave -noupdate -radix default -format Logic /test_pavr/pm_wr
+add wave -noupdate -radix unsigned /test_pavr/pm_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_clk
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_res
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_syncres
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_pavr_res
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_pavr_syncres
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_addr_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s1_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s2_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s3_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_pavr_pm_do
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s3_instr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s3_instr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_instr32bits
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_pavr_pm_wr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_pcinc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_pcinc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_grant_s2_pm_access
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_grant_control_flow_access
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_freeze_control_flow
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_k12rel_23b
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_do
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_pm_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s1_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s1_pc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s2_pmdo_valid
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s2_pmdo_valid
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s2_pmdo_valid_shadow
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_pm_do_shadow_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd1_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd2_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_do_shadow
+add wave -noupdate -radix default /test_pavr/pavr_instance1/rfrd1_manager/v_rfrd1rq_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_rfrd1_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_rfrd2_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s3_rfrd1_addr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s3_rfrd2_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_rfrd1_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_rfwr_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/next_pavr_s4_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/next_pavr_s4_s61_rfwr_addr2
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_bpr0wr_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr0
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr0_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_bpr0_active
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_bpr1wr_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr1_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_bpr1_active
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_iof_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_s5s6_iof_addr
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5s6_iof_bitaddr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_clriflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_setiflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_inc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51s52_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51_retinc_spwr_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_opcode
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_op1_hi8_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_op2_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_s5_k8
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_do_shadow_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd1_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd2_do_shadow
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_op1_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op1bpu
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_op2_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op2bpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_flagsin
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_flagsout
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_alu_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_out
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/next_pavr_s4_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_iof_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_dm_dacu_q
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_dacudo_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_dacu_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_dacu_dm_addr
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_dacu_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dacu_do
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp10_1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp10_2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp10_3
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp18_1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp18_2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp18_3
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s6_alu_out
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s61_alu_out_hi8
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_x_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_y_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_z_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_sp_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_k16_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51s52_pc_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_sp_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_k16_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_x_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_y_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_z_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51s52_pc_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_dmrd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_dmwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_lpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_elpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_z_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_zeind_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_k22abs_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_k12rel_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_k22int_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_branch_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_skip_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr00_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr00_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr00
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr01_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr01_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr01
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr02_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr02_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr02
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr03_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr03_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr03
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr10_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr10_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr10
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr11_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr11_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr11
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr12_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr12_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr12
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr13_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr13_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr13
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr20
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr20_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr20_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr21
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr21_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr21_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr22
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr22_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr22_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr23
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr23_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr23_active
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_k6
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_k12
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_k22int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_k12rel_23b
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_addr_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_zlsb
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s51s52s53_retpc_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s6_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s61_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s6_branch_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_nop_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_skip_en
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_skip_bitrf_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s6_skip_bitiof_sel
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/next_pavr_s4_s5_k7_branch_offset
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_branch_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_branch_en
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_branch_bitsreg_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_branch_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_nop_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s53_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s54_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s55_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s1_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s2_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s1
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s2
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s3
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s4
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s5
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s6
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s1
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s2
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s3
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s4
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s5
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s6
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_instr32bits
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_int_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_int_vec
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_rf_rd1_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_rd1_rd
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd1_do
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_rf_rd2_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_rd2_rd
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd2_do
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_rf_wr_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_wr_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_wr_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_x
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_x_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_x_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_y
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_y_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_y_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_z
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_z_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_z_di
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_do
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_bitaddr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_bitout
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sreg
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_sreg_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sreg_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_spl
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_spl_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_spl_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sph
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_sph_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sph_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampx
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampx_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampx_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampy
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampy_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampy_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampz
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampz_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampz_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampd
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampd_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampd_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_eind
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_eind_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_eind_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_do
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_dm_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_di
+add wave -noupdate -radix binary /test_pavr/pavr_instance1/dacu_manager/tmpv_rd
+add wave -noupdate -radix binary /test_pavr/pavr_instance1/dacu_manager/tmpv_wr
+add wave -noupdate -radix binary /test_pavr/pavr_instance1/dacu_manager/tmpv_rdwr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_dacu_wr_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_dacu_ptr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_rf_dacu_addrtest
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_iof_dacu_addrtest
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_dm_dacu_addrtest
+add wave -noupdate -radix default /test_pavr/pavr_instance1/dacu_manager/v_pavr_dacu_device_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_iof_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_iof_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_iof_rfwr_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s61_rfwr_addr2
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_s61_rfwr_addr2
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_s61_rfwr_addr2
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s61_rfwr_addr2
+add wave -noupdate -radix default /test_pavr/pavr_instance1/bpr0wr_manager/v_bpr0wrrq_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_alu_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_daculd_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_iof_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_iof_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_daculd_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_alu_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_iof_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_daculd_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacust_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_pmdo_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_alu_bpr1wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_alu_bpr1wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dacux_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dacuy_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dacuz_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dacux_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacux_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dacuy_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacuy_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dacuz_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacuz_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_iof_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s5_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s6_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_s6_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s6_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_s5s6_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s6_iof_addr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s5s6_iof_bitaddr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_iof_bitaddr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_iof_bitaddr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_alu_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_alu_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_clriflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_clriflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_setiflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_setiflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_inc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_inc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51s52_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51_retinc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_retinc2_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_retinc_spwr_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_k8
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s5_rf_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s5_iof_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s5_dm_dacu_q
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s6_dacudo_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_k16
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_x_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_x_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_y_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_y_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_z_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_z_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_sp_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_sp_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_k16_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_k16_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51s52_pc_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_pchi8_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_pcmid8_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_pclo8_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_sp_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_sp_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_k16_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_k16_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_x_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_x_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_y_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_y_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_z_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_z_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51s52_pc_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_pclo8_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_pcmid8_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_pchi8_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_lpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_lpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_elpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_elpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_z_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_zeind_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_k22abs_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_k12rel_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_k22int_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s53_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s54_ret_pm_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_k6
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_k12
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_k22int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s2_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s3_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s51_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s52_pc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s51s52s53_retpc_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s51s52s53_retpc_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_retpchi8_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_retpcmid8_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s53_retpclo8_ld
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s52_retpchi8
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s53_retpcmid8
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s54_retpclo8
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s5_skip_cond_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_en
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s5_skip_bitrf_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_skip_bitrf_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s6_skip_bitiof_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_s6_skip_bitiof_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_skip_bitiof_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_s5_k7_branch_offset
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_k7_branch_offset
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s6_branch_pc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_branch_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_branch_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_branch_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_branch_en
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s5_branch_bitsreg_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_clk
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_res
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_syncres
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_opcode
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_do
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_bitout
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_bitaddr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_pa
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_vec
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_branch_bitsreg_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_nop_ack
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_instr32bits
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_disable_int
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_instance1/clk_t0_cnt
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/next_pavr_t0_clk
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_t0_clk
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int0_clk
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_mcucr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_gimsk
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_gifr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_tcnt0
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_tccr0
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_tifr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_timsk
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_porta
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_ddra
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_pina
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_tmpdi
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_flgs
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_flgs_dcd
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sreg
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_xbpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_ybpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_zbpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_instance1/data_array
+add wave -noupdate -radix hexadecimal -expand /test_pavr/pavr_instance1/pavr_rf_instance1/pavr_rf_data_array
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {47832250 ns}
+WaveRestoreZoom {47831259 ns} {47832564 ns}
Index: pavr_hwres_bpr1_01.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: pavr_hwres_bpr1_01.gif
===================================================================
--- pavr_hwres_bpr1_01.gif (nonexistent)
+++ pavr_hwres_bpr1_01.gif (revision 6)
Program Memory
+
+[Hardware resources]
+
- +PM handling
-
+
+++
+
+ The Program Memory is a single port RAM.
+ That port provides read-only access. Support for the instruction SPM (Store Program Memory) is currently not provided.
+ The PM is organized on 16 bit words, and has the length set by a constant in the constants definition file (`pavr-constants.vhd').
+
+ Apart from controlling the Program Memory, the PM manager also controls the Program Counter.
+ Some PM access requests need to modify the PC, others don't. The only PM requests that don't modify the PC are the loads from PM (LPM and ELPM instructions). The other requests correspond to instructions that want to modify the instruction flow, thus modify the PC (jumps, branches, calls and returns).
+
- +Program Counter handling
-
+At a given time, the pipeline can process more than one instruction. Up to 6 instructions can be simultaneousely processed. Obviousely, each of these instructions has its own address in the PM.
+ One may ask: how is defined the Program Counter, as long as two or more instructions are simultaneousely executed? Whose address is considered to be the Program Counter?
+ The answer is: the Program Counter is in fact composed of a set of registers. Each instruction in the pipeline has an associated Program Counter that follows it while flowing through the pipeline. Implementation details can be found in the description of jumps, branches, skips, calls and returns.
+ As an example, when a relative jump computes the target address, it considers its own Program Counter rather than the address of the instruction fetched that moment from the PM. The instructions that modify the instruction flow (jumps, branches, skips, calls and returns) must be able to manipulate the program counters associated with pipeline stages s1, s2 and s3. However, this is done not directly, but via the Program Memory manager. The PM manager centralizes all instruction flow access requests (jump requests, branch requests, etc) and takes care of the program counters in an organized and manageable manner.
+
- +Requests to PM
-
+
-
+
- pavr_s5_lpm_pm_rq
+ Needed by LPM instruction.
+ This request doesn't modify the instruction flow.
+ - pavr_s5_elpm_pm_rq
+ Needed by ELPM instruction.
+ This request doesn't modify the instruction flow.
+ - pavr_s4_z_pm_rq
+ Needed by ICALL and IJMP.
+ - pavr_s4_zeind_pm_rq
+ Needed by EICALL and EIJMP.
+ - pavr_s4_k22abs_pm_rq
+ Needed by CALL and JMP.
+ To get to the jump address, the 16 bit instruction constant is concatenated with a 6 bit constant previousely read also from the instruction opcode. - pavr_s4_k12rel_pm_rq
+ Needed by RCALL and RJMP.
+ Note that pavr_s4_pc is a pipeline register that holds the Program Memory address of the instruction executing in pipeline stage s4.
+ Because the relative jump actually occurs in stage s4, pavr_s4_pc is needed rather than the current Program Counter (pavr_pc). - pavr_s6_branch_pm_rq
+ Needed by branch instructions (BRBC and BRBS).
+ - pavr_s6_skip_pm_rq
+ Needed by some skip instructions (CPSE, SBRC and SBRS).
+ - pavr_s61_skip_pm_rq
+ Needed by some skip instructions (SBIC and SBIS).
+ - pavr_s4_k22int_pm_rq
+ Needed by implicit interrupt CALL.
+ - pavr_s54_ret_pm_rq
+ Needed by RET and RETI.
+
+
- pavr_s5_lpm_pm_rq
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_alu.vhd
===================================================================
--- pavr_alu.vhd (nonexistent)
+++ pavr_alu.vhd (revision 6)
@@ -0,0 +1,443 @@
+-- Returns
+
+[Pipeline details]
+
- +A few details
-
+There are two kinds of returns:
-
+
- RET
+ Return from subroutine.
+ The Program Counter is loaded with the return address (22 bit wide) read from the stack, and the Stack Pointer is incremented by 3. - RETI
+ The same as RET, but in addition sets the general interrupt flag (flag I in the Status Register).
+ Returns are the slowest instructions in the pAVR implementation of the AVR instruction set. They take 9 clocks.
+ First 2 clocks are spent while waiting the previous instructions to write the Unified Memory. Next 5 clocks, the Program Counter is read from the Unified Memory. In a future version, this part might take only 4 clocks. Finally, another 2 clocks are spent while bringing the target instruction into the instruction register.
+
+++
+
+ - RET
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__hwres__iof__eindwr.html
===================================================================
--- group__pavr__hwres__iof__eindwr.html (nonexistent)
+++ group__pavr__hwres__iof__eindwr.html (revision 6)
@@ -0,0 +1,35 @@
+
+
+EIND port
+
+[IO File]
+
- +EIND port connectivity
-
+
+++
+
+ This is a trivial read-only port.
+
+ The register EIND is used in controllers with more than 64K words of Program Memory, to access the whole program space.
+ EIND is used by instructions EICALL (Extended Indirect CALL) and EIJMP (Extended Indirect JuMP). In order to get to the desired program space address, these instructions concatenate EIND with the Z register (EIND:Z).
+
+ In controllers with less than 64K words of Program Memory, this register is not used.
+ The EIND register can be written only through the IOF general read and write port.
+ No instruction explicitely requests to write this register.
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: wave.do
===================================================================
--- wave.do (nonexistent)
+++ wave.do (revision 6)
@@ -0,0 +1,1093 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -radix unsigned /test_pavr/main_clk_cnt
+add wave -noupdate -radix default -format Logic /test_pavr/pm_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pm_di
+add wave -noupdate -radix default -format Logic /test_pavr/pm_wr
+add wave -noupdate -radix unsigned /test_pavr/pm_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_clk
+add wave -noupdate -radix unsigned /test_pavr/run_clk_cnt
+add wave -noupdate -radix unsigned /test_pavr/instr_cnt
+add wave -noupdate -radix default /test_pavr/pavr_pavr_inc_instr_cnt
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_res
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_syncres
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_pavr_res
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_pavr_syncres
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_addr_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s1_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s2_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s3_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_pavr_pm_do
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s3_instr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s3_instr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_instr32bits
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_pavr_pm_wr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_pcinc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_pcinc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_grant_s2_pm_access
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_grant_control_flow_access
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_freeze_control_flow
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_k12rel_23b
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_do
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_pm_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s1_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s1_pc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s2_pmdo_valid
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s2_pmdo_valid
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s2_pmdo_valid_shadow
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_pm_do_shadow_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd1_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd2_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_do_shadow
+add wave -noupdate -radix default /test_pavr/pavr_instance1/rfrd1_manager/v_rfrd1rq_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_rfrd1_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_rfrd2_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s3_rfrd1_addr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s3_rfrd2_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_rfrd1_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_rfwr_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/next_pavr_s4_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/next_pavr_s4_s61_rfwr_addr2
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_bpr0wr_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr0
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr0_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_bpr0_active
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_bpr1wr_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr1_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_bpr1_active
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_iof_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_s5s6_iof_addr
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5s6_iof_bitaddr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_clriflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_setiflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_inc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51s52_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51_retinc_spwr_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_opcode
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_op1_hi8_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_op2_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_s5_k8
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_do_shadow_active
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_dacu_do_shadow_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dacu_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd1_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd2_do_shadow
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_op1_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op1bpu
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_op2_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op2bpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_flagsin
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_flagsout
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_alu_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_out
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/next_pavr_s4_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_iof_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_dm_dacu_q
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_dacudo_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_dacu_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_dacu_dm_addr
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_dacu_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dacu_do
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp10_1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp10_2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp10_3
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp18_1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp18_2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp18_3
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s6_alu_out
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s61_alu_out_hi8
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_x_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_y_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_z_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_sp_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_k16_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51s52_pc_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_sp_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_k16_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_x_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_y_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_z_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51s52_pc_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_dmrd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_dmwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_lpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_elpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_z_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_zeind_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_k22abs_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_k12rel_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_k22int_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_branch_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_skip_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr00_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr00_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr00
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr01_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr01_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr01
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr02_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr02_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr02
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr03_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr03_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr03
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr10_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr10_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr10
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr11_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr11_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr11
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr12_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr12_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr12
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr13_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr13_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr13
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr20
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr20_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr20_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr21
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr21_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr21_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr22
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr22_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr22_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr23
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr23_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr23_active
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_k6
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_k12
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_k22int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_k12rel_23b
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_addr_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_zlsb
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s51s52s53_retpc_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s6_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s61_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s6_branch_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_nop_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_skip_en
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_skip_bitrf_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s6_skip_bitiof_sel
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/next_pavr_s4_s5_k7_branch_offset
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_branch_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_branch_en
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_branch_bitsreg_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_branch_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_nop_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s53_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s54_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s55_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s1_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s2_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s1
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s2
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s3
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s4
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s5
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s6
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s1
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s2
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s3
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s4
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s5
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s6
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_instr32bits
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_int_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_int_vec
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_rf_rd1_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_rd1_rd
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd1_do
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_rf_rd2_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_rd2_rd
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd2_do
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_rf_wr_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_wr_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_wr_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_x
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_x_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_x_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_y
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_y_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_y_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_z
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_z_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_z_di
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_do
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_bitaddr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_bitout
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sreg
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_sreg_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sreg_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_spl
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_spl_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_spl_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sph
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_sph_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sph_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampx
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampx_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampx_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampy
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampy_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampy_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampz
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampz_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampz_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampd
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampd_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampd_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_eind
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_eind_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_eind_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_do
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_dm_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_di
+add wave -noupdate -radix binary /test_pavr/pavr_instance1/dacu_manager/tmpv_rd
+add wave -noupdate -radix binary /test_pavr/pavr_instance1/dacu_manager/tmpv_wr
+add wave -noupdate -radix binary /test_pavr/pavr_instance1/dacu_manager/tmpv_rdwr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_dacu_wr_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_dacu_ptr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_rf_dacu_addrtest
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_iof_dacu_addrtest
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_dm_dacu_addrtest
+add wave -noupdate -radix default /test_pavr/pavr_instance1/dacu_manager/v_pavr_dacu_device_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_iof_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_iof_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_iof_rfwr_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s61_rfwr_addr2
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_s61_rfwr_addr2
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_s61_rfwr_addr2
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s61_rfwr_addr2
+add wave -noupdate -radix default /test_pavr/pavr_instance1/bpr0wr_manager/v_bpr0wrrq_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_alu_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_daculd_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_iof_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_iof_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_daculd_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_alu_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_iof_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_daculd_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacust_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_pmdo_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_alu_bpr1wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_alu_bpr1wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dacux_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dacuy_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dacuz_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dacux_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacux_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dacuy_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacuy_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dacuz_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacuz_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_iof_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s5_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s6_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_s6_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s6_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_s5s6_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s6_iof_addr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s5s6_iof_bitaddr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_iof_bitaddr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_iof_bitaddr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_alu_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_alu_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_clriflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_clriflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_setiflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_setiflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_inc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_inc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51s52_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51_retinc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_retinc2_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_retinc_spwr_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_k8
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s5_rf_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s5_iof_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s5_dm_dacu_q
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s6_dacudo_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_k16
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_x_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_x_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_y_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_y_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_z_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_z_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_sp_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_sp_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_k16_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_k16_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51s52_pc_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_pchi8_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_pcmid8_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_pclo8_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_sp_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_sp_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_k16_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_k16_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_x_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_x_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_y_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_y_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_z_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_z_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51s52_pc_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_pclo8_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_pcmid8_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_pchi8_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_lpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_lpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_elpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_elpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_z_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_zeind_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_k22abs_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_k12rel_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_k22int_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s53_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s54_ret_pm_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_k6
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_k12
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_k22int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s2_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s3_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s51_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s52_pc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s51s52s53_retpc_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s51s52s53_retpc_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_retpchi8_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_retpcmid8_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s53_retpclo8_ld
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s52_retpchi8
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s53_retpcmid8
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s54_retpclo8
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s5_skip_cond_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_en
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s5_skip_bitrf_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_skip_bitrf_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s6_skip_bitiof_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_s6_skip_bitiof_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_skip_bitiof_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_s5_k7_branch_offset
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_k7_branch_offset
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s6_branch_pc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_branch_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_branch_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_branch_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_branch_en
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s5_branch_bitsreg_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_clk
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_res
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_syncres
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_opcode
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_do
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_bitout
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_bitaddr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_pa
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_vec
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_branch_bitsreg_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_nop_ack
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_instr32bits
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_disable_int
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_instance1/clk_t0_cnt
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/next_pavr_t0_clk
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_t0_clk
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int0_clk
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_mcucr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_gimsk
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_gifr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_tcnt0
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_tccr0
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_tifr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_timsk
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_porta
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_ddra
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_pina
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_tmpdi
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_flgs
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_flgs_dcd
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sreg
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_xbpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_ybpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_zbpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_instance1/data_array
+add wave -noupdate -radix hexadecimal -expand /test_pavr/pavr_instance1/pavr_rf_instance1/pavr_rf_data_array
+add wave -noupdate -radix default -format Logic /test_pavr/pm_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pm_di
+add wave -noupdate -radix default -format Logic /test_pavr/pm_wr
+add wave -noupdate -radix unsigned /test_pavr/pm_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_clk
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_res
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_syncres
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_pavr_res
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_pavr_syncres
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_addr_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s1_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s2_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s3_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_pavr_pm_do
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s3_instr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s3_instr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_instr32bits
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_pavr_pm_wr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_pcinc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_pcinc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_grant_s2_pm_access
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_grant_control_flow_access
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_freeze_control_flow
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_k12rel_23b
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_do
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_pm_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s1_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s1_pc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s2_pmdo_valid
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s2_pmdo_valid
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s2_pmdo_valid_shadow
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_pm_do_shadow_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd1_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd2_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_do_shadow
+add wave -noupdate -radix default /test_pavr/pavr_instance1/rfrd1_manager/v_rfrd1rq_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_rfrd1_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_rfrd2_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s3_rfrd1_addr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s3_rfrd2_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_rfrd1_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_rfwr_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/next_pavr_s4_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/next_pavr_s4_s61_rfwr_addr2
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_bpr0wr_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr0
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr0_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_bpr0_active
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_bpr1wr_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_bpr1_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_bpr1_active
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_iof_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s6_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_s5s6_iof_addr
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5s6_iof_bitaddr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_clriflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_setiflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_inc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51s52_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51_retinc_spwr_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_opcode
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_op1_hi8_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_alu_op2_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_s5_k8
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_do_shadow_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd1_do_shadow
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd2_do_shadow
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_op1_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op1bpu
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_op2_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_op2bpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_flagsin
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_flagsout
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_alu_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_alu_out
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/next_pavr_s4_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_iof_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_dm_dacu_q
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_dacudo_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_dacu_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_dacu_dm_addr
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_dacu_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dacu_do
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp10_1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp10_2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp10_3
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp18_1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp18_2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_alu_instance1/tmp18_3
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s6_alu_out
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s61_alu_out_hi8
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_x_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_y_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_z_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_sp_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_k16_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51s52_pc_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_sp_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_k16_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_x_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_y_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_z_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5s51s52_pc_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_dmrd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacu_dmwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_lpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_elpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_z_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_zeind_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_k22abs_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_k12rel_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_k22int_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_branch_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_skip_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr00_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr00_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr00
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr01_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr01_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr01
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr02_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr02_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr02
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr03_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr03_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr03
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr10_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr10_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr10
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr11_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr11_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr11
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr12_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr12_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr12
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr13_active
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr13_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr13
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr20
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr20_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr20_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr21
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr21_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr21_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr22
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr22_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr22_active
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_bpr23
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_bpr23_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_bpr23_active
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_k6
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_k12
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/next_pavr_s4_k22int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op1
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_22b_op2
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pm_manager/v_pavr_pc_k12rel_23b
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_pm_addr_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_zlsb
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s51s52s53_retpc_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s6_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s61_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s6_branch_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_nop_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s6_skip_en
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_skip_bitrf_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s6_skip_bitiof_sel
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/next_pavr_s4_s5_k7_branch_offset
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_branch_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_branch_en
+add wave -noupdate -radix default /test_pavr/pavr_instance1/next_pavr_s4_s5_branch_bitsreg_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_stall_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_branch_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_nop_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s53_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s54_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s55_ret_flush_s2_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s1_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s2_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s3_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_hwrq_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s1
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s2
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s3
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s4
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s5
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_stall_s6
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s1
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s2
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s3
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s4
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s5
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_flush_s6
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_instr32bits
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_int_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_int_vec
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_rf_rd1_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_rd1_rd
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd1_do
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_rf_rd2_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_rd2_rd
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_rd2_do
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_rf_wr_addr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_wr_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_wr_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_x
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_x_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_x_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_y
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_y_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_y_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_z
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_rf_z_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_rf_z_di
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_do
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_bitaddr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_bitout
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sreg
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_sreg_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sreg_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_spl
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_spl_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_spl_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sph
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_sph_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sph_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampx
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampx_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampx_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampy
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampy_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampy_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampz
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampz_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampz_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampd
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_rampd_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_rampd_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_eind
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_iof_eind_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_eind_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_do
+add wave -noupdate -radix hexadecimal -format Logic /test_pavr/pavr_instance1/pavr_dm_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_di
+add wave -noupdate -radix binary /test_pavr/pavr_instance1/dacu_manager/tmpv_rd
+add wave -noupdate -radix binary /test_pavr/pavr_instance1/dacu_manager/tmpv_wr
+add wave -noupdate -radix binary /test_pavr/pavr_instance1/dacu_manager/tmpv_rdwr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_dacu_wr_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_dacu_ptr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_rf_dacu_addrtest
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_iof_dacu_addrtest
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/dacu_manager/v_pavr_s5_dm_dacu_addrtest
+add wave -noupdate -radix default /test_pavr/pavr_instance1/dacu_manager/v_pavr_dacu_device_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_aluoutlo8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s61_aluouthi8_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_iof_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_iof_rfwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_iof_rfwr_rq
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_rfwr_addr1
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s61_rfwr_addr2
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_s61_rfwr_addr2
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_s61_rfwr_addr2
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s61_rfwr_addr2
+add wave -noupdate -radix default /test_pavr/pavr_instance1/bpr0wr_manager/v_bpr0wrrq_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_alu_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_daculd_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_iof_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_iof_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_daculd_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_alu_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_iof_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_daculd_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacust_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_pmdo_bpr0wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_alu_bpr1wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_alu_bpr1wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dacux_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dacuy_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/next_pavr_s4_s5_dacuz_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dacux_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacux_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dacuy_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacuy_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dacuz_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dacuz_bpr12wr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_iof_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_iof_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s5_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s6_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_s6_iof_opcode
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s6_iof_opcode
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_s5s6_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s6_iof_addr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s5s6_iof_bitaddr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_iof_bitaddr
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_iof_bitaddr
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_alu_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_alu_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_clriflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_clriflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_setiflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_setiflag_sregwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_inc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_inc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_dec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_dec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51s52_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_calldec_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51_retinc_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_retinc2_spwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_retinc_spwr_rq
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_k8
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s5_rf_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s5_iof_dacu_q
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s5_dm_dacu_q
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s6_dacudo_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_k16
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_x_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_x_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_y_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_y_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_z_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_z_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_sp_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_sp_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_k16_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_k16_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51s52_pc_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_pchi8_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_pcmid8_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_pclo8_dacurd_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_sp_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_sp_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_k16_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_k16_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_x_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_x_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_y_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_y_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_z_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_z_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5s51s52_pc_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_pclo8_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_pcmid8_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_pchi8_dacuwr_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_lpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_lpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_elpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_elpm_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_z_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_zeind_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_k22abs_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_k12rel_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_k22int_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s53_s54_ret_pm_rq
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s54_ret_pm_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_k6
+add wave -noupdate -radix decimal /test_pavr/pavr_instance1/pavr_s4_k12
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_k22int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s2_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s3_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s51_pc
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s52_pc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s51s52s53_retpc_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s51s52s53_retpc_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_retpchi8_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_retpcmid8_ld
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s53_retpclo8_ld
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s52_retpchi8
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s53_retpcmid8
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s54_retpclo8
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s5_skip_cond_sel
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s6_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_s6_skip_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s6_skip_en
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s5_skip_bitrf_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_skip_bitrf_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s4_s6_skip_bitiof_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s5_s6_skip_bitiof_sel
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_s6_skip_bitiof_sel
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s4_s5_k7_branch_offset
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s5_k7_branch_offset
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_s6_branch_pc
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_branch_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_branch_cond_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_s5_branch_en
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_branch_en
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s4_s5_branch_bitsreg_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_clk
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_res
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_syncres
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_opcode
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_addr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_do
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_bitout
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_bitaddr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind_wr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind_di
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_pa
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_rq
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_vec
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_s5_branch_bitsreg_sel
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_nop_ack
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_instr32bits
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s4_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s5_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s51_disable_int
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_s52_disable_int
+add wave -noupdate -radix unsigned /test_pavr/pavr_instance1/pavr_iof_instance1/clk_t0_cnt
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/next_pavr_t0_clk
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_t0_clk
+add wave -noupdate -radix default -format Logic /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int0_clk
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sreg_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_sph_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_spl_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampx_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampy_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampz_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_rampd_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_eind_int
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_mcucr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_gimsk
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_gifr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_tcnt0
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_tccr0
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_tifr
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_timsk
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_porta
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_ddra
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_iof_pina
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_tmpdi
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_flgs
+add wave -noupdate -radix default /test_pavr/pavr_instance1/pavr_iof_instance1/pavr_int_flgs_dcd
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_iof_sreg
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_xbpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_ybpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_zbpu
+add wave -noupdate -radix hexadecimal /test_pavr/pavr_instance1/pavr_dm_instance1/data_array
+add wave -noupdate -radix hexadecimal -expand /test_pavr/pavr_instance1/pavr_rf_instance1/pavr_rf_data_array
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {47832250 ns}
+WaveRestoreZoom {47831259 ns} {47832564 ns}
Index: pavr_hwres_bpr1_01.gif
===================================================================
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Index: pavr_hwres_bpr1_01.gif
===================================================================
--- pavr_hwres_bpr1_01.gif (nonexistent)
+++ pavr_hwres_bpr1_01.gif (revision 6)
pavr_hwres_bpr1_01.gif
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+application/octet-stream
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Index: pavr_hwres_iof_perif_t0_01.gif
===================================================================
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Index: pavr_hwres_iof_perif_t0_01.gif
===================================================================
--- pavr_hwres_iof_perif_t0_01.gif (nonexistent)
+++ pavr_hwres_iof_perif_t0_01.gif (revision 6)
pavr_hwres_iof_perif_t0_01.gif
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Index: pavr_hwres_iof_perif_t0_03.gif
===================================================================
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Index: pavr_hwres_iof_perif_t0_03.gif
===================================================================
--- pavr_hwres_iof_perif_t0_03.gif (nonexistent)
+++ pavr_hwres_iof_perif_t0_03.gif (revision 6)
pavr_hwres_iof_perif_t0_03.gif
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+application/octet-stream
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Index: pavr_pipe_returns_01.gif
===================================================================
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Index: pavr_pipe_returns_01.gif
===================================================================
--- pavr_pipe_returns_01.gif (nonexistent)
+++ pavr_pipe_returns_01.gif (revision 6)
pavr_pipe_returns_01.gif
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+application/octet-stream
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Index: test_pavr_data_mem.vhd
===================================================================
--- test_pavr_data_mem.vhd (nonexistent)
+++ test_pavr_data_mem.vhd (revision 6)
@@ -0,0 +1,152 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- Test the Data Memory.
+-- A trivial read-write test.
+--
+
+
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+library work;
+use work.std_util.all;
+use work.pavr_util.all;
+use work.pavr_constants.all;
+
+
+entity test_pavr_dm is
+end;
+
+
+architecture test_pavr_dm_arch of test_pavr_dm is
+ signal clk, res: std_logic;
+
+ -- Clock counter
+ signal cnt: std_logic_vector(7 downto 0);
+
+ -- DM connectivity
+ signal pavr_dm_do : std_logic_vector(7 downto 0);
+ signal pavr_dm_wr : std_logic;
+ signal pavr_dm_addr : std_logic_vector(pavr_dm_addr_w - 1 downto 0);
+ signal pavr_dm_di : std_logic_vector(7 downto 0);
+
+ -- Declare the Data Memory
+ component pavr_dm
+ port(
+ pavr_dm_clk: in std_logic;
+ pavr_dm_wr: in std_logic;
+ pavr_dm_addr: in std_logic_vector(pavr_dm_addr_w - 1 downto 0);
+ pavr_dm_di: in std_logic_vector(7 downto 0);
+ pavr_dm_do: out std_logic_vector(7 downto 0)
+ );
+ end component;
+ for all: pavr_dm use entity work.pavr_dm(pavr_dm_arch);
+
+begin
+
+ -- Instantiate the Data Memory
+ pavr_dm_instance1: pavr_dm
+ port map(
+ clk,
+ pavr_dm_wr,
+ pavr_dm_addr,
+ pavr_dm_di,
+ pavr_dm_do
+ );
+
+ generate_clock:
+ process
+ begin
+ clk <= '1';
+ wait for 50 ns;
+ clk <= '0';
+ wait for 50 ns;
+ end process generate_clock;
+
+
+ generate_reset:
+ process
+ begin
+ res <= '0';
+ wait for 100 ns;
+ res <= '1';
+ wait for 110 ns;
+ res <= '0';
+ wait for 1 ms;
+ end process generate_reset;
+
+
+ test_main:
+ process(clk, res,
+ cnt,
+ pavr_dm_addr, pavr_dm_di
+ )
+ begin
+ if res='1' then
+ -- Async reset
+ cnt <= int_to_std_logic_vector(0, cnt'length);
+ elsif clk'event and clk='1' then
+ -- Clock counter
+ cnt <= cnt+1;
+
+ -- Initialize inputs.
+ pavr_dm_wr <= '0';
+ pavr_dm_addr <= int_to_std_logic_vector(0, pavr_dm_addr'length);
+ pavr_dm_di <= int_to_std_logic_vector(0, pavr_dm_di'length);
+
+ case std_logic_vector_to_nat(cnt) is
+ -- TEST 1. Write DM.
+ when 3 =>
+ pavr_dm_wr <= '1';
+ pavr_dm_addr <= int_to_std_logic_vector(24, pavr_dm_addr'length);
+ pavr_dm_di <= int_to_std_logic_vector(16#A9#, pavr_dm_di'length);
+
+ -- TEST 2. Read DM.
+ when 4 =>
+ pavr_dm_wr <= '0';
+ pavr_dm_addr <= int_to_std_logic_vector(24, pavr_dm_addr'length);
+
+ when others =>
+ null;
+ end case;
+ end if;
+ end process test_main;
+
+
+end;
+--
Index: pavr_hwres_iof_eind_01.gif
===================================================================
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Index: pavr_hwres_iof_eind_01.gif
===================================================================
--- pavr_hwres_iof_eind_01.gif (nonexistent)
+++ pavr_hwres_iof_eind_01.gif (revision 6)
pavr_hwres_iof_eind_01.gif
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+application/octet-stream
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Index: group__pavr__ref.html
===================================================================
--- group__pavr__ref.html (nonexistent)
+++ group__pavr__ref.html (revision 6)
@@ -0,0 +1,31 @@
+
+
+References
+
+
+
+
+Main Page Modules Related Pages
+
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__hwres__iof__gen.html
===================================================================
--- group__pavr__hwres__iof__gen.html (nonexistent)
+++ group__pavr__hwres__iof__gen.html (revision 6)
@@ -0,0 +1,40 @@
+
+
+General IO port
+
+
+
+
+Main Page Modules Related Pages
+
General IO port
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__pipeline__skips.html
===================================================================
--- group__pavr__pipeline__skips.html (nonexistent)
+++ group__pavr__pipeline__skips.html (revision 6)
@@ -0,0 +1,33 @@
+
+
+Skips
+
+
+
+
+Main Page Modules Related Pages
+
Skips
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__hwres__rf__ywr.html
===================================================================
--- group__pavr__hwres__rf__ywr.html (nonexistent)
+++ group__pavr__hwres__rf__ywr.html (revision 6)
@@ -0,0 +1,38 @@
+
+
+Y port
+
+
+
+
+Main Page Modules Related Pages
+
Y port
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__hwres__rf.html
===================================================================
--- group__pavr__hwres__rf.html (nonexistent)
+++ group__pavr__hwres__rf.html (revision 6)
@@ -0,0 +1,36 @@
+
+
+Register File
+
+
+
+
+Main Page Modules Related Pages
+
Register File
+
+
+ It has 32 locations, 8 bits each.
+ Separate read and write ports for the upper three 16 bit words are provided. The upper three 16 bit words are the pointer registers X (at byte address 27:26), Y (29:28) and Z (31:30).
+ The RF is placed at the beginning of the Unified Memory space.
+
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_hwres_iof_perif_pa_01.gif
===================================================================
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Index: pavr_hwres_iof_perif_pa_01.gif
===================================================================
--- pavr_hwres_iof_perif_pa_01.gif (nonexistent)
+++ pavr_hwres_iof_perif_pa_01.gif (revision 6)
References
- +References
-
+Most of the documentation needed for this project was found on Atmel's website, http://www.atmel.com. While working on this project (2002 Q1, Q2), it was available in PDF format, free for downloading.
+
+ The specific documents that were used are:-
+
- "AVR Instruction Set", Atmel Corporation
- Datasheets for the controllers:
-
+
- ATtiny28 series
- AT90S2313
- AT90S8535
- ATmega8 series
- ATmega103 series
+ While designing pAVR's pipeline, I found many interesting ideas in the book "Computer architecture - a quantitative approach", by J. Hennessy and D. Patterson. If you are a processor designer, then this book is for you.
+
- +Errata
-
+A few bugs have been found in Atmel's documents.
+
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__hwres__iof__gen.html
===================================================================
--- group__pavr__hwres__iof__gen.html (nonexistent)
+++ group__pavr__hwres__iof__gen.html (revision 6)
@@ -0,0 +1,40 @@
+
+
+General IO port
+
+[IO File]
+
- +General IO File port connectivity
-
+
+++
+
+ The general IO File port is a little bit more ellaborated than a simple read/write port. It can read bytes from IO registers to output and write bytes from input to IO registers. Also, it can do some bit processing: load bits (from T flag in SREG to output), store bits (from input to T bit in SREG), set IO bits, clear IO bits.
+ An opcode has to be provided to specify one of the actions that this port is capable of.
+
+ The following opcodes are implemented for the IO File general port:-
+
- read byte (needed by instructions IN, SBIC, SBIS)
- write byte (OUT)
- clear bit (CBI)
- set bit (SBI)
- load bit (BLD)
- store bit (BST)
- +Requests to this port
-
+
-
+
- pavr_s5_iof_rq
+ Needed by instructions that manipulate IO File in stage s5: CBI, SBI, SBIC, SBIS, BSET, BCLR, IN, OUT, BLD, BST. - pavr_s6_iof_rq
+ Needed by instructions that manipulate IO File in stage s6: CBI, SBI, BSET, BCLR. - pavr_s5_dacu_iof_rq
+ Needed by loads and stores that are decoded by DACU as accessing IO File.
+
+
- pavr_s5_iof_rq
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__pipeline__skips.html
===================================================================
--- group__pavr__pipeline__skips.html (nonexistent)
+++ group__pavr__pipeline__skips.html (revision 6)
@@ -0,0 +1,33 @@
+
+
+Skips
+
+[Pipeline details]
+
- +A few details
-
+Skips are implemented as branches that have the relative target address equal to 0, 1 or 2, depending on the skip condition and on whether the following instruction has 16 or 32 bits.
+ There are two kinds of skips: one category that makes the skip request in stage s6 (the same as branches), and one that requests skip in s61. The first category includes instructions CPSE (Compare registers and skip if equal), SBRC and SBRS (skip if bit in register is cleared/set). The second category includes SBIC, SBIS (Skip if bit in IO register is cleared/set).
+
+ CPSE, SBRC and SBRS take 2 clocks if not taken, and 4 clocks if taken.
+ SBIC and SBIS take 3 clocks if not taken, and 5 clocks if taken.
+
- +Skip state machine
-
+
+++
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__hwres__rf__ywr.html
===================================================================
--- group__pavr__hwres__rf__ywr.html (nonexistent)
+++ group__pavr__hwres__rf__ywr.html (revision 6)
@@ -0,0 +1,38 @@
+
+
+Y port
+
+[Register File]
+
- +Y port connectivity
-
+
+++
+
+ This is a read and write port.
+
- +Requests to Y write port
-
+
-
+
- pavr_s5_ldstincrampy_ywr_rq
+ Increment Y or RAMPY:Y.
+ Needed by loads and stores with postincrement.
+ - pavr_s5_ldstdecrampy_ywr_rq
+ Decrement Y or RAMPY:Y.
+ Needed by loads and stores with predecrement.
+
+
- pavr_s5_ldstincrampy_ywr_rq
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__hwres__rf.html
===================================================================
--- group__pavr__hwres__rf.html (nonexistent)
+++ group__pavr__hwres__rf.html (revision 6)
@@ -0,0 +1,36 @@
+
+
+Register File
+
+[Hardware resources]
+
Modules | |
| Read port 1 | |
| Read port 2 | |
| Write port | |
| X port | |
| Y port | |
| Z port | |
Detailed Description
+The Register File is a 3 port memory, with 2 read ports and 1 write port.+ It has 32 locations, 8 bits each.
+ Separate read and write ports for the upper three 16 bit words are provided. The upper three 16 bit words are the pointer registers X (at byte address 27:26), Y (29:28) and Z (31:30).
+ The RF is placed at the beginning of the Unified Memory space.
+
+
+
+
+
++
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_hwres_iof_perif_pa_01.gif
===================================================================
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Index: pavr_hwres_iof_perif_pa_01.gif
===================================================================
--- pavr_hwres_iof_perif_pa_01.gif (nonexistent)
+++ pavr_hwres_iof_perif_pa_01.gif (revision 6)
pavr_hwres_iof_perif_pa_01.gif
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+application/octet-stream
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Index: main.html
===================================================================
--- main.html (nonexistent)
+++ main.html (revision 6)
@@ -0,0 +1,16 @@
+
+
+Main Page
+
+
+
+
+Main Page Modules Related Pages
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__hwres__dacu.html
===================================================================
--- group__pavr__hwres__dacu.html (nonexistent)
+++ group__pavr__hwres__dacu.html (revision 6)
@@ -0,0 +1,74 @@
+
+
+DACU
+
+
+
+
+Main Page Modules Related Pages
+
DACU
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_hwres_bpu_01.gif
===================================================================
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Index: pavr_hwres_bpu_01.gif
===================================================================
--- pavr_hwres_bpu_01.gif (nonexistent)
+++ pavr_hwres_bpu_01.gif (revision 6)
Pipelined AVR microcontroller Documentation
++
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__hwres__dacu.html
===================================================================
--- group__pavr__hwres__dacu.html (nonexistent)
+++ group__pavr__hwres__dacu.html (revision 6)
@@ -0,0 +1,74 @@
+
+
+DACU
+
+[Hardware resources]
+
- +Overview
-
+The Data Address Calculation Unit offers a unified read and write access over the concatenated RF, IOF and DM space, that is, over the Unified Memory (UM) space.
+ Loads and stores operate in the UM space. They use the DACU in order to translate the Unified Memory address into a RF, IOF or DM address.
+ The DACU takes requests to read or write into UM space, translates the UM address into RF, IOF or DM address, and transparently places requests to read or write the specific hardware resource (RF, IOF or DM) that corresponds to the given UM address.
+
- +Reading DACU
-
+
+++
+
+ DACU read requests:-
+
- pavr_s5_x_dacurd_rq
+ Needed by loads from address given by X pointer register. - pavr_s5_y_dacurd_rq
+ Needed by loads from address given by Y pointer register. - pavr_s5_z_dacurd_rq
+ Needed by loads from address given by Z pointer register. - pavr_s5_sp_dacurd_rq
+ Needed by POP instruction. - pavr_s5_k16_dacurd_rq
+ Needed by LDS instruction.
+ If the controller has more than 64KB of Data Memory, the Unified Memory address is built by concatenating the RAMPD with the 16 bit constant. - pavr_s5_pchi8_dacurd_rq
+ The higher 8 bits of the PC are loaded from the stack.
+ Needed by RET and RETI instructions. - pavr_s51_pcmid8_dacurd_rq
+ The middle 8 bits of the PC are loaded from the stack.
+ Needed by RET and RETI instructions. - pavr_s52_pclo8_dacurd_rq
+ The lower 8 bits of the PC are loaded from the stack.
+ Needed by RET and RETI instructions.
+ As a response to read requests, the DACU places read requests to RF, IOF or DM:-
+
- pavr_s5_dacu_rfrd1_rq
- pavr_s5_dacu_iof_rq
- pavr_s5_dacu_dmrd_rq
- pavr_s5_x_dacurd_rq
- +Writing DACU
-
+
+++
+
+ DACU write requests:-
+
- pavr_s5_x_dacuwr_rq
+ Needed by stores to address given by X pointer register. - pavr_s5_y_dacuwr_rq
+ Needed by stores to address given by Y pointer register. - pavr_s5_z_dacuwr_rq
+ Needed by stores to address given by Z pointer register. - pavr_s5_sp_dacuwr_rq
+ Needed by PUSH instruction.
+ - pavr_s5_k16_dacuwr_rq
+ Needed by STS instruction.
+ If the controller has more than 64KB of Data Memory, the Unified Memory address is built by concatenating the RAMPD with the 16 bit constant. - pavr_s5_pclo8_dacuwr_rq
+ The lower 8 bits of the PC are stored on the stack.
+ Needed by CALL family instructions (CALL, RCALL, ICALL, EICALL, implicit interrupt CALL). - pavr_s51_pcmid8_dacuwr_rq
+ The middle 8 bits of the PC are stored on the stack.
+ Needed by CALL family instructions. - pavr_s52_pchi8_dacuwr_rq
+ The higher 8 bits of the PC are stored on the stack.
+ Needed by CALL family instructions.
+ As a response to write requests, the DACU places write requests to RF, IOF or DM, and BPU:-
+
- pavr_s5_dacu_rfwr_rq
- pavr_s5_dacu_iof_rq
- pavr_s5_dacu_dmwr_rq
- pavr_s5_dacust_bpr0wr_rq
+ - pavr_s5_x_dacuwr_rq
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_hwres_bpu_01.gif
===================================================================
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Index: pavr_hwres_bpu_01.gif
===================================================================
--- pavr_hwres_bpu_01.gif (nonexistent)
+++ pavr_hwres_bpu_01.gif (revision 6)
pavr_hwres_bpu_01.gif
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: pavr_register_file.vhd
===================================================================
--- pavr_register_file.vhd (nonexistent)
+++ pavr_register_file.vhd (revision 6)
@@ -0,0 +1,315 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This defines pAVR's Register File.
+-- The Register File has 3 ports: 2 for reading and 1 for writing. All these
+-- access all 32 locations in the register file. Apart from these 3 ports,
+-- there are 3 special ports that access 16 bit pointer registers X, Y, Z, for
+-- both reading and writing. The pointer registers are mapped on the register
+-- file, at addresses 26-27 (pointer register X), 28-29 (Y) and 30-31 (Z).
+-- Physically, the register file consists of a memory-like entity with 26 8 bit
+-- locations, and 3 16 bit registers. Together, these form the 32 locations
+-- of the register file. The physical separation of locations <26 and >=26 is
+-- is invisible from outside.
+-- Writing on the write port and on every pointer register port can be done
+-- in parallel. However, if writing at the same time a location via the write
+-- port and one of the pointer registers, writing via pointer register port
+-- has priority.
+--
+
+
+
+--
+library work;
+use work.std_util.all;
+use work.pavr_util.all;
+use work.pavr_constants.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+
+entity pavr_rf is
+ port(
+ pavr_rf_clk: in std_logic;
+ pavr_rf_res: in std_logic;
+ pavr_rf_syncres: in std_logic;
+
+ -- Read port 1
+ pavr_rf_rd1_addr: in std_logic_vector(4 downto 0);
+ pavr_rf_rd1_rd: in std_logic;
+ pavr_rf_rd1_do: out std_logic_vector(7 downto 0);
+
+ -- Read port 2
+ pavr_rf_rd2_addr: in std_logic_vector(4 downto 0);
+ pavr_rf_rd2_rd: in std_logic;
+ pavr_rf_rd2_do: out std_logic_vector(7 downto 0);
+
+ -- Write port
+ pavr_rf_wr_addr: in std_logic_vector(4 downto 0);
+ pavr_rf_wr_wr: in std_logic;
+ pavr_rf_wr_di: in std_logic_vector(7 downto 0);
+
+ -- Pointer registers
+ pavr_rf_x: out std_logic_vector(15 downto 0);
+ pavr_rf_x_wr: in std_logic;
+ pavr_rf_x_di: in std_logic_vector(15 downto 0);
+
+ pavr_rf_y: out std_logic_vector(15 downto 0);
+ pavr_rf_y_wr: in std_logic;
+ pavr_rf_y_di: in std_logic_vector(15 downto 0);
+
+ pavr_rf_z: out std_logic_vector(15 downto 0);
+ pavr_rf_z_wr: in std_logic;
+ pavr_rf_z_di: in std_logic_vector(15 downto 0)
+ );
+end;
+
+
+
+architecture pavr_rf_arch of pavr_rf is
+
+ signal pavr_rf_x_int: std_logic_vector(15 downto 0);
+ signal pavr_rf_y_int: std_logic_vector(15 downto 0);
+ signal pavr_rf_z_int: std_logic_vector(15 downto 0);
+
+ type t_pavr_rf_data_array is array (0 to 25) of std_logic_vector(7 downto 0);
+ signal pavr_rf_data_array: t_pavr_rf_data_array;
+
+begin
+
+ -- Read port 1
+ process
+ variable is_x, is_y, is_z: std_logic;
+ variable tv: std_logic_vector(2 downto 0);
+ begin
+ tv := int_to_std_logic_vector(0, 3);
+
+ wait until ((pavr_rf_clk'event) and (pavr_rf_clk = '1'));
+
+ if (pavr_rf_rd1_addr(4 downto 1) = "1101") then
+ is_x := '1';
+ else
+ is_x := '0';
+ end if;
+
+ if (pavr_rf_rd1_addr(4 downto 1) = "1110") then
+ is_y := '1';
+ else
+ is_y := '0';
+ end if;
+
+ if (pavr_rf_rd1_addr(4 downto 1) = "1111") then
+ is_z := '1';
+ else
+ is_z := '0';
+ end if;
+
+ if (pavr_rf_rd1_rd = '1') then
+ tv := is_x & is_y & is_z;
+ case tv is
+ when "000" =>
+ pavr_rf_rd1_do <= pavr_rf_data_array(std_logic_vector_to_nat(pavr_rf_rd1_addr));
+ when "100" =>
+ if (pavr_rf_rd1_addr(0) = '0') then
+ pavr_rf_rd1_do <= pavr_rf_x_int(7 downto 0);
+ else
+ pavr_rf_rd1_do <= pavr_rf_x_int(15 downto 8);
+ end if;
+ when "010" =>
+ if (pavr_rf_rd1_addr(0) = '0') then
+ pavr_rf_rd1_do <= pavr_rf_y_int(7 downto 0);
+ else
+ pavr_rf_rd1_do <= pavr_rf_y_int(15 downto 8);
+ end if;
+ when others =>
+ if (pavr_rf_rd1_addr(0) = '0') then
+ pavr_rf_rd1_do <= pavr_rf_z_int(7 downto 0);
+ else
+ pavr_rf_rd1_do <= pavr_rf_z_int(15 downto 8);
+ end if;
+ end case;
+ end if;
+ end process;
+
+
+
+ -- Read port 2
+ process
+ variable is_x, is_y, is_z: std_logic;
+ variable tv: std_logic_vector(2 downto 0);
+ begin
+ tv := int_to_std_logic_vector(0, 3);
+
+ wait until ((pavr_rf_clk'event) and (pavr_rf_clk = '1'));
+
+ if (pavr_rf_rd2_addr(4 downto 1) = "1101") then
+ is_x := '1';
+ else
+ is_x := '0';
+ end if;
+
+ if (pavr_rf_rd2_addr(4 downto 1) = "1110") then
+ is_y := '1';
+ else
+ is_y := '0';
+ end if;
+
+ if (pavr_rf_rd2_addr(4 downto 1) = "1111") then
+ is_z := '1';
+ else
+ is_z := '0';
+ end if;
+
+ if (pavr_rf_rd2_rd = '1') then
+ tv := is_x & is_y & is_z;
+ case tv is
+ when "000" =>
+ pavr_rf_rd2_do <= pavr_rf_data_array(std_logic_vector_to_nat(pavr_rf_rd2_addr));
+ when "100" =>
+ if (pavr_rf_rd2_addr(0) = '0') then
+ pavr_rf_rd2_do <= pavr_rf_x_int(7 downto 0);
+ else
+ pavr_rf_rd2_do <= pavr_rf_x_int(15 downto 8);
+ end if;
+ when "010" =>
+ if (pavr_rf_rd2_addr(0) = '0') then
+ pavr_rf_rd2_do <= pavr_rf_y_int(7 downto 0);
+ else
+ pavr_rf_rd2_do <= pavr_rf_y_int(15 downto 8);
+ end if;
+ when others =>
+ if (pavr_rf_rd2_addr(0) = '0') then
+ pavr_rf_rd2_do <= pavr_rf_z_int(7 downto 0);
+ else
+ pavr_rf_rd2_do <= pavr_rf_z_int(15 downto 8);
+ end if;
+ end case;
+ end if;
+ end process;
+
+
+
+ -- Write port and pointer registers
+ process(pavr_rf_clk, pavr_rf_res, pavr_rf_syncres,
+ pavr_rf_wr_addr, pavr_rf_wr_wr, pavr_rf_wr_di, pavr_rf_x_wr, pavr_rf_y_wr, pavr_rf_z_wr,
+ pavr_rf_x_di, pavr_rf_y_di, pavr_rf_z_di)
+ variable is_x, is_y, is_z: std_logic;
+ variable tv: std_logic_vector(2 downto 0);
+ begin
+ tv := int_to_std_logic_vector(0, 3);
+
+ if (pavr_rf_wr_addr(4 downto 1) = "1101") then
+ is_x := '1';
+ else
+ is_x := '0';
+ end if;
+
+ if (pavr_rf_wr_addr(4 downto 1) = "1110") then
+ is_y := '1';
+ else
+ is_y := '0';
+ end if;
+
+ if (pavr_rf_wr_addr(4 downto 1) = "1111") then
+ is_z := '1';
+ else
+ is_z := '0';
+ end if;
+
+ if (pavr_rf_res = '1') then
+ -- Asynchronous reset
+ pavr_rf_x_int <= int_to_std_logic_vector(0, 16);
+ pavr_rf_y_int <= int_to_std_logic_vector(0, 16);
+ pavr_rf_z_int <= int_to_std_logic_vector(0, 16);
+ elsif ((pavr_rf_clk'event) and (pavr_rf_clk = '1')) then
+
+ -- Write port
+ if (pavr_rf_wr_wr = '1') then
+ tv := is_x & is_y & is_z;
+ case tv is
+ when "000" =>
+ pavr_rf_data_array(std_logic_vector_to_nat(pavr_rf_wr_addr)) <= pavr_rf_wr_di;
+ when "100" =>
+ if (pavr_rf_wr_addr(0) = '0') then
+ pavr_rf_x_int(7 downto 0) <= pavr_rf_wr_di;
+ else
+ pavr_rf_x_int(15 downto 8) <= pavr_rf_wr_di;
+ end if;
+ when "010" =>
+ if (pavr_rf_wr_addr(0) = '0') then
+ pavr_rf_y_int(7 downto 0) <= pavr_rf_wr_di;
+ else
+ pavr_rf_y_int(15 downto 8) <= pavr_rf_wr_di;
+ end if;
+ when others =>
+ if (pavr_rf_wr_addr(0) = '0') then
+ pavr_rf_z_int(7 downto 0) <= pavr_rf_wr_di;
+ else
+ pavr_rf_z_int(15 downto 8) <= pavr_rf_wr_di;
+ end if;
+ end case;
+ end if;
+
+ -- Write pointer registers. Possibly overwrite the above write.
+ if (pavr_rf_x_wr = '1') then
+ pavr_rf_x_int <= pavr_rf_x_di;
+ end if;
+ if (pavr_rf_y_wr = '1') then
+ pavr_rf_y_int <= pavr_rf_y_di;
+ end if;
+ if (pavr_rf_z_wr = '1') then
+ pavr_rf_z_int <= pavr_rf_z_di;
+ end if;
+
+ if (pavr_rf_syncres = '1') then
+ -- Synchronous reset
+ pavr_rf_x_int <= int_to_std_logic_vector(0, 16);
+ pavr_rf_y_int <= int_to_std_logic_vector(0, 16);
+ pavr_rf_z_int <= int_to_std_logic_vector(0, 16);
+ end if;
+ end if;
+ end process;
+
+
+
+ -- Zero-level assignments
+ pavr_rf_x <= pavr_rf_x_int;
+ pavr_rf_y <= pavr_rf_y_int;
+ pavr_rf_z <= pavr_rf_z_int;
+
+end;
+--
Index: group__pavr__pipeline__others.html
===================================================================
--- group__pavr__pipeline__others.html (nonexistent)
+++ group__pavr__pipeline__others.html (revision 6)
@@ -0,0 +1,27 @@
+
+
+Others
+
+
+
+
+Main Page Modules Related Pages
+
Others
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_hwres_int_01.gif
===================================================================
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svn:mime-type = application/octet-stream
Index: pavr_hwres_int_01.gif
===================================================================
--- pavr_hwres_int_01.gif (nonexistent)
+++ pavr_hwres_int_01.gif (revision 6)
Others
+
+[Pipeline details]
+
- +LPM/ELPM state machine
-
+This is how the LPM/ELPM state machine plugs into the pipeline:
+
+++
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_hwres_int_01.gif
===================================================================
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Index: pavr_hwres_int_01.gif
===================================================================
--- pavr_hwres_int_01.gif (nonexistent)
+++ pavr_hwres_int_01.gif (revision 6)
pavr_hwres_int_01.gif
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+application/octet-stream
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Index: doxygen.png
===================================================================
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Index: doxygen.png
===================================================================
--- doxygen.png (nonexistent)
+++ doxygen.png (revision 6)
doxygen.png
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+application/octet-stream
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Index: pavr_pipe_skips_01.gif
===================================================================
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Index: pavr_pipe_skips_01.gif
===================================================================
--- pavr_pipe_skips_01.gif (nonexistent)
+++ pavr_pipe_skips_01.gif (revision 6)
pavr_pipe_skips_01.gif
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Index: group__pavr__hwres__iof__spwr.html
===================================================================
--- group__pavr__hwres__iof__spwr.html (nonexistent)
+++ group__pavr__hwres__iof__spwr.html (revision 6)
@@ -0,0 +1,49 @@
+
+
+SP port
+
+
+
+
+Main Page Modules Related Pages
+
SP port
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__hwres__iof__perif__int0.html
===================================================================
--- group__pavr__hwres__iof__perif__int0.html (nonexistent)
+++ group__pavr__hwres__iof__perif__int0.html (revision 6)
@@ -0,0 +1,41 @@
+
+
+External interrupt 0
+
+
+
+
+Main Page Modules Related Pages
+
External interrupt 0
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_hwres_bpr0_01.gif
===================================================================
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Index: pavr_hwres_bpr0_01.gif
===================================================================
--- pavr_hwres_bpr0_01.gif (nonexistent)
+++ pavr_hwres_bpr0_01.gif (revision 6)
SP port
+
+[IO File]
+
- +SP port connectivity
-
+
+++
+
+ This the stack pointer.
+ It is 16 bits wide, being composed of two 8 bit registers, SPL and SPH.
+ The stack can reside anywhere in the Unified Memory space. That is, anywhere in the RF, IOF or DM. It can even begin, for example, in RF and continue in IOF. However, placing the stack pointer in the IOF is likely to be a programming error, as the IOF registers have dedicated functions. Quasi-random values from stack written into IOF could result, for example, in an unpredictably trigerring any interrupt, and in general, in unpredictable behavior of the controller.
+
- +Requests to this port
-
+
-
+
- pavr_s5_inc_spwr_rq
+ Increment SP (SPH & SPL) with 1.
+ Needed by POP. - pavr_s5_dec_spwr_rq
+ Increment SP with 1.
+ Needed by PUSH. - pavr_s5_calldec_spwr_rq
+ Decrement SP with 1.
+ Needed by RCALL, ICALL, EICALL, CALL, interrupt implicit CALL. - pavr_s51_calldec_spwr_rq
+ Decrement SP with 1.
+ Needed by RCALL, ICALL, EICALL, CALL, interrupt implicit CALL. - pavr_s52_calldec_spwr_rq
+ Decrement SP with 1.
+ Needed by RCALL, ICALL, EICALL, CALL, interrupt implicit CALL. - pavr_s5_retinc2_spwr_rq
+ Increment SP with 2.
+ Needed by RET, RETI. - pavr_s51_retinc_spwr_rq
+ Increment SP with 1.
+ Needed by RET, RETI.
+
+
- pavr_s5_inc_spwr_rq
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__hwres__iof__perif__int0.html
===================================================================
--- group__pavr__hwres__iof__perif__int0.html (nonexistent)
+++ group__pavr__hwres__iof__perif__int0.html (revision 6)
@@ -0,0 +1,41 @@
+
+
+External interrupt 0
+
+[Peripherals]
+
- +Features
-
+External interrupt 0 is physically mapped on the line 0 (bit 0) of port A.
+
+ Its associated interrupt flag resides into the IO File register GIFR (General Interrupt Flags Register):
+
+++
+
+ External interrupt 0 is enabled/disabled by setting/clearing bit 6 in GIMSK (General Interrupt Mask) register:
+
+++
+
+ If enabled, it can trigger an interrupt on high-to-low transition, low-to-high transition, or on a low level of the interrupt 0 input. This behavior is defined by 2 bits in the MCUCR (Microcontroller Control) register:
+
+++
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_hwres_bpr0_01.gif
===================================================================
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Index: pavr_hwres_bpr0_01.gif
===================================================================
--- pavr_hwres_bpr0_01.gif (nonexistent)
+++ pavr_hwres_bpr0_01.gif (revision 6)
pavr_hwres_bpr0_01.gif
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: test_pavr_io_file.vhd
===================================================================
--- test_pavr_io_file.vhd (nonexistent)
+++ test_pavr_io_file.vhd (revision 6)
@@ -0,0 +1,599 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This tests pAVR's IO File.
+-- The following tests are performed on the IOF:
+-- - test the IOF general write/read/bit processing port.
+-- Test all opcodes that this port is capable of:
+-- - wrbyte
+-- - rdbyte
+-- - clrbit
+-- - setbit
+-- - stbit
+-- - ldbit
+-- - test the IOF port A.
+-- Port A is intended to offer to pAVR pin-level IO connectivity with the
+-- outside world.
+-- Test that Port A pins correctly take the appropriate logic values
+-- (high, low, high Z or weak high).
+-- - test Timer 0.
+-- - test Timer 0 prescaler.
+-- - test Timer 0 overflow.
+-- - test Timer 0 interrupt.
+-- - test External Interrupt 0.
+-- External Interrupt 0 is mapped on port A pin 0.
+-- Test if each possible configuration (activation on low level, rising edge
+-- or falling edge) correctly triggers External Interrupt 0.
+--
+
+
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+library work;
+use work.std_util.all;
+use work.pavr_util.all;
+use work.pavr_constants.all;
+
+
+
+entity test_pavr_iof is
+end;
+
+
+
+architecture test_pavr_iof_arch of test_pavr_iof is
+ signal clk, res, syncres: std_logic;
+
+ -- Clock counter
+ signal cnt: std_logic_vector(20 downto 0);
+
+ -- IOF general read and write port
+ signal pavr_iof_opcode : std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
+ signal pavr_iof_addr : std_logic_vector(5 downto 0);
+ signal pavr_iof_di : std_logic_vector(7 downto 0);
+ signal pavr_iof_do : std_logic_vector(7 downto 0);
+ signal pavr_iof_bitaddr : std_logic_vector(2 downto 0);
+ signal pavr_iof_bitout : std_logic;
+
+ -- SREG port
+ signal pavr_iof_sreg : std_logic_vector(7 downto 0);
+ signal pavr_iof_sreg_wr : std_logic;
+ signal pavr_iof_sreg_di : std_logic_vector(7 downto 0);
+
+ -- SP port
+ signal pavr_iof_spl : std_logic_vector(7 downto 0);
+ signal pavr_iof_spl_wr : std_logic;
+ signal pavr_iof_spl_di : std_logic_vector(7 downto 0);
+
+ signal pavr_iof_sph : std_logic_vector(7 downto 0);
+ signal pavr_iof_sph_wr : std_logic;
+ signal pavr_iof_sph_di : std_logic_vector(7 downto 0);
+
+ -- RAMPX port
+ signal pavr_iof_rampx : std_logic_vector(7 downto 0);
+ signal pavr_iof_rampx_wr : std_logic;
+ signal pavr_iof_rampx_di : std_logic_vector(7 downto 0);
+
+ -- RAMPY port
+ signal pavr_iof_rampy : std_logic_vector(7 downto 0);
+ signal pavr_iof_rampy_wr : std_logic;
+ signal pavr_iof_rampy_di : std_logic_vector(7 downto 0);
+
+ -- RAMPZ port
+ signal pavr_iof_rampz : std_logic_vector(7 downto 0);
+ signal pavr_iof_rampz_wr : std_logic;
+ signal pavr_iof_rampz_di : std_logic_vector(7 downto 0);
+
+ -- RAMPD port
+ signal pavr_iof_rampd : std_logic_vector(7 downto 0);
+ signal pavr_iof_rampd_wr : std_logic;
+ signal pavr_iof_rampd_di : std_logic_vector(7 downto 0);
+
+ -- EIND port
+ signal pavr_iof_eind : std_logic_vector(7 downto 0);
+ signal pavr_iof_eind_wr : std_logic;
+ signal pavr_iof_eind_di : std_logic_vector(7 downto 0);
+
+ -- Port A
+ signal pavr_iof_pa : std_logic_vector(7 downto 0);
+
+ -- Interrupt-related interface signals to control module (to the pipeline).
+ signal pavr_disable_int : std_logic;
+ signal pavr_int_rq : std_logic;
+ signal pavr_int_vec : std_logic_vector(21 downto 0);
+
+ -- Declare the IO File.
+ component pavr_iof
+ port(
+ pavr_iof_clk : in std_logic;
+ pavr_iof_res : in std_logic;
+ pavr_iof_syncres : in std_logic;
+
+ -- General IO file port
+ pavr_iof_opcode : in std_logic_vector(pavr_iof_opcode_w - 1 downto 0);
+ pavr_iof_addr : in std_logic_vector(5 downto 0);
+ pavr_iof_di : in std_logic_vector(7 downto 0);
+ pavr_iof_do : out std_logic_vector(7 downto 0);
+ pavr_iof_bitout : out std_logic;
+ pavr_iof_bitaddr : in std_logic_vector(2 downto 0);
+
+ -- AVR kernel register ports
+ -- Status register (SREG)
+ pavr_iof_sreg : out std_logic_vector(7 downto 0);
+ pavr_iof_sreg_wr : in std_logic;
+ pavr_iof_sreg_di : in std_logic_vector(7 downto 0);
+
+ -- Stack pointer (SP = SPH&SPL)
+ pavr_iof_sph : out std_logic_vector(7 downto 0);
+ pavr_iof_sph_wr : in std_logic;
+ pavr_iof_sph_di : in std_logic_vector(7 downto 0);
+ pavr_iof_spl : out std_logic_vector(7 downto 0);
+ pavr_iof_spl_wr : in std_logic;
+ pavr_iof_spl_di : in std_logic_vector(7 downto 0);
+
+ -- Pointer registers extensions (RAMPX, RAMPY, RAMPZ)
+ pavr_iof_rampx : out std_logic_vector(7 downto 0);
+ pavr_iof_rampx_wr : in std_logic;
+ pavr_iof_rampx_di : in std_logic_vector(7 downto 0);
+
+ pavr_iof_rampy : out std_logic_vector(7 downto 0);
+ pavr_iof_rampy_wr : in std_logic;
+ pavr_iof_rampy_di : in std_logic_vector(7 downto 0);
+
+ pavr_iof_rampz : out std_logic_vector(7 downto 0);
+ pavr_iof_rampz_wr : in std_logic;
+ pavr_iof_rampz_di : in std_logic_vector(7 downto 0);
+
+ -- Data Memory extension address register (RAMPD)
+ pavr_iof_rampd : out std_logic_vector(7 downto 0);
+ pavr_iof_rampd_wr : in std_logic;
+ pavr_iof_rampd_di : in std_logic_vector(7 downto 0);
+
+ -- Program Memory extension address register (EIND)
+ pavr_iof_eind : out std_logic_vector(7 downto 0);
+ pavr_iof_eind_wr : in std_logic;
+ pavr_iof_eind_di : in std_logic_vector(7 downto 0);
+
+ -- AVR non-kernel (feature) register ports
+ -- Port A
+ pavr_iof_pa : inout std_logic_vector(7 downto 0);
+
+ -- Interrupt-related interface signals to control module (to the pipeline).
+ pavr_disable_int : in std_logic;
+ pavr_int_rq : out std_logic;
+ pavr_int_vec : out std_logic_vector(21 downto 0)
+ );
+ end component;
+ for all: pavr_iof use entity work.pavr_iof(pavr_iof_arch);
+
+begin
+
+ -- Instantiate the IO File.
+ pavr_iof_instance1: pavr_iof
+ port map(
+ clk,
+ res,
+ syncres,
+
+ -- General IO file port
+ pavr_iof_opcode,
+ pavr_iof_addr,
+ pavr_iof_di,
+ pavr_iof_do,
+ pavr_iof_bitout,
+ pavr_iof_bitaddr,
+
+ -- AVR kernel register ports
+ -- Status register (SREG)
+ pavr_iof_sreg,
+ pavr_iof_sreg_wr,
+ pavr_iof_sreg_di,
+
+ -- Stack pointer (SP = SPH&SPL)
+ pavr_iof_sph,
+ pavr_iof_sph_wr,
+ pavr_iof_sph_di,
+ pavr_iof_spl,
+ pavr_iof_spl_wr,
+ pavr_iof_spl_di,
+
+ -- Pointer registers extensions (RAMPX, RAMPY, RAMPZ)
+ pavr_iof_rampx,
+ pavr_iof_rampx_wr,
+ pavr_iof_rampx_di,
+
+ pavr_iof_rampy,
+ pavr_iof_rampy_wr,
+ pavr_iof_rampy_di,
+
+ pavr_iof_rampz,
+ pavr_iof_rampz_wr,
+ pavr_iof_rampz_di,
+
+ -- Data Memory extension address register (RAMPD)
+ pavr_iof_rampd,
+ pavr_iof_rampd_wr,
+ pavr_iof_rampd_di,
+
+ -- Program Memory extension address register (EIND)
+ pavr_iof_eind,
+ pavr_iof_eind_wr,
+ pavr_iof_eind_di,
+
+ -- AVR non-kernel (feature) register ports
+ -- Port A
+ pavr_iof_pa,
+
+ -- Interrupt-related interface signals to control module (to the pipeline).
+ pavr_disable_int,
+ pavr_int_rq,
+ pavr_int_vec
+ );
+
+
+ generate_clock:
+ process
+ begin
+ clk <= '1';
+ wait for 50 ns;
+ clk <= '0';
+ wait for 50 ns;
+ end process generate_clock;
+
+
+ generate_reset:
+ process
+ begin
+ res <= '0';
+ wait for 100 ns;
+ res <= '1';
+ wait for 110 ns;
+ res <= '0';
+ wait for 1 ms;
+ end process generate_reset;
+
+
+ generate_sync_reset:
+ process
+ begin
+ syncres <= '0';
+ wait for 300 ns;
+ syncres <= '1';
+ wait for 110 ns;
+ syncres <= '0';
+ wait for 1 ms;
+ end process generate_sync_reset;
+
+
+ test_main:
+ process(clk, res, syncres,
+ cnt,
+ pavr_iof_opcode, pavr_iof_addr, pavr_iof_di, pavr_iof_bitaddr,
+ pavr_iof_sreg_di,
+ pavr_iof_spl_di,
+ pavr_iof_sph_di,
+ pavr_iof_rampx_di,
+ pavr_iof_rampy_di,
+ pavr_iof_rampz_di,
+ pavr_iof_rampd_di,
+ pavr_iof_eind_di,
+
+ pavr_iof_rampy
+ )
+ begin
+ if res='1' then
+ -- Async reset
+ -- The IO File should take care of reseting its registers. Check this.
+ cnt <= int_to_std_logic_vector(0, cnt'length);
+ elsif clk'event and clk='1' then
+ -- Clock counter
+ cnt <= cnt+1;
+
+ -- Initialize inputs.
+ pavr_iof_opcode <= int_to_std_logic_vector(0, pavr_iof_opcode'length);
+ pavr_iof_addr <= int_to_std_logic_vector(0, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(0, pavr_iof_di'length);
+ pavr_iof_bitaddr <= int_to_std_logic_vector(0, pavr_iof_bitaddr'length);
+
+ pavr_iof_sreg_wr <= '0';
+ pavr_iof_sreg_di <= int_to_std_logic_vector(0, pavr_iof_sreg_di'length);
+
+ pavr_iof_spl_wr <= '0';
+ pavr_iof_spl_di <= int_to_std_logic_vector(0, pavr_iof_spl_di'length);
+
+ pavr_iof_sph_wr <= '0';
+ pavr_iof_sph_di <= int_to_std_logic_vector(0, pavr_iof_sph_di'length);
+
+ pavr_iof_rampx_wr <= '0';
+ pavr_iof_rampx_di <= int_to_std_logic_vector(0, pavr_iof_rampx_di'length);
+
+ pavr_iof_rampy_wr <= '0';
+ pavr_iof_rampy_di <= int_to_std_logic_vector(0, pavr_iof_rampy_di'length);
+
+ pavr_iof_rampz_wr <= '0';
+ pavr_iof_rampz_di <= int_to_std_logic_vector(0, pavr_iof_rampz_di'length);
+
+ pavr_iof_rampd_wr <= '0';
+ pavr_iof_rampd_di <= int_to_std_logic_vector(0, pavr_iof_rampd_di'length);
+
+ pavr_iof_eind_wr <= '0';
+ pavr_iof_eind_di <= int_to_std_logic_vector(0, pavr_iof_eind_di'length);
+
+ pavr_disable_int <= '0';
+
+ case std_logic_vector_to_nat(cnt) is
+ -- TEST 1. Test IO general port.
+ -- IOF opcode = wrbyte. Write RAMPY.
+ when 3 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_rampy_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#C5#, pavr_iof_di'length);
+ -- IOF opcode = rdbyte. Read RAMPY.
+ when 4 =>
+ pavr_iof_opcode <= pavr_iof_opcode_rdbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_rampy_addr, pavr_iof_addr'length);
+ -- IOF opcode = clrbit. Clear bit 2 of RAMPY.
+ when 5 =>
+ pavr_iof_opcode <= pavr_iof_opcode_clrbit;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_rampy_addr, pavr_iof_addr'length);
+ pavr_iof_di <= pavr_iof_rampy;
+ pavr_iof_bitaddr <= int_to_std_logic_vector(2, pavr_iof_bitaddr'length);
+ -- IOF opcode = setbit. Set bit 3 of RAMPY.
+ when 6 =>
+ pavr_iof_opcode <= pavr_iof_opcode_setbit;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_rampy_addr, pavr_iof_addr'length);
+ pavr_iof_di <= pavr_iof_rampy;
+ pavr_iof_bitaddr <= int_to_std_logic_vector(3, pavr_iof_bitaddr'length);
+ -- IOF opcode = stbit. Store bit 4 of input into T flag.
+ when 7 =>
+ pavr_iof_opcode <= pavr_iof_opcode_stbit;
+ pavr_iof_di <= int_to_std_logic_vector(16#93#, pavr_iof_di'length);
+ pavr_iof_bitaddr <= int_to_std_logic_vector(4, pavr_iof_bitaddr'length);
+ -- IOF opcode = ldbit. Load T flag into bit 5 of output.
+ when 8 =>
+ pavr_iof_opcode <= pavr_iof_opcode_ldbit;
+ pavr_iof_di <= int_to_std_logic_vector(16#93#, pavr_iof_di'length);
+ pavr_iof_bitaddr <= int_to_std_logic_vector(5, pavr_iof_bitaddr'length);
+
+
+ -- TEST 2. Write some of the IOF registers that have dedicated write
+ -- ports.
+ when 9 =>
+ pavr_iof_sph_wr <= '1';
+ pavr_iof_sph_di <= int_to_std_logic_vector(16#5E#, 8);
+ pavr_iof_eind_wr <= '1';
+ pavr_iof_eind_di <= int_to_std_logic_vector(16#A2#, 8);
+
+
+ -- TEST 3. Test Port A.
+ -- The idea is:
+ -- - 1. set some bits in PORTA
+ -- - 2. set some bits in DDRA
+ -- Now check the output pins PA to see which is Hi Z input, weakly
+ -- pulled hi input, or output low/hi.
+ -- - 3. read PINA and see if IOF data out gets all those HiZ/H/0/1
+ -- lines.
+ -- Write PORTA.
+ when 20 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_porta_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#0F#, pavr_iof_di'length);
+ -- Set port pins into Hi Z (nobody sources or sink into/from them
+ -- from outside). Note that a 3 state latch is generated.
+ pavr_iof_pa <= "ZZZZZZZZ";
+ -- Write DDRA.
+ when 21 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_ddra_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#33#, pavr_iof_di'length);
+ -- Read PINA.
+ when 22 =>
+ pavr_iof_opcode <= pavr_iof_opcode_rdbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_pina_addr, pavr_iof_addr'length);
+ -- Now clear the Port A mess for next tests (remember that PA also has
+ -- alternate functions: int 0 and timer 0, that will be tested
+ -- below). Thus, set PA as Hi Z input (DDRA=0 and PORTA=0).
+ when 23 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_ddra_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#00#, pavr_iof_di'length);
+ pavr_iof_pa <= "ZZZZZZZZ";
+ when 24 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_porta_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#00#, pavr_iof_di'length);
+
+
+ -- TEST 4. Test timer 0 prescaler options.
+ -- Timer 0 clock = main clock.
+ when 30 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_tccr0_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#01#, pavr_iof_di'length);
+ -- Timer 0 clock = main clock / 8.
+ when 40 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_tccr0_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#02#, pavr_iof_di'length);
+ -- Timer 0 clock = main clock / 64.
+ when 100 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_tccr0_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#03#, pavr_iof_di'length);
+ -- Timer 0 clock = main clock / 256.
+ when 250 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_tccr0_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#04#, pavr_iof_di'length);
+ -- Timer 0 clock = main clock / 1024.
+ when 1000 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_tccr0_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#05#, pavr_iof_di'length);
+ -- Timer 0 clock = dedicated external input PINA(1), negative edge.
+ when 5000 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_tccr0_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#06#, pavr_iof_di'length);
+ pavr_iof_pa(1) <= '0';
+ when 5001 | 5002 =>
+ pavr_iof_pa(1) <= '0';
+ when 5003 | 5004 =>
+ pavr_iof_pa(1) <= '1';
+ when 5005 | 5006 | 5007 =>
+ pavr_iof_pa(1) <= '0';
+ when 5008 | 5009 =>
+ pavr_iof_pa(1) <= '1';
+ when 5010 | 5011 | 5012 =>
+ pavr_iof_pa(1) <= '0';
+ when 5013 | 5014 | 5015 | 5016 | 5017 | 5018 | 5019 =>
+ pavr_iof_pa(1) <= '1';
+ when 5020 =>
+ pavr_iof_pa(1) <= '0';
+ -- Timer 0 clock = dedicated external input PINA(1), positive edge.
+ when 5030 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_tccr0_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#07#, pavr_iof_di'length);
+ when 5031 | 5032 =>
+ pavr_iof_pa(1) <= '0';
+ when 5033 | 5034 =>
+ pavr_iof_pa(1) <= '1';
+ when 5035 | 5036 | 5037 =>
+ pavr_iof_pa(1) <= '0';
+ when 5038 | 5039 =>
+ pavr_iof_pa(1) <= '1';
+ when 5040 | 5041 | 5042 =>
+ pavr_iof_pa(1) <= '0';
+ when 5043 | 5044 | 5045 | 5046 | 5047 | 5048 | 5049 =>
+ pavr_iof_pa(1) <= '1';
+ when 5050 =>
+ pavr_iof_pa(1) <= '0';
+
+
+ -- TEST 5. Test timer 0 overflow.
+ -- Check if timer 0 overflows and if the overflow event is captured in
+ -- TIFR(1). Set timer 0 clock to main clock, to count faster.
+ when 5100 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_tccr0_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#01#, pavr_iof_di'length);
+
+
+ -- TEST 6. Test timer 0 overflow interrupt.
+ -- Enable interrupts globally, by setting set SREG(7).
+ when 5500 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_sreg_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#80#, pavr_iof_di'length);
+ -- Enable timer 0 overflow interrupt, by setting TIMSK(1).
+ when 5501 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_timsk_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#02#, pavr_iof_di'length);
+ -- Set timer 0 clock to system clock (highest speed).
+ when 5502 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_tccr0_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#01#, pavr_iof_di'length);
+ -- Disable timer 0 overflow interrupt, to keep the timer 0 `quiet'
+ -- during next tests.
+ when 5503 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_timsk_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#00#, pavr_iof_di'length);
+
+
+ -- TEST 7. Test external interrupt 0.
+ -- Enable external interrupt 0.
+ when 5799 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_gimsk_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#40#, pavr_iof_di'length);
+ pavr_iof_pa(0) <= '1';
+ -- Check if external interrupt 0 event is captured in GIFR(6).
+ -- External interrupt 0 triggers on low PA(0).
+ when 5800 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_mcucr_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#00#, pavr_iof_di'length);
+ pavr_iof_pa(0) <= '1';
+ when 5801 =>
+ pavr_iof_pa(0) <= '0';
+ -- External interrupt 0 triggers on negative edge of PA(0).
+ when 5802 | 5803 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_mcucr_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#02#, pavr_iof_di'length);
+ pavr_iof_pa(0) <= '0';
+ when 5804 | 5805 =>
+ pavr_iof_pa(0) <= '1';
+ when 5806 | 5807 =>
+ pavr_iof_pa(0) <= '0';
+ when 5808 | 5809 | 5810 | 5811 =>
+ pavr_iof_pa(0) <= '1';
+ -- External interrupt 0 triggers on positive edge of PA(0).
+ when 5812 | 5813 =>
+ pavr_iof_opcode <= pavr_iof_opcode_wrbyte;
+ pavr_iof_addr <= int_to_std_logic_vector(pavr_mcucr_addr, pavr_iof_addr'length);
+ pavr_iof_di <= int_to_std_logic_vector(16#03#, pavr_iof_di'length);
+ pavr_iof_pa(0) <= '0';
+ when 5814 | 5815 =>
+ pavr_iof_pa(0) <= '1';
+ when 5816 | 5817 =>
+ pavr_iof_pa(0) <= '0';
+ when 5818 | 5819 =>
+ pavr_iof_pa(0) <= '1';
+
+
+ -- That's all about testing IO File.
+ when others =>
+ null;
+ end case;
+
+ if syncres='1' then
+ -- Sync reset
+ -- The IO File should take care of reseting its registers. Check this.
+ cnt <= int_to_std_logic_vector(0, cnt'length);
+ end if;
+ end if;
+ end process test_main;
+
+
+end;
+--
Index: ftv2vertline.png
===================================================================
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Index: ftv2vertline.png
===================================================================
--- ftv2vertline.png (nonexistent)
+++ ftv2vertline.png (revision 6)
ftv2vertline.png
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: ftv2plastnode.png
===================================================================
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Index: ftv2plastnode.png
===================================================================
--- ftv2plastnode.png (nonexistent)
+++ ftv2plastnode.png (revision 6)
ftv2plastnode.png
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: group__pavr__hwres__bpr0.html
===================================================================
--- group__pavr__hwres__bpr0.html (nonexistent)
+++ group__pavr__hwres__bpr0.html (revision 6)
@@ -0,0 +1,37 @@
+
+
+Bypass chain 0
+
+
+
+
+Main Page Modules Related Pages
+
Bypass chain 0
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__hwres__rf__xwr.html
===================================================================
--- group__pavr__hwres__rf__xwr.html (nonexistent)
+++ group__pavr__hwres__rf__xwr.html (revision 6)
@@ -0,0 +1,41 @@
+
+
+X port
+
+
+
+
+Main Page Modules Related Pages
+
X port
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: test_pavr_pm.vhd
===================================================================
--- test_pavr_pm.vhd (nonexistent)
+++ test_pavr_pm.vhd (revision 6)
@@ -0,0 +1,81 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This defines the Program Memory needed by pAVR control-section tests.
+-- The Program Memory is a trivial, single port, read-write RAM.
+-- This is just a testing utility, NOT actually a test.
+--
+
+
+
+--
+library work;
+use work.std_util.all;
+use work.pavr_util.all;
+use work.pavr_constants.all;
+use work.test_pavr_constants.all;
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+
+entity pavr_pm is
+ port(
+ pavr_pm_clk: in std_logic;
+ pavr_pm_wr: in std_logic;
+ pavr_pm_addr: in std_logic_vector(21 downto 0);
+ pavr_pm_di: in std_logic_vector(15 downto 0);
+ pavr_pm_do: out std_logic_vector(15 downto 0)
+ );
+end;
+
+
+
+architecture pavr_pm_arch of pavr_pm is
+ type tdata_array is array (0 to pavr_pm_len - 1) of std_logic_vector(15 downto 0);
+ signal data_array: tdata_array;
+begin
+ process
+ begin
+ wait until pavr_pm_clk'event and pavr_pm_clk='1';
+ if pavr_pm_wr='0' then
+ pavr_pm_do <= data_array(std_logic_vector_to_nat(pavr_pm_addr));
+ else
+ data_array(std_logic_vector_to_int(pavr_pm_addr)) <= pavr_pm_di;
+ end if;
+ end process;
+end;
+--
Index: test_pavr_constants.vhd
===================================================================
--- test_pavr_constants.vhd (nonexistent)
+++ test_pavr_constants.vhd (revision 6)
@@ -0,0 +1,63 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This file defines the constants needed by pAVR test architectures but NOT by the
+-- pAVR architectures.
+-- This is just a testing utility, NOT actually a test.
+--
+
+
+
+--
+library work;
+use work.std_util.all;
+use work.pavr_util.all;
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+
+package test_pavr_constants is
+
+ -- Program Memory length
+ constant pavr_pm_len : natural := 4096;
+
+ -- Program Memory belongs to pAVR or to the test architecture?
+ constant pm_sel_pavr: std_logic := '0';
+ constant pm_sel_usr: std_logic := '1';
+
+end;
+--
Index: pavr_hwres_iof_sp_01.gif
===================================================================
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svn:mime-type = application/octet-stream
Index: pavr_hwres_iof_sp_01.gif
===================================================================
--- pavr_hwres_iof_sp_01.gif (nonexistent)
+++ pavr_hwres_iof_sp_01.gif (revision 6)
Bypass chain 0
+
+[Bypass Unit]
+
- +Bypass chain 0 (BPR0) write port connectivity
-
+
+++
+
+
- +Requests to BPR0 write port
-
+
-
+
- pavr_s5_alu_bpr0wr_rq
+ Need by regular ALU instructions.
+ - pavr_s6_iof_bpr0wr_rq
+ Needed by instructions that read the IO File (IN, BLD). - pavr_s6_daculd_bpr0wr_rq
+ Needed by loads. - pavr_s5_dacust_bpr0wr_rq
+ Needed by stores. - pavr_s6_pmdo_bpr0wr_rq
+ Needed by LPM family instructions.
+
- pavr_s5_alu_bpr0wr_rq
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__hwres__rf__xwr.html
===================================================================
--- group__pavr__hwres__rf__xwr.html (nonexistent)
+++ group__pavr__hwres__rf__xwr.html (revision 6)
@@ -0,0 +1,41 @@
+
+
+X port
+
+[Register File]
+
- +X port connectivity
-
+
+++
+
+ This is a read and write port.
+ The contents of the X register is permanently available for reading, under the name `pavr_rf_x'.
+ The X write port consists of a data in (pavr_rf_x_di) and a write strobe (pavr_rf_x_wr).
- +Requests to X write port
-
+
-
+
- pavr_s5_ldstincrampx_xwr_rq
+ Increment X.
+ If the controller has more than 64KB memory, than increment RAMPX:X (24 bits) rather than X (16 bits).
+ Needed by loads and stores with postincrement.
+ - pavr_s5_ldstdecrampx_xwr_rq
+ Decrement X.
+ If more than 64KB memory, than decrement RAMPX:X rather than X.
+ Needed by loads and stores with predecrement.
+
+
- pavr_s5_ldstincrampx_xwr_rq
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: test_pavr_pm.vhd
===================================================================
--- test_pavr_pm.vhd (nonexistent)
+++ test_pavr_pm.vhd (revision 6)
@@ -0,0 +1,81 @@
+--
pavr_hwres_iof_sp_01.gif
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: pavr_hwres_rf_wr_01.gif
===================================================================
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svn:mime-type = application/octet-stream
Index: pavr_hwres_rf_wr_01.gif
===================================================================
--- pavr_hwres_rf_wr_01.gif (nonexistent)
+++ pavr_hwres_rf_wr_01.gif (revision 6)
pavr_hwres_rf_wr_01.gif
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: pavr_constants.vhd
===================================================================
--- pavr_constants.vhd (nonexistent)
+++ pavr_constants.vhd (revision 6)
@@ -0,0 +1,252 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This file defines the constants needed by pAVR.
+-- When costumizing pAVR, modify model-specific settings.
+-- However, don't touch family-specific settings.
+--
+
+
+
+--
+library work;
+use work.std_util.all;
+use work.pavr_util.all;
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+
+package pavr_constants is
+
+ ----------------------------------------------------------------------------
+ -- Controller model-specific settings. Modify here to costumize pAVR.
+
+
+
+ -- Data memory RAM-related constants. Take care, these must be self-consistent.
+ -- Data memory length and address width
+ constant pavr_dm_len : natural := 4096;
+ constant pavr_dm_addr_w : natural := 12;
+
+ -- Is data memory bigger than 256 bytes? (to be corellated with the
+ -- above) We need this to know whether to update both bytes of pointer
+ -- registers, or only the low byte, in loads/stores with pre/post
+ -- de/increment.
+ -- This is basically a boolean (=1 -> true; =0 -> false).
+ constant pavr_dm_bigger_than_256: std_logic := '1';
+
+ -- Is data memory bigger than 64KB? (to be corellated with the above) We need
+ -- this to know whether if to make use of data ramp registers or not. That
+ -- is, ramp registers RAMPX, RAMPY and RAMPZ.
+ constant pavr_dm_bigger_than_64K: std_logic := '0';
+
+
+
+ -- Program memory-related constants
+ -- Is program memory bigger than 64KB? We need this to know whether or not to
+ -- make use of ramp registers when accessing the Program Memory. These
+ -- registers are: ramp register EIND (for instructions EICALL and EIJMP)
+ -- and RAMPZ (for instruction ELPM).
+ constant pavr_pm_bigger_than_64K: std_logic := '1';
+
+
+
+ -- IOF registers addresses
+ -- Kernel registers
+ constant pavr_sreg_addr : natural := 16#3F#;
+ constant pavr_sph_addr : natural := 16#3E#;
+ constant pavr_spl_addr : natural := 16#3D#;
+ constant pavr_rampx_addr : natural := 16#39#;
+ constant pavr_rampy_addr : natural := 16#3a#;
+ constant pavr_rampz_addr : natural := 16#3b#;
+ constant pavr_rampd_addr : natural := 16#30#;
+ constant pavr_eind_addr : natural := 16#31#;
+
+ -- Feature registers
+ -- Microcontroller control
+ constant pavr_mcucr_addr : natural := 16#35#;
+ -- General interrupt mask
+ constant pavr_gimsk_addr : natural := 16#34#;
+ -- General interrupt flags
+ constant pavr_gifr_addr : natural := 16#38#;
+ -- Timer 0
+ constant pavr_tcnt0_addr : natural := 16#32#;
+ constant pavr_tccr0_addr : natural := 16#33#;
+ constant pavr_tifr_addr : natural := 16#36#;
+ constant pavr_timsk_addr : natural := 16#37#;
+ -- Port A
+ constant pavr_porta_addr : natural := 16#1B#;
+ constant pavr_ddra_addr : natural := 16#1A#;
+ constant pavr_pina_addr : natural := 16#19#;
+
+
+
+ -- Interrupt priorities
+ constant pavr_int0_int_pri: natural := 16#05#;
+ constant pavr_tov0_int_pri: natural := 16#09#;
+
+
+
+ -- Interrupt vectors
+ -- These can be anywhere in the 22 bit wide addressing space.
+ constant pavr_int0_int_vec: natural := 16#000001#;
+ constant pavr_tov0_int_vec: natural := 16#000006#;
+
+
+
+ ----------------------------------------------------------------------------
+ -- Family-specific settings. That is, don't touch.
+
+ -- ALU
+ constant pavr_alu_opcode_w : natural := 5;
+ constant pavr_alu_opcode_nop : natural := 0;
+ constant pavr_alu_opcode_op1 : natural := 1;
+ constant pavr_alu_opcode_op2 : natural := 2;
+ constant pavr_alu_opcode_add8 : natural := 3;
+ constant pavr_alu_opcode_adc8 : natural := 4;
+ constant pavr_alu_opcode_sub8 : natural := 5;
+ constant pavr_alu_opcode_sbc8 : natural := 6;
+ constant pavr_alu_opcode_and8 : natural := 7;
+ constant pavr_alu_opcode_eor8 : natural := 8;
+ constant pavr_alu_opcode_or8 : natural := 9;
+ constant pavr_alu_opcode_inc8 : natural := 10;
+ constant pavr_alu_opcode_dec8 : natural := 11;
+ constant pavr_alu_opcode_com8 : natural := 12;
+ constant pavr_alu_opcode_neg8 : natural := 13;
+ constant pavr_alu_opcode_swap8 : natural := 14;
+ constant pavr_alu_opcode_lsr8 : natural := 15;
+ constant pavr_alu_opcode_asr8 : natural := 16;
+ constant pavr_alu_opcode_ror8 : natural := 17;
+ constant pavr_alu_opcode_add16 : natural := 18;
+ constant pavr_alu_opcode_sub16 : natural := 19;
+ constant pavr_alu_opcode_mul8 : natural := 20;
+ constant pavr_alu_opcode_muls8 : natural := 21;
+ constant pavr_alu_opcode_mulsu8 : natural := 22;
+ constant pavr_alu_opcode_fmul8 : natural := 23;
+ constant pavr_alu_opcode_fmuls8 : natural := 24;
+ constant pavr_alu_opcode_fmulsu8 : natural := 25;
+ -- Select operand 1's higher 8 bits source.
+ constant pavr_alu_op1_hi8_sel_w : natural := 1;
+ constant pavr_alu_op1_hi8_sel_zero : std_logic := '0';
+ constant pavr_alu_op1_hi8_sel_op1bpu : std_logic := '1';
+ -- Select operand 2's source.
+ constant pavr_alu_op2_sel_w : natural := 2;
+ constant pavr_alu_op2_sel_op2bpu : std_logic_vector(pavr_alu_op2_sel_w - 1 downto 0) := "00";
+ constant pavr_alu_op2_sel_k8 : std_logic_vector(pavr_alu_op2_sel_w - 1 downto 0) := "01";
+ constant pavr_alu_op2_sel_1 : std_logic_vector(pavr_alu_op2_sel_w - 1 downto 0) := "10";
+ constant pavr_alu_op2_sel_minus1 : std_logic_vector(pavr_alu_op2_sel_w - 1 downto 0) := "11";
+ -- Flags
+ constant pavr_alu_h_sel_w : natural := 2;
+ constant pavr_alu_h_sel_same : std_logic_vector(pavr_alu_h_sel_w - 1 downto 0) := "00";
+ constant pavr_alu_h_sel_add8 : std_logic_vector(pavr_alu_h_sel_w - 1 downto 0) := "01";
+ constant pavr_alu_h_sel_sub8 : std_logic_vector(pavr_alu_h_sel_w - 1 downto 0) := "10";
+ constant pavr_alu_h_sel_neg8 : std_logic_vector(pavr_alu_h_sel_w - 1 downto 0) := "11";
+ constant pavr_alu_s_sel_w : natural := 1;
+ constant pavr_alu_s_sel_same : std_logic := '0';
+ constant pavr_alu_s_sel_nxorv : std_logic := '1';
+ constant pavr_alu_v_sel_w : natural := 4;
+ constant pavr_alu_v_sel_same : std_logic_vector(pavr_alu_v_sel_w - 1 downto 0) := "0000";
+ constant pavr_alu_v_sel_add8 : std_logic_vector(pavr_alu_v_sel_w - 1 downto 0) := "0001";
+ constant pavr_alu_v_sel_sub8 : std_logic_vector(pavr_alu_v_sel_w - 1 downto 0) := "0010";
+ constant pavr_alu_v_sel_z : std_logic_vector(pavr_alu_v_sel_w - 1 downto 0) := "0011";
+ constant pavr_alu_v_sel_inc8 : std_logic_vector(pavr_alu_v_sel_w - 1 downto 0) := "0100";
+ constant pavr_alu_v_sel_dec8 : std_logic_vector(pavr_alu_v_sel_w - 1 downto 0) := "0101";
+ constant pavr_alu_v_sel_neg8 : std_logic_vector(pavr_alu_v_sel_w - 1 downto 0) := "0110";
+ constant pavr_alu_v_sel_nxorc : std_logic_vector(pavr_alu_v_sel_w - 1 downto 0) := "0111";
+ constant pavr_alu_v_sel_add16 : std_logic_vector(pavr_alu_v_sel_w - 1 downto 0) := "1000";
+ constant pavr_alu_v_sel_sub16 : std_logic_vector(pavr_alu_v_sel_w - 1 downto 0) := "1001";
+ constant pavr_alu_n_sel_w : natural := 2;
+ constant pavr_alu_n_sel_same : std_logic_vector(pavr_alu_n_sel_w - 1 downto 0) := "00";
+ constant pavr_alu_n_sel_msb8 : std_logic_vector(pavr_alu_n_sel_w - 1 downto 0) := "01";
+ constant pavr_alu_n_sel_z : std_logic_vector(pavr_alu_n_sel_w - 1 downto 0) := "10";
+ constant pavr_alu_n_sel_msb16 : std_logic_vector(pavr_alu_n_sel_w - 1 downto 0) := "11";
+ constant pavr_alu_z_sel_w : natural := 2;
+ constant pavr_alu_z_sel_same : std_logic_vector(pavr_alu_z_sel_w - 1 downto 0) := "00";
+ constant pavr_alu_z_sel_z8 : std_logic_vector(pavr_alu_z_sel_w - 1 downto 0) := "01";
+ constant pavr_alu_z_sel_z8c : std_logic_vector(pavr_alu_z_sel_w - 1 downto 0) := "10";
+ constant pavr_alu_z_sel_z16 : std_logic_vector(pavr_alu_z_sel_w - 1 downto 0) := "11";
+ constant pavr_alu_c_sel_w : natural := 3;
+ constant pavr_alu_c_sel_same : std_logic_vector(pavr_alu_c_sel_w - 1 downto 0) := "000";
+ constant pavr_alu_c_sel_add8 : std_logic_vector(pavr_alu_c_sel_w - 1 downto 0) := "001";
+ constant pavr_alu_c_sel_sub8 : std_logic_vector(pavr_alu_c_sel_w - 1 downto 0) := "010";
+ constant pavr_alu_c_sel_one : std_logic_vector(pavr_alu_c_sel_w - 1 downto 0) := "011";
+ constant pavr_alu_c_sel_neg8 : std_logic_vector(pavr_alu_c_sel_w - 1 downto 0) := "100";
+ constant pavr_alu_c_sel_lsbop1 : std_logic_vector(pavr_alu_c_sel_w - 1 downto 0) := "101";
+ constant pavr_alu_c_sel_add16 : std_logic_vector(pavr_alu_c_sel_w - 1 downto 0) := "110";
+ constant pavr_alu_c_sel_sub16 : std_logic_vector(pavr_alu_c_sel_w - 1 downto 0) := "111";
+
+ -- IOF
+ constant pavr_iof_opcode_w : natural := 3;
+ constant pavr_iof_opcode_nop : std_logic_vector(pavr_iof_opcode_w - 1 downto 0) := "000";
+ constant pavr_iof_opcode_rdbyte : std_logic_vector(pavr_iof_opcode_w - 1 downto 0) := "001";
+ constant pavr_iof_opcode_wrbyte : std_logic_vector(pavr_iof_opcode_w - 1 downto 0) := "010";
+ constant pavr_iof_opcode_clrbit : std_logic_vector(pavr_iof_opcode_w - 1 downto 0) := "011";
+ constant pavr_iof_opcode_setbit : std_logic_vector(pavr_iof_opcode_w - 1 downto 0) := "100";
+ constant pavr_iof_opcode_ldbit : std_logic_vector(pavr_iof_opcode_w - 1 downto 0) := "101";
+ constant pavr_iof_opcode_stbit : std_logic_vector(pavr_iof_opcode_w - 1 downto 0) := "110";
+
+ -- DACU
+ constant pavr_dacudo_sel_w : natural := 2;
+ constant pavr_dacudo_sel_rfrd1do : std_logic_vector(pavr_dacudo_sel_w - 1 downto 0) := "00";
+ constant pavr_dacudo_sel_iofdo : std_logic_vector(pavr_dacudo_sel_w - 1 downto 0) := "01";
+ constant pavr_dacudo_sel_dmdo : std_logic_vector(pavr_dacudo_sel_w - 1 downto 0) := "10";
+ constant pavr_dacu_device_sel_w : natural := 2;
+ constant pavr_dacu_device_sel_rf : std_logic_vector(pavr_dacu_device_sel_w - 1 downto 0) := "00";
+ constant pavr_dacu_device_sel_iof : std_logic_vector(pavr_dacu_device_sel_w - 1 downto 0) := "01";
+ constant pavr_dacu_device_sel_dm : std_logic_vector(pavr_dacu_device_sel_w - 1 downto 0) := "10";
+
+ -- PM
+ constant pavr_pc_sel_w : natural := 1;
+ constant pavr_pc_sel_same : std_logic := '0';
+ constant pavr_pc_sel_inc : std_logic := '1';
+
+ -- SFU
+ constant pavr_s5_skip_cond_sel_w : natural := 2;
+ constant pavr_s5_skip_cond_sel_zflag : std_logic_vector(pavr_s5_skip_cond_sel_w - 1 downto 0) := "00";
+ constant pavr_s5_skip_cond_sel_bitrf : std_logic_vector(pavr_s5_skip_cond_sel_w - 1 downto 0) := "01";
+ constant pavr_s5_skip_cond_sel_notbitrf : std_logic_vector(pavr_s5_skip_cond_sel_w - 1 downto 0) := "10";
+ constant pavr_s6_skip_cond_sel_w : natural := 1;
+ constant pavr_s6_skip_cond_sel_bitiof : std_logic := '0';
+ constant pavr_s6_skip_cond_sel_notbitiof : std_logic := '1';
+ constant pavr_s5_skip_bitrf_sel_w : natural := 3;
+ constant pavr_s6_skip_bitiof_sel_w : natural := 3;
+ constant pavr_s5_branch_cond_sel_w : natural := 1;
+ constant pavr_s5_branch_cond_sel_bitsreg : std_logic := '0';
+ constant pavr_s5_branch_cond_sel_notbitsreg : std_logic := '1';
+
+end;
+--
Index: test_pavr_control_interrupts.vhd
===================================================================
--- test_pavr_control_interrupts.vhd (nonexistent)
+++ test_pavr_control_interrupts.vhd (revision 6)
@@ -0,0 +1,138 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This tests pAVR's interrupts.
+-- NOT DONE YET.
+--
+
+
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+library work;
+use work.std_util.all;
+use work.pavr_util.all;
+use work.pavr_constants.all;
+
+
+entity test_pavr_rf is
+end;
+
+
+architecture test_pavr_rf_arch of test_pavr_rf is
+ signal clk, res, syncres: std_logic;
+
+ -- Clock counter
+ signal cnt: std_logic_vector(7 downto 0);
+
+begin
+
+ generate_clock:
+ process
+ begin
+ clk <= '1';
+ wait for 50 ns;
+ clk <= '0';
+ wait for 50 ns;
+ end process generate_clock;
+
+
+ generate_reset:
+ process
+ begin
+ res <= '0';
+ wait for 100 ns;
+ res <= '1';
+ wait for 110 ns;
+ res <= '0';
+ wait for 1 ms;
+ end process generate_reset;
+
+
+ generate_sync_reset:
+ process
+ begin
+ syncres <= '0';
+ wait for 300 ns;
+ syncres <= '1';
+ wait for 110 ns;
+ syncres <= '0';
+ wait for 1 ms;
+ end process generate_sync_reset;
+
+
+ test_main:
+ process(clk, res, syncres,
+ cnt,
+ pavr_rf_rd1_addr,
+ pavr_rf_rd2_addr,
+ pavr_rf_wr_addr, pavr_rf_wr_di,
+ pavr_rf_x_di,
+ pavr_rf_y_di,
+ pavr_rf_z_di
+ )
+ begin
+ if res='1' then
+ -- Async reset
+
+ cnt <= int_to_std_logic_vector(0, cnt'length);
+ elsif clk'event and clk='1' then
+ -- Clock counter
+ cnt <= cnt+1;
+
+ -- Initialize inputs.
+
+ case std_logic_vector_to_nat(cnt) is
+
+ -- TEST 1
+
+
+ when others =>
+ null;
+ end case;
+
+ if syncres='1' then
+ -- Sync reset
+
+ cnt <= int_to_std_logic_vector(0, cnt'length);
+ end if;
+ end if;
+ end process test_main;
+
+
+end;
+--
Index: test_pavr.vhd
===================================================================
--- test_pavr.vhd (nonexistent)
+++ test_pavr.vhd (revision 6)
@@ -0,0 +1,1199 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This is the main test entity. It embedds a pAVR controller, its Program
+-- Memory and a muxer for taking/getting Program Memory access to/from pAVR.
+-- This entity implements the following behavior:
+-- - 1. reset all registers.
+-- For the easyness of debugging, they are resetted to a particular non-zero
+-- value (0x77).
+-- Funny enough, the registers are initialized by pAVR itself, by providing
+-- to it code for that.
+-- - 2. load the Program Memory with pAVR's program.
+-- This section is tagged. By using the TagScan utility, this architecture
+-- is automatically modified so that an external binary file is transposed
+-- into VHDL statements that load the Program Memory.
+-- This section rewrites the code from the previous section (register
+-- loading).
+-- - 3. Finally, release the reset lines and let pAVR do its job.
+-- Note
+-- Care has NOT been taken not to generate latches all over these tests.
+-- They ARE generated, there are even 3 state latches, for the ease of testing.
+-- However, care HAS BEEN taken in pAVR sources that no latches should be
+-- generated there. That is because pAVR is meant to be synthesizable, while
+-- pAVR tests are not.
+-- To do
+-- - Afer resetting registers, but before loading binary file, pAVR executes
+-- instructions that are made of Xs. It happens that the instruction decoder
+-- decodes these into nops, so it's OK, but not nice. This must be corrected.
+--
+
+
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+library work;
+use work.std_util.all;
+use work.pavr_util.all;
+use work.pavr_constants.all;
+use work.test_pavr_util.all;
+use work.test_pavr_constants.all;
+
+
+entity test_pavr is
+end;
+
+
+architecture test_pavr_arch of test_pavr is
+ signal clk, res, syncres: std_logic;
+
+ -- Clock counter
+ -- Maximum number of testing clocks: 2 billions instructions. Should be enough...
+ signal main_clk_cnt, run_clk_cnt: std_logic_vector(30 downto 0);
+
+ -- Instruction counter
+ signal instr_cnt: std_logic_vector(30 downto 0);
+
+ -- Signals to control the mixture formed by pAVR, Program Memory and muxers.
+ signal pm_sel: std_logic;
+ signal pm_di: std_logic_vector(15 downto 0);
+ signal pm_wr: std_logic;
+ signal pm_addr: std_logic_vector(21 downto 0);
+ signal pa: std_logic_vector(7 downto 0);
+
+ -- pAVR controller-related connectivity
+ signal pavr_pavr_res: std_logic;
+ signal pavr_pavr_syncres: std_logic;
+ signal pavr_pavr_pm_addr: std_logic_vector(21 downto 0);
+ signal pavr_pavr_pm_do: std_logic_vector(15 downto 0);
+ signal pavr_pavr_pm_wr: std_logic;
+ signal pavr_pavr_inc_instr_cnt: std_logic_vector(1 downto 0);
+
+ -- PM-related connectivity
+ signal pm_pavr_pm_wr: std_logic;
+ signal pm_pavr_pm_addr: std_logic_vector(21 downto 0);
+ signal pm_pavr_pm_di: std_logic_vector(15 downto 0);
+ signal pm_pavr_pm_do: std_logic_vector(15 downto 0);
+
+ -- Declare the pAVR controller.
+ component pavr
+ port(
+ pavr_clk: in std_logic;
+ pavr_res: in std_logic;
+ pavr_syncres: in std_logic;
+ pavr_pm_addr: out std_logic_vector(21 downto 0);
+ pavr_pm_do: in std_logic_vector(15 downto 0);
+ pavr_pm_wr: out std_logic;
+ pavr_pa: inout std_logic_vector(7 downto 0);
+ pavr_inc_instr_cnt: out std_logic_vector(1 downto 0)
+ );
+ end component;
+ for all: pavr use entity work.pavr(pavr_arch);
+
+ -- Declare the Program Memory.
+ component pavr_pm
+ port(
+ pavr_pm_clk: in std_logic;
+ pavr_pm_wr: in std_logic;
+ pavr_pm_addr: in std_logic_vector(21 downto 0);
+ pavr_pm_di: in std_logic_vector(15 downto 0);
+ pavr_pm_do: out std_logic_vector(15 downto 0)
+ );
+ end component;
+ for all: pavr_pm use entity work.pavr_pm(pavr_pm_arch);
+
+begin
+
+ -- Instantiate the pAVR controller.
+ pavr_instance1: pavr
+ port map(
+ clk,
+ pavr_pavr_res,
+ pavr_pavr_syncres,
+ pavr_pavr_pm_addr,
+ pavr_pavr_pm_do,
+ pavr_pavr_pm_wr,
+ pa,
+ pavr_pavr_inc_instr_cnt
+ );
+
+ -- Instantiate the Program Memory.
+ pavr_pm_instance1: pavr_pm
+ port map(
+ clk,
+ pm_pavr_pm_wr,
+ pm_pavr_pm_addr,
+ pm_pavr_pm_di,
+ pm_pavr_pm_do
+ );
+
+ generate_clock:
+ process
+ begin
+ clk <= '1';
+ wait for 50 ns;
+ clk <= '0';
+ wait for 50 ns;
+ end process generate_clock;
+
+
+ generate_reset:
+ process
+ begin
+ --res <= '0';
+ --wait for 100 ns;
+ res <= '1';
+ wait for 110 ns;
+ res <= '0';
+ wait for 1000000 sec;
+ end process generate_reset;
+
+
+ generate_sync_reset:
+ process
+ begin
+ --syncres <= '0';
+ --wait for 300 ns;
+ syncres <= '1';
+ wait for 310 ns;
+ syncres <= '0';
+ wait for 1000000 sec;
+ end process generate_sync_reset;
+
+
+ test_main:
+ process(clk, res, syncres,
+ pm_di, pm_addr, pavr_pavr_res, pavr_pavr_syncres,
+ main_clk_cnt, run_clk_cnt, instr_cnt,
+ pavr_pavr_inc_instr_cnt
+ )
+ variable tmpv1: std_logic_vector(pm_di'length+pm_addr'length-1 downto 0); -- This will generate a latch, but who cares? this is not intended to be synthesized.
+ begin
+ if res='1' then
+ -- Async reset
+
+ -- Reset the controller in turn.
+ pavr_pavr_res <= '1';
+
+ main_clk_cnt <= int_to_std_logic_vector(0, main_clk_cnt'length);
+ run_clk_cnt <= int_to_std_logic_vector(0, run_clk_cnt'length);
+ instr_cnt <= int_to_std_logic_vector(0, instr_cnt'length);
+ elsif clk'event and clk='1' then
+ -- Clock counter
+ main_clk_cnt <= main_clk_cnt+1;
+ run_clk_cnt <= run_clk_cnt+1;
+
+ -- Instruction counter
+ case pavr_pavr_inc_instr_cnt is
+ when "01" =>
+ instr_cnt <= instr_cnt+1;
+ when "10" =>
+ instr_cnt <= instr_cnt+2;
+ when "11" =>
+ instr_cnt <= instr_cnt-1;
+ when others =>
+ null;
+ end case;
+
+ -- Set up Program Memory and let pAVR do its job.
+ if (std_logic_vector_to_nat(main_clk_cnt)>=3 and std_logic_vector_to_nat(main_clk_cnt)<35) or
+ (std_logic_vector_to_nat(main_clk_cnt)>=100 and std_logic_vector_to_nat(main_clk_cnt)<
+ -- The following tagged lines are written automatically, based on the binary file,
+ -- by using the tagScan utility.
+--
+964
+--
+ ) then
+ -- Set up Program Memory.
+ case std_logic_vector_to_nat(main_clk_cnt) is
+ -- Initialize all 32 registers to 0x77.
+ when 3 => tmpv1 := pm_setup( 0, 16#e747#);
+ when 4 => tmpv1 := pm_setup( 1, 16#2e04#);
+ when 5 => tmpv1 := pm_setup( 2, 16#2e14#);
+ when 6 => tmpv1 := pm_setup( 3, 16#2e24#);
+ when 7 => tmpv1 := pm_setup( 4, 16#2e34#);
+ when 8 => tmpv1 := pm_setup( 5, 16#2e44#);
+ when 9 => tmpv1 := pm_setup( 6, 16#2e54#);
+ when 10 => tmpv1 := pm_setup( 7, 16#2e64#);
+ when 11 => tmpv1 := pm_setup( 8, 16#2e74#);
+ when 12 => tmpv1 := pm_setup( 9, 16#2e84#);
+ when 13 => tmpv1 := pm_setup(10, 16#2e94#);
+ when 14 => tmpv1 := pm_setup(11, 16#2ea4#);
+ when 15 => tmpv1 := pm_setup(12, 16#2eb4#);
+ when 16 => tmpv1 := pm_setup(13, 16#2ec4#);
+ when 17 => tmpv1 := pm_setup(14, 16#2ed4#);
+ when 18 => tmpv1 := pm_setup(15, 16#2ee4#);
+ when 19 => tmpv1 := pm_setup(16, 16#2ef4#);
+ when 20 => tmpv1 := pm_setup(17, 16#2f04#);
+ when 21 => tmpv1 := pm_setup(18, 16#2f14#);
+ when 22 => tmpv1 := pm_setup(19, 16#2f24#);
+ when 23 => tmpv1 := pm_setup(20, 16#2f34#);
+ when 24 => tmpv1 := pm_setup(21, 16#2f54#);
+ when 25 => tmpv1 := pm_setup(22, 16#2f64#);
+ when 26 => tmpv1 := pm_setup(23, 16#2f74#);
+ when 27 => tmpv1 := pm_setup(24, 16#2f84#);
+ when 28 => tmpv1 := pm_setup(25, 16#2f94#);
+ when 29 => tmpv1 := pm_setup(26, 16#2fa4#);
+ when 30 => tmpv1 := pm_setup(27, 16#2fb4#);
+ when 31 => tmpv1 := pm_setup(28, 16#2fc4#);
+ when 32 => tmpv1 := pm_setup(29, 16#2fd4#);
+ when 33 => tmpv1 := pm_setup(30, 16#2fe4#);
+ when 34 => tmpv1 := pm_setup(31, 16#2ff4#);
+ -- The following tagged lines are written automatically, based on the binary file,
+ -- by using the tagScan utility.
+--
+ when 100 => tmpv1 := pm_setup(0, 16#940c#);
+ when 101 => tmpv1 := pm_setup(1, 16#0030#);
+ when 102 => tmpv1 := pm_setup(2, 16#940c#);
+ when 103 => tmpv1 := pm_setup(3, 16#0050#);
+ when 104 => tmpv1 := pm_setup(4, 16#940c#);
+ when 105 => tmpv1 := pm_setup(5, 16#0050#);
+ when 106 => tmpv1 := pm_setup(6, 16#940c#);
+ when 107 => tmpv1 := pm_setup(7, 16#0050#);
+ when 108 => tmpv1 := pm_setup(8, 16#940c#);
+ when 109 => tmpv1 := pm_setup(9, 16#0050#);
+ when 110 => tmpv1 := pm_setup(10, 16#940c#);
+ when 111 => tmpv1 := pm_setup(11, 16#0050#);
+ when 112 => tmpv1 := pm_setup(12, 16#940c#);
+ when 113 => tmpv1 := pm_setup(13, 16#0050#);
+ when 114 => tmpv1 := pm_setup(14, 16#940c#);
+ when 115 => tmpv1 := pm_setup(15, 16#0050#);
+ when 116 => tmpv1 := pm_setup(16, 16#940c#);
+ when 117 => tmpv1 := pm_setup(17, 16#0050#);
+ when 118 => tmpv1 := pm_setup(18, 16#940c#);
+ when 119 => tmpv1 := pm_setup(19, 16#0050#);
+ when 120 => tmpv1 := pm_setup(20, 16#940c#);
+ when 121 => tmpv1 := pm_setup(21, 16#0050#);
+ when 122 => tmpv1 := pm_setup(22, 16#940c#);
+ when 123 => tmpv1 := pm_setup(23, 16#0050#);
+ when 124 => tmpv1 := pm_setup(24, 16#940c#);
+ when 125 => tmpv1 := pm_setup(25, 16#0050#);
+ when 126 => tmpv1 := pm_setup(26, 16#940c#);
+ when 127 => tmpv1 := pm_setup(27, 16#0050#);
+ when 128 => tmpv1 := pm_setup(28, 16#940c#);
+ when 129 => tmpv1 := pm_setup(29, 16#0050#);
+ when 130 => tmpv1 := pm_setup(30, 16#940c#);
+ when 131 => tmpv1 := pm_setup(31, 16#0050#);
+ when 132 => tmpv1 := pm_setup(32, 16#940c#);
+ when 133 => tmpv1 := pm_setup(33, 16#0050#);
+ when 134 => tmpv1 := pm_setup(34, 16#940c#);
+ when 135 => tmpv1 := pm_setup(35, 16#0050#);
+ when 136 => tmpv1 := pm_setup(36, 16#940c#);
+ when 137 => tmpv1 := pm_setup(37, 16#0050#);
+ when 138 => tmpv1 := pm_setup(38, 16#940c#);
+ when 139 => tmpv1 := pm_setup(39, 16#0050#);
+ when 140 => tmpv1 := pm_setup(40, 16#940c#);
+ when 141 => tmpv1 := pm_setup(41, 16#0050#);
+ when 142 => tmpv1 := pm_setup(42, 16#940c#);
+ when 143 => tmpv1 := pm_setup(43, 16#0050#);
+ when 144 => tmpv1 := pm_setup(44, 16#940c#);
+ when 145 => tmpv1 := pm_setup(45, 16#0050#);
+ when 146 => tmpv1 := pm_setup(46, 16#940c#);
+ when 147 => tmpv1 := pm_setup(47, 16#0050#);
+ when 148 => tmpv1 := pm_setup(48, 16#2411#);
+ when 149 => tmpv1 := pm_setup(49, 16#be1f#);
+ when 150 => tmpv1 := pm_setup(50, 16#efcf#);
+ when 151 => tmpv1 := pm_setup(51, 16#e0df#);
+ when 152 => tmpv1 := pm_setup(52, 16#bfde#);
+ when 153 => tmpv1 := pm_setup(53, 16#bfcd#);
+ when 154 => tmpv1 := pm_setup(54, 16#e010#);
+ when 155 => tmpv1 := pm_setup(55, 16#e6a0#);
+ when 156 => tmpv1 := pm_setup(56, 16#e0b0#);
+ when 157 => tmpv1 := pm_setup(57, 16#ece0#);
+ when 158 => tmpv1 := pm_setup(58, 16#e0f6#);
+ when 159 => tmpv1 := pm_setup(59, 16#ef0f#);
+ when 160 => tmpv1 := pm_setup(60, 16#9503#);
+ when 161 => tmpv1 := pm_setup(61, 16#bf0b#);
+ when 162 => tmpv1 := pm_setup(62, 16#c004#);
+ when 163 => tmpv1 := pm_setup(63, 16#95c8#);
+ when 164 => tmpv1 := pm_setup(64, 16#920d#);
+ when 165 => tmpv1 := pm_setup(65, 16#9631#);
+ when 166 => tmpv1 := pm_setup(66, 16#f3c8#);
+ when 167 => tmpv1 := pm_setup(67, 16#36a0#);
+ when 168 => tmpv1 := pm_setup(68, 16#07b1#);
+ when 169 => tmpv1 := pm_setup(69, 16#f7c9#);
+ when 170 => tmpv1 := pm_setup(70, 16#e011#);
+ when 171 => tmpv1 := pm_setup(71, 16#e6a0#);
+ when 172 => tmpv1 := pm_setup(72, 16#e0b0#);
+ when 173 => tmpv1 := pm_setup(73, 16#c001#);
+ when 174 => tmpv1 := pm_setup(74, 16#921d#);
+ when 175 => tmpv1 := pm_setup(75, 16#35a1#);
+ when 176 => tmpv1 := pm_setup(76, 16#07b1#);
+ when 177 => tmpv1 := pm_setup(77, 16#f7e1#);
+ when 178 => tmpv1 := pm_setup(78, 16#940c#);
+ when 179 => tmpv1 := pm_setup(79, 16#0052#);
+ when 180 => tmpv1 := pm_setup(80, 16#940c#);
+ when 181 => tmpv1 := pm_setup(81, 16#0000#);
+ when 182 => tmpv1 := pm_setup(82, 16#eecf#);
+ when 183 => tmpv1 := pm_setup(83, 16#e0df#);
+ when 184 => tmpv1 := pm_setup(84, 16#bfde#);
+ when 185 => tmpv1 := pm_setup(85, 16#bfcd#);
+ when 186 => tmpv1 := pm_setup(86, 16#8219#);
+ when 187 => tmpv1 := pm_setup(87, 16#821a#);
+ when 188 => tmpv1 := pm_setup(88, 16#e040#);
+ when 189 => tmpv1 := pm_setup(89, 16#e050#);
+ when 190 => tmpv1 := pm_setup(90, 16#821b#);
+ when 191 => tmpv1 := pm_setup(91, 16#821c#);
+ when 192 => tmpv1 := pm_setup(92, 16#2f24#);
+ when 193 => tmpv1 := pm_setup(93, 16#2f35#);
+ when 194 => tmpv1 := pm_setup(94, 16#0f22#);
+ when 195 => tmpv1 := pm_setup(95, 16#1f33#);
+ when 196 => tmpv1 := pm_setup(96, 16#0f22#);
+ when 197 => tmpv1 := pm_setup(97, 16#1f33#);
+ when 198 => tmpv1 := pm_setup(98, 16#2ff3#);
+ when 199 => tmpv1 := pm_setup(99, 16#2fe2#);
+ when 200 => tmpv1 := pm_setup(100, 16#5ae0#);
+ when 201 => tmpv1 := pm_setup(101, 16#4fff#);
+ when 202 => tmpv1 := pm_setup(102, 16#e080#);
+ when 203 => tmpv1 := pm_setup(103, 16#e090#);
+ when 204 => tmpv1 := pm_setup(104, 16#e0a0#);
+ when 205 => tmpv1 := pm_setup(105, 16#e0b0#);
+ when 206 => tmpv1 := pm_setup(106, 16#8380#);
+ when 207 => tmpv1 := pm_setup(107, 16#8391#);
+ when 208 => tmpv1 := pm_setup(108, 16#83a2#);
+ when 209 => tmpv1 := pm_setup(109, 16#83b3#);
+ when 210 => tmpv1 := pm_setup(110, 16#2ff3#);
+ when 211 => tmpv1 := pm_setup(111, 16#2fe2#);
+ when 212 => tmpv1 := pm_setup(112, 16#53ec#);
+ when 213 => tmpv1 := pm_setup(113, 16#4fff#);
+ when 214 => tmpv1 := pm_setup(114, 16#8380#);
+ when 215 => tmpv1 := pm_setup(115, 16#8391#);
+ when 216 => tmpv1 := pm_setup(116, 16#83a2#);
+ when 217 => tmpv1 := pm_setup(117, 16#83b3#);
+ when 218 => tmpv1 := pm_setup(118, 16#5f2c#);
+ when 219 => tmpv1 := pm_setup(119, 16#4f3f#);
+ when 220 => tmpv1 := pm_setup(120, 16#818b#);
+ when 221 => tmpv1 := pm_setup(121, 16#819c#);
+ when 222 => tmpv1 := pm_setup(122, 16#9601#);
+ when 223 => tmpv1 := pm_setup(123, 16#838b#);
+ when 224 => tmpv1 := pm_setup(124, 16#839c#);
+ when 225 => tmpv1 := pm_setup(125, 16#9705#);
+ when 226 => tmpv1 := pm_setup(126, 16#f31c#);
+ when 227 => tmpv1 := pm_setup(127, 16#5f4b#);
+ when 228 => tmpv1 := pm_setup(128, 16#4f5f#);
+ when 229 => tmpv1 := pm_setup(129, 16#81e9#);
+ when 230 => tmpv1 := pm_setup(130, 16#81fa#);
+ when 231 => tmpv1 := pm_setup(131, 16#9631#);
+ when 232 => tmpv1 := pm_setup(132, 16#83e9#);
+ when 233 => tmpv1 := pm_setup(133, 16#83fa#);
+ when 234 => tmpv1 := pm_setup(134, 16#9735#);
+ when 235 => tmpv1 := pm_setup(135, 16#f294#);
+ when 236 => tmpv1 := pm_setup(136, 16#e686#);
+ when 237 => tmpv1 := pm_setup(137, 16#e696#);
+ when 238 => tmpv1 := pm_setup(138, 16#e6a6#);
+ when 239 => tmpv1 := pm_setup(139, 16#e3bf#);
+ when 240 => tmpv1 := pm_setup(140, 16#9380#);
+ when 241 => tmpv1 := pm_setup(141, 16#0078#);
+ when 242 => tmpv1 := pm_setup(142, 16#9390#);
+ when 243 => tmpv1 := pm_setup(143, 16#0079#);
+ when 244 => tmpv1 := pm_setup(144, 16#93a0#);
+ when 245 => tmpv1 := pm_setup(145, 16#007a#);
+ when 246 => tmpv1 := pm_setup(146, 16#93b0#);
+ when 247 => tmpv1 := pm_setup(147, 16#007b#);
+ when 248 => tmpv1 := pm_setup(148, 16#821d#);
+ when 249 => tmpv1 := pm_setup(149, 16#821e#);
+ when 250 => tmpv1 := pm_setup(150, 16#8219#);
+ when 251 => tmpv1 := pm_setup(151, 16#821a#);
+ when 252 => tmpv1 := pm_setup(152, 16#e020#);
+ when 253 => tmpv1 := pm_setup(153, 16#e030#);
+ when 254 => tmpv1 := pm_setup(154, 16#832f#);
+ when 255 => tmpv1 := pm_setup(155, 16#8738#);
+ when 256 => tmpv1 := pm_setup(156, 16#8729#);
+ when 257 => tmpv1 := pm_setup(157, 16#873a#);
+ when 258 => tmpv1 := pm_setup(158, 16#821b#);
+ when 259 => tmpv1 := pm_setup(159, 16#821c#);
+ when 260 => tmpv1 := pm_setup(160, 16#818f#);
+ when 261 => tmpv1 := pm_setup(161, 16#8598#);
+ when 262 => tmpv1 := pm_setup(162, 16#0f88#);
+ when 263 => tmpv1 := pm_setup(163, 16#1f99#);
+ when 264 => tmpv1 := pm_setup(164, 16#0f88#);
+ when 265 => tmpv1 := pm_setup(165, 16#1f99#);
+ when 266 => tmpv1 := pm_setup(166, 16#2ff9#);
+ when 267 => tmpv1 := pm_setup(167, 16#2fe8#);
+ when 268 => tmpv1 := pm_setup(168, 16#5be8#);
+ when 269 => tmpv1 := pm_setup(169, 16#4fff#);
+ when 270 => tmpv1 := pm_setup(170, 16#87ef#);
+ when 271 => tmpv1 := pm_setup(171, 16#8bf8#);
+ when 272 => tmpv1 := pm_setup(172, 16#2f28#);
+ when 273 => tmpv1 := pm_setup(173, 16#2f39#);
+ when 274 => tmpv1 := pm_setup(174, 16#532c#);
+ when 275 => tmpv1 := pm_setup(175, 16#4f3f#);
+ when 276 => tmpv1 := pm_setup(176, 16#872b#);
+ when 277 => tmpv1 := pm_setup(177, 16#873c#);
+ when 278 => tmpv1 := pm_setup(178, 16#8589#);
+ when 279 => tmpv1 := pm_setup(179, 16#859a#);
+ when 280 => tmpv1 := pm_setup(180, 16#0f88#);
+ when 281 => tmpv1 := pm_setup(181, 16#1f99#);
+ when 282 => tmpv1 := pm_setup(182, 16#0f88#);
+ when 283 => tmpv1 := pm_setup(183, 16#1f99#);
+ when 284 => tmpv1 := pm_setup(184, 16#878d#);
+ when 285 => tmpv1 := pm_setup(185, 16#879e#);
+ when 286 => tmpv1 := pm_setup(186, 16#81e9#);
+ when 287 => tmpv1 := pm_setup(187, 16#81fa#);
+ when 288 => tmpv1 := pm_setup(188, 16#9730#);
+ when 289 => tmpv1 := pm_setup(189, 16#f409#);
+ when 290 => tmpv1 := pm_setup(190, 16#c19a#);
+ when 291 => tmpv1 := pm_setup(191, 16#812b#);
+ when 292 => tmpv1 := pm_setup(192, 16#813c#);
+ when 293 => tmpv1 := pm_setup(193, 16#1521#);
+ when 294 => tmpv1 := pm_setup(194, 16#0531#);
+ when 295 => tmpv1 := pm_setup(195, 16#f409#);
+ when 296 => tmpv1 := pm_setup(196, 16#c194#);
+ when 297 => tmpv1 := pm_setup(197, 16#9734#);
+ when 298 => tmpv1 := pm_setup(198, 16#f409#);
+ when 299 => tmpv1 := pm_setup(199, 16#c191#);
+ when 300 => tmpv1 := pm_setup(200, 16#3024#);
+ when 301 => tmpv1 := pm_setup(201, 16#0531#);
+ when 302 => tmpv1 := pm_setup(202, 16#f409#);
+ when 303 => tmpv1 := pm_setup(203, 16#c18d#);
+ when 304 => tmpv1 := pm_setup(204, 16#85eb#);
+ when 305 => tmpv1 := pm_setup(205, 16#85fc#);
+ when 306 => tmpv1 := pm_setup(206, 16#8180#);
+ when 307 => tmpv1 := pm_setup(207, 16#8191#);
+ when 308 => tmpv1 := pm_setup(208, 16#81a2#);
+ when 309 => tmpv1 := pm_setup(209, 16#81b3#);
+ when 310 => tmpv1 := pm_setup(210, 16#e626#);
+ when 311 => tmpv1 := pm_setup(211, 16#e636#);
+ when 312 => tmpv1 := pm_setup(212, 16#e646#);
+ when 313 => tmpv1 := pm_setup(213, 16#e35f#);
+ when 314 => tmpv1 := pm_setup(214, 16#2f68#);
+ when 315 => tmpv1 := pm_setup(215, 16#2f79#);
+ when 316 => tmpv1 := pm_setup(216, 16#2f8a#);
+ when 317 => tmpv1 := pm_setup(217, 16#2f9b#);
+ when 318 => tmpv1 := pm_setup(218, 16#940e#);
+ when 319 => tmpv1 := pm_setup(219, 16#030f#);
+ when 320 => tmpv1 := pm_setup(220, 16#2e26#);
+ when 321 => tmpv1 := pm_setup(221, 16#2e37#);
+ when 322 => tmpv1 := pm_setup(222, 16#2e48#);
+ when 323 => tmpv1 := pm_setup(223, 16#2e59#);
+ when 324 => tmpv1 := pm_setup(224, 16#85ef#);
+ when 325 => tmpv1 := pm_setup(225, 16#89f8#);
+ when 326 => tmpv1 := pm_setup(226, 16#8c60#);
+ when 327 => tmpv1 := pm_setup(227, 16#8c71#);
+ when 328 => tmpv1 := pm_setup(228, 16#8c82#);
+ when 329 => tmpv1 := pm_setup(229, 16#8c93#);
+ when 330 => tmpv1 := pm_setup(230, 16#e020#);
+ when 331 => tmpv1 := pm_setup(231, 16#e030#);
+ when 332 => tmpv1 := pm_setup(232, 16#ec40#);
+ when 333 => tmpv1 := pm_setup(233, 16#e450#);
+ when 334 => tmpv1 := pm_setup(234, 16#2d99#);
+ when 335 => tmpv1 := pm_setup(235, 16#2d88#);
+ when 336 => tmpv1 := pm_setup(236, 16#2d77#);
+ when 337 => tmpv1 := pm_setup(237, 16#2d66#);
+ when 338 => tmpv1 := pm_setup(238, 16#940e#);
+ when 339 => tmpv1 := pm_setup(239, 16#030f#);
+ when 340 => tmpv1 := pm_setup(240, 16#2ea6#);
+ when 341 => tmpv1 := pm_setup(241, 16#2eb7#);
+ when 342 => tmpv1 := pm_setup(242, 16#2ec8#);
+ when 343 => tmpv1 := pm_setup(243, 16#2ed9#);
+ when 344 => tmpv1 := pm_setup(244, 16#85ef#);
+ when 345 => tmpv1 := pm_setup(245, 16#89f8#);
+ when 346 => tmpv1 := pm_setup(246, 16#80e4#);
+ when 347 => tmpv1 := pm_setup(247, 16#80f5#);
+ when 348 => tmpv1 := pm_setup(248, 16#8106#);
+ when 349 => tmpv1 := pm_setup(249, 16#8117#);
+ when 350 => tmpv1 := pm_setup(250, 16#a584#);
+ when 351 => tmpv1 := pm_setup(251, 16#a595#);
+ when 352 => tmpv1 := pm_setup(252, 16#a5a6#);
+ when 353 => tmpv1 := pm_setup(253, 16#a5b7#);
+ when 354 => tmpv1 := pm_setup(254, 16#2f28#);
+ when 355 => tmpv1 := pm_setup(255, 16#2f39#);
+ when 356 => tmpv1 := pm_setup(256, 16#2f4a#);
+ when 357 => tmpv1 := pm_setup(257, 16#2f5b#);
+ when 358 => tmpv1 := pm_setup(258, 16#2f91#);
+ when 359 => tmpv1 := pm_setup(259, 16#2f80#);
+ when 360 => tmpv1 := pm_setup(260, 16#2d7f#);
+ when 361 => tmpv1 := pm_setup(261, 16#2d6e#);
+ when 362 => tmpv1 := pm_setup(262, 16#940e#);
+ when 363 => tmpv1 := pm_setup(263, 16#0273#);
+ when 364 => tmpv1 := pm_setup(264, 16#2ee6#);
+ when 365 => tmpv1 := pm_setup(265, 16#2ef7#);
+ when 366 => tmpv1 := pm_setup(266, 16#2f08#);
+ when 367 => tmpv1 := pm_setup(267, 16#2f19#);
+ when 368 => tmpv1 := pm_setup(268, 16#85ef#);
+ when 369 => tmpv1 := pm_setup(269, 16#89f8#);
+ when 370 => tmpv1 := pm_setup(270, 16#8984#);
+ when 371 => tmpv1 := pm_setup(271, 16#8995#);
+ when 372 => tmpv1 := pm_setup(272, 16#89a6#);
+ when 373 => tmpv1 := pm_setup(273, 16#89b7#);
+ when 374 => tmpv1 := pm_setup(274, 16#2f28#);
+ when 375 => tmpv1 := pm_setup(275, 16#2f39#);
+ when 376 => tmpv1 := pm_setup(276, 16#2f4a#);
+ when 377 => tmpv1 := pm_setup(277, 16#2f5b#);
+ when 378 => tmpv1 := pm_setup(278, 16#2f91#);
+ when 379 => tmpv1 := pm_setup(279, 16#2f80#);
+ when 380 => tmpv1 := pm_setup(280, 16#2d7f#);
+ when 381 => tmpv1 := pm_setup(281, 16#2d6e#);
+ when 382 => tmpv1 := pm_setup(282, 16#940e#);
+ when 383 => tmpv1 := pm_setup(283, 16#0273#);
+ when 384 => tmpv1 := pm_setup(284, 16#2ee6#);
+ when 385 => tmpv1 := pm_setup(285, 16#2ef7#);
+ when 386 => tmpv1 := pm_setup(286, 16#2f08#);
+ when 387 => tmpv1 := pm_setup(287, 16#2f19#);
+ when 388 => tmpv1 := pm_setup(288, 16#85ef#);
+ when 389 => tmpv1 := pm_setup(289, 16#89f8#);
+ when 390 => tmpv1 := pm_setup(290, 16#8d84#);
+ when 391 => tmpv1 := pm_setup(291, 16#8d95#);
+ when 392 => tmpv1 := pm_setup(292, 16#8da6#);
+ when 393 => tmpv1 := pm_setup(293, 16#8db7#);
+ when 394 => tmpv1 := pm_setup(294, 16#2f28#);
+ when 395 => tmpv1 := pm_setup(295, 16#2f39#);
+ when 396 => tmpv1 := pm_setup(296, 16#2f4a#);
+ when 397 => tmpv1 := pm_setup(297, 16#2f5b#);
+ when 398 => tmpv1 := pm_setup(298, 16#2f91#);
+ when 399 => tmpv1 := pm_setup(299, 16#2f80#);
+ when 400 => tmpv1 := pm_setup(300, 16#2d7f#);
+ when 401 => tmpv1 := pm_setup(301, 16#2d6e#);
+ when 402 => tmpv1 := pm_setup(302, 16#940e#);
+ when 403 => tmpv1 := pm_setup(303, 16#0273#);
+ when 404 => tmpv1 := pm_setup(304, 16#2fb9#);
+ when 405 => tmpv1 := pm_setup(305, 16#2fa8#);
+ when 406 => tmpv1 := pm_setup(306, 16#2f97#);
+ when 407 => tmpv1 := pm_setup(307, 16#2f86#);
+ when 408 => tmpv1 := pm_setup(308, 16#2f28#);
+ when 409 => tmpv1 := pm_setup(309, 16#2f39#);
+ when 410 => tmpv1 := pm_setup(310, 16#2f4a#);
+ when 411 => tmpv1 := pm_setup(311, 16#2f5b#);
+ when 412 => tmpv1 := pm_setup(312, 16#2d9d#);
+ when 413 => tmpv1 := pm_setup(313, 16#2d8c#);
+ when 414 => tmpv1 := pm_setup(314, 16#2d7b#);
+ when 415 => tmpv1 := pm_setup(315, 16#2d6a#);
+ when 416 => tmpv1 := pm_setup(316, 16#940e#);
+ when 417 => tmpv1 := pm_setup(317, 16#0272#);
+ when 418 => tmpv1 := pm_setup(318, 16#2ea6#);
+ when 419 => tmpv1 := pm_setup(319, 16#2eb7#);
+ when 420 => tmpv1 := pm_setup(320, 16#2ec8#);
+ when 421 => tmpv1 := pm_setup(321, 16#2ed9#);
+ when 422 => tmpv1 := pm_setup(322, 16#85ef#);
+ when 423 => tmpv1 := pm_setup(323, 16#89f8#);
+ when 424 => tmpv1 := pm_setup(324, 16#80e0#);
+ when 425 => tmpv1 := pm_setup(325, 16#80f1#);
+ when 426 => tmpv1 := pm_setup(326, 16#8102#);
+ when 427 => tmpv1 := pm_setup(327, 16#8113#);
+ when 428 => tmpv1 := pm_setup(328, 16#8580#);
+ when 429 => tmpv1 := pm_setup(329, 16#8591#);
+ when 430 => tmpv1 := pm_setup(330, 16#85a2#);
+ when 431 => tmpv1 := pm_setup(331, 16#85b3#);
+ when 432 => tmpv1 := pm_setup(332, 16#2f28#);
+ when 433 => tmpv1 := pm_setup(333, 16#2f39#);
+ when 434 => tmpv1 := pm_setup(334, 16#2f4a#);
+ when 435 => tmpv1 := pm_setup(335, 16#2f5b#);
+ when 436 => tmpv1 := pm_setup(336, 16#2f91#);
+ when 437 => tmpv1 := pm_setup(337, 16#2f80#);
+ when 438 => tmpv1 := pm_setup(338, 16#2d7f#);
+ when 439 => tmpv1 := pm_setup(339, 16#2d6e#);
+ when 440 => tmpv1 := pm_setup(340, 16#940e#);
+ when 441 => tmpv1 := pm_setup(341, 16#0273#);
+ when 442 => tmpv1 := pm_setup(342, 16#2ee6#);
+ when 443 => tmpv1 := pm_setup(343, 16#2ef7#);
+ when 444 => tmpv1 := pm_setup(344, 16#2f08#);
+ when 445 => tmpv1 := pm_setup(345, 16#2f19#);
+ when 446 => tmpv1 := pm_setup(346, 16#85ef#);
+ when 447 => tmpv1 := pm_setup(347, 16#89f8#);
+ when 448 => tmpv1 := pm_setup(348, 16#a580#);
+ when 449 => tmpv1 := pm_setup(349, 16#a591#);
+ when 450 => tmpv1 := pm_setup(350, 16#a5a2#);
+ when 451 => tmpv1 := pm_setup(351, 16#a5b3#);
+ when 452 => tmpv1 := pm_setup(352, 16#2f28#);
+ when 453 => tmpv1 := pm_setup(353, 16#2f39#);
+ when 454 => tmpv1 := pm_setup(354, 16#2f4a#);
+ when 455 => tmpv1 := pm_setup(355, 16#2f5b#);
+ when 456 => tmpv1 := pm_setup(356, 16#2f91#);
+ when 457 => tmpv1 := pm_setup(357, 16#2f80#);
+ when 458 => tmpv1 := pm_setup(358, 16#2d7f#);
+ when 459 => tmpv1 := pm_setup(359, 16#2d6e#);
+ when 460 => tmpv1 := pm_setup(360, 16#940e#);
+ when 461 => tmpv1 := pm_setup(361, 16#0273#);
+ when 462 => tmpv1 := pm_setup(362, 16#2ee6#);
+ when 463 => tmpv1 := pm_setup(363, 16#2ef7#);
+ when 464 => tmpv1 := pm_setup(364, 16#2f08#);
+ when 465 => tmpv1 := pm_setup(365, 16#2f19#);
+ when 466 => tmpv1 := pm_setup(366, 16#85ef#);
+ when 467 => tmpv1 := pm_setup(367, 16#89f8#);
+ when 468 => tmpv1 := pm_setup(368, 16#a980#);
+ when 469 => tmpv1 := pm_setup(369, 16#a991#);
+ when 470 => tmpv1 := pm_setup(370, 16#a9a2#);
+ when 471 => tmpv1 := pm_setup(371, 16#a9b3#);
+ when 472 => tmpv1 := pm_setup(372, 16#2f28#);
+ when 473 => tmpv1 := pm_setup(373, 16#2f39#);
+ when 474 => tmpv1 := pm_setup(374, 16#2f4a#);
+ when 475 => tmpv1 := pm_setup(375, 16#2f5b#);
+ when 476 => tmpv1 := pm_setup(376, 16#2f91#);
+ when 477 => tmpv1 := pm_setup(377, 16#2f80#);
+ when 478 => tmpv1 := pm_setup(378, 16#2d7f#);
+ when 479 => tmpv1 := pm_setup(379, 16#2d6e#);
+ when 480 => tmpv1 := pm_setup(380, 16#940e#);
+ when 481 => tmpv1 := pm_setup(381, 16#0273#);
+ when 482 => tmpv1 := pm_setup(382, 16#2fb9#);
+ when 483 => tmpv1 := pm_setup(383, 16#2fa8#);
+ when 484 => tmpv1 := pm_setup(384, 16#2f97#);
+ when 485 => tmpv1 := pm_setup(385, 16#2f86#);
+ when 486 => tmpv1 := pm_setup(386, 16#e020#);
+ when 487 => tmpv1 := pm_setup(387, 16#e030#);
+ when 488 => tmpv1 := pm_setup(388, 16#e040#);
+ when 489 => tmpv1 := pm_setup(389, 16#e35f#);
+ when 490 => tmpv1 := pm_setup(390, 16#2f68#);
+ when 491 => tmpv1 := pm_setup(391, 16#2f79#);
+ when 492 => tmpv1 := pm_setup(392, 16#2f8a#);
+ when 493 => tmpv1 := pm_setup(393, 16#2f9b#);
+ when 494 => tmpv1 := pm_setup(394, 16#940e#);
+ when 495 => tmpv1 := pm_setup(395, 16#030f#);
+ when 496 => tmpv1 := pm_setup(396, 16#2fb9#);
+ when 497 => tmpv1 := pm_setup(397, 16#2fa8#);
+ when 498 => tmpv1 := pm_setup(398, 16#2f97#);
+ when 499 => tmpv1 := pm_setup(399, 16#2f86#);
+ when 500 => tmpv1 := pm_setup(400, 16#2f28#);
+ when 501 => tmpv1 := pm_setup(401, 16#2f39#);
+ when 502 => tmpv1 := pm_setup(402, 16#2f4a#);
+ when 503 => tmpv1 := pm_setup(403, 16#2f5b#);
+ when 504 => tmpv1 := pm_setup(404, 16#2d9d#);
+ when 505 => tmpv1 := pm_setup(405, 16#2d8c#);
+ when 506 => tmpv1 := pm_setup(406, 16#2d7b#);
+ when 507 => tmpv1 := pm_setup(407, 16#2d6a#);
+ when 508 => tmpv1 := pm_setup(408, 16#940e#);
+ when 509 => tmpv1 := pm_setup(409, 16#0272#);
+ when 510 => tmpv1 := pm_setup(410, 16#2fb9#);
+ when 511 => tmpv1 := pm_setup(411, 16#2fa8#);
+ when 512 => tmpv1 := pm_setup(412, 16#2f97#);
+ when 513 => tmpv1 := pm_setup(413, 16#2f86#);
+ when 514 => tmpv1 := pm_setup(414, 16#e925#);
+ when 515 => tmpv1 := pm_setup(415, 16#e635#);
+ when 516 => tmpv1 := pm_setup(416, 16#e048#);
+ when 517 => tmpv1 := pm_setup(417, 16#e35d#);
+ when 518 => tmpv1 := pm_setup(418, 16#2f68#);
+ when 519 => tmpv1 := pm_setup(419, 16#2f79#);
+ when 520 => tmpv1 := pm_setup(420, 16#2f8a#);
+ when 521 => tmpv1 := pm_setup(421, 16#2f9b#);
+ when 522 => tmpv1 := pm_setup(422, 16#940e#);
+ when 523 => tmpv1 := pm_setup(423, 16#030f#);
+ when 524 => tmpv1 := pm_setup(424, 16#2fb9#);
+ when 525 => tmpv1 := pm_setup(425, 16#2fa8#);
+ when 526 => tmpv1 := pm_setup(426, 16#2f97#);
+ when 527 => tmpv1 := pm_setup(427, 16#2f86#);
+ when 528 => tmpv1 := pm_setup(428, 16#2f28#);
+ when 529 => tmpv1 := pm_setup(429, 16#2f39#);
+ when 530 => tmpv1 := pm_setup(430, 16#2f4a#);
+ when 531 => tmpv1 := pm_setup(431, 16#2f5b#);
+ when 532 => tmpv1 := pm_setup(432, 16#2d95#);
+ when 533 => tmpv1 := pm_setup(433, 16#2d84#);
+ when 534 => tmpv1 := pm_setup(434, 16#2d73#);
+ when 535 => tmpv1 := pm_setup(435, 16#2d62#);
+ when 536 => tmpv1 := pm_setup(436, 16#940e#);
+ when 537 => tmpv1 := pm_setup(437, 16#0272#);
+ when 538 => tmpv1 := pm_setup(438, 16#2fb9#);
+ when 539 => tmpv1 := pm_setup(439, 16#2fa8#);
+ when 540 => tmpv1 := pm_setup(440, 16#2f97#);
+ when 541 => tmpv1 := pm_setup(441, 16#2f86#);
+ when 542 => tmpv1 := pm_setup(442, 16#85eb#);
+ when 543 => tmpv1 := pm_setup(443, 16#85fc#);
+ when 544 => tmpv1 := pm_setup(444, 16#8380#);
+ when 545 => tmpv1 := pm_setup(445, 16#8391#);
+ when 546 => tmpv1 := pm_setup(446, 16#83a2#);
+ when 547 => tmpv1 := pm_setup(447, 16#83b3#);
+ when 548 => tmpv1 := pm_setup(448, 16#2f28#);
+ when 549 => tmpv1 := pm_setup(449, 16#2f39#);
+ when 550 => tmpv1 := pm_setup(450, 16#2f4a#);
+ when 551 => tmpv1 := pm_setup(451, 16#2f5b#);
+ when 552 => tmpv1 := pm_setup(452, 16#2d99#);
+ when 553 => tmpv1 := pm_setup(453, 16#2d88#);
+ when 554 => tmpv1 := pm_setup(454, 16#2d77#);
+ when 555 => tmpv1 := pm_setup(455, 16#2d66#);
+ when 556 => tmpv1 := pm_setup(456, 16#940e#);
+ when 557 => tmpv1 := pm_setup(457, 16#0273#);
+ when 558 => tmpv1 := pm_setup(458, 16#2fb9#);
+ when 559 => tmpv1 := pm_setup(459, 16#2fa8#);
+ when 560 => tmpv1 := pm_setup(460, 16#2f97#);
+ when 561 => tmpv1 := pm_setup(461, 16#2f86#);
+ when 562 => tmpv1 := pm_setup(462, 16#85ef#);
+ when 563 => tmpv1 := pm_setup(463, 16#89f8#);
+ when 564 => tmpv1 := pm_setup(464, 16#8f80#);
+ when 565 => tmpv1 := pm_setup(465, 16#8f91#);
+ when 566 => tmpv1 := pm_setup(466, 16#8fa2#);
+ when 567 => tmpv1 := pm_setup(467, 16#8fb3#);
+ when 568 => tmpv1 := pm_setup(468, 16#852f#);
+ when 569 => tmpv1 := pm_setup(469, 16#8938#);
+ when 570 => tmpv1 := pm_setup(470, 16#5f2c#);
+ when 571 => tmpv1 := pm_setup(471, 16#4f3f#);
+ when 572 => tmpv1 := pm_setup(472, 16#872f#);
+ when 573 => tmpv1 := pm_setup(473, 16#8b38#);
+ when 574 => tmpv1 := pm_setup(474, 16#858b#);
+ when 575 => tmpv1 := pm_setup(475, 16#859c#);
+ when 576 => tmpv1 := pm_setup(476, 16#9604#);
+ when 577 => tmpv1 := pm_setup(477, 16#878b#);
+ when 578 => tmpv1 := pm_setup(478, 16#879c#);
+ when 579 => tmpv1 := pm_setup(479, 16#85ed#);
+ when 580 => tmpv1 := pm_setup(480, 16#85fe#);
+ when 581 => tmpv1 := pm_setup(481, 16#9634#);
+ when 582 => tmpv1 := pm_setup(482, 16#87ed#);
+ when 583 => tmpv1 := pm_setup(483, 16#87fe#);
+ when 584 => tmpv1 := pm_setup(484, 16#812b#);
+ when 585 => tmpv1 := pm_setup(485, 16#813c#);
+ when 586 => tmpv1 := pm_setup(486, 16#5f2f#);
+ when 587 => tmpv1 := pm_setup(487, 16#4f3f#);
+ when 588 => tmpv1 := pm_setup(488, 16#832b#);
+ when 589 => tmpv1 := pm_setup(489, 16#833c#);
+ when 590 => tmpv1 := pm_setup(490, 16#3025#);
+ when 591 => tmpv1 := pm_setup(491, 16#0531#);
+ when 592 => tmpv1 := pm_setup(492, 16#f40c#);
+ when 593 => tmpv1 := pm_setup(493, 16#cecc#);
+ when 594 => tmpv1 := pm_setup(494, 16#818f#);
+ when 595 => tmpv1 := pm_setup(495, 16#8598#);
+ when 596 => tmpv1 := pm_setup(496, 16#9605#);
+ when 597 => tmpv1 := pm_setup(497, 16#838f#);
+ when 598 => tmpv1 := pm_setup(498, 16#8798#);
+ when 599 => tmpv1 := pm_setup(499, 16#85e9#);
+ when 600 => tmpv1 := pm_setup(500, 16#85fa#);
+ when 601 => tmpv1 := pm_setup(501, 16#9635#);
+ when 602 => tmpv1 := pm_setup(502, 16#87e9#);
+ when 603 => tmpv1 := pm_setup(503, 16#87fa#);
+ when 604 => tmpv1 := pm_setup(504, 16#8129#);
+ when 605 => tmpv1 := pm_setup(505, 16#813a#);
+ when 606 => tmpv1 := pm_setup(506, 16#5f2f#);
+ when 607 => tmpv1 := pm_setup(507, 16#4f3f#);
+ when 608 => tmpv1 := pm_setup(508, 16#8329#);
+ when 609 => tmpv1 := pm_setup(509, 16#833a#);
+ when 610 => tmpv1 := pm_setup(510, 16#3025#);
+ when 611 => tmpv1 := pm_setup(511, 16#0531#);
+ when 612 => tmpv1 := pm_setup(512, 16#f40c#);
+ when 613 => tmpv1 := pm_setup(513, 16#ce9c#);
+ when 614 => tmpv1 := pm_setup(514, 16#818d#);
+ when 615 => tmpv1 := pm_setup(515, 16#819e#);
+ when 616 => tmpv1 := pm_setup(516, 16#9601#);
+ when 617 => tmpv1 := pm_setup(517, 16#838d#);
+ when 618 => tmpv1 := pm_setup(518, 16#839e#);
+ when 619 => tmpv1 := pm_setup(519, 16#9705#);
+ when 620 => tmpv1 := pm_setup(520, 16#f40c#);
+ when 621 => tmpv1 := pm_setup(521, 16#ce8c#);
+ when 622 => tmpv1 := pm_setup(522, 16#8219#);
+ when 623 => tmpv1 := pm_setup(523, 16#821a#);
+ when 624 => tmpv1 := pm_setup(524, 16#24ee#);
+ when 625 => tmpv1 := pm_setup(525, 16#24ff#);
+ when 626 => tmpv1 := pm_setup(526, 16#821b#);
+ when 627 => tmpv1 := pm_setup(527, 16#821c#);
+ when 628 => tmpv1 := pm_setup(528, 16#2d1f#);
+ when 629 => tmpv1 := pm_setup(529, 16#2d0e#);
+ when 630 => tmpv1 := pm_setup(530, 16#5c08#);
+ when 631 => tmpv1 := pm_setup(531, 16#4f1e#);
+ when 632 => tmpv1 := pm_setup(532, 16#2cce#);
+ when 633 => tmpv1 := pm_setup(533, 16#2cdf#);
+ when 634 => tmpv1 := pm_setup(534, 16#0ccc#);
+ when 635 => tmpv1 := pm_setup(535, 16#1cdd#);
+ when 636 => tmpv1 := pm_setup(536, 16#0ccc#);
+ when 637 => tmpv1 := pm_setup(537, 16#1cdd#);
+ when 638 => tmpv1 := pm_setup(538, 16#e6e0#);
+ when 639 => tmpv1 := pm_setup(539, 16#e0f0#);
+ when 640 => tmpv1 := pm_setup(540, 16#0ece#);
+ when 641 => tmpv1 := pm_setup(541, 16#1edf#);
+ when 642 => tmpv1 := pm_setup(542, 16#2dfd#);
+ when 643 => tmpv1 := pm_setup(543, 16#2dec#);
+ when 644 => tmpv1 := pm_setup(544, 16#9181#);
+ when 645 => tmpv1 := pm_setup(545, 16#9191#);
+ when 646 => tmpv1 := pm_setup(546, 16#91a1#);
+ when 647 => tmpv1 := pm_setup(547, 16#91b1#);
+ when 648 => tmpv1 := pm_setup(548, 16#2ece#);
+ when 649 => tmpv1 := pm_setup(549, 16#2edf#);
+ when 650 => tmpv1 := pm_setup(550, 16#e020#);
+ when 651 => tmpv1 := pm_setup(551, 16#e030#);
+ when 652 => tmpv1 := pm_setup(552, 16#e040#);
+ when 653 => tmpv1 := pm_setup(553, 16#e453#);
+ when 654 => tmpv1 := pm_setup(554, 16#2f68#);
+ when 655 => tmpv1 := pm_setup(555, 16#2f79#);
+ when 656 => tmpv1 := pm_setup(556, 16#2f8a#);
+ when 657 => tmpv1 := pm_setup(557, 16#2f9b#);
+ when 658 => tmpv1 := pm_setup(558, 16#940e#);
+ when 659 => tmpv1 := pm_setup(559, 16#030f#);
+ when 660 => tmpv1 := pm_setup(560, 16#2fb9#);
+ when 661 => tmpv1 := pm_setup(561, 16#2fa8#);
+ when 662 => tmpv1 := pm_setup(562, 16#2f97#);
+ when 663 => tmpv1 := pm_setup(563, 16#2f86#);
+ when 664 => tmpv1 := pm_setup(564, 16#2f68#);
+ when 665 => tmpv1 := pm_setup(565, 16#2f79#);
+ when 666 => tmpv1 := pm_setup(566, 16#2f8a#);
+ when 667 => tmpv1 := pm_setup(567, 16#2f9b#);
+ when 668 => tmpv1 := pm_setup(568, 16#940e#);
+ when 669 => tmpv1 := pm_setup(569, 16#02b5#);
+ when 670 => tmpv1 := pm_setup(570, 16#2fb9#);
+ when 671 => tmpv1 := pm_setup(571, 16#2fa8#);
+ when 672 => tmpv1 := pm_setup(572, 16#2f97#);
+ when 673 => tmpv1 := pm_setup(573, 16#2f86#);
+ when 674 => tmpv1 := pm_setup(574, 16#2ff1#);
+ when 675 => tmpv1 := pm_setup(575, 16#2fe0#);
+ when 676 => tmpv1 := pm_setup(576, 16#9381#);
+ when 677 => tmpv1 := pm_setup(577, 16#2f0e#);
+ when 678 => tmpv1 := pm_setup(578, 16#2f1f#);
+ when 679 => tmpv1 := pm_setup(579, 16#812b#);
+ when 680 => tmpv1 := pm_setup(580, 16#813c#);
+ when 681 => tmpv1 := pm_setup(581, 16#5f2f#);
+ when 682 => tmpv1 := pm_setup(582, 16#4f3f#);
+ when 683 => tmpv1 := pm_setup(583, 16#832b#);
+ when 684 => tmpv1 := pm_setup(584, 16#833c#);
+ when 685 => tmpv1 := pm_setup(585, 16#3025#);
+ when 686 => tmpv1 := pm_setup(586, 16#0531#);
+ when 687 => tmpv1 := pm_setup(587, 16#f294#);
+ when 688 => tmpv1 := pm_setup(588, 16#e085#);
+ when 689 => tmpv1 := pm_setup(589, 16#e090#);
+ when 690 => tmpv1 := pm_setup(590, 16#0ee8#);
+ when 691 => tmpv1 := pm_setup(591, 16#1ef9#);
+ when 692 => tmpv1 := pm_setup(592, 16#81e9#);
+ when 693 => tmpv1 := pm_setup(593, 16#81fa#);
+ when 694 => tmpv1 := pm_setup(594, 16#9631#);
+ when 695 => tmpv1 := pm_setup(595, 16#83e9#);
+ when 696 => tmpv1 := pm_setup(596, 16#83fa#);
+ when 697 => tmpv1 := pm_setup(597, 16#9735#);
+ when 698 => tmpv1 := pm_setup(598, 16#f40c#);
+ when 699 => tmpv1 := pm_setup(599, 16#cfb6#);
+ when 700 => tmpv1 := pm_setup(600, 16#cfff#);
+ when 701 => tmpv1 := pm_setup(601, 16#852d#);
+ when 702 => tmpv1 := pm_setup(602, 16#853e#);
+ when 703 => tmpv1 := pm_setup(603, 16#5a20#);
+ when 704 => tmpv1 := pm_setup(604, 16#4f3f#);
+ when 705 => tmpv1 := pm_setup(605, 16#e080#);
+ when 706 => tmpv1 := pm_setup(606, 16#e090#);
+ when 707 => tmpv1 := pm_setup(607, 16#e0a0#);
+ when 708 => tmpv1 := pm_setup(608, 16#e0b0#);
+ when 709 => tmpv1 := pm_setup(609, 16#2ff3#);
+ when 710 => tmpv1 := pm_setup(610, 16#2fe2#);
+ when 711 => tmpv1 := pm_setup(611, 16#8380#);
+ when 712 => tmpv1 := pm_setup(612, 16#8391#);
+ when 713 => tmpv1 := pm_setup(613, 16#83a2#);
+ when 714 => tmpv1 := pm_setup(614, 16#83b3#);
+ when 715 => tmpv1 := pm_setup(615, 16#852d#);
+ when 716 => tmpv1 := pm_setup(616, 16#853e#);
+ when 717 => tmpv1 := pm_setup(617, 16#532c#);
+ when 718 => tmpv1 := pm_setup(618, 16#4f3f#);
+ when 719 => tmpv1 := pm_setup(619, 16#2ff3#);
+ when 720 => tmpv1 := pm_setup(620, 16#2fe2#);
+ when 721 => tmpv1 := pm_setup(621, 16#8380#);
+ when 722 => tmpv1 := pm_setup(622, 16#8391#);
+ when 723 => tmpv1 := pm_setup(623, 16#83a2#);
+ when 724 => tmpv1 := pm_setup(624, 16#83b3#);
+ when 725 => tmpv1 := pm_setup(625, 16#cf62#);
+ when 726 => tmpv1 := pm_setup(626, 16#5850#);
+ when 727 => tmpv1 := pm_setup(627, 16#2e19#);
+ when 728 => tmpv1 := pm_setup(628, 16#d078#);
+ when 729 => tmpv1 := pm_setup(629, 16#d001#);
+ when 730 => tmpv1 := pm_setup(630, 16#c05e#);
+ when 731 => tmpv1 := pm_setup(631, 16#17ba#);
+ when 732 => tmpv1 := pm_setup(632, 16#0762#);
+ when 733 => tmpv1 := pm_setup(633, 16#0773#);
+ when 734 => tmpv1 := pm_setup(634, 16#0784#);
+ when 735 => tmpv1 := pm_setup(635, 16#0795#);
+ when 736 => tmpv1 := pm_setup(636, 16#f1b1#);
+ when 737 => tmpv1 := pm_setup(637, 16#f488#);
+ when 738 => tmpv1 := pm_setup(638, 16#f40e#);
+ when 739 => tmpv1 := pm_setup(639, 16#9410#);
+ when 740 => tmpv1 := pm_setup(640, 16#2e0b#);
+ when 741 => tmpv1 := pm_setup(641, 16#2fba#);
+ when 742 => tmpv1 := pm_setup(642, 16#2da0#);
+ when 743 => tmpv1 := pm_setup(643, 16#2e06#);
+ when 744 => tmpv1 := pm_setup(644, 16#2f62#);
+ when 745 => tmpv1 := pm_setup(645, 16#2d20#);
+ when 746 => tmpv1 := pm_setup(646, 16#2e07#);
+ when 747 => tmpv1 := pm_setup(647, 16#2f73#);
+ when 748 => tmpv1 := pm_setup(648, 16#2d30#);
+ when 749 => tmpv1 := pm_setup(649, 16#2e08#);
+ when 750 => tmpv1 := pm_setup(650, 16#2f84#);
+ when 751 => tmpv1 := pm_setup(651, 16#2d40#);
+ when 752 => tmpv1 := pm_setup(652, 16#2e09#);
+ when 753 => tmpv1 := pm_setup(653, 16#2f95#);
+ when 754 => tmpv1 := pm_setup(654, 16#2d50#);
+ when 755 => tmpv1 := pm_setup(655, 16#27ff#);
+ when 756 => tmpv1 := pm_setup(656, 16#2355#);
+ when 757 => tmpv1 := pm_setup(657, 16#f0b9#);
+ when 758 => tmpv1 := pm_setup(658, 16#1b59#);
+ when 759 => tmpv1 := pm_setup(659, 16#f049#);
+ when 760 => tmpv1 := pm_setup(660, 16#3e57#);
+ when 761 => tmpv1 := pm_setup(661, 16#f098#);
+ when 762 => tmpv1 := pm_setup(662, 16#9546#);
+ when 763 => tmpv1 := pm_setup(663, 16#9537#);
+ when 764 => tmpv1 := pm_setup(664, 16#9527#);
+ when 765 => tmpv1 := pm_setup(665, 16#95a7#);
+ when 766 => tmpv1 := pm_setup(666, 16#40f0#);
+ when 767 => tmpv1 := pm_setup(667, 16#9553#);
+ when 768 => tmpv1 := pm_setup(668, 16#f7c9#);
+ when 769 => tmpv1 := pm_setup(669, 16#f076#);
+ when 770 => tmpv1 := pm_setup(670, 16#0fba#);
+ when 771 => tmpv1 := pm_setup(671, 16#1f62#);
+ when 772 => tmpv1 := pm_setup(672, 16#1f73#);
+ when 773 => tmpv1 := pm_setup(673, 16#1f84#);
+ when 774 => tmpv1 := pm_setup(674, 16#f430#);
+ when 775 => tmpv1 := pm_setup(675, 16#9587#);
+ when 776 => tmpv1 := pm_setup(676, 16#9577#);
+ when 777 => tmpv1 := pm_setup(677, 16#9567#);
+ when 778 => tmpv1 := pm_setup(678, 16#95b7#);
+ when 779 => tmpv1 := pm_setup(679, 16#40f0#);
+ when 780 => tmpv1 := pm_setup(680, 16#9593#);
+ when 781 => tmpv1 := pm_setup(681, 16#fa17#);
+ when 782 => tmpv1 := pm_setup(682, 16#2e0f#);
+ when 783 => tmpv1 := pm_setup(683, 16#9508#);
+ when 784 => tmpv1 := pm_setup(684, 16#1bbf#);
+ when 785 => tmpv1 := pm_setup(685, 16#27bb#);
+ when 786 => tmpv1 := pm_setup(686, 16#0bba#);
+ when 787 => tmpv1 := pm_setup(687, 16#0b62#);
+ when 788 => tmpv1 := pm_setup(688, 16#0b73#);
+ when 789 => tmpv1 := pm_setup(689, 16#0b84#);
+ when 790 => tmpv1 := pm_setup(690, 16#cff6#);
+ when 791 => tmpv1 := pm_setup(691, 16#f6de#);
+ when 792 => tmpv1 := pm_setup(692, 16#c054#);
+ when 793 => tmpv1 := pm_setup(693, 16#fb97#);
+ when 794 => tmpv1 := pm_setup(694, 16#d042#);
+ when 795 => tmpv1 := pm_setup(695, 16#379f#);
+ when 796 => tmpv1 := pm_setup(696, 16#f038#);
+ when 797 => tmpv1 := pm_setup(697, 16#e9fe#);
+ when 798 => tmpv1 := pm_setup(698, 16#1bf9#);
+ when 799 => tmpv1 := pm_setup(699, 16#2f98#);
+ when 800 => tmpv1 := pm_setup(700, 16#2f87#);
+ when 801 => tmpv1 := pm_setup(701, 16#2f76#);
+ when 802 => tmpv1 := pm_setup(702, 16#2f6b#);
+ when 803 => tmpv1 := pm_setup(703, 16#c005#);
+ when 804 => tmpv1 := pm_setup(704, 16#c045#);
+ when 805 => tmpv1 := pm_setup(705, 16#9596#);
+ when 806 => tmpv1 := pm_setup(706, 16#9587#);
+ when 807 => tmpv1 := pm_setup(707, 16#9577#);
+ when 808 => tmpv1 := pm_setup(708, 16#9567#);
+ when 809 => tmpv1 := pm_setup(709, 16#50f1#);
+ when 810 => tmpv1 := pm_setup(710, 16#f7d0#);
+ when 811 => tmpv1 := pm_setup(711, 16#f43e#);
+ when 812 => tmpv1 := pm_setup(712, 16#9590#);
+ when 813 => tmpv1 := pm_setup(713, 16#9580#);
+ when 814 => tmpv1 := pm_setup(714, 16#9570#);
+ when 815 => tmpv1 := pm_setup(715, 16#9561#);
+ when 816 => tmpv1 := pm_setup(716, 16#4f7f#);
+ when 817 => tmpv1 := pm_setup(717, 16#4f8f#);
+ when 818 => tmpv1 := pm_setup(718, 16#4f9f#);
+ when 819 => tmpv1 := pm_setup(719, 16#9508#);
+ when 820 => tmpv1 := pm_setup(720, 16#959a#);
+ when 821 => tmpv1 := pm_setup(721, 16#0fbb#);
+ when 822 => tmpv1 := pm_setup(722, 16#1f66#);
+ when 823 => tmpv1 := pm_setup(723, 16#1f77#);
+ when 824 => tmpv1 := pm_setup(724, 16#1f88#);
+ when 825 => tmpv1 := pm_setup(725, 16#2411#);
+ when 826 => tmpv1 := pm_setup(726, 16#2399#);
+ when 827 => tmpv1 := pm_setup(727, 16#f0a1#);
+ when 828 => tmpv1 := pm_setup(728, 16#2388#);
+ when 829 => tmpv1 := pm_setup(729, 16#f7b2#);
+ when 830 => tmpv1 := pm_setup(730, 16#3f9f#);
+ when 831 => tmpv1 := pm_setup(731, 16#f059#);
+ when 832 => tmpv1 := pm_setup(732, 16#0fbb#);
+ when 833 => tmpv1 := pm_setup(733, 16#f448#);
+ when 834 => tmpv1 := pm_setup(734, 16#f421#);
+ when 835 => tmpv1 := pm_setup(735, 16#2000#);
+ when 836 => tmpv1 := pm_setup(736, 16#f411#);
+ when 837 => tmpv1 := pm_setup(737, 16#ff60#);
+ when 838 => tmpv1 := pm_setup(738, 16#c004#);
+ when 839 => tmpv1 := pm_setup(739, 16#5f6f#);
+ when 840 => tmpv1 := pm_setup(740, 16#4f7f#);
+ when 841 => tmpv1 := pm_setup(741, 16#4f8f#);
+ when 842 => tmpv1 := pm_setup(742, 16#4f9f#);
+ when 843 => tmpv1 := pm_setup(743, 16#1f88#);
+ when 844 => tmpv1 := pm_setup(744, 16#9597#);
+ when 845 => tmpv1 := pm_setup(745, 16#9587#);
+ when 846 => tmpv1 := pm_setup(746, 16#f997#);
+ when 847 => tmpv1 := pm_setup(747, 16#9508#);
+ when 848 => tmpv1 := pm_setup(748, 16#c019#);
+ when 849 => tmpv1 := pm_setup(749, 16#2e05#);
+ when 850 => tmpv1 := pm_setup(750, 16#2609#);
+ when 851 => tmpv1 := pm_setup(751, 16#fa07#);
+ when 852 => tmpv1 := pm_setup(752, 16#0f44#);
+ when 853 => tmpv1 := pm_setup(753, 16#1f55#);
+ when 854 => tmpv1 := pm_setup(754, 16#3f5f#);
+ when 855 => tmpv1 := pm_setup(755, 16#f079#);
+ when 856 => tmpv1 := pm_setup(756, 16#27aa#);
+ when 857 => tmpv1 := pm_setup(757, 16#17a5#);
+ when 858 => tmpv1 := pm_setup(758, 16#f008#);
+ when 859 => tmpv1 := pm_setup(759, 16#e051#);
+ when 860 => tmpv1 := pm_setup(760, 16#9547#);
+ when 861 => tmpv1 := pm_setup(761, 16#0f88#);
+ when 862 => tmpv1 := pm_setup(762, 16#1f99#);
+ when 863 => tmpv1 := pm_setup(763, 16#3f9f#);
+ when 864 => tmpv1 := pm_setup(764, 16#f031#);
+ when 865 => tmpv1 := pm_setup(765, 16#27bb#);
+ when 866 => tmpv1 := pm_setup(766, 16#17b9#);
+ when 867 => tmpv1 := pm_setup(767, 16#f008#);
+ when 868 => tmpv1 := pm_setup(768, 16#e091#);
+ when 869 => tmpv1 := pm_setup(769, 16#9587#);
+ when 870 => tmpv1 := pm_setup(770, 16#9508#);
+ when 871 => tmpv1 := pm_setup(771, 16#919f#);
+ when 872 => tmpv1 := pm_setup(772, 16#919f#);
+ when 873 => tmpv1 := pm_setup(773, 16#c057#);
+ when 874 => tmpv1 := pm_setup(774, 16#2766#);
+ when 875 => tmpv1 := pm_setup(775, 16#2777#);
+ when 876 => tmpv1 := pm_setup(776, 16#2788#);
+ when 877 => tmpv1 := pm_setup(777, 16#2799#);
+ when 878 => tmpv1 := pm_setup(778, 16#9508#);
+ when 879 => tmpv1 := pm_setup(779, 16#2f59#);
+ when 880 => tmpv1 := pm_setup(780, 16#2f48#);
+ when 881 => tmpv1 := pm_setup(781, 16#2f37#);
+ when 882 => tmpv1 := pm_setup(782, 16#2f26#);
+ when 883 => tmpv1 := pm_setup(783, 16#dfdd#);
+ when 884 => tmpv1 := pm_setup(784, 16#d001#);
+ when 885 => tmpv1 := pm_setup(785, 16#cfc3#);
+ when 886 => tmpv1 := pm_setup(786, 16#2399#);
+ when 887 => tmpv1 := pm_setup(787, 16#f039#);
+ when 888 => tmpv1 := pm_setup(788, 16#2355#);
+ when 889 => tmpv1 := pm_setup(789, 16#f029#);
+ when 890 => tmpv1 := pm_setup(790, 16#579f#);
+ when 891 => tmpv1 := pm_setup(791, 16#575f#);
+ when 892 => tmpv1 := pm_setup(792, 16#0f95#);
+ when 893 => tmpv1 := pm_setup(793, 16#f413#);
+ when 894 => tmpv1 := pm_setup(794, 16#f1ca#);
+ when 895 => tmpv1 := pm_setup(795, 16#cfed#);
+ when 896 => tmpv1 := pm_setup(796, 16#5891#);
+ when 897 => tmpv1 := pm_setup(797, 16#3f9f#);
+ when 898 => tmpv1 := pm_setup(798, 16#f3e1#);
+ when 899 => tmpv1 := pm_setup(799, 16#2fa6#);
+ when 900 => tmpv1 := pm_setup(800, 16#2400#);
+ when 901 => tmpv1 := pm_setup(801, 16#2411#);
+ when 902 => tmpv1 := pm_setup(802, 16#27bb#);
+ when 903 => tmpv1 := pm_setup(803, 16#2766#);
+ when 904 => tmpv1 := pm_setup(804, 16#2755#);
+ when 905 => tmpv1 := pm_setup(805, 16#e0f8#);
+ when 906 => tmpv1 := pm_setup(806, 16#95a6#);
+ when 907 => tmpv1 := pm_setup(807, 16#f420#);
+ when 908 => tmpv1 := pm_setup(808, 16#0e02#);
+ when 909 => tmpv1 := pm_setup(809, 16#1e13#);
+ when 910 => tmpv1 := pm_setup(810, 16#1fb4#);
+ when 911 => tmpv1 := pm_setup(811, 16#1f65#);
+ when 912 => tmpv1 := pm_setup(812, 16#0f22#);
+ when 913 => tmpv1 := pm_setup(813, 16#1f33#);
+ when 914 => tmpv1 := pm_setup(814, 16#1f44#);
+ when 915 => tmpv1 := pm_setup(815, 16#1f55#);
+ when 916 => tmpv1 := pm_setup(816, 16#95fa#);
+ when 917 => tmpv1 := pm_setup(817, 16#f7a1#);
+ when 918 => tmpv1 := pm_setup(818, 16#e0f8#);
+ when 919 => tmpv1 := pm_setup(819, 16#2fe7#);
+ when 920 => tmpv1 := pm_setup(820, 16#2777#);
+ when 921 => tmpv1 := pm_setup(821, 16#e0f8#);
+ when 922 => tmpv1 := pm_setup(822, 16#95e6#);
+ when 923 => tmpv1 := pm_setup(823, 16#f420#);
+ when 924 => tmpv1 := pm_setup(824, 16#0e13#);
+ when 925 => tmpv1 := pm_setup(825, 16#1fb4#);
+ when 926 => tmpv1 := pm_setup(826, 16#1f65#);
+ when 927 => tmpv1 := pm_setup(827, 16#1f7a#);
+ when 928 => tmpv1 := pm_setup(828, 16#0f33#);
+ when 929 => tmpv1 := pm_setup(829, 16#1f44#);
+ when 930 => tmpv1 := pm_setup(830, 16#1f55#);
+ when 931 => tmpv1 := pm_setup(831, 16#1faa#);
+ when 932 => tmpv1 := pm_setup(832, 16#95fa#);
+ when 933 => tmpv1 := pm_setup(833, 16#f7a1#);
+ when 934 => tmpv1 := pm_setup(834, 16#2ff8#);
+ when 935 => tmpv1 := pm_setup(835, 16#2788#);
+ when 936 => tmpv1 := pm_setup(836, 16#95f6#);
+ when 937 => tmpv1 := pm_setup(837, 16#f420#);
+ when 938 => tmpv1 := pm_setup(838, 16#0fb4#);
+ when 939 => tmpv1 := pm_setup(839, 16#1f65#);
+ when 940 => tmpv1 := pm_setup(840, 16#1f7a#);
+ when 941 => tmpv1 := pm_setup(841, 16#1f8e#);
+ when 942 => tmpv1 := pm_setup(842, 16#0f44#);
+ when 943 => tmpv1 := pm_setup(843, 16#1f55#);
+ when 944 => tmpv1 := pm_setup(844, 16#1faa#);
+ when 945 => tmpv1 := pm_setup(845, 16#1fee#);
+ when 946 => tmpv1 := pm_setup(846, 16#23ff#);
+ when 947 => tmpv1 := pm_setup(847, 16#f7a1#);
+ when 948 => tmpv1 := pm_setup(848, 16#2388#);
+ when 949 => tmpv1 := pm_setup(849, 16#f41a#);
+ when 950 => tmpv1 := pm_setup(850, 16#9593#);
+ when 951 => tmpv1 := pm_setup(851, 16#f439#);
+ when 952 => tmpv1 := pm_setup(852, 16#c008#);
+ when 953 => tmpv1 := pm_setup(853, 16#0c00#);
+ when 954 => tmpv1 := pm_setup(854, 16#1c11#);
+ when 955 => tmpv1 := pm_setup(855, 16#1fbb#);
+ when 956 => tmpv1 := pm_setup(856, 16#1f66#);
+ when 957 => tmpv1 := pm_setup(857, 16#1f77#);
+ when 958 => tmpv1 := pm_setup(858, 16#1f88#);
+ when 959 => tmpv1 := pm_setup(859, 16#2801#);
+ when 960 => tmpv1 := pm_setup(860, 16#9508#);
+ when 961 => tmpv1 := pm_setup(861, 16#ef9f#);
+ when 962 => tmpv1 := pm_setup(862, 16#ec80#);
+ when 963 => tmpv1 := pm_setup(863, 16#9508#);
+--
+
+ when others =>
+ null;
+ end case;
+ pm_sel <= pm_sel_usr;
+ pm_wr <= '1';
+ pm_addr <= tmpv1(tmpv1'length-1 downto 16);
+ pm_di <= tmpv1(15 downto 0);
+ -- Keep the controller in reset state until the Program Memory is prepared.
+ pavr_pavr_res <= '1';
+ pavr_pavr_syncres <= '1';
+ else
+ pm_sel <= pm_sel_pavr;
+ pm_wr <= '0';
+ pm_addr <= int_to_std_logic_vector(0, pm_addr'length);
+ pm_di <= int_to_std_logic_vector(0, pm_di'length);
+ -- Now the Program Memory is prepared. Free the beast.
+ pavr_pavr_res <= '0';
+ pavr_pavr_syncres <= '0';
+ end if;
+
+ if pavr_pavr_res='1' or pavr_pavr_syncres='1' then
+ instr_cnt <= int_to_std_logic_vector(0, instr_cnt'length);
+ run_clk_cnt <= int_to_std_logic_vector(0, run_clk_cnt'length);
+ end if;
+
+ if syncres='1' then
+ -- Sync reset
+
+ -- Reset the controller in turn.
+ pavr_pavr_syncres <= '1';
+
+ main_clk_cnt <= int_to_std_logic_vector(0, main_clk_cnt'length);
+ run_clk_cnt <= int_to_std_logic_vector(0, run_clk_cnt'length);
+ instr_cnt <= int_to_std_logic_vector(0, instr_cnt'length);
+ end if;
+ end if;
+ end process test_main;
+
+
+ -- Connect components.
+ select_muxers:
+ process(pavr_pavr_pm_addr, pm_addr, pm_sel)
+ begin
+ if pm_sel=pm_sel_pavr then
+ pm_pavr_pm_addr <= pavr_pavr_pm_addr;
+ else
+ pm_pavr_pm_addr <= pm_addr;
+ end if;
+ end process select_muxers;
+ pm_pavr_pm_wr <= pm_wr;
+ pm_pavr_pm_di <= pm_di;
+ pavr_pavr_pm_do <= pm_pavr_pm_do;
+
+end;
+--
Index: group__pavr__hwres__iof.html
===================================================================
--- group__pavr__hwres__iof.html (nonexistent)
+++ group__pavr__hwres__iof.html (revision 6)
@@ -0,0 +1,41 @@
+
+
+IO File
+
+
+
+
+Main Page Modules Related Pages
+
IO File
+
+
+
+
+ Each IO File register is assigned a unique address in the IO space. That address is defined in the in the constants definition file (`pavr-constants.vhd').
+ The IO space is placed in the Unified Memory just above the RF, that is, starting with address 32.
+ The IO addressing space range is 0...63 (Unified Memory addresses 32...95).
+ Undefined IO registers will read an undefined value.
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__implementation.html
===================================================================
--- group__pavr__implementation.html (nonexistent)
+++ group__pavr__implementation.html (revision 6)
@@ -0,0 +1,20 @@
+
+
+Implementation
+
+
+
+
+Main Page Modules Related Pages
+
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_pipestruct_02.gif
===================================================================
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Index: pavr_pipestruct_02.gif
===================================================================
--- pavr_pipestruct_02.gif (nonexistent)
+++ pavr_pipestruct_02.gif (revision 6)
IO File
+
+[Hardware resources]
+
Modules | |
| General IO port | |
| SREG port | |
| SP port | |
| RAMPX port | |
| RAMPY port | |
| RAMPZ port | |
| RAMPD port | |
| EIND port | |
| Peripherals | |
Detailed Description
+The IO File is composed of a set of discrete registers, that are grouped into a memory-like entity. The IO File has a general write/read port that is byte-oriented, and separate read and write ports for each register in the IO File.+
+
+
+
+
++ Each IO File register is assigned a unique address in the IO space. That address is defined in the in the constants definition file (`pavr-constants.vhd').
+ The IO space is placed in the Unified Memory just above the RF, that is, starting with address 32.
+ The IO addressing space range is 0...63 (Unified Memory addresses 32...95).
+ Undefined IO registers will read an undefined value.
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__implementation.html
===================================================================
--- group__pavr__implementation.html (nonexistent)
+++ group__pavr__implementation.html (revision 6)
@@ -0,0 +1,20 @@
+
+
+Implementation
Modules | |
| Pipeline structure | |
| Hardware resources | |
| Pipeline details | |
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_pipestruct_02.gif
===================================================================
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Index: pavr_pipestruct_02.gif
===================================================================
--- pavr_pipestruct_02.gif (nonexistent)
+++ pavr_pipestruct_02.gif (revision 6)
pavr_pipestruct_02.gif
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+application/octet-stream
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Index: pavr_hwres_sfu_01.gif
===================================================================
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Index: pavr_hwres_sfu_01.gif
===================================================================
--- pavr_hwres_sfu_01.gif (nonexistent)
+++ pavr_hwres_sfu_01.gif (revision 6)
pavr_hwres_sfu_01.gif
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+application/octet-stream
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Index: group__pavr__hwres__bpu.html
===================================================================
--- group__pavr__hwres__bpu.html (nonexistent)
+++ group__pavr__hwres__bpu.html (revision 6)
@@ -0,0 +1,57 @@
+
+
+Bypass Unit
+
+
+
+
+Main Page Modules Related Pages
+
Bypass Unit
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: todo.html
===================================================================
--- todo.html (nonexistent)
+++ todo.html (revision 6)
@@ -0,0 +1,43 @@
+
+
+Todo List
+
+
+
+
+Main Page Modules Related Pages
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_hwres_iof_gen_01.gif
===================================================================
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svn:mime-type = application/octet-stream
Index: pavr_hwres_iof_gen_01.gif
===================================================================
--- pavr_hwres_iof_gen_01.gif (nonexistent)
+++ pavr_hwres_iof_gen_01.gif (revision 6)
Bypass Unit
+
+[Hardware resources]
+
Modules | |
| Bypass chain 0 | |
| Bypass chain 1 | |
| Bypass chain 2 | |
Detailed Description
+- +General considerations
-
+The Bypass Unit (BPU) is a FIFO-like temporary storage area, that keeps data to be written into the Register File.
+ If an instruction computes a value that must be written into the Register File (RF) (an ALU instruction, for example) it first writes the BPU, and then (or at the same time) actually writes the RF.
+ If the following instructions need an operand from the RF, at the same address where the previous result should have been written into the RF, they will actually read that operand from the BPU rather than from RF.
+ This way, `read before write' pipeline hazards are avoided.
+
+ The specific situations where BPU is needed are:-
+
- when reading Register File operand(s).
+ Reading Register File operands is done through the BPU. - when reading pointer registers.
+ Reading pointer registers is done through the BPU.
- when reading Register File operand(s).
- +Details
-
+The algorithm of using BPU:
-
+
- the instruction that wants to write a result into the RF, writes first the BPU with 3 data fields:
-
+
- the result itself
- result's address into RF
- a flag that marks this BPU entry as having valid data (a so-called `active' flag)
- next instruction(s) that need an operand from RF, read it through a dedicated function (combinational logic), that does the following:
-
+
- checks all BPU entries and see which ones are active (hold meaningful data).
- compares operand's address against the addresses in all active BPU entries.
- if a single address matches, gets the data in that BPU entry rather than data from the RF.
- if multiple addresses match, gets the data in the most recent BPU entry. Even though it's possible that 2 matches happen at simultaneous BPU entries, this situation should never occur; it would indicate a design bug. This illegal situation would assert an error during simulation.
- if no address matches, gets data from the RF (as if BPU were not existing).
+ The maximum delay between a write and a read from the RF is 4 clocks. Thus, the BPU FIFO-like structure has a depth of 4.
+ On the other hand, the BPU must be able to be written 3 one byte operands, at a time (must have 3 write ports). The most BPU demanding instructions are stores with pre(post) decrement(increment). Both the one byte data and a 2 byte pointer register must be written into the BPU, as well as into the RF. The 3 bytes are simultaneousely written into so-called `BPU chains' or `BPU registers' (BPU chains 0, 1, 2; or BPU registers 0, 1, 2; or BPR0, BPR1, BPR2).
+
+ The BPU has 3x4 entries, each consisting of:-
+
- an 8 bit data field
- a 5 bit address field
- a flag that marks the entry as active or inactive
- the instruction that wants to write a result into the RF, writes first the BPU with 3 data fields:
- +Accessing BPU:
-
+
+++
+
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: todo.html
===================================================================
--- todo.html (nonexistent)
+++ todo.html (revision 6)
@@ -0,0 +1,43 @@
+
+
+Todo List
+ +-
+
- Group pavr_avrarch
- Add some AVR kernel schematics.
+ Add some AVR general considerations. +
+ +
-
+
- Group pavr_control
-
+
- Branch prediction with hashed branch prediction table and 2 bit predictor.
- Super-RAM interfacing to Program Memory.
+ A super-RAM is a classic RAM with two supplemental lines: a mem_rq input and a mem_ack output. The device that writes/reads the super-RAM knows that it can place an access request when the memory signalizes it's ready via mem_ack. Only then, it can place an access request via mem_rq.
+ A super-RAM is a super-class for classic RAM. That is, a super-RAM becomes classic RAM if the RAM ignores mem_rq and keeps continousely mem_ack to 1.
+ The super-RAM protocol is so flexible that, as an extreme example, it can serially (!) interface the Program Memory to the controller. That is, about 2-3 wires instead of 38 wires, without needing to modify anything in the controller. Of course, that would come with a very large speed penalty, but it allows choosing the most advantageous compromise between the number of wires and speed. The only thing to be done is to add a serial to parallel converter, that complies to the super-RAM protocol.
+ After pAVR is made super-RAM compatible, it can run anyway from a regular RAM, as it runs now, by ignoring the two extra lines. Thus, nothing is removed, it's only added. No speed penalty should be payed.
+ A simple way to add the super-RAM interface is to force nops into the pipeline as long as the serial-to-parallel converter works on an instruction word.
+ - Modify stall handling so that no nops are required after the instruction wavefront. The instructions could take care of themselves. The idea is that a request to a hardware resource that is already in use by an older instruction, could automatically generate a stall.
+ That would:-
+
- generally simplify instruction handling
- make average instruction execution slightly faster.
+ +
-
+
- Group pavr_src
- Replace `next_...' signals family with a (pretty wide) state decoder. +
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_hwres_iof_gen_01.gif
===================================================================
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Index: pavr_hwres_iof_gen_01.gif
===================================================================
--- pavr_hwres_iof_gen_01.gif (nonexistent)
+++ pavr_hwres_iof_gen_01.gif (revision 6)
pavr_hwres_iof_gen_01.gif
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+application/octet-stream
\ No newline at end of property
Index: modules.html
===================================================================
--- modules.html (nonexistent)
+++ modules.html (revision 6)
@@ -0,0 +1,85 @@
+
+
+Module Index
+
+
+
+
+Main Page Modules Related Pages
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_hwres_rf_01.gif
===================================================================
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Index: pavr_hwres_rf_01.gif
===================================================================
--- pavr_hwres_rf_01.gif (nonexistent)
+++ pavr_hwres_rf_01.gif (revision 6)
Pipelined AVR microcontroller Modules
Here is a list of all modules:-
+
- Introduction +
- AVR architecture +
- AVR instruction set +
- Implementation
+
-
+
- Pipeline structure +
- Hardware resources
+
-
+
- Register File
+
-
+
- Read port 1 +
- Read port 2 +
- Write port +
- X port +
- Y port +
- Z port +
- Bypass Unit + +
- IO File + +
- ALU +
- DACU +
- Data Memory +
- Program Memory +
- Stall and Flush Unit +
- Register File
+
- Pipeline details
+
-
+
- ALU +
- IOF access +
- DACU access +
- Jumps +
- Branches +
- Skips +
- Calls +
- Returns +
- Interrupts +
- Others +
- Testing
+
-
+
- Bugs +
- FPGA prototyping +
- Sources +
- References +
- Some final thoughts +
- About ... +
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_hwres_rf_01.gif
===================================================================
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Index: pavr_hwres_rf_01.gif
===================================================================
--- pavr_hwres_rf_01.gif (nonexistent)
+++ pavr_hwres_rf_01.gif (revision 6)
pavr_hwres_rf_01.gif
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+application/octet-stream
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Index: ftv2blank.png
===================================================================
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Index: ftv2blank.png
===================================================================
--- ftv2blank.png (nonexistent)
+++ ftv2blank.png (revision 6)
ftv2blank.png
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+application/octet-stream
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Index: test_pavr_compile.do
===================================================================
--- test_pavr_compile.do (nonexistent)
+++ test_pavr_compile.do (revision 6)
@@ -0,0 +1,15 @@
+;# This is a Modelsim PE/Plus 5.3a_p1 macro file.
+;# It can be seen here what's the compiling order for pAVR's test VHDL sources.
+
+;# Compile pAVR
+do pavr_compile.do
+
+;# Compile test architectures
+;# Test-only constants (such as Program Memory length, etc)
+vcom -reportprogress 300 -work work {test_pavr_constants.vhd}
+;# Test-only functions (such as for quickly writing Program Memory)
+vcom -reportprogress 300 -work work {test_pavr_util.vhd}
+;# Program Memory
+vcom -reportprogress 300 -work work {test_pavr_pm.vhd}
+;# Main test architecture
+vcom -reportprogress 300 -work work {test_pavr.vhd}
Index: pavr_hwres_dacu_01.gif
===================================================================
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Index: pavr_hwres_dacu_01.gif
===================================================================
--- pavr_hwres_dacu_01.gif (nonexistent)
+++ pavr_hwres_dacu_01.gif (revision 6)
pavr_hwres_dacu_01.gif
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+application/octet-stream
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Index: group__pavr__hwres__iof__sregwr.html
===================================================================
--- group__pavr__hwres__iof__sregwr.html (nonexistent)
+++ group__pavr__hwres__iof__sregwr.html (revision 6)
@@ -0,0 +1,40 @@
+
+
+SREG port
+
+
+
+
+Main Page Modules Related Pages
+
SREG port
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__fpga.html
===================================================================
--- group__pavr__fpga.html (nonexistent)
+++ group__pavr__fpga.html (revision 6)
@@ -0,0 +1,23 @@
+
+
+FPGA prototyping
+
+
+
+
+Main Page Modules Related Pages
+
FPGA prototyping
+
+No FPGAs were burned so far.
+
+
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: test_pavr_util.vhd
===================================================================
--- test_pavr_util.vhd (nonexistent)
+++ test_pavr_util.vhd (revision 6)
@@ -0,0 +1,72 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This is a utility for easely setting up Program Memory in the main testing
+-- architecture.
+-- This is just a testing utility, NOT actually a test.
+--
+
+
+
+--
+library work;
+use work.std_util.all;
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+
+package test_pavr_util is
+
+ -- Function for writing Program Memory
+ function pm_setup(pm_addr: natural; pm_val: natural) return std_logic_vector;
+
+end;
+
+
+
+package body test_pavr_util is
+
+ -- Function for writing Program Memory
+ function pm_setup(pm_addr: natural; pm_val: natural) return std_logic_vector is
+ variable rv: std_logic_vector(22+16-1 downto 0);
+ begin
+ rv := int_to_std_logic_vector(pm_addr, 22) & int_to_std_logic_vector(pm_val, 16);
+ return rv;
+ end;
+
+end;
+--
Index: group__pavr__hwres__iof__rampdwr.html
===================================================================
--- group__pavr__hwres__iof__rampdwr.html (nonexistent)
+++ group__pavr__hwres__iof__rampdwr.html (revision 6)
@@ -0,0 +1,35 @@
+
+
+RAMPD port
+
+
+
+
+Main Page Modules Related Pages
+
RAMPD port
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: ftv2mnode.png
===================================================================
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Index: ftv2mnode.png
===================================================================
--- ftv2mnode.png (nonexistent)
+++ ftv2mnode.png (revision 6)
SREG port
+
+[IO File]
+
- +SREG port connectivity
-
+
+++
+
+
- +Requests to this port
-
+
-
+
- pavr_s5_alu_sregwr_rq
+ This signalizes that an instruction that uses the ALU wants to update the arithmetic flags.
+ Flags I (general interrupt enable, SREG(7)) and T (transfer bit, SREG(6)) are left unchanged.
+ - pavr_s5_setiflag_sregwr_rq
+ This sets the I flag.
+ Only RETI instruction needs this. - pavr_s5_clriflag_sregwr_rq
+ This clears the I flag.
+ No instruction explicitely requests this.
+ This is only requested when an interrupt is acknowledged (during the consequent implicit CALL).
+
+
- pavr_s5_alu_sregwr_rq
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__fpga.html
===================================================================
--- group__pavr__fpga.html (nonexistent)
+++ group__pavr__fpga.html (revision 6)
@@ -0,0 +1,23 @@
+
+
+FPGA prototyping
+
+[Testing]
+
+
+
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: test_pavr_util.vhd
===================================================================
--- test_pavr_util.vhd (nonexistent)
+++ test_pavr_util.vhd (revision 6)
@@ -0,0 +1,72 @@
+-- RAMPD port
+
+[IO File]
+
- +RAMPD port connectivity
-
+
+++
+
+ This is a trivial read-only port.
+
+ The register RAMPD is used in controllers with more than 64KB of Data Memory, to access the whole Data Memory space.
+ RAMPD is used by instructions LDS (LoaD direct from data Space) and STS (STore direct to data Space). In order to get to the desired Data Memory space address, these instructions concatenate RAMPD with a 16 bit constant from the instruction word (RAMPD:k16).
+
+ In controllers with less than 64KB of Data Memory, this register is not used.
+ The RAMPD register can be written only through the IOF general read and write port.
+ No instruction explicitely requests to write this register.
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: ftv2mnode.png
===================================================================
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Index: ftv2mnode.png
===================================================================
--- ftv2mnode.png (nonexistent)
+++ ftv2mnode.png (revision 6)
ftv2mnode.png
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+application/octet-stream
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Index: group__pavr__hwres__rf__rd2.html
===================================================================
--- group__pavr__hwres__rf__rd2.html (nonexistent)
+++ group__pavr__hwres__rf__rd2.html (revision 6)
@@ -0,0 +1,32 @@
+
+
+Read port 2
+
+
+
+
+Main Page Modules Related Pages
+
Read port 2
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: ftv2pnode.png
===================================================================
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Index: ftv2pnode.png
===================================================================
--- ftv2pnode.png (nonexistent)
+++ ftv2pnode.png (revision 6)
Read port 2
+
+[Register File]
+
- +Register File read port 2 connectivity
-
+
+++
+
+
- +Requests to RF read port 2
-
+
-
+
- pavr_s3_rfrd2_rq
+ Needed by 2 operands instructions (most ALU instructions, moves).
+
- pavr_s3_rfrd2_rq
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: ftv2pnode.png
===================================================================
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Index: ftv2pnode.png
===================================================================
--- ftv2pnode.png (nonexistent)
+++ ftv2pnode.png (revision 6)
ftv2pnode.png
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+application/octet-stream
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Index: ftv2doc.png
===================================================================
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Index: ftv2doc.png
===================================================================
--- ftv2doc.png (nonexistent)
+++ ftv2doc.png (revision 6)
ftv2doc.png
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+application/octet-stream
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Index: group__pavr__hwres__alu.html
===================================================================
--- group__pavr__hwres__alu.html (nonexistent)
+++ group__pavr__hwres__alu.html (revision 6)
@@ -0,0 +1,72 @@
+
+
+ALU
+
+
+
+
+Main Page Modules Related Pages
+
ALU
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_pipe_branches_01.gif
===================================================================
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Index: pavr_pipe_branches_01.gif
===================================================================
--- pavr_pipe_branches_01.gif (nonexistent)
+++ pavr_pipe_branches_01.gif (revision 6)
ALU
+
+[Hardware resources]
+
- +ALU connectivity:
-
+
+++
+
+ Here it can be seen how the ALU plugs into the pipeline.
+
+ The ALU is a 100% combinational device.
+ It accepts 2 operands:-
+
- a 16 bit operand
+ This is taken through the Bypass Unit. - an 8 bit operand
+ This is taken through the Bypass Unit.
+ - a 16 bit operand
- +ALU opcodes:
-
+
-
+
- NOP
+ - OP1
+ Transfers operand 1 directly to the ALU output.
+ OP2
+ Transfers operand 2 directly to the lower 8 bits of ALU output.
+ - ADD8
+ ADC8
+ Adds with carry lower 8 bits of operand 1 with operand 2.
+ SUB8
+ SBC8
+ - AND8
+ EOR8
+ OR8
+ - INC8
+ DEC8
+ - COM8
+ NEG8
+ SWAP8
+ - LSR8
+ ASR8
+ ROR8
+ - ADD16
+ Adds without carry operand 1 with operand 2 sign extended to 16 bits.
+ SUB16
+ - MUL8
+ MULS8
+ MULSU8
+ FMUL8
+ FMULS8
+ FMULSU8
+
- NOP
- +ALU flags:
-
+
-
+
- H (half carry)
- S (sign)
- V (two's complement)
- N (negative)
- Z (zero)
- C (carry)
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_pipe_branches_01.gif
===================================================================
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Index: pavr_pipe_branches_01.gif
===================================================================
--- pavr_pipe_branches_01.gif (nonexistent)
+++ pavr_pipe_branches_01.gif (revision 6)
pavr_pipe_branches_01.gif
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+application/octet-stream
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Index: pavr_hwres_iof_perif_int0_01.gif
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Index: pavr_hwres_iof_perif_int0_01.gif
===================================================================
--- pavr_hwres_iof_perif_int0_01.gif (nonexistent)
+++ pavr_hwres_iof_perif_int0_01.gif (revision 6)
pavr_hwres_iof_perif_int0_01.gif
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Index: pavr_hwres_iof_sreg_01.gif
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Index: pavr_hwres_iof_sreg_01.gif
===================================================================
--- pavr_hwres_iof_sreg_01.gif (nonexistent)
+++ pavr_hwres_iof_sreg_01.gif (revision 6)
pavr_hwres_iof_sreg_01.gif
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+application/octet-stream
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Index: tree.html
===================================================================
--- tree.html (nonexistent)
+++ tree.html (revision 6)
@@ -0,0 +1,11 @@
+
+
+
+
+
+
+
+
+
Index: pavr_hwres_iof_perif_int0_03.gif
===================================================================
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Index: pavr_hwres_iof_perif_int0_03.gif
===================================================================
--- pavr_hwres_iof_perif_int0_03.gif (nonexistent)
+++ pavr_hwres_iof_perif_int0_03.gif (revision 6)
pavr_hwres_iof_perif_int0_03.gif
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Index: pavr_hwres_iof_rampd_01.gif
===================================================================
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Index: pavr_hwres_iof_rampd_01.gif
===================================================================
--- pavr_hwres_iof_rampd_01.gif (nonexistent)
+++ pavr_hwres_iof_rampd_01.gif (revision 6)
pavr_hwres_iof_rampd_01.gif
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+application/octet-stream
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Index: pavr_hwres_dm_01.gif
===================================================================
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Index: pavr_hwres_dm_01.gif
===================================================================
--- pavr_hwres_dm_01.gif (nonexistent)
+++ pavr_hwres_dm_01.gif (revision 6)
pavr_hwres_dm_01.gif
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+application/octet-stream
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Index: group__pavr__pipeline__iof.html
===================================================================
--- group__pavr__pipeline__iof.html (nonexistent)
+++ group__pavr__pipeline__iof.html (revision 6)
@@ -0,0 +1,33 @@
+
+
+IOF access
+
+
+
+
+Main Page Modules Related Pages
+
IOF access
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_hwres_pm_01.gif
===================================================================
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Index: pavr_hwres_pm_01.gif
===================================================================
--- pavr_hwres_pm_01.gif (nonexistent)
+++ pavr_hwres_pm_01.gif (revision 6)
IOF access
+
+[Pipeline details]
+
- +A few details
-
+The IO File is accessed during stages s5 or/and s6.
+ As presented here, the IO File can do more than byte-oriented read-write operations. It can also do bit processing.
+ The following data is provided to the IOF, for each pipeline stage in which IOF access is required:-
+
- byte address
- bit address
- opcode
- byte data in
- +Accessing the IOF
-
+Main pipeline registers that implement IOF accessing instructions are presented here:
+
+++
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_hwres_pm_01.gif
===================================================================
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Index: pavr_hwres_pm_01.gif
===================================================================
--- pavr_hwres_pm_01.gif (nonexistent)
+++ pavr_hwres_pm_01.gif (revision 6)
pavr_hwres_pm_01.gif
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+application/octet-stream
\ No newline at end of property
Index: group__pavr__hwres__bpr2.html
===================================================================
--- group__pavr__hwres__bpr2.html (nonexistent)
+++ group__pavr__hwres__bpr2.html (revision 6)
@@ -0,0 +1,35 @@
+
+
+Bypass chain 2
+
+
+
+
+Main Page Modules Related Pages
+
Bypass chain 2
+
+
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_hwres_rf_rd2_01.gif
===================================================================
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Index: pavr_hwres_rf_rd2_01.gif
===================================================================
--- pavr_hwres_rf_rd2_01.gif (nonexistent)
+++ pavr_hwres_rf_rd2_01.gif (revision 6)
Bypass chain 2
+
+[Bypass Unit]
+
- +Bypass chain 2 (BPR2) write port connectivity
-
+
+++
+
+
- +Requests to BPR2 write port
-
+
-
+
- pavr_s5_dacux_bpr12wr_rq
+ Needed by loads and stores with pre(post) decrement(increment).
+ Higher byte of X pointer will be written into BPR2. - pavr_s5_dacuy_bpr12wr_rq
+ Needed by loads and stores with pre(post) decrement(increment).
+ Higher byte of Y pointer will be written into BPR2. - pavr_s5_dacuz_bpr12wr_rq Needed by loads and stores with pre(post) decrement(increment).
+ Higher byte of Z pointer will be written into BPR2.
- pavr_s5_dacux_bpr12wr_rq
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: pavr_hwres_rf_rd2_01.gif
===================================================================
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Index: pavr_hwres_rf_rd2_01.gif
===================================================================
--- pavr_hwres_rf_rd2_01.gif (nonexistent)
+++ pavr_hwres_rf_rd2_01.gif (revision 6)
pavr_hwres_rf_rd2_01.gif
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## -0,0 +1 ##
+application/octet-stream
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Index: group__pavr__pipeline__int.html
===================================================================
--- group__pavr__pipeline__int.html (nonexistent)
+++ group__pavr__pipeline__int.html (revision 6)
@@ -0,0 +1,41 @@
+
+
+Interrupts
+
+
+
+
+Main Page Modules Related Pages
+
Interrupts
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__pipeline__jumps.html
===================================================================
--- group__pavr__pipeline__jumps.html (nonexistent)
+++ group__pavr__pipeline__jumps.html (revision 6)
@@ -0,0 +1,45 @@
+
+
+Jumps
+
+
+
+
+Main Page Modules Related Pages
+
Jumps
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: ftv2lastnode.png
===================================================================
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Index: ftv2lastnode.png
===================================================================
--- ftv2lastnode.png (nonexistent)
+++ ftv2lastnode.png (revision 6)
Interrupts
+
+[Pipeline details]
+
- +General
-
+The Interrupt System can forcedly place calls into the pipeline stage s3, as a result of specific IO activity.
+
+
- +Implementation
-
+The core of the Interrupt System is the Interrupt Manager module. It prioritizes the interrupt sources, checks if interrupts are enabled and if the pipeline is ready to process interrupts, and finally sends interrupt requests to the pipeline, together with the associated interrupt vector and other pipeline control signals.
+
+++
+
+ The pipeline acknowledges interrupt requests by forcing the Instruction Decoder to decode a call instruction, with the absolute jump address given by the Interrupt Manager. Next 2 instructions, that were already uselessly fetched, are flushed.
+
+ The interrupt vectors are parameterized, and can be placed anywhere in the Program Memory.
+ Every interrupt has a parameterized priority.
+ In the present implementation, up to 32 interrupt sources are handled.
+ 2 interrupt sources are implemented: external interrupt 0 and timer 0 interrupt.
+
+ Because the Interrupt Manger shares much with the IO File, it is not built as a separate entity, but rather embedded into the IO File. The Interrupt Manager might be implemented as separate entity in a future version of pAVR.
+
+ The interrupt latency is 5 clocks (1 clock needed by the interrupt manager and 4 clocks needed by the implicit call).
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__pipeline__jumps.html
===================================================================
--- group__pavr__pipeline__jumps.html (nonexistent)
+++ group__pavr__pipeline__jumps.html (revision 6)
@@ -0,0 +1,45 @@
+
+
+Jumps
+
+[Pipeline details]
+
- +A few details
-
+There are 4 jump instructions:
-
+
- RJMP (relative jump)
+ The jump address is obtained by adding to the current Program Counter a 12 bit signed offset obtained from the instruction word. - IJMP (indirect jump)
+ The jump address is read from the Z pointer register.
+ The jump destination resides in the lower 64 Kwords of Program Memory.
+ - EIJMP (extended indirect jump)
+ The jump address is read from EIND:Z (higher 6 bis from EIND register in IOF, and lower 16 bits from Z pointer in RF).
+ This jump accesses the whole 22 bit addressing space of the Program Memory.
+ - JMP (long jump)
+ The jump address is read from two consecutive instruction words.
+ This jump accesses the whole 22 bit addressing space of the Program Memory.
+
+ When a jump is detected into the pipeline, next two instructions (that were already uselessly fetched from the Program Memory) are flushed. Then, the Program Memory manager is asked permission to access the Program Memory and to modify the instruction flow (modify the Program Counter).
+ After that, unless it gets flushed or stalled by an older instruction, the jump instruction will configure the pipeline to fetch from the new PM address.
+
+ RJMP and JMP take 3 clocks, while IJMP and EIJMP take 4 clocks.
+ - RJMP (relative jump)
- +Jump state machine
-
+
+++
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: ftv2lastnode.png
===================================================================
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Index: ftv2lastnode.png
===================================================================
--- ftv2lastnode.png (nonexistent)
+++ ftv2lastnode.png (revision 6)
ftv2lastnode.png
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: doxygen.css
===================================================================
--- doxygen.css (nonexistent)
+++ doxygen.css (revision 6)
@@ -0,0 +1,49 @@
+H1 { text-align: center; }
+CAPTION { font-weight: bold }
+A.qindex {}
+A.qindexRef {}
+A.el { text-decoration: none; font-weight: bold }
+A.elRef { font-weight: bold }
+A.code { text-decoration: none; font-weight: normal; color: #4444ee }
+A.codeRef { font-weight: normal; color: #4444ee }
+A:hover { text-decoration: none; background-color: #f2f2ff }
+DL.el { margin-left: -1cm }
+DIV.fragment { width: 100%; border: none; background-color: #eeeeee }
+DIV.ah { background-color: black; font-weight: bold; color: #ffffff; margin-bottom: 3px; margin-top: 3px }
+TD.md { background-color: #f2f2ff; font-weight: bold; }
+TD.mdname1 { background-color: #f2f2ff; font-weight: bold; color: #602020; }
+TD.mdname { background-color: #f2f2ff; font-weight: bold; color: #602020; width: 600px; }
+DIV.groupHeader { margin-left: 16px; margin-top: 12px; margin-bottom: 6px; font-weight: bold }
+DIV.groupText { margin-left: 16px; font-style: italic; font-size: smaller }
+BODY { background: white }
+TD.indexkey {
+ background-color: #eeeeff;
+ font-weight: bold;
+ padding-right : 10px;
+ padding-top : 2px;
+ padding-left : 10px;
+ padding-bottom : 2px;
+ margin-left : 0px;
+ margin-right : 0px;
+ margin-top : 2px;
+ margin-bottom : 2px
+}
+TD.indexvalue {
+ background-color: #eeeeff;
+ font-style: italic;
+ padding-right : 10px;
+ padding-top : 2px;
+ padding-left : 10px;
+ padding-bottom : 2px;
+ margin-left : 0px;
+ margin-right : 0px;
+ margin-top : 2px;
+ margin-bottom : 2px
+}
+FONT.keyword { color: #008000 }
+FONT.keywordtype { color: #604020 }
+FONT.keywordflow { color: #e08000 }
+FONT.comment { color: #800000 }
+FONT.preprocessor { color: #806020 }
+FONT.stringliteral { color: #002080 }
+FONT.charliteral { color: #008080 }
Index: test_std_util.vhd
===================================================================
--- test_std_util.vhd (nonexistent)
+++ test_std_util.vhd (revision 6)
@@ -0,0 +1,169 @@
+--
+-- Project
+-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
+-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
+-- The increase in speed comes from a relatively deep pipeline. The original
+-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
+-- 6 pipeline stages:
+-- 1. PM (read Program Memory)
+-- 2. INSTR (load Instruction)
+-- 3. RFRD (decode Instruction and read Register File)
+-- 4. OPS (load Operands)
+-- 5. ALU (execute ALU opcode or access Unified Memory)
+-- 6. RFWR (write Register File)
+-- Version
+-- 0.32
+-- Date
+-- 2002 August 07
+-- Author
+-- Doru Cuturela, doruu@yahoo.com
+-- License
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+--
+
+
+
+--
+-- This tests the utilities defined in `std_util.vhd':
+-- - cmp_std_logic_vector (asynchronous function)
+-- - sign_extend (asynchronous function)
+-- - zero_extend (asynchronous function)
+--
+
+
+
+--
+library ieee;
+use ieee.std_logic_1164.all;
+library work;
+use work.std_util.all;
+
+
+entity test_std_util is
+end;
+
+
+architecture arch_test_std_util of test_std_util is
+ signal clk: std_logic;
+ -- Comparision output
+ signal flag1: std_logic;
+ -- Candidates to sign/zero extension and comparision
+ signal v2_1, v2_2, v2_3: std_logic_vector( 1 downto 0);
+ signal v50_1, v50_2, v50_3: std_logic_vector(49 downto 0);
+begin
+
+ generate_clock:
+ process
+ begin
+ clk <= '1';
+ wait for 50 ns;
+ clk <= '0';
+ wait for 50 ns;
+ end process generate_clock;
+
+
+ test_main:
+ process
+ begin
+ -- Set up default inputs.
+ v2_1 <= "10";
+ v2_2 <= "01";
+ for i in 0 to 49 loop
+ v50_1(i) <= '0';
+ v50_2(i) <= '0';
+ end loop;
+ v50_1(49) <= '1';
+ v50_1(3 downto 0) <= "1001";
+ v50_2(3 downto 0) <= "1010";
+ wait for 110 ns;
+
+ -- TEST 1
+ -- Test function `cmp_std_logic_vector'
+ -- Try to compare 2 vectors with different lengths; this should assert the dedicated error.
+ --flag1 <= cmp_std_logic_vector(v2_1, v50_1);
+ --wait until clk'event and clk='1';
+ -- Typical situations
+ -- Shouldn't match
+ flag1 <= cmp_std_logic_vector(v50_1, v50_2);
+ wait until clk'event and clk='1';
+ -- Should match
+ flag1 <= cmp_std_logic_vector(v50_1, v50_1);
+ wait until clk'event and clk='1';
+ -- Shouldn't match
+ flag1 <= cmp_std_logic_vector(sign_extend(v2_1, v50_1'length), zero_extend(v2_1, v50_1'length));
+ wait until clk'event and clk='1';
+ -- Should match
+ flag1 <= cmp_std_logic_vector(sign_extend(v2_2, v50_1'length), zero_extend(v2_2, v50_1'length));
+ wait until clk'event and clk='1';
+
+ -- TEST 2
+ -- Test function `sign_extend' and `zero_extend', negative input.
+ -- Extremal case that should work. For length 2, typical case = extremal case.
+ v2_3 <= sign_extend(v2_1, v2_3'length);
+ wait until clk'event and clk='1';
+ v2_3 <= zero_extend(v2_1, v2_3'length);
+ wait until clk'event and clk='1';
+ -- Some stupid length that should generate an error
+ --v2_3 <= sign_extend(v2_1, 7);
+ --wait until clk'event and clk='1';
+ --v2_3 <= zero_extend(v2_1, 7);
+ --wait until clk'event and clk='1';
+ -- The same with width 50
+ -- Typical case
+ v50_3 <= sign_extend(v2_1, v50_3'length);
+ wait until clk'event and clk='1';
+ v50_3 <= zero_extend(v2_1, v50_3'length);
+ wait until clk'event and clk='1';
+ -- Extremal case that should work
+ v50_3 <= sign_extend(v50_1, v50_3'length);
+ wait until clk'event and clk='1';
+ v50_3 <= zero_extend(v50_1, v50_3'length);
+ wait until clk'event and clk='1';
+ -- Some stupid length that should generate an error
+ --v50_3 <= sign_extend(v50_1, 7);
+ --wait until clk'event and clk='1';
+ --v50_3 <= zero_extend(v50_1, 7);
+ --wait until clk'event and clk='1';
+
+ -- TEST 1
+ -- Test function `sign_extend' and `zero_extend', positive input.
+ -- Extremal case that should work. For length 2, typical case = extremal case.
+ v2_3 <= sign_extend(v2_2, v2_3'length);
+ wait until clk'event and clk='1';
+ v2_3 <= zero_extend(v2_2, v2_3'length);
+ wait until clk'event and clk='1';
+ -- Some stupid length that should generate an error
+ --v2_3 <= sign_extend(v2_2, 7);
+ --wait until clk'event and clk='1';
+ --v2_3 <= zero_extend(v2_2, 7);
+ --wait until clk'event and clk='1';
+ -- The same with width 50
+ -- Typical case
+ v50_3 <= sign_extend(v2_2, v50_3'length);
+ wait until clk'event and clk='1';
+ v50_3 <= zero_extend(v2_2, v50_3'length);
+ wait until clk'event and clk='1';
+ -- Extremal case that should work
+ v50_3 <= sign_extend(v50_2, v50_3'length);
+ wait until clk'event and clk='1';
+ v50_3 <= zero_extend(v50_2, v50_3'length);
+ wait until clk'event and clk='1';
+ -- Some stupid length that should generate an error
+ --v50_3 <= sign_extend(v50_2, 7);
+ --wait until clk'event and clk='1';
+ --v50_3 <= zero_extend(v50_2, 7);
+ --wait until clk'event and clk='1';
+ end process test_main;
+
+end;
+--
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Index: index.html
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+
+Pipelined AVR microcontroller
+
+
Index: group__pavr__thoughts.html
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+++ group__pavr__thoughts.html (revision 6)
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+
+
+Some final thoughts
+
+
+
+
+Main Page Modules Related Pages
+
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: group__pavr__pipeline__alu.html
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+++ group__pavr__pipeline__alu.html (revision 6)
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+
+
+ALU
+
+
+
+
+Main Page Modules Related Pages
+
ALU
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +1.2.16
+
+
Index: pavr_hwres_rf_xwr_01.gif
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+++ pavr_hwres_rf_xwr_01.gif (revision 6)
Some final thoughts
- +Instead of conclusion...
-
+It's relatively easy to design a fast 8 bit controller. All that has to be done is to follow the path well known from the big brothers, the 32 bit controllers. The short story is: analyze what "typical programs" mean, imagine a simple and fast instruction set, and implement it into a deep pipeline (by the way, for this topics, I recommend you "Computer architecture - a quantitative approach", by J. Hennessy and D. Patterson).
+
+ Then, why are the 8 bit controllers currently on the market so slow? The instruction set, CPI, max frequency for current 8 bit ucs are bad. In fact, they are so bad, that we must consider other factors than pure uc design to explain that. My guess is that market issues distructively interfere here. How is that, this could be another project's goal...
+
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
Index: group__pavr__pipeline__alu.html
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+
+
+ALU
+
+[Pipeline details]
+
- +ALU description
-
+The ALU is not a potentially conflicting resource, as it is fully controlled by pipeline stage s5.
+
+ There are two ALU operands. The first operand is taken either from RF read port 1, if it's an 8 bit operand, or taken from RF read port 1 (lower 8 bits) and from RF read port 2 (higher 8 bits), if it's a 16 bit operand. The second operand is taken either from the RF read port 2 or directly from the instruction opcode; it is always 8 bit-wide.
+ Both operands are fed to the ALU through the Bypass Unit.
+ All ALU-requiring instructions write their result into the Bypass Unit.
+ Details about the ALU hardware resource (connectivity, ALU opcodes) can be found here.
+ Instructions that make use of the ALU-related pipeline registers:-
+
- ADD, ADC, ADIW
- SUB, SUBI, SBC, SBCI, SBIW
- INC, DEC
- AND, ANDI
- OR, ORI, EOR
- COM, NEG, CP, CPC, CPI, SWAP
- LSR, ROR, ASR
- MUL, MULS, MULSU
- FMUL, FMULS, FMULSU
- MOV, MOVW
- +Plugging the ALU into the pipeline
-
+The pipeline registers related to ALU access are presented in the picture below.
+ From this picture, it can also easely figured out instructions' timing.
+
+++
+
+
Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by + +
1.2.16
+
+
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