URL
https://opencores.org/ocsvn/pci/pci/trunk
Subversion Repositories pci
Compare Revisions
- This comparison shows the changes necessary to convert path
/pci/tags/rel_12/sim/rtl_sim/bin
- from Rev 129 to Rev 154
- ↔ Reverse comparison
Rev 129 → Rev 154
/rtl_file_list.lst
0,0 → 1,54
../../../rtl/verilog/pci_parity_check.v |
../../../rtl/verilog/pci_target_unit.v |
../../../rtl/verilog/pci_wb_addr_mux.v |
../../../rtl/verilog/pci_cbe_en_crit.v |
../../../rtl/verilog/pci_pcir_fifo_control.v |
../../../rtl/verilog/pci_out_reg.v |
../../../rtl/verilog/pci_pci_tpram.v |
../../../rtl/verilog/pci_wb_master.v |
../../../rtl/verilog/pci_conf_cyc_addr_dec.v |
../../../rtl/verilog/pci_frame_crit.v |
../../../rtl/verilog/pci_target32_clk_en.v |
../../../rtl/verilog/pci_pciw_fifo_control.v |
../../../rtl/verilog/pci_wb_slave.v |
../../../rtl/verilog/pci_conf_space.v |
../../../rtl/verilog/pci_frame_en_crit.v |
../../../rtl/verilog/pci_par_crit.v |
../../../rtl/verilog/pci_pciw_pcir_fifos.v |
../../../rtl/verilog/pci_wb_slave_unit.v |
../../../rtl/verilog/pci_frame_load_crit.v |
../../../rtl/verilog/pci_bridge32.v |
../../../rtl/verilog/pci_target32_devs_crit.v |
../../../rtl/verilog/pci_perr_crit.v |
../../../rtl/verilog/pci_wbr_fifo_control.v |
../../../rtl/verilog/pci_cur_out_reg.v |
../../../rtl/verilog/pci_pci_decoder.v |
../../../rtl/verilog/pci_target32_interface.v |
../../../rtl/verilog/pci_perr_en_crit.v |
../../../rtl/verilog/pci_wbw_fifo_control.v |
../../../rtl/verilog/pci_wb_decoder.v |
../../../rtl/verilog/pci_in_reg.v |
../../../rtl/verilog/pci_serr_crit.v |
../../../rtl/verilog/pci_wbw_wbr_fifos.v |
../../../rtl/verilog/pci_delayed_sync.v |
../../../rtl/verilog/pci_irdy_out_crit.v |
../../../rtl/verilog/pci_io_mux.v |
../../../rtl/verilog/pci_io_mux_ad_en_crit.v |
../../../rtl/verilog/pci_io_mux_ad_load_crit.v |
../../../rtl/verilog/pci_target32_sm.v |
../../../rtl/verilog/pci_serr_en_crit.v |
../../../rtl/verilog/pci_delayed_write_reg.v |
../../../rtl/verilog/pci_mas_ad_en_crit.v |
../../../rtl/verilog/pci_mas_ad_load_crit.v |
../../../rtl/verilog/pci_master32_sm.v |
../../../rtl/verilog/pci_target32_stop_crit.v |
../../../rtl/verilog/pci_synchronizer_flop.v |
../../../rtl/verilog/pci_async_reset_flop.v |
../../../rtl/verilog/pci_mas_ch_state_crit.v |
../../../rtl/verilog/pci_master32_sm_if.v |
../../../rtl/verilog/pci_target32_trdy_crit.v |
../../../rtl/verilog/top.v |
../../../rtl/verilog/pci_rst_int.v |
../../../rtl/verilog/pci_sync_module.v |
../../../rtl/verilog/pci_wb_tpram.v |
../../../rtl/verilog/pci_wbs_wbb3_2_wbb2.v |
rtl_file_list.lst
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncelab.args
===================================================================
--- ncelab.args (nonexistent)
+++ ncelab.args (revision 154)
@@ -0,0 +1,8 @@
+-snapshot worklib.bridge32:fun
+-cdslib ../bin/cds.lib
+-hdlvar ../bin/hdl.var
+-logfile ../log/ncelab.log
+-access +wc
+-messages
+-no_tchk_msg
+-v93 worklib.SYSTEM
ncelab.args
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncelab_xilinx.args
===================================================================
--- ncelab_xilinx.args (nonexistent)
+++ ncelab_xilinx.args (revision 154)
@@ -0,0 +1,9 @@
+-snapshot worklib.bridge32:fun
+-cdslib ../bin/cds.lib
+-hdlvar ../bin/hdl.var
+-logfile ../log/ncelab_xilinx.log
+-access +wc
+-messages
+-no_tchk_msg
+-v93
+worklib.SYSTEM worklib.glbl
ncelab_xilinx.args
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: vs_file_list.lst
===================================================================
--- vs_file_list.lst (nonexistent)
+++ vs_file_list.lst (revision 154)
@@ -0,0 +1,4 @@
+vs_rams/018/vs_hdtp_64x40/vs_hdtp_64x40.v
+vs_rams/018/vs_hdtp_64x40_bist.v
+bist/rtl/verilog/bist_two_port.v
+logic/rtl/verilog/jt_bc1in.v
Index: xilinx_file_list.lst
===================================================================
--- xilinx_file_list.lst (nonexistent)
+++ xilinx_file_list.lst (revision 154)
@@ -0,0 +1,4 @@
+../../../../../../lib/xilinx/lib/glbl/glbl.v
+../../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
+../../../../../../lib/xilinx/lib/unisims/RAM16X1D.v
+../../../rtl/verilog/pci_ram_16x40d.v
xilinx_file_list.lst
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sim_file_list.lst
===================================================================
--- sim_file_list.lst (nonexistent)
+++ sim_file_list.lst (revision 154)
@@ -0,0 +1,12 @@
+../../../bench/verilog/wb_master32.v
+../../../bench/verilog/wb_master_behavioral.v
+../../../bench/verilog/system.v
+../../../bench/verilog/pci_blue_arbiter.v
+../../../bench/verilog/pci_bus_monitor.v
+../../../bench/verilog/pci_behaviorial_device.v
+../../../bench/verilog/pci_behaviorial_master.v
+../../../bench/verilog/pci_behaviorial_target.v
+../../../bench/verilog/wb_slave_behavioral.v
+../../../bench/verilog/wb_bus_mon.v
+../../../bench/verilog/pci_unsupported_commands_master.v
+../../../bench/verilog/pci_behavioral_pci2pci_bridge.v
sim_file_list.lst
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncsim_waves.rc
===================================================================
--- ncsim_waves.rc (nonexistent)
+++ ncsim_waves.rc (revision 154)
@@ -0,0 +1,7 @@
+set dump_level all
+
+database -open waves -shm -into ../out/waves.shm
+probe -create -database waves SYSTEM -shm -all -depth $dump_level
+
+run
+quit
ncsim_waves.rc
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: artisan_file_list.lst
===================================================================
--- artisan_file_list.lst (nonexistent)
+++ artisan_file_list.lst (revision 154)
@@ -0,0 +1,6 @@
+-cdslib ../bin/cds.lib
+-hdlvar ../bin/hdl.var
+-logfile ../log/ncvlog_artisan.log
+-update
+-messages
+../../../../../../lib/artisan/art_hsdp_256x40.v
artisan_file_list.lst
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncsim.rc
===================================================================
--- ncsim.rc (nonexistent)
+++ ncsim.rc (revision 154)
@@ -0,0 +1,2 @@
+run
+quit
ncsim.rc
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: nc_xilinx.scr
===================================================================
--- nc_xilinx.scr (nonexistent)
+++ nc_xilinx.scr (revision 154)
@@ -0,0 +1,76 @@
+//+ncelabargs+"-timescale 1ns/10ps"
++libext+.v
+// RTL sources
+../../../rtl/verilog/pci_parity_check.v
+../../../rtl/verilog/pci_target_unit.v
+../../../rtl/verilog/wb_addr_mux.v
+../../../rtl/verilog/cbe_en_crit.v
+../../../rtl/verilog/fifo_control.v
+../../../rtl/verilog/out_reg.v
+../../../rtl/verilog/pci_tpram.v
+../../../rtl/verilog/wb_master.v
+../../../rtl/verilog/conf_cyc_addr_dec.v
+../../../rtl/verilog/frame_crit.v
+../../../rtl/verilog/pci_target32_clk_en.v
+../../../rtl/verilog/pciw_fifo_control.v
+../../../rtl/verilog/wb_slave.v
+../../../rtl/verilog/conf_space.v
+../../../rtl/verilog/frame_en_crit.v
+../../../rtl/verilog/par_crit.v
+../../../rtl/verilog/pci_target32_ctrl_en_crit.v
+../../../rtl/verilog/pciw_pcir_fifos.v
+../../../rtl/verilog/wb_slave_unit.v
+../../../rtl/verilog/frame_load_crit.v
+../../../rtl/verilog/pci_bridge32.v
+../../../rtl/verilog/pci_target32_devs_crit.v
+../../../rtl/verilog/perr_crit.v
+../../../rtl/verilog/wbr_fifo_control.v
+../../../rtl/verilog/cur_out_reg.v
+../../../rtl/verilog/pci_decoder.v
+../../../rtl/verilog/pci_target32_interface.v
+../../../rtl/verilog/perr_en_crit.v
+../../../rtl/verilog/wbw_fifo_control.v
+../../../rtl/verilog/decoder.v
+../../../rtl/verilog/pci_in_reg.v
+../../../rtl/verilog/pci_target32_load_crit.v
+../../../rtl/verilog/serr_crit.v
+../../../rtl/verilog/wbw_wbr_fifos.v
+../../../rtl/verilog/delayed_sync.v
+../../../rtl/verilog/irdy_out_crit.v
+../../../rtl/verilog/pci_io_mux.v
+../../../rtl/verilog/pci_io_mux_ad_en_crit.v
+../../../rtl/verilog/pci_io_mux_ad_load_crit.v
+../../../rtl/verilog/pci_target32_sm.v
+../../../rtl/verilog/serr_en_crit.v
+../../../rtl/verilog/delayed_write_reg.v
+../../../rtl/verilog/mas_ad_en_crit.v
+../../../rtl/verilog/mas_ad_load_crit.v
+../../../rtl/verilog/pci_master32_sm.v
+../../../rtl/verilog/pci_target32_stop_crit.v
+../../../rtl/verilog/synchronizer_flop.v
+../../../rtl/verilog/async_reset_flop.v
+../../../rtl/verilog/mas_ch_state_crit.v
+../../../rtl/verilog/pci_master32_sm_if.v
+../../../rtl/verilog/pci_target32_trdy_crit.v
+../../../rtl/verilog/top.v
+../../../rtl/verilog/pci_rst_int.v
+../../../rtl/verilog/sync_module.v
+../../../rtl/verilog/wb_tpram.v
+// Sim sources
+../../../bench/verilog/wb_master32.v
+../../../bench/verilog/wb_master_behavioral.v
+../../../bench/verilog/system.v
+../../../bench/verilog/pci_blue_arbiter.v
+../../../bench/verilog/pci_bus_monitor.v
+../../../bench/verilog/pci_behaviorial_device.v
+../../../bench/verilog/pci_behaviorial_master.v
+../../../bench/verilog/pci_behaviorial_target.v
+../../../bench/verilog/wb_slave_behavioral.v
+../../../bench/verilog/wb_bus_mon.v
+../../../bench/verilog/wb_slave32.v
+../../../bench/verilog/pci_behavioral_iack_target.v
+../../../bench/verilog/pci_unsupported_commands_master.v
+// Libs
+../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
+../../../../lib/xilinx/lib/glbl/glbl.v
+//../../../../lib/artisan/art_hsdp_256x40.v
\ No newline at end of file
nc_xilinx.scr
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: nc.scr
===================================================================
--- nc.scr (nonexistent)
+++ nc.scr (revision 154)
@@ -0,0 +1,76 @@
+//+ncelabargs+"-timescale 1ns/10ps"
++libext+.v
+// RTL sources
+../../../rtl/verilog/pci_parity_check.v
+../../../rtl/verilog/pci_target_unit.v
+../../../rtl/verilog/wb_addr_mux.v
+../../../rtl/verilog/cbe_en_crit.v
+../../../rtl/verilog/fifo_control.v
+../../../rtl/verilog/out_reg.v
+../../../rtl/verilog/pci_tpram.v
+../../../rtl/verilog/wb_master.v
+../../../rtl/verilog/conf_cyc_addr_dec.v
+../../../rtl/verilog/frame_crit.v
+../../../rtl/verilog/pci_target32_clk_en.v
+../../../rtl/verilog/pciw_fifo_control.v
+../../../rtl/verilog/wb_slave.v
+../../../rtl/verilog/conf_space.v
+../../../rtl/verilog/frame_en_crit.v
+../../../rtl/verilog/par_crit.v
+../../../rtl/verilog/pci_target32_ctrl_en_crit.v
+../../../rtl/verilog/pciw_pcir_fifos.v
+../../../rtl/verilog/wb_slave_unit.v
+../../../rtl/verilog/frame_load_crit.v
+../../../rtl/verilog/pci_bridge32.v
+../../../rtl/verilog/pci_target32_devs_crit.v
+../../../rtl/verilog/perr_crit.v
+../../../rtl/verilog/wbr_fifo_control.v
+../../../rtl/verilog/cur_out_reg.v
+../../../rtl/verilog/pci_decoder.v
+../../../rtl/verilog/pci_target32_interface.v
+../../../rtl/verilog/perr_en_crit.v
+../../../rtl/verilog/wbw_fifo_control.v
+../../../rtl/verilog/decoder.v
+../../../rtl/verilog/pci_in_reg.v
+../../../rtl/verilog/pci_target32_load_crit.v
+../../../rtl/verilog/serr_crit.v
+../../../rtl/verilog/wbw_wbr_fifos.v
+../../../rtl/verilog/delayed_sync.v
+../../../rtl/verilog/irdy_out_crit.v
+../../../rtl/verilog/pci_io_mux.v
+../../../rtl/verilog/pci_io_mux_ad_en_crit.v
+../../../rtl/verilog/pci_io_mux_ad_load_crit.v
+../../../rtl/verilog/pci_target32_sm.v
+../../../rtl/verilog/serr_en_crit.v
+../../../rtl/verilog/delayed_write_reg.v
+../../../rtl/verilog/mas_ad_en_crit.v
+../../../rtl/verilog/mas_ad_load_crit.v
+../../../rtl/verilog/pci_master32_sm.v
+../../../rtl/verilog/pci_target32_stop_crit.v
+../../../rtl/verilog/synchronizer_flop.v
+../../../rtl/verilog/async_reset_flop.v
+../../../rtl/verilog/mas_ch_state_crit.v
+../../../rtl/verilog/pci_master32_sm_if.v
+../../../rtl/verilog/pci_target32_trdy_crit.v
+../../../rtl/verilog/top.v
+../../../rtl/verilog/pci_rst_int.v
+../../../rtl/verilog/sync_module.v
+../../../rtl/verilog/wb_tpram.v
+// Sim sources
+../../../bench/verilog/wb_master32.v
+../../../bench/verilog/wb_master_behavioral.v
+../../../bench/verilog/system.v
+../../../bench/verilog/pci_blue_arbiter.v
+../../../bench/verilog/pci_bus_monitor.v
+../../../bench/verilog/pci_behaviorial_device.v
+../../../bench/verilog/pci_behaviorial_master.v
+../../../bench/verilog/pci_behaviorial_target.v
+../../../bench/verilog/wb_slave_behavioral.v
+../../../bench/verilog/wb_bus_mon.v
+../../../bench/verilog/wb_slave32.v
+../../../bench/verilog/pci_behavioral_iack_target.v
+../../../bench/verilog/pci_unsupported_commands_master.v
+// Libs
+//../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
+//../../../../lib/xilinx/lib/glbl/glbl.v
+//../../../../lib/artisan/art_hsdp_256x40.v
\ No newline at end of file
nc.scr
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncvlog_sim.args
===================================================================
--- ncvlog_sim.args (nonexistent)
+++ ncvlog_sim.args (revision 154)
@@ -0,0 +1,19 @@
+-cdslib ../bin/cds.lib
+-hdlvar ../bin/hdl.var
+-logfile ../log/ncvlog_sim.log
+-update
+-messages
+-INCDIR ../../../bench/verilog
+-INCDIR ../../../rtl/verilog
+../../../bench/verilog/wb_master32.v
+../../../bench/verilog/wb_master_behavioral.v
+../../../bench/verilog/system.v
+../../../bench/verilog/pci_blue_arbiter.v
+../../../bench/verilog/pci_bus_monitor.v
+../../../bench/verilog/pci_behaviorial_device.v
+../../../bench/verilog/pci_behaviorial_master.v
+../../../bench/verilog/pci_behaviorial_target.v
+../../../bench/verilog/wb_slave_behavioral.v
+../../../bench/verilog/wb_bus_mon.v
+../../../bench/verilog/pci_behavioral_iack_target.v
+../../../bench/verilog/pci_unsupported_commands_master.v
ncvlog_sim.args
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: hdl.var
===================================================================
--- hdl.var (nonexistent)
+++ hdl.var (revision 154)
@@ -0,0 +1,9 @@
+#
+# hdl.var: Defines variables used by the INCA tools.
+# Created by ncprep on Sat Aug 4 10:51:23 2001
+#
+
+softinclude $CDS_INST_DIR/tools/inca/files/hdl.var
+
+define LIB_MAP ( $LIB_MAP, + => worklib )
+define VIEW_MAP ( $VIEW_MAP, .v => v)
hdl.var
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncvlog_artisan.scr
===================================================================
--- ncvlog_artisan.scr (nonexistent)
+++ ncvlog_artisan.scr (revision 154)
@@ -0,0 +1 @@
+ncvlog -cdslib ../bin/cds.lib -hdlvar ../bin/hdl.var -logfile ../log/ncvlog_artisan.log -update -messages $ARTISAN/art_hsdp_256x40.v
ncvlog_artisan.scr
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: nc_xilinx_artisan.scr
===================================================================
--- nc_xilinx_artisan.scr (nonexistent)
+++ nc_xilinx_artisan.scr (revision 154)
@@ -0,0 +1,76 @@
+//+ncelabargs+"-timescale 1ns/10ps"
++libext+.v
+// RTL sources
+../../../rtl/verilog/pci_parity_check.v
+../../../rtl/verilog/pci_target_unit.v
+../../../rtl/verilog/wb_addr_mux.v
+../../../rtl/verilog/cbe_en_crit.v
+../../../rtl/verilog/fifo_control.v
+../../../rtl/verilog/out_reg.v
+../../../rtl/verilog/pci_tpram.v
+../../../rtl/verilog/wb_master.v
+../../../rtl/verilog/conf_cyc_addr_dec.v
+../../../rtl/verilog/frame_crit.v
+../../../rtl/verilog/pci_target32_clk_en.v
+../../../rtl/verilog/pciw_fifo_control.v
+../../../rtl/verilog/wb_slave.v
+../../../rtl/verilog/conf_space.v
+../../../rtl/verilog/frame_en_crit.v
+../../../rtl/verilog/par_crit.v
+../../../rtl/verilog/pci_target32_ctrl_en_crit.v
+../../../rtl/verilog/pciw_pcir_fifos.v
+../../../rtl/verilog/wb_slave_unit.v
+../../../rtl/verilog/frame_load_crit.v
+../../../rtl/verilog/pci_bridge32.v
+../../../rtl/verilog/pci_target32_devs_crit.v
+../../../rtl/verilog/perr_crit.v
+../../../rtl/verilog/wbr_fifo_control.v
+../../../rtl/verilog/cur_out_reg.v
+../../../rtl/verilog/pci_decoder.v
+../../../rtl/verilog/pci_target32_interface.v
+../../../rtl/verilog/perr_en_crit.v
+../../../rtl/verilog/wbw_fifo_control.v
+../../../rtl/verilog/decoder.v
+../../../rtl/verilog/pci_in_reg.v
+../../../rtl/verilog/pci_target32_load_crit.v
+../../../rtl/verilog/serr_crit.v
+../../../rtl/verilog/wbw_wbr_fifos.v
+../../../rtl/verilog/delayed_sync.v
+../../../rtl/verilog/irdy_out_crit.v
+../../../rtl/verilog/pci_io_mux.v
+../../../rtl/verilog/pci_io_mux_ad_en_crit.v
+../../../rtl/verilog/pci_io_mux_ad_load_crit.v
+../../../rtl/verilog/pci_target32_sm.v
+../../../rtl/verilog/serr_en_crit.v
+../../../rtl/verilog/delayed_write_reg.v
+../../../rtl/verilog/mas_ad_en_crit.v
+../../../rtl/verilog/mas_ad_load_crit.v
+../../../rtl/verilog/pci_master32_sm.v
+../../../rtl/verilog/pci_target32_stop_crit.v
+../../../rtl/verilog/synchronizer_flop.v
+../../../rtl/verilog/async_reset_flop.v
+../../../rtl/verilog/mas_ch_state_crit.v
+../../../rtl/verilog/pci_master32_sm_if.v
+../../../rtl/verilog/pci_target32_trdy_crit.v
+../../../rtl/verilog/top.v
+../../../rtl/verilog/pci_rst_int.v
+../../../rtl/verilog/sync_module.v
+../../../rtl/verilog/wb_tpram.v
+// Sim sources
+../../../bench/verilog/wb_master32.v
+../../../bench/verilog/wb_master_behavioral.v
+../../../bench/verilog/system.v
+../../../bench/verilog/pci_blue_arbiter.v
+../../../bench/verilog/pci_bus_monitor.v
+../../../bench/verilog/pci_behaviorial_device.v
+../../../bench/verilog/pci_behaviorial_master.v
+../../../bench/verilog/pci_behaviorial_target.v
+../../../bench/verilog/wb_slave_behavioral.v
+../../../bench/verilog/wb_bus_mon.v
+../../../bench/verilog/wb_slave32.v
+../../../bench/verilog/pci_behavioral_iack_target.v
+../../../bench/verilog/pci_unsupported_commands_master.v
+// Libs
+../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
+../../../../lib/xilinx/lib/glbl/glbl.v
+../../../../lib/artisan/art_hsdp_256x40.v
\ No newline at end of file
nc_xilinx_artisan.scr
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncsim.args
===================================================================
--- ncsim.args (nonexistent)
+++ ncsim.args (revision 154)
@@ -0,0 +1,6 @@
+-cdslib ../bin/cds.lib
+-hdlvar ../bin/hdl.var
+-logfile ../log/ncsim.log
+-messages
+-input ../bin/ncsim.rc
+worklib.bridge32:fun
ncsim.args
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncvlog_artisan.args
===================================================================
--- ncvlog_artisan.args (nonexistent)
+++ ncvlog_artisan.args (revision 154)
@@ -0,0 +1 @@
+../../../../lib/artisan/art_hsdp_256x40.v
ncvlog_artisan.args
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncvlog_rtl.args
===================================================================
--- ncvlog_rtl.args (nonexistent)
+++ ncvlog_rtl.args (revision 154)
@@ -0,0 +1,59 @@
+-cdslib ../bin/cds.lib
+-hdlvar ../bin/hdl.var
+-logfile ../log/ncvlog_rtl.log
+-update
+-messages
+-INCDIR ../../../rtl/verilog
+../../../rtl/verilog/pci_parity_check.v
+../../../rtl/verilog/pci_target_unit.v
+../../../rtl/verilog/wb_addr_mux.v
+../../../rtl/verilog/cbe_en_crit.v
+../../../rtl/verilog/fifo_control.v
+../../../rtl/verilog/out_reg.v
+../../../rtl/verilog/pci_tpram.v
+../../../rtl/verilog/wb_master.v
+../../../rtl/verilog/conf_cyc_addr_dec.v
+../../../rtl/verilog/frame_crit.v
+../../../rtl/verilog/pci_target32_clk_en.v
+../../../rtl/verilog/pciw_fifo_control.v
+../../../rtl/verilog/wb_slave.v
+../../../rtl/verilog/conf_space.v
+../../../rtl/verilog/frame_en_crit.v
+../../../rtl/verilog/par_crit.v
+../../../rtl/verilog/pciw_pcir_fifos.v
+../../../rtl/verilog/wb_slave_unit.v
+../../../rtl/verilog/frame_load_crit.v
+../../../rtl/verilog/pci_bridge32.v
+../../../rtl/verilog/pci_target32_devs_crit.v
+../../../rtl/verilog/perr_crit.v
+../../../rtl/verilog/wbr_fifo_control.v
+../../../rtl/verilog/cur_out_reg.v
+../../../rtl/verilog/pci_decoder.v
+../../../rtl/verilog/pci_target32_interface.v
+../../../rtl/verilog/perr_en_crit.v
+../../../rtl/verilog/wbw_fifo_control.v
+../../../rtl/verilog/decoder.v
+../../../rtl/verilog/pci_in_reg.v
+../../../rtl/verilog/serr_crit.v
+../../../rtl/verilog/wbw_wbr_fifos.v
+../../../rtl/verilog/delayed_sync.v
+../../../rtl/verilog/irdy_out_crit.v
+../../../rtl/verilog/pci_io_mux.v
+../../../rtl/verilog/pci_io_mux_ad_en_crit.v
+../../../rtl/verilog/pci_io_mux_ad_load_crit.v
+../../../rtl/verilog/pci_target32_sm.v
+../../../rtl/verilog/serr_en_crit.v
+../../../rtl/verilog/delayed_write_reg.v
+../../../rtl/verilog/mas_ad_en_crit.v
+../../../rtl/verilog/mas_ad_load_crit.v
+../../../rtl/verilog/pci_master32_sm.v
+../../../rtl/verilog/pci_target32_stop_crit.v
+../../../rtl/verilog/synchronizer_flop.v
+../../../rtl/verilog/async_reset_flop.v
+../../../rtl/verilog/mas_ch_state_crit.v
+../../../rtl/verilog/pci_master32_sm_if.v
+../../../rtl/verilog/pci_target32_trdy_crit.v
+../../../rtl/verilog/top.v
+../../../rtl/verilog/pci_rst_int.v
+../../../rtl/verilog/sync_module.v
+../../../rtl/verilog/wb_tpram.v
ncvlog_rtl.args
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: nc_artisan.scr
===================================================================
--- nc_artisan.scr (nonexistent)
+++ nc_artisan.scr (revision 154)
@@ -0,0 +1,76 @@
+//+ncelabargs+"-timescale 1ns/10ps"
++libext+.v
+// RTL sources
+../../../rtl/verilog/pci_parity_check.v
+../../../rtl/verilog/pci_target_unit.v
+../../../rtl/verilog/wb_addr_mux.v
+../../../rtl/verilog/cbe_en_crit.v
+../../../rtl/verilog/fifo_control.v
+../../../rtl/verilog/out_reg.v
+../../../rtl/verilog/pci_tpram.v
+../../../rtl/verilog/wb_master.v
+../../../rtl/verilog/conf_cyc_addr_dec.v
+../../../rtl/verilog/frame_crit.v
+../../../rtl/verilog/pci_target32_clk_en.v
+../../../rtl/verilog/pciw_fifo_control.v
+../../../rtl/verilog/wb_slave.v
+../../../rtl/verilog/conf_space.v
+../../../rtl/verilog/frame_en_crit.v
+../../../rtl/verilog/par_crit.v
+../../../rtl/verilog/pci_target32_ctrl_en_crit.v
+../../../rtl/verilog/pciw_pcir_fifos.v
+../../../rtl/verilog/wb_slave_unit.v
+../../../rtl/verilog/frame_load_crit.v
+../../../rtl/verilog/pci_bridge32.v
+../../../rtl/verilog/pci_target32_devs_crit.v
+../../../rtl/verilog/perr_crit.v
+../../../rtl/verilog/wbr_fifo_control.v
+../../../rtl/verilog/cur_out_reg.v
+../../../rtl/verilog/pci_decoder.v
+../../../rtl/verilog/pci_target32_interface.v
+../../../rtl/verilog/perr_en_crit.v
+../../../rtl/verilog/wbw_fifo_control.v
+../../../rtl/verilog/decoder.v
+../../../rtl/verilog/pci_in_reg.v
+../../../rtl/verilog/pci_target32_load_crit.v
+../../../rtl/verilog/serr_crit.v
+../../../rtl/verilog/wbw_wbr_fifos.v
+../../../rtl/verilog/delayed_sync.v
+../../../rtl/verilog/irdy_out_crit.v
+../../../rtl/verilog/pci_io_mux.v
+../../../rtl/verilog/pci_io_mux_ad_en_crit.v
+../../../rtl/verilog/pci_io_mux_ad_load_crit.v
+../../../rtl/verilog/pci_target32_sm.v
+../../../rtl/verilog/serr_en_crit.v
+../../../rtl/verilog/delayed_write_reg.v
+../../../rtl/verilog/mas_ad_en_crit.v
+../../../rtl/verilog/mas_ad_load_crit.v
+../../../rtl/verilog/pci_master32_sm.v
+../../../rtl/verilog/pci_target32_stop_crit.v
+../../../rtl/verilog/synchronizer_flop.v
+../../../rtl/verilog/async_reset_flop.v
+../../../rtl/verilog/mas_ch_state_crit.v
+../../../rtl/verilog/pci_master32_sm_if.v
+../../../rtl/verilog/pci_target32_trdy_crit.v
+../../../rtl/verilog/top.v
+../../../rtl/verilog/pci_rst_int.v
+../../../rtl/verilog/sync_module.v
+../../../rtl/verilog/wb_tpram.v
+// Sim sources
+../../../bench/verilog/wb_master32.v
+../../../bench/verilog/wb_master_behavioral.v
+../../../bench/verilog/system.v
+../../../bench/verilog/pci_blue_arbiter.v
+../../../bench/verilog/pci_bus_monitor.v
+../../../bench/verilog/pci_behaviorial_device.v
+../../../bench/verilog/pci_behaviorial_master.v
+../../../bench/verilog/pci_behaviorial_target.v
+../../../bench/verilog/wb_slave_behavioral.v
+../../../bench/verilog/wb_bus_mon.v
+../../../bench/verilog/wb_slave32.v
+../../../bench/verilog/pci_behavioral_iack_target.v
+../../../bench/verilog/pci_unsupported_commands_master.v
+// Libs
+//../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
+//../../../../lib/xilinx/lib/glbl/glbl.v
+../../../../lib/artisan/art_hsdp_256x40.v
\ No newline at end of file
nc_artisan.scr
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncvlog_xilinx.scr
===================================================================
--- ncvlog_xilinx.scr (nonexistent)
+++ ncvlog_xilinx.scr (revision 154)
@@ -0,0 +1 @@
+ncvlog -cdslib ../bin/cds.lib -hdlvar ../bin/hdl.var -logfile ../log/ncvlog_xilinx.log -update -messages $XILINX/lib/unisims/RAMB4_S16_S16.v $XILINX/lib/glbl/glbl.v $XILINX/lib/unisims/RAM16X1D.v
ncvlog_xilinx.scr
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncvlog_xilinx.args
===================================================================
--- ncvlog_xilinx.args (nonexistent)
+++ ncvlog_xilinx.args (revision 154)
@@ -0,0 +1,8 @@
+-cdslib ../bin/cds.lib
+-hdlvar ../bin/hdl.var
+-logfile ../log/ncvlog_xilinx.log
+-update
+-messages
+../../../../lib/xilinx/lib/glbl/glbl.v
+../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
+../../../../lib/xilinx/lib/unisims/RAM16X1D.v
ncvlog_xilinx.args
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: cds.lib
===================================================================
--- cds.lib (nonexistent)
+++ cds.lib (revision 154)
@@ -0,0 +1,2 @@
+define worklib ../bin/INCA_libs/worklib
+include $CDS_INST_DIR/tools/inca/files/cds.lib
cds.lib
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property