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https://opencores.org/ocsvn/pci/pci/trunk
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/pci/tags/rel_13/apps/test/syn
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Rev 135 → Rev 154
/synplify/pci_test_top_2clks.sdc
0,0 → 1,262
# Synplicity, Inc. constraint file |
# /shared/projects/pci/mihad/pci_new_bist/apps/test/syn/synplify/pci_test_top_2clks.sdc |
# Written on Tue Dec 16 13:13:13 2003 |
# by Synplify Pro, 7.3.4 Scope Editor |
|
# |
# Clocks |
# |
define_clock -name {pci_clk_pad_i} -period 30.000 -clockgroup pci_clkgrp |
define_clock -name {i_bufg_wb_clk} -freq 50.000 -clockgroup clk_clkgrp |
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# |
# Clock to Clock |
# |
|
# |
# Inputs/Outputs |
# |
define_input_delay {pci_devsel_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_trdy_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_stop_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_idsel_pad_i} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_frame_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_irdy_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_gnt_pad_i} 20.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_par_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_perr_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad0_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad1_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad2_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad3_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad4_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad5_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad6_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad7_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad8_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad9_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad10_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad11_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad12_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad13_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad14_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad15_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad16_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad17_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad18_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad19_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad20_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad21_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad22_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad23_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad24_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad25_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad26_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad27_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad28_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad29_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad30_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_ad31_pad_io} 23.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_cbe0_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_cbe1_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_cbe2_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r} |
define_input_delay {pci_cbe3_pad_io} 23.00 -improve 0.00 -route 2.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad0_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad1_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad2_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad3_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad4_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad5_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad6_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad7_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad8_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad9_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad10_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad11_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad12_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad13_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad14_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad15_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad16_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad17_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad18_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad19_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad20_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad21_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad22_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad23_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad24_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad25_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad26_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad27_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad28_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad29_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad30_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_ad31_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_cbe0_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_cbe1_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_cbe2_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_cbe3_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_devsel_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_trdy_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_stop_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_frame_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_irdy_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_req_pad_o} 18.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_par_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_perr_pad_io} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
define_output_delay {pci_serr_pad_o} 19.00 -improve 0.00 -route 0.00 -ref {pci_clk_pad_i:r} |
|
# |
# Registers |
# |
define_reg_output_delay {*sync_data_out*} -route 10.00 |
|
# |
# Multicycle Path |
# |
|
# |
# False Path |
# |
|
# |
# Delay Path |
# |
|
# |
# Attributes |
# |
define_attribute {pci_clk_pad_i} xc_loc {P185} |
define_attribute {pci_rst_pad_i} xc_loc {P199} |
define_attribute {pci_gnt_pad_i} xc_loc {P200} |
define_attribute {pci_req_pad_o} xc_loc {P201} |
define_attribute {pci_ad31_pad_io} xc_loc {P203} |
define_attribute {pci_ad30_pad_io} xc_loc {P204} |
define_attribute {pci_ad29_pad_io} xc_loc {P205} |
define_attribute {pci_ad28_pad_io} xc_loc {P206} |
define_attribute {pci_ad27_pad_io} xc_loc {P3} |
define_attribute {pci_ad26_pad_io} xc_loc {P4} |
define_attribute {pci_ad25_pad_io} xc_loc {P5} |
define_attribute {pci_ad24_pad_io} xc_loc {P6} |
define_attribute {pci_cbe3_pad_io} xc_loc {P8} |
define_attribute {pci_idsel_pad_i} xc_loc {P9} |
define_attribute {pci_ad23_pad_io} xc_loc {P10} |
define_attribute {pci_ad22_pad_io} xc_loc {P14} |
define_attribute {pci_ad21_pad_io} xc_loc {P15} |
define_attribute {pci_ad20_pad_io} xc_loc {P16} |
define_attribute {pci_ad19_pad_io} xc_loc {P17} |
define_attribute {pci_ad18_pad_io} xc_loc {P18} |
define_attribute {pci_ad17_pad_io} xc_loc {P20} |
define_attribute {pci_ad16_pad_io} xc_loc {P21} |
define_attribute {pci_cbe2_pad_io} xc_loc {P22} |
define_attribute {pci_frame_pad_io} xc_loc {P23} |
define_attribute {pci_irdy_pad_io} xc_loc {P24} |
define_attribute {pci_trdy_pad_io} xc_loc {P27} |
define_attribute {pci_devsel_pad_io} xc_loc {P29} |
define_attribute {pci_stop_pad_io} xc_loc {P30} |
define_attribute {pci_perr_pad_io} xc_loc {P31} |
define_attribute {pci_serr_pad_o} xc_loc {P33} |
define_attribute {pci_par_pad_io} xc_loc {P34} |
define_attribute {pci_cbe1_pad_io} xc_loc {P35} |
define_attribute {pci_ad15_pad_io} xc_loc {P36} |
define_attribute {pci_ad14_pad_io} xc_loc {P37} |
define_attribute {pci_ad13_pad_io} xc_loc {P41} |
define_attribute {pci_ad12_pad_io} xc_loc {P42} |
define_attribute {pci_ad11_pad_io} xc_loc {P43} |
define_attribute {pci_ad10_pad_io} xc_loc {P45} |
define_attribute {pci_ad9_pad_io} xc_loc {P46} |
define_attribute {pci_ad8_pad_io} xc_loc {P47} |
define_attribute {pci_cbe0_pad_io} xc_loc {P48} |
define_attribute {pci_ad7_pad_io} xc_loc {P49} |
define_attribute {pci_ad6_pad_io} xc_loc {P57} |
define_attribute {pci_ad5_pad_io} xc_loc {P58} |
define_attribute {pci_ad4_pad_io} xc_loc {P59} |
define_attribute {pci_ad3_pad_io} xc_loc {P61} |
define_attribute {pci_ad2_pad_io} xc_loc {P62} |
define_attribute {pci_ad1_pad_io} xc_loc {P63} |
define_attribute {pci_ad0_pad_io} xc_loc {P67} |
define_attribute {clk_pad_i} xc_loc {P182} |
define_global_attribute syn_useioff {1} |
define_attribute -disable {v:work.pci_cbe_en_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_frame_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_frame_en_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_frame_load_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_irdy_out_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_mas_ad_en_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_mas_ad_load_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_mas_ch_state_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_par_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_io_mux_ad_en_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_io_mux_ad_load_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_target32_clk_en} syn_hier {hard} |
define_attribute -disable {v:work.pci_target32_devs_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_target32_stop_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_target32_trdy_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_perr_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_perr_en_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_serr_crit} syn_hier {hard} |
define_attribute -disable {v:work.pci_serr_en_crit} syn_hier {hard} |
define_attribute {pci_gnt_pad_i} xc_padtype {IBUF_PCI33_5} |
define_attribute {pci_req_pad_o} xc_padtype {OBUFT_PCI33_5} |
define_attribute {pci_ad31_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad30_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad29_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad28_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad27_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad26_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad25_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad24_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_cbe3_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_idsel_pad_i} xc_padtype {IBUF_PCI33_5} |
define_attribute {pci_ad23_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad22_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad21_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad20_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad19_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad18_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad17_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad16_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_cbe2_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_frame_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_irdy_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_trdy_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_devsel_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_stop_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_perr_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_serr_pad_o} xc_padtype {OBUFT_PCI33_5} |
define_attribute {pci_par_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_cbe1_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad15_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad14_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad13_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad12_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad11_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad10_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad9_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad8_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_cbe0_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad7_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad6_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad5_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad4_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad3_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad2_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad1_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute {pci_ad0_pad_io} xc_padtype {IOBUF_PCI33_5} |
define_attribute -disable {v:work.synchronizer_flop_1_0} syn_hier {hard} |
define_attribute -disable {v:work.synchronizer_flop_3_0} syn_hier {hard} |
define_attribute -disable {v:work.synchronizer_flop_4_0} syn_hier {hard} |
define_attribute -disable {v:work.synchronizer_flop_4_1} syn_hier {hard} |
define_attribute -disable {v:work.synchronizer_flop_4_3} syn_hier {hard} |
define_attribute -disable {v:work.synchronizer_flop_6_0} syn_hier {hard} |
define_attribute -disable {v:work.synchronizer_flop_7_0} syn_hier {hard} |
define_attribute -disable {v:work.synchronizer_flop_7_3} syn_hier {hard} |
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# |
# Compile Points |
# |
|
# |
# Other Constraints |
# |
/synplify/pci_test_top.prj
0,0 → 1,116
#-- Synplicity, Inc. |
#-- Version 7.3.4 |
#-- Project file /shared/projects/pci/mihad/pci_new_bist/apps/test/syn/synplify/pci_test_top.prj |
#-- Written on Tue Dec 16 12:47:51 2003 |
|
|
#add_file options |
add_file -verilog "$LIB/xilinx/virtex.v" |
add_file -verilog "../../../../rtl/verilog/pci_async_reset_flop.v" |
add_file -verilog "../../rtl/verilog/pci_bridge32.v" |
add_file -verilog "../../../../rtl/verilog/pci_cbe_en_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_conf_cyc_addr_dec.v" |
add_file -verilog "../../../../rtl/verilog/pci_conf_space.v" |
add_file -verilog "../../../../rtl/verilog/pci_cur_out_reg.v" |
add_file -verilog "../../../../rtl/verilog/pci_delayed_sync.v" |
add_file -verilog "../../../../rtl/verilog/pci_delayed_write_reg.v" |
add_file -verilog "../../../../rtl/verilog/pci_frame_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_frame_en_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_frame_load_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_in_reg.v" |
add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_en_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_load_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_io_mux.v" |
add_file -verilog "../../../../rtl/verilog/pci_irdy_out_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_mas_ad_en_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_mas_ad_load_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_mas_ch_state_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_master32_sm_if.v" |
add_file -verilog "../../../../rtl/verilog/pci_master32_sm.v" |
add_file -verilog "../../../../rtl/verilog/pci_out_reg.v" |
add_file -verilog "../../../../rtl/verilog/pci_par_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_parity_check.v" |
add_file -verilog "../../../../rtl/verilog/pci_pci_decoder.v" |
add_file -verilog "../../../../rtl/verilog/pci_pcir_fifo_control.v" |
add_file -verilog "../../../../rtl/verilog/pci_pci_tpram.v" |
add_file -verilog "../../../../rtl/verilog/pci_pciw_fifo_control.v" |
add_file -verilog "../../../../rtl/verilog/pci_pciw_pcir_fifos.v" |
add_file -verilog "../../../../rtl/verilog/pci_perr_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_perr_en_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_ram_16x40d.v" |
add_file -verilog "../../../../rtl/verilog/pci_rst_int.v" |
add_file -verilog "../../../../rtl/verilog/pci_serr_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_serr_en_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_sync_module.v" |
add_file -verilog "../../../../rtl/verilog/pci_target32_clk_en.v" |
add_file -verilog "../../../../rtl/verilog/pci_target32_devs_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_target32_interface.v" |
add_file -verilog "../../../../rtl/verilog/pci_target32_sm.v" |
add_file -verilog "../../../../rtl/verilog/pci_target32_stop_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_target32_trdy_crit.v" |
add_file -verilog "../../../../rtl/verilog/pci_target_unit.v" |
add_file -verilog "../../../../rtl/verilog/pci_wb_addr_mux.v" |
add_file -verilog "../../../../rtl/verilog/pci_wb_decoder.v" |
add_file -verilog "../../../../rtl/verilog/pci_wb_master.v" |
add_file -verilog "../../../../rtl/verilog/pci_wbr_fifo_control.v" |
add_file -verilog "../../../../rtl/verilog/pci_wb_slave_unit.v" |
add_file -verilog "../../../../rtl/verilog/pci_wb_slave.v" |
add_file -verilog "../../../../rtl/verilog/pci_wb_tpram.v" |
add_file -verilog "../../../../rtl/verilog/pci_wbw_fifo_control.v" |
add_file -verilog "../../../../rtl/verilog/pci_wbw_wbr_fifos.v" |
add_file -verilog "../../../../rtl/verilog/pci_synchronizer_flop.v" |
add_file -constraint "pci_test_top_2clks.sdc" |
add_file -verilog "../../../../rtl/verilog/pci_wbs_wbb3_2_wbb2.v" |
add_file -verilog "../../rtl/verilog/test.v" |
add_file -verilog "../../rtl/verilog/pci_test_top_2clks.v" |
|
|
#implementation: "rev_1" |
impl -add rev_1 |
|
#device options |
set_option -technology SPARTAN2 |
set_option -part XC2S200 |
set_option -package PQ208 |
set_option -speed_grade -6 |
|
#compilation/mapping options |
set_option -default_enum_encoding default |
set_option -symbolic_fsm_compiler 0 |
set_option -resource_sharing 1 |
set_option -use_fsm_explorer 0 |
|
#map options |
set_option -frequency 50.000 |
set_option -fanout_limit 16 |
set_option -disable_io_insertion 0 |
set_option -pipe 0 |
set_option -fixgatedclocks 0 |
set_option -retiming 0 |
set_option -modular 0 |
set_option -update_models_cp 0 |
set_option -verification_mode 0 |
|
#simulation options |
set_option -write_verilog 0 |
set_option -write_vhdl 0 |
|
#automatic place and route (vendor) options |
set_option -write_apr_constraint 1 |
|
#set result format/file last |
project -result_file "rev_1/pci_test_top.edf" |
|
#implementation attributes |
set_option -vlog_std v2001 |
|
#implementation attributes |
set_option -random_floorplan 0 |
set_option -popfeed 1 |
set_option -constprop 1 |
set_option -createhierarchy 0 |
set_option -floorplan "" |
set_option -nfilter_user_path "" |
set_option -pin_assignment "" |
set_option -include_path "../../rtl/verilog/;../../../../rtl/verilog/" |
impl -active "rev_1" |
synplify/pci_test_top.prj
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: synplify/pci_test_top.ucf
===================================================================
--- synplify/pci_test_top.ucf (nonexistent)
+++ synplify/pci_test_top.ucf (revision 154)
@@ -0,0 +1,5 @@
+INST "i_clkdll" CLKDV_DIVIDE = 2.0 ;
+INST "i_clkdll" LOC = DLL0 ;
+INST "i_bufg_clk0" LOC = GCLKBUF0 ;
+INST "i_bufg_wb_clk" LOC = GCLKBUF1 ;
+NET "pci_clk_pad_i" TNM_NET = "pci_clk_pad_i";
\ No newline at end of file
Index: synplify/pci_test_top_1clk.sdc
===================================================================
--- synplify/pci_test_top_1clk.sdc (nonexistent)
+++ synplify/pci_test_top_1clk.sdc (revision 154)
@@ -0,0 +1,253 @@
+# Synplicity, Inc. constraint file
+# /shared/projects/pci/mihad/pci/apps/test/syn/synplify/pci_test_top.sdc
+# Written on Thu Apr 17 16:11:16 2003
+# by Amplify, Amplify 3.1 Scope Editor
+
+#
+# Clocks
+#
+define_clock -name {pci_clk_pad_i} -period 30.000 -clockgroup pci_clkgrp
+
+#
+# Inputs/Outputs
+#
+define_input_delay {pci_devsel_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_trdy_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_stop_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_idsel_pad_i} 23.00 -route 2.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_frame_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_irdy_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_gnt_pad_i} 20.00 -route 2.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_par_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_perr_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad0_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad1_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad2_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad3_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad4_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad5_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad6_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad7_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad8_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad9_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad10_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad11_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad12_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad13_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad14_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad15_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad16_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad17_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad18_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad19_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad20_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad21_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad22_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad23_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad24_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad25_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad26_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad27_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad28_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad29_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad30_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_ad31_pad_io} 23.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_cbe0_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_cbe1_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_cbe2_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
+define_input_delay {pci_cbe3_pad_io} 23.00 -route 2.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad0_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad1_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad2_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad3_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad4_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad5_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad6_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad7_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad8_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad9_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad10_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad11_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad12_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad13_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad14_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad15_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad16_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad17_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad18_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad19_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad20_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad21_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad22_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad23_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad24_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad25_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad26_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad27_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad28_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad29_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad30_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_ad31_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_cbe0_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_cbe1_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_cbe2_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_cbe3_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_devsel_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_trdy_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_stop_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_frame_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_irdy_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_req_pad_o} 18.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_par_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_perr_pad_io} 19.00 -ref pci_clk_pad_i:r
+define_output_delay {pci_serr_pad_o} 19.00 -ref pci_clk_pad_i:r
+
+#
+# Registers
+#
+define_reg_output_delay {*sync_data_out*} -route 10.00
+
+#
+# Multicycle Path
+#
+
+#
+# False Path
+#
+
+#
+# Attributes
+#
+define_attribute {pci_clk_pad_i} xc_loc {P185}
+define_attribute {pci_rst_pad_i} xc_loc {P199}
+define_attribute {pci_gnt_pad_i} xc_loc {P200}
+define_attribute {pci_req_pad_o} xc_loc {P201}
+define_attribute {pci_ad31_pad_io} xc_loc {P203}
+define_attribute {pci_ad30_pad_io} xc_loc {P204}
+define_attribute {pci_ad29_pad_io} xc_loc {P205}
+define_attribute {pci_ad28_pad_io} xc_loc {P206}
+define_attribute {pci_ad27_pad_io} xc_loc {P3}
+define_attribute {pci_ad26_pad_io} xc_loc {P4}
+define_attribute {pci_ad25_pad_io} xc_loc {P5}
+define_attribute {pci_ad24_pad_io} xc_loc {P6}
+define_attribute {pci_cbe3_pad_io} xc_loc {P8}
+define_attribute {pci_idsel_pad_i} xc_loc {P9}
+define_attribute {pci_ad23_pad_io} xc_loc {P10}
+define_attribute {pci_ad22_pad_io} xc_loc {P14}
+define_attribute {pci_ad21_pad_io} xc_loc {P15}
+define_attribute {pci_ad20_pad_io} xc_loc {P16}
+define_attribute {pci_ad19_pad_io} xc_loc {P17}
+define_attribute {pci_ad18_pad_io} xc_loc {P18}
+define_attribute {pci_ad17_pad_io} xc_loc {P20}
+define_attribute {pci_ad16_pad_io} xc_loc {P21}
+define_attribute {pci_cbe2_pad_io} xc_loc {P22}
+define_attribute {pci_frame_pad_io} xc_loc {P23}
+define_attribute {pci_irdy_pad_io} xc_loc {P24}
+define_attribute {pci_trdy_pad_io} xc_loc {P27}
+define_attribute {pci_devsel_pad_io} xc_loc {P29}
+define_attribute {pci_stop_pad_io} xc_loc {P30}
+define_attribute {pci_perr_pad_io} xc_loc {P31}
+define_attribute {pci_serr_pad_o} xc_loc {P33}
+define_attribute {pci_par_pad_io} xc_loc {P34}
+define_attribute {pci_cbe1_pad_io} xc_loc {P35}
+define_attribute {pci_ad15_pad_io} xc_loc {P36}
+define_attribute {pci_ad14_pad_io} xc_loc {P37}
+define_attribute {pci_ad13_pad_io} xc_loc {P41}
+define_attribute {pci_ad12_pad_io} xc_loc {P42}
+define_attribute {pci_ad11_pad_io} xc_loc {P43}
+define_attribute {pci_ad10_pad_io} xc_loc {P45}
+define_attribute {pci_ad9_pad_io} xc_loc {P46}
+define_attribute {pci_ad8_pad_io} xc_loc {P47}
+define_attribute {pci_cbe0_pad_io} xc_loc {P48}
+define_attribute {pci_ad7_pad_io} xc_loc {P49}
+define_attribute {pci_ad6_pad_io} xc_loc {P57}
+define_attribute {pci_ad5_pad_io} xc_loc {P58}
+define_attribute {pci_ad4_pad_io} xc_loc {P59}
+define_attribute {pci_ad3_pad_io} xc_loc {P61}
+define_attribute {pci_ad2_pad_io} xc_loc {P62}
+define_attribute {pci_ad1_pad_io} xc_loc {P63}
+define_attribute {pci_ad0_pad_io} xc_loc {P67}
+define_attribute {clk_pad_i} xc_loc {P182}
+define_global_attribute syn_useioff {1}
+define_attribute {v:work.pci_cbe_en_crit} syn_hier {hard}
+define_attribute {v:work.pci_frame_crit} syn_hier {hard}
+define_attribute {v:work.pci_frame_en_crit} syn_hier {hard}
+define_attribute {v:work.pci_frame_load_crit} syn_hier {hard}
+define_attribute {v:work.pci_irdy_out_crit} syn_hier {hard}
+define_attribute {v:work.pci_mas_ad_en_crit} syn_hier {hard}
+define_attribute {v:work.pci_mas_ad_load_crit} syn_hier {hard}
+define_attribute {v:work.pci_mas_ch_state_crit} syn_hier {hard}
+define_attribute {v:work.pci_par_crit} syn_hier {hard}
+define_attribute {v:work.pci_io_mux_ad_en_crit} syn_hier {hard}
+define_attribute {v:work.pci_io_mux_ad_load_crit} syn_hier {hard}
+define_attribute {v:work.pci_target32_clk_en} syn_hier {hard}
+define_attribute {v:work.pci_target32_devs_crit} syn_hier {hard}
+define_attribute {v:work.pci_target32_stop_crit} syn_hier {hard}
+define_attribute {v:work.pci_target32_trdy_crit} syn_hier {hard}
+define_attribute {v:work.pci_perr_crit} syn_hier {hard}
+define_attribute {v:work.pci_perr_en_crit} syn_hier {hard}
+define_attribute {v:work.pci_serr_crit} syn_hier {hard}
+define_attribute {v:work.pci_serr_en_crit} syn_hier {hard}
+define_attribute {pci_gnt_pad_i} xc_padtype {IBUF_PCI33_5}
+define_attribute {pci_req_pad_o} xc_padtype {OBUFT_PCI33_5}
+define_attribute {pci_ad31_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad30_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad29_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad28_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad27_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad26_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad25_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad24_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_cbe3_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_idsel_pad_i} xc_padtype {IBUF_PCI33_5}
+define_attribute {pci_ad23_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad22_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad21_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad20_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad19_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad18_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad17_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad16_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_cbe2_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_frame_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_irdy_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_trdy_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_devsel_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_stop_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_perr_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_serr_pad_o} xc_padtype {OBUFT_PCI33_5}
+define_attribute {pci_par_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_cbe1_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad15_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad14_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad13_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad12_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad11_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad10_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad9_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad8_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_cbe0_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad7_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad6_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad5_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad4_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad3_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad2_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad1_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {pci_ad0_pad_io} xc_padtype {IOBUF_PCI33_5}
+define_attribute {v:work.synchronizer_flop_1_0} syn_hier {hard}
+define_attribute {v:work.synchronizer_flop_3_0} syn_hier {hard}
+define_attribute {v:work.synchronizer_flop_4_0} syn_hier {hard}
+define_attribute {v:work.synchronizer_flop_4_1} syn_hier {hard}
+define_attribute {v:work.synchronizer_flop_4_3} syn_hier {hard}
+define_attribute {v:work.synchronizer_flop_6_0} syn_hier {hard}
+define_attribute {v:work.synchronizer_flop_7_0} syn_hier {hard}
+define_attribute {v:work.synchronizer_flop_7_3} syn_hier {hard}
+
+#
+# Other Constraints
+#
+
+#
+# Order of waveforms
+#