Subversion Repositories pci

/crt/rtl/verilog/top.v

/crt/rtl/verilog/ssvga_wbm_if.v

/crt/rtl/verilog/pci_user_constants.v

crt/rtl/verilog/pci_user_constants.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: crt/rtl/verilog/ssvga_wbs_if.v =================================================================== --- crt/rtl/verilog/ssvga_wbs_if.v (nonexistent) +++ crt/rtl/verilog/ssvga_wbs_if.v (revision 154) @@ -0,0 +1,177 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Simple Small VGA IP Core //// +//// //// +//// This file is part of the Simple Small VGA project //// +//// //// +//// //// +//// Description //// +//// LITTLE-ENDIAN WISHBONE slave interface. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2001/10/02 15:33:33 mihad +// New project directory structure +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`define SEL_PAL 10 +`define SEL_ADDRESS 2 + +module ssvga_wbs_if( + // Clock and reset + wb_clk_i, wb_rst_i, + + // WISHBONE Slave I/F + wbs_cyc_i, wbs_stb_i, wbs_sel_i, wbs_we_i, + wbs_adr_i, wbs_dat_i, wbs_cab_i, + wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o, + + // Other signals + ssvga_en, pal_wr_en, pal_rd_en, pal_dat, + pix_start_addr +); + +// +// I/O ports +// + +// +// Clock and reset +// +input wb_clk_i; // Pixel Clock +input wb_rst_i; // Reset + +// +// WISHBONE Slave I/F +// +input wbs_cyc_i; +input wbs_stb_i; +input [3:0] wbs_sel_i; +input wbs_we_i; +input [31:0] wbs_adr_i; +input [31:0] wbs_dat_i; +input wbs_cab_i; +output [31:0] wbs_dat_o; +output wbs_ack_o; +output wbs_err_o; +output wbs_rty_o; + +// +// Other signals +// +output ssvga_en; // Global enable +output pal_wr_en; // Palette write enable +output pal_rd_en; // Palette read enable +input [15:0] pal_dat; // Palette data +output [31:2] pix_start_addr ; + +// +// Internal regs and wires +// +reg wbs_ack_o; // WISHBONE ack +reg wbs_err_o; // WISHBONE err +reg [0:0] ctrl_r; // Control register +wire valid_access; // Access to SSVGA + +// +// Control register +// +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + ctrl_r <= #1 1'b0; + else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & !wbs_adr_i[`SEL_ADDRESS]) + ctrl_r <= #1 wbs_dat_i[0]; + +reg [31:2] pix_start_addr ; +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + pix_start_addr <= #1 30'h0000_0000 ; + else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & wbs_adr_i[`SEL_ADDRESS] ) + pix_start_addr <= #1 wbs_dat_i[31:2] ; + +// +// Generate delayed WISHBONE ack/err +// +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + wbs_ack_o <= #1 1'b0; + wbs_err_o <= #1 1'b0; + end + else if (valid_access) begin + wbs_ack_o <= #1 1'b1; + wbs_err_o <= #1 1'b0; + end + else if (wbs_cyc_i & wbs_stb_i) begin + wbs_ack_o <= #1 1'b0; + wbs_err_o <= #1 1'b1; + end + else begin + wbs_ack_o <= #1 1'b0; + wbs_err_o <= #1 1'b0; + end + +// +// Generate WISHBONE output signals +// +reg [31:0] wbs_dat_o ; +always@(wbs_adr_i or pal_dat or ctrl_r or pix_start_addr) +begin + if ( wbs_adr_i[`SEL_PAL] ) + wbs_dat_o = {16'h0000, pal_dat} ; + else + if ( wbs_adr_i[`SEL_ADDRESS] ) + wbs_dat_o = {pix_start_addr, 2'b00} ; + else + wbs_dat_o = {{31{1'b0}}, ctrl_r}; +end + +assign wbs_rty_o = 1'b0; + +// +// Generate other signals +// +assign valid_access = wbs_cyc_i & wbs_stb_i & (wbs_sel_i == 4'b1111); +assign ssvga_en = ctrl_r[0]; +assign pal_wr_en = valid_access & wbs_we_i & wbs_adr_i[`SEL_PAL]; +assign pal_rd_en = valid_access & ~wbs_we_i & wbs_adr_i[`SEL_PAL]; + +endmodule Index: crt/rtl/verilog/ssvga_defines.v =================================================================== --- crt/rtl/verilog/ssvga_defines.v (nonexistent) +++ crt/rtl/verilog/ssvga_defines.v (revision 154) @@ -0,0 +1,75 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Simple Small VGA IP Core //// +//// //// +//// This file is part of the Simple Small VGA project //// +//// //// +//// //// +//// Description //// +//// Definitions. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2001/10/02 15:33:33 mihad +// New project directory structure +// +// + +//`define XILINX_RAMB4 +`define SSVGA_640x480 + +`ifdef SSVGA_640x480 +`define PIXEL_NUM 'd307200 // 383330 +`define SSVGA_HCW 10 +`define SSVGA_VCW 10 +//`define SSVGA_HTOT `SSVGA_HCW'd3178 +//`define SSVGA_HPULSE `SSVGA_HCW'd381 +`define SSVGA_HTOT `SSVGA_HCW'd750 +`define SSVGA_HPULSE `SSVGA_HCW'd90 +`define SSVGA_HFRONTP `SSVGA_HCW'd10 +`define SSVGA_HBACKP `SSVGA_HCW'd10 + +//`define SSVGA_VTOT `SSVGA_VCW'd525 +//`define SSVGA_VPULSE `SSVGA_VCW'd3 +`define SSVGA_VTOT `SSVGA_VCW'd511 +`define SSVGA_VPULSE `SSVGA_VCW'd4 +`define SSVGA_VFRONTP `SSVGA_HCW'd12 +`define SSVGA_VBACKP `SSVGA_HCW'd15 +`define SSVGA_VMCW 17 +`endif + +`define XILINX_RAMB4 \ No newline at end of file Index: crt/rtl/verilog/ssvga_top.v =================================================================== --- crt/rtl/verilog/ssvga_top.v (nonexistent) +++ crt/rtl/verilog/ssvga_top.v (revision 154) @@ -0,0 +1,303 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Simple Small VGA IP Core //// +//// //// +//// This file is part of the Simple Small VGA project //// +//// //// +//// //// +//// Description //// +//// Top level of SSVGA. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2001/10/02 15:33:33 mihad +// New project directory structure +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module ssvga_top( + // Clock and reset + wb_clk_i, wb_rst_i, + + // WISHBONE Master I/F + wbm_cyc_o, wbm_stb_o, wbm_sel_o, wbm_we_o, + wbm_adr_o, wbm_dat_o, wbm_cab_o, + wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i, + + // WISHBONE Slave I/F + wbs_cyc_i, wbs_stb_i, wbs_sel_i, wbs_we_i, + wbs_adr_i, wbs_dat_i, wbs_cab_i, + wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o, + + // Signals to VGA display + pad_hsync_o, pad_vsync_o, pad_rgb_o, led_o +); + +// +// I/O ports +// + +// +// Clock and reset +// +input wb_clk_i; // Write Clock +input wb_rst_i; // Reset + +// +// WISHBONE Master I/F +// +output wbm_cyc_o; +output wbm_stb_o; +output [3:0] wbm_sel_o; +output wbm_we_o; +output [31:0] wbm_adr_o; +output [31:0] wbm_dat_o; +output wbm_cab_o; +input [31:0] wbm_dat_i; +input wbm_ack_i; +input wbm_err_i; +input wbm_rty_i; + +// +// WISHBONE Slave I/F +// +input wbs_cyc_i; +input wbs_stb_i; +input [3:0] wbs_sel_i; +input wbs_we_i; +input [31:0] wbs_adr_i; +input [31:0] wbs_dat_i; +input wbs_cab_i; +output [31:0] wbs_dat_o; +output wbs_ack_o; +output wbs_err_o; +output wbs_rty_o; + +// +// VGA display +// +output pad_hsync_o; // H sync +output pad_vsync_o; // V sync +output [15:0] pad_rgb_o; // Digital RGB data +output led_o; + +// +// Internal wires and regs +// +wire ssvga_en; // Global enable +wire fifo_full; // FIFO full flag +wire fifo_empty; // FIFO empty flag +wire wbm_restart ; // indicator on when WISHBONE master should restart whole screen because of pixel buffer underrun +wire crtc_hblank; // H blank +wire crtc_vblank; // V blank +wire fifo_wr_en; // FIFO write enable +wire fifo_rd_en; // FIFO read enable +wire [31:0] fifo_in; // FIFO input data +wire [7:0] fifo_out; // FIFO output data +//wire [7:0] pal_indx; // Palette index +wire pal_wr_en; // Palette write enable +wire pal_rd_en; // Palette read enable +wire [15:0] pal_pix_dat ; // pixel output from pallete RAM + +reg go ; + +// rgb output assignment - when blank output transmits black pixels, otherwise it transmits pallete data +reg drive_blank_reg ; +always@(posedge wb_clk_i or posedge wb_rst_i) +begin + if ( wb_rst_i ) + drive_blank_reg <= #1 1'b0 ; + else + drive_blank_reg <= #1 ( crtc_hblank || crtc_vblank || ~go ) ; +end + +assign pad_rgb_o = drive_blank_reg ? 16'h0000 : pal_pix_dat ; + +assign led_o = ssvga_en ; + +// +// Read FIFO when blanks are not asserted and fifo has been filled once +// +always@(posedge wb_clk_i or posedge wb_rst_i) +begin + if ( wb_rst_i ) + go <= #1 1'b0 ; + else + if ( ~ssvga_en ) + go <= #1 1'b0 ; + else + go <= #1 ( fifo_full & crtc_hblank & crtc_vblank ) || ( go && ~fifo_empty ) ; +end + +assign fifo_rd_en = !crtc_hblank & !crtc_vblank & go ; + +assign wbm_restart = go & fifo_empty ; + +// +// Palette index is either color index from FIFO or +// address from WISHBONE slave when writing into palette +// +//assign pal_indx = (pal_wr_en || pal_rd_en) ? wbs_adr_i[9:2] : fifo_out; + +// +// Instantiation of WISHBONE Master block +// +wire [31:2] pix_start_addr ; +ssvga_wbm_if ssvga_wbm_if( + + // Clock and reset + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + + // WISHBONE Master I/F + .wbm_cyc_o(wbm_cyc_o), + .wbm_stb_o(wbm_stb_o), + .wbm_sel_o(wbm_sel_o), + .wbm_we_o(wbm_we_o), + .wbm_adr_o(wbm_adr_o), + .wbm_dat_o(wbm_dat_o), + .wbm_cab_o(wbm_cab_o), + .wbm_dat_i(wbm_dat_i), + .wbm_ack_i(wbm_ack_i), + .wbm_err_i(wbm_err_i), + .wbm_rty_i(wbm_rty_i), + + // FIFO control and other signals + .ssvga_en(ssvga_en), + .fifo_full(fifo_full), + .fifo_wr_en(fifo_wr_en), + .fifo_dat(fifo_in), + .pix_start_addr(pix_start_addr), + .resync(wbm_restart) +); + +// +// Instantiation of WISHBONE Slave block +// +wire [15:0] wbs_pal_data ; +ssvga_wbs_if ssvga_wbs_if( + + // Clock and reset + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + + // WISHBONE Slave I/F + .wbs_cyc_i(wbs_cyc_i), + .wbs_stb_i(wbs_stb_i), + .wbs_sel_i(wbs_sel_i), + .wbs_we_i(wbs_we_i), + .wbs_adr_i(wbs_adr_i), + .wbs_dat_i(wbs_dat_i), + .wbs_cab_i(wbs_cab_i), + .wbs_dat_o(wbs_dat_o), + .wbs_ack_o(wbs_ack_o), + .wbs_err_o(wbs_err_o), + .wbs_rty_o(wbs_rty_o), + + // Control for other SSVGA blocks + .ssvga_en(ssvga_en), + .pal_wr_en(pal_wr_en), + .pal_rd_en(pal_rd_en), + .pal_dat(wbs_pal_data), + .pix_start_addr(pix_start_addr) +); + +// +// Instantiation of line FIFO block +// +ssvga_fifo ssvga_fifo( + .clk(wb_clk_i), + .rst(wb_rst_i), + .wr_en(fifo_wr_en), + .rd_en(fifo_rd_en), + .dat_i(fifo_in), + .dat_o(fifo_out), + .full(fifo_full), + .empty(fifo_empty), + .ssvga_en(ssvga_en) +); + +// +// Instantiation of 256x16 Palette block +// +RAMB4_S16_S16 ssvga_pallete +( + .ADDRA(wbs_adr_i[9:2]), + .DIA(wbs_dat_i[15:0]), + .ENA(1'b1), + .RSTA(wb_rst_i), + .CLKA(wb_clk_i), + .WEA(pal_wr_en), + .DOA(wbs_pal_data), + .ADDRB(fifo_out), + .DIB(16'h0000), + .ENB(1'b1), + .RSTB(wb_rst_i), + .CLKB(wb_clk_i), + .WEB(1'b0), + .DOB(pal_pix_dat) +) ; + +/*generic_spram_256x16 ssvga_palette( + // Generic synchronous single-port RAM interface + .clk(wb_clk_i), + .rst(wb_rst_i), + .ce(1'b1), + .we(pal_wr_en), + .oe(1'b1), + .addr(pal_indx), + .di(wbs_dat_i[15:0]), + .do(pad_rgb_o) +); +*/ +// +// Instantiation of CRT controller block +// +ssvga_crtc ssvga_crtc( + .crt_clk(wb_clk_i), + .rst(wb_rst_i), + .hsync(pad_hsync_o), + .vsync(pad_vsync_o), + .hblank(crtc_hblank), + .vblank(crtc_vblank) +); + +endmodule Index: crt/rtl/verilog/ssvga_fifo.v =================================================================== --- crt/rtl/verilog/ssvga_fifo.v (nonexistent) +++ crt/rtl/verilog/ssvga_fifo.v (revision 154) @@ -0,0 +1,187 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Simple Small VGA IP Core //// +//// //// +//// This file is part of the Simple Small VGA project //// +//// //// +//// //// +//// Description //// +//// 512 entry FIFO for storing line video data. It uses one //// +//// clock for reading and writing. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2001/10/02 15:33:33 mihad +// New project directory structure +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module ssvga_fifo( + clk, rst, dat_i, wr_en, rd_en, + dat_o, full, empty, ssvga_en +); + +// +// I/O ports +// +input clk; // Clock +input rst; // Reset +input [31:0] dat_i; // Input data +input wr_en; // Write enable +input rd_en; // Read enable +output [7:0] dat_o; // Output data +output full; // Full flag +output empty; // Empty flag +input ssvga_en ; // vga enable + +// +// Internal wires and regs +// +reg [7:0] wr_ptr; // Write pointer +reg [7:0] wr_ptr_plus1; // Write pointer +reg [9:0] rd_ptr; // Read pointer +reg [9:0] rd_ptr_plus1; // Read pointer plus1 +wire rd_en_int; // FIFO internal read enable + +// +// Write pointer + 1 +// + +always @(posedge clk or posedge rst) + if (rst) + wr_ptr_plus1 <= #1 8'b0000_0001 ; + else if (~ssvga_en) + wr_ptr_plus1 <= #1 8'b0000_0001 ; + else if (wr_en) + wr_ptr_plus1 <= #1 wr_ptr_plus1 + 1; + +// +// Write pointer +// +always @(posedge clk or posedge rst) + if (rst) + wr_ptr <= #1 8'b0000_0000; + else if (~ssvga_en) + wr_ptr <= #1 8'b0000_0000; + else if (wr_en) + wr_ptr <= #1 wr_ptr_plus1 ; + +// +// Read pointer +// +always @(posedge clk or posedge rst) + if (rst) + rd_ptr <= #1 10'b00_0000_0000; + else if (~ssvga_en) + rd_ptr <= #1 10'b00_0000_0000; + else if (rd_en_int) + rd_ptr <= #1 rd_ptr_plus1 ; + +always @(posedge clk or posedge rst) + if (rst) + rd_ptr_plus1 <= #1 10'b00_0000_0001; + else if (~ssvga_en) + rd_ptr_plus1 <= #1 10'b00_0000_0001; + else if (rd_en_int) + rd_ptr_plus1 <= #1 rd_ptr_plus1 + 1 ; + +// +// Empty is asserted when both pointers match +// +assign empty = ( rd_ptr == {wr_ptr, 2'b00} ) ; + +// +// Full is asserted when both pointers match +// and wr_ptr did increment in previous clock cycle +// +assign full = ( wr_ptr_plus1 == rd_ptr[9:2] ) ; + +wire valid_pix = 1'b1 ; + +// +// Read enable for FIFO +// +assign rd_en_int = rd_en & !empty & valid_pix; + +wire [8:0] ram_pix_address = rd_en_int ? {rd_ptr_plus1[9:2], rd_ptr_plus1[0]} : {rd_ptr[9:2], rd_ptr[0]} ; + +wire [7:0] dat_o_low ; +wire [7:0] dat_o_high ; + +assign dat_o = rd_ptr[1] ? dat_o_high : dat_o_low ; + +RAMB4_S8_S16 ramb4_s8_0( + .CLKA(clk), + .RSTA(rst), + .ADDRA(ram_pix_address), + .DIA(8'h00), + .ENA(1'b1), + .WEA(1'b0), + .DOA(dat_o_low), + + .CLKB(clk), + .RSTB(rst), + .ADDRB(wr_ptr), + .DIB(dat_i[15:0]), + .ENB(1'b1), + .WEB(wr_en), + .DOB() +); + +RAMB4_S8_S16 ramb4_s8_1( + .CLKA(clk), + .RSTA(rst), + .ADDRA(ram_pix_address), + .DIA(8'h00), + .ENA(1'b1), + .WEA(1'b0), + .DOA(dat_o_high), + + .CLKB(clk), + .RSTB(rst), + .ADDRB(wr_ptr), + .DIB(dat_i[31:16]), + .ENB(1'b1), + .WEB(wr_en), + .DOB() +); + +endmodule Index: crt/rtl/verilog/crtc_iob.v =================================================================== --- crt/rtl/verilog/crtc_iob.v (nonexistent) +++ crt/rtl/verilog/crtc_iob.v (revision 154) @@ -0,0 +1,45 @@ +module CRTC_IOB +( + reset_in, + clk_in, + hsync_in, + vsync_in, + rgb_in, + hsync_out, + vsync_out, + rgb_out +) ; + +input reset_in, + clk_in ; + +input hsync_in, + vsync_in ; + +input [15:4] rgb_in ; + +output hsync_out, + vsync_out ; +output [15:4] rgb_out ; + +reg hsync_out, + vsync_out ; + +reg [15:4] rgb_out ; + +always@(posedge clk_in or posedge reset_in) +begin + if ( reset_in ) + begin + hsync_out <= #1 1'b0 ; + vsync_out <= #1 1'b0 ; + rgb_out <= #1 12'h000 ; + end + else + begin + hsync_out <= #1 hsync_in ; + vsync_out <= #1 vsync_in ; + rgb_out <= #1 rgb_in ; + end +end +endmodule \ No newline at end of file Index: crt/rtl/verilog/ssvga_crtc.v =================================================================== --- crt/rtl/verilog/ssvga_crtc.v (nonexistent) +++ crt/rtl/verilog/ssvga_crtc.v (revision 154) @@ -0,0 +1,167 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Simple Small VGA IP Core //// +//// //// +//// This file is part of the Simple Small VGA project //// +//// //// +//// //// +//// Description //// +//// Hsync/Vsync generator. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "ssvga_defines.v" + +module ssvga_crtc( + crt_clk, rst, hsync, vsync, hblank, vblank +); + +// +// I/O ports +// +input crt_clk;// Pixel Clock +input rst; // Reset +output hsync; // H sync +output vsync; // V sync +output hblank; // H blank +output vblank; // V blank + +// +// Internal wires and regs +// +reg [`SSVGA_HCW-1:0] hcntr; // Horizontal counter +reg [`SSVGA_VCW-1:0] vcntr; // Vertical counter +reg hsync; // Horizontal sync +reg vsync; // Vertical sync + +// flip - flops for decoding end of one line +reg line_end1 ; +reg line_end2 ; + +always@(posedge crt_clk or posedge rst) +begin + if (rst) + begin + line_end1 <= #1 1'b0 ; + line_end2 <= #1 1'b0 ; + end + else + begin + line_end1 <= #1 hsync ; + line_end2 <= #1 line_end1 ; + end +end + +wire line_end = ~line_end2 && line_end1 ; + +// +// Assert hblank when hsync is not asserted +// +reg hblank ; +always@(posedge crt_clk or posedge rst) +begin + if (rst) + hblank <= #1 1'b0 ; + else + if ( hcntr == (`SSVGA_HPULSE + `SSVGA_HBACKP) ) + hblank <= #1 1'b0 ; + else + if ( hcntr == (`SSVGA_HTOT - `SSVGA_HFRONTP) ) + hblank <= #1 1'b1 ; +end + +reg vblank ; +always@(posedge crt_clk or posedge rst) +begin + if ( rst ) + vblank <= #1 1'b0 ; + else + if ((vcntr == (`SSVGA_VPULSE + `SSVGA_VBACKP)) && line_end) + vblank <= #1 1'b0 ; + else + if ((vcntr == (`SSVGA_VTOT - `SSVGA_VFRONTP)) && line_end) + vblank <= #1 1'b1 ; +end + +// +// Horizontal counter +// +always @(posedge crt_clk or posedge rst) + if (rst) + hcntr <= #1 `SSVGA_HCW'h0; + else if (hcntr == `SSVGA_HTOT - 1) + hcntr <= #1 `SSVGA_HCW'h0; + else + hcntr <= #1 hcntr + 1; +// +// Horizontal sync +// +always @(posedge crt_clk or posedge rst) + if (rst) + hsync <= #1 1'b0; + else if (hcntr == `SSVGA_HCW'h0) + hsync <= #1 1'b1; + else if (hcntr == `SSVGA_HPULSE) + hsync <= #1 1'b0 ; + +// +// Vertical counter +// +always @(posedge crt_clk or posedge rst) + if (rst) + vcntr <= #1 `SSVGA_VCW'h0; + else if ((vcntr == `SSVGA_VTOT - 1) && line_end) + vcntr <= #1 `SSVGA_VCW'h0; + else if ( line_end ) + vcntr <= #1 vcntr + 1; +// +// Vertical sync +// +always @(posedge crt_clk or posedge rst) + if (rst) + vsync <= #1 1'b0; + else if ((vcntr == `SSVGA_VCW'd0) && line_end) + vsync <= #1 1'b1; + else if ((vcntr == `SSVGA_VPULSE) && line_end) + vsync <= #1 1'b0; +endmodule Index: crt/rtl/verilog/timescale.v =================================================================== --- crt/rtl/verilog/timescale.v (nonexistent) +++ crt/rtl/verilog/timescale.v (revision 154) @@ -0,0 +1 @@ +`timescale 1ns/10ps Index: crt/syn/synplify/pci_crt.ucf =================================================================== --- crt/syn/synplify/pci_crt.ucf (nonexistent) +++ crt/syn/synplify/pci_crt.ucf (revision 154) @@ -0,0 +1,376 @@ +############################################## +# BASIC UCF SYNTAX EXAMPLES V2.1.6 # +############################################## +# +# The "#" symbol is a comment character. To use this sample file, find the +# specification necessary, remove the comment character (#) from the beginning +# of the line, and modify the line (if necessary) to fit your design. +# +# TIMING SPECIFICATIONS +# +# Timing specifications can be applied to the entire device (global) or to +# specific groups in your design (called "time groups'). The time groups are +# declared in two basic ways. +# +# Method 1: Based on a net name, where 'my_net' is a net that touches all the +# logic to be grouped in to 'logic_grp'. Example: +#NET my_net TNM_NET = logic_grp ; +# +# Method 2: Group using the key word 'TIMEGRP' and declare using the names of +# logic in your design. Example: +#TIMEGRP group_name = FFS ("U1/*"); +# creates a group called 'group_name' for all flip-flops within +# the hierarchical block called U1. Wildcards are valid. +# +# Grouping is very important because it lets you tell the software which parts +# of a design run at which speeds. For the majority of the designs with only +# one clock, use simple global constraints. +# +# The type of grouping constraint you use can vary depending on the synthesis +# tools you are using. Foundation Express does better with Method 2. +# +# +############################################################ +# Internal to the device clock speed specifications - Tsys # +############################################################ +# +# data _________ /^^^^^\ _________ out +# ----------| D Q |-----{ LOGIC } -----| D Q |------ +# | | \vvvvv/ | | +# ---|> CLK | ---|> CLK | +# clock | --------- | --------- +# ------------------------------------ +# +# --------------- +# Single Clock +# --------------- +# +# ---------------- +# PERIOD TIME-SPEC +# ---------------- +# The PERIOD spec. covers all timing paths that start or end at a +# register, latch, or synchronous RAM which are clocked by the reference +# net (excluding pad destinations). Also covered is the setup +# requirement of the synchronous element relative to other elements +# (ex. flip flops, pads, etc...). +# NOTE: The default unit for time is nanoseconds. +# +#NET clock PERIOD = 50ns ; +# +# -OR- +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +# FROM:TO style timespecs can be used to constrain paths between time +# groups. NOTE: Keywords: RAMS, FFS, PADS, and LATCHES are predefined +# time groups used to specify all elements of each type in a design. +#TIMEGRP RFFS = RISING FFS ("*"); // creates a rising group called RFFS +#TIMEGRP FFFS = FALLING FFS ("*"); // creates a falling group called FFFS +#TIMESPEC TSF2F = FROM : FFS : TO : FFS : 50 ns; // Flip-flips with the same edge +#TIMESPEC TSR2F = FROM : RFFS : TO : FFFS : 25 ns; // rising edge to falling edge +#TIMESPEC TSF2R = FROM : FFFS : TO : RFFS : 25 ns; // falling edge to rising edge +# +# --------------- +# Multiple Clocks +# --------------- +# Requires a combination of the 'Period' and 'FROM:TO' type time specifications +#NET clock1 TNM_NET = clk1_grp ; +#NET clock2 TNM_NET = clk2_grp ; +# +#TIMESPEC TS_clk1 = PERIOD : clk1_grp : 50 ; +#TIMESPEC TS_clk2 = PERIOD : clk2_grp : 30 ; +#TIMESPEC TS_ck1_2_ck2 = FROM : clk1_grp : TO : clk2_grp : 50 ; +#TIMESPEC TS_ck2_2_ck1 = FROM : clk2_grp : TO : clk1_grp : 30 ; +# +# +############################################################ +# CLOCK TO OUT specifications - Tco # +############################################################ +# +# from _________ /^^^^^\ --------\ +# ----------| D Q |-----{ LOGIC } -----| Pad > +# PLD | | \vvvvv/ --------/ +# ---|> CLK | +# clock | --------- +# -------- +# +# ---------------- +# OFFSET TIME-SPEC +# ---------------- +# To automatically include clock buffer/routing delay in your +# clock-to-out timing specifications, use OFFSET constraints . +# For an output where the maximum clock-to-out (Tco) is 25 ns: +# +#NET out_net_name OFFSET = OUT 25 AFTER clock_net_name ; +# +# -OR- +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +#TIMESPEC TSF2P = FROM : FFS : TO : PADS : 25 ns; +# Note that FROM: FFS : TO: PADS constraints start the delay analysis +# at the flip flop itself, and not the clock input pin. The recommended +# method to create a clock-to-out constraint is to use an OFFSET constraint. +# +# +############################################################ +# Pad to Flip-Flop speed specifications - Tsu # +############################################################ +# +# ------\ /^^^^^\ _________ into PLD +# |pad >-------{ LOGIC } -----| D Q |------ +# ------/ \vvvvv/ | | +# ---|> CLK | +# clock | --------- +# ---------------------------- +# +# ---------------- +# OFFSET TIME-SPEC +# ---------------- +# To automatically account for clock delay in your input setup timing +# specifications, use OFFSET constraints. +# For an input where the maximum setup time is 25 ns: +#NET in_net_name OFFSET = IN 25 BEFORE clock_net_name ; +# +# -OR- +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +#TIMESPEC TSP2F = FROM : PADS : TO : FFS : 25 ns; +# Note that FROM: PADS : TO: FFS constraints do not take into account any +# delay for the clock path. The recommended method to create an input +# setup time constraint is to use an OFFSET constraint. +# +# +############################################################ +# Pad to Pad speed specifications - Tpd # +############################################################ +# +# ------\ /^^^^^\ -------\ +# |pad >-------{ LOGIC } -----| pad > +# ------/ \vvvvv/ -------/ +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +#TIMESPEC TSP2P = FROM : PADS : TO : PADS : 125 ns; +# +# +############################################################ +# Other timing specifications # +############################################################ +# +# ------------- +# TIMING IGNORE +# ------------- +# If you can ignore timing of paths, use Timing Ignore (TIG). NOTE: The +# "*" character is a wild card, which can be used for bus names. A "?" +# character can be used to wild-card one character. +# Ignore timing of net reset_n: +#NET : reset_n : TIG ; +# +# Ignore data_reg(7:0) net in instance mux_mem: +#NET : mux_mem/data_reg* : TIG ; +# +# Ignore data_reg(7:0) net in instance mux_mem as related to a TIMESPEC +# named TS01 only: +#NET : mux_mem/data_reg* : TIG = TS01 ; +# +# Ignore data1_sig and data2_sig nets: +#NET : data?_sig : TIG ; +# +# --------------- +# PATH EXCEPTIONS +# --------------- +# If your design has outputs that can be slower than others, you can +# create specific timespecs similar to this example for output nets +# named out_data(7:0) and irq_n: +#TIMEGRP slow_outs = PADS(out_data* : irq_n) ; +#TIMEGRP fast_outs = PADS : EXCEPT : slow_outs ; +#TIMESPEC TS08 = FROM : FFS : TO : fast_outs : 22 ; +#TIMESPEC TS09 = FROM : FFS : TO : slow_outs : 75 ; +# +# If you have multi-cycle FF to FF paths, you can create a time group +# using either the TIMEGRP or TNM statements. +# +# WARNING: Many VHDL/Verilog synthesizers do not predictably name flip +# flop Q output nets. Most synthesizers do assign predictable instance +# names to flip flops, however. +# +# TIMEGRP example: +#TIMEGRP slowffs = FFS(inst_path/ff_q_output_net1* : +#inst_path/ff_q_output_net2*); +# +# TNM attached to instance example: +#INST inst_path/ff_instance_name1_reg* TNM = slowffs ; +#INST inst_path/ff_instance_name2_reg* TNM = slowffs ; +# +# If a FF clock-enable is used on all flip flops of a multi-cycle path, +# you can attach TNM to the clock enable net. NOTE: TNM attached to a +# net "forward traces" to any FF, LATCH, RAM, or PAD attached to the +# net. +#NET ff_clock_enable_net TNM = slowffs ; +# +# Example of using "slowffs" timegroup, in a FROM:TO timespec, with +# either of the three timegroup methods shown above: +#TIMESPEC TS10 = FROM : slowffs : TO : FFS : 100 ; +# +# Constrain the skew or delay associate with a net. +#NET any_net_name MAXSKEW = 7 ; +#NET any_net_name MAXDELAY = 20 ns; +# +# +# Constraint priority in your .ucf file is as follows: +# +# highest 1. Timing Ignore (TIG) +# 2. FROM : THRU : TO specs +# 3. FROM : TO specs +# lowest 4. PERIOD specs +# +# See the on-line "Library Reference Guide" document for +# additional timespec features and more information. +# +# +############################################################ +# # +# LOCATION and ATTRIBUTE SPECIFICATIONS # +# # +############################################################ +# Pin and CLB location locking constraints # +############################################################ +# +# ----------------------- +# Assign an IO pin number +# ----------------------- +#INST io_buf_instance_name LOC = P110 ; +#NET io_net_name LOC = P111 ; +# +# ----------------------- +# Assign a signal to a range of I/O pins +# ----------------------- +#NET "signal_name" LOC=P32, P33, P34; +# +# ----------------------- +# Place a logic element(called a BEL) in a specific CLB location. +# BEL = FF, LUT, RAM, etc... +# ----------------------- +#INST instance_path/BEL_inst_name LOC = CLB_R17C36 ; +# +# ----------------------- +# Place CLB in rectangular area from CLB R1C1 to CLB R5C7 +# ----------------------- +#INST /U1/U2/reg<0> LOC=clb_r1c1:clb_r5c7; +# +# ----------------------- +# Place hierarchical logic block in rectangular area from CLB R1C1 to CLB R5C7 +# ----------------------- +#INST /U1* LOC=clb_r1c1:clb_r5c7; +# +# ----------------------- +# Prohibit IO pin P26 or CLBR5C3 from being used: +# ----------------------- +#CONFIG PROHIBIT = P26 ; +#CONFIG PROHIBIT = CLB_R5C3 ; +# Config Prohibit is very important for forcing the software to not use critical +# configuration pins like INIT or DOUT on the FPGA. The Mode pins and JTAG +# Pins require a special pad so they will not be available to this constraint +# +# ----------------------- +# Assign an OBUF to be FAST or SLOW: +# ----------------------- +#INST obuf_instance_name FAST ; +#INST obuf_instance_name SLOW ; +# +# ----------------------- +# FPGAs only: IOB input Flip-flop delay specification +# ----------------------- +# Declare an IOB input FF delay (default = MAXDELAY). +# NOTE: MEDDELAY/NODELAY can be attached to a CLB FF that is pushed +# into an IOB by the "map -pr i" option. +#INST input_ff_instance_name MEDDELAY ; +#INST input_ff_instance_name NODELAY ; +# +# ----------------------- +# Assign Global Clock Buffers Lower Left Right Side +# ----------------------- +# INST gbuf1 LOC=SSW +# +# # + + +# define a group of metastable Flip-Flops +INST *sync_data_out* TNM = sync_ffs ; +TIMESPEC TS_sync_flops = FROM : sync_ffs : TO : FFS : 15 ; +INST *meta_q_o* TNM = meta_ffs ; +TIMESPEC TS_meta_flops = FROM : meta_ffs : TO : FFS : 15 ; + +NET CLK TNM_NET = CLK_GRP ; +NET CRT_CLK TNM_NET = CRT_CLK_GRP ; + +TIMESPEC TS_CLK_2_CRT_CLK = FROM : CLK_GRP : TO : CRT_CLK_GRP : 15 ; +TIMESPEC TS_CRT_CLK_2_CLK = FROM : CRT_CLK_GRP : TO : CLK_GRP : 15 ; + +NET "AD0" IOSTANDARD = PCI33_5; +NET "AD1" IOSTANDARD = PCI33_5; +NET "AD2" IOSTANDARD = PCI33_5; +NET "AD3" IOSTANDARD = PCI33_5; +NET "AD4" IOSTANDARD = PCI33_5; +NET "AD5" IOSTANDARD = PCI33_5; +NET "AD6" IOSTANDARD = PCI33_5; +NET "AD7" IOSTANDARD = PCI33_5; +NET "AD8" IOSTANDARD = PCI33_5; +NET "AD9" IOSTANDARD = PCI33_5; +NET "AD10" IOSTANDARD = PCI33_5; +NET "AD11" IOSTANDARD = PCI33_5; +NET "AD12" IOSTANDARD = PCI33_5; +NET "AD13" IOSTANDARD = PCI33_5; +NET "AD14" IOSTANDARD = PCI33_5; +NET "AD15" IOSTANDARD = PCI33_5; +NET "AD16" IOSTANDARD = PCI33_5; +NET "AD17" IOSTANDARD = PCI33_5; +NET "AD18" IOSTANDARD = PCI33_5; +NET "AD19" IOSTANDARD = PCI33_5; +NET "AD20" IOSTANDARD = PCI33_5; +NET "AD21" IOSTANDARD = PCI33_5; +NET "AD22" IOSTANDARD = PCI33_5; +NET "AD23" IOSTANDARD = PCI33_5; +NET "AD24" IOSTANDARD = PCI33_5; +NET "AD25" IOSTANDARD = PCI33_5; +NET "AD26" IOSTANDARD = PCI33_5; +NET "AD27" IOSTANDARD = PCI33_5; +NET "AD28" IOSTANDARD = PCI33_5; +NET "AD29" IOSTANDARD = PCI33_5; +NET "AD30" IOSTANDARD = PCI33_5; +NET "AD31" IOSTANDARD = PCI33_5; + +NET "CBE0" IOSTANDARD = PCI33_5; +NET "CBE1" IOSTANDARD = PCI33_5; +NET "CBE2" IOSTANDARD = PCI33_5; +NET "CBE3" IOSTANDARD = PCI33_5; + +NET "DEVSEL" IOSTANDARD = PCI33_5; + +NET "FRAME" IOSTANDARD = PCI33_5; + +NET "GNT" IOSTANDARD = PCI33_5; +NET "RST" IOSTANDARD = PCI33_5; +NET "INTA" IOSTANDARD = PCI33_5; + +NET "IRDY" IOSTANDARD = PCI33_5; + +NET "PAR" IOSTANDARD = PCI33_5; + +NET "PERR" IOSTANDARD = PCI33_5; + +NET "REQ" IOSTANDARD = PCI33_5; + +NET "SERR" IOSTANDARD = PCI33_5; + +NET "STOP" IOSTANDARD = PCI33_5; + +NET "TRDY" IOSTANDARD = PCI33_5; + +NET "IDSEL" IOSTANDARD = PCI33_5;

crt/syn/synplify/pci_crt.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: crt/syn/synplify/pci_crt.sdc =================================================================== --- crt/syn/synplify/pci_crt.sdc (nonexistent) +++ crt/syn/synplify/pci_crt.sdc (revision 154) @@ -0,0 +1,259 @@ +# Synplicity, Inc. constraint file +# /shared/projects/pci/mihad/pci/apps/crt/syn/synplify/pci_crt.sdc +# Written on Fri Sep 27 11:42:06 2002 +# by Amplify, Amplify 3.1 Scope Editor + +# +# Clocks +# +define_clock -name {CLK} -period 30.000 -clockgroup pci_clkgrp +define_clock -name {CRT_CLK} -period 44.000 -clockgroup crt_clkgrp + +# +# Inputs/Outputs +# +define_input_delay {DEVSEL} 23.00 -ref CLK:r +define_input_delay {TRDY} 23.00 -ref CLK:r +define_input_delay {STOP} 23.00 -ref CLK:r +define_input_delay {IDSEL} 23.00 -ref CLK:r +define_input_delay {FRAME} 23.00 -ref CLK:r +define_input_delay {IRDY} 23.00 -ref CLK:r +define_input_delay {GNT} 20.00 -ref CLK:r +define_input_delay {PAR} 23.00 -ref CLK:r +define_input_delay {PERR} 23.00 -ref CLK:r +define_input_delay {AD0} 23.00 -ref CLK:r +define_input_delay {AD1} 23.00 -ref CLK:r +define_input_delay {AD2} 23.00 -ref CLK:r +define_input_delay {AD3} 23.00 -ref CLK:r +define_input_delay {AD4} 23.00 -ref CLK:r +define_input_delay {AD5} 23.00 -ref CLK:r +define_input_delay {AD6} 23.00 -ref CLK:r +define_input_delay {AD7} 23.00 -ref CLK:r +define_input_delay {AD8} 23.00 -ref CLK:r +define_input_delay {AD9} 23.00 -ref CLK:r +define_input_delay {AD10} 23.00 -ref CLK:r +define_input_delay {AD11} 23.00 -ref CLK:r +define_input_delay {AD12} 23.00 -ref CLK:r +define_input_delay {AD13} 23.00 -ref CLK:r +define_input_delay {AD14} 23.00 -ref CLK:r +define_input_delay {AD15} 23.00 -ref CLK:r +define_input_delay {AD16} 23.00 -ref CLK:r +define_input_delay {AD17} 23.00 -ref CLK:r +define_input_delay {AD18} 23.00 -ref CLK:r +define_input_delay {AD19} 23.00 -ref CLK:r +define_input_delay {AD20} 23.00 -ref CLK:r +define_input_delay {AD21} 23.00 -ref CLK:r +define_input_delay {AD22} 23.00 -ref CLK:r +define_input_delay {AD23} 23.00 -ref CLK:r +define_input_delay {AD24} 23.00 -ref CLK:r +define_input_delay {AD25} 23.00 -ref CLK:r +define_input_delay {AD26} 23.00 -ref CLK:r +define_input_delay {AD27} 23.00 -ref CLK:r +define_input_delay {AD28} 23.00 -ref CLK:r +define_input_delay {AD29} 23.00 -ref CLK:r +define_input_delay {AD30} 23.00 -ref CLK:r +define_input_delay {AD31} 23.00 -ref CLK:r +define_input_delay {CBE0} 23.00 -ref CLK:r +define_input_delay {CBE1} 23.00 -ref CLK:r +define_input_delay {CBE2} 23.00 -ref CLK:r +define_input_delay {CBE3} 23.00 -ref CLK:r +define_output_delay {AD0} 19.00 -ref CLK:r +define_output_delay {AD1} 19.00 -ref CLK:r +define_output_delay {AD2} 19.00 -ref CLK:r +define_output_delay {AD3} 19.00 -ref CLK:r +define_output_delay {AD4} 19.00 -ref CLK:r +define_output_delay {AD5} 19.00 -ref CLK:r +define_output_delay {AD6} 19.00 -ref CLK:r +define_output_delay {AD7} 19.00 -ref CLK:r +define_output_delay {AD8} 19.00 -ref CLK:r +define_output_delay {AD9} 19.00 -ref CLK:r +define_output_delay {AD10} 19.00 -ref CLK:r +define_output_delay {AD11} 19.00 -ref CLK:r +define_output_delay {AD12} 19.00 -ref CLK:r +define_output_delay {AD13} 19.00 -ref CLK:r +define_output_delay {AD14} 19.00 -ref CLK:r +define_output_delay {AD15} 19.00 -ref CLK:r +define_output_delay {AD16} 19.00 -ref CLK:r +define_output_delay {AD17} 19.00 -ref CLK:r +define_output_delay {AD18} 19.00 -ref CLK:r +define_output_delay {AD19} 19.00 -ref CLK:r +define_output_delay {AD20} 19.00 -ref CLK:r +define_output_delay {AD21} 19.00 -ref CLK:r +define_output_delay {AD22} 19.00 -ref CLK:r +define_output_delay {AD23} 19.00 -ref CLK:r +define_output_delay {AD24} 19.00 -ref CLK:r +define_output_delay {AD25} 19.00 -ref CLK:r +define_output_delay {AD26} 19.00 -ref CLK:r +define_output_delay {AD27} 19.00 -ref CLK:r +define_output_delay {AD28} 19.00 -ref CLK:r +define_output_delay {AD29} 19.00 -ref CLK:r +define_output_delay {AD30} 19.00 -ref CLK:r +define_output_delay {AD31} 19.00 -ref CLK:r +define_output_delay {CBE0} 19.00 -ref CLK:r +define_output_delay {CBE1} 19.00 -ref CLK:r +define_output_delay {CBE2} 19.00 -ref CLK:r +define_output_delay {CBE3} 19.00 -ref CLK:r +define_output_delay {DEVSEL} 19.00 -ref CLK:r +define_output_delay {TRDY} 19.00 -ref CLK:r +define_output_delay {STOP} 19.00 -ref CLK:r +define_output_delay {FRAME} 19.00 -ref CLK:r +define_output_delay {IRDY} 19.00 -ref CLK:r +define_output_delay {REQ} 18.00 -ref CLK:r +define_output_delay {PAR} 19.00 -ref CLK:r +define_output_delay {PERR} 19.00 -ref CLK:r +define_output_delay {SERR} 19.00 -ref CLK:r +define_input_delay -default 10.00 -ref CRT_CLK:r +define_output_delay -default 10.00 -ref CRT_CLK:r + +# +# Registers +# +#define_reg_output_delay {bridge.pci_target_unit.del_sync.comp_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.del_sync.done_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.cache_lsize_to_wb_bits_sync.sync_data_out[6:0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.command_bit_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.int_pin_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.isr_bit0_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.isr_bit2_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.pci_err_cs_bits_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.sync_isr_2.clear_delete_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.sync_isr_2.delete_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.sync_pci_err_cs_8.clear_delete_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.sync_pci_err_cs_8.delete_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.del_sync.comp_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.del_sync.done_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.del_sync.req_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.del_sync.rty_exp_back_prop_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.del_sync.rty_exp_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pcir_fifo_ctrl.almost_empty} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pcir_fifo_ctrl.empty} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pcir_fifo_ctrl.full_out} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pcir_fifo_ctrl.stretched_empty} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.almost_empty} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.almost_full} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.empty} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.full_out} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.stretched_empty} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.two_left_out} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_transaction_ready_out} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.del_sync.comp_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.del_sync.done_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.del_sync.req_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.del_sync.rty_exp_back_prop_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.del_sync.rty_exp_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbr_fifo_ctrl.empty} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbr_fifo_ctrl.stretched_empty} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbw_fifo_ctrl.almost_full} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbw_fifo_ctrl.empty} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbw_fifo_ctrl.full_out} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbw_fifo_ctrl.stretched_empty} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbw_transaction_ready_out} -route 15.00 + +define_reg_output_delay {*sync_data_out*} -route 20.00 +define_reg_output_delay {*meta_q_o*} -route 20.00 + +# +# Multicycle Path +# + +# +# False Path +# + +# +# Attributes +# +define_attribute {CLK} xc_loc {P185} +define_attribute {INTA} xc_loc {P195} +define_attribute {RST} xc_loc {P199} +define_attribute {GNT} xc_loc {P200} +define_attribute {REQ} xc_loc {P201} +define_attribute {AD31} xc_loc {P203} +define_attribute {AD30} xc_loc {P204} +define_attribute {AD29} xc_loc {P205} +define_attribute {AD28} xc_loc {P206} +define_attribute {AD27} xc_loc {P3} +define_attribute {AD26} xc_loc {P4} +define_attribute {AD25} xc_loc {P5} +define_attribute {AD24} xc_loc {P6} +define_attribute {CBE3} xc_loc {P8} +define_attribute {IDSEL} xc_loc {P9} +define_attribute {AD23} xc_loc {P10} +define_attribute {AD22} xc_loc {P14} +define_attribute {AD21} xc_loc {P15} +define_attribute {AD20} xc_loc {P16} +define_attribute {AD19} xc_loc {P17} +define_attribute {AD18} xc_loc {P18} +define_attribute {AD17} xc_loc {P20} +define_attribute {AD16} xc_loc {P21} +define_attribute {CBE2} xc_loc {P22} +define_attribute {FRAME} xc_loc {P23} +define_attribute {IRDY} xc_loc {P24} +define_attribute {TRDY} xc_loc {P27} +define_attribute {DEVSEL} xc_loc {P29} +define_attribute {STOP} xc_loc {P30} +define_attribute {PERR} xc_loc {P31} +define_attribute {SERR} xc_loc {P33} +define_attribute {PAR} xc_loc {P34} +define_attribute {CBE1} xc_loc {P35} +define_attribute {AD15} xc_loc {P36} +define_attribute {AD14} xc_loc {P37} +define_attribute {AD13} xc_loc {P41} +define_attribute {AD12} xc_loc {P42} +define_attribute {AD11} xc_loc {P43} +define_attribute {AD10} xc_loc {P45} +define_attribute {AD9} xc_loc {P46} +define_attribute {AD8} xc_loc {P47} +define_attribute {CBE0} xc_loc {P48} +define_attribute {AD7} xc_loc {P49} +define_attribute {AD6} xc_loc {P57} +define_attribute {AD5} xc_loc {P58} +define_attribute {AD4} xc_loc {P59} +define_attribute {AD3} xc_loc {P61} +define_attribute {AD2} xc_loc {P62} +define_attribute {AD1} xc_loc {P63} +define_attribute {AD0} xc_loc {P67} +define_attribute {CRT_CLK} xc_loc {P182} +define_attribute {HSYNC} xc_loc {P83} +define_attribute {VSYNC} xc_loc {P84} +define_attribute {RGB4} xc_loc {P166} +define_attribute {RGB5} xc_loc {P167} +define_attribute {RGB6} xc_loc {P168} +define_attribute {RGB7} xc_loc {P172} +define_attribute {RGB8} xc_loc {P173} +define_attribute {RGB9} xc_loc {P174} +define_attribute {RGB10} xc_loc {P175} +define_attribute {RGB11} xc_loc {P176} +define_attribute {RGB12} xc_loc {P178} +define_attribute {RGB13} xc_loc {P179} +define_attribute {RGB14} xc_loc {P180} +define_attribute {RGB15} xc_loc {P181} +define_attribute {LED} xc_loc {P202} +define_global_attribute syn_useioff {1} +define_attribute {v:work.pci_cbe_en_crit} syn_hier {hard} +define_attribute {v:work.pci_frame_crit} syn_hier {hard} +define_attribute {v:work.pci_frame_en_crit} syn_hier {hard} +define_attribute {v:work.pci_frame_load_crit} syn_hier {hard} +define_attribute {v:work.pci_irdy_out_crit} syn_hier {hard} +define_attribute {v:work.pci_mad_ad_en_crit} syn_hier {hard} +define_attribute {v:work.pci_mas_ad_load_crit} syn_hier {hard} +define_attribute {v:work.pci_mas_ch_state_crit} syn_hier {hard} +define_attribute {v:work.pci_par_crit} syn_hier {hard} +define_attribute {v:work.pci_io_mux_ad_en_crit} syn_hier {hard} +define_attribute {v:work.pci_io_mux_ad_load_crit} syn_hier {hard} +define_attribute {v:work.pci_target32_clk_en} syn_hier {hard} +define_attribute {v:work.pci_target32_devs_crit} syn_hier {hard} +define_attribute {v:work.pci_target32_stop_crit} syn_hier {hard} +define_attribute {v:work.pci_target32_trdy_crit} syn_hier {hard} +define_attribute {v:work.pci_perr_crit} syn_hier {hard} +define_attribute {v:work.pci_perr_en_crit} syn_hier {hard} +define_attribute {v:work.pci_serr_crit} syn_hier {hard} +define_attribute {v:work.pci_serr_en_crit} syn_hier {hard} + +# +# Other Constraints +# + +# +# Order of waveforms +#

crt/syn/synplify/pci_crt.sdc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: crt/syn/synplify/pci_crt.prj =================================================================== --- crt/syn/synplify/pci_crt.prj (nonexistent) +++ crt/syn/synplify/pci_crt.prj (revision 154) @@ -0,0 +1,125 @@ +#-- Synplicity, Inc. +#-- Version Amplify 3.1 +#-- Project file /shared/projects/pci/mihad/pci/apps/crt/syn/synplify/pci_crt.prj +#-- Written on Fri Sep 27 16:20:50 2002 + + +#add_file options +add_file -verilog "$LIB/xilinx/virtex.v" +add_file -verilog "../../../../rtl/verilog/meta_flop.v" +add_file -verilog "../../../../rtl/verilog/pci_async_reset_flop.v" +add_file -verilog "../../../../rtl/verilog/pci_bridge32.v" +add_file -verilog "../../../../rtl/verilog/pci_cbe_en_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_conf_cyc_addr_dec.v" +add_file -verilog "../../../../rtl/verilog/pci_conf_space.v" +add_file -verilog "../../../../rtl/verilog/pci_cur_out_reg.v" +add_file -verilog "../../../../rtl/verilog/pci_delayed_sync.v" +add_file -verilog "../../../../rtl/verilog/pci_delayed_write_reg.v" +add_file -verilog "../../../../rtl/verilog/pci_frame_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_frame_en_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_frame_load_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_in_reg.v" +add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_en_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_load_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_io_mux.v" +add_file -verilog "../../../../rtl/verilog/pci_irdy_out_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_mas_ad_en_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_mas_ad_load_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_mas_ch_state_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_master32_sm_if.v" +add_file -verilog "../../../../rtl/verilog/pci_master32_sm.v" +add_file -verilog "../../../../rtl/verilog/pci_out_reg.v" +add_file -verilog "../../../../rtl/verilog/pci_par_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_parity_check.v" +add_file -verilog "../../../../rtl/verilog/pci_pci_decoder.v" +add_file -verilog "../../../../rtl/verilog/pci_pcir_fifo_control.v" +add_file -verilog "../../../../rtl/verilog/pci_pci_tpram.v" +add_file -verilog "../../../../rtl/verilog/pci_pciw_fifo_control.v" +add_file -verilog "../../../../rtl/verilog/pci_pciw_pcir_fifos.v" +add_file -verilog "../../../../rtl/verilog/pci_perr_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_perr_en_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_ram_16x40d.v" +add_file -verilog "../../../../rtl/verilog/pci_rst_int.v" +add_file -verilog "../../../../rtl/verilog/pci_serr_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_serr_en_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_sync_module.v" +add_file -verilog "../../../../rtl/verilog/pci_target32_clk_en.v" +add_file -verilog "../../../../rtl/verilog/pci_target32_devs_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_target32_interface.v" +add_file -verilog "../../../../rtl/verilog/pci_target32_sm.v" +add_file -verilog "../../../../rtl/verilog/pci_target32_stop_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_target32_trdy_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_target_unit.v" +add_file -verilog "../../../../rtl/verilog/pci_wb_addr_mux.v" +add_file -verilog "../../../../rtl/verilog/pci_wb_decoder.v" +add_file -verilog "../../../../rtl/verilog/pci_wb_master.v" +add_file -verilog "../../../../rtl/verilog/pci_wbr_fifo_control.v" +add_file -verilog "../../../../rtl/verilog/pci_wb_slave_unit.v" +add_file -verilog "../../../../rtl/verilog/pci_wb_slave.v" +add_file -verilog "../../../../rtl/verilog/pci_wb_tpram.v" +add_file -verilog "../../../../rtl/verilog/pci_wbw_fifo_control.v" +add_file -verilog "../../../../rtl/verilog/pci_wbw_wbr_fifos.v" +add_file -verilog "../../../../rtl/verilog/synchronizer_flop.v" +add_file -verilog "../../rtl/verilog/crtc_iob.v" +add_file -verilog "../../rtl/verilog/ssvga_crtc.v" +add_file -verilog "../../rtl/verilog/ssvga_fifo.v" +add_file -verilog "../../rtl/verilog/ssvga_top.v" +add_file -verilog "../../rtl/verilog/ssvga_wbm_if.v" +add_file -verilog "../../rtl/verilog/ssvga_wbs_if.v" +add_file -constraint "pci_crt.sdc" +add_file -verilog "../../rtl/verilog/top.v" + +#reporting options + + +#implementation: "rev_1" +impl -add rev_1 + +#device options +set_option -technology SPARTAN2 +set_option -part XC2S150 +set_option -package PQ208 +set_option -speed_grade -5 + +#compilation/mapping options +set_option -default_enum_encoding default +set_option -symbolic_fsm_compiler 0 +set_option -resource_sharing 0 +set_option -use_fsm_explorer 0 + +#map options +set_option -frequency 50.000 +set_option -fanout_limit 50 +set_option -disable_io_insertion 0 +set_option -pipe 0 +set_option -fixgatedclocks 0 +set_option -retiming 0 +set_option -modular 0 + +#simulation options +set_option -write_verilog 0 +set_option -write_vhdl 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "rev_1/top.edf" + +#implementation attributes +set_option -vlog_std v95 +set_option -compiler_compatible 0 +set_option -random_floorplan 0 +set_option -include_path "../../rtl/verilog/;../../../../rtl/verilog/" + +#netlist optimizer options +set_option -enable_nfilter 0 +set_option -feedthrough 1 +set_option -constant_prop 1 +set_option -level_hierarchy 0 + +#physical constraint options +set_option -floorplan "" +set_option -nfilter_user_path "" +set_option -pin_assignment "" +impl -active "rev_1"

crt/syn/synplify/pci_crt.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: crt/syn/ucf/pci_crt.ucf =================================================================== --- crt/syn/ucf/pci_crt.ucf (nonexistent) +++ crt/syn/ucf/pci_crt.ucf (revision 154) @@ -0,0 +1,678 @@ +############################################## +# BASIC UCF SYNTAX EXAMPLES V2.1.6 # +############################################## +# +# The "#" symbol is a comment character. To use this sample file, find the +# specification necessary, remove the comment character (#) from the beginning +# of the line, and modify the line (if necessary) to fit your design. +# +# TIMING SPECIFICATIONS +# +# Timing specifications can be applied to the entire device (global) or to +# specific groups in your design (called "time groups'). The time groups are +# declared in two basic ways. +# +# Method 1: Based on a net name, where 'my_net' is a net that touches all the +# logic to be grouped in to 'logic_grp'. Example: +#NET my_net TNM_NET = logic_grp ; +# +# Method 2: Group using the key word 'TIMEGRP' and declare using the names of +# logic in your design. Example: +#TIMEGRP group_name = FFS ("U1/*"); +# creates a group called 'group_name' for all flip-flops within +# the hierarchical block called U1. Wildcards are valid. +# +# Grouping is very important because it lets you tell the software which parts +# of a design run at which speeds. For the majority of the designs with only +# one clock, use simple global constraints. +# +# The type of grouping constraint you use can vary depending on the synthesis +# tools you are using. Foundation Express does better with Method 2. +# +# +############################################################ +# Internal to the device clock speed specifications - Tsys # +############################################################ +# +# data _________ /^^^^^\ _________ out +# ----------| D Q |-----{ LOGIC } -----| D Q |------ +# | | \vvvvv/ | | +# ---|> CLK | ---|> CLK | +# clock | --------- | --------- +# ------------------------------------ +# +# --------------- +# Single Clock +# --------------- +# +# ---------------- +# PERIOD TIME-SPEC +# ---------------- +# The PERIOD spec. covers all timing paths that start or end at a +# register, latch, or synchronous RAM which are clocked by the reference +# net (excluding pad destinations). Also covered is the setup +# requirement of the synchronous element relative to other elements +# (ex. flip flops, pads, etc...). +# NOTE: The default unit for time is nanoseconds. +# +#NET clock PERIOD = 50ns ; +# +# -OR- +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +# FROM:TO style timespecs can be used to constrain paths between time +# groups. NOTE: Keywords: RAMS, FFS, PADS, and LATCHES are predefined +# time groups used to specify all elements of each type in a design. +#TIMEGRP RFFS = RISING FFS ("*"); // creates a rising group called RFFS +#TIMEGRP FFFS = FALLING FFS ("*"); // creates a falling group called FFFS +#TIMESPEC TSF2F = FROM : FFS : TO : FFS : 50 ns; // Flip-flips with the same edge +#TIMESPEC TSR2F = FROM : RFFS : TO : FFFS : 25 ns; // rising edge to falling edge +#TIMESPEC TSF2R = FROM : FFFS : TO : RFFS : 25 ns; // falling edge to rising edge +# +# --------------- +# Multiple Clocks +# --------------- +# Requires a combination of the 'Period' and 'FROM:TO' type time specifications +#NET clock1 TNM_NET = clk1_grp ; +#NET clock2 TNM_NET = clk2_grp ; +# +#TIMESPEC TS_clk1 = PERIOD : clk1_grp : 50 ; +#TIMESPEC TS_clk2 = PERIOD : clk2_grp : 30 ; +#TIMESPEC TS_ck1_2_ck2 = FROM : clk1_grp : TO : clk2_grp : 50 ; +#TIMESPEC TS_ck2_2_ck1 = FROM : clk2_grp : TO : clk1_grp : 30 ; +# +# +############################################################ +# CLOCK TO OUT specifications - Tco # +############################################################ +# +# from _________ /^^^^^\ --------\ +# ----------| D Q |-----{ LOGIC } -----| Pad > +# PLD | | \vvvvv/ --------/ +# ---|> CLK | +# clock | --------- +# -------- +# +# ---------------- +# OFFSET TIME-SPEC +# ---------------- +# To automatically include clock buffer/routing delay in your +# clock-to-out timing specifications, use OFFSET constraints . +# For an output where the maximum clock-to-out (Tco) is 25 ns: +# +#NET out_net_name OFFSET = OUT 25 AFTER clock_net_name ; +# +# -OR- +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +#TIMESPEC TSF2P = FROM : FFS : TO : PADS : 25 ns; +# Note that FROM: FFS : TO: PADS constraints start the delay analysis +# at the flip flop itself, and not the clock input pin. The recommended +# method to create a clock-to-out constraint is to use an OFFSET constraint. +# +# +############################################################ +# Pad to Flip-Flop speed specifications - Tsu # +############################################################ +# +# ------\ /^^^^^\ _________ into PLD +# |pad >-------{ LOGIC } -----| D Q |------ +# ------/ \vvvvv/ | | +# ---|> CLK | +# clock | --------- +# ---------------------------- +# +# ---------------- +# OFFSET TIME-SPEC +# ---------------- +# To automatically account for clock delay in your input setup timing +# specifications, use OFFSET constraints. +# For an input where the maximum setup time is 25 ns: +#NET in_net_name OFFSET = IN 25 BEFORE clock_net_name ; +# +# -OR- +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +#TIMESPEC TSP2F = FROM : PADS : TO : FFS : 25 ns; +# Note that FROM: PADS : TO: FFS constraints do not take into account any +# delay for the clock path. The recommended method to create an input +# setup time constraint is to use an OFFSET constraint. +# +# +############################################################ +# Pad to Pad speed specifications - Tpd # +############################################################ +# +# ------\ /^^^^^\ -------\ +# |pad >-------{ LOGIC } -----| pad > +# ------/ \vvvvv/ -------/ +# +# ------------------ +# FROM:TO TIME-SPECs +# ------------------ +#TIMESPEC TSP2P = FROM : PADS : TO : PADS : 125 ns; +# +# +############################################################ +# Other timing specifications # +############################################################ +# +# ------------- +# TIMING IGNORE +# ------------- +# If you can ignore timing of paths, use Timing Ignore (TIG). NOTE: The +# "*" character is a wild card, which can be used for bus names. A "?" +# character can be used to wild-card one character. +# Ignore timing of net reset_n: +#NET : reset_n : TIG ; +# +# Ignore data_reg(7:0) net in instance mux_mem: +#NET : mux_mem/data_reg* : TIG ; +# +# Ignore data_reg(7:0) net in instance mux_mem as related to a TIMESPEC +# named TS01 only: +#NET : mux_mem/data_reg* : TIG = TS01 ; +# +# Ignore data1_sig and data2_sig nets: +#NET : data?_sig : TIG ; +# +# --------------- +# PATH EXCEPTIONS +# --------------- +# If your design has outputs that can be slower than others, you can +# create specific timespecs similar to this example for output nets +# named out_data(7:0) and irq_n: +#TIMEGRP slow_outs = PADS(out_data* : irq_n) ; +#TIMEGRP fast_outs = PADS : EXCEPT : slow_outs ; +#TIMESPEC TS08 = FROM : FFS : TO : fast_outs : 22 ; +#TIMESPEC TS09 = FROM : FFS : TO : slow_outs : 75 ; +# +# If you have multi-cycle FF to FF paths, you can create a time group +# using either the TIMEGRP or TNM statements. +# +# WARNING: Many VHDL/Verilog synthesizers do not predictably name flip +# flop Q output nets. Most synthesizers do assign predictable instance +# names to flip flops, however. +# +# TIMEGRP example: +#TIMEGRP slowffs = FFS(inst_path/ff_q_output_net1* : +#inst_path/ff_q_output_net2*); +# +# TNM attached to instance example: +#INST inst_path/ff_instance_name1_reg* TNM = slowffs ; +#INST inst_path/ff_instance_name2_reg* TNM = slowffs ; +# +# If a FF clock-enable is used on all flip flops of a multi-cycle path, +# you can attach TNM to the clock enable net. NOTE: TNM attached to a +# net "forward traces" to any FF, LATCH, RAM, or PAD attached to the +# net. +#NET ff_clock_enable_net TNM = slowffs ; +# +# Example of using "slowffs" timegroup, in a FROM:TO timespec, with +# either of the three timegroup methods shown above: +#TIMESPEC TS10 = FROM : slowffs : TO : FFS : 100 ; +# +# Constrain the skew or delay associate with a net. +#NET any_net_name MAXSKEW = 7 ; +#NET any_net_name MAXDELAY = 20 ns; +# +# +# Constraint priority in your .ucf file is as follows: +# +# highest 1. Timing Ignore (TIG) +# 2. FROM : THRU : TO specs +# 3. FROM : TO specs +# lowest 4. PERIOD specs +# +# See the on-line "Library Reference Guide" document for +# additional timespec features and more information. +# +# +############################################################ +# # +# LOCATION and ATTRIBUTE SPECIFICATIONS # +# # +############################################################ +# Pin and CLB location locking constraints # +############################################################ +# +# ----------------------- +# Assign an IO pin number +# ----------------------- +#INST io_buf_instance_name LOC = P110 ; +#NET io_net_name LOC = P111 ; +# +# ----------------------- +# Assign a signal to a range of I/O pins +# ----------------------- +#NET "signal_name" LOC=P32, P33, P34; +# +# ----------------------- +# Place a logic element(called a BEL) in a specific CLB location. +# BEL = FF, LUT, RAM, etc... +# ----------------------- +#INST instance_path/BEL_inst_name LOC = CLB_R17C36 ; +# +# ----------------------- +# Place CLB in rectangular area from CLB R1C1 to CLB R5C7 +# ----------------------- +#INST /U1/U2/reg<0> LOC=clb_r1c1:clb_r5c7; +# +# ----------------------- +# Place hierarchical logic block in rectangular area from CLB R1C1 to CLB R5C7 +# ----------------------- +#INST /U1* LOC=clb_r1c1:clb_r5c7; +# +# ----------------------- +# Prohibit IO pin P26 or CLBR5C3 from being used: +# ----------------------- +#CONFIG PROHIBIT = P26 ; +#CONFIG PROHIBIT = CLB_R5C3 ; +# Config Prohibit is very important for forcing the software to not use critical +# configuration pins like INIT or DOUT on the FPGA. The Mode pins and JTAG +# Pins require a special pad so they will not be available to this constraint +# +# ----------------------- +# Assign an OBUF to be FAST or SLOW: +# ----------------------- +#INST obuf_instance_name FAST ; +#INST obuf_instance_name SLOW ; +# +# ----------------------- +# FPGAs only: IOB input Flip-flop delay specification +# ----------------------- +# Declare an IOB input FF delay (default = MAXDELAY). +# NOTE: MEDDELAY/NODELAY can be attached to a CLB FF that is pushed +# into an IOB by the "map -pr i" option. +#INST input_ff_instance_name MEDDELAY ; +#INST input_ff_instance_name NODELAY ; +# +# ----------------------- +# Assign Global Clock Buffers Lower Left Right Side +# ----------------------- +# INST gbuf1 LOC=SSW +# +# # + +NET "CLK" IOSTANDARD = PCI33_5 ; +NET "CLK" TNM_NET = "CLK"; +NET "CRT_CLK" TNM_NET = "CRT_CLK"; + +TIMESPEC "TS_CLK" = PERIOD "CLK" 30 ns HIGH 50 %; +TIMESPEC "TS_CRT_CLK" = PERIOD "CRT_CLK" 44 ns HIGH 50 %; +TIMESPEC "TS_CLK_2_CRT_CLK" = FROM : "CLK" : TO : "CRT_CLK" : 5 ; +TIMESPEC "TS_CRT_CLK_2_CLK" = FROM : "CRT_CLK" : TO : "CLK" : 5 ; + +INST "AD0.PAD" TNM = "PCI_AD"; +INST "AD1.PAD" TNM = "PCI_AD"; +INST "AD2.PAD" TNM = "PCI_AD"; +INST "AD3.PAD" TNM = "PCI_AD"; +INST "AD4.PAD" TNM = "PCI_AD"; +INST "AD5.PAD" TNM = "PCI_AD"; +INST "AD6.PAD" TNM = "PCI_AD"; +INST "AD7.PAD" TNM = "PCI_AD"; +INST "AD8.PAD" TNM = "PCI_AD"; +INST "AD9.PAD" TNM = "PCI_AD"; +INST "AD10.PAD" TNM = "PCI_AD"; +INST "AD11.PAD" TNM = "PCI_AD"; +INST "AD12.PAD" TNM = "PCI_AD"; +INST "AD13.PAD" TNM = "PCI_AD"; +INST "AD14.PAD" TNM = "PCI_AD"; +INST "AD15.PAD" TNM = "PCI_AD"; +INST "AD16.PAD" TNM = "PCI_AD"; +INST "AD17.PAD" TNM = "PCI_AD"; +INST "AD18.PAD" TNM = "PCI_AD"; +INST "AD19.PAD" TNM = "PCI_AD"; +INST "AD20.PAD" TNM = "PCI_AD"; +INST "AD21.PAD" TNM = "PCI_AD"; +INST "AD22.PAD" TNM = "PCI_AD"; +INST "AD23.PAD" TNM = "PCI_AD"; +INST "AD24.PAD" TNM = "PCI_AD"; +INST "AD25.PAD" TNM = "PCI_AD"; +INST "AD26.PAD" TNM = "PCI_AD"; +INST "AD27.PAD" TNM = "PCI_AD"; +INST "AD28.PAD" TNM = "PCI_AD"; +INST "AD29.PAD" TNM = "PCI_AD"; +INST "AD30.PAD" TNM = "PCI_AD"; +INST "AD31.PAD" TNM = "PCI_AD"; +TIMEGRP "PCI_AD" OFFSET = IN 7 ns BEFORE "CLK"; +TIMEGRP "PCI_AD" OFFSET = OUT 11 ns AFTER "CLK"; +NET "AD0" IOSTANDARD = PCI33_5; +NET "AD1" IOSTANDARD = PCI33_5; +NET "AD2" IOSTANDARD = PCI33_5; +NET "AD3" IOSTANDARD = PCI33_5; +NET "AD4" IOSTANDARD = PCI33_5; +NET "AD5" IOSTANDARD = PCI33_5; +NET "AD6" IOSTANDARD = PCI33_5; +NET "AD7" IOSTANDARD = PCI33_5; +NET "AD8" IOSTANDARD = PCI33_5; +NET "AD9" IOSTANDARD = PCI33_5; +NET "AD10" IOSTANDARD = PCI33_5; +NET "AD11" IOSTANDARD = PCI33_5; +NET "AD12" IOSTANDARD = PCI33_5; +NET "AD13" IOSTANDARD = PCI33_5; +NET "AD14" IOSTANDARD = PCI33_5; +NET "AD15" IOSTANDARD = PCI33_5; +NET "AD16" IOSTANDARD = PCI33_5; +NET "AD17" IOSTANDARD = PCI33_5; +NET "AD18" IOSTANDARD = PCI33_5; +NET "AD19" IOSTANDARD = PCI33_5; +NET "AD20" IOSTANDARD = PCI33_5; +NET "AD21" IOSTANDARD = PCI33_5; +NET "AD22" IOSTANDARD = PCI33_5; +NET "AD23" IOSTANDARD = PCI33_5; +NET "AD24" IOSTANDARD = PCI33_5; +NET "AD25" IOSTANDARD = PCI33_5; +NET "AD26" IOSTANDARD = PCI33_5; +NET "AD27" IOSTANDARD = PCI33_5; +NET "AD28" IOSTANDARD = PCI33_5; +NET "AD29" IOSTANDARD = PCI33_5; +NET "AD30" IOSTANDARD = PCI33_5; +NET "AD31" IOSTANDARD = PCI33_5; +INST "CBE0.PAD" TNM = "PCI_CBE"; +INST "CBE1.PAD" TNM = "PCI_CBE"; +INST "CBE2.PAD" TNM = "PCI_CBE"; +INST "CBE3.PAD" TNM = "PCI_CBE"; + +TIMEGRP "PCI_CBE" OFFSET = IN 7 ns BEFORE "CLK"; +TIMEGRP "PCI_CBE" OFFSET = OUT 11 ns AFTER "CLK"; + +NET "CBE0" IOSTANDARD = PCI33_5; +NET "CBE1" IOSTANDARD = PCI33_5; +NET "CBE2" IOSTANDARD = PCI33_5; +NET "CBE3" IOSTANDARD = PCI33_5; + +#INST "DEVSEL.PAD" TNM = "PCI_CTRL" ; + +NET "DEVSEL" OFFSET = IN 7 ns BEFORE "CLK"; + +NET "DEVSEL" OFFSET = OUT 11 ns AFTER "CLK"; + +NET "DEVSEL" IOSTANDARD = PCI33_5; + +NET "FRAME" OFFSET = IN 7 ns BEFORE "CLK"; + +NET "FRAME" OFFSET = OUT 11 ns AFTER "CLK"; + +NET "FRAME" IOSTANDARD = PCI33_5; + +#INST "FRAME.PAD" TNM = "PCI_CTRL" ; + +NET "GNT" OFFSET = IN 10 ns BEFORE "CLK"; + +NET "GNT" IOSTANDARD = PCI33_5; +NET "RST" IOSTANDARD = PCI33_5; +NET "INTA" IOSTANDARD = PCI33_5; + +#INST "GNT.PAD" TNM = "PCI_GNT" ; + +NET "IRDY" OFFSET = IN 7 ns BEFORE "CLK"; +NET "IRDY" OFFSET = OUT 11 ns AFTER "CLK"; + +NET "IRDY" IOSTANDARD = PCI33_5; + +#INST "IRDY.PAD" TNM="PCI_CTRL" ; + +NET "PAR" OFFSET = IN 7 ns BEFORE "CLK"; +NET "PAR" OFFSET = OUT 11 ns AFTER "CLK"; + +NET "PAR" IOSTANDARD = PCI33_5; + +#INST "PAR.PAD" TNM = "PCI_CTRL" ; + +NET "PERR" OFFSET = IN 7 ns BEFORE "CLK"; + +NET "PERR" OFFSET = OUT 11 ns AFTER "CLK"; + +NET "PERR" IOSTANDARD = PCI33_5; + +#INST "PERR.PAD" TNM = "PCI_CTRL" ; + +NET "REQ" OFFSET = OUT 12 ns AFTER "CLK"; + +NET "REQ" IOSTANDARD = PCI33_5; + +#INST "REQ.PAD" TNM = "PCI_REQ" ; + +NET "SERR" OFFSET = OUT 11 ns AFTER "CLK"; + +NET "SERR" IOSTANDARD = PCI33_5; + +#INST "SERR.PAD" TNM = "PCI_CTRL" ; + +NET "STOP" OFFSET = IN 7 ns BEFORE "CLK"; +NET "STOP" OFFSET = OUT 11 ns AFTER "CLK"; + +NET "STOP" IOSTANDARD = PCI33_5; + +#INST "STOP.PAD" TNM = "PCI_CTRL" ; + +NET "TRDY" OFFSET = IN 7 ns BEFORE "CLK"; +NET "TRDY" OFFSET = OUT 11 ns AFTER "CLK"; + +NET "TRDY" IOSTANDARD = PCI33_5; + +#INST "TRDY.PAD" TNM = "PCI_CTRL" ; + +NET "IDSEL" OFFSET = IN 7ns BEFORE "CLK" ; +NET "IDSEL" IOSTANDARD = PCI33_5 ; + +################################################################################## +# Pin locations +################################################################################## +NET "CLK" LOC = "P185" ; +NET "INTA" LOC = "P195" ; +NET "RST" LOC = "P199" ; +NET "GNT" LOC = "P200" ; +NET "REQ" LOC = "P201" ; +NET "AD31" LOC = "P203" ; +NET "AD30" LOC = "P204" ; +NET "AD29" LOC = "P205" ; +NET "AD28" LOC = "P206" ; +NET "AD27" LOC = "P3" ; +NET "AD26" LOC = "P4" ; +NET "AD25" LOC = "P5" ; +NET "AD24" LOC = "P6" ; +NET "CBE3" LOC = "P8" ; +NET "IDSEL" LOC = "P9" ; +NET "AD23" LOC = "P10" ; +NET "AD22" LOC = "P14" ; +NET "AD21" LOC = "P15" ; +NET "AD20" LOC = "P16" ; +NET "AD19" LOC = "P17" ; +NET "AD18" LOC = "P18" ; +NET "AD17" LOC = "P20" ; +NET "AD16" LOC = "P21" ; +NET "CBE2" LOC = "P22" ; +NET "FRAME" LOC = "P23" ; +NET "IRDY" LOC = "P24" ; +# +NET "TRDY" LOC = "P27" ; +NET "DEVSEL" LOC = "P29" ; +NET "STOP" LOC = "P30" ; +NET "PERR" LOC = "P31" ; +NET "SERR" LOC = "P33" ; +NET "PAR" LOC = "P34" ; +NET "CBE1" LOC = "P35" ; +NET "AD15" LOC = "P36" ; +NET "AD14" LOC = "P37" ; +NET "AD13" LOC = "P41" ; +NET "AD12" LOC = "P42" ; +NET "AD11" LOC = "P43" ; +NET "AD10" LOC = "P45" ; +NET "AD9" LOC = "P46" ; +NET "AD8" LOC = "P47" ; +NET "CBE0" LOC = "P48" ; +NET "AD7" LOC = "P49" ; +NET "AD6" LOC = "P57" ; +NET "AD5" LOC = "P58" ; +NET "AD4" LOC = "P59" ; +NET "AD3" LOC = "P61" ; +NET "AD2" LOC = "P62" ; +NET "AD1" LOC = "P63" ; +NET "AD0" LOC = "P67" ; + +# +#NET "HSYNC" LOC = "P188" ; +#NET "VSYNC" LOC = "P187" ; +#NET "RGB<0>" LOC = "P81" ; +#NET "RGB<1>" LOC = "P82" ; +#NET "RGB<2>" LOC = "P83" ; +#NET "RGB<3>" LOC = "P84" ; +# +NET "CRT_CLK" LOC = "P182" ; +NET "HSYNC" LOC = "P83" ; +NET "VSYNC" LOC = "P84" ; +NET "RGB4" LOC = "P166" ; +NET "RGB5" LOC = "P167" ; +NET "RGB6" LOC = "P168" ; +NET "RGB7" LOC = "P172" ; +NET "RGB8" LOC = "P173" ; +NET "RGB9" LOC = "P174" ; +NET "RGB10" LOC = "P175" ; +NET "RGB11" LOC = "P176" ; +NET "RGB12" LOC = "P178" ; +NET "RGB13" LOC = "P179" ; +NET "RGB14" LOC = "P180" ; +NET "RGB15" LOC = "P181" ; +NET "LED" LOC = "P202" ; +# + +################################################################################## +# IOB force +################################################################################## +INST "bridge/pci_io_mux/ad_iob0/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob1/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob2/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob3/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob4/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob5/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob6/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob7/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob8/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob9/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob10/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob11/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob12/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob13/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob14/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob15/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob16/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob17/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob18/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob19/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob20/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob21/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob22/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob23/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob24/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob25/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob26/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob27/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob28/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob29/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob30/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob31/dat_out_reg" IOB = TRUE ; + +#################################################################################### +# Force output enable IOBs +#################################################################################### +INST "bridge/pci_io_mux/ad_iob0/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob1/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob2/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob3/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob4/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob5/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob6/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob7/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob8/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob9/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob10/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob11/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob12/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob13/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob14/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob15/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob16/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob17/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob18/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob19/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob20/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob21/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob22/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob23/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob24/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob25/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob26/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob27/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob28/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob29/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob30/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/ad_iob31/en_out_reg" IOB = TRUE ; + +#################################################################################### +# CBE IOBs +#################################################################################### +INST "bridge/pci_io_mux/cbe_iob0/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/cbe_iob1/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/cbe_iob2/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/cbe_iob3/dat_out_reg" IOB = TRUE ; + +INST "bridge/pci_io_mux/cbe_iob0/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/cbe_iob1/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/cbe_iob2/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/cbe_iob3/en_out_reg" IOB = TRUE ; + +#################################################################################### +# Control signals IOBs +#################################################################################### +INST "bridge/pci_io_mux/frame_iob/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/frame_iob/en_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/irdy_iob/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/irdy_iob/en_out_reg" IOB = TRUE ; + +INST "bridge/pci_io_mux/trdy_iob/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/trdy_iob/en_out_reg" IOB = TRUE ; + +INST "bridge/pci_io_mux/devsel_iob/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/devsel_iob/en_out_reg" IOB = TRUE ; + +INST "bridge/pci_io_mux/stop_iob/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/stop_iob/en_out_reg" IOB = TRUE ; + +INST "bridge/pci_io_mux/par_iob/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/par_iob/en_out_reg" IOB = TRUE ; + +INST "bridge/pci_io_mux/perr_iob/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/perr_iob/en_out_reg" IOB = TRUE ; + +INST "bridge/pci_io_mux/serr_iob/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/serr_iob/en_out_reg" IOB = TRUE ; + +INST "bridge/pci_io_mux/req_iob/dat_out_reg" IOB = TRUE ; +INST "bridge/pci_io_mux/req_iob/en_out_reg" IOB = TRUE ; + +#INST "bridge/wishbone_slave_unit/pci_initiator_if" TNM=FFS:PCI_MIF_FFS ; +#INST "bridge/wishbone_slave_unit/pci_initiator_sm" TNM=FFS:PCI_MSM_FFS ; +#INST "bridge/pci_io_mux/frame_iob/dat_out_reg" TNM=FFS:PCI_O_FFS ; +#INST "bridge/parity_checker" TNM=FFS:PCI_PAR_FFS ; +#INST "bridge/input_register" TNM=FFS:PCI_I_FFS ; + +#TIMEGRP "ALL_PCI_FFS" = "PCI_O_FFS" ; + +#TIMESPEC TS_PCI_AD_SETUP = FROM : "PCI_AD" : TO : "ALL_PCI_FFS" : 7.000 ; +#TIMESPEC TS_PCI_CBE_SETUP = FROM : "PCI_CBE" : TO : "ALL_PCI_FFS" : 7.000 ; +#TIMESPEC TS_PCI_CTRL_SETUP = FROM : "PCI_CTRL" : TO : "ALL_PCI_FFS" : 7.000 ; + +#TIMESPEC TS_PCI_REQ_TIME_OUT = FROM : "ALL_PCI_FFS" : TO : "PCI_REQ" : 12.000 ; +#TIMESPEC TS_PCI_GNT_SETUP = FROM : "PCI_GNT" : TO : "ALL_PCI_FFS" : 10.000 ; + +#TIMESPEC TS_PCI_AD_HOLD = FROM : "ALL_PCI_FFS" : TO : "PCI_AD" : 11.000 ; +#TIMESPEC TS_PCI_CBE_HOLD = FROM : "ALL_PCI_FFS" : TO : "PCI_CBE" : 11.000 ; +#TIMESPEC TS_PCI_CTRL_HOLD = FROM : "ALL_PCI_FFS" : TO : "PCI_CTRL" : 11.000 ; Index: crt/syn/out/bit/fe.log =================================================================== --- crt/syn/out/bit/fe.log (nonexistent) +++ crt/syn/out/bit/fe.log (revision 154) @@ -0,0 +1,742 @@ +ngdbuild -p xc2s150-5-pq208 -uc pci_crt.ucf -dd .. f:\mihad\fpga_t~1\pci_crt\pci_crt.edf pci_crt.ngd +Release 3.3.08i - ngdbuild D.27 +Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. + +Command Line: ngdbuild -p xc2s150-5-pq208 -uc pci_crt.ucf -dd .. +f:\mihad\fpga_t~1\pci_crt\pci_crt.edf pci_crt.ngd + +Launcher: Executing edif2ngd "f:\mihad\fpga_t~1\pci_crt\pci_crt.edf" +"F:\mihad\fpga_t~1\pci_crt\xproj\ver2\pci_crt.ngo" +Release 3.3.08i - edif2ngd D.27 +Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. +Writing the design to "F:/mihad/fpga_t~1/pci_crt/xproj/ver2/pci_crt.ngo"... +Reading NGO file "F:/mihad/fpga_t~1/pci_crt/xproj/ver2/pci_crt.ngo" ... +Reading component libraries for design expansion... + +Annotating constraints to design from file "pci_crt.ucf" ... + +Checking timing specifications ... + +Checking expanded design ... +WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol "CRT/ssvga_pallete", the + following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, + INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, + INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be + used. +WARNING:NgdBuild:526 - On the RAMB4_S8_S16 symbol "CRT/ssvga_fifo/ramb4_s8_1", + the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, + INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, + INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be + used. +WARNING:NgdBuild:526 - On the RAMB4_S8_S16 symbol "CRT/ssvga_fifo/ramb4_s8_0", + the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, + INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, + INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be + used. +WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol + "bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_0", the + following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, + INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, + INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be + used. +WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol + "bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_1", the + following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, + INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, + INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be + used. +WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol + "bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2", the + following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, + INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, + INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be + used. + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 6 + +Writing NGD file "pci_crt.ngd" ... + +Writing NGDBUILD log file "pci_crt.bld"... + +NGDBUILD done. + +================================================== + +map -p xc2s150-5-pq208 -o map.ncd -pr b pci_crt.ngd pci_crt.pcf +Release 3.3.08i - Map D.27 +Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. +Using target part "2s150pq208-5". +Reading NGD file "pci_crt.ngd"... +Processing FMAPs... +Removing unused or disabled logic... +Running cover... +Writing file map.ngm... +Running directed packing... +Running delay-based packing... +Running related packing... +Writing design file "map.ncd"... + +Design Summary: + Number of errors: 0 + Number of warnings: 72 + Number of Slices: 1,402 out of 1,728 81% + Number of Slices containing + unrelated logic: 0 out of 1,402 0% + Number of Slice Flip Flops: 1,135 out of 3,456 32% + Total Number 4 input LUTs: 1,863 out of 3,456 53% + Number used as LUTs: 1,720 + Number used as a route-thru: 1 + Number used for Dual Port RAMs: 142 + (Two LUTs used per Dual Port RAM) + Number of bonded IOBs: 64 out of 140 45% + IOB Flip Flops: 147 + Number of Block RAMs: 6 out of 12 50% + Number of GCLKs: 2 out of 4 50% + Number of GCLKIOBs: 2 out of 4 50% +Total equivalent gate count for design: 129,333 +Additional JTAG gate count for IOBs: 3,168 + +Removed Logic Summary: + 11 block(s) removed + 121 block(s) optimized away + 1 signal(s) removed + +Mapping completed. +See MAP report file "map.mrp" for details. + +================================================== + +par -w -ol 2 map.ncd pci_crt.ncd pci_crt.pcf +Release 3.3.08i - Par D.27 +Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. + + + + +Constraints file: pci_crt.pcf + +Loading design for application par from file map.ncd. + "TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5 +Loading device for application par from file 'v150.nph' in environment +C:/Foundation. +Device speed data version: PRELIMINARY 1.21 2001-04-09. + + +Resolving physical constraints. +Finished resolving physical constraints. + +Device utilization summary: + + Number of External GCLKIOBs 2 out of 4 50% + Number of External IOBs 64 out of 140 45% + + Number of BLOCKRAMs 6 out of 12 50% + Number of SLICEs 1402 out of 1728 81% + + Number of GCLKs 2 out of 4 50% + + + +Overall effort level (-ol): 2 (set by user) +Placer effort level (-pl): 2 (set by user) +Placer cost table entry (-t): 1 +Router effort level (-rl): 2 (set by user) + +Starting initial Timing Analysis. REAL time: 14 secs +Finished initial Timing Analysis. REAL time: 40 secs + +Design passed SelectIO DRC. +Starting the placer. REAL time: 43 secs +Placement pass 1 ................... +Placer score = 379658 +Placement pass 2 ......................... +Placer score = 368407 +Placement pass 3 ..................... +Placer score = 369308 +Optimizing ... +Placer score = 301933 +Improving the placement. REAL time: 1 mins 15 secs +Placer score = 474349 +Placer score = 507794 +Placer score = 471774 +Placer score = 440616 +Placer score = 418456 +Placer score = 403030 +Placer score = 390280 +Placer score = 381864 +Placer score = 372761 +Placer score = 367215 +Placer score = 361011 +Placer score = 356024 +Placer score = 346592 +Placer score = 342238 +Placer score = 339291 +Placer score = 335589 +Placer score = 332722 +Placer score = 328768 +Placer score = 324807 +Placer score = 319970 +Placer score = 316171 +Placer score = 310589 +Placer score = 305289 +Placer score = 300126 +Placer score = 295734 +Placer score = 293094 +Placer score = 290570 +Placer score = 288768 +Placer score = 287281 +Placer score = 285736 +Placer score = 284379 +Placer score = 283262 +Placer score = 282647 +Placer score = 282077 +Placer stage completed in real time: 2 mins 38 secs + +All IOBs have been constrained to specific sites. + +Select IO Utilization and Usage Summary +_______________________________________ + +NR - means Not Required. +Each Group of a specific Standard is listed. + +IO standard (PCI33_5 Vref=NR Vcco=3.30) occupies 48 pads. +IO standard (LVTTL Vref=NR Vcco=3.30) occupies 18 pads. + +Bank Summary +____________ +If an IOB is placed in a Vref site, it will be indicated by the word 'Vref' at +the end of a summary row. IOBs can be placed in a bank's Vref sites when none of +the IOBs in the bank require a Vref site. +NR - means Not Required + +Bank 0 has 17 pads and is 58% utilized. +Vref should be set to NR volts. +Vcco should be set to 3.30 volts. + Name IO Select Std Vref Vcco Pad Pin + ---- -- ---------- ------ ------ ------ ------ + AD<28> IO PCI33_5 NR 3.30 PAD2 P206 + AD<29> IO PCI33_5 NR 3.30 PAD6 P205 + AD<30> IO PCI33_5 NR 3.30 PAD10 P204 + AD<31> IO PCI33_5 NR 3.30 PAD11 P203 Vref + LED O LVTTL 3.30 PAD12 P202 + REQ O PCI33_5 3.30 PAD16 P201 + GNT I PCI33_5 NR PAD18 P200 Vref + RST I PCI33_5 NR PAD19 P199 + INTA O PCI33_5 3.30 PAD20 P195 + CLK I LVTTL NR GCLKPAD3 P185 + +Bank 1 has 19 pads and is 68% utilized. +Vref should be set to NR volts. +Vcco should be set to 3.30 volts. + Name IO Select Std Vref Vcco Pad Pin + ---- -- ---------- ------ ------ ------ ------ + CRT_CLK I LVTTL NR GCLKPAD2 P182 + RGB<15> O LVTTL 3.30 PAD38 P181 + RGB<14> O LVTTL 3.30 PAD40 P180 + RGB<13> O LVTTL 3.30 PAD42 P179 + RGB<12> O LVTTL 3.30 PAD43 P178 Vref + RGB<11> O LVTTL 3.30 PAD44 P176 + RGB<10> O LVTTL 3.30 PAD45 P175 + RGB<9> O LVTTL 3.30 PAD48 P174 + RGB<8> O LVTTL 3.30 PAD52 P173 + RGB<7> O LVTTL 3.30 PAD53 P172 + RGB<6> O LVTTL 3.30 PAD54 P168 + RGB<5> O LVTTL 3.30 PAD55 P167 Vref + RGB<4> O LVTTL 3.30 PAD57 P166 + +Bank 4 has 19 pads and is 10% utilized. +Vcco should be set to 3.30 volts. + Name IO Select Std Vref Vcco Pad Pin + ---- -- ---------- ------ ------ ------ ------ + VSYNC O LVTTL 3.30 PAD174 P84 Vref + HSYNC O LVTTL 3.30 PAD175 P83 + +Bank 5 has 16 pads and is 43% utilized. +Vref should be set to NR volts. +Vcco should be set to 3.30 volts. + Name IO Select Std Vref Vcco Pad Pin + ---- -- ---------- ------ ------ ------ ------ + AD<0> IO PCI33_5 NR 3.30 PAD197 P67 + AD<1> IO PCI33_5 NR 3.30 PAD198 P63 + AD<2> IO PCI33_5 NR 3.30 PAD199 P62 Vref + AD<3> IO PCI33_5 NR 3.30 PAD201 P61 + AD<4> IO PCI33_5 NR 3.30 PAD206 P59 Vref + AD<5> IO PCI33_5 NR 3.30 PAD207 P58 + AD<6> IO PCI33_5 NR 3.30 PAD211 P57 + +Bank 6 has 18 pads and is 94% utilized. +Vref should be set to NR volts. +Vcco should be set to 3.30 volts. + Name IO Select Std Vref Vcco Pad Pin + ---- -- ---------- ------ ------ ------ ------ + AD<7> IO PCI33_5 NR 3.30 PAD217 P49 + CBE<0> IO PCI33_5 NR 3.30 PAD218 P48 + AD<8> IO PCI33_5 NR 3.30 PAD222 P47 + AD<9> IO PCI33_5 NR 3.30 PAD226 P46 + AD<10> IO PCI33_5 NR 3.30 PAD227 P45 Vref + AD<11> IO PCI33_5 NR 3.30 PAD232 P43 + AD<12> IO PCI33_5 NR 3.30 PAD234 P42 Vref + AD<13> IO PCI33_5 NR 3.30 PAD235 P41 + AD<14> IO PCI33_5 NR 3.30 PAD236 P37 + AD<15> IO PCI33_5 NR 3.30 PAD237 P36 + CBE<1> IO PCI33_5 NR 3.30 PAD241 P35 + PAR IO PCI33_5 NR 3.30 PAD244 P34 + SERR O PCI33_5 3.30 PAD245 P33 + PERR IO PCI33_5 NR 3.30 PAD246 P31 Vref + STOP IO PCI33_5 NR 3.30 PAD247 P30 + DEVSEL IO PCI33_5 NR 3.30 PAD249 P29 + TRDY IO PCI33_5 NR 3.30 PAD252 P27 + +Bank 7 has 18 pads and is 94% utilized. +Vref should be set to NR volts. +Vcco should be set to 3.30 volts. + Name IO Select Std Vref Vcco Pad Pin + ---- -- ---------- ------ ------ ------ ------ + IRDY IO PCI33_5 NR 3.30 PAD253 P24 + FRAME IO PCI33_5 NR 3.30 PAD254 P23 + CBE<2> IO PCI33_5 NR 3.30 PAD256 P22 + AD<16> IO PCI33_5 NR 3.30 PAD258 P21 + AD<17> IO PCI33_5 NR 3.30 PAD259 P20 Vref + AD<18> IO PCI33_5 NR 3.30 PAD260 P18 + AD<19> IO PCI33_5 NR 3.30 PAD261 P17 + AD<20> IO PCI33_5 NR 3.30 PAD264 P16 + AD<21> IO PCI33_5 NR 3.30 PAD268 P15 + AD<22> IO PCI33_5 NR 3.30 PAD269 P14 + AD<23> IO PCI33_5 NR 3.30 PAD270 P10 + IDSEL I LVTTL NR PAD271 P9 Vref + CBE<3> IO PCI33_5 NR 3.30 PAD273 P8 + AD<24> IO PCI33_5 NR 3.30 PAD278 P6 Vref + AD<25> IO PCI33_5 NR 3.30 PAD279 P5 + AD<26> IO PCI33_5 NR 3.30 PAD283 P4 + AD<27> IO PCI33_5 NR 3.30 PAD287 P3 + +Placer completed in real time: 2 mins 40 secs + +Dumping design to file pci_crt.ncd. + +Total REAL time to Placer completion: 2 mins 49 secs +Total CPU time to Placer completion: 2 mins 30 secs + +0 connection(s) routed; 9789 unrouted active, 56 unrouted PWR/GND. +Starting router resource preassignment +Completed router resource preassignment. REAL time: 3 mins 4 secs +Starting iterative routing. +Routing active signals. +..................... +End of iteration 1 +9845 successful; 0 unrouted; (0) REAL time: 5 mins 31 secs +Constraints are met. +Total REAL time: 5 mins 36 secs +Total CPU time: 5 mins +End of route. 9845 routed (100.00%); 0 unrouted. +No errors found. +Completely routed. + +Total REAL time to Router completion: 5 mins 43 secs +Total CPU time to Router completion: 5 mins 5 secs + +Generating PAR statistics. +Timing Score: 0 + +Asterisk (*) preceding a constraint indicates it was not met. + +-------------------------------------------------------------------------------- + Constraint | Requested | Actual | Logic + | | | Levels +-------------------------------------------------------------------------------- + TS_CLK = PERIOD TIMEGRP "CLK" 30 nS HI | 30.000ns | 23.294ns | 8 + GH 50.000 % | | | +-------------------------------------------------------------------------------- + TS_CRT_CLK = PERIOD TIMEGRP "CRT_CLK" 44 | 44.000ns | 23.360ns | 6 + nS HIGH 50.000 % | | | +-------------------------------------------------------------------------------- + TS_CLK_2_CRT_CLK = MAXDELAY FROM TIMEGRP | 30.000ns | 21.603ns | 9 + "CLK" TO TIMEGRP "CRT_CLK" 30 nS | | | +-------------------------------------------------------------------------------- + TS_CRT_CLK_2_CLK = MAXDELAY FROM TIMEGRP | 30.000ns | 16.423ns | 8 + "CRT_CLK" TO TIMEGRP "CLK" 30 nS | | | +-------------------------------------------------------------------------------- + COMP "REQ" OFFSET = OUT 12 nS AFTER COMP | 12.000ns | 9.486ns | 1 + "CLK" | | | +-------------------------------------------------------------------------------- + COMP "SERR" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.434ns | 1 + P "CLK" | | | +-------------------------------------------------------------------------------- + COMP "GNT" OFFSET = IN 10 nS BEFORE COMP | 10.000ns | 9.535ns | 5 + "CLK" | | | +-------------------------------------------------------------------------------- + COMP "FRAME" OFFSET = IN 7 nS BEFORE COM | 7.000ns | 6.287ns | 4 + P "CLK" | | | +-------------------------------------------------------------------------------- + COMP "FRAME" OFFSET = OUT 11 nS AFTER CO | 11.000ns | 9.432ns | 1 + MP "CLK" | | | +-------------------------------------------------------------------------------- + COMP "IRDY" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 6.442ns | 4 + "CLK" | | | +-------------------------------------------------------------------------------- + COMP "IRDY" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.432ns | 1 + P "CLK" | | | +-------------------------------------------------------------------------------- + COMP "DEVSEL" OFFSET = IN 7 nS BEFORE CO | 7.000ns | 3.800ns | 3 + MP "CLK" | | | +-------------------------------------------------------------------------------- + COMP "DEVSEL" OFFSET = OUT 11 nS AFTER C | 11.000ns | 9.432ns | 1 + OMP "CLK" | | | +-------------------------------------------------------------------------------- + COMP "TRDY" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 6.473ns | 3 + "CLK" | | | +-------------------------------------------------------------------------------- + COMP "TRDY" OFFSET = OUT 10 nS AFTER COM | 10.000ns | 9.435ns | 1 + P "CLK" | | | +-------------------------------------------------------------------------------- + COMP "STOP" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 5.665ns | 3 + "CLK" | | | +-------------------------------------------------------------------------------- + COMP "STOP" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.432ns | 1 + P "CLK" | | | +-------------------------------------------------------------------------------- + COMP "PAR" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 4.610ns | 4 + "CLK" | | | +-------------------------------------------------------------------------------- + COMP "PAR" OFFSET = OUT 11 nS AFTER COMP | 11.000ns | 9.434ns | 1 + "CLK" | | | +-------------------------------------------------------------------------------- + COMP "PERR" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 2.145ns | 2 + "CLK" | | | +-------------------------------------------------------------------------------- + COMP "PERR" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.434ns | 1 + P "CLK" | | | +-------------------------------------------------------------------------------- + TIMEGRP "PCI_AD" OFFSET = IN 7 nS BEFORE | 7.000ns | 2.762ns | 1 + COMP "CLK" | | | +-------------------------------------------------------------------------------- + TIMEGRP "PCI_AD" OFFSET = OUT 11 nS AFTE | 11.000ns | 9.540ns | 1 + R COMP "CLK" | | | +-------------------------------------------------------------------------------- + TIMEGRP "PCI_CBE" OFFSET = IN 7 nS BEFOR | 7.000ns | 5.437ns | 4 + E COMP "CLK" | | | +-------------------------------------------------------------------------------- + TIMEGRP "PCI_CBE" OFFSET = OUT 11 nS AFT | 11.000ns | 9.435ns | 1 + ER COMP "CLK" | | | +-------------------------------------------------------------------------------- + + +All constraints were met. +Dumping design to file pci_crt.ncd. + + +All signals are completely routed. + +Total REAL time to PAR completion: 7 mins 13 secs +Total CPU time to PAR completion: 6 mins 10 secs + +Placement: Completed - No errors found. +Routing: Completed - No errors found. +Timing: Completed - No errors found. + +PAR done. + +================================================== + +trce pci_crt.ncd pci_crt.pcf -e 3 -o pci_crt.twr -xml pci_crt_trce.xml +Release 3.3.08i - Trace D.27 +Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. + + + +Loading design for application trce from file pci_crt.ncd. + "TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5 +Loading device for application trce from file 'v150.nph' in environment +C:/Foundation. +-------------------------------------------------------------------------------- +Xilinx TRACE, Version D.27 +Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. + +trce pci_crt.ncd pci_crt.pcf -e 3 -o pci_crt.twr -xml pci_crt_trce.xml + +Design file: pci_crt.ncd +Physical constraint file: pci_crt.pcf +Device,speed: xc2s150,-5 (PRELIMINARY 1.21 2001-04-09) +Report level: error report +-------------------------------------------------------------------------------- + + + +Timing summary: +--------------- + +Timing errors: 0 Score: 0 + +Constraints cover 97754 paths, 0 nets, and 8987 connections (91.8% coverage) + +Design statistics: + Minimum period: 23.360ns (Maximum frequency: 42.808MHz) + Maximum path delay from/to any node: 21.603ns + Minimum input arrival time before clock: 9.535ns + Minimum output required time after clock: 9.540ns + + +Analysis completed Tue Jan 15 13:36:48 2002 +-------------------------------------------------------------------------------- + +Total time: 1 mins 6 secs + +================================================== + +ngdanno pci_crt.ncd +Release 3.3.08i - ngdanno D.27 +Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. + +Loading design for application ngdanno from file pci_crt.ncd. + "TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5 +Loading device for application ngdanno from file 'v150.nph' in environment +C:/Foundation. +Loading constraints from file "pci_crt.pcf"... +WARNING:Anno:12 - Since the .ngm file was not specified, the .nga will be + created from the .ncd. +Building NGA image... +Annotating NGA image... +Distributing delays... +Resolving logical and physical hierarchies... +Running NGD DRC... +WARNING:Ngd:333 - NOTE: This design contains the undriven net "GSR" which you + could drive during simulation to get valid results. +WARNING:Ngd:333 - NOTE: This design contains the undriven net "GTS" which you + could drive during simulation to get valid results. +Writing .nga file "pci_crt.nga"... + 1476 physical models annotated + +================================================== + +ngd2ver -w pci_crt.nga pci_crt_time_sim.v +Release 3.3.08i - ngd2ver D.27 +Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. +--- Initializing ... + --- Reading pci_crt.nga. + --- Running prep. + --- Initializing module list. +--- Processing netlist ... +WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[10] not found for + wire bus bridge/pciu_err_addr_out[31:0] on block TOP. +WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[9] not found for + wire bus bridge/pciu_err_addr_out[31:0] on block TOP. +WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[8] not found for + wire bus bridge/pciu_err_addr_out[31:0] on block TOP. +WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[7] not found for + wire bus bridge/pciu_err_addr_out[31:0] on block TOP. +WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[6] not found for + wire bus bridge/pciu_err_addr_out[31:0] on block TOP. +WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[5] not found for + wire bus bridge/pciu_err_addr_out[31:0] on block TOP. +WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[4] not found for + wire bus bridge/pciu_err_addr_out[31:0] on block TOP. +WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[3] not found for + wire bus bridge/pciu_err_addr_out[31:0] on block TOP. +WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[2] not found for + wire bus bridge/pciu_err_addr_out[31:0] on block TOP. +WARNING:NetListWriters:107 - Signal bus bridge/pciu_err_addr_out[31:0] on block + TOP is not reconstructed. +WARNING:NetListWriters:106 - Wire + bridge/pci_target_unit/pcit_if_pciw_fifo_control_out[1] not found for wire + bus bridge/pci_target_unit/pcit_if_pciw_fifo_control_out[2:0] on block TOP. +WARNING:NetListWriters:107 - Signal bus + bridge/pci_target_unit/pcit_if_pciw_fifo_control_out[2:0] on block TOP is not + reconstructed. +WARNING:NetListWriters:106 - Wire + bridge/pci_target_unit/fifos_pciw_control_out[1] not found for wire bus + bridge/pci_target_unit/fifos_pciw_control_out[2:0] on block TOP. +WARNING:NetListWriters:107 - Signal bus + bridge/pci_target_unit/fifos_pciw_control_out[2:0] on block TOP is not + reconstructed. +--- Generating ngd2ver output file(s) ... + --- Writing sdf file pci_crt_time_sim.sdf. + --- Writing netlist file pci_crt_time_sim.v. +WARNING:NetListWriters:108 - In order to compile this verilog file + successfully, please add $XILINX/verilog/src/glbl.v to your compile command. +--- ngd2ver is done ! + +================================================== + +xcpy pci_crt_time_sim.v f:\mihad\fpga_t~1\pci_crt\pci_crt_time_sim.v + +================================================== + +xcpy pci_crt_time_sim.sdf f:\mihad\fpga_t~1\pci_crt\pci_crt_time_sim.sdf + +================================================== + +bitgen pci_crt.ncd -l -w -f bitgen.ut +Release 3.3.08i - Bitgen D.27 +Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved. + +Loading design for application Bitgen from file pci_crt.ncd. + "TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5 +Loading device for application Bitgen from file 'v150.nph' in environment +C:/Foundation. +Opened constraints file pci_crt.pcf. + +Tue Jan 15 13:40:02 2002 + +Running DRC. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA0 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA1 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA2 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA3 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA6 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA7 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA8 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA9 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA10 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA11 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA12 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA13 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA14 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA15 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB5 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB6 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB7 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB8 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB9 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB10 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB11 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB12 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB13 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB14 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB15 of comp + bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not + connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB0 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB1 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB2 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB3 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB4 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB5 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB6 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB7 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB8 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB9 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB10 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB11 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB12 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB13 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB14 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB15 of comp + CRT/ssvga_fifo/ramb4_s8_0 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB0 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB1 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB2 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB3 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB4 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB5 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB6 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB7 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB8 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB9 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB10 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB11 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB12 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB13 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB14 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB15 of comp + CRT/ssvga_fifo/ramb4_s8_1 is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB0 of comp + CRT/ssvga_pallete is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB1 of comp + CRT/ssvga_pallete is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB2 of comp + CRT/ssvga_pallete is not connected. +WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB3 of comp + CRT/ssvga_pallete is not connected. +DRC detected 0 errors and 61 warnings. +Saving ll file in "pci_crt.ll". +Creating bit map... +Saving bit stream in "pci_crt.bit". + +================================================== + +xcpy pci_crt.bit f:\mihad\fpga_t~1\pci_crt\pci_crt.bit + +================================================== + +xcpy pci_crt.ll f:\mihad\fpga_t~1\pci_crt\pci_crt.ll

crt/syn/out/bit/fe.log Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: crt/syn/out/bit/pci_crt.bit =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: crt/syn/out/bit/pci_crt.bit =================================================================== --- crt/syn/out/bit/pci_crt.bit (nonexistent) +++ crt/syn/out/bit/pci_crt.bit (revision 154)

crt/syn/out/bit/pci_crt.bit Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: crt/syn/exc/pci_crt.exc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: crt/syn/exc/pci_crt.exc =================================================================== --- crt/syn/exc/pci_crt.exc (nonexistent) +++ crt/syn/exc/pci_crt.exc (revision 154)

crt/syn/exc/pci_crt.exc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sw/driver/fb/spartan_fb.c =================================================================== --- sw/driver/fb/spartan_fb.c (nonexistent) +++ sw/driver/fb/spartan_fb.c (revision 154) @@ -0,0 +1,774 @@ +/* + * framebuffer driver for VBE 2.0 compliant graphic boards + * + * switching to graphics mode happens at boot time (while + * running in real mode, see arch/i386/video.S). + * + * (c) 1998 Gerd Knorr + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include

sw/driver/fb/spartan_fb.o Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sw/driver/slide.c =================================================================== --- sw/driver/slide.c (nonexistent) +++ sw/driver/slide.c (revision 154) @@ -0,0 +1,85 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +int main() +{ + int result ; + int fd ; + int i = 0; + char buff[640*480] ; + int palette[256] ; + int c; + unsigned long value ; + + fd = open("/dev/spartan", O_RDWR) ; + + if (fd < 0) { + printf("Error: Opening device /dev/spartan\n"); + return fd ; + } + + while (i < 54) { + c = getchar(); + if (c == EOF) + error("Early end-of-file."); + if ((i == 0) && (c != 0x42)) + error("Not BMP format."); + if ((i == 1) && (c != 0x4d)) + error("Not BMP format."); + if ((i == 2) && (c != 0x38)) + error("Not 8-bit BMP format."); + if ((i == 10) && (c != 0x36)) + error("Not limited to 64 colors (6 bits)."); + if ((i == 11) && (c != 0x01)) + error("Not limited to 64 colors (6 bits)."); + if ((i == 18) && (c != 0x80)) + error("Not 640 pixels horizontal resolution."); + if ((i == 19) && (c != 0x02)) + error("Not 640 pixels horizontal resolution."); + if ((i == 22) && (c != 0xe0)) + error("Not 480 pixels vertical resolution."); + if ((i == 23) && (c != 0x01)) + error("Not 480 pixels vertical resolution."); + i++; + } + + // activate resource 2 + value = 0x00000002 ; + result = ioctl(fd, SPARTAN_IOC_CURRESSET, value) ; + + /* Set palette */ + lseek(fd, SPARTAN_CRT_PALETTE_BASE, 0); + + while (i < 310) { + if (c == EOF) + error("Early end-of-file."); + + palette[(i - 54)/4] = ((getchar() >> 4) << 12) | ((getchar() >> 4) << 8) | ((getchar() >> 4) << 4); + +printf("%.4x\n", palette[(i - 54)/4]); + getchar(); + i+=4; + } + + while (i < 307510) { + buff[sizeof(buff) - (i - 310)] = (char)getchar(); + i++; + } + + if(write(fd, palette, 0x400) != 0x400) { + printf("Error writing device /dev/spartan\n"); + return -1; + } + + ioctl(fd, SPARTAN_IOC_SET_VIDEO_BUFF, buff) ; + + close(fd); + return 0; +} + Index: sw/driver/spartan_kint.h =================================================================== --- sw/driver/spartan_kint.h (nonexistent) +++ sw/driver/spartan_kint.h (revision 154) @@ -0,0 +1,31 @@ +#include + +#define SPARTAN_IOC_NUM 'S' +#define SPARTAN_IOC_MAX_NUM 10 + +#define SPARTAN_IOC_CURRESGET _IO(SPARTAN_IOC_NUM, 1) // read current resource - (0 = none) +#define SPARTAN_IOC_CURRESSET _IO(SPARTAN_IOC_NUM, 2) // set current resource +#define SPARTAN_IOC_CURBASE _IOR(SPARTAN_IOC_NUM, 3, base) // read current resource base address +#define SPARTAN_IOC_CURBASEMAP _IOR(SPARTAN_IOC_NUM, 4, base) // read current resource remaped base address ( 0 - not remaped) +#define SPARTAN_IOC_CURBASESIZE _IOR(SPARTAN_IOC_NUM, 5, base_size)// read current resource size +#define SPARTAN_IOC_NUMOFRES _IO(SPARTAN_IOC_NUM, 6) // read number of found resources +#define SPARTAN_IOC_VIDEO_BASE _IOR(SPARTAN_IOC_NUM, 7, base) // read video buffer phyisical base address +#define SPARTAN_IOC_VIDEO_VBASE _IOR(SPARTAN_IOC_NUM, 8, base) // read video buffer virtual base address +#define SPARTAN_IOC_VIDEO_SIZE _IOR(SPARTAN_IOC_NUM, 9, base_size) // read video buffer size +#define SPARTAN_IOC_SET_VIDEO_BUFF _IO(SPARTAN_IOC_NUM, 10) + + +#define SPARTAN_P_IMG_CTRL1_ADDR 0x110 +#define SPARTAN_P_BA1_ADDR 0x114 +#define SPARTAN_P_AM1_ADDR 0x118 +#define SPARTAN_P_TA1_ADDR 0x11c + + +#define SPARTAN_W_IMG_CTRL1_ADDR 0x184 +#define SPARTAN_W_BA1_ADDR 0x188 +#define SPARTAN_W_AM1_ADDR 0x18C +#define SPARTAN_W_TA1_ADDR 0x190 + +#define SPARTAN_CRT_CTRL 0x000 +#define SPARTAN_CRT_ADD 0x004 +#define SPARTAN_CRT_PALETTE_BASE 0x400 Index: sw/driver/spartan_drv.c =================================================================== --- sw/driver/spartan_drv.c (nonexistent) +++ sw/driver/spartan_drv.c (revision 154) @@ -0,0 +1,598 @@ + +#define __KERNEL__ +#define MODULE + +#include +#include +#include +#include + +#include +#include //IOCTL definitions + +// define vendor and device ID here - currently this definitions specify reference designs from insight electronic +#ifdef __SDRAM__ +#define OC_PCI_VENDOR 0x1597 +#define OC_PCI_DEVICE 0x0300 +#endif +#ifdef __VGA__ +#define OC_PCI_VENDOR 0x2321 +#define OC_PCI_DEVICE 0x0001 +#endif + +// if someone wants specific major number assigned to spartan board - specify it here +// if 0 is used, kernel assigns it automaticaly +#ifdef __SDRAM__ +#define REQUESTED_MAJOR 243 +#endif + +#ifdef __VGA__ +#define REQUESTED_MAJOR 244 +#endif + +// if compiling module for kernel 2.4 - leave this defined +// for kernel 2.2 - comment this out +#define KERNEL_VER_24 + +#ifndef SEEK_SET + #define SEEK_SET 0 + #define SEEK_CUR 1 + #define SEEK_END 2 +#endif + +// io.h needed just for kernel 2.2 +#ifndef KERNEL_VER_24 + #include +#endif + +// memory mapped or IO mapped region definitions +#define SPARTAN_MEM_MAPPED 0 +#define SPARTAN_IO_MAPPED 1 + +#ifdef __VGA__ +#define VIDEO_SZ (640*480) +#endif + +// structure for holding board information +// (6 base addresses, mapping, page etc. +static struct our_dev +{ + int major ; + u32 bases[6] ; + u8 num_of_bases ; + u32 base_size[6] ; + u32 offset ; + u32 page_addr ; + u32 base_page_offset ; + int current_resource ; + int base_map[6] ; + u32 video_base ; + u32 video_vbase ; + u32 video_size ; + struct pci_dev *ppci_spartan_dev ; +} pspartan_dev ; + +// function prototypes +int spartan_open(struct inode *inode, struct file *filp); + +int spartan_release(struct inode *inode, struct file *filp); + +ssize_t spartan_read(struct file *filp, char *buf, size_t count, loff_t *offset ) ; +ssize_t spartan_write(struct file *filp, const char *buf, size_t count, loff_t *offset) ; +int spartan_ioctl(struct inode *pnode, struct file *filp, unsigned int cmd, unsigned long arg) ; +loff_t spartan_seek(struct file *filp, loff_t offset, int what) ; + +// file operations structure - different for kernels 2.2 and 2.4 +static struct file_operations *pspartan_fops ; +static struct file_operations spartan_fops = { + #ifdef KERNEL_VER_24 + NULL, + #endif + spartan_seek, + spartan_read, + spartan_write, + NULL, + NULL, + spartan_ioctl, + NULL, + spartan_open, + NULL, + spartan_release, +} ; + +int open_mem_mapped(void) ; + +// seek file operation function +loff_t spartan_seek(struct file *filp, loff_t offset, int origin) +{ + loff_t requested_offset ; + int resource_num = pspartan_dev.current_resource ; + + switch (origin) + { + case SEEK_CUR:requested_offset = pspartan_dev.offset + offset ; break ; + case SEEK_END:requested_offset = pspartan_dev.base_size[resource_num] + offset ; break ; + default:requested_offset = offset ; break ; + } + + if ((requested_offset < 0) || (requested_offset > pspartan_dev.base_size[resource_num])) + return -EFAULT ; + + pspartan_dev.offset = requested_offset ; + + return requested_offset ; +} + +// ioctl for device +// currently just a few operations are supported here - defined in spartan_kint.h header +int spartan_ioctl(struct inode *pnode, struct file *filp, unsigned int cmd, unsigned long arg) +{ + int error = 0; + int size = _IOC_SIZE(cmd) ; + unsigned long base ; + unsigned long base_size ; + int i; + + if (_IOC_TYPE(cmd) != SPARTAN_IOC_NUM) return -EINVAL ; + if (_IOC_NR(cmd) > SPARTAN_IOC_MAX_NUM) return -EINVAL ; + + // Writes through pointers not allowed - writes only through argument + if (_IOC_DIR(cmd) & _IOC_WRITE) return -EINVAL ; + else if (_IOC_DIR(cmd) & _IOC_READ) + error = verify_area(VERIFY_WRITE, (void *) arg, size) ; + + if (error) + return error ; + + switch (cmd){ + case SPARTAN_IOC_CURRESGET: + // current resource - they start at 1 + return (pspartan_dev.current_resource + 1) ; + case SPARTAN_IOC_CURRESSET: + // check if resource is in a range of implemented resources + if (arg < 0 ) + return -EINVAL ; + + // unmap previous resource if it was mapped + if (pspartan_dev.current_resource >= 0) + { + iounmap((void *)pspartan_dev.page_addr) ; + } + + if (arg == 0) + { + // previous resource unmaped - that's all + pspartan_dev.current_resource = -1 ; + return 0 ; + } + + if (pspartan_dev.num_of_bases < arg) + return -ENODEV ; + + // IO mapped not supported yet + if (pspartan_dev.base_map[arg] == SPARTAN_IO_MAPPED) + { + // set current resource to none, since it was unmapped + pspartan_dev.current_resource = -1 ; + return -ENODEV ; + } + pspartan_dev.current_resource= (int)(arg-1) ; + // remap new resource + if ( (error = open_mem_mapped()) ) + { + pspartan_dev.current_resource = -1 ; + return error ; + } + return 0 ; + case SPARTAN_IOC_CURBASE: + // check if any resource is currently activated + if (pspartan_dev.current_resource>=0) + base = pspartan_dev.bases[pspartan_dev.current_resource] ; + else + base = 0x00000000 ; + + *(unsigned long *)arg = base ; + return 0 ; + case SPARTAN_IOC_CURBASEMAP: + // check if any resource is currently activated + if (pspartan_dev.current_resource>=0) + base = pspartan_dev.page_addr ; + else + base = 0x00000000 ; + + *(unsigned long *)arg = base ; + + return 0 ; + case SPARTAN_IOC_CURBASESIZE: + // check if any resource is currently activated + if (pspartan_dev.current_resource>=0) + base_size = pspartan_dev.base_size[pspartan_dev.current_resource] ; + else + base_size = 0x00000000 ; + + *(unsigned long *)arg = base_size ; + return 0 ; + case SPARTAN_IOC_NUMOFRES: + return (pspartan_dev.num_of_bases) ; +#ifdef __VGA__ + case SPARTAN_IOC_VIDEO_BASE: + *((unsigned long *)arg) = pspartan_dev.video_base; + put_user(pspartan_dev.video_base, ((unsigned long *)arg)); + return 0 ; + + case SPARTAN_IOC_VIDEO_VBASE: + *(unsigned long *)arg = pspartan_dev.video_vbase; + put_user(pspartan_dev.video_vbase, ((unsigned long *)arg)); + return 0 ; + + case SPARTAN_IOC_VIDEO_SIZE: + *(unsigned long *)arg = pspartan_dev.video_size; + put_user(pspartan_dev.video_size, ((unsigned long *)arg)); + return 0; + + case SPARTAN_IOC_SET_VIDEO_BUFF: + for(i = 0; i < VIDEO_SZ; i++) { + get_user(*((char *)(pspartan_dev.video_vbase + i)), ((char *)(arg + i))); + } + + return 0; +#endif + default: + return -EINVAL ; + } +} + +// helper function for memory remaping +int open_mem_mapped(void) +{ + int resource_num = pspartan_dev.current_resource ; + unsigned long num_of_pages = 0 ; + unsigned long base = pspartan_dev.bases[resource_num] ; + unsigned long size = pspartan_dev.base_size[resource_num] ; + + if (!(num_of_pages = (unsigned long)(size/PAGE_SIZE))) ; + num_of_pages++ ; + + pspartan_dev.base_page_offset = base & ~PAGE_MASK ; + + if ((pspartan_dev.base_page_offset + size) < (num_of_pages*PAGE_SIZE)) + num_of_pages++ ; + + // remap memory mapped space + pspartan_dev.page_addr = (unsigned long)ioremap(base & PAGE_MASK, num_of_pages * PAGE_SIZE) ; + + if (pspartan_dev.page_addr == 0x00000000) + return -ENOMEM ; + + return 0 ; +} + +// add io mapped resource handler here +int open_io_mapped( void ) +{ + return 0 ; +} + +// open file operation function +int spartan_open(struct inode *inode, struct file *filp) +{ + if (MOD_IN_USE) + return -EBUSY ; + + pspartan_fops = &spartan_fops ; + filp->f_op = pspartan_fops ; + pspartan_dev.offset = 0 ; + pspartan_dev.current_resource = -1 ; + MOD_INC_USE_COUNT ; + return 0 ; +} + +// release - called by close on file descriptor +int spartan_release(struct inode *inode, struct file *filp) +{ + // unmap any remaped pages + if (pspartan_dev.current_resource >= 0) + iounmap((void *)pspartan_dev.page_addr) ; + + pspartan_dev.current_resource = -1 ; + + MOD_DEC_USE_COUNT ; + return 0 ; +} + +// memory mapped resource read function +ssize_t spartan_read(struct file *filp, char *buf, size_t count, loff_t *offset_out ) +{ + + unsigned long current_address = pspartan_dev.page_addr + pspartan_dev.base_page_offset + pspartan_dev.offset ; + unsigned long actual_count ; + unsigned long offset = pspartan_dev.offset ; + int resource_num = pspartan_dev.current_resource ; + int i; + int value; + + unsigned long size = pspartan_dev.base_size[resource_num] ; + int result ; + + if (pspartan_dev.current_resource < 0) + return -ENODEV ; + + if (offset == size) + return 0 ; + + if ( (offset + count) > size ) + actual_count = size - offset ; + else + actual_count = count ; + + // verify range if it is OK to copy from + if ((result = verify_area(VERIFY_WRITE, buf, actual_count))) + return result ; + + i = actual_count/4; + while(i--) { + + value = readl(current_address); + put_user(value, ((int *)buf)); + buf += 4; + current_address += 4; + } + + pspartan_dev.offset = pspartan_dev.offset + actual_count ; + + *(offset_out) = pspartan_dev.offset ; + + return actual_count ; + } + +// memory mapped resource write function +ssize_t spartan_write(struct file *filp, const char *buf, size_t count, loff_t *offset_out) +{ + unsigned long current_address = pspartan_dev.page_addr + pspartan_dev.base_page_offset + pspartan_dev.offset ; + unsigned long actual_count ; + unsigned long offset = pspartan_dev.offset ; + int resource_num = pspartan_dev.current_resource ; + int i; + int value; + unsigned long size = pspartan_dev.base_size[resource_num] ; + int result ; + + if (pspartan_dev.current_resource < 0) + return -ENODEV ; + + if (offset == size) + return 0 ; + + if ( (offset + count) > size ) + actual_count = size - offset ; + else + actual_count = count ; + + // verify range if it is OK to copy from + if ((result = verify_area(VERIFY_READ, buf, actual_count))) + return result ; + + i = actual_count/4; + while(i--) { + get_user(value, ((int *)buf)); + writel(value, current_address); + buf += 4; + current_address += 4; + } + pspartan_dev.offset = pspartan_dev.offset + actual_count ; + + *(offset_out) = pspartan_dev.offset ; + + return actual_count ; +} + +// initialization function - different for 2.2 and 2.4 kernel because of different pci_dev structure +int init_module(void) +{ + int result ; + u32 base_address ; + unsigned long size ; + unsigned short num_of_bases ; + u16 wvalue ; + struct pci_dev *ppci_spartan_dev = NULL ; + struct resource spartan_resource ; + struct page *page; + int sz ; + + if(!pci_present()) + { + printk("<1> Kernel reports no PCI bus support!\n " ); + return -ENODEV; + } + + if((ppci_spartan_dev = pci_find_device(OC_PCI_VENDOR, OC_PCI_DEVICE, ppci_spartan_dev))==NULL ) + { + printk("<1> Device not found!\n " ); + return -ENODEV ; + } + + pspartan_dev.ppci_spartan_dev = ppci_spartan_dev ; + +#ifdef KERNEL_VER_24 + //printk("<1> Board found at address 0x%08X\n", ppci_spartan_dev->resource[0].start) ; + // copy implemented base addresses to private structure + + spartan_resource = ppci_spartan_dev->resource[0] ; + base_address = spartan_resource.start ; + printk("<1> First base address register found at %08X \n ", base_address ); + num_of_bases = 0 ; + while ((base_address != 0x00000000) && (num_of_bases < 6)) + { + pspartan_dev.bases[num_of_bases] = spartan_resource.start ; + pspartan_dev.base_size[num_of_bases] = spartan_resource.end - spartan_resource.start + 1 ; + // check if resource is IO mapped + if (spartan_resource.flags & IORESOURCE_IO) + pspartan_dev.base_map[num_of_bases] = SPARTAN_IO_MAPPED ; + else + pspartan_dev.base_map[num_of_bases] = SPARTAN_MEM_MAPPED ; + + num_of_bases++ ; + spartan_resource = ppci_spartan_dev->resource[num_of_bases] ; + base_address = spartan_resource.start ; + } + + result = pci_read_config_word(ppci_spartan_dev, PCI_COMMAND, &wvalue) ; + if (result < 0) + { + printk("<1> Read from command register failed! \n " ); + return result ; + } + + result = pci_write_config_word(ppci_spartan_dev, PCI_COMMAND, wvalue | PCI_COMMAND_MEMORY | PCI_COMMAND_IO) ; + + if (result < 0) + { + printk("<1>Write to command register failed! \n " ); + return result ; + } + +#else + + printk("<1> Board found at address 0x%08X\n", ppci_spartan_dev->base_address[0]); + + // now go through base addresses of development board + // and see what size they are - first disable devices response + result = pci_read_config_word(ppci_spartan_dev, PCI_COMMAND, &wvalue) ; + if (result < 0) + { + printk("<1> Read from command register failed! \n " ); + return result ; + } + + // write masked config value back to command register to + // disable devices response! mask value + result = pci_write_config_word(ppci_spartan_dev, PCI_COMMAND, wvalue & ~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY) ; + + if (result < 0) + { + printk("<1>Write to command register failed! \n " ); + return result ; + } + + // write to base address registers and read back until all 0s are read + base_address = ppci_spartan_dev->base_address[0] ; + num_of_bases = 0 ; + while ((base_address != 0x00000000) && (num_of_bases < 6)) + { + // copy non-zero base address to private structure + pspartan_dev.bases[num_of_bases] = ppci_spartan_dev->base_address[num_of_bases] ; + + // write to current register + result = pci_write_config_dword(ppci_spartan_dev, PCI_BASE_ADDRESS_0 + (num_of_bases * 4), 0xFFFFFFFF) ; + + if (result < 0) + { + printk("<1>Write to BAR%d failed! \n ", num_of_bases); + return result ; + } + + result = pci_read_config_dword(ppci_spartan_dev, PCI_BASE_ADDRESS_0 + (num_of_bases * 4), &base_address) ; + if (result < 0) + { + printk("<1>Read from BAR%d failed! \n ", num_of_bases); + return result ; + } + + // calculate size of this base address register's range + size = 0xFFFFFFFF - base_address ; + + // store size in structure + pspartan_dev.base_size[num_of_bases] = size + 1; + + // set base address back to original value + base_address = pspartan_dev.bases[num_of_bases] ; + + // now write original base address back to this register + result = pci_write_config_dword(ppci_spartan_dev, PCI_BASE_ADDRESS_0 + (num_of_bases * 4), base_address) ; + + if (result < 0) + { + printk("<1>Write to BAR%d failed! \n ", num_of_bases); + return result ; + } + num_of_bases++ ; + // read new base address + base_address = ppci_spartan_dev->base_address[num_of_bases] ; + + } + // write original value back to command register! + result = pci_write_config_word(ppci_spartan_dev, PCI_COMMAND, wvalue) ; + + if (result < 0) + { + printk("<1>Write to command register failed! \n " ); + return result ; + } +#endif + if (num_of_bases < 1) + printk("<1>No implemented base address registers found! \n ") ; + + pspartan_dev.current_resource = - 1 ; + + // store number of bases in structure + pspartan_dev.num_of_bases = num_of_bases ; + + // display information about all base addresses found in this procedure + for (num_of_bases = 0; num_of_bases < pspartan_dev.num_of_bases; num_of_bases++) + { + printk("<1>BAR%d range from %08X to %08X \n ", num_of_bases, pspartan_dev.bases[num_of_bases], pspartan_dev.bases[num_of_bases] + pspartan_dev.base_size[num_of_bases]); + } +#ifdef __VGA__ + for (sz = 0, size = PAGE_SIZE; size < VIDEO_SZ; sz++, size <<= 1); + pspartan_dev.video_vbase = __get_free_pages(GFP_KERNEL, sz); + + if (pspartan_dev.video_vbase == 0) { + printk(KERN_ERR "spartan: abort, cannot allocate video memory\n"); + return -EIO; + } + + pspartan_dev.video_size = PAGE_SIZE * (1 << sz); + pspartan_dev.video_base = virt_to_bus(pspartan_dev.video_vbase); + + for (page = virt_to_page(pspartan_dev.video_vbase); page <= virt_to_page(pspartan_dev.video_vbase + pspartan_dev.video_size - 1); page++) + mem_map_reserve(page); + + printk(KERN_INFO "spartan: framebuffer at 0x%lx (phy 0x%lx), mapped to 0x%p, size %dk\n", + pspartan_dev.video_base, virt_to_phys(pspartan_dev.video_vbase), pspartan_dev.video_vbase, pspartan_dev.video_size/1024); +#endif + + result = register_chrdev(REQUESTED_MAJOR, "spartan", &spartan_fops) ; + if (result < 0) + { + printk(KERN_WARNING "spartan: can't get major number %d\n",REQUESTED_MAJOR) ; + return result ; + } + + printk("<1> Major number for spartan is %d \n", result ); + pspartan_dev.major = result ; + + return 0 ; +} + +// celanup - unregister device +void cleanup_module(void) +{ + int result ; + int size, sz; + +#ifdef __VGA__ + for (sz = 0, size = PAGE_SIZE; size < VIDEO_SZ; sz++, size <<= 1); + free_pages(pspartan_dev.video_vbase, sz); +#endif + result = unregister_chrdev(pspartan_dev.major, "spartan") ; + if (result < 0) + { + printk("<1> spartan device with major number %d unregistration failed \n", pspartan_dev.major); + return ; + } + else + { + printk("<1> spartan device with major number %d unregistered succesfully \n", pspartan_dev.major); + return ; + } +} Index: sw/driver/sdram_test.c =================================================================== --- sw/driver/sdram_test.c (nonexistent) +++ sw/driver/sdram_test.c (revision 154) @@ -0,0 +1,120 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +int main() +{ + int result ; + int fd ; + unsigned long *buf ; + unsigned long value ; + unsigned long base ; + unsigned long base_size ; + + fd = open("/dev/spartan", O_RDWR) ; + + if (fd < 0) + return fd ; + + buf = (void *)malloc(4) ; + + if (buf == NULL) + return -1 ; + + // probe driver + result = ioctl(fd, SPARTAN_IOC_CURRESGET) ; + + if (result > 0) + printf("Driver reports enabled resource although it was not enabled through ioctl yet\n!") ; + + result = ioctl(fd, SPARTAN_IOC_NUMOFRES) ; + if (result != 2) + printf("SDRAM reference design implements 2 BARs, driver reported %d!\n", result) ; + + result = ioctl(fd, SPARTAN_IOC_CURBASE, &base) ; + if (base) + printf("Driver reports base address resource selected although it was not yet initialized!\n") ; + + result = ioctl(fd, SPARTAN_IOC_CURBASEMAP, &base) ; + + if (base) + printf("Driver reports base address remaped although it was not yet initialized!\n") ; + + result = ioctl(fd, SPARTAN_IOC_CURBASESIZE, &base_size) ; + if (base_size) + printf("Driver reports base address range non-zero although it was not yet initialized!\n") ; + + // activate resource 1 + value = 0x00000001 ; + result = ioctl(fd, SPARTAN_IOC_CURRESSET, value) ; + + if (result) + printf("Driver reported failure to intialize resource 1 !\n") ; + + // activate resource 2 + value = 0x00000002 ; + result = ioctl(fd, SPARTAN_IOC_CURRESSET, value) ; + + if (result) + printf("Driver reported failure to intialize resource 2!\n") ; + + // check if ioctl returns any meaningful values! + result = ioctl(fd, SPARTAN_IOC_CURRESGET) ; + + if (result != 2) + printf("Resource 2 was enabled, driver reports resurce %d active!\n", result) ; + + result = ioctl(fd, SPARTAN_IOC_CURBASE, &base) ; + if (!base) + printf("Driver should report non-zero base address when resource is selected!\n") ; + else + printf("Driver reports SDRAM at address %X\n", base) ; + + result = ioctl(fd, SPARTAN_IOC_CURBASEMAP, &base) ; + + if (!base) + printf("Driver reports zero page base address although resource 2 is supposed to be enabled!\n") ; + else + printf("Driver reports SDRAM at remaped address %X\n", base) ; + + result = ioctl(fd, SPARTAN_IOC_CURBASESIZE, &base_size) ; + if (!base_size) + printf("Driver reports zero base address range although resource is supposed to be enabled\n") ; + else + printf("Driver reports SDRAM size %li\n", base_size) ; + + value = 0x00000001 ; + *(buf) = value ; + while ((result = write(fd, buf, 4)) > 0) + { + value = value + 1 ; + *(buf) = value ; + } + + printf("%li writes succesfull!\n", value-1) ; + + // go back to start of image + value = lseek(fd, 0, 0) ; + if (result != 0) + { + printf("Seek didn't reset offset to 0i\n") ; + return -1 ; + } + value = 0x00000001 ; + while ((result = read(fd, buf, 4)) > 0) + { + if (value != *buf) + printf("Expected value was %X, actually read value was %X\n", value, *buf) ; + + value = value + 1 ; + } + + printf("%li reads done!\n", value-1) ; + close(fd) ; + return result ; +} Index: sw/driver/README.txt =================================================================== --- sw/driver/README.txt (nonexistent) +++ sw/driver/README.txt (revision 154) @@ -0,0 +1,20 @@ +Files provided in this directory are intended for +PCI development purposes. Kernel interface provides +some basic functionality for accessing PCI memory mapped +resources on single device. Modules have been tested +on Linux kernels 2.2 and 2.4, inserted with modutils version 2.4.6-1 for i386 +IO resources as well as interrupts or DMA (mastership) +are not supported by this interface yet - they will probably be when +PCI bridge development is finished. +sdram_test.c source and binary is a little program that tests driver response +with Insight's Spartan-II PCI development kit with SDRAM reference design +loaded. + +I have compiled modules with +gcc -D__KERNEL__ -DMODULE -c -O and it worked fine - if it doesn't for you, don't ask me why, because I'm not Linux guru + +I have inserted modules with +insmod -f spartan_drv-2.*.o and it also worked, nonetheless insmod was complaining about versions + +Have fun, + Miha Dolenc \ No newline at end of file Index: sw/driver/Makefile =================================================================== --- sw/driver/Makefile (nonexistent) +++ sw/driver/Makefile (revision 154) @@ -0,0 +1,6 @@ +spartan_fb.o: spartan_drv.c + gcc -D__KERNEL__ -DMODULE -D__VGA__ -I. -c -O2 -o spspartan_fb.o spartan_drv.c + +slide: slide.c + gcc -O2 -I. -o slide slide.c + Index: sw/driver/sdram_test =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: sw/driver/sdram_test =================================================================== --- sw/driver/sdram_test (nonexistent) +++ sw/driver/sdram_test (revision 154)

sw/driver/sdram_test Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: README.txt =================================================================== --- README.txt (nonexistent) +++ README.txt (revision 154) @@ -0,0 +1,2 @@ +This directory contains actual applications provided for testing or developing pci bridge core. +- crt - a simple crt controller which uses master interface to fetch pixel data from system memory \ No newline at end of file