Subversion Repositories pci

/run/run_pci_sim_regr.scr File deleted

run/run_pci_sim_regr.scr Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: run/clean =================================================================== --- run/clean (revision 154) +++ run/clean (nonexistent) @@ -1,61 +0,0 @@ -#!/bin/csh -f - -if ($#argv < 1) then - echo "Missing required argument: all | log | wave | nc_out" - exit -endif - -set cur_arg = 1 -set arg_chk = 0 - -set log = 0 -set wave = 0 -set nc_out = 0 - -while ($cur_arg <= $#argv) - if ($argv[$cur_arg] == "all") then - set log = 1 - set wave = 1 - set nc_out = 1 - - @ arg_chk = $arg_chk + 1 - endif - - if ($argv[$cur_arg] == "log") then - set log = 1 - - @ arg_chk = $arg_chk + 1 - endif - - if ($argv[$cur_arg] == "wave") then - set wave = 1 - - @ arg_chk = $arg_chk + 1 - endif - - if ($argv[$cur_arg] == "nc_out") then - set nc_out = 1 - - @ arg_chk = $arg_chk + 1 - endif - - if ($arg_chk != $cur_arg) then - echo "Invalid argument $argv[$cur_arg]" - exit - endif - - @ cur_arg = $cur_arg + 1 -end - -if ($nc_out) then - rm ../bin/INCA_libs/worklib/* - rm ../bin/INCA_libs/worklib/.* -endif - -if ($log) then - rm ../log/*.log -endif - -if ($wave) then - rm -rf ../out/*.shm -endif

run/clean Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: run/top_groups.do =================================================================== --- run/top_groups.do (revision 154) +++ run/top_groups.do (nonexistent) @@ -1,218 +0,0 @@ -// Signalscan Version 6.7p1 - - -define noactivityindicator -define analog waveform lines -define add variable default overlay off -define waveform window analogheight 1 -define terminal automatic -define buttons control \ - 1 opensimmulationfile \ - 2 executedofile \ - 3 designbrowser \ - 4 waveform \ - 5 source \ - 6 breakpoints \ - 7 definesourcessearchpath \ - 8 exit \ - 9 createbreakpoint \ - 10 creategroup \ - 11 createmarker \ - 12 closesimmulationfile \ - 13 renamesimmulationfile \ - 14 replacesimulationfiledata \ - 15 listopensimmulationfiles \ - 16 savedofile -define buttons waveform \ - 1 undo \ - 2 cut \ - 3 copy \ - 4 paste \ - 5 delete \ - 6 zoomin \ - 7 zoomout \ - 8 zoomoutfull \ - 9 expand \ - 10 createmarker \ - 11 designbrowser:1 \ - 12 variableradixbinary \ - 13 variableradixoctal \ - 14 variableradixdecimal \ - 15 variableradixhexadecimal \ - 16 variableradixascii -define buttons designbrowser \ - 1 undo \ - 2 cut \ - 3 copy \ - 4 paste \ - 5 delete \ - 6 cdupscope \ - 7 getallvariables \ - 8 getdeepallvariables \ - 9 addvariables \ - 10 addvarsandclosewindow \ - 11 closewindow \ - 12 scopefiltermodule \ - 13 scopefiltertask \ - 14 scopefilterfunction \ - 15 scopefilterblock \ - 16 scopefilterprimitive -define buttons event \ - 1 undo \ - 2 cut \ - 3 copy \ - 4 paste \ - 5 delete \ - 6 move \ - 7 closewindow \ - 8 duplicate \ - 9 defineasrisingedge \ - 10 defineasfallingedge \ - 11 defineasanyedge \ - 12 variableradixbinary \ - 13 variableradixoctal \ - 14 variableradixdecimal \ - 15 variableradixhexadecimal \ - 16 variableradixascii -define buttons source \ - 1 undo \ - 2 cut \ - 3 copy \ - 4 paste \ - 5 delete \ - 6 createbreakpoint \ - 7 creategroup \ - 8 createmarker \ - 9 createevent \ - 10 createregisterpage \ - 11 closewindow \ - 12 opensimmulationfile \ - 13 closesimmulationfile \ - 14 renamesimmulationfile \ - 15 replacesimulationfiledata \ - 16 listopensimmulationfiles -define buttons register \ - 1 undo \ - 2 cut \ - 3 copy \ - 4 paste \ - 5 delete \ - 6 createregisterpage \ - 7 closewindow \ - 8 continuefor \ - 9 continueuntil \ - 10 continueforever \ - 11 stop \ - 12 previous \ - 13 next \ - 14 variableradixbinary \ - 15 variableradixhexadecimal \ - 16 variableradixascii -define show related transactions -define exit prompt -define event search direction forward -define variable nofullhierarchy -define variable nofilenames -define variable nofullpathfilenames -include bookmark with filenames -include scope history without filenames -define waveform window listpane 5.78 -define waveform window namepane 13.93 -define multivalueindication -define pattern curpos dot -define pattern cursor1 dot -define pattern cursor2 dot -define pattern marker dot -define print designer "Miha Dolenc" -define print border -define print color blackonwhite -define print command "/usr/ucb/lpr -P%P" -define print printer lp -define print range visible -define print variable visible -define rise fall time low threshold percentage 10 -define rise fall time high threshold percentage 90 -define rise fall time low value 0 -define rise fall time high value 3.3 -define sendmail command "/usr/lib/sendmail" -define sequence time width 30.00 -define snap - -define source noprompt -define time units default -define userdefinedbussymbol -define user guide directory "/usr/local/designacc/signalscan-6.7p1/doc/html" -define waveform window grid off -define waveform window waveheight 14 -define waveform window wavespace 6 -define web browser command netscape -define zoom outfull on initial add off -add group \ - A \ - -add group \ - "PCI signals" \ - SYSTEM.pci_clock \ - SYSTEM.MAS0_REQ \ - SYSTEM.MAS0_GNT \ - SYSTEM.MAS1_REQ \ - SYSTEM.MAS1_GNT \ - SYSTEM.MAS2_REQ \ - SYSTEM.MAS2_GNT \ - SYSTEM.FRAME \ - SYSTEM.IRDY \ - SYSTEM.DEVSEL \ - SYSTEM.TRDY \ - SYSTEM.STOP \ - SYSTEM.AD[31:0]'h \ - SYSTEM.CBE[3:0]'h \ - SYSTEM.PAR \ - SYSTEM.INTA \ - SYSTEM.PERR \ - SYSTEM.SERR \ - -add group \ - "WISHBONE slave signals" \ - SYSTEM.wb_clock \ - SYSTEM.CYC_I \ - SYSTEM.STB_I \ - SYSTEM.CAB_I \ - SYSTEM.WE_I \ - SYSTEM.ACK_O \ - SYSTEM.RTY_O \ - SYSTEM.ERR_O \ - SYSTEM.ADR_I[31:0]'h \ - SYSTEM.SDAT_I[31:0]'h \ - SYSTEM.SDAT_O[31:0]'h \ - SYSTEM.SEL_I[3:0]'h \ - SYSTEM.INT_O \ - -add group \ - "WISHBONE master signals" \ - SYSTEM.wb_clock \ - SYSTEM.CYC_O \ - SYSTEM.STB_O \ - SYSTEM.CAB_O \ - SYSTEM.WE_O \ - SYSTEM.ACK_I \ - SYSTEM.RTY_I \ - SYSTEM.ERR_I \ - SYSTEM.ADR_O[31:0]'h \ - SYSTEM.MDAT_I[31:0]'h \ - SYSTEM.MDAT_O[31:0]'h \ - SYSTEM.SEL_O[3:0]'h \ - SYSTEM.INT_I \ - -add group \ - "Clocks, resets" \ - SYSTEM.wb_clock \ - SYSTEM.pci_clock \ - SYSTEM.RST \ - SYSTEM.RST_O \ - SYSTEM.RTY_I \ - SYSTEM.test_name[799:0]'a \ - - -deselect all -open window waveform 1 geometry 10 59 1368 926 -zoom at 815149.757(0)ns 0.00214844 0.00000000

run/top_groups.do Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: run/ncsim.key =================================================================== --- run/ncsim.key (revision 154) +++ run/ncsim.key (nonexistent) @@ -1,2 +0,0 @@ -run -exit

run/ncsim.key Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: run/ncvlog.args =================================================================== --- run/ncvlog.args (revision 154) +++ run/ncvlog.args (nonexistent) @@ -1,75 +0,0 @@ --cdslib ../bin/cds.lib --hdlvar ../bin/hdl.var --logfile ../log/ncvlog.log --update --messages --INCDIR ../../../bench/verilog --INCDIR ../../../rtl/verilog -../../../rtl/verilog/pci_parity_check.v -../../../rtl/verilog/pci_target_unit.v -../../../rtl/verilog/wb_addr_mux.v -../../../rtl/verilog/cbe_en_crit.v -../../../rtl/verilog/fifo_control.v -../../../rtl/verilog/out_reg.v -../../../rtl/verilog/pci_tpram.v -../../../rtl/verilog/wb_master.v -../../../rtl/verilog/conf_cyc_addr_dec.v -../../../rtl/verilog/frame_crit.v -../../../rtl/verilog/pci_target32_clk_en.v -../../../rtl/verilog/pciw_fifo_control.v -../../../rtl/verilog/wb_slave.v -../../../rtl/verilog/conf_space.v -../../../rtl/verilog/frame_en_crit.v -../../../rtl/verilog/par_crit.v -../../../rtl/verilog/pciw_pcir_fifos.v -../../../rtl/verilog/wb_slave_unit.v -../../../rtl/verilog/frame_load_crit.v -../../../rtl/verilog/pci_bridge32.v -../../../rtl/verilog/pci_target32_devs_crit.v -../../../rtl/verilog/perr_crit.v -../../../rtl/verilog/wbr_fifo_control.v -../../../rtl/verilog/cur_out_reg.v -../../../rtl/verilog/pci_decoder.v -../../../rtl/verilog/pci_target32_interface.v -../../../rtl/verilog/perr_en_crit.v -../../../rtl/verilog/wbw_fifo_control.v -../../../rtl/verilog/decoder.v -../../../rtl/verilog/pci_in_reg.v -../../../rtl/verilog/serr_crit.v -../../../rtl/verilog/wbw_wbr_fifos.v -../../../rtl/verilog/delayed_sync.v -../../../rtl/verilog/irdy_out_crit.v -../../../rtl/verilog/pci_io_mux.v -../../../rtl/verilog/pci_io_mux_ad_en_crit.v -../../../rtl/verilog/pci_io_mux_ad_load_crit.v -../../../rtl/verilog/pci_target32_sm.v -../../../rtl/verilog/serr_en_crit.v -../../../rtl/verilog/delayed_write_reg.v -../../../rtl/verilog/mas_ad_en_crit.v -../../../rtl/verilog/mas_ad_load_crit.v -../../../rtl/verilog/pci_master32_sm.v -../../../rtl/verilog/pci_target32_stop_crit.v -../../../rtl/verilog/synchronizer_flop.v -../../../rtl/verilog/async_reset_flop.v -../../../rtl/verilog/mas_ch_state_crit.v -../../../rtl/verilog/pci_master32_sm_if.v -../../../rtl/verilog/pci_target32_trdy_crit.v -../../../rtl/verilog/top.v -../../../rtl/verilog/pci_rst_int.v -../../../rtl/verilog/sync_module.v -../../../rtl/verilog/wb_tpram.v -../../../bench/verilog/wb_master32.v -../../../bench/verilog/wb_master_behavioral.v -../../../bench/verilog/system.v -../../../bench/verilog/pci_blue_arbiter.v -../../../bench/verilog/pci_bus_monitor.v -../../../bench/verilog/pci_behaviorial_device.v -../../../bench/verilog/pci_behaviorial_master.v -../../../bench/verilog/pci_behaviorial_target.v -../../../bench/verilog/wb_slave_behavioral.v -../../../bench/verilog/wb_bus_mon.v -../../../bench/verilog/pci_behavioral_iack_target.v -../../../bench/verilog/pci_unsupported_commands_master.v -../../../../../../lib/xilinx/lib/glbl/glbl.v -../../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v -../../../../../../lib/xilinx/lib/unisims/RAM16X1D.v

run/ncvlog.args Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: run/ncsim.args =================================================================== --- run/ncsim.args (revision 154) +++ run/ncsim.args (nonexistent) @@ -1,6 +0,0 @@ --cdslib ../bin/cds.lib --hdlvar ../bin/hdl.var --logfile ../log/ncsim.log --messages --input ../bin/ncsim_waves.rc -worklib.bridge32:fun

run/ncsim.args Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: run/ncelab.args =================================================================== --- run/ncelab.args (revision 154) +++ run/ncelab.args (nonexistent) @@ -1,42 +0,0 @@ -// -// ncelab.args: Arguments passed to the NC-Verilog elaborator. -// Created by ncprep on Tue Jan 29 18:18:34 2002 - -// Turn on informative messages. --MESSAGES -// -NOCOPYRIGHT - -// Uncomment the following line to generate a named log file -// -LOGFILE ncelab.log - -// Top level module(s) -CBE_EN_CRIT -PCI_TPRAM -CONF_CYC_ADDR_DEC -FRAME_CRIT -PCI_TARGET32_CLK_EN -FRAME_EN_CRIT -PAR_CRIT -FRAME_LOAD_CRIT -PCI_TARGET32_DEVS_CRIT -PERR_CRIT -PCI_DECODER -PERR_EN_CRIT -DECODER -SERR_CRIT -IRDY_OUT_CRIT -PCI_IO_MUX -PCI_IO_MUX_AD_EN_CRIT -PCI_IO_MUX_AD_LOAD_CRIT -SERR_EN_CRIT -MAS_AD_EN_CRIT -MAS_AD_LOAD_CRIT -PCI_TARGET32_STOP_CRIT -synchronizer_flop -MAS_CH_STATE_CRIT -PCI_TARGET32_TRDY_CRIT -TOP -PCI_RST_INT -SYNC_MODULE -WB_TPRAM -

run/ncelab.args Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: run/regression_example =================================================================== --- run/regression_example (revision 154) +++ run/regression_example (nonexistent) @@ -1,173 +0,0 @@ -#!/bin/csh -f - -set iter = 1; -set failed = 0; -set all_tests = 0; -# List all test cases -set simpletests=(buserr-nocache immu-nocache dmmu-nocache basic-nocache mul-nocache-O2 syscall-nocache cbasic-nocache-O2 ints1-nocache ints2-nocache \ - buserr-icdc immu-icdc dmmu-icdc basic-icdc mul-icdc-O2 syscall-icdc cbasic-icdc-O2 ints1-icdc ints2-icdc) -set complextests=(buserr-ic immu-ic dmmu-ic basic-ic mul-ic-O2 syscall-ic cbasic-ic-O2 ints1-ic ints2-ic \ - buserr-dc immu-dc dmmu-dc basic-dc mul-dc-O2 syscall-dc cbasic-dc-O2 ints1-dc ints2-dc \ - mul-nocache-O0 cbasic-nocache-O0 \ - mul-icdc-O0 cbasic-icdc-O0 \ - mul-ic-O0 cbasic-ic-O0 \ - mul-dc-O0 cbasic-dc-O0) -set simpletimes=(10 10 10 40 40 40 40 40 60 \ - 10 10 10 40 40 40 40 40 40) -set complextimes=(10 10 10 40 40 40 40 40 40 \ - 10 10 10 40 40 40 40 40 100 \ - 40 40 \ - 40 40 \ - 40 40 \ - 40 40) -set iterations=( \ - "OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC" \ - "OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+OR1200_REGISTERED_INPUTS" \ - "OR1200_REGISTERED_OUTPUTS+OR1200_REGISTERED_INPUTS" \ - "OR1200_REGISTERED_OUTPUTS+OR1200_REGISTERED_INPUTS+OR1200_CLMODE_1TO2" \ - "OR1200_REGISTERED_OUTPUTS+OR1200_CLMODE_1TO2" \ - "OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+OR1200_CLMODE_1TO2" \ - "OR1200_REGISTERED_OUTPUTS" \ - "" \ - "OR1200_REGISTERED_OUTPUTS+OR1200_REGISTERED_INPUTS+FLASH_GENERIC_REGISTERED" \ - "") - -# Process arguments -if ($1 == "simple") then - set tests=(${simpletests}) - set maxtimes=(${simpletimes}) -else - set tests=(${simpletests} ${complextests}) - set maxtimes=(${simpletimes} ${complextimes}) -endif -if ($1 == "single") then - set tests=(${simpletests} ${complextests}) - set maxtimes=(${simpletimes} ${complextimes}) - set tests=${tests[$2]} - set maxtimes=${maxtimes[$2]} -endif -if ($1 == "clean") then - rm -rf ../log/* - rm -rf ../out/wave/* - exit 0; -else if ($1 == "sim") then - goto sim; -endif - -# List all selected tests -set i = 0; -foreach test ($tests) - @ i += 1; - echo -n " Test ${i}: ${test}, $maxtimes[$i] ms\t" - if ((${i} % 2) == 0) then - echo "" - endif -end - -echo "" - -set i = 1; -while ($iterations[$i] != "") - echo " Iteration ${i}: ${iterations[$i]}\t" - @ i += 1; -end - -# Prepare all .args files -iteration: -echo "" -echo "<<<" -echo "<<< Iteration ${iter}: ${iterations[$iter]}" -echo "<<<" -if (${iterations[$iter]} != "") then - ncprep +define+${iterations[$iter]} -f ../bin/nc.scr > ncprep.out -else - ncprep -f ../bin/nc.scr > ncprep.out -endif -if (`tail -1 ncprep.out | grep Failed` != "") then - echo "" - cat ncprep.out - exit -endif - -# Run NC-Verilog compiler -echo "" -echo "\t@@@" -echo "\t@@@ Compiling sources" -echo "\t@@@" -ncvlog -NOCOPYRIGHT -f ncvlog.args > ncvlog.out -if ($status != 0) then - echo "\t@@@ FAILED" - echo "" - cat ncvlog.out - exit -else - echo "\t@@@ Passed" -endif - -# Run the NC-Verilog elaborator (build the design hierarchy) -echo "" -echo "\t@@@" -echo "\t@@@ Building design hierarchy (elaboration)" -echo "\t@@@" -ncelab -NOTIMINGCHECKS -NOCOPYRIGHT -f ncelab.args > ncelab.out -if ($status != 0) then - echo "\t@@@ FAILED" - echo "" - cat ncelab.out - exit -else - echo "\t@@@ Passed" -endif - -# Run the NC-Verilog simulator (simulate the design) -sim: -set i = 0; -foreach test ($tests) - @ i += 1; - echo "" - echo "\t###" - echo "\t### Running test ${i}: ${test}, $maxtimes[$i] ms" - echo "\t###" - - echo "database -open waves -into ../out/wave/i${iter}-${test} -default" > sim.tcl - echo "probe -create -shm xess_top -all -variables -depth all" >> sim.tcl - echo "stop -create -time $maxtimes[$i]ms -relative" >> sim.tcl - echo "run" >> sim.tcl - echo "quit" >> sim.tcl - - cp ../src/${test}.mem ../src/flash.in - ncsim -NOCOPYRIGHT -f ncsim.args > ncsim.out - if ($status != 0) then - cat ncsim.out - exit - else - set magic=`tail -1 nop.log | cut -d'(' -f2 | cut -d')' -f1` - set magictime=`tail -1 nop.log | cut -d'n' -f1` - if ($magic == "deaddead") then - echo "\t### Passed (@time $magictime)" - @ all_tests += 1; - else - echo "\t### FAILED (@time $magictime, magic# 0x$magic)" - @ failed += 1; - @ all_tests += 1; - endif - mv flash.log ../log/i${iter}-${test}-flash.log - mv executed.log ../log/i${iter}-${test}-executed.log - mv sram.log ../log/i${iter}-${test}-sram.log - mv sprs.log ../log/i${iter}-${test}-sprs.log - mv nop.log ../log/i${iter}-${test}-nop.log - endif -end - -@ iter += 1; -if ($iterations[$iter] != "") then - goto iteration -else - echo "" - echo "<<<" - echo "<<< End of Regression Iterations" - echo "<<<" - echo "<<< Failed $failed out of $all_tests" - echo "<<<" -endif -

run/regression_example Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/rtl_file_list.lst =================================================================== --- bin/rtl_file_list.lst (revision 154) +++ bin/rtl_file_list.lst (nonexistent) @@ -1,54 +0,0 @@ -../../../rtl/verilog/pci_parity_check.v -../../../rtl/verilog/pci_target_unit.v -../../../rtl/verilog/pci_wb_addr_mux.v -../../../rtl/verilog/pci_cbe_en_crit.v -../../../rtl/verilog/pci_pcir_fifo_control.v -../../../rtl/verilog/pci_out_reg.v -../../../rtl/verilog/pci_pci_tpram.v -../../../rtl/verilog/pci_wb_master.v -../../../rtl/verilog/pci_conf_cyc_addr_dec.v -../../../rtl/verilog/pci_frame_crit.v -../../../rtl/verilog/pci_target32_clk_en.v -../../../rtl/verilog/pci_pciw_fifo_control.v -../../../rtl/verilog/pci_wb_slave.v -../../../rtl/verilog/pci_conf_space.v -../../../rtl/verilog/pci_frame_en_crit.v -../../../rtl/verilog/pci_par_crit.v -../../../rtl/verilog/pci_pciw_pcir_fifos.v -../../../rtl/verilog/pci_wb_slave_unit.v -../../../rtl/verilog/pci_frame_load_crit.v -../../../rtl/verilog/pci_bridge32.v -../../../rtl/verilog/pci_target32_devs_crit.v -../../../rtl/verilog/pci_perr_crit.v -../../../rtl/verilog/pci_wbr_fifo_control.v -../../../rtl/verilog/pci_cur_out_reg.v -../../../rtl/verilog/pci_pci_decoder.v -../../../rtl/verilog/pci_target32_interface.v -../../../rtl/verilog/pci_perr_en_crit.v -../../../rtl/verilog/pci_wbw_fifo_control.v -../../../rtl/verilog/pci_wb_decoder.v -../../../rtl/verilog/pci_in_reg.v -../../../rtl/verilog/pci_serr_crit.v -../../../rtl/verilog/pci_wbw_wbr_fifos.v -../../../rtl/verilog/pci_delayed_sync.v -../../../rtl/verilog/pci_irdy_out_crit.v -../../../rtl/verilog/pci_io_mux.v -../../../rtl/verilog/pci_io_mux_ad_en_crit.v -../../../rtl/verilog/pci_io_mux_ad_load_crit.v -../../../rtl/verilog/pci_target32_sm.v -../../../rtl/verilog/pci_serr_en_crit.v -../../../rtl/verilog/pci_delayed_write_reg.v -../../../rtl/verilog/pci_mas_ad_en_crit.v -../../../rtl/verilog/pci_mas_ad_load_crit.v -../../../rtl/verilog/pci_master32_sm.v -../../../rtl/verilog/pci_target32_stop_crit.v -../../../rtl/verilog/synchronizer_flop.v -../../../rtl/verilog/pci_async_reset_flop.v -../../../rtl/verilog/pci_mas_ch_state_crit.v -../../../rtl/verilog/pci_master32_sm_if.v -../../../rtl/verilog/pci_target32_trdy_crit.v -../../../rtl/verilog/top.v -../../../rtl/verilog/pci_rst_int.v -../../../rtl/verilog/pci_sync_module.v -../../../rtl/verilog/pci_wb_tpram.v -../../../rtl/verilog/meta_flop.v

bin/rtl_file_list.lst Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/vs_file_list.lst =================================================================== --- bin/vs_file_list.lst (revision 154) +++ bin/vs_file_list.lst (nonexistent) @@ -1,4 +0,0 @@ -vs_rams/018/vs_hdtp_64x40/vs_hdtp_64x40.v -vs_rams/018/vs_hdtp_64x40_bist.v -bist/rtl/verilog/bist_two_port.v -logic/rtl/verilog/jt_bc1in.v Index: bin/xilinx_file_list.lst =================================================================== --- bin/xilinx_file_list.lst (revision 154) +++ bin/xilinx_file_list.lst (nonexistent) @@ -1,4 +0,0 @@ -../../../../../../lib/xilinx/lib/glbl/glbl.v -../../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v -../../../../../../lib/xilinx/lib/unisims/RAM16X1D.v -../../../rtl/verilog/pci_ram_16x40d.v

bin/xilinx_file_list.lst Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/sim_file_list.lst =================================================================== --- bin/sim_file_list.lst (revision 154) +++ bin/sim_file_list.lst (nonexistent) @@ -1,12 +0,0 @@ -../../../bench/verilog/wb_master32.v -../../../bench/verilog/wb_master_behavioral.v -../../../bench/verilog/system.v -../../../bench/verilog/pci_blue_arbiter.v -../../../bench/verilog/pci_bus_monitor.v -../../../bench/verilog/pci_behaviorial_device.v -../../../bench/verilog/pci_behaviorial_master.v -../../../bench/verilog/pci_behaviorial_target.v -../../../bench/verilog/wb_slave_behavioral.v -../../../bench/verilog/wb_bus_mon.v -../../../bench/verilog/pci_unsupported_commands_master.v -../../../bench/verilog/pci_behavioral_pci2pci_bridge.v

bin/sim_file_list.lst Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/ncsim_waves.rc =================================================================== --- bin/ncsim_waves.rc (revision 154) +++ bin/ncsim_waves.rc (nonexistent) @@ -1,7 +0,0 @@ -set dump_level all - -database -open waves -shm -into ../out/waves.shm -probe -create -database waves SYSTEM -shm -all -depth $dump_level - -run -quit

bin/ncsim_waves.rc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/artisan_file_list.lst =================================================================== --- bin/artisan_file_list.lst (revision 154) +++ bin/artisan_file_list.lst (nonexistent) @@ -1,6 +0,0 @@ --cdslib ../bin/cds.lib --hdlvar ../bin/hdl.var --logfile ../log/ncvlog_artisan.log --update --messages -../../../../../../lib/artisan/art_hsdp_256x40.v

bin/artisan_file_list.lst Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/ncsim.rc =================================================================== --- bin/ncsim.rc (revision 154) +++ bin/ncsim.rc (nonexistent) @@ -1,2 +0,0 @@ -run -quit

bin/ncsim.rc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/ncelab.args =================================================================== --- bin/ncelab.args (revision 154) +++ bin/ncelab.args (nonexistent) @@ -1,7 +0,0 @@ --snapshot worklib.bridge32:fun --cdslib ../bin/cds.lib --logfile ../log/ncelab.log --access +wc --messages --no_tchk_msg --v93 worklib.SYSTEM

bin/ncelab.args Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/nc_xilinx.scr =================================================================== --- bin/nc_xilinx.scr (revision 154) +++ bin/nc_xilinx.scr (nonexistent) @@ -1,76 +0,0 @@ -//+ncelabargs+"-timescale 1ns/10ps" -+libext+.v -// RTL sources -../../../rtl/verilog/pci_parity_check.v -../../../rtl/verilog/pci_target_unit.v -../../../rtl/verilog/wb_addr_mux.v -../../../rtl/verilog/cbe_en_crit.v -../../../rtl/verilog/fifo_control.v -../../../rtl/verilog/out_reg.v -../../../rtl/verilog/pci_tpram.v -../../../rtl/verilog/wb_master.v -../../../rtl/verilog/conf_cyc_addr_dec.v -../../../rtl/verilog/frame_crit.v -../../../rtl/verilog/pci_target32_clk_en.v -../../../rtl/verilog/pciw_fifo_control.v -../../../rtl/verilog/wb_slave.v -../../../rtl/verilog/conf_space.v -../../../rtl/verilog/frame_en_crit.v -../../../rtl/verilog/par_crit.v -../../../rtl/verilog/pci_target32_ctrl_en_crit.v -../../../rtl/verilog/pciw_pcir_fifos.v -../../../rtl/verilog/wb_slave_unit.v -../../../rtl/verilog/frame_load_crit.v -../../../rtl/verilog/pci_bridge32.v -../../../rtl/verilog/pci_target32_devs_crit.v -../../../rtl/verilog/perr_crit.v -../../../rtl/verilog/wbr_fifo_control.v -../../../rtl/verilog/cur_out_reg.v -../../../rtl/verilog/pci_decoder.v -../../../rtl/verilog/pci_target32_interface.v -../../../rtl/verilog/perr_en_crit.v -../../../rtl/verilog/wbw_fifo_control.v -../../../rtl/verilog/decoder.v -../../../rtl/verilog/pci_in_reg.v -../../../rtl/verilog/pci_target32_load_crit.v -../../../rtl/verilog/serr_crit.v -../../../rtl/verilog/wbw_wbr_fifos.v -../../../rtl/verilog/delayed_sync.v -../../../rtl/verilog/irdy_out_crit.v -../../../rtl/verilog/pci_io_mux.v -../../../rtl/verilog/pci_io_mux_ad_en_crit.v -../../../rtl/verilog/pci_io_mux_ad_load_crit.v -../../../rtl/verilog/pci_target32_sm.v -../../../rtl/verilog/serr_en_crit.v -../../../rtl/verilog/delayed_write_reg.v -../../../rtl/verilog/mas_ad_en_crit.v -../../../rtl/verilog/mas_ad_load_crit.v -../../../rtl/verilog/pci_master32_sm.v -../../../rtl/verilog/pci_target32_stop_crit.v -../../../rtl/verilog/synchronizer_flop.v -../../../rtl/verilog/async_reset_flop.v -../../../rtl/verilog/mas_ch_state_crit.v -../../../rtl/verilog/pci_master32_sm_if.v -../../../rtl/verilog/pci_target32_trdy_crit.v -../../../rtl/verilog/top.v -../../../rtl/verilog/pci_rst_int.v -../../../rtl/verilog/sync_module.v -../../../rtl/verilog/wb_tpram.v -// Sim sources -../../../bench/verilog/wb_master32.v -../../../bench/verilog/wb_master_behavioral.v -../../../bench/verilog/system.v -../../../bench/verilog/pci_blue_arbiter.v -../../../bench/verilog/pci_bus_monitor.v -../../../bench/verilog/pci_behaviorial_device.v -../../../bench/verilog/pci_behaviorial_master.v -../../../bench/verilog/pci_behaviorial_target.v -../../../bench/verilog/wb_slave_behavioral.v -../../../bench/verilog/wb_bus_mon.v -../../../bench/verilog/wb_slave32.v -../../../bench/verilog/pci_behavioral_iack_target.v -../../../bench/verilog/pci_unsupported_commands_master.v -// Libs -../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v -../../../../lib/xilinx/lib/glbl/glbl.v -//../../../../lib/artisan/art_hsdp_256x40.v \ No newline at end of file

bin/nc_xilinx.scr Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/nc.scr =================================================================== --- bin/nc.scr (revision 154) +++ bin/nc.scr (nonexistent) @@ -1,76 +0,0 @@ -//+ncelabargs+"-timescale 1ns/10ps" -+libext+.v -// RTL sources -../../../rtl/verilog/pci_parity_check.v -../../../rtl/verilog/pci_target_unit.v -../../../rtl/verilog/wb_addr_mux.v -../../../rtl/verilog/cbe_en_crit.v -../../../rtl/verilog/fifo_control.v -../../../rtl/verilog/out_reg.v -../../../rtl/verilog/pci_tpram.v -../../../rtl/verilog/wb_master.v -../../../rtl/verilog/conf_cyc_addr_dec.v -../../../rtl/verilog/frame_crit.v -../../../rtl/verilog/pci_target32_clk_en.v -../../../rtl/verilog/pciw_fifo_control.v -../../../rtl/verilog/wb_slave.v -../../../rtl/verilog/conf_space.v -../../../rtl/verilog/frame_en_crit.v -../../../rtl/verilog/par_crit.v -../../../rtl/verilog/pci_target32_ctrl_en_crit.v -../../../rtl/verilog/pciw_pcir_fifos.v -../../../rtl/verilog/wb_slave_unit.v -../../../rtl/verilog/frame_load_crit.v -../../../rtl/verilog/pci_bridge32.v -../../../rtl/verilog/pci_target32_devs_crit.v -../../../rtl/verilog/perr_crit.v -../../../rtl/verilog/wbr_fifo_control.v -../../../rtl/verilog/cur_out_reg.v -../../../rtl/verilog/pci_decoder.v -../../../rtl/verilog/pci_target32_interface.v -../../../rtl/verilog/perr_en_crit.v -../../../rtl/verilog/wbw_fifo_control.v -../../../rtl/verilog/decoder.v -../../../rtl/verilog/pci_in_reg.v -../../../rtl/verilog/pci_target32_load_crit.v -../../../rtl/verilog/serr_crit.v -../../../rtl/verilog/wbw_wbr_fifos.v -../../../rtl/verilog/delayed_sync.v -../../../rtl/verilog/irdy_out_crit.v -../../../rtl/verilog/pci_io_mux.v -../../../rtl/verilog/pci_io_mux_ad_en_crit.v -../../../rtl/verilog/pci_io_mux_ad_load_crit.v -../../../rtl/verilog/pci_target32_sm.v -../../../rtl/verilog/serr_en_crit.v -../../../rtl/verilog/delayed_write_reg.v -../../../rtl/verilog/mas_ad_en_crit.v -../../../rtl/verilog/mas_ad_load_crit.v -../../../rtl/verilog/pci_master32_sm.v -../../../rtl/verilog/pci_target32_stop_crit.v -../../../rtl/verilog/synchronizer_flop.v -../../../rtl/verilog/async_reset_flop.v -../../../rtl/verilog/mas_ch_state_crit.v -../../../rtl/verilog/pci_master32_sm_if.v -../../../rtl/verilog/pci_target32_trdy_crit.v -../../../rtl/verilog/top.v -../../../rtl/verilog/pci_rst_int.v -../../../rtl/verilog/sync_module.v -../../../rtl/verilog/wb_tpram.v -// Sim sources -../../../bench/verilog/wb_master32.v -../../../bench/verilog/wb_master_behavioral.v -../../../bench/verilog/system.v -../../../bench/verilog/pci_blue_arbiter.v -../../../bench/verilog/pci_bus_monitor.v -../../../bench/verilog/pci_behaviorial_device.v -../../../bench/verilog/pci_behaviorial_master.v -../../../bench/verilog/pci_behaviorial_target.v -../../../bench/verilog/wb_slave_behavioral.v -../../../bench/verilog/wb_bus_mon.v -../../../bench/verilog/wb_slave32.v -../../../bench/verilog/pci_behavioral_iack_target.v -../../../bench/verilog/pci_unsupported_commands_master.v -// Libs -//../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v -//../../../../lib/xilinx/lib/glbl/glbl.v -//../../../../lib/artisan/art_hsdp_256x40.v \ No newline at end of file

bin/nc.scr Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/ncvlog_sim.args =================================================================== --- bin/ncvlog_sim.args (revision 154) +++ bin/ncvlog_sim.args (nonexistent) @@ -1,19 +0,0 @@ --cdslib ../bin/cds.lib --hdlvar ../bin/hdl.var --logfile ../log/ncvlog_sim.log --update --messages --INCDIR ../../../bench/verilog --INCDIR ../../../rtl/verilog -../../../bench/verilog/wb_master32.v -../../../bench/verilog/wb_master_behavioral.v -../../../bench/verilog/system.v -../../../bench/verilog/pci_blue_arbiter.v -../../../bench/verilog/pci_bus_monitor.v -../../../bench/verilog/pci_behaviorial_device.v -../../../bench/verilog/pci_behaviorial_master.v -../../../bench/verilog/pci_behaviorial_target.v -../../../bench/verilog/wb_slave_behavioral.v -../../../bench/verilog/wb_bus_mon.v -../../../bench/verilog/pci_behavioral_iack_target.v -../../../bench/verilog/pci_unsupported_commands_master.v

bin/ncvlog_sim.args Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/hdl.var =================================================================== --- bin/hdl.var (revision 154) +++ bin/hdl.var (nonexistent) @@ -1,9 +0,0 @@ -# -# hdl.var: Defines variables used by the INCA tools. -# Created by ncprep on Sat Aug 4 10:51:23 2001 -# - -softinclude $CDS_INST_DIR/tools/inca/files/hdl.var - -define LIB_MAP ( $LIB_MAP, + => worklib ) -define VIEW_MAP ( $VIEW_MAP, .v => v)

bin/hdl.var Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/ncvlog_artisan.scr =================================================================== --- bin/ncvlog_artisan.scr (revision 154) +++ bin/ncvlog_artisan.scr (nonexistent) @@ -1 +0,0 @@ -ncvlog -cdslib ../bin/cds.lib -hdlvar ../bin/hdl.var -logfile ../log/ncvlog_artisan.log -update -messages $ARTISAN/art_hsdp_256x40.v

bin/ncvlog_artisan.scr Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/nc_xilinx_artisan.scr =================================================================== --- bin/nc_xilinx_artisan.scr (revision 154) +++ bin/nc_xilinx_artisan.scr (nonexistent) @@ -1,76 +0,0 @@ -//+ncelabargs+"-timescale 1ns/10ps" -+libext+.v -// RTL sources -../../../rtl/verilog/pci_parity_check.v -../../../rtl/verilog/pci_target_unit.v -../../../rtl/verilog/wb_addr_mux.v -../../../rtl/verilog/cbe_en_crit.v -../../../rtl/verilog/fifo_control.v -../../../rtl/verilog/out_reg.v -../../../rtl/verilog/pci_tpram.v -../../../rtl/verilog/wb_master.v -../../../rtl/verilog/conf_cyc_addr_dec.v -../../../rtl/verilog/frame_crit.v -../../../rtl/verilog/pci_target32_clk_en.v -../../../rtl/verilog/pciw_fifo_control.v -../../../rtl/verilog/wb_slave.v -../../../rtl/verilog/conf_space.v -../../../rtl/verilog/frame_en_crit.v -../../../rtl/verilog/par_crit.v -../../../rtl/verilog/pci_target32_ctrl_en_crit.v -../../../rtl/verilog/pciw_pcir_fifos.v -../../../rtl/verilog/wb_slave_unit.v -../../../rtl/verilog/frame_load_crit.v -../../../rtl/verilog/pci_bridge32.v -../../../rtl/verilog/pci_target32_devs_crit.v -../../../rtl/verilog/perr_crit.v -../../../rtl/verilog/wbr_fifo_control.v -../../../rtl/verilog/cur_out_reg.v -../../../rtl/verilog/pci_decoder.v -../../../rtl/verilog/pci_target32_interface.v -../../../rtl/verilog/perr_en_crit.v -../../../rtl/verilog/wbw_fifo_control.v -../../../rtl/verilog/decoder.v -../../../rtl/verilog/pci_in_reg.v -../../../rtl/verilog/pci_target32_load_crit.v -../../../rtl/verilog/serr_crit.v -../../../rtl/verilog/wbw_wbr_fifos.v -../../../rtl/verilog/delayed_sync.v -../../../rtl/verilog/irdy_out_crit.v -../../../rtl/verilog/pci_io_mux.v -../../../rtl/verilog/pci_io_mux_ad_en_crit.v -../../../rtl/verilog/pci_io_mux_ad_load_crit.v -../../../rtl/verilog/pci_target32_sm.v -../../../rtl/verilog/serr_en_crit.v -../../../rtl/verilog/delayed_write_reg.v -../../../rtl/verilog/mas_ad_en_crit.v -../../../rtl/verilog/mas_ad_load_crit.v -../../../rtl/verilog/pci_master32_sm.v -../../../rtl/verilog/pci_target32_stop_crit.v -../../../rtl/verilog/synchronizer_flop.v -../../../rtl/verilog/async_reset_flop.v -../../../rtl/verilog/mas_ch_state_crit.v -../../../rtl/verilog/pci_master32_sm_if.v -../../../rtl/verilog/pci_target32_trdy_crit.v -../../../rtl/verilog/top.v -../../../rtl/verilog/pci_rst_int.v -../../../rtl/verilog/sync_module.v -../../../rtl/verilog/wb_tpram.v -// Sim sources -../../../bench/verilog/wb_master32.v -../../../bench/verilog/wb_master_behavioral.v -../../../bench/verilog/system.v -../../../bench/verilog/pci_blue_arbiter.v -../../../bench/verilog/pci_bus_monitor.v -../../../bench/verilog/pci_behaviorial_device.v -../../../bench/verilog/pci_behaviorial_master.v -../../../bench/verilog/pci_behaviorial_target.v -../../../bench/verilog/wb_slave_behavioral.v -../../../bench/verilog/wb_bus_mon.v -../../../bench/verilog/wb_slave32.v -../../../bench/verilog/pci_behavioral_iack_target.v -../../../bench/verilog/pci_unsupported_commands_master.v -// Libs -../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v -../../../../lib/xilinx/lib/glbl/glbl.v -../../../../lib/artisan/art_hsdp_256x40.v \ No newline at end of file

bin/nc_xilinx_artisan.scr Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/ncsim.args =================================================================== --- bin/ncsim.args (revision 154) +++ bin/ncsim.args (nonexistent) @@ -1,6 +0,0 @@ --cdslib ../bin/cds.lib --hdlvar ../bin/hdl.var --logfile ../log/ncsim.log --messages --input ../bin/ncsim.rc -worklib.bridge32:fun

bin/ncsim.args Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/ncvlog_artisan.args =================================================================== --- bin/ncvlog_artisan.args (revision 154) +++ bin/ncvlog_artisan.args (nonexistent) @@ -1 +0,0 @@ -../../../../lib/artisan/art_hsdp_256x40.v

bin/ncvlog_artisan.args Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/ncvlog_rtl.args =================================================================== --- bin/ncvlog_rtl.args (revision 154) +++ bin/ncvlog_rtl.args (nonexistent) @@ -1,59 +0,0 @@ --cdslib ../bin/cds.lib --hdlvar ../bin/hdl.var --logfile ../log/ncvlog_rtl.log --update --messages --INCDIR ../../../rtl/verilog -../../../rtl/verilog/pci_parity_check.v -../../../rtl/verilog/pci_target_unit.v -../../../rtl/verilog/wb_addr_mux.v -../../../rtl/verilog/cbe_en_crit.v -../../../rtl/verilog/fifo_control.v -../../../rtl/verilog/out_reg.v -../../../rtl/verilog/pci_tpram.v -../../../rtl/verilog/wb_master.v -../../../rtl/verilog/conf_cyc_addr_dec.v -../../../rtl/verilog/frame_crit.v -../../../rtl/verilog/pci_target32_clk_en.v -../../../rtl/verilog/pciw_fifo_control.v -../../../rtl/verilog/wb_slave.v -../../../rtl/verilog/conf_space.v -../../../rtl/verilog/frame_en_crit.v -../../../rtl/verilog/par_crit.v -../../../rtl/verilog/pciw_pcir_fifos.v -../../../rtl/verilog/wb_slave_unit.v -../../../rtl/verilog/frame_load_crit.v -../../../rtl/verilog/pci_bridge32.v -../../../rtl/verilog/pci_target32_devs_crit.v -../../../rtl/verilog/perr_crit.v -../../../rtl/verilog/wbr_fifo_control.v -../../../rtl/verilog/cur_out_reg.v -../../../rtl/verilog/pci_decoder.v -../../../rtl/verilog/pci_target32_interface.v -../../../rtl/verilog/perr_en_crit.v -../../../rtl/verilog/wbw_fifo_control.v -../../../rtl/verilog/decoder.v -../../../rtl/verilog/pci_in_reg.v -../../../rtl/verilog/serr_crit.v -../../../rtl/verilog/wbw_wbr_fifos.v -../../../rtl/verilog/delayed_sync.v -../../../rtl/verilog/irdy_out_crit.v -../../../rtl/verilog/pci_io_mux.v -../../../rtl/verilog/pci_io_mux_ad_en_crit.v -../../../rtl/verilog/pci_io_mux_ad_load_crit.v -../../../rtl/verilog/pci_target32_sm.v -../../../rtl/verilog/serr_en_crit.v -../../../rtl/verilog/delayed_write_reg.v -../../../rtl/verilog/mas_ad_en_crit.v -../../../rtl/verilog/mas_ad_load_crit.v -../../../rtl/verilog/pci_master32_sm.v -../../../rtl/verilog/pci_target32_stop_crit.v -../../../rtl/verilog/synchronizer_flop.v -../../../rtl/verilog/async_reset_flop.v -../../../rtl/verilog/mas_ch_state_crit.v -../../../rtl/verilog/pci_master32_sm_if.v -../../../rtl/verilog/pci_target32_trdy_crit.v -../../../rtl/verilog/top.v -../../../rtl/verilog/pci_rst_int.v -../../../rtl/verilog/sync_module.v -../../../rtl/verilog/wb_tpram.v

bin/ncvlog_rtl.args Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/nc_artisan.scr =================================================================== --- bin/nc_artisan.scr (revision 154) +++ bin/nc_artisan.scr (nonexistent) @@ -1,76 +0,0 @@ -//+ncelabargs+"-timescale 1ns/10ps" -+libext+.v -// RTL sources -../../../rtl/verilog/pci_parity_check.v -../../../rtl/verilog/pci_target_unit.v -../../../rtl/verilog/wb_addr_mux.v -../../../rtl/verilog/cbe_en_crit.v -../../../rtl/verilog/fifo_control.v -../../../rtl/verilog/out_reg.v -../../../rtl/verilog/pci_tpram.v -../../../rtl/verilog/wb_master.v -../../../rtl/verilog/conf_cyc_addr_dec.v -../../../rtl/verilog/frame_crit.v -../../../rtl/verilog/pci_target32_clk_en.v -../../../rtl/verilog/pciw_fifo_control.v -../../../rtl/verilog/wb_slave.v -../../../rtl/verilog/conf_space.v -../../../rtl/verilog/frame_en_crit.v -../../../rtl/verilog/par_crit.v -../../../rtl/verilog/pci_target32_ctrl_en_crit.v -../../../rtl/verilog/pciw_pcir_fifos.v -../../../rtl/verilog/wb_slave_unit.v -../../../rtl/verilog/frame_load_crit.v -../../../rtl/verilog/pci_bridge32.v -../../../rtl/verilog/pci_target32_devs_crit.v -../../../rtl/verilog/perr_crit.v -../../../rtl/verilog/wbr_fifo_control.v -../../../rtl/verilog/cur_out_reg.v -../../../rtl/verilog/pci_decoder.v -../../../rtl/verilog/pci_target32_interface.v -../../../rtl/verilog/perr_en_crit.v -../../../rtl/verilog/wbw_fifo_control.v -../../../rtl/verilog/decoder.v -../../../rtl/verilog/pci_in_reg.v -../../../rtl/verilog/pci_target32_load_crit.v -../../../rtl/verilog/serr_crit.v -../../../rtl/verilog/wbw_wbr_fifos.v -../../../rtl/verilog/delayed_sync.v -../../../rtl/verilog/irdy_out_crit.v -../../../rtl/verilog/pci_io_mux.v -../../../rtl/verilog/pci_io_mux_ad_en_crit.v -../../../rtl/verilog/pci_io_mux_ad_load_crit.v -../../../rtl/verilog/pci_target32_sm.v -../../../rtl/verilog/serr_en_crit.v -../../../rtl/verilog/delayed_write_reg.v -../../../rtl/verilog/mas_ad_en_crit.v -../../../rtl/verilog/mas_ad_load_crit.v -../../../rtl/verilog/pci_master32_sm.v -../../../rtl/verilog/pci_target32_stop_crit.v -../../../rtl/verilog/synchronizer_flop.v -../../../rtl/verilog/async_reset_flop.v -../../../rtl/verilog/mas_ch_state_crit.v -../../../rtl/verilog/pci_master32_sm_if.v -../../../rtl/verilog/pci_target32_trdy_crit.v -../../../rtl/verilog/top.v -../../../rtl/verilog/pci_rst_int.v -../../../rtl/verilog/sync_module.v -../../../rtl/verilog/wb_tpram.v -// Sim sources -../../../bench/verilog/wb_master32.v -../../../bench/verilog/wb_master_behavioral.v -../../../bench/verilog/system.v -../../../bench/verilog/pci_blue_arbiter.v -../../../bench/verilog/pci_bus_monitor.v -../../../bench/verilog/pci_behaviorial_device.v -../../../bench/verilog/pci_behaviorial_master.v -../../../bench/verilog/pci_behaviorial_target.v -../../../bench/verilog/wb_slave_behavioral.v -../../../bench/verilog/wb_bus_mon.v -../../../bench/verilog/wb_slave32.v -../../../bench/verilog/pci_behavioral_iack_target.v -../../../bench/verilog/pci_unsupported_commands_master.v -// Libs -//../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v -//../../../../lib/xilinx/lib/glbl/glbl.v -../../../../lib/artisan/art_hsdp_256x40.v \ No newline at end of file

bin/nc_artisan.scr Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/ncvlog_xilinx.scr =================================================================== --- bin/ncvlog_xilinx.scr (revision 154) +++ bin/ncvlog_xilinx.scr (nonexistent) @@ -1 +0,0 @@ -ncvlog -cdslib ../bin/cds.lib -hdlvar ../bin/hdl.var -logfile ../log/ncvlog_xilinx.log -update -messages $XILINX/lib/unisims/RAMB4_S16_S16.v $XILINX/lib/glbl/glbl.v $XILINX/lib/unisims/RAM16X1D.v

bin/ncvlog_xilinx.scr Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/ncelab_xilinx.args =================================================================== --- bin/ncelab_xilinx.args (revision 154) +++ bin/ncelab_xilinx.args (nonexistent) @@ -1,8 +0,0 @@ --snapshot worklib.bridge32:fun --cdslib ../bin/cds.lib --logfile ../log/ncelab_xilinx.log --access +wc --messages --no_tchk_msg --v93 -worklib.SYSTEM worklib.glbl

bin/ncelab_xilinx.args Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/ncvlog_xilinx.args =================================================================== --- bin/ncvlog_xilinx.args (revision 154) +++ bin/ncvlog_xilinx.args (nonexistent) @@ -1,8 +0,0 @@ --cdslib ../bin/cds.lib --hdlvar ../bin/hdl.var --logfile ../log/ncvlog_xilinx.log --update --messages -../../../../lib/xilinx/lib/glbl/glbl.v -../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v -../../../../lib/xilinx/lib/unisims/RAM16X1D.v

bin/ncvlog_xilinx.args Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/cds.lib =================================================================== --- bin/cds.lib (revision 154) +++ bin/cds.lib (nonexistent) @@ -1,2 +0,0 @@ -define worklib ../bin/INCA_libs/worklib -include $CDS_INST_DIR/tools/inca/files/cds.lib

bin/cds.lib Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property