Subversion Repositories pci

/cons_vs_umc18.inc File deleted

cons_vs_umc18.inc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: elaborate_design.inc =================================================================== --- elaborate_design.inc (revision 154) +++ elaborate_design.inc (nonexistent) @@ -1,10 +0,0 @@ -/* Set search path for verilog include files */ -search_path = search_path + { RTL_PATH } + { GATE_PATH } - -/* Read verilog files of the PCI IP core */ -if (TOPLEVEL == "TOP") { - elaborate TOPLEVEL -} else { - echo "Non-existing top level." - exit -}

elaborate_design.inc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: save_design.inc =================================================================== --- save_design.inc (revision 154) +++ save_design.inc (nonexistent) @@ -1,5 +0,0 @@ -/* Save current design using synopsys format */ -write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db - -/* Save current design using verilog format */ -write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v

save_design.inc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: tech_vs_umc18.inc =================================================================== --- tech_vs_umc18.inc (revision 154) +++ tech_vs_umc18.inc (nonexistent) @@ -1,16 +0,0 @@ -/* Set Virtual Silicon UMC 0.18u standard cell library */ - -search_path = {. /projects/libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ /projects/libs/Artisan/artisan_rams/art_hsdp_256x40/} -snps = get_unix_variable("SYNOPSYS") -synthetic_library = { \ - snps + "/libraries/syn/dw01.sldb" \ - snps + "/libraries/syn/dw02.sldb" \ - snps + "/libraries/syn/dw03.sldb" \ - snps + "/libraries/syn/dw04.sldb" \ - snps + "/libraries/syn/dw05.sldb" \ - snps + "/libraries/syn/dw06.sldb" \ - snps + "/libraries/syn/dw07.sldb" } -target_library = { umcl18u250t2_bc.db umcl18u250t2_wc.db art_hsdp_256x40_slow_syn.db art_hsdp_256x40_fast_syn.db} -link_library = target_library + synthetic_library -symbol_library = { umcl18u250t2.sdb } -set_min_library umcl18u250t2_wc.db -min_version umcl18u250t2_bc.db

tech_vs_umc18.inc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: analyze_design.inc =================================================================== --- analyze_design.inc (revision 154) +++ analyze_design.inc (nonexistent) @@ -1,67 +0,0 @@ -/* Set search path for verilog include files */ -search_path = search_path + { RTL_PATH } + { GATE_PATH } - -/* Read verilog files of the PCI IP core */ -if (TOPLEVEL == "TOP") { - analyze -f verilog pci_bridge32.v - analyze -f verilog mas_load_next_crit.v - analyze -f verilog pci_parity_check.v - analyze -f verilog pci_target_unit.v - analyze -f verilog wb_addr_mux.v - analyze -f verilog cbe_en_crit.v - analyze -f verilog fifo_control.v - analyze -f verilog out_reg.v - analyze -f verilog pci_target32_ad_en_crit.v - analyze -f verilog pci_tpram.v - analyze -f verilog wb_master.v - analyze -f verilog conf_cyc_addr_dec.v - analyze -f verilog frame_crit.v - analyze -f verilog par_cbe_crit.v - analyze -f verilog pci_target32_clk_en.v - analyze -f verilog pciw_fifo_control.v - analyze -f verilog wb_slave.v - analyze -f verilog conf_space.v - analyze -f verilog frame_en_crit.v - analyze -f verilog par_crit.v - analyze -f verilog pci_target32_ctrl_en_crit.v - analyze -f verilog pciw_pcir_fifos.v - analyze -f verilog wb_slave_unit.v - analyze -f verilog frame_load_crit.v - analyze -f verilog pci_bridge32.v - analyze -f verilog pci_target32_devs_crit.v - analyze -f verilog perr_crit.v - analyze -f verilog wbr_fifo_control.v - analyze -f verilog cur_out_reg.v - analyze -f verilog io_mux_en_mult.v - analyze -f verilog pci_decoder.v - analyze -f verilog pci_target32_interface.v - analyze -f verilog perr_en_crit.v - analyze -f verilog wbw_fifo_control.v - analyze -f verilog decoder.v - analyze -f verilog io_mux_load_mux.v - analyze -f verilog pci_in_reg.v - analyze -f verilog pci_target32_load_crit.v - analyze -f verilog serr_crit.v - analyze -f verilog wbw_wbr_fifos.v - analyze -f verilog delayed_sync.v - analyze -f verilog irdy_out_crit.v - analyze -f verilog pci_io_mux.v - analyze -f verilog pci_target32_sm.v - analyze -f verilog serr_en_crit.v - analyze -f verilog delayed_write_reg.v - analyze -f verilog mas_ad_en_crit.v - analyze -f verilog pci_master32_sm.v - analyze -f verilog pci_target32_stop_crit.v - analyze -f verilog synchronizer_flop.v - analyze -f verilog mas_ch_state_crit.v - analyze -f verilog pci_master32_sm_if.v - analyze -f verilog pci_target32_trdy_crit.v - analyze -f verilog top.v - analyze -f verilog pci_rst_int.v - analyze -f verilog sync_module.v - analyze -f verilog wb_tpram.v -} else { - echo "Non-existing top level." - exit -} -

analyze_design.inc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: reports.inc =================================================================== --- reports.inc (revision 154) +++ reports.inc (nonexistent) @@ -1,10 +0,0 @@ -/* Basic reports */ -report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log -report_timing -nworst 1000 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log -report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log -report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log -report_constraint -all_violators > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log -/* -report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log -*/ -

reports.inc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: top_pci32.scr =================================================================== --- top_pci32.scr (revision 154) +++ top_pci32.scr (nonexistent) @@ -1,76 +0,0 @@ -/* - * User defines for synthesizing RTC IP core - * - */ -TOPLEVEL = TOP -include select_tech.inc -PCI_CLK = CLK -WB_CLK = CLK_I -RST = RST_I -PCI_CLK_PERIOD = 15 /* 66 MHz */ -WB_CLK_PERIOD = 5 /* 200 MHz */ -MAX_AREA = 0 /* Push hard */ -DO_UNGROUP = yes /* yes, no */ -DO_VERIFY = no /* yes, no */ -CHECK = no /* yes, no */ - -/* Set some basic variables related to environment */ -include set_env.inc -STAGE = final - -/* Load libraries */ -include tech_ + TECH + .inc - -/* Load HDL source files */ -/*include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log*/ -include analyze_design.inc > LOG_PATH + analyze_design_ + TOPLEVEL + .log -include elaborate_design.inc > LOG_PATH + elaborate_design_ + TOPLEVEL + .log - -/* Set design top */ -current_design TOPLEVEL - -/* Link all blocks and uniquify them */ -link -uniquify - -if (CHECK == "yes"){ -check_design > LOG_PATH + check_design_ + TOPLEVEL + .log -} - -create_clock WB_CLK -period WB_CLK_PERIOD -create_clock PCI_CLK -period PCI_CLK_PERIOD - -/* Apply PCI constraints */ -include cons_pci_ports.inc -include cons_wb_ports.inc - -/* Apply technology constraints */ -if (TECH == "vs_umc18") { - include cons_vs_umc18.inc -} else if (TECH == "art_umc18") { - include cons_art_umc18.inc -} else { - echo "Error: Unsupported technology" - exit -} - -/* Lets do basic synthesis */ -if (DO_UNGROUP == "yes") { - ungroup -all -flatten -} -compile -boundary_optimization -map_effort low - -/* Dump gate-level from incremental synthesis */ -include save_design.inc - -/* Generate reports for incremental synthesis */ -include reports.inc - -/* Verify design */ -if (DO_VERIFY == "yes") { - compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log -} - -/* Finish */ -sh date -exit

top_pci32.scr Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: cons_wb_ports.inc =================================================================== --- cons_wb_ports.inc (revision 154) +++ cons_wb_ports.inc (nonexistent) @@ -1,24 +0,0 @@ -set_input_delay -max 2 -clock WB_CLK {SDAT_I} -set_input_delay -max 2 -clock WB_CLK {ADR_I} -set_input_delay -max 2 -clock WB_CLK {SDAT_I} -set_input_delay -max 2 -clock WB_CLK {SEL_I} -set_input_delay -max 2 -clock WB_CLK {CYC_I} -set_input_delay -max 2 -clock WB_CLK {STB_I} -set_input_delay -max 2 -clock WB_CLK {CAB_I} -set_input_delay -max 2 -clock WB_CLK {WE_I} - -set_input_delay -max 2 -clock WB_CLK {MDAT_I} -set_input_delay -max 2 -clock WB_CLK {ACK_I} -set_input_delay -max 2 -clock WB_CLK {ERR_I} -set_input_delay -max 2 -clock WB_CLK {RTY_I} - -set_output_delay -max 2 -clock WB_CLK {SDAT_O} -set_output_delay -max 2 -clock WB_CLK {MDAT_O} -set_output_delay -max 2 -clock WB_CLK {ADR_O} -set_output_delay -max 2 -clock WB_CLK {ACK_O} -set_output_delay -max 2 -clock WB_CLK {ERR_O} -set_output_delay -max 2 -clock WB_CLK {RTY_O} -set_output_delay -max 2 -clock WB_CLK {CYC_O} -set_output_delay -max 2 -clock WB_CLK {CAB_O} -set_output_delay -max 2 -clock WB_CLK {WE_O} -set_output_delay -max 2 -clock WB_CLK {STB_O}

cons_wb_ports.inc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: select_tech.inc =================================================================== --- select_tech.inc (revision 154) +++ select_tech.inc (nonexistent) @@ -1,3 +0,0 @@ -/* Defaults */ - -TECH = vs_umc18 /* vs_umc18, art_umc18 */

select_tech.inc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: set_env.inc =================================================================== --- set_env.inc (revision 154) +++ set_env.inc (nonexistent) @@ -1,18 +0,0 @@ -/* Enable Verilog HDL preprocessor */ -hdlin_enable_vpp = true - -/* Set log path */ -LOG_PATH = "../logs/" - -/* Set gate-level netlist path */ -GATE_PATH = "../gate/" - -/* Set RAMS_PATH */ -RAMS_PATH = "../../lib/" - -/* Set RTL source path */ -RTL_PATH = "../../rtl/verilog/" - -/* Optimize adders */ -synlib_model_map_effort = high -hlo_share_effort = medium

set_env.inc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: cons_pci_ports.inc =================================================================== --- cons_pci_ports.inc (revision 154) +++ cons_pci_ports.inc (nonexistent) @@ -1,98 +0,0 @@ -/* PCI input delay constraints definition*/ -if ( PCI_CLK_PERIOD == 15 ){ - - /* 3ns setup time constraint */ - set_input_delay -max 12 -clock PCI_CLK {AD} - set_input_delay -max 12 -clock PCI_CLK {CBE} - set_input_delay -max 12 -clock PCI_CLK {FRAME} - set_input_delay -max 12 -clock PCI_CLK {IRDY} - set_input_delay -max 12 -clock PCI_CLK {IDSEL} - set_input_delay -max 12 -clock PCI_CLK {DEVSEL} - set_input_delay -max 12 -clock PCI_CLK {TRDY} - set_input_delay -max 12 -clock PCI_CLK {STOP} - set_input_delay -max 12 -clock PCI_CLK {PAR} - set_input_delay -max 12 -clock PCI_CLK {PERR} - - /* 0ns hold time constraints */ - set_input_delay -min 0 -clock PCI_CLK {AD} - set_input_delay -min 0 -clock PCI_CLK {CBE} - set_input_delay -min 0 -clock PCI_CLK {FRAME} - set_input_delay -min 0 -clock PCI_CLK {IRDY} - set_input_delay -min 0 -clock PCI_CLK {IDSEL} - set_input_delay -min 0 -clock PCI_CLK {DEVSEL} - set_input_delay -min 0 -clock PCI_CLK {TRDY} - set_input_delay -min 0 -clock PCI_CLK {STOP} - set_input_delay -min 0 -clock PCI_CLK {PAR} - set_input_delay -min 0 -clock PCI_CLK {PERR} - - /* GNT has 5ns constraint */ - set_input_delay -max 10 -clock PCI_CLK {GNT} - set_input_delay -min 0 -clock PCI_CLK {GNT} - - /* 6ns output delay constraints */ - set_output_delay -max 9 -clock PCI_CLK {AD} - set_output_delay -max 9 -clock PCI_CLK {CBE} - set_output_delay -max 9 -clock PCI_CLK {FRAME} - set_output_delay -max 9 -clock PCI_CLK {IRDY} - set_output_delay -max 9 -clock PCI_CLK {DEVSEL} - set_output_delay -max 9 -clock PCI_CLK {TRDY} - set_output_delay -max 9 -clock PCI_CLK {STOP} - set_output_delay -max 9 -clock PCI_CLK {PAR} - set_output_delay -max 9 -clock PCI_CLK {PERR} - set_output_delay -max 9 -clock PCI_CLK {SERR} - set_output_delay -max 9 -clock PCI_CLK {REQ} - -}else if ( PCI_CLK_PERIOD == 30 ){ - - /* 7ns setup time constraint */ - set_input_delay -max 23 -clock PCI_CLK {AD} - set_input_delay -max 23 -clock PCI_CLK {CBE} - set_input_delay -max 23 -clock PCI_CLK {FRAME} - set_input_delay -max 23 -clock PCI_CLK {IRDY} - set_input_delay -max 23 -clock PCI_CLK {IDSEL} - set_input_delay -max 23 -clock PCI_CLK {DEVSEL} - set_input_delay -max 23 -clock PCI_CLK {TRDY} - set_input_delay -max 23 -clock PCI_CLK {STOP} - set_input_delay -max 23 -clock PCI_CLK {PAR} - set_input_delay -max 23 -clock PCI_CLK {PERR} - - /* 0ns hold time constraints */ - set_input_delay -min 0 -clock PCI_CLK {AD} - set_input_delay -min 0 -clock PCI_CLK {CBE} - set_input_delay -min 0 -clock PCI_CLK {FRAME} - set_input_delay -min 0 -clock PCI_CLK {IRDY} - set_input_delay -min 0 -clock PCI_CLK {IDSEL} - set_input_delay -min 0 -clock PCI_CLK {DEVSEL} - set_input_delay -min 0 -clock PCI_CLK {TRDY} - set_input_delay -min 0 -clock PCI_CLK {STOP} - set_input_delay -min 0 -clock PCI_CLK {PAR} - set_input_delay -min 0 -clock PCI_CLK {PERR} - - /* GNT has 10ns constraint */ - set_input_delay -max 20 -clock PCI_CLK {GNT} - set_input_delay -min 0 -clock PCI_CLK {GNT} - - /* 11ns output delay constraints */ - set_output_delay -max 19 -clock PCI_CLK {AD} - set_output_delay -max 19 -clock PCI_CLK {CBE} - set_output_delay -max 19 -clock PCI_CLK {FRAME} - set_output_delay -max 19 -clock PCI_CLK {IRDY} - set_output_delay -max 19 -clock PCI_CLK {DEVSEL} - set_output_delay -max 19 -clock PCI_CLK {TRDY} - set_output_delay -max 19 -clock PCI_CLK {STOP} - set_output_delay -max 19 -clock PCI_CLK {PAR} - set_output_delay -max 19 -clock PCI_CLK {PERR} - set_output_delay -max 19 -clock PCI_CLK {SERR} - - /* REQ has 12ns output delay constraint */ - set_output_delay -max 12 -clock PCI_CLK {REQ} - -}else{ - echo "Error: Unsupported PCI clock period specified!" - exit -} - -set_false_path -from PCI_CLK -to WB_CLK -set_false_path -from WB_CLK -to PCI_CLK -set_false_path -from {bridge/configuration/*} -to {SDAT_O} -

cons_pci_ports.inc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: read_design.inc =================================================================== --- read_design.inc (revision 154) +++ read_design.inc (nonexistent) @@ -1,66 +0,0 @@ -/* Set search path for verilog include files */ -search_path = search_path + { RTL_PATH } + { GATE_PATH } - -/* Read verilog files of the PCI IP core */ -if (TOPLEVEL == "TOP") { - read -f verilog pci_bridge32.v - read -f verilog mas_load_next_crit.v - read -f verilog pci_parity_check.v - read -f verilog pci_target_unit.v - read -f verilog wb_addr_mux.v - read -f verilog cbe_en_crit.v - read -f verilog fifo_control.v - read -f verilog out_reg.v - read -f verilog pci_target32_ad_en_crit.v - read -f verilog pci_tpram.v - read -f verilog wb_master.v - read -f verilog conf_cyc_addr_dec.v - read -f verilog frame_crit.v - read -f verilog par_cbe_crit.v - read -f verilog pci_target32_clk_en.v - read -f verilog pciw_fifo_control.v - read -f verilog wb_slave.v - read -f verilog conf_space.v - read -f verilog frame_en_crit.v - read -f verilog par_crit.v - read -f verilog pci_target32_ctrl_en_crit.v - read -f verilog pciw_pcir_fifos.v - read -f verilog wb_slave_unit.v - read -f verilog frame_load_crit.v - read -f verilog pci_bridge32.v - read -f verilog pci_target32_devs_crit.v - read -f verilog perr_crit.v - read -f verilog wbr_fifo_control.v - read -f verilog cur_out_reg.v - read -f verilog io_mux_en_mult.v - read -f verilog pci_decoder.v - read -f verilog pci_target32_interface.v - read -f verilog perr_en_crit.v - read -f verilog wbw_fifo_control.v - read -f verilog decoder.v - read -f verilog io_mux_load_mux.v - read -f verilog pci_in_reg.v - read -f verilog pci_target32_load_crit.v - read -f verilog serr_crit.v - read -f verilog wbw_wbr_fifos.v - read -f verilog delayed_sync.v - read -f verilog irdy_out_crit.v - read -f verilog pci_io_mux.v - read -f verilog pci_target32_sm.v - read -f verilog serr_en_crit.v - read -f verilog delayed_write_reg.v - read -f verilog mas_ad_en_crit.v - read -f verilog pci_master32_sm.v - read -f verilog pci_target32_stop_crit.v - read -f verilog synchronizer_flop.v - read -f verilog mas_ch_state_crit.v - read -f verilog pci_master32_sm_if.v - read -f verilog pci_target32_trdy_crit.v - read -f verilog top.v - read -f verilog pci_rst_int.v - read -f verilog wb_tpram.v -} else { - echo "Non-existing top level." - exit -} -

read_design.inc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: cons_art_umc18.inc =================================================================== --- cons_art_umc18.inc (revision 154) +++ cons_art_umc18.inc (nonexistent) @@ -1,51 +0,0 @@ -/* Constraints */ -CLK_UNCERTAINTY = 0.1 /* 100 ps */ -DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */ -DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */ - -/* Clocks constraints */ -create_clock CLK -period CLK_PERIOD -create_clock ECLK -period CLK_PERIOD -set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY -set_dont_touch_network all_clocks() - -/* Reset constraints */ -set_driving_cell -none RST -set_drive 0 RST -set_dont_touch_network RST - -/* All inputs except reset and clock */ -all_inputs_wo_rst_clk = all_inputs() - CLK - RST - -/* Set output delays and load for output signals - * - * All outputs are assumed to go directly into - * external flip-flops for the purpose of this - * synthesis - */ -set_output_delay DFFHQX2_SETUP -clock CLK all_outputs() -set_load load_of(typical/DFFHQX2/D) * 1 all_outputs() - -/* Input delay and driving cell of all inputs - * - * All these signals are assumed to come directly from - * flip-flops for the purpose of this synthesis - * - */ -set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk -set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk - -/* Set design fanout */ -/* -set_max_fanout 10 TOPLEVEL -*/ - -/* Set area constraint */ -set_max_area MAX_AREA - -/* Optimize all near-critical paths to give extra slack for layout */ -c_range = CLK_PERIOD * 0.05 -group_path -critical_range c_range -name CLK -to CLK - -/* Operating conditions */ -set_operating_conditions typical

cons_art_umc18.inc Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property