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Rev 114 → Rev 154

/verilog/test.v
0,0 → 1,752
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module test
(
pci_clk_i,
clk_i,
rst_i,
wbm_cyc_o,
wbm_stb_o,
wbm_cab_o,
wbm_we_o,
wbm_adr_o,
wbm_sel_o,
wbm_dat_o,
wbm_dat_i,
wbm_ack_i,
wbm_rty_i,
wbm_err_i,
 
wbs_cyc_i,
wbs_stb_i,
wbs_cab_i,
wbs_we_i,
wbs_adr_i,
wbs_sel_i,
wbs_dat_i,
wbs_dat_o,
wbs_ack_o,
wbs_rty_o,
wbs_err_o,
 
// pci trdy, irdy and irdy enable inputs used to count number of transfers on pci bus
pci_irdy_reg_i,
pci_irdy_en_reg_i,
pci_trdy_reg_i,
pci_ad_reg_i
);
 
input pci_clk_i,
clk_i,
rst_i ;
output wbm_cyc_o,
wbm_stb_o,
wbm_cab_o,
wbm_we_o ;
 
output [31:0] wbm_adr_o ;
output [3:0] wbm_sel_o ;
assign wbm_sel_o = 4'hF ;
output [31:0] wbm_dat_o ;
input [31:0] wbm_dat_i ;
input wbm_ack_i,
wbm_rty_i,
wbm_err_i ;
 
input wbs_cyc_i,
wbs_stb_i,
wbs_cab_i,
wbs_we_i ;
 
input [31:0] wbs_adr_i ;
input [3:0] wbs_sel_i ;
input [31:0] wbs_dat_i ;
output [31:0] wbs_dat_o ;
output wbs_ack_o,
wbs_rty_o,
wbs_err_o ;
 
input pci_irdy_reg_i,
pci_irdy_en_reg_i,
pci_trdy_reg_i ;
 
input [31:0] pci_ad_reg_i ;
 
wire sel_registers = wbs_adr_i[12] ;
wire sel_rams = ~wbs_adr_i[12] ;
 
wire wbs_write = wbs_cyc_i & wbs_stb_i & wbs_we_i ;
 
wire wbs_ram0_255_we = wbs_write & sel_rams & (wbs_adr_i[11:10] == 2'b00) ;
wire wbs_ram256_511_we = wbs_write & sel_rams & (wbs_adr_i[11:10] == 2'b01) ;
wire wbs_ram512_767_we = wbs_write & sel_rams & (wbs_adr_i[11:10] == 3'b10) ;
wire wbs_ram768_1023_we = wbs_write & sel_rams & (wbs_adr_i[11:10] == 3'b11) ;
 
reg sel_master_transaction_size,
sel_master_transaction_count,
sel_master_opcode,
sel_master_base,
sel_target_burst_transaction_count,
sel_target_test_size,
sel_target_test_start_adr,
sel_target_test_start_dat,
sel_target_test_error_detected,
sel_master_num_of_wb_transfers,
sel_master_num_of_pci_transfers,
sel_master_test_start_dat,
sel_master_test_size,
sel_master_dat_err_detected ;
 
wire [31:0] wbs_ram0_255_o ;
wire [31:0] wbs_ram256_511_o ;
wire [31:0] wbs_ram512_767_o ;
wire [31:0] wbs_ram768_1023_o ;
 
wire wbm_write = wbm_cyc_o & wbm_stb_o & wbm_we_o ;
wire wbm_read = wbm_cyc_o & wbm_stb_o & ~wbm_we_o ;
 
wire wbm_ram0_255_we = wbm_ack_i & wbm_read & (wbm_adr_o[11:10] == 2'b00) ;
wire wbm_ram256_511_we = wbm_ack_i & wbm_read & (wbm_adr_o[11:10] == 2'b01) ;
wire wbm_ram512_767_we = wbm_ack_i & wbm_read & (wbm_adr_o[11:10] == 2'b10) ;
wire wbm_ram768_1023_we = wbm_ack_i & wbm_read & (wbm_adr_o[11:10] == 2'b11) ;
 
wire [31:0] wbm_ram0_255_o ;
wire [31:0] wbm_ram256_511_o ;
wire [31:0] wbm_ram512_767_o ;
wire [31:0] wbm_ram768_1023_o ;
 
reg [31:0] wbm_dat_o ;
 
always@(wbm_adr_o or wbm_ram0_255_o or wbm_ram256_511_o or wbm_ram512_767_o or wbm_ram768_1023_o)
begin
case (wbm_adr_o[11:10])
2'b00:
begin
wbm_dat_o = wbm_ram0_255_o ;
end
2'b01:
begin
wbm_dat_o = wbm_ram256_511_o ;
end
2'b10:
begin
wbm_dat_o = wbm_ram512_767_o ;
end
2'b11:
begin
wbm_dat_o = wbm_ram768_1023_o ;
end
endcase
end
 
reg [10:0] master_transaction_size ;
reg [10:0] master_transaction_count ;
reg master_opcode ;
reg [31:0] master_base ;
reg [31:0] master_base_next ;
reg [10:0] target_test_size ;
reg [31:0] target_test_start_adr ;
reg [31:0] target_test_expect_adr ;
reg [31:0] target_test_start_dat ;
reg [31:0] target_test_expect_dat ;
reg target_test_adr_error_detected,
target_test_dat_error_detected ;
reg [31:0] master_num_of_wb_transfers,
master_num_of_pci_transfers ;
reg [31:0] master_test_start_dat ;
reg [31:0] pci_clk_master_test_expect_dat ;
reg [20:0] master_test_size ;
reg [20:0] pci_clk_master_test_size ;
reg pci_clk_master_test_done,
wb_clk_master_test_done_sync,
wb_clk_master_test_done,
wb_clk_master_test_start,
pci_clk_master_test_start_sync,
pci_clk_master_test_start,
pci_clk_master_test_started,
wb_clk_master_test_started_sync,
wb_clk_master_test_started,
master_dat_err_detected ;
 
always@(posedge pci_clk_i or posedge rst_i)
begin
if (rst_i)
begin
pci_clk_master_test_expect_dat <= 0 ;
pci_clk_master_test_size <= 0 ;
pci_clk_master_test_done <= 1 ;
pci_clk_master_test_start_sync <= 0 ;
pci_clk_master_test_start <= 0 ;
pci_clk_master_test_started <= 0 ;
master_dat_err_detected <= 0 ;
end
else
begin
// sync flop always samples the data
pci_clk_master_test_start_sync <= wb_clk_master_test_start ;
if (pci_clk_master_test_size == 0)
begin
// load test start_flop only when test size is zero
pci_clk_master_test_start <= pci_clk_master_test_start_sync ;
pci_clk_master_test_started <= 0 ;
pci_clk_master_test_done <= 1 ;
if (pci_clk_master_test_start)
begin
pci_clk_master_test_size <= master_test_size ;
pci_clk_master_test_expect_dat <= master_test_start_dat ;
 
// error detected bit is cleared when new test starts
master_dat_err_detected <= 0 ;
end
end
else
begin
pci_clk_master_test_done <= 0 ;
pci_clk_master_test_start <= 0 ;
pci_clk_master_test_started <= 1 ;
if (~(pci_irdy_reg_i | ~pci_irdy_en_reg_i | pci_trdy_reg_i))
begin
pci_clk_master_test_size <= pci_clk_master_test_size - 1'b1 ;
 
if (pci_ad_reg_i != pci_clk_master_test_expect_dat)
master_dat_err_detected <= 1'b1 ;
 
pci_clk_master_test_expect_dat <= {pci_clk_master_test_expect_dat[30:0], pci_clk_master_test_expect_dat[31]} ;
end
end
end
end
 
always@(posedge clk_i or posedge rst_i)
begin
if (rst_i)
begin
wb_clk_master_test_done_sync <= 1'b1 ;
wb_clk_master_test_done <= 1'b1 ;
wb_clk_master_test_started_sync <= 1'b0 ;
wb_clk_master_test_started <= 1'b0 ;
end
else
begin
wb_clk_master_test_done_sync <= pci_clk_master_test_done ;
if (wb_clk_master_test_start)
wb_clk_master_test_done <= 1'b0 ;
else
wb_clk_master_test_done <= wb_clk_master_test_done_sync ;
 
wb_clk_master_test_started_sync <= pci_clk_master_test_started ;
wb_clk_master_test_started <= wb_clk_master_test_started_sync ;
end
end
 
assign wbm_we_o = master_opcode ;
 
reg [10:0] master_current_transaction_size ;
 
reg [10:0] target_burst_transaction_count ;
reg wbs_cyc_i_previous ;
 
reg clr_master_num_of_pci_transfers ;
reg clr_master_num_of_pci_transfers_sync ;
reg wb_clk_clr_master_num_of_pci_transfers ;
 
always@(posedge pci_clk_i or posedge rst_i)
begin
if (rst_i)
begin
master_num_of_pci_transfers <= 0 ;
end
else if (clr_master_num_of_pci_transfers)
begin
master_num_of_pci_transfers <= 0 ;
end
else if (~(pci_irdy_reg_i | ~pci_irdy_en_reg_i | pci_trdy_reg_i))
begin
master_num_of_pci_transfers <= master_num_of_pci_transfers + 1'b1 ;
end
 
if (rst_i)
begin
clr_master_num_of_pci_transfers <= 1'b1 ;
clr_master_num_of_pci_transfers_sync <= 1'b1 ;
end
else
begin
clr_master_num_of_pci_transfers <= clr_master_num_of_pci_transfers_sync ;
clr_master_num_of_pci_transfers_sync <= wb_clk_clr_master_num_of_pci_transfers ;
end
end
 
always@(posedge clk_i or posedge rst_i)
begin
if (rst_i)
begin
master_transaction_size <= 0 ;
master_transaction_count <= 0 ;
master_opcode <= 0 ;
master_base <= 0 ;
master_base_next <= 4 ;
target_burst_transaction_count <= 0 ;
wbs_cyc_i_previous <= 0 ;
target_test_size <= 0 ;
target_test_start_adr <= 0 ;
target_test_start_dat <= 0 ;
target_test_adr_error_detected <= 0 ;
target_test_dat_error_detected <= 0 ;
target_test_expect_adr <= 0 ;
target_test_expect_dat <= 0 ;
master_num_of_wb_transfers <= 0 ;
wb_clk_clr_master_num_of_pci_transfers <= 1'b1 ;
master_test_size <= 0 ;
master_test_start_dat <= 0 ;
wb_clk_master_test_start <= 0 ;
end
else
begin
if (sel_master_transaction_size & wbs_write & sel_registers)
// write new value to transaction size register
master_transaction_size <= wbs_dat_i[10:0] ;
 
if (sel_master_transaction_count & wbs_write & sel_registers)
// write new value to transaction count register
master_transaction_count <= wbs_dat_i[10:0] ;
else if (wbm_cyc_o & wbm_stb_o & wbm_ack_i & (master_current_transaction_size == 11'h1))
// decrement the transaction count when ack is received and transaction size is 1
master_transaction_count <= master_transaction_count - 1'b1 ;
 
if (sel_master_opcode & wbs_write & sel_registers)
// master opcode write
master_opcode <= wbs_dat_i[0] ;
 
if (sel_master_base & wbs_write & sel_registers)
// master base address write
master_base <= {wbs_dat_i[31:2], 2'b00} ;
 
if (sel_target_burst_transaction_count & wbs_write & sel_registers)
target_burst_transaction_count <= 0 ;
else if (wbs_cyc_i & ~wbs_cyc_i_previous & wbs_cab_i)
target_burst_transaction_count <= target_burst_transaction_count + 1 ;
 
if (sel_target_test_size & wbs_write & sel_registers)
target_test_size <= wbs_dat_i[10:0] ;
else if ((target_test_size != 0) & wbs_cyc_i & wbs_stb_i & wbs_we_i & wbs_ack_o & ~sel_registers)
begin
target_test_size <= target_test_size - 1'b1 ;
end
 
if (sel_target_test_start_adr & wbs_write & sel_registers)
target_test_start_adr <= wbs_dat_i ;
 
if (sel_target_test_start_dat & wbs_write & sel_registers)
target_test_start_dat <= wbs_dat_i ;
 
if (sel_target_test_error_detected & wbs_write & sel_registers)
begin
target_test_adr_error_detected <= 1'b0 ;
target_test_dat_error_detected <= 1'b0 ;
end
else if ((target_test_size != 0) & wbs_cyc_i & wbs_stb_i & wbs_we_i & wbs_ack_o & ~sel_registers)
begin
target_test_adr_error_detected <= (target_test_expect_adr != wbs_adr_i) | target_test_adr_error_detected ;
target_test_dat_error_detected <= (target_test_expect_dat != wbs_dat_i) | target_test_dat_error_detected ;
end
 
if (target_test_size == 0)
begin
target_test_expect_adr <= target_test_start_adr ;
target_test_expect_dat <= target_test_start_dat ;
end
else if (wbs_cyc_i & wbs_stb_i & wbs_we_i & wbs_ack_o & ~sel_registers)
begin
target_test_expect_adr <= target_test_expect_adr + 'd4 ;
target_test_expect_dat <= {target_test_expect_dat[30:0], target_test_expect_dat[31]} ;
end
 
if (sel_master_num_of_wb_transfers & wbs_write & sel_registers)
begin
master_num_of_wb_transfers <= 0 ;
wb_clk_clr_master_num_of_pci_transfers <= 1'b1 ;
end
else if (wbm_cyc_o & wbm_stb_o & wbm_ack_i)
begin
wb_clk_clr_master_num_of_pci_transfers <= 1'b0 ;
master_num_of_wb_transfers <= master_num_of_wb_transfers + 1'b1 ;
end
 
if (wb_clk_master_test_done & wbs_write & sel_master_test_size & sel_registers & ~wb_clk_master_test_start)
begin
master_test_size <= wbs_dat_i[20:0] ;
wb_clk_master_test_start <= 1'b1 ;
end
else
begin
if (wb_clk_master_test_started & !wb_clk_master_test_done)
wb_clk_master_test_start <= 1'b0 ;
end
 
if (sel_master_test_start_dat & wbs_write & sel_registers)
master_test_start_dat <= wbs_dat_i ;
 
master_base_next <= master_base + 4 ;
 
wbs_cyc_i_previous <= wbs_cyc_i ;
end
end
 
reg [31:0] register_output ;
reg [31:0] ram_output ;
 
always@
(
wbs_adr_i or
master_transaction_size or
master_transaction_count or
master_opcode or
master_base or
target_burst_transaction_count or
target_test_size or
target_test_start_adr or
target_test_start_dat or
target_test_adr_error_detected or
target_test_dat_error_detected or
master_num_of_wb_transfers or
master_num_of_pci_transfers or
master_test_size or
master_test_start_dat or
master_dat_err_detected
)
begin
sel_master_transaction_size = 1'b0 ;
sel_master_transaction_count = 1'b0 ;
sel_master_opcode = 1'b0 ;
sel_master_base = 1'b0 ;
sel_target_burst_transaction_count = 1'b0 ;
sel_target_test_size = 1'b0 ;
sel_target_test_start_adr = 1'b0 ;
sel_target_test_start_dat = 1'b0 ;
sel_target_test_error_detected = 1'b0 ;
sel_master_num_of_wb_transfers = 1'b0 ;
sel_master_test_size = 1'b0 ;
sel_master_test_start_dat = 1'b0 ;
sel_master_dat_err_detected = 1'b0 ;
register_output = 0 ;
 
case (wbs_adr_i[5:2])
4'b0000:
begin
sel_master_transaction_size = 1'b1 ;
register_output = {21'h0, master_transaction_size} ;
end
4'b0001:
begin
sel_master_transaction_count = 1'b1 ;
register_output = {21'h0, master_transaction_count} ;
end
4'b0010:
begin
sel_master_opcode = 1'b1 ;
register_output = {31'h0, master_opcode} ;
end
4'b0011:
begin
sel_master_base = 1'b1 ;
register_output = master_base ;
end
4'b0100:
begin
sel_target_burst_transaction_count = 1'b1 ;
register_output = target_burst_transaction_count ;
end
4'b0101:
begin
sel_target_test_size = 1'b1 ;
register_output = {20'h0, target_test_size} ;
end
4'b0110:
begin
sel_target_test_start_adr = 1'b1 ;
register_output = target_test_start_adr ;
end
4'b0111:
begin
sel_target_test_start_dat = 1'b1 ;
register_output = target_test_start_dat ;
end
4'b1000:
begin
sel_target_test_error_detected = 1'b1 ;
register_output = {30'h0, target_test_adr_error_detected, target_test_dat_error_detected} ;
end
4'b1001:
begin
sel_master_num_of_wb_transfers = 1'b1 ;
register_output = master_num_of_wb_transfers ;
end
4'b1010:
begin
sel_master_num_of_pci_transfers = 1'b1 ;
register_output = master_num_of_pci_transfers ;
end
4'b1011:
begin
sel_master_test_size = 1'b1 ;
register_output = {11'h0, master_test_size} ;
end
4'b1100:
begin
sel_master_test_start_dat = 1'b1 ;
register_output = master_test_start_dat ;
end
4'b1101:
begin
sel_master_dat_err_detected = 1'b1 ;
register_output = {31'h0, master_dat_err_detected} ;
end
endcase
end
 
always@(wbs_adr_i or wbs_ram0_255_o or wbs_ram256_511_o or wbs_ram512_767_o or wbs_ram768_1023_o)
begin
case (wbs_adr_i[11:10])
2'b00:ram_output = wbs_ram0_255_o ;
2'b01:ram_output = wbs_ram256_511_o ;
2'b10:ram_output = wbs_ram512_767_o ;
2'b11:ram_output = wbs_ram768_1023_o ;
endcase
end
 
assign wbs_dat_o = sel_registers ? register_output : ram_output ;
 
reg delayed_ack_for_reads ;
 
always@(posedge clk_i or posedge rst_i)
begin
if (rst_i)
delayed_ack_for_reads <= 1'b0 ;
else if (delayed_ack_for_reads)
delayed_ack_for_reads <= 1'b0 ;
else
delayed_ack_for_reads <= wbs_cyc_i & wbs_stb_i & (~wbs_we_i) ;
end
 
assign wbs_ack_o = wbs_we_i ? (wbs_cyc_i & wbs_stb_i) : delayed_ack_for_reads ;
 
assign wbs_err_o = 1'b0 ;
assign wbs_rty_o = 1'b0 ;
 
reg wbm_cyc_o, wbm_cab_o, wbm_stb_o;
reg [31:0] wbm_adr_o ;
reg [31:0] wbm_next_adr_o ;
 
wire wbm_end_cycle = wbm_cyc_o & wbm_stb_o & wbm_ack_i & (master_current_transaction_size == 11'h1) ;
wire wbm_start_cycle = (master_transaction_size != 11'h0) & (master_transaction_count != 11'h0) & ~wbm_cyc_o ;
 
always@(posedge clk_i or posedge rst_i)
begin
if (rst_i)
begin
wbm_cyc_o <= 1'b0 ;
wbm_cab_o <= 1'b0 ;
wbm_stb_o <= 1'b0 ;
wbm_adr_o <= 32'h0 ;
master_current_transaction_size <= 11'h0 ;
wbm_next_adr_o <= 32'h4 ;
end
else
begin
if (master_transaction_count == 11'h0)
begin
wbm_adr_o <= master_base ;
wbm_next_adr_o <= master_base_next ;
end
else if (wbm_cyc_o & wbm_stb_o & wbm_ack_i)
begin
wbm_adr_o <= wbm_next_adr_o ;
wbm_next_adr_o[31:2] <= wbm_next_adr_o[31:2] + 1'b1 ;
end
if (wbm_start_cycle)
begin
wbm_cyc_o <= 1'b1 ;
wbm_cab_o <= (master_transaction_size != 11'h1) ;
wbm_stb_o <= 1'b1 ;
master_current_transaction_size <= master_transaction_size ;
end
else if (wbm_cyc_o)
begin
if (wbm_end_cycle)
begin
wbm_cyc_o <= 1'b0 ;
wbm_stb_o <= 1'b0 ;
wbm_cab_o <= 1'b0 ;
end
else
begin
if (wbm_stb_o & wbm_ack_i)
begin
master_current_transaction_size <= master_current_transaction_size - 1'b1 ;
end
end
end
end
end
 
wire [7:0] master_ram_adr = (wbm_we_o & wbm_ack_i) ? wbm_next_adr_o[9:2] : wbm_adr_o[9:2] ;
 
RAMB4_S16_S16 ramb4_s16_s16_00
(
.CLKA(clk_i),
.RSTA(rst_i),
.ADDRA(wbs_adr_i[9:2]),
.DIA(wbs_dat_i[31:16]),
.ENA(1'b1),
.WEA(wbs_ram0_255_we),
.DOA(wbs_ram0_255_o[31:16]),
 
.CLKB(clk_i),
.RSTB(rst_i),
.ADDRB(master_ram_adr),
.DIB(wbm_dat_i[31:16]),
.ENB(1'b1),
.WEB(wbm_ram0_255_we),
.DOB(wbm_ram0_255_o[31:16])
);
 
RAMB4_S16_S16 ramb4_s16_s16_01
(
.CLKA(clk_i),
.RSTA(rst_i),
.ADDRA(wbs_adr_i[9:2]),
.DIA(wbs_dat_i[15:0]),
.ENA(1'b1),
.WEA(wbs_ram0_255_we),
.DOA(wbs_ram0_255_o[15:0]),
 
.CLKB(clk_i),
.RSTB(rst_i),
.ADDRB(master_ram_adr),
.DIB(wbm_dat_i[15:0]),
.ENB(1'b1),
.WEB(wbm_ram0_255_we),
.DOB(wbm_ram0_255_o[15:0])
);
 
RAMB4_S16_S16 ramb4_s16_s16_10
(
.CLKA(clk_i),
.RSTA(rst_i),
.ADDRA(wbs_adr_i[9:2]),
.DIA(wbs_dat_i[31:16]),
.ENA(1'b1),
.WEA(wbs_ram256_511_we),
.DOA(wbs_ram256_511_o[31:16]),
 
.CLKB(clk_i),
.RSTB(rst_i),
.ADDRB(master_ram_adr),
.DIB(wbm_dat_i[31:16]),
.ENB(1'b1),
.WEB(wbm_ram256_511_we),
.DOB(wbm_ram256_511_o[31:16])
);
 
RAMB4_S16_S16 ramb4_s16_s16_11
(
.CLKA(clk_i),
.RSTA(rst_i),
.ADDRA(wbs_adr_i[9:2]),
.DIA(wbs_dat_i[15:0]),
.ENA(1'b1),
.WEA(wbs_ram256_511_we),
.DOA(wbs_ram256_511_o[15:0]),
 
.CLKB(clk_i),
.RSTB(rst_i),
.ADDRB(master_ram_adr),
.DIB(wbm_dat_i[15:0]),
.ENB(1'b1),
.WEB(wbm_ram256_511_we),
.DOB(wbm_ram256_511_o[15:0])
);
 
RAMB4_S16_S16 ramb4_s16_s16_20
(
.CLKA(clk_i),
.RSTA(rst_i),
.ADDRA(wbs_adr_i[9:2]),
.DIA(wbs_dat_i[31:16]),
.ENA(1'b1),
.WEA(wbs_ram512_767_we),
.DOA(wbs_ram512_767_o[31:16]),
 
.CLKB(clk_i),
.RSTB(rst_i),
.ADDRB(master_ram_adr),
.DIB(wbm_dat_i[31:16]),
.ENB(1'b1),
.WEB(wbm_ram512_767_we),
.DOB(wbm_ram512_767_o[31:16])
);
 
RAMB4_S16_S16 ramb4_s16_s16_21
(
.CLKA(clk_i),
.RSTA(rst_i),
.ADDRA(wbs_adr_i[9:2]),
.DIA(wbs_dat_i[15:0]),
.ENA(1'b1),
.WEA(wbs_ram512_767_we),
.DOA(wbs_ram512_767_o[15:0]),
 
.CLKB(clk_i),
.RSTB(rst_i),
.ADDRB(master_ram_adr),
.DIB(wbm_dat_i[15:0]),
.ENB(1'b1),
.WEB(wbm_ram512_767_we),
.DOB(wbm_ram512_767_o[15:0])
);
 
RAMB4_S16_S16 ramb4_s16_s16_30
(
.CLKA(clk_i),
.RSTA(rst_i),
.ADDRA(wbs_adr_i[9:2]),
.DIA(wbs_dat_i[31:16]),
.ENA(1'b1),
.WEA(wbs_ram768_1023_we),
.DOA(wbs_ram768_1023_o[31:16]),
 
.CLKB(clk_i),
.RSTB(rst_i),
.ADDRB(master_ram_adr),
.DIB(wbm_dat_i[31:16]),
.ENB(1'b1),
.WEB(wbm_ram768_1023_we),
.DOB(wbm_ram768_1023_o[31:16])
);
 
RAMB4_S16_S16 ramb4_s16_s16_31
(
.CLKA(clk_i),
.RSTA(rst_i),
.ADDRA(wbs_adr_i[9:2]),
.DIA(wbs_dat_i[15:0]),
.ENA(1'b1),
.WEA(wbs_ram768_1023_we),
.DOA(wbs_ram768_1023_o[15:0]),
 
.CLKB(clk_i),
.RSTB(rst_i),
.ADDRB(master_ram_adr),
.DIB(wbm_dat_i[15:0]),
.ENB(1'b1),
.WEB(wbm_ram768_1023_we),
.DOB(wbm_ram768_1023_o[15:0])
);
 
endmodule // test
/verilog/pci_test_top_2clks.v
0,0 → 1,515
module pci_test_top
(
pci_clk_pad_i,
pci_rst_pad_i,
clk_pad_i,
 
pci_req_pad_o,
pci_gnt_pad_i,
pci_idsel_pad_i,
 
pci_ad0_pad_io,
pci_ad1_pad_io,
pci_ad2_pad_io,
pci_ad3_pad_io,
pci_ad4_pad_io,
pci_ad5_pad_io,
pci_ad6_pad_io,
pci_ad7_pad_io,
pci_ad8_pad_io,
pci_ad9_pad_io,
pci_ad10_pad_io,
pci_ad11_pad_io,
pci_ad12_pad_io,
pci_ad13_pad_io,
pci_ad14_pad_io,
pci_ad15_pad_io,
pci_ad16_pad_io,
pci_ad17_pad_io,
pci_ad18_pad_io,
pci_ad19_pad_io,
pci_ad20_pad_io,
pci_ad21_pad_io,
pci_ad22_pad_io,
pci_ad23_pad_io,
pci_ad24_pad_io,
pci_ad25_pad_io,
pci_ad26_pad_io,
pci_ad27_pad_io,
pci_ad28_pad_io,
pci_ad29_pad_io,
pci_ad30_pad_io,
pci_ad31_pad_io,
 
pci_cbe0_pad_io,
pci_cbe1_pad_io,
pci_cbe2_pad_io,
pci_cbe3_pad_io,
 
pci_frame_pad_io,
pci_irdy_pad_io,
pci_devsel_pad_io,
pci_trdy_pad_io,
pci_stop_pad_io,
pci_par_pad_io,
pci_perr_pad_io,
pci_serr_pad_o
);
 
// input/output inout declarations
input pci_clk_pad_i,
pci_rst_pad_i,
clk_pad_i ;
 
output pci_req_pad_o, pci_serr_pad_o ;
input pci_gnt_pad_i,
pci_idsel_pad_i ;
 
inout pci_frame_pad_io,
pci_irdy_pad_io,
pci_devsel_pad_io,
pci_trdy_pad_io,
pci_stop_pad_io,
pci_par_pad_io,
pci_perr_pad_io,
pci_ad0_pad_io,
pci_ad1_pad_io,
pci_ad2_pad_io,
pci_ad3_pad_io,
pci_ad4_pad_io,
pci_ad5_pad_io,
pci_ad6_pad_io,
pci_ad7_pad_io,
pci_ad8_pad_io,
pci_ad9_pad_io,
pci_ad10_pad_io,
pci_ad11_pad_io,
pci_ad12_pad_io,
pci_ad13_pad_io,
pci_ad14_pad_io,
pci_ad15_pad_io,
pci_ad16_pad_io,
pci_ad17_pad_io,
pci_ad18_pad_io,
pci_ad19_pad_io,
pci_ad20_pad_io,
pci_ad21_pad_io,
pci_ad22_pad_io,
pci_ad23_pad_io,
pci_ad24_pad_io,
pci_ad25_pad_io,
pci_ad26_pad_io,
pci_ad27_pad_io,
pci_ad28_pad_io,
pci_ad29_pad_io,
pci_ad30_pad_io,
pci_ad31_pad_io,
pci_cbe0_pad_io,
pci_cbe1_pad_io,
pci_cbe2_pad_io,
pci_cbe3_pad_io ;
 
// wires for test master to pci slave connections
wire wbm_test_wbs_pci_cyc,
wbm_test_wbs_pci_stb,
wbm_test_wbs_pci_cab,
wbm_test_wbs_pci_we,
wbs_pci_wbm_test_ack ;
 
wire [31:0] wbm_test_wbs_pci_adr,
wbm_test_wbs_pci_dat,
wbs_pci_wbm_test_dat ;
 
wire [3:0] wbm_test_wbs_pci_sel ;
 
// wires for test slave to pci master connections
wire wbm_pci_wbs_test_cyc,
wbm_pci_wbs_test_stb,
wbm_pci_wbs_test_cab,
wbm_pci_wbs_test_we,
wbs_test_wbm_pci_ack ;
 
wire [31:0] wbm_pci_wbs_test_adr,
wbm_pci_wbs_test_dat,
wbs_test_wbm_pci_dat ;
 
wire [3:0] wbm_pci_wbs_test_sel ;
 
wire wb_rst ;
 
wire wb_clk ;
wire wb_clk_unbuf ;
 
wire clk0 ;
wire clk0_buf ;
wire clk_i_buf ;
 
CLKDLL i_clkdll
(
.CLKIN ( clk_i_buf ),
.CLKFB ( clk0_buf ),
.RST ( 1'b0 ),
.CLK2X ( ),
.CLK0 ( clk0 ),
.CLK90 ( ),
.CLK180 ( ),
.CLK270 ( ),
.CLKDV ( wb_clk_unbuf ),
.LOCKED ( )
);
 
BUFG i_bufg_clk0
(
.I( clk0 ),
.O( clk0_buf )
) ;
 
BUFG i_bufg_wb_clk
(
.I( wb_clk_unbuf ),
.O( wb_clk )
) ;
 
IBUFG i_ibufg_clk_pad_i
(
.I( clk_pad_i ),
.O( clk_i_buf )
) ;
 
// prevent concurent accesses through pci bridge master and slave interfaces
reg test_wbs_cyc ;
reg pci_wbs_cyc ;
 
always@(posedge wb_clk or posedge wb_rst)
begin
if (wb_rst)
begin
test_wbs_cyc <= 1'b0 ;
pci_wbs_cyc <= 1'b0 ;
end
else
begin
if (~pci_wbs_cyc & ~test_wbs_cyc)
begin
// currently no cyc signal is asserted - the pci bridge wb master will have the priority here, so check if it has cycle asserted!
if (wbm_pci_wbs_test_cyc)
test_wbs_cyc <= 1'b1 ;
else // no cycle is asserted and pci wb master is not starting the transaction - test wb master can start
pci_wbs_cyc <= wbm_test_wbs_pci_cyc ;
end
else
begin
// at least one of the cycles is asserted - wait for transaction to finish
if (test_wbs_cyc)
test_wbs_cyc <= wbm_pci_wbs_test_cyc ;
 
if (pci_wbs_cyc)
pci_wbs_cyc <= wbm_test_wbs_pci_cyc ;
end
end
end
 
wire pci_irdy_out,
pci_irdy_en,
pci_trdy_reg ;
 
reg pci_irdy_reg ;
reg pci_irdy_en_reg ;
reg [31:0] pci_ad_reg ;
wire [31:0] pci_ad_bckp ;
 
always@(posedge pci_clk_pad_i or negedge pci_rst_pad_i)
begin
if (~pci_rst_pad_i)
begin
pci_irdy_reg <= 1'b1 ;
pci_irdy_en_reg <= 1'b0 ;
pci_ad_reg <= 0 ;
end
else
begin
pci_irdy_reg <= pci_irdy_out ;
pci_irdy_en_reg <= pci_irdy_en ;
pci_ad_reg <= pci_ad_bckp ;
end
end
 
test i_test
(
.pci_clk_i (pci_clk_pad_i),
.clk_i (wb_clk),
.rst_i (wb_rst),
 
.wbm_cyc_o (wbm_test_wbs_pci_cyc),
.wbm_stb_o (wbm_test_wbs_pci_stb),
.wbm_cab_o (wbm_test_wbs_pci_cab),
.wbm_we_o (wbm_test_wbs_pci_we),
.wbm_adr_o (wbm_test_wbs_pci_adr),
.wbm_sel_o (wbm_test_wbs_pci_sel),
.wbm_dat_o (wbm_test_wbs_pci_dat),
.wbm_dat_i (wbs_pci_wbm_test_dat),
.wbm_ack_i (wbs_pci_wbm_test_ack),
.wbm_rty_i (1'b0),
.wbm_err_i (1'b0),
 
.wbs_cyc_i (test_wbs_cyc),
.wbs_stb_i (wbm_pci_wbs_test_stb),
.wbs_cab_i (wbm_pci_wbs_test_cab),
.wbs_we_i (wbm_pci_wbs_test_we),
.wbs_adr_i (wbm_pci_wbs_test_adr),
.wbs_sel_i (wbm_pci_wbs_test_sel),
.wbs_dat_i (wbm_pci_wbs_test_dat),
.wbs_dat_o (wbs_test_wbm_pci_dat),
.wbs_ack_o (wbs_test_wbm_pci_ack),
.wbs_rty_o (),
.wbs_err_o (),
 
.pci_irdy_reg_i (pci_irdy_reg),
.pci_irdy_en_reg_i (pci_irdy_en_reg),
.pci_trdy_reg_i (pci_trdy_reg),
.pci_ad_reg_i (pci_ad_reg)
);
 
wire pci_req_o,
pci_req_oe,
pci_frame_i,
pci_frame_o,
pci_frame_oe,
pci_irdy_oe,
pci_devsel_oe,
pci_trdy_oe,
pci_stop_oe,
pci_irdy_i,
pci_irdy_o,
pci_devsel_i,
pci_devsel_o,
pci_trdy_i,
pci_trdy_o,
pci_stop_i,
pci_stop_o,
pci_par_i,
pci_par_o,
pci_par_oe,
pci_perr_i,
pci_perr_o,
pci_perr_oe,
pci_serr_o,
pci_serr_oe
;
 
wire [31:0] pci_ad_oe,
pci_ad_i,
pci_ad_o ;
 
wire [3:0] pci_cbe_oe,
pci_cbe_i,
pci_cbe_o ;
bufif0 ad_buffer00 (pci_ad0_pad_io , pci_ad_o[0] , pci_ad_oe[0] ) ;
bufif0 ad_buffer01 (pci_ad1_pad_io , pci_ad_o[1] , pci_ad_oe[1] ) ;
bufif0 ad_buffer02 (pci_ad2_pad_io , pci_ad_o[2] , pci_ad_oe[2] ) ;
bufif0 ad_buffer03 (pci_ad3_pad_io , pci_ad_o[3] , pci_ad_oe[3] ) ;
bufif0 ad_buffer04 (pci_ad4_pad_io , pci_ad_o[4] , pci_ad_oe[4] ) ;
bufif0 ad_buffer05 (pci_ad5_pad_io , pci_ad_o[5] , pci_ad_oe[5] ) ;
bufif0 ad_buffer06 (pci_ad6_pad_io , pci_ad_o[6] , pci_ad_oe[6] ) ;
bufif0 ad_buffer07 (pci_ad7_pad_io , pci_ad_o[7] , pci_ad_oe[7] ) ;
bufif0 ad_buffer08 (pci_ad8_pad_io , pci_ad_o[8] , pci_ad_oe[8] ) ;
bufif0 ad_buffer09 (pci_ad9_pad_io , pci_ad_o[9] , pci_ad_oe[9] ) ;
bufif0 ad_buffer10 (pci_ad10_pad_io, pci_ad_o[10], pci_ad_oe[10]) ;
bufif0 ad_buffer11 (pci_ad11_pad_io, pci_ad_o[11], pci_ad_oe[11]) ;
bufif0 ad_buffer12 (pci_ad12_pad_io, pci_ad_o[12], pci_ad_oe[12]) ;
bufif0 ad_buffer13 (pci_ad13_pad_io, pci_ad_o[13], pci_ad_oe[13]) ;
bufif0 ad_buffer14 (pci_ad14_pad_io, pci_ad_o[14], pci_ad_oe[14]) ;
bufif0 ad_buffer15 (pci_ad15_pad_io, pci_ad_o[15], pci_ad_oe[15]) ;
bufif0 ad_buffer16 (pci_ad16_pad_io, pci_ad_o[16], pci_ad_oe[16]) ;
bufif0 ad_buffer17 (pci_ad17_pad_io, pci_ad_o[17], pci_ad_oe[17]) ;
bufif0 ad_buffer18 (pci_ad18_pad_io, pci_ad_o[18], pci_ad_oe[18]) ;
bufif0 ad_buffer19 (pci_ad19_pad_io, pci_ad_o[19], pci_ad_oe[19]) ;
bufif0 ad_buffer20 (pci_ad20_pad_io, pci_ad_o[20], pci_ad_oe[20]) ;
bufif0 ad_buffer21 (pci_ad21_pad_io, pci_ad_o[21], pci_ad_oe[21]) ;
bufif0 ad_buffer22 (pci_ad22_pad_io, pci_ad_o[22], pci_ad_oe[22]) ;
bufif0 ad_buffer23 (pci_ad23_pad_io, pci_ad_o[23], pci_ad_oe[23]) ;
bufif0 ad_buffer24 (pci_ad24_pad_io, pci_ad_o[24], pci_ad_oe[24]) ;
bufif0 ad_buffer25 (pci_ad25_pad_io, pci_ad_o[25], pci_ad_oe[25]) ;
bufif0 ad_buffer26 (pci_ad26_pad_io, pci_ad_o[26], pci_ad_oe[26]) ;
bufif0 ad_buffer27 (pci_ad27_pad_io, pci_ad_o[27], pci_ad_oe[27]) ;
bufif0 ad_buffer28 (pci_ad28_pad_io, pci_ad_o[28], pci_ad_oe[28]) ;
bufif0 ad_buffer29 (pci_ad29_pad_io, pci_ad_o[29], pci_ad_oe[29]) ;
bufif0 ad_buffer30 (pci_ad30_pad_io, pci_ad_o[30], pci_ad_oe[30]) ;
bufif0 ad_buffer31 (pci_ad31_pad_io, pci_ad_o[31], pci_ad_oe[31]) ;
 
bufif0 cbe_buffer0 (pci_cbe0_pad_io, pci_cbe_o[0], pci_cbe_oe[0]) ;
bufif0 cbe_buffer1 (pci_cbe1_pad_io, pci_cbe_o[1], pci_cbe_oe[1]) ;
bufif0 cbe_buffer2 (pci_cbe2_pad_io, pci_cbe_o[2], pci_cbe_oe[2]) ;
bufif0 cbe_buffer3 (pci_cbe3_pad_io, pci_cbe_o[3], pci_cbe_oe[3]) ;
 
assign pci_ad_i = {
pci_ad31_pad_io,
pci_ad30_pad_io,
pci_ad29_pad_io,
pci_ad28_pad_io,
pci_ad27_pad_io,
pci_ad26_pad_io,
pci_ad25_pad_io,
pci_ad24_pad_io,
pci_ad23_pad_io,
pci_ad22_pad_io,
pci_ad21_pad_io,
pci_ad20_pad_io,
pci_ad19_pad_io,
pci_ad18_pad_io,
pci_ad17_pad_io,
pci_ad16_pad_io,
pci_ad15_pad_io,
pci_ad14_pad_io,
pci_ad13_pad_io,
pci_ad12_pad_io,
pci_ad11_pad_io,
pci_ad10_pad_io,
pci_ad9_pad_io,
pci_ad8_pad_io,
pci_ad7_pad_io,
pci_ad6_pad_io,
pci_ad5_pad_io,
pci_ad4_pad_io,
pci_ad3_pad_io,
pci_ad2_pad_io,
pci_ad1_pad_io,
pci_ad0_pad_io
} ;
 
assign pci_cbe_i = {
pci_cbe3_pad_io,
pci_cbe2_pad_io,
pci_cbe1_pad_io,
pci_cbe0_pad_io
} ;
 
bufif0 req_buf (pci_req_pad_o, pci_req_o, pci_req_oe) ;
 
bufif0 frame_buf (pci_frame_pad_io, pci_frame_o, pci_frame_oe) ;
assign pci_frame_i = pci_frame_pad_io ;
 
bufif0 irdy_buf (pci_irdy_pad_io, pci_irdy_o, pci_irdy_oe) ;
assign pci_irdy_i = pci_irdy_pad_io ;
 
bufif0 devsel_buf (pci_devsel_pad_io, pci_devsel_o, pci_devsel_oe) ;
assign pci_devsel_i = pci_devsel_pad_io ;
 
bufif0 trdy_buf (pci_trdy_pad_io, pci_trdy_o, pci_trdy_oe) ;
assign pci_trdy_i = pci_trdy_pad_io ;
 
bufif0 stop_buf (pci_stop_pad_io, pci_stop_o, pci_stop_oe) ;
assign pci_stop_i = pci_stop_pad_io ;
 
bufif0 par_buf (pci_par_pad_io, pci_par_o, pci_par_oe) ;
assign pci_par_i = pci_par_pad_io ;
 
bufif0 perr_buf (pci_perr_pad_io, pci_perr_o, pci_perr_oe) ;
assign pci_perr_i = pci_perr_pad_io ;
 
bufif0 serr_buf (pci_serr_pad_o, pci_serr_o, pci_serr_oe) ;
 
pci_bridge32 i_pci_bridge32
(
// WISHBONE system signals
.wb_clk_i(wb_clk),
.wb_rst_i(1'b0),
.wb_rst_o(wb_rst),
.wb_int_i(1'b0),
.wb_int_o(),
 
// WISHBONE slave interface
.wbs_adr_i(wbm_test_wbs_pci_adr),
.wbs_dat_i(wbm_test_wbs_pci_dat),
.wbs_dat_o(wbs_pci_wbm_test_dat),
.wbs_sel_i(wbm_test_wbs_pci_sel),
.wbs_cyc_i(pci_wbs_cyc),
.wbs_stb_i(wbm_test_wbs_pci_stb),
.wbs_we_i (wbm_test_wbs_pci_we),
.wbs_cab_i(wbm_test_wbs_pci_cab),
.wbs_ack_o(wbs_pci_wbm_test_ack),
.wbs_rty_o(),
.wbs_err_o(),
 
// WISHBONE master interface
.wbm_adr_o(wbm_pci_wbs_test_adr),
.wbm_dat_i(wbs_test_wbm_pci_dat),
.wbm_dat_o(wbm_pci_wbs_test_dat),
.wbm_sel_o(wbm_pci_wbs_test_sel),
.wbm_cyc_o(wbm_pci_wbs_test_cyc),
.wbm_stb_o(wbm_pci_wbs_test_stb),
.wbm_we_o (wbm_pci_wbs_test_we),
.wbm_cab_o(wbm_pci_wbs_test_cab),
.wbm_ack_i(wbs_test_wbm_pci_ack),
.wbm_rty_i(1'b0),
.wbm_err_i(1'b0),
 
// pci interface - system pins
.pci_clk_i (pci_clk_pad_i),
.pci_rst_i (pci_rst_pad_i),
.pci_rst_o (),
.pci_inta_i (1'b1),
.pci_inta_o (),
.pci_rst_oe_o (),
.pci_inta_oe_o (),
 
// arbitration pins
.pci_req_o (pci_req_o),
.pci_req_oe_o (pci_req_oe),
 
.pci_gnt_i (pci_gnt_pad_i),
 
// protocol pins
.pci_frame_i (pci_frame_i),
.pci_frame_o (pci_frame_o),
 
.pci_frame_oe_o (pci_frame_oe),
.pci_irdy_oe_o (pci_irdy_oe),
.pci_devsel_oe_o(pci_devsel_oe),
.pci_trdy_oe_o (pci_trdy_oe),
.pci_stop_oe_o (pci_stop_oe),
.pci_ad_oe_o (pci_ad_oe),
.pci_cbe_oe_o (pci_cbe_oe),
 
.pci_irdy_i (pci_irdy_i),
.pci_irdy_o (pci_irdy_o),
 
.pci_idsel_i (pci_idsel_pad_i),
 
.pci_devsel_i (pci_devsel_i),
.pci_devsel_o (pci_devsel_o),
 
.pci_trdy_i (pci_trdy_i),
.pci_trdy_o (pci_trdy_o),
 
.pci_stop_i (pci_stop_i),
.pci_stop_o (pci_stop_o),
 
// data transfer pins
.pci_ad_i (pci_ad_i),
.pci_ad_o (pci_ad_o),
 
.pci_cbe_i (pci_cbe_i),
.pci_cbe_o (pci_cbe_o),
 
// parity generation and checking pins
.pci_par_i (pci_par_i),
.pci_par_o (pci_par_o),
.pci_par_oe_o (pci_par_oe),
 
.pci_perr_i (pci_perr_i),
.pci_perr_o (pci_perr_o),
.pci_perr_oe_o (pci_perr_oe),
 
// system error pin
.pci_serr_o (pci_serr_o),
.pci_serr_oe_o (pci_serr_oe),
 
// debug
.trdy_reg_o (pci_trdy_reg),
.irdy_o (pci_irdy_out),
.irdy_en_o (pci_irdy_en),
.pci_ad_bckp_o (pci_ad_bckp)
);
endmodule // pci_test_top
/verilog/pci_bridge32.v
0,0 → 1,1452
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "pci_bridge32.v" ////
//// ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc (mihad@opencores.org) ////
//// - Tadej Markovic (tadej@opencores.org) ////
//// ////
//// All additional information is avaliable in the README ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2003/01/27 16:49:31 mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.8 2002/10/21 13:04:33 mihad
// Changed BIST signal names etc..
//
// Revision 1.7 2002/10/18 03:36:37 tadejm
// Changed wrong signal name scanb_sen into scanb_en.
//
// Revision 1.6 2002/10/17 22:51:50 tadejm
// Changed BIST signals for RAMs.
//
// Revision 1.5 2002/10/11 10:09:01 mihad
// Added additional testcase and changed rst name in BIST to trst
//
// Revision 1.4 2002/10/08 17:17:05 mihad
// Added BIST signals for RAMs.
//
// Revision 1.3 2002/02/01 15:25:12 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2 2001/10/05 08:14:28 mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
// New project directory structure
//
//
 
`include "pci_constants.v"
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
// this is top level module of pci bridge core
// it instantiates and connects other lower level modules
// check polarity of PCI output enables in file out_reg.v and change it according to IO interface specification
 
module pci_bridge32
(
// WISHBONE system signals
wb_clk_i,
wb_rst_i,
wb_rst_o,
wb_int_i,
wb_int_o,
 
// WISHBONE slave interface
wbs_adr_i,
wbs_dat_i,
wbs_dat_o,
wbs_sel_i,
wbs_cyc_i,
wbs_stb_i,
wbs_we_i,
wbs_cab_i,
wbs_ack_o,
wbs_rty_o,
wbs_err_o,
 
// WISHBONE master interface
wbm_adr_o,
wbm_dat_i,
wbm_dat_o,
wbm_sel_o,
wbm_cyc_o,
wbm_stb_o,
wbm_we_o,
wbm_cab_o,
wbm_ack_i,
wbm_rty_i,
wbm_err_i,
 
// pci interface - system pins
pci_clk_i,
pci_rst_i,
pci_rst_o,
pci_inta_i,
pci_inta_o,
pci_rst_oe_o,
pci_inta_oe_o,
 
// arbitration pins
pci_req_o,
pci_req_oe_o,
 
pci_gnt_i,
 
// protocol pins
pci_frame_i,
pci_frame_o,
 
pci_frame_oe_o,
pci_irdy_oe_o,
pci_devsel_oe_o,
pci_trdy_oe_o,
pci_stop_oe_o,
pci_ad_oe_o,
pci_cbe_oe_o,
 
pci_irdy_i,
pci_irdy_o,
 
pci_idsel_i,
 
pci_devsel_i,
pci_devsel_o,
 
pci_trdy_i,
pci_trdy_o,
 
pci_stop_i,
pci_stop_o ,
 
// data transfer pins
pci_ad_i,
pci_ad_o,
 
pci_cbe_i,
pci_cbe_o,
 
// parity generation and checking pins
pci_par_i,
pci_par_o,
pci_par_oe_o,
 
pci_perr_i,
pci_perr_o,
pci_perr_oe_o,
 
// system error pin
pci_serr_o,
pci_serr_oe_o,
 
// debug
trdy_reg_o,
irdy_o,
irdy_en_o,
pci_ad_bckp_o
 
`ifdef PCI_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
`endif
);
 
// WISHBONE system signals
input wb_clk_i ;
input wb_rst_i ;
output wb_rst_o ;
input wb_int_i ;
output wb_int_o ;
 
// WISHBONE slave interface
input [31:0] wbs_adr_i ;
input [31:0] wbs_dat_i ;
output [31:0] wbs_dat_o ;
input [3:0] wbs_sel_i ;
input wbs_cyc_i ;
input wbs_stb_i ;
input wbs_we_i ;
input wbs_cab_i ;
output wbs_ack_o ;
output wbs_rty_o ;
output wbs_err_o ;
 
// WISHBONE master interface
output [31:0] wbm_adr_o ;
input [31:0] wbm_dat_i ;
output [31:0] wbm_dat_o ;
output [3:0] wbm_sel_o ;
output wbm_cyc_o ;
output wbm_stb_o ;
output wbm_we_o ;
output wbm_cab_o ;
input wbm_ack_i ;
input wbm_rty_i ;
input wbm_err_i ;
 
// pci interface - system pins
input pci_clk_i ;
input pci_rst_i ;
output pci_rst_o ;
output pci_rst_oe_o ;
 
input pci_inta_i ;
output pci_inta_o ;
output pci_inta_oe_o ;
 
// arbitration pins
output pci_req_o ;
output pci_req_oe_o ;
 
input pci_gnt_i ;
 
// protocol pins
input pci_frame_i ;
output pci_frame_o ;
output pci_frame_oe_o ;
output pci_irdy_oe_o ;
output pci_devsel_oe_o ;
output pci_trdy_oe_o ;
output pci_stop_oe_o ;
output [31:0] pci_ad_oe_o ;
output [3:0] pci_cbe_oe_o ;
 
input pci_irdy_i ;
output pci_irdy_o ;
 
input pci_idsel_i ;
 
input pci_devsel_i ;
output pci_devsel_o ;
 
input pci_trdy_i ;
output pci_trdy_o ;
 
input pci_stop_i ;
output pci_stop_o ;
 
// data transfer pins
input [31:0] pci_ad_i ;
output [31:0] pci_ad_o ;
 
input [3:0] pci_cbe_i ;
output [3:0] pci_cbe_o ;
 
// parity generation and checking pins
input pci_par_i ;
output pci_par_o ;
output pci_par_oe_o ;
 
input pci_perr_i ;
output pci_perr_o ;
output pci_perr_oe_o ;
 
// system error pin
output pci_serr_o ;
output pci_serr_oe_o ;
 
// debug
output trdy_reg_o,
irdy_o,
irdy_en_o ;
 
output [31:0] pci_ad_bckp_o ;
 
`ifdef PCI_BIST
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
 
// internal wires for serial chain connection
wire SO_internal ;
wire SI_internal = SO_internal ;
`endif
 
// declare clock and reset wires
wire pci_clk = pci_clk_i ;
wire wb_clk = wb_clk_i ;
wire reset ; // assigned at pci bridge reset and interrupt logic
 
/*=========================================================================================================
First comes definition of all modules' outputs, so they can be assigned to any other module's input later
in the file, when module is instantiated
=========================================================================================================*/
// PCI BRIDGE RESET AND INTERRUPT LOGIC OUTPUTS
wire pci_reso_reset ;
wire pci_reso_pci_rstn_out ;
wire pci_reso_pci_rstn_en_out ;
wire pci_reso_rst_o ;
wire pci_into_pci_intan_out ;
wire pci_into_pci_intan_en_out ;
wire pci_into_int_o ;
wire pci_into_conf_isr_int_prop_out ;
 
// assign pci bridge reset interrupt logic outputs to top outputs where possible
assign reset = pci_reso_reset ;
assign pci_rst_o = pci_reso_pci_rstn_out ;
assign pci_rst_oe_o = pci_reso_pci_rstn_en_out ;
assign wb_rst_o = pci_reso_rst_o ;
assign pci_inta_o = pci_into_pci_intan_out ;
assign pci_inta_oe_o = pci_into_pci_intan_en_out ;
assign wb_int_o = pci_into_int_o ;
 
// WISHBONE SLAVE UNIT OUTPUTS
wire [31:0] wbu_sdata_out ;
wire wbu_ack_out ;
wire wbu_rty_out ;
wire wbu_err_out ;
wire wbu_pciif_req_out ;
wire wbu_pciif_frame_out ;
wire wbu_pciif_frame_en_out ;
wire wbu_pciif_irdy_out ;
wire wbu_pciif_irdy_en_out ;
wire [31:0] wbu_pciif_ad_out ;
wire wbu_pciif_ad_en_out ;
wire [3:0] wbu_pciif_cbe_out ;
wire wbu_pciif_cbe_en_out ;
wire [31:0] wbu_err_addr_out ;
wire [3:0] wbu_err_bc_out ;
wire wbu_err_signal_out ;
wire wbu_err_source_out ;
wire wbu_err_rty_exp_out ;
wire wbu_tabort_rec_out ;
wire wbu_mabort_rec_out ;
wire [11:0] wbu_conf_offset_out ;
wire wbu_conf_renable_out ;
wire wbu_conf_wenable_out ;
wire [3:0] wbu_conf_be_out ;
wire [31:0] wbu_conf_data_out ;
wire wbu_del_read_comp_pending_out ;
wire wbu_wbw_fifo_empty_out ;
wire wbu_ad_load_out ;
wire wbu_ad_load_on_transfer_out ;
wire wbu_pciif_frame_load_out ;
 
// assign wishbone slave unit's outputs to top outputs where possible
assign wbs_dat_o = wbu_sdata_out ;
assign wbs_ack_o = wbu_ack_out ;
assign wbs_rty_o = wbu_rty_out ;
assign wbs_err_o = wbu_err_out ;
 
// PCI TARGET UNIT OUTPUTS
wire [31:0] pciu_adr_out ;
wire [31:0] pciu_mdata_out ;
wire pciu_cyc_out ;
wire pciu_stb_out ;
wire pciu_we_out ;
wire [3:0] pciu_sel_out ;
wire pciu_cab_out ;
wire pciu_pciif_trdy_out ;
wire pciu_pciif_stop_out ;
wire pciu_pciif_devsel_out ;
wire pciu_pciif_trdy_en_out ;
wire pciu_pciif_stop_en_out ;
wire pciu_pciif_devsel_en_out ;
wire pciu_ad_load_out ;
wire pciu_ad_load_on_transfer_out ;
wire [31:0] pciu_pciif_ad_out ;
wire pciu_pciif_ad_en_out ;
wire pciu_pciif_tabort_set_out ;
wire [31:0] pciu_err_addr_out ;
wire [3:0] pciu_err_bc_out ;
wire [31:0] pciu_err_data_out ;
wire [3:0] pciu_err_be_out ;
wire pciu_err_signal_out ;
wire pciu_err_source_out ;
wire pciu_err_rty_exp_out ;
wire pciu_conf_select_out ;
wire [11:0] pciu_conf_offset_out ;
wire pciu_conf_renable_out ;
wire pciu_conf_wenable_out ;
wire [3:0] pciu_conf_be_out ;
wire [31:0] pciu_conf_data_out ;
wire pciu_pci_drcomp_pending_out ;
wire pciu_pciw_fifo_empty_out ;
 
// assign pci target unit's outputs to top outputs where possible
assign wbm_adr_o = pciu_adr_out ;
assign wbm_dat_o = pciu_mdata_out ;
assign wbm_cyc_o = pciu_cyc_out ;
assign wbm_stb_o = pciu_stb_out ;
assign wbm_we_o = pciu_we_out ;
assign wbm_sel_o = pciu_sel_out ;
assign wbm_cab_o = pciu_cab_out ;
 
// CONFIGURATION SPACE OUTPUTS
wire [31:0] conf_w_data_out ;
wire [31:0] conf_r_data_out ;
wire conf_serr_enable_out ;
wire conf_perr_response_out ;
wire conf_pci_master_enable_out ;
wire conf_mem_space_enable_out ;
wire conf_io_space_enable_out ;
wire [7:0] conf_cache_line_size_to_pci_out ;
wire [7:0] conf_cache_line_size_to_wb_out ;
wire conf_cache_lsize_not_zero_to_wb_out ;
wire [7:0] conf_latency_tim_out ;
 
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ba0_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ba1_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ba2_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ba3_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ba4_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ba5_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ta0_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ta1_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ta2_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ta3_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ta4_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_ta5_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_am0_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_am1_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_am2_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_am3_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_am4_out ;
wire [19:(20 - `PCI_NUM_OF_DEC_ADDR_LINES)] conf_pci_am5_out ;
 
wire conf_pci_mem_io0_out ;
wire conf_pci_mem_io1_out ;
wire conf_pci_mem_io2_out ;
wire conf_pci_mem_io3_out ;
wire conf_pci_mem_io4_out ;
wire conf_pci_mem_io5_out ;
 
wire [1:0] conf_pci_img_ctrl0_out ;
wire [1:0] conf_pci_img_ctrl1_out ;
wire [1:0] conf_pci_img_ctrl2_out ;
wire [1:0] conf_pci_img_ctrl3_out ;
wire [1:0] conf_pci_img_ctrl4_out ;
wire [1:0] conf_pci_img_ctrl5_out ;
 
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba0_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba1_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba2_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba3_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba4_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba5_out ;
 
wire conf_wb_mem_io0_out ;
wire conf_wb_mem_io1_out ;
wire conf_wb_mem_io2_out ;
wire conf_wb_mem_io3_out ;
wire conf_wb_mem_io4_out ;
wire conf_wb_mem_io5_out ;
 
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am0_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am1_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am2_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am3_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am4_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am5_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta0_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta1_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta2_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta3_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta4_out ;
wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta5_out ;
wire [2:0] conf_wb_img_ctrl0_out ;
wire [2:0] conf_wb_img_ctrl1_out ;
wire [2:0] conf_wb_img_ctrl2_out ;
wire [2:0] conf_wb_img_ctrl3_out ;
wire [2:0] conf_wb_img_ctrl4_out ;
wire [2:0] conf_wb_img_ctrl5_out ;
wire [23:0] conf_ccyc_addr_out ;
wire conf_soft_res_out ;
wire conf_int_out ;
 
// PCI IO MUX OUTPUTS
wire pci_mux_frame_out ;
wire pci_mux_irdy_out ;
wire pci_mux_devsel_out ;
wire pci_mux_trdy_out ;
wire pci_mux_stop_out ;
wire [3:0] pci_mux_cbe_out ;
wire [31:0] pci_mux_ad_out ;
wire pci_mux_ad_load_out ;
 
wire [31:0] pci_mux_ad_en_out ;
wire pci_mux_ad_en_unregistered_out ;
wire pci_mux_frame_en_out ;
wire pci_mux_irdy_en_out ;
wire pci_mux_devsel_en_out ;
wire pci_mux_trdy_en_out ;
wire pci_mux_stop_en_out ;
wire [3:0] pci_mux_cbe_en_out ;
 
wire pci_mux_par_out ;
wire pci_mux_par_en_out ;
wire pci_mux_perr_out ;
wire pci_mux_perr_en_out ;
wire pci_mux_serr_out ;
wire pci_mux_serr_en_out ;
 
wire pci_mux_req_out ;
wire pci_mux_req_en_out ;
 
// assign outputs to top level outputs
 
assign pci_ad_oe_o = pci_mux_ad_en_out ;
assign pci_frame_oe_o = pci_mux_frame_en_out ;
assign pci_irdy_oe_o = pci_mux_irdy_en_out ;
assign pci_cbe_oe_o = pci_mux_cbe_en_out ;
 
assign pci_par_o = pci_mux_par_out ;
assign pci_par_oe_o = pci_mux_par_en_out ;
assign pci_perr_o = pci_mux_perr_out ;
assign pci_perr_oe_o = pci_mux_perr_en_out ;
assign pci_serr_o = pci_mux_serr_out ;
assign pci_serr_oe_o = pci_mux_serr_en_out ;
 
assign pci_req_o = pci_mux_req_out ;
assign pci_req_oe_o = pci_mux_req_en_out ;
 
assign pci_trdy_oe_o = pci_mux_trdy_en_out ;
assign pci_devsel_oe_o = pci_mux_devsel_en_out ;
assign pci_stop_oe_o = pci_mux_stop_en_out ;
assign pci_trdy_o = pci_mux_trdy_out ;
assign pci_devsel_o = pci_mux_devsel_out ;
assign pci_stop_o = pci_mux_stop_out ;
 
assign pci_ad_o = pci_mux_ad_out ;
assign pci_frame_o = pci_mux_frame_out ;
assign pci_irdy_o = pci_mux_irdy_out ;
assign pci_cbe_o = pci_mux_cbe_out ;
 
// duplicate output register's outputs
wire out_bckp_frame_out ;
wire out_bckp_irdy_out ;
wire out_bckp_devsel_out ;
wire out_bckp_trdy_out ;
wire out_bckp_stop_out ;
wire [3:0] out_bckp_cbe_out ;
wire out_bckp_cbe_en_out ;
wire [31:0] out_bckp_ad_out ;
wire out_bckp_ad_en_out ;
wire out_bckp_irdy_en_out ;
wire out_bckp_frame_en_out ;
wire out_bckp_tar_ad_en_out ;
wire out_bckp_mas_ad_en_out ;
wire out_bckp_trdy_en_out ;
 
wire out_bckp_par_out ;
wire out_bckp_par_en_out ;
wire out_bckp_perr_out ;
wire out_bckp_perr_en_out ;
wire out_bckp_serr_out ;
wire out_bckp_serr_en_out ;
 
 
// PARITY CHECKER OUTPUTS
wire parchk_pci_par_out ;
wire parchk_pci_par_en_out ;
wire parchk_pci_perr_out ;
wire parchk_pci_perr_en_out ;
wire parchk_pci_serr_out ;
wire parchk_pci_serr_en_out ;
wire parchk_par_err_detect_out ;
wire parchk_perr_mas_detect_out ;
wire parchk_sig_serr_out ;
 
// input register outputs
wire in_reg_gnt_out ;
wire in_reg_frame_out ;
wire in_reg_irdy_out ;
wire in_reg_trdy_out ;
wire in_reg_stop_out ;
wire in_reg_devsel_out ;
wire in_reg_idsel_out ;
wire [31:0] in_reg_ad_out ;
wire [3:0] in_reg_cbe_out ;
 
/*=========================================================================================================
Now comes definition of all modules' and their appropriate inputs
=========================================================================================================*/
// PCI BRIDGE RESET AND INTERRUPT LOGIC INPUTS
wire pci_resi_rst_i = wb_rst_i ;
wire pci_resi_pci_rstn_in = pci_rst_i ;
wire pci_resi_conf_soft_res_in = conf_soft_res_out ;
wire pci_inti_pci_intan_in = pci_inta_i ;
wire pci_inti_conf_int_in = conf_int_out ;
wire pci_inti_int_i = wb_int_i ;
wire pci_inti_out_bckp_perr_en_in = out_bckp_perr_en_out ;
wire pci_inti_out_bckp_serr_en_in = out_bckp_serr_en_out ;
 
pci_rst_int pci_resets_and_interrupts
(
.clk_in (pci_clk),
.rst_i (pci_resi_rst_i),
.pci_rstn_in (pci_resi_pci_rstn_in),
.conf_soft_res_in (pci_resi_conf_soft_res_in),
.reset (pci_reso_reset),
.pci_rstn_out (pci_reso_pci_rstn_out),
.pci_rstn_en_out (pci_reso_pci_rstn_en_out),
.rst_o (pci_reso_rst_o),
.pci_intan_in (pci_inti_pci_intan_in),
.conf_int_in (pci_inti_conf_int_in),
.int_i (pci_inti_int_i),
.out_bckp_perr_en_in (pci_inti_out_bckp_perr_en_in),
.out_bckp_serr_en_in (pci_inti_out_bckp_serr_en_in),
.pci_intan_out (pci_into_pci_intan_out),
.pci_intan_en_out (pci_into_pci_intan_en_out),
.int_o (pci_into_int_o),
.conf_isr_int_prop_out (pci_into_conf_isr_int_prop_out)
);
 
// WISHBONE SLAVE UNIT INPUTS
wire [31:0] wbu_addr_in = wbs_adr_i ;
wire [31:0] wbu_sdata_in = wbs_dat_i ;
wire wbu_cyc_in = wbs_cyc_i ;
wire wbu_stb_in = wbs_stb_i ;
wire wbu_we_in = wbs_we_i ;
wire [3:0] wbu_sel_in = wbs_sel_i ;
wire wbu_cab_in = wbs_cab_i ;
 
wire [5:0] wbu_map_in = {
conf_wb_mem_io5_out,
conf_wb_mem_io4_out,
conf_wb_mem_io3_out,
conf_wb_mem_io2_out,
conf_wb_mem_io1_out,
conf_wb_mem_io0_out
} ;
 
wire [5:0] wbu_pref_en_in = {
conf_wb_img_ctrl5_out[1],
conf_wb_img_ctrl4_out[1],
conf_wb_img_ctrl3_out[1],
conf_wb_img_ctrl2_out[1],
conf_wb_img_ctrl1_out[1],
conf_wb_img_ctrl0_out[1]
};
wire [5:0] wbu_mrl_en_in = {
conf_wb_img_ctrl5_out[0],
conf_wb_img_ctrl4_out[0],
conf_wb_img_ctrl3_out[0],
conf_wb_img_ctrl2_out[0],
conf_wb_img_ctrl1_out[0],
conf_wb_img_ctrl0_out[0]
};
 
wire [5:0] wbu_at_en_in = {
conf_wb_img_ctrl5_out[2],
conf_wb_img_ctrl4_out[2],
conf_wb_img_ctrl3_out[2],
conf_wb_img_ctrl2_out[2],
conf_wb_img_ctrl1_out[2],
conf_wb_img_ctrl0_out[2]
} ;
 
wire wbu_pci_drcomp_pending_in = pciu_pci_drcomp_pending_out ;
wire wbu_pciw_empty_in = pciu_pciw_fifo_empty_out ;
 
`ifdef HOST
wire [31:0] wbu_conf_data_in = conf_w_data_out ;
`else
`ifdef GUEST
wire [31:0] wbu_conf_data_in = conf_r_data_out ;
`endif
`endif
 
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar0_in = conf_wb_ba0_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar1_in = conf_wb_ba1_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar2_in = conf_wb_ba2_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar3_in = conf_wb_ba3_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar4_in = conf_wb_ba4_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar5_in = conf_wb_ba5_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am0_in = conf_wb_am0_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am1_in = conf_wb_am1_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am2_in = conf_wb_am2_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am3_in = conf_wb_am3_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am4_in = conf_wb_am4_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am5_in = conf_wb_am5_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta0_in = conf_wb_ta0_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta1_in = conf_wb_ta1_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta2_in = conf_wb_ta2_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta3_in = conf_wb_ta3_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta4_in = conf_wb_ta4_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta5_in = conf_wb_ta5_out ;
 
wire [23:0] wbu_ccyc_addr_in = conf_ccyc_addr_out ;
wire wbu_master_enable_in = conf_pci_master_enable_out ;
wire wbu_cache_line_size_not_zero = conf_cache_lsize_not_zero_to_wb_out ;
wire [7:0] wbu_cache_line_size_in = conf_cache_line_size_to_pci_out ;
 
wire wbu_pciif_gnt_in = pci_gnt_i ;
wire wbu_pciif_frame_in = in_reg_frame_out ;
wire wbu_pciif_irdy_in = in_reg_irdy_out ;
wire wbu_pciif_trdy_in = pci_trdy_i ;
wire wbu_pciif_stop_in = pci_stop_i ;
wire wbu_pciif_devsel_in = pci_devsel_i ;
wire [31:0] wbu_pciif_ad_reg_in = in_reg_ad_out ;
wire wbu_pciif_trdy_reg_in = in_reg_trdy_out ;
wire wbu_pciif_stop_reg_in = in_reg_stop_out ;
wire wbu_pciif_devsel_reg_in = in_reg_devsel_out ;
 
 
wire [7:0] wbu_latency_tim_val_in = conf_latency_tim_out ;
 
wire wbu_pciif_frame_en_in = out_bckp_frame_en_out ;
wire wbu_pciif_frame_out_in = out_bckp_frame_out ;
 
pci_wb_slave_unit wishbone_slave_unit
(
.reset_in (reset),
.wb_clock_in (wb_clk),
.pci_clock_in (pci_clk),
.ADDR_I (wbu_addr_in),
.SDATA_I (wbu_sdata_in),
.SDATA_O (wbu_sdata_out),
.CYC_I (wbu_cyc_in),
.STB_I (wbu_stb_in),
.WE_I (wbu_we_in),
.SEL_I (wbu_sel_in),
.ACK_O (wbu_ack_out),
.RTY_O (wbu_rty_out),
.ERR_O (wbu_err_out),
.CAB_I (wbu_cab_in),
.wbu_map_in (wbu_map_in),
.wbu_pref_en_in (wbu_pref_en_in),
.wbu_mrl_en_in (wbu_mrl_en_in),
.wbu_pci_drcomp_pending_in (wbu_pci_drcomp_pending_in),
.wbu_conf_data_in (wbu_conf_data_in),
.wbu_pciw_empty_in (wbu_pciw_empty_in),
.wbu_bar0_in (wbu_bar0_in),
.wbu_bar1_in (wbu_bar1_in),
.wbu_bar2_in (wbu_bar2_in),
.wbu_bar3_in (wbu_bar3_in),
.wbu_bar4_in (wbu_bar4_in),
.wbu_bar5_in (wbu_bar5_in),
.wbu_am0_in (wbu_am0_in),
.wbu_am1_in (wbu_am1_in),
.wbu_am2_in (wbu_am2_in),
.wbu_am3_in (wbu_am3_in),
.wbu_am4_in (wbu_am4_in),
.wbu_am5_in (wbu_am5_in),
.wbu_ta0_in (wbu_ta0_in),
.wbu_ta1_in (wbu_ta1_in),
.wbu_ta2_in (wbu_ta2_in),
.wbu_ta3_in (wbu_ta3_in),
.wbu_ta4_in (wbu_ta4_in),
.wbu_ta5_in (wbu_ta5_in),
.wbu_at_en_in (wbu_at_en_in),
.wbu_ccyc_addr_in (wbu_ccyc_addr_in),
.wbu_master_enable_in (wbu_master_enable_in),
.wbu_cache_line_size_not_zero (wbu_cache_line_size_not_zero),
.wbu_cache_line_size_in (wbu_cache_line_size_in),
.wbu_pciif_gnt_in (wbu_pciif_gnt_in),
.wbu_pciif_frame_in (wbu_pciif_frame_in),
.wbu_pciif_frame_en_in (wbu_pciif_frame_en_in),
.wbu_pciif_frame_out_in (wbu_pciif_frame_out_in),
.wbu_pciif_irdy_in (wbu_pciif_irdy_in),
.wbu_pciif_trdy_in (wbu_pciif_trdy_in),
.wbu_pciif_stop_in (wbu_pciif_stop_in),
.wbu_pciif_devsel_in (wbu_pciif_devsel_in),
.wbu_pciif_ad_reg_in (wbu_pciif_ad_reg_in),
.wbu_pciif_req_out (wbu_pciif_req_out),
.wbu_pciif_frame_out (wbu_pciif_frame_out),
.wbu_pciif_frame_en_out (wbu_pciif_frame_en_out),
.wbu_pciif_frame_load_out (wbu_pciif_frame_load_out),
.wbu_pciif_irdy_out (wbu_pciif_irdy_out),
.wbu_pciif_irdy_en_out (wbu_pciif_irdy_en_out),
.wbu_pciif_ad_out (wbu_pciif_ad_out),
.wbu_pciif_ad_en_out (wbu_pciif_ad_en_out),
.wbu_pciif_cbe_out (wbu_pciif_cbe_out),
.wbu_pciif_cbe_en_out (wbu_pciif_cbe_en_out),
.wbu_err_addr_out (wbu_err_addr_out),
.wbu_err_bc_out (wbu_err_bc_out),
.wbu_err_signal_out (wbu_err_signal_out),
.wbu_err_source_out (wbu_err_source_out),
.wbu_err_rty_exp_out (wbu_err_rty_exp_out),
.wbu_tabort_rec_out (wbu_tabort_rec_out),
.wbu_mabort_rec_out (wbu_mabort_rec_out),
.wbu_conf_offset_out (wbu_conf_offset_out),
.wbu_conf_renable_out (wbu_conf_renable_out),
.wbu_conf_wenable_out (wbu_conf_wenable_out),
.wbu_conf_be_out (wbu_conf_be_out),
.wbu_conf_data_out (wbu_conf_data_out),
.wbu_del_read_comp_pending_out (wbu_del_read_comp_pending_out),
.wbu_wbw_fifo_empty_out (wbu_wbw_fifo_empty_out),
.wbu_latency_tim_val_in (wbu_latency_tim_val_in),
.wbu_ad_load_out (wbu_ad_load_out),
.wbu_ad_load_on_transfer_out (wbu_ad_load_on_transfer_out),
.wbu_pciif_trdy_reg_in (wbu_pciif_trdy_reg_in),
.wbu_pciif_stop_reg_in (wbu_pciif_stop_reg_in),
.wbu_pciif_devsel_reg_in (wbu_pciif_devsel_reg_in)
 
`ifdef PCI_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so_internal),
.scanb_en (scanb_en)
`endif
);
 
// PCI TARGET UNIT INPUTS
wire [31:0] pciu_mdata_in = wbm_dat_i ;
wire pciu_ack_in = wbm_ack_i ;
wire pciu_rty_in = wbm_rty_i ;
wire pciu_err_in = wbm_err_i ;
 
wire [5:0] pciu_map_in = {
conf_pci_mem_io5_out,
conf_pci_mem_io4_out,
conf_pci_mem_io3_out,
conf_pci_mem_io2_out,
conf_pci_mem_io1_out,
conf_pci_mem_io0_out
} ;
 
wire [5:0] pciu_pref_en_in = {
conf_pci_img_ctrl5_out[0],
conf_pci_img_ctrl4_out[0],
conf_pci_img_ctrl3_out[0],
conf_pci_img_ctrl2_out[0],
conf_pci_img_ctrl1_out[0],
conf_pci_img_ctrl0_out[0]
};
 
wire [5:0] pciu_at_en_in = {
conf_pci_img_ctrl5_out[1],
conf_pci_img_ctrl4_out[1],
conf_pci_img_ctrl3_out[1],
conf_pci_img_ctrl2_out[1],
conf_pci_img_ctrl1_out[1],
conf_pci_img_ctrl0_out[1]
} ;
 
wire pciu_mem_enable_in = conf_mem_space_enable_out ;
wire pciu_io_enable_in = conf_io_space_enable_out ;
 
wire pciu_wbw_fifo_empty_in = wbu_wbw_fifo_empty_out ;
wire pciu_wbu_del_read_comp_pending_in = wbu_del_read_comp_pending_out ;
wire pciu_wbu_frame_en_in = out_bckp_frame_en_out ;
 
`ifdef HOST
wire [31:0] pciu_conf_data_in = conf_r_data_out ;
`else
`ifdef GUEST
wire [31:0] pciu_conf_data_in = conf_w_data_out ;
`endif
`endif
 
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar0_in = conf_pci_ba0_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar1_in = conf_pci_ba1_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar2_in = conf_pci_ba2_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar3_in = conf_pci_ba3_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar4_in = conf_pci_ba4_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_bar5_in = conf_pci_ba5_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am0_in = conf_pci_am0_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am1_in = conf_pci_am1_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am2_in = conf_pci_am2_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am3_in = conf_pci_am3_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am4_in = conf_pci_am4_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_am5_in = conf_pci_am5_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta0_in = conf_pci_ta0_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta1_in = conf_pci_ta1_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta2_in = conf_pci_ta2_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta3_in = conf_pci_ta3_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta4_in = conf_pci_ta4_out ;
wire [(`PCI_NUM_OF_DEC_ADDR_LINES - 1):0] pciu_ta5_in = conf_pci_ta5_out ;
 
wire [7:0] pciu_cache_line_size_in = conf_cache_line_size_to_wb_out ;
wire pciu_cache_lsize_not_zero_in = conf_cache_lsize_not_zero_to_wb_out ;
 
wire pciu_pciif_frame_in = pci_frame_i ;
wire pciu_pciif_irdy_in = pci_irdy_i ;
wire pciu_pciif_idsel_in = pci_idsel_i ;
wire pciu_pciif_frame_reg_in = in_reg_frame_out ;
wire pciu_pciif_irdy_reg_in = in_reg_irdy_out ;
wire pciu_pciif_idsel_reg_in = in_reg_idsel_out ;
wire [31:0] pciu_pciif_ad_reg_in = in_reg_ad_out ;
wire [3:0] pciu_pciif_cbe_reg_in = in_reg_cbe_out ;
 
wire pciu_pciif_bckp_trdy_en_in = out_bckp_trdy_en_out ;
wire pciu_pciif_bckp_devsel_in = out_bckp_devsel_out ;
wire pciu_pciif_bckp_trdy_in = out_bckp_trdy_out ;
wire pciu_pciif_bckp_stop_in = out_bckp_stop_out ;
wire pciu_pciif_trdy_reg_in = in_reg_trdy_out ;
wire pciu_pciif_stop_reg_in = in_reg_stop_out ;
 
pci_target_unit pci_target_unit
(
.reset_in (reset),
.wb_clock_in (wb_clk),
.pci_clock_in (pci_clk),
.ADR_O (pciu_adr_out),
.MDATA_O (pciu_mdata_out),
.MDATA_I (pciu_mdata_in),
.CYC_O (pciu_cyc_out),
.STB_O (pciu_stb_out),
.WE_O (pciu_we_out),
.SEL_O (pciu_sel_out),
.ACK_I (pciu_ack_in),
.RTY_I (pciu_rty_in),
.ERR_I (pciu_err_in),
.CAB_O (pciu_cab_out),
.pciu_mem_enable_in (pciu_mem_enable_in),
.pciu_io_enable_in (pciu_io_enable_in),
.pciu_map_in (pciu_map_in),
.pciu_pref_en_in (pciu_pref_en_in),
.pciu_conf_data_in (pciu_conf_data_in),
.pciu_wbw_fifo_empty_in (pciu_wbw_fifo_empty_in),
.pciu_wbu_del_read_comp_pending_in (pciu_wbu_del_read_comp_pending_in),
.pciu_wbu_frame_en_in (pciu_wbu_frame_en_in),
.pciu_bar0_in (pciu_bar0_in),
.pciu_bar1_in (pciu_bar1_in),
.pciu_bar2_in (pciu_bar2_in),
.pciu_bar3_in (pciu_bar3_in),
.pciu_bar4_in (pciu_bar4_in),
.pciu_bar5_in (pciu_bar5_in),
.pciu_am0_in (pciu_am0_in),
.pciu_am1_in (pciu_am1_in),
.pciu_am2_in (pciu_am2_in),
.pciu_am3_in (pciu_am3_in),
.pciu_am4_in (pciu_am4_in),
.pciu_am5_in (pciu_am5_in),
.pciu_ta0_in (pciu_ta0_in),
.pciu_ta1_in (pciu_ta1_in),
.pciu_ta2_in (pciu_ta2_in),
.pciu_ta3_in (pciu_ta3_in),
.pciu_ta4_in (pciu_ta4_in),
.pciu_ta5_in (pciu_ta5_in),
.pciu_at_en_in (pciu_at_en_in),
.pciu_cache_line_size_in (pciu_cache_line_size_in),
.pciu_cache_lsize_not_zero_in (pciu_cache_lsize_not_zero_in),
.pciu_pciif_frame_in (pciu_pciif_frame_in),
.pciu_pciif_irdy_in (pciu_pciif_irdy_in),
.pciu_pciif_idsel_in (pciu_pciif_idsel_in),
.pciu_pciif_frame_reg_in (pciu_pciif_frame_reg_in),
.pciu_pciif_irdy_reg_in (pciu_pciif_irdy_reg_in),
.pciu_pciif_idsel_reg_in (pciu_pciif_idsel_reg_in),
.pciu_pciif_ad_reg_in (pciu_pciif_ad_reg_in),
.pciu_pciif_cbe_reg_in (pciu_pciif_cbe_reg_in),
.pciu_pciif_bckp_trdy_en_in (pciu_pciif_bckp_trdy_en_in),
.pciu_pciif_bckp_devsel_in (pciu_pciif_bckp_devsel_in),
.pciu_pciif_bckp_trdy_in (pciu_pciif_bckp_trdy_in),
.pciu_pciif_bckp_stop_in (pciu_pciif_bckp_stop_in),
.pciu_pciif_trdy_reg_in (pciu_pciif_trdy_reg_in),
.pciu_pciif_stop_reg_in (pciu_pciif_stop_reg_in),
.pciu_pciif_trdy_out (pciu_pciif_trdy_out),
.pciu_pciif_stop_out (pciu_pciif_stop_out),
.pciu_pciif_devsel_out (pciu_pciif_devsel_out),
.pciu_pciif_trdy_en_out (pciu_pciif_trdy_en_out),
.pciu_pciif_stop_en_out (pciu_pciif_stop_en_out),
.pciu_pciif_devsel_en_out (pciu_pciif_devsel_en_out),
.pciu_ad_load_out (pciu_ad_load_out),
.pciu_ad_load_on_transfer_out (pciu_ad_load_on_transfer_out),
.pciu_pciif_ad_out (pciu_pciif_ad_out),
.pciu_pciif_ad_en_out (pciu_pciif_ad_en_out),
.pciu_pciif_tabort_set_out (pciu_pciif_tabort_set_out),
.pciu_err_addr_out (pciu_err_addr_out),
.pciu_err_bc_out (pciu_err_bc_out),
.pciu_err_data_out (pciu_err_data_out),
.pciu_err_be_out (pciu_err_be_out),
.pciu_err_signal_out (pciu_err_signal_out),
.pciu_err_source_out (pciu_err_source_out),
.pciu_err_rty_exp_out (pciu_err_rty_exp_out),
.pciu_conf_offset_out (pciu_conf_offset_out),
.pciu_conf_renable_out (pciu_conf_renable_out),
.pciu_conf_wenable_out (pciu_conf_wenable_out),
.pciu_conf_be_out (pciu_conf_be_out),
.pciu_conf_data_out (pciu_conf_data_out),
.pciu_conf_select_out (pciu_conf_select_out),
.pciu_pci_drcomp_pending_out (pciu_pci_drcomp_pending_out),
.pciu_pciw_fifo_empty_out (pciu_pciw_fifo_empty_out)
 
`ifdef PCI_BIST
,
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_so_internal),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
`endif
);
 
 
// CONFIGURATION SPACE INPUTS
`ifdef HOST
 
wire [11:0] conf_w_addr_in = wbu_conf_offset_out ;
wire [31:0] conf_w_data_in = wbu_conf_data_out ;
wire conf_w_we_in = wbu_conf_wenable_out ;
wire conf_w_re_in = wbu_conf_renable_out ;
wire [3:0] conf_w_be_in = wbu_conf_be_out ;
wire conf_w_clock = wb_clk ;
wire [11:0] conf_r_addr_in = pciu_conf_offset_out ;
wire conf_r_re_in = pciu_conf_renable_out ;
 
`else
`ifdef GUEST
 
wire [11:0] conf_r_addr_in = wbu_conf_offset_out ;
wire conf_r_re_in = wbu_conf_renable_out ;
wire conf_w_clock = pci_clk ;
wire [11:0] conf_w_addr_in = pciu_conf_offset_out ;
wire [31:0] conf_w_data_in = pciu_conf_data_out ;
wire conf_w_we_in = pciu_conf_wenable_out ;
wire conf_w_re_in = pciu_conf_renable_out ;
wire [3:0] conf_w_be_in = pciu_conf_be_out ;
 
`endif
`endif
 
 
wire conf_perr_in = parchk_par_err_detect_out ;
wire conf_serr_in = parchk_sig_serr_out ;
wire conf_master_abort_recv_in = wbu_mabort_rec_out ;
wire conf_target_abort_recv_in = wbu_tabort_rec_out ;
wire conf_target_abort_set_in = pciu_pciif_tabort_set_out ;
 
wire conf_master_data_par_err_in = parchk_perr_mas_detect_out ;
 
wire [3:0] conf_pci_err_be_in = pciu_err_be_out ;
wire [3:0] conf_pci_err_bc_in = pciu_err_bc_out;
wire conf_pci_err_es_in = pciu_err_source_out ;
wire conf_pci_err_rty_exp_in = pciu_err_rty_exp_out ;
wire conf_pci_err_sig_in = pciu_err_signal_out ;
wire [31:0] conf_pci_err_addr_in = pciu_err_addr_out ;
wire [31:0] conf_pci_err_data_in = pciu_err_data_out ;
 
wire [3:0] conf_wb_err_be_in = out_bckp_cbe_out ;
wire [3:0] conf_wb_err_bc_in = wbu_err_bc_out ;
wire conf_wb_err_rty_exp_in = wbu_err_rty_exp_out ;
wire conf_wb_err_es_in = wbu_err_source_out ;
wire conf_wb_err_sig_in = wbu_err_signal_out ;
wire [31:0] conf_wb_err_addr_in = wbu_err_addr_out ;
wire [31:0] conf_wb_err_data_in = out_bckp_ad_out ;
 
wire conf_isr_int_prop_in = pci_into_conf_isr_int_prop_out ;
wire conf_par_err_int_in = parchk_perr_mas_detect_out ;
wire conf_sys_err_int_in = parchk_sig_serr_out ;
 
pci_conf_space configuration(
.reset (reset),
.pci_clk (pci_clk),
.wb_clk (wb_clk),
.w_conf_address_in (conf_w_addr_in),
.w_conf_data_in (conf_w_data_in),
.w_conf_data_out (conf_w_data_out),
.r_conf_address_in (conf_r_addr_in),
.r_conf_data_out (conf_r_data_out),
.w_we (conf_w_we_in),
.w_re (conf_w_re_in),
.r_re (conf_r_re_in),
.w_byte_en (conf_w_be_in),
.w_clock (conf_w_clock),
.serr_enable (conf_serr_enable_out),
.perr_response (conf_perr_response_out),
.pci_master_enable (conf_pci_master_enable_out),
.memory_space_enable (conf_mem_space_enable_out),
.io_space_enable (conf_io_space_enable_out),
.perr_in (conf_perr_in),
.serr_in (conf_serr_in),
.master_abort_recv (conf_master_abort_recv_in),
.target_abort_recv (conf_target_abort_recv_in),
.target_abort_set (conf_target_abort_set_in),
.master_data_par_err (conf_master_data_par_err_in),
.cache_line_size_to_pci (conf_cache_line_size_to_pci_out),
.cache_line_size_to_wb (conf_cache_line_size_to_wb_out),
.cache_lsize_not_zero_to_wb (conf_cache_lsize_not_zero_to_wb_out),
.latency_tim (conf_latency_tim_out),
.pci_base_addr0 (conf_pci_ba0_out),
.pci_base_addr1 (conf_pci_ba1_out),
.pci_base_addr2 (conf_pci_ba2_out),
.pci_base_addr3 (conf_pci_ba3_out),
.pci_base_addr4 (conf_pci_ba4_out),
.pci_base_addr5 (conf_pci_ba5_out),
.pci_memory_io0 (conf_pci_mem_io0_out),
.pci_memory_io1 (conf_pci_mem_io1_out),
.pci_memory_io2 (conf_pci_mem_io2_out),
.pci_memory_io3 (conf_pci_mem_io3_out),
.pci_memory_io4 (conf_pci_mem_io4_out),
.pci_memory_io5 (conf_pci_mem_io5_out),
.pci_addr_mask0 (conf_pci_am0_out),
.pci_addr_mask1 (conf_pci_am1_out),
.pci_addr_mask2 (conf_pci_am2_out),
.pci_addr_mask3 (conf_pci_am3_out),
.pci_addr_mask4 (conf_pci_am4_out),
.pci_addr_mask5 (conf_pci_am5_out),
.pci_tran_addr0 (conf_pci_ta0_out),
.pci_tran_addr1 (conf_pci_ta1_out),
.pci_tran_addr2 (conf_pci_ta2_out),
.pci_tran_addr3 (conf_pci_ta3_out),
.pci_tran_addr4 (conf_pci_ta4_out),
.pci_tran_addr5 (conf_pci_ta5_out),
.pci_img_ctrl0 (conf_pci_img_ctrl0_out),
.pci_img_ctrl1 (conf_pci_img_ctrl1_out),
.pci_img_ctrl2 (conf_pci_img_ctrl2_out),
.pci_img_ctrl3 (conf_pci_img_ctrl3_out),
.pci_img_ctrl4 (conf_pci_img_ctrl4_out),
.pci_img_ctrl5 (conf_pci_img_ctrl5_out),
.pci_error_be (conf_pci_err_be_in),
.pci_error_bc (conf_pci_err_bc_in),
.pci_error_rty_exp (conf_pci_err_rty_exp_in),
.pci_error_es (conf_pci_err_es_in),
.pci_error_sig (conf_pci_err_sig_in),
.pci_error_addr (conf_pci_err_addr_in),
.pci_error_data (conf_pci_err_data_in),
.wb_base_addr0 (conf_wb_ba0_out),
.wb_base_addr1 (conf_wb_ba1_out),
.wb_base_addr2 (conf_wb_ba2_out),
.wb_base_addr3 (conf_wb_ba3_out),
.wb_base_addr4 (conf_wb_ba4_out),
.wb_base_addr5 (conf_wb_ba5_out),
.wb_memory_io0 (conf_wb_mem_io0_out),
.wb_memory_io1 (conf_wb_mem_io1_out),
.wb_memory_io2 (conf_wb_mem_io2_out),
.wb_memory_io3 (conf_wb_mem_io3_out),
.wb_memory_io4 (conf_wb_mem_io4_out),
.wb_memory_io5 (conf_wb_mem_io5_out),
.wb_addr_mask0 (conf_wb_am0_out),
.wb_addr_mask1 (conf_wb_am1_out),
.wb_addr_mask2 (conf_wb_am2_out),
.wb_addr_mask3 (conf_wb_am3_out),
.wb_addr_mask4 (conf_wb_am4_out),
.wb_addr_mask5 (conf_wb_am5_out),
.wb_tran_addr0 (conf_wb_ta0_out),
.wb_tran_addr1 (conf_wb_ta1_out),
.wb_tran_addr2 (conf_wb_ta2_out),
.wb_tran_addr3 (conf_wb_ta3_out),
.wb_tran_addr4 (conf_wb_ta4_out),
.wb_tran_addr5 (conf_wb_ta5_out),
.wb_img_ctrl0 (conf_wb_img_ctrl0_out),
.wb_img_ctrl1 (conf_wb_img_ctrl1_out),
.wb_img_ctrl2 (conf_wb_img_ctrl2_out),
.wb_img_ctrl3 (conf_wb_img_ctrl3_out),
.wb_img_ctrl4 (conf_wb_img_ctrl4_out),
.wb_img_ctrl5 (conf_wb_img_ctrl5_out),
.wb_error_be (conf_wb_err_be_in),
.wb_error_bc (conf_wb_err_bc_in),
.wb_error_rty_exp (conf_wb_err_rty_exp_in),
.wb_error_es (conf_wb_err_es_in),
.wb_error_sig (conf_wb_err_sig_in),
.wb_error_addr (conf_wb_err_addr_in),
.wb_error_data (conf_wb_err_data_in),
.config_addr (conf_ccyc_addr_out),
.icr_soft_res (conf_soft_res_out),
.int_out (conf_int_out),
.isr_int_prop (conf_isr_int_prop_in),
.isr_par_err_int (conf_par_err_int_in),
.isr_sys_err_int (conf_sys_err_int_in)
) ;
 
// pci data io multiplexer inputs
wire pci_mux_tar_ad_en_in = pciu_pciif_ad_en_out ;
wire pci_mux_tar_ad_en_reg_in = out_bckp_tar_ad_en_out ;
wire [31:0] pci_mux_tar_ad_in = pciu_pciif_ad_out ;
wire pci_mux_devsel_in = pciu_pciif_devsel_out ;
wire pci_mux_devsel_en_in = pciu_pciif_devsel_en_out ;
wire pci_mux_trdy_in = pciu_pciif_trdy_out ;
wire pci_mux_trdy_en_in = pciu_pciif_trdy_en_out ;
wire pci_mux_stop_in = pciu_pciif_stop_out ;
wire pci_mux_stop_en_in = pciu_pciif_stop_en_out ;
wire pci_mux_tar_load_in = pciu_ad_load_out ;
wire pci_mux_tar_load_on_transfer_in = pciu_ad_load_on_transfer_out ;
 
wire pci_mux_mas_ad_en_in = wbu_pciif_ad_en_out ;
wire [31:0] pci_mux_mas_ad_in = wbu_pciif_ad_out ;
 
wire pci_mux_frame_in = wbu_pciif_frame_out ;
wire pci_mux_frame_en_in = wbu_pciif_frame_en_out ;
wire pci_mux_irdy_in = wbu_pciif_irdy_out;
wire pci_mux_irdy_en_in = wbu_pciif_irdy_en_out;
wire pci_mux_mas_load_in = wbu_ad_load_out ;
wire pci_mux_mas_load_on_transfer_in = wbu_ad_load_on_transfer_out ;
wire [3:0] pci_mux_cbe_in = wbu_pciif_cbe_out ;
wire pci_mux_cbe_en_in = wbu_pciif_cbe_en_out ;
 
wire pci_mux_par_in = parchk_pci_par_out ;
wire pci_mux_par_en_in = parchk_pci_par_en_out ;
wire pci_mux_perr_in = parchk_pci_perr_out ;
wire pci_mux_perr_en_in = parchk_pci_perr_en_out ;
wire pci_mux_serr_in = parchk_pci_serr_out ;
wire pci_mux_serr_en_in = parchk_pci_serr_en_out;
 
wire pci_mux_req_in = wbu_pciif_req_out ;
wire pci_mux_frame_load_in = wbu_pciif_frame_load_out ;
 
wire pci_mux_pci_irdy_in = pci_irdy_i ;
wire pci_mux_pci_trdy_in = pci_trdy_i ;
wire pci_mux_pci_frame_in = pci_frame_i ;
wire pci_mux_pci_stop_in = pci_stop_i ;
 
pci_io_mux pci_io_mux
(
.reset_in (reset),
.clk_in (pci_clk),
.frame_in (pci_mux_frame_in),
.frame_en_in (pci_mux_frame_en_in),
.frame_load_in (pci_mux_frame_load_in),
.irdy_in (pci_mux_irdy_in),
.irdy_en_in (pci_mux_irdy_en_in),
.devsel_in (pci_mux_devsel_in),
.devsel_en_in (pci_mux_devsel_en_in),
.trdy_in (pci_mux_trdy_in),
.trdy_en_in (pci_mux_trdy_en_in),
.stop_in (pci_mux_stop_in),
.stop_en_in (pci_mux_stop_en_in),
.master_load_in (pci_mux_mas_load_in),
.master_load_on_transfer_in (pci_mux_mas_load_on_transfer_in),
.target_load_in (pci_mux_tar_load_in),
.target_load_on_transfer_in (pci_mux_tar_load_on_transfer_in),
.cbe_in (pci_mux_cbe_in),
.cbe_en_in (pci_mux_cbe_en_in),
.mas_ad_in (pci_mux_mas_ad_in),
.tar_ad_in (pci_mux_tar_ad_in),
 
.mas_ad_en_in (pci_mux_mas_ad_en_in),
.tar_ad_en_in (pci_mux_tar_ad_en_in),
.tar_ad_en_reg_in (pci_mux_tar_ad_en_reg_in),
 
.par_in (pci_mux_par_in),
.par_en_in (pci_mux_par_en_in),
.perr_in (pci_mux_perr_in),
.perr_en_in (pci_mux_perr_en_in),
.serr_in (pci_mux_serr_in),
.serr_en_in (pci_mux_serr_en_in),
 
.frame_en_out (pci_mux_frame_en_out),
.irdy_en_out (pci_mux_irdy_en_out),
.devsel_en_out (pci_mux_devsel_en_out),
.trdy_en_out (pci_mux_trdy_en_out),
.stop_en_out (pci_mux_stop_en_out),
.cbe_en_out (pci_mux_cbe_en_out),
.ad_en_out (pci_mux_ad_en_out),
 
.frame_out (pci_mux_frame_out),
.irdy_out (pci_mux_irdy_out),
.devsel_out (pci_mux_devsel_out),
.trdy_out (pci_mux_trdy_out),
.stop_out (pci_mux_stop_out),
.cbe_out (pci_mux_cbe_out),
.ad_out (pci_mux_ad_out),
.ad_load_out (pci_mux_ad_load_out),
 
.par_out (pci_mux_par_out),
.par_en_out (pci_mux_par_en_out),
.perr_out (pci_mux_perr_out),
.perr_en_out (pci_mux_perr_en_out),
.serr_out (pci_mux_serr_out),
.serr_en_out (pci_mux_serr_en_out),
.req_in (pci_mux_req_in),
.req_out (pci_mux_req_out),
.req_en_out (pci_mux_req_en_out),
.pci_irdy_in (pci_mux_pci_irdy_in),
.pci_trdy_in (pci_mux_pci_trdy_in),
.pci_frame_in (pci_mux_pci_frame_in),
.pci_stop_in (pci_mux_pci_stop_in),
.ad_en_unregistered_out (pci_mux_ad_en_unregistered_out)
);
 
pci_cur_out_reg output_backup
(
.reset_in (reset),
.clk_in (pci_clk),
.frame_in (pci_mux_frame_in),
.frame_en_in (pci_mux_frame_en_in),
.frame_load_in (pci_mux_frame_load_in),
.irdy_in (pci_mux_irdy_in),
.irdy_en_in (pci_mux_irdy_en_in),
.devsel_in (pci_mux_devsel_in),
.trdy_in (pci_mux_trdy_in),
.trdy_en_in (pci_mux_trdy_en_in),
.stop_in (pci_mux_stop_in),
.ad_load_in (pci_mux_ad_load_out),
.cbe_in (pci_mux_cbe_in),
.cbe_en_in (pci_mux_cbe_en_in),
.mas_ad_in (pci_mux_mas_ad_in),
.tar_ad_in (pci_mux_tar_ad_in),
 
.mas_ad_en_in (pci_mux_mas_ad_en_in),
.tar_ad_en_in (pci_mux_tar_ad_en_in),
.ad_en_unregistered_in (pci_mux_ad_en_unregistered_out),
 
.par_in (pci_mux_par_in),
.par_en_in (pci_mux_par_en_in),
.perr_in (pci_mux_perr_in),
.perr_en_in (pci_mux_perr_en_in),
.serr_in (pci_mux_serr_in),
.serr_en_in (pci_mux_serr_en_in),
 
.frame_out (out_bckp_frame_out),
.frame_en_out (out_bckp_frame_en_out),
.irdy_out (out_bckp_irdy_out),
.irdy_en_out (out_bckp_irdy_en_out),
.devsel_out (out_bckp_devsel_out),
.trdy_out (out_bckp_trdy_out),
.trdy_en_out (out_bckp_trdy_en_out),
.stop_out (out_bckp_stop_out),
.cbe_out (out_bckp_cbe_out),
.ad_out (out_bckp_ad_out),
.ad_en_out (out_bckp_ad_en_out),
.cbe_en_out (out_bckp_cbe_en_out),
.tar_ad_en_out (out_bckp_tar_ad_en_out),
.mas_ad_en_out (out_bckp_mas_ad_en_out),
 
.par_out (out_bckp_par_out),
.par_en_out (out_bckp_par_en_out),
.perr_out (out_bckp_perr_out),
.perr_en_out (out_bckp_perr_en_out),
.serr_out (out_bckp_serr_out),
.serr_en_out (out_bckp_serr_en_out)
) ;
assign irdy_o = out_bckp_irdy_out ;
assign irdy_en_o = out_bckp_irdy_en_out ;
assign pci_ad_bckp_o = out_bckp_ad_out ;
 
// PARITY CHECKER INPUTS
wire parchk_pci_par_in = pci_par_i ;
wire parchk_pci_perr_in = pci_perr_i ;
wire parchk_pci_frame_reg_in = in_reg_frame_out ;
wire parchk_pci_frame_en_in = out_bckp_frame_en_out ;
wire parchk_pci_irdy_en_in = out_bckp_irdy_en_out ;
wire parchk_pci_irdy_reg_in = in_reg_irdy_out ;
wire parchk_pci_trdy_reg_in = in_reg_trdy_out ;
 
 
wire parchk_pci_trdy_en_in = out_bckp_trdy_en_out ;
 
 
wire [31:0] parchk_pci_ad_out_in = out_bckp_ad_out ;
wire [31:0] parchk_pci_ad_reg_in = in_reg_ad_out ;
wire [3:0] parchk_pci_cbe_in_in = pci_cbe_i ;
wire [3:0] parchk_pci_cbe_reg_in = in_reg_cbe_out ;
wire [3:0] parchk_pci_cbe_out_in = out_bckp_cbe_out ;
wire parchk_pci_ad_en_in = out_bckp_ad_en_out ;
wire parchk_par_err_response_in = conf_perr_response_out ;
wire parchk_serr_enable_in = conf_serr_enable_out ;
 
wire parchk_pci_perr_out_in = out_bckp_perr_out ;
wire parchk_pci_serr_en_in = out_bckp_serr_en_out ;
wire parchk_pci_serr_out_in = out_bckp_serr_out ;
wire parchk_pci_cbe_en_in = out_bckp_cbe_en_out ;
 
wire parchk_pci_par_en_in = out_bckp_par_en_out ;
 
pci_parity_check parity_checker
(
.reset_in (reset),
.clk_in (pci_clk),
.pci_par_in (parchk_pci_par_in),
.pci_par_out (parchk_pci_par_out),
.pci_par_en_out (parchk_pci_par_en_out),
.pci_par_en_in (parchk_pci_par_en_in),
.pci_perr_in (parchk_pci_perr_in),
.pci_perr_out (parchk_pci_perr_out),
.pci_perr_en_out (parchk_pci_perr_en_out),
.pci_perr_out_in (parchk_pci_perr_out_in),
.pci_serr_out (parchk_pci_serr_out),
.pci_serr_out_in (parchk_pci_serr_out_in),
.pci_serr_en_out (parchk_pci_serr_en_out),
.pci_serr_en_in (parchk_pci_serr_en_in),
.pci_frame_reg_in (parchk_pci_frame_reg_in),
.pci_frame_en_in (parchk_pci_frame_en_in),
.pci_irdy_en_in (parchk_pci_irdy_en_in),
.pci_irdy_reg_in (parchk_pci_irdy_reg_in),
.pci_trdy_reg_in (parchk_pci_trdy_reg_in),
.pci_trdy_en_in (parchk_pci_trdy_en_in),
.pci_ad_out_in (parchk_pci_ad_out_in),
.pci_ad_reg_in (parchk_pci_ad_reg_in),
.pci_cbe_in_in (parchk_pci_cbe_in_in),
.pci_cbe_reg_in (parchk_pci_cbe_reg_in),
.pci_cbe_en_in (parchk_pci_cbe_en_in),
.pci_cbe_out_in (parchk_pci_cbe_out_in),
.pci_ad_en_in (parchk_pci_ad_en_in),
.par_err_response_in (parchk_par_err_response_in),
.par_err_detect_out (parchk_par_err_detect_out),
.perr_mas_detect_out (parchk_perr_mas_detect_out),
.serr_enable_in (parchk_serr_enable_in),
.sig_serr_out (parchk_sig_serr_out)
);
 
wire in_reg_gnt_in = pci_gnt_i ;
wire in_reg_frame_in = pci_frame_i ;
wire in_reg_irdy_in = pci_irdy_i ;
wire in_reg_trdy_in = pci_trdy_i ;
wire in_reg_stop_in = pci_stop_i ;
wire in_reg_devsel_in = pci_devsel_i ;
wire in_reg_idsel_in = pci_idsel_i ;
wire [31:0] in_reg_ad_in = pci_ad_i ;
wire [3:0] in_reg_cbe_in = pci_cbe_i ;
 
assign trdy_reg_o = in_reg_trdy_out ;
 
pci_in_reg input_register
(
.reset_in (reset),
.clk_in (pci_clk),
 
.pci_gnt_in (in_reg_gnt_in),
.pci_frame_in (in_reg_frame_in),
.pci_irdy_in (in_reg_irdy_in),
.pci_trdy_in (in_reg_trdy_in),
.pci_stop_in (in_reg_stop_in),
.pci_devsel_in (in_reg_devsel_in),
.pci_idsel_in (in_reg_idsel_in),
.pci_ad_in (in_reg_ad_in),
.pci_cbe_in (in_reg_cbe_in),
 
.pci_gnt_reg_out (in_reg_gnt_out),
.pci_frame_reg_out (in_reg_frame_out),
.pci_irdy_reg_out (in_reg_irdy_out),
.pci_trdy_reg_out (in_reg_trdy_out),
.pci_stop_reg_out (in_reg_stop_out),
.pci_devsel_reg_out (in_reg_devsel_out),
.pci_idsel_reg_out (in_reg_idsel_out),
.pci_ad_reg_out (in_reg_ad_out),
.pci_cbe_reg_out (in_reg_cbe_out)
);
 
endmodule
/verilog/pci_user_constants.v
0,0 → 1,238
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "pci_user_constants.v" ////
//// ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc (mihad@opencores.org) ////
//// - Tadej Markovic (tadej@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2003/03/14 15:31:57 mihad
// Entered the option to disable no response counter in wb master.
//
// Revision 1.7 2003/01/27 17:05:50 mihad
// Updated.
//
// Revision 1.6 2003/01/27 16:51:19 mihad
// Old files with wrong names removed.
//
// Revision 1.5 2003/01/21 16:06:56 mihad
// Bug fixes, testcases added.
//
// Revision 1.4 2002/09/30 17:22:45 mihad
// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
//
// Revision 1.3 2002/08/13 11:03:53 mihad
// Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image
//
// Revision 1.2 2002/03/05 11:53:47 mihad
// Added some testcases, removed un-needed fifo signals
//
// Revision 1.1 2002/02/01 14:43:31 mihad
// *** empty log message ***
//
//
 
// Fifo implementation defines:
// If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.
// 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),
// then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used
// If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations )
// If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with
// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
// WB_FIFO_RAM_ADDR_LENGTH.
 
`define WBW_ADDR_LENGTH 4
`define WBR_ADDR_LENGTH 4
`define PCIW_ADDR_LENGTH 4
`define PCIR_ADDR_LENGTH 4
 
`define FPGA
`define XILINX
 
//`define WB_RAM_DONT_SHARE
`define PCI_RAM_DONT_SHARE
 
`ifdef FPGA
`ifdef XILINX
`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
//`define PCI_XILINX_RAMB4
`define WB_XILINX_RAMB4
`define PCI_XILINX_DIST_RAM
//`define WB_XILINX_DIST_RAM
`endif
`else
`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
`define WB_FIFO_RAM_ADDR_LENGTH 7 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
// `define WB_ARTISAN_SDP
// `define PCI_ARTISAN_SDP
// `define PCI_VS_STP
// `define WB_VS_STP
`endif
 
// these two defines allow user to select active high or low output enables on PCI bus signals, depending on
// output buffers instantiated. Xilinx FPGAs use active low output enables.
`define ACTIVE_LOW_OE
//`define ACTIVE_HIGH_OE
 
// HOST/GUEST implementation selection - see design document and specification for description of each implementation
// only one can be defined at same time
//`define HOST
`define GUEST
 
// if NO_CNF_IMAGE is commented out, then READ-ONLY access to configuration space is ENABLED:
// - ENABLED Read-Only access from WISHBONE for GUEST bridges
// - ENABLED Read-Only access from PCI for HOST bridges
// with defining NO_CNF_IMAGE, one decoder and one multiplexer are saved
`define NO_CNF_IMAGE
 
// number defined here specifies how many MS bits in PCI address are compared with base address, to decode
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
// smaller the number here, faster the decoder operation
`define PCI_NUM_OF_DEC_ADDR_LINES 12
 
// no. of PCI Target IMAGES
// - PCI provides 6 base address registers for image implementation.
// PCI_IMAGE1 definition is not required and has no effect, since PCI image 1 is always implemented
// If GUEST is defined, PCI Image 0 is also always implemented and is used for configuration space
// access.
// If HOST is defined and NO_CNF_IMAGE is not, then PCI Image 0 is used for Read Only access to configuration
// space. If HOST is defined and NO_CNF_IMAGE is defined, then user can define PCI_IMAGE0 as normal image, and there
// is no access to Configuration space possible from PCI bus.
// Implementation of all other PCI images is selected by defining PCI_IMAGE2 through PCI_IMAGE5 regardles of HOST
// or GUEST implementation.
`ifdef HOST
`ifdef NO_CNF_IMAGE
`define PCI_IMAGE0
`endif
`endif
 
`define PCI_IMAGE2
//`define PCI_IMAGE3
//`define PCI_IMAGE4
//`define PCI_IMAGE5
 
// initial value for PCI image address masks. Address masks can be defined in enabled state,
// to allow device independent software to detect size of image and map base addresses to
// memory space. If initial mask for an image is defined as 0, then device independent software
// won't detect base address implemented and device dependent software will have to configure
// address masks as well as base addresses!
`define PCI_AM0 20'hffff_f
`define PCI_AM1 20'hffff_f
`define PCI_AM2 20'hffff_8
`define PCI_AM3 20'hffff_0
`define PCI_AM4 20'hfffe_0
`define PCI_AM5 20'h0000_0
 
// initial value for PCI image maping to MEMORY or IO spaces. If initial define is set to 0,
// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D
// Device independent software sets the base addresses acording to MEMORY or IO maping!
`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
`define PCI_BA1_MEM_IO 1'b0
`define PCI_BA2_MEM_IO 1'b0
`define PCI_BA3_MEM_IO 1'b1
`define PCI_BA4_MEM_IO 1'b0
`define PCI_BA5_MEM_IO 1'b1
 
// number defined here specifies how many MS bits in WB address are compared with base address, to decode
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
// smaller the number here, faster the decoder operation
`define WB_NUM_OF_DEC_ADDR_LINES 1
 
// no. of WISHBONE Slave IMAGES
// WB image 0 is always used for access to configuration space. In case configuration space access is not implemented,
// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
// WB Image 1 is always implemented and user doesnt need to specify its definition
// WB images' 2 through 5 implementation by defining each one.
`define WB_IMAGE2
//`define WB_IMAGE3
//`define WB_IMAGE4
//`define WB_IMAGE5
 
// If this define is commented out, then address translation will not be implemented.
// addresses will pass through bridge unchanged, regardles of address translation enable bits.
// Address translation also slows down the decoding
`define ADDR_TRAN_IMPL
 
// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
// slower decode speed can be used, to provide enough time for address to be decoded.
`define WB_DECODE_FAST
//`define WB_DECODE_MEDIUM
//`define WB_DECODE_SLOW
 
// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
`define WB_CONFIGURATION_BASE 20'hF300_0
 
// Turn registered WISHBONE slave outputs on or off
// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
// outputs to internals of the core.
//`define REGISTER_WBS_OUTPUTS
 
/*-----------------------------------------------------------------------------------------------------------
Core speed definition - used for simulation and 66MHz Capable bit value in status register indicating 66MHz
capable device
-----------------------------------------------------------------------------------------------------------*/
`define PCI33
//`define PCI66
 
/*-----------------------------------------------------------------------------------------------------------
[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
together by application.
-----------------------------------------------------------------------------------------------------------*/
`define HEADER_VENDOR_ID 16'h1895
`define HEADER_DEVICE_ID 16'h0001
`define HEADER_REVISION_ID 8'h01
 
// Turn registered WISHBONE master outputs on or off
// all outputs from WB Master state machine are registered, if this is defined - WB bus outputs as well as
// outputs to internals of the core.
`define REGISTER_WBM_OUTPUTS
 
// MAX Retry counter value for WISHBONE Master state-machine
// This value is 8-bit because of 8-bit retry counter !!!
`define WB_RTY_CNT_MAX 8'hff
 
// define the macro below to disable internal retry generation in the wishbone master interface
// used when wb master accesses extremly slow devices.
//`define PCI_WBM_NO_RESPONSE_CNT_DISABLE
verilog/pci_user_constants.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: verilog/pci_test_top_1clk.v =================================================================== --- verilog/pci_test_top_1clk.v (nonexistent) +++ verilog/pci_test_top_1clk.v (revision 154) @@ -0,0 +1,461 @@ +module pci_test_top +( + pci_clk_pad_i, + pci_rst_pad_i, + + pci_req_pad_o, + pci_gnt_pad_i, + pci_idsel_pad_i, + + pci_ad0_pad_io, + pci_ad1_pad_io, + pci_ad2_pad_io, + pci_ad3_pad_io, + pci_ad4_pad_io, + pci_ad5_pad_io, + pci_ad6_pad_io, + pci_ad7_pad_io, + pci_ad8_pad_io, + pci_ad9_pad_io, + pci_ad10_pad_io, + pci_ad11_pad_io, + pci_ad12_pad_io, + pci_ad13_pad_io, + pci_ad14_pad_io, + pci_ad15_pad_io, + pci_ad16_pad_io, + pci_ad17_pad_io, + pci_ad18_pad_io, + pci_ad19_pad_io, + pci_ad20_pad_io, + pci_ad21_pad_io, + pci_ad22_pad_io, + pci_ad23_pad_io, + pci_ad24_pad_io, + pci_ad25_pad_io, + pci_ad26_pad_io, + pci_ad27_pad_io, + pci_ad28_pad_io, + pci_ad29_pad_io, + pci_ad30_pad_io, + pci_ad31_pad_io, + + pci_cbe0_pad_io, + pci_cbe1_pad_io, + pci_cbe2_pad_io, + pci_cbe3_pad_io, + + pci_frame_pad_io, + pci_irdy_pad_io, + pci_devsel_pad_io, + pci_trdy_pad_io, + pci_stop_pad_io, + pci_par_pad_io, + pci_perr_pad_io, + pci_serr_pad_o +); + +// input/output inout declarations +input pci_clk_pad_i, + pci_rst_pad_i ; + +output pci_req_pad_o, pci_serr_pad_o ; +input pci_gnt_pad_i, + pci_idsel_pad_i ; + +inout pci_frame_pad_io, + pci_irdy_pad_io, + pci_devsel_pad_io, + pci_trdy_pad_io, + pci_stop_pad_io, + pci_par_pad_io, + pci_perr_pad_io, + pci_ad0_pad_io, + pci_ad1_pad_io, + pci_ad2_pad_io, + pci_ad3_pad_io, + pci_ad4_pad_io, + pci_ad5_pad_io, + pci_ad6_pad_io, + pci_ad7_pad_io, + pci_ad8_pad_io, + pci_ad9_pad_io, + pci_ad10_pad_io, + pci_ad11_pad_io, + pci_ad12_pad_io, + pci_ad13_pad_io, + pci_ad14_pad_io, + pci_ad15_pad_io, + pci_ad16_pad_io, + pci_ad17_pad_io, + pci_ad18_pad_io, + pci_ad19_pad_io, + pci_ad20_pad_io, + pci_ad21_pad_io, + pci_ad22_pad_io, + pci_ad23_pad_io, + pci_ad24_pad_io, + pci_ad25_pad_io, + pci_ad26_pad_io, + pci_ad27_pad_io, + pci_ad28_pad_io, + pci_ad29_pad_io, + pci_ad30_pad_io, + pci_ad31_pad_io, + pci_cbe0_pad_io, + pci_cbe1_pad_io, + pci_cbe2_pad_io, + pci_cbe3_pad_io ; + +// wires for test master to pci slave connections +wire wbm_test_wbs_pci_cyc, + wbm_test_wbs_pci_stb, + wbm_test_wbs_pci_cab, + wbm_test_wbs_pci_we, + wbs_pci_wbm_test_ack ; + +wire [31:0] wbm_test_wbs_pci_adr, + wbm_test_wbs_pci_dat, + wbs_pci_wbm_test_dat ; + +wire [3:0] wbm_test_wbs_pci_sel ; + +// wires for test slave to pci master connections +wire wbm_pci_wbs_test_cyc, + wbm_pci_wbs_test_stb, + wbm_pci_wbs_test_cab, + wbm_pci_wbs_test_we, + wbs_test_wbm_pci_ack ; + +wire [31:0] wbm_pci_wbs_test_adr, + wbm_pci_wbs_test_dat, + wbs_test_wbm_pci_dat ; + +wire [3:0] wbm_pci_wbs_test_sel ; + +wire wb_rst ; + +wire wb_clk = pci_clk_pad_i; + +// prevent concurent accesses through pci bridge master and slave interfaces +reg test_wbs_cyc ; +reg pci_wbs_cyc ; + +always@(posedge wb_clk or posedge wb_rst) +begin + if (wb_rst) + begin + test_wbs_cyc <= 1'b0 ; + pci_wbs_cyc <= 1'b0 ; + end + else + begin + if (~pci_wbs_cyc & ~test_wbs_cyc) + begin + // currently no cyc signal is asserted - the pci bridge wb master will have the priority here, so check if it has cycle asserted! + if (wbm_pci_wbs_test_cyc) + test_wbs_cyc <= 1'b1 ; + else // no cycle is asserted and pci wb master is not starting the transaction - test wb master can start + pci_wbs_cyc <= wbm_test_wbs_pci_cyc ; + end + else + begin + // at least one of the cycles is asserted - wait for transaction to finish + if (test_wbs_cyc) + test_wbs_cyc <= wbm_pci_wbs_test_cyc ; + + if (pci_wbs_cyc) + pci_wbs_cyc <= wbm_test_wbs_pci_cyc ; + end + end +end + +reg pci_irdy_reg, + pci_irdy_en_reg ; + +wire pci_trdy_reg = i_pci_bridge32.input_register.pci_trdy_reg_out ; + +always@(posedge pci_clk_pad_i or negedge pci_rst_pad_i) +begin + if (~pci_rst_pad_i) + begin + pci_irdy_reg <= 1'b1 ; + pci_irdy_en_reg <= 1'b0 ; + end + else + pci_irdy_reg <= i_pci_bridge32.output_backup.irdy_out ; + pci_irdy_en_reg <= i_pci_bridge32.output_backup.irdy_en_out ; + end +end + +test i_test +( + .clk_i (wb_clk), + .rst_i (wb_rst), + + .wbm_cyc_o (wbm_test_wbs_pci_cyc), + .wbm_stb_o (wbm_test_wbs_pci_stb), + .wbm_cab_o (wbm_test_wbs_pci_cab), + .wbm_we_o (wbm_test_wbs_pci_we), + .wbm_adr_o (wbm_test_wbs_pci_adr), + .wbm_sel_o (wbm_test_wbs_pci_sel), + .wbm_dat_o (wbm_test_wbs_pci_dat), + .wbm_dat_i (wbs_pci_wbm_test_dat), + .wbm_ack_i (wbs_pci_wbm_test_ack), + .wbm_rty_i (1'b0), + .wbm_err_i (1'b0), + + .wbs_cyc_i (test_wbs_cyc), + .wbs_stb_i (wbm_pci_wbs_test_stb), + .wbs_cab_i (wbm_pci_wbs_test_cab), + .wbs_we_i (wbm_pci_wbs_test_we), + .wbs_adr_i (wbm_pci_wbs_test_adr), + .wbs_sel_i (wbm_pci_wbs_test_sel), + .wbs_dat_i (wbm_pci_wbs_test_dat), + .wbs_dat_o (wbs_test_wbm_pci_dat), + .wbs_ack_o (wbs_test_wbm_pci_ack), + .wbs_rty_o (), + .wbs_err_o (), + + .pci_irdy_reg_i (pci_irdy_reg), + .pci_irdy_en_reg_i (pci_irdy_en_reg), + .pci_trdy_reg_i (pci_trdy_reg) +); + +wire pci_req_o, + pci_req_oe, + pci_frame_i, + pci_frame_o, + pci_frame_oe, + pci_irdy_oe, + pci_devsel_oe, + pci_trdy_oe, + pci_stop_oe, + pci_irdy_i, + pci_irdy_o, + pci_devsel_i, + pci_devsel_o, + pci_trdy_i, + pci_trdy_o, + pci_stop_i, + pci_stop_o, + pci_par_i, + pci_par_o, + pci_par_oe, + pci_perr_i, + pci_perr_o, + pci_perr_oe, + pci_serr_o, + pci_serr_oe +; + +wire [31:0] pci_ad_oe, + pci_ad_i, + pci_ad_o ; + +wire [3:0] pci_cbe_oe, + pci_cbe_i, + pci_cbe_o ; + +bufif0 ad_buffer00 (pci_ad0_pad_io , pci_ad_o[0] , pci_ad_oe[0] ) ; +bufif0 ad_buffer01 (pci_ad1_pad_io , pci_ad_o[1] , pci_ad_oe[1] ) ; +bufif0 ad_buffer02 (pci_ad2_pad_io , pci_ad_o[2] , pci_ad_oe[2] ) ; +bufif0 ad_buffer03 (pci_ad3_pad_io , pci_ad_o[3] , pci_ad_oe[3] ) ; +bufif0 ad_buffer04 (pci_ad4_pad_io , pci_ad_o[4] , pci_ad_oe[4] ) ; +bufif0 ad_buffer05 (pci_ad5_pad_io , pci_ad_o[5] , pci_ad_oe[5] ) ; +bufif0 ad_buffer06 (pci_ad6_pad_io , pci_ad_o[6] , pci_ad_oe[6] ) ; +bufif0 ad_buffer07 (pci_ad7_pad_io , pci_ad_o[7] , pci_ad_oe[7] ) ; +bufif0 ad_buffer08 (pci_ad8_pad_io , pci_ad_o[8] , pci_ad_oe[8] ) ; +bufif0 ad_buffer09 (pci_ad9_pad_io , pci_ad_o[9] , pci_ad_oe[9] ) ; +bufif0 ad_buffer10 (pci_ad10_pad_io, pci_ad_o[10], pci_ad_oe[10]) ; +bufif0 ad_buffer11 (pci_ad11_pad_io, pci_ad_o[11], pci_ad_oe[11]) ; +bufif0 ad_buffer12 (pci_ad12_pad_io, pci_ad_o[12], pci_ad_oe[12]) ; +bufif0 ad_buffer13 (pci_ad13_pad_io, pci_ad_o[13], pci_ad_oe[13]) ; +bufif0 ad_buffer14 (pci_ad14_pad_io, pci_ad_o[14], pci_ad_oe[14]) ; +bufif0 ad_buffer15 (pci_ad15_pad_io, pci_ad_o[15], pci_ad_oe[15]) ; +bufif0 ad_buffer16 (pci_ad16_pad_io, pci_ad_o[16], pci_ad_oe[16]) ; +bufif0 ad_buffer17 (pci_ad17_pad_io, pci_ad_o[17], pci_ad_oe[17]) ; +bufif0 ad_buffer18 (pci_ad18_pad_io, pci_ad_o[18], pci_ad_oe[18]) ; +bufif0 ad_buffer19 (pci_ad19_pad_io, pci_ad_o[19], pci_ad_oe[19]) ; +bufif0 ad_buffer20 (pci_ad20_pad_io, pci_ad_o[20], pci_ad_oe[20]) ; +bufif0 ad_buffer21 (pci_ad21_pad_io, pci_ad_o[21], pci_ad_oe[21]) ; +bufif0 ad_buffer22 (pci_ad22_pad_io, pci_ad_o[22], pci_ad_oe[22]) ; +bufif0 ad_buffer23 (pci_ad23_pad_io, pci_ad_o[23], pci_ad_oe[23]) ; +bufif0 ad_buffer24 (pci_ad24_pad_io, pci_ad_o[24], pci_ad_oe[24]) ; +bufif0 ad_buffer25 (pci_ad25_pad_io, pci_ad_o[25], pci_ad_oe[25]) ; +bufif0 ad_buffer26 (pci_ad26_pad_io, pci_ad_o[26], pci_ad_oe[26]) ; +bufif0 ad_buffer27 (pci_ad27_pad_io, pci_ad_o[27], pci_ad_oe[27]) ; +bufif0 ad_buffer28 (pci_ad28_pad_io, pci_ad_o[28], pci_ad_oe[28]) ; +bufif0 ad_buffer29 (pci_ad29_pad_io, pci_ad_o[29], pci_ad_oe[29]) ; +bufif0 ad_buffer30 (pci_ad30_pad_io, pci_ad_o[30], pci_ad_oe[30]) ; +bufif0 ad_buffer31 (pci_ad31_pad_io, pci_ad_o[31], pci_ad_oe[31]) ; + +bufif0 cbe_buffer0 (pci_cbe0_pad_io, pci_cbe_o[0], pci_cbe_oe[0]) ; +bufif0 cbe_buffer1 (pci_cbe1_pad_io, pci_cbe_o[1], pci_cbe_oe[1]) ; +bufif0 cbe_buffer2 (pci_cbe2_pad_io, pci_cbe_o[2], pci_cbe_oe[2]) ; +bufif0 cbe_buffer3 (pci_cbe3_pad_io, pci_cbe_o[3], pci_cbe_oe[3]) ; + +assign pci_ad_i = { + pci_ad31_pad_io, + pci_ad30_pad_io, + pci_ad29_pad_io, + pci_ad28_pad_io, + pci_ad27_pad_io, + pci_ad26_pad_io, + pci_ad25_pad_io, + pci_ad24_pad_io, + pci_ad23_pad_io, + pci_ad22_pad_io, + pci_ad21_pad_io, + pci_ad20_pad_io, + pci_ad19_pad_io, + pci_ad18_pad_io, + pci_ad17_pad_io, + pci_ad16_pad_io, + pci_ad15_pad_io, + pci_ad14_pad_io, + pci_ad13_pad_io, + pci_ad12_pad_io, + pci_ad11_pad_io, + pci_ad10_pad_io, + pci_ad9_pad_io, + pci_ad8_pad_io, + pci_ad7_pad_io, + pci_ad6_pad_io, + pci_ad5_pad_io, + pci_ad4_pad_io, + pci_ad3_pad_io, + pci_ad2_pad_io, + pci_ad1_pad_io, + pci_ad0_pad_io +} ; + +assign pci_cbe_i = { + pci_cbe3_pad_io, + pci_cbe2_pad_io, + pci_cbe1_pad_io, + pci_cbe0_pad_io +} ; + +bufif0 req_buf (pci_req_pad_o, pci_req_o, pci_req_oe) ; + +bufif0 frame_buf (pci_frame_pad_io, pci_frame_o, pci_frame_oe) ; +assign pci_frame_i = pci_frame_pad_io ; + +bufif0 irdy_buf (pci_irdy_pad_io, pci_irdy_o, pci_irdy_oe) ; +assign pci_irdy_i = pci_irdy_pad_io ; + +bufif0 devsel_buf (pci_devsel_pad_io, pci_devsel_o, pci_devsel_oe) ; +assign pci_devsel_i = pci_devsel_pad_io ; + +bufif0 trdy_buf (pci_trdy_pad_io, pci_trdy_o, pci_trdy_oe) ; +assign pci_trdy_i = pci_trdy_pad_io ; + +bufif0 stop_buf (pci_stop_pad_io, pci_stop_o, pci_stop_oe) ; +assign pci_stop_i = pci_stop_pad_io ; + +bufif0 par_buf (pci_par_pad_io, pci_par_o, pci_par_oe) ; +assign pci_par_i = pci_par_pad_io ; + +bufif0 perr_buf (pci_perr_pad_io, pci_perr_o, pci_perr_oe) ; +assign pci_perr_i = pci_perr_pad_io ; + +bufif0 serr_buf (pci_serr_pad_o, pci_serr_o, pci_serr_oe) ; + +pci_bridge32 i_pci_bridge32 +( + // WISHBONE system signals + .wb_clk_i(wb_clk), + .wb_rst_i(1'b0), + .wb_rst_o(wb_rst), + .wb_int_i(1'b0), + .wb_int_o(), + + // WISHBONE slave interface + .wbs_adr_i(wbm_test_wbs_pci_adr), + .wbs_dat_i(wbm_test_wbs_pci_dat), + .wbs_dat_o(wbs_pci_wbm_test_dat), + .wbs_sel_i(wbm_test_wbs_pci_sel), + .wbs_cyc_i(pci_wbs_cyc), + .wbs_stb_i(wbm_test_wbs_pci_stb), + .wbs_we_i (wbm_test_wbs_pci_we), + .wbs_cab_i(wbm_test_wbs_pci_cab), + .wbs_ack_o(wbs_pci_wbm_test_ack), + .wbs_rty_o(), + .wbs_err_o(), + + // WISHBONE master interface + .wbm_adr_o(wbm_pci_wbs_test_adr), + .wbm_dat_i(wbs_test_wbm_pci_dat), + .wbm_dat_o(wbm_pci_wbs_test_dat), + .wbm_sel_o(wbm_pci_wbs_test_sel), + .wbm_cyc_o(wbm_pci_wbs_test_cyc), + .wbm_stb_o(wbm_pci_wbs_test_stb), + .wbm_we_o (wbm_pci_wbs_test_we), + .wbm_cab_o(wbm_pci_wbs_test_cab), + .wbm_ack_i(wbs_test_wbm_pci_ack), + .wbm_rty_i(1'b0), + .wbm_err_i(1'b0), + + // pci interface - system pins + .pci_clk_i (pci_clk_pad_i), + .pci_rst_i (pci_rst_pad_i), + .pci_rst_o (), + .pci_inta_i (1'b1), + .pci_inta_o (), + .pci_rst_oe_o (), + .pci_inta_oe_o (), + + // arbitration pins + .pci_req_o (pci_req_o), + .pci_req_oe_o (pci_req_oe), + + .pci_gnt_i (pci_gnt_pad_i), + + // protocol pins + .pci_frame_i (pci_frame_i), + .pci_frame_o (pci_frame_o), + + .pci_frame_oe_o (pci_frame_oe), + .pci_irdy_oe_o (pci_irdy_oe), + .pci_devsel_oe_o(pci_devsel_oe), + .pci_trdy_oe_o (pci_trdy_oe), + .pci_stop_oe_o (pci_stop_oe), + .pci_ad_oe_o (pci_ad_oe), + .pci_cbe_oe_o (pci_cbe_oe), + + .pci_irdy_i (pci_irdy_i), + .pci_irdy_o (pci_irdy_o), + + .pci_idsel_i (pci_idsel_pad_i), + + .pci_devsel_i (pci_devsel_i), + .pci_devsel_o (pci_devsel_o), + + .pci_trdy_i (pci_trdy_i), + .pci_trdy_o (pci_trdy_o), + + .pci_stop_i (pci_stop_i), + .pci_stop_o (pci_stop_o), + + // data transfer pins + .pci_ad_i (pci_ad_i), + .pci_ad_o (pci_ad_o), + + .pci_cbe_i (pci_cbe_i), + .pci_cbe_o (pci_cbe_o), + + // parity generation and checking pins + .pci_par_i (pci_par_i), + .pci_par_o (pci_par_o), + .pci_par_oe_o (pci_par_oe), + + .pci_perr_i (pci_perr_i), + .pci_perr_o (pci_perr_o), + .pci_perr_oe_o (pci_perr_oe), + + // system error pin + .pci_serr_o (pci_serr_o), + .pci_serr_oe_o (pci_serr_oe) +); +endmodule // pci_test_top
verilog/pci_test_top_1clk.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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