URL
https://opencores.org/ocsvn/pci/pci/trunk
Subversion Repositories pci
Compare Revisions
- This comparison shows the changes necessary to convert path
/pci/tags/rel_7/sim/rtl_sim/run
- from Rev 114 to Rev 154
- ↔ Reverse comparison
Rev 114 → Rev 154
/ncvlog.args
0,0 → 1,90
-cdslib ../bin/cds.lib |
-hdlvar ../bin/hdl.var |
-logfile ../log/ncvlog.log |
-update |
-messages |
-INCDIR ../../../bench/verilog |
-INCDIR ../../../rtl/verilog |
-DEFINE REGRESSION |
-DEFINE REGR_FIFO_SMALL_GENERIC |
-DEFINE GUEST |
-DEFINE WB_DECODE_FAST |
-DEFINE PCI_DECODE_MAX |
-DEFINE WB_DECODE_MED |
-DEFINE PCI66 |
-DEFINE WB_CLK66 |
-DEFINE ACTIVE_HIGH_OE |
-DEFINE WB_CNF_BASE_ZERO |
-DEFINE NO_CNF_IMAGE |
-DEFINE PCI_CLOCK_FOLLOWS_WB_CLOCK=2 |
-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS |
../../../rtl/verilog/pci_parity_check.v |
../../../rtl/verilog/pci_target_unit.v |
../../../rtl/verilog/pci_wb_addr_mux.v |
../../../rtl/verilog/pci_cbe_en_crit.v |
../../../rtl/verilog/pci_pcir_fifo_control.v |
../../../rtl/verilog/pci_out_reg.v |
../../../rtl/verilog/pci_pci_tpram.v |
../../../rtl/verilog/pci_wb_master.v |
../../../rtl/verilog/pci_conf_cyc_addr_dec.v |
../../../rtl/verilog/pci_frame_crit.v |
../../../rtl/verilog/pci_target32_clk_en.v |
../../../rtl/verilog/pci_pciw_fifo_control.v |
../../../rtl/verilog/pci_wb_slave.v |
../../../rtl/verilog/pci_conf_space.v |
../../../rtl/verilog/pci_frame_en_crit.v |
../../../rtl/verilog/pci_par_crit.v |
../../../rtl/verilog/pci_pciw_pcir_fifos.v |
../../../rtl/verilog/pci_wb_slave_unit.v |
../../../rtl/verilog/pci_frame_load_crit.v |
../../../rtl/verilog/pci_bridge32.v |
../../../rtl/verilog/pci_target32_devs_crit.v |
../../../rtl/verilog/pci_perr_crit.v |
../../../rtl/verilog/pci_wbr_fifo_control.v |
../../../rtl/verilog/pci_cur_out_reg.v |
../../../rtl/verilog/pci_pci_decoder.v |
../../../rtl/verilog/pci_target32_interface.v |
../../../rtl/verilog/pci_perr_en_crit.v |
../../../rtl/verilog/pci_wbw_fifo_control.v |
../../../rtl/verilog/pci_wb_decoder.v |
../../../rtl/verilog/pci_in_reg.v |
../../../rtl/verilog/pci_serr_crit.v |
../../../rtl/verilog/pci_wbw_wbr_fifos.v |
../../../rtl/verilog/pci_delayed_sync.v |
../../../rtl/verilog/pci_irdy_out_crit.v |
../../../rtl/verilog/pci_io_mux.v |
../../../rtl/verilog/pci_io_mux_ad_en_crit.v |
../../../rtl/verilog/pci_io_mux_ad_load_crit.v |
../../../rtl/verilog/pci_target32_sm.v |
../../../rtl/verilog/pci_serr_en_crit.v |
../../../rtl/verilog/pci_delayed_write_reg.v |
../../../rtl/verilog/pci_mas_ad_en_crit.v |
../../../rtl/verilog/pci_mas_ad_load_crit.v |
../../../rtl/verilog/pci_master32_sm.v |
../../../rtl/verilog/pci_target32_stop_crit.v |
../../../rtl/verilog/synchronizer_flop.v |
../../../rtl/verilog/pci_async_reset_flop.v |
../../../rtl/verilog/pci_mas_ch_state_crit.v |
../../../rtl/verilog/pci_master32_sm_if.v |
../../../rtl/verilog/pci_target32_trdy_crit.v |
../../../rtl/verilog/top.v |
../../../rtl/verilog/pci_rst_int.v |
../../../rtl/verilog/pci_sync_module.v |
../../../rtl/verilog/pci_wb_tpram.v |
../../../rtl/verilog/pci_wbs_wbb3_2_wbb2.v |
../../../bench/verilog/wb_master32.v |
../../../bench/verilog/wb_master_behavioral.v |
../../../bench/verilog/system.v |
../../../bench/verilog/pci_blue_arbiter.v |
../../../bench/verilog/pci_bus_monitor.v |
../../../bench/verilog/pci_behaviorial_device.v |
../../../bench/verilog/pci_behaviorial_master.v |
../../../bench/verilog/pci_behaviorial_target.v |
../../../bench/verilog/wb_slave_behavioral.v |
../../../bench/verilog/wb_bus_mon.v |
../../../bench/verilog/pci_unsupported_commands_master.v |
../../../bench/verilog/pci_behavioral_pci2pci_bridge.v |
../../../../../../lib/xilinx/lib/glbl/glbl.v |
../../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v |
../../../../../../lib/xilinx/lib/unisims/RAM16X1D.v |
../../../rtl/verilog/pci_ram_16x40d.v |
ncvlog.args
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: run_pci_sim_regr.scr
===================================================================
--- run_pci_sim_regr.scr (nonexistent)
+++ run_pci_sim_regr.scr (revision 154)
@@ -0,0 +1,705 @@
+#!/bin/csh -f
+
+set arg_num = $#argv; # number of arguments
+
+# current iterration
+set iter = 1;
+# number of tests with DEFINES + test with user defined constants!
+set all_iterations = 14;
+
+# variables
+set iter_failed = 0;
+set all_iters = 0;
+set subtest_failed = 0;
+set sub_tests = 0;
+set test_failed = 0;
+set all_tests = 0;
+
+# Process arguments
+set arg_regression = 0;
+set arg_xilinx = 0;
+set arg_artisan = 0;
+set arg_waves = 0;
+set arg_vs_hdtp = 0
+set arg_dis_comp_exp_test = 0
+set arg_wb_b3 = 0
+set arg_wbs_non_alligned = 0
+
+@ arg_num = 1
+set arg_check = 0
+
+while($arg_num <= $#)
+
+ switch ( $argv[$arg_num] )
+ case "help":
+ goto help
+ breaksw
+
+ case "regression":
+ @ arg_regression = 1
+ breaksw
+
+ case "xilinx":
+ @ arg_xilinx = 1
+ breaksw
+
+ case "artisan":
+ @ arg_artisan = 1
+ breaksw
+
+ case "waves":
+ @ arg_waves = 1
+ breaksw
+
+ case "vs_two_port":
+ @ arg_vs_hdtp = 1
+ breaksw
+
+ case "disable_completion_expired_tests":
+ @ arg_dis_comp_exp_test = 1
+ breaksw
+
+ case "wb_b3":
+ @ arg_wb_b3 = 1
+ breaksw
+
+ case "wb_na":
+ @ arg_wbs_non_alligned = 1
+ breaksw
+
+ case "iter":
+ @ arg_num = $arg_num + 1
+ @ iter = $argv[$arg_num]
+ @ all_iterations = $iter
+ breaksw
+
+ default:
+ echo "Invalid argument!"
+ goto help
+ breaksw
+ endsw
+
+ @ arg_num++
+end
+
+# ITERATION LOOP
+iteration:
+
+echo ""
+echo "<<<"
+echo "<<< Iteration ${iter}"
+echo "<<<"
+
+
+if ($arg_regression == 1) then
+ # Preparing defines into file
+ if ($iter <= $all_iterations) then
+
+ if ($iter == 1) then
+ echo "<<< Defines:"
+
+ if ($arg_xilinx == 0) then
+ echo "\tREGR_FIFO_SMALL_GENERIC, "
+ else
+ echo "\tREGR_FIFO_SMALL_XILINX, "
+ endif
+
+ echo "\tHOST, WB_DECODE_FAST, PCI_DECODE_MAX, "
+ echo "\tWB_DECODE_MIN, PCI33, WB_CLK10, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
+ echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ if ($arg_xilinx == 0) then
+ echo "-DEFINE REGR_FIFO_SMALL_GENERIC" >> ./defines.args
+ else
+ echo "-DEFINE REGR_FIFO_SMALL_XILINX" >> ./defines.args
+ endif
+
+ echo "-DEFINE HOST " >> ./defines.args
+ echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE PCI33 " >> ./defines.args
+ echo "-DEFINE WB_CLK10 " >> ./defines.args
+ echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
+ echo "-DEFINE REGISTER_WBM_OUTPUTS" >> ./defines.args
+ echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
+ echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE2 " >> ./defines.args
+
+ endif
+
+ if ($iter == 2) then
+
+ echo "<<< Defines:"
+
+ if ($arg_xilinx == 1) then
+ echo "\tREGR_FIFO_MEDIUM_XILINX, "
+ else if ($arg_artisan == 1) then
+ echo "\tREGR_FIFO_MEDIUM_ARTISAN, "
+ else
+ echo "\tREGR_FIFO_MEDIUM_GENERIC, "
+ endif
+
+ echo "\tHOST, WB_DECODE_MEDIUM, PCI_DECODE_MED, "
+ echo "\tWB_DECODE_MED, PCI33, WB_CLK66, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
+ echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2, "
+ echo "\tPCI_IMAGE3, PCI_IMAGE4, PCI_IMAGE5, WB_IMAGE2, WB_IMAGE5. "
+
+ echo "-DEFINE REGRESSION " > ./defines.args
+
+ if ($arg_xilinx == 1) then
+ echo "-DEFINE REGR_FIFO_MEDIUM_XILINX" >> ./defines.args
+ else if ($arg_artisan == 1) then
+ echo "-DEFINE REGR_FIFO_MEDIUM_ARTISAN" >> ./defines.args
+ else
+ echo "-DEFINE REGR_FIFO_MEDIUM_GENERIC" >> ./defines.args
+ endif
+
+ echo "-DEFINE HOST " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MED " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MED " >> ./defines.args
+ echo "-DEFINE PCI33 " >> ./defines.args
+ echo "-DEFINE WB_CLK66 " >> ./defines.args
+ echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
+ echo "-DEFINE REGISTER_WBM_OUTPUTS" >> ./defines.args
+ echo "-DEFINE REGISTER_WBS_OUTPUTS" >> ./defines.args
+ echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE2 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE3 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE4 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE5 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE2 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE5 " >> ./defines.args
+
+ endif
+
+ if ($iter == 3) then
+ echo "<<< Defines:"
+ echo "\tHOST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MIN, "
+ echo "\tWB_DECODE_MAX, PCI66, WB_CLK66, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
+ echo "\tREGISTER_WBS_OUTPUTS, WB_IMAGE5. "
+
+ echo "-DEFINE REGRESSION " > ./defines.args
+
+ echo "-DEFINE HOST " >> ./defines.args
+ echo "-DEFINE REGR_FIFO_LARGE_GENERIC" >> ./defines.args
+ echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK66 " >> ./defines.args
+ echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
+ echo "-DEFINE REGISTER_WBM_OUTPUTS " >> ./defines.args
+ echo "-DEFINE REGISTER_WBS_OUTPUTS " >> ./defines.args
+ echo "-DEFINE WB_IMAGE5 " >> ./defines.args
+
+ endif
+
+ if ($iter == 4) then
+ echo "<<< Defines:"
+ echo "\tGUEST, REGR_FIFO_SMALL_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MED, "
+ echo "\tWB_DECODE_MIN, PCI66, WB_CLK220, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
+ echo "\tREGISTER_WBS_OUTPUTS, PCI_IMAGE0, PCI_IMAGE5, WB_IMAGE4. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE REGR_FIFO_SMALL_GENERIC" >> ./defines.args
+ echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MED " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK220 " >> ./defines.args
+ echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
+ echo "-DEFINE REGISTER_WBM_OUTPUTS " >> ./defines.args
+ echo "-DEFINE REGISTER_WBS_OUTPUTS " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE5 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE4 " >> ./defines.args
+ endif
+
+ if ($iter == 5) then
+ echo "<<< Defines:"
+
+ if ($arg_artisan == 1) then
+ echo "\tREGR_FIFO_MEDIUM_ARTISAN, "
+ else
+ echo "\tREGR_FIFO_MEDIUM_GENERIC, "
+ endif
+
+ echo "\tGUEST, WB_DECODE_FAST, PCI_DECODE_MIN, "
+ echo "\tWB_DECODE_MAX, PCI33, WB_CLK220, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
+ echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL, PCI_IMAGE0, PCI_IMAGE2, "
+ echo "\tWB_IMAGE2, WB_IMAGE3, WB_IMAGE4. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ if ($arg_artisan == 1) then
+ echo "-DEFINE REGR_FIFO_MEDIUM_ARTISAN" >> ./defines.args
+ else
+ echo "-DEFINE REGR_FIFO_MEDIUM_GENERIC" >> ./defines.args
+ endif
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE PCI33 " >> ./defines.args
+ echo "-DEFINE WB_CLK220 " >> ./defines.args
+ echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
+ echo "-DEFINE REGISTER_WBM_OUTPUTS " >> ./defines.args
+ echo "-DEFINE REGISTER_WBS_OUTPUTS " >> ./defines.args
+ echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE2 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE2 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE3 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE4 " >> ./defines.args
+ endif
+
+ if ($iter == 6) then
+ echo "<<< Defines:"
+ echo "\tGUEST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MAX, "
+ echo "\tWB_DECODE_MED, PCI66, WB_CLK10, ACTIVE_LOW_OE, REGISTER_WBM_OUTPUTS, "
+ echo "\tREGISTER_WBS_OUTPUTS, ADDR_TRAN_IMPL. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE REGR_FIFO_LARGE_GENERIC" >> ./defines.args
+ echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MED " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK10 " >> ./defines.args
+ echo "-DEFINE ACTIVE_LOW_OE " >> ./defines.args
+ echo "-DEFINE REGISTER_WBM_OUTPUTS " >> ./defines.args
+ echo "-DEFINE REGISTER_WBS_OUTPUTS " >> ./defines.args
+ echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
+ endif
+
+ if ($iter == 7) then
+ echo "<<< Defines:"
+
+ if ($arg_xilinx == 0) then
+ echo "\tREGR_FIFO_SMALL_GENERIC, "
+ else
+ echo "\tREGR_FIFO_SMALL_XILINX, "
+ endif
+
+ echo "\tHOST, WB_DECODE_FAST, PCI_DECODE_MAX, "
+ echo "\tWB_DECODE_MIN, PCI66, WB_CLK220, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
+ echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE4. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ if ($arg_xilinx == 0) then
+ echo "-DEFINE REGR_FIFO_SMALL_GENERIC" >> ./defines.args
+ else
+ echo "-DEFINE REGR_FIFO_SMALL_XILINX" >> ./defines.args
+ endif
+
+ echo "-DEFINE HOST " >> ./defines.args
+ echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK220 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO" >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE4 " >> ./defines.args
+ endif
+
+ if ($iter == 8) then
+ echo "<<< Defines:"
+ echo "\tHOST, REGR_FIFO_MEDIUM_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MED, "
+ echo "\tWB_DECODE_MED, PCI66, WB_CLK10, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
+ echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE2, PCI_IMAGE3, PCI_IMAGE4, "
+ echo "\tPCI_IMAGE5, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ echo "-DEFINE HOST " >> ./defines.args
+ echo "-DEFINE REGR_FIFO_MEDIUM_GENERIC" >> ./defines.args
+ echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MED " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MED " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK10 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO " >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE2 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE3 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE4 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE5 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE2 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE3 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE4 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE5 " >> ./defines.args
+ endif
+
+ if ($iter == 9) then
+ echo "<<< Defines:"
+ echo "\tHOST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MIN, "
+ echo "\tWB_DECODE_MAX, PCI33, WB_CLK220, ACTIVE_HIGH_OE, ADDR_TRAN_IMPL, "
+ echo "\tWB_CNF_BASE_ZERO, NO_CNF_IMAGE, WB_IMAGE3. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ echo "-DEFINE HOST " >> ./defines.args
+ echo "-DEFINE REGR_FIFO_LARGE_GENERIC" >> ./defines.args
+ echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE PCI33 " >> ./defines.args
+ echo "-DEFINE WB_CLK220 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO " >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE WB_IMAGE3 " >> ./defines.args
+ endif
+
+ if ($iter == 10) then
+ echo "<<< Defines:"
+ echo "\tGUEST, REGR_FIFO_SMALL_GENERIC, WB_DECODE_SLOW, PCI_DECODE_MED, "
+ echo "\tWB_DECODE_MIN, PCI33, WB_CLK66, ACTIVE_HIGH_OE, ADDR_TRAN_IMPL, "
+ echo "\tWB_CNF_BASE_ZERO, NO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE3. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE REGR_FIFO_SMALL_GENERIC" >> ./defines.args
+ echo "-DEFINE WB_DECODE_SLOW " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MED " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE PCI33 " >> ./defines.args
+ echo "-DEFINE WB_CLK66 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE ADDR_TRAN_IMPL " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO " >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE3 " >> ./defines.args
+ endif
+
+ if ($iter == 11) then
+ echo "<<< Defines:"
+
+ if ($arg_xilinx == 1) then
+ echo "\tREGR_FIFO_MEDIUM_XILINX, "
+ else if ($arg_artisan == 1) then
+ echo "\tREGR_FIFO_MEDIUM_ARTISAN, "
+ else
+ echo "\tREGR_FIFO_MEDIUM_GENERIC, "
+ endif
+
+ echo "\tGUEST, WB_DECODE_FAST, PCI_DECODE_MIN, "
+ echo "\tWB_DECODE_MAX, PCI66, WB_CLK66, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
+ echo "\tNO_CNF_IMAGE, PCI_IMAGE0, PCI_IMAGE2, PCI_IMAGE3, PCI_IMAGE4, "
+ echo "\tPCI_IMAGE5, WB_IMAGE2. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ if ($arg_xilinx == 1) then
+ echo "-DEFINE REGR_FIFO_MEDIUM_XILINX" >> ./defines.args
+ else if ($arg_artisan == 1) then
+ echo "-DEFINE REGR_FIFO_MEDIUM_ARTISAN" >> ./defines.args
+ else
+ echo "-DEFINE REGR_FIFO_MEDIUM_GENERIC" >> ./defines.args
+ endif
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MIN " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK66 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO" >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE0 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE2 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE3 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE4 " >> ./defines.args
+ echo "-DEFINE PCI_IMAGE5 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE2 " >> ./defines.args
+ endif
+
+ if ($iter == 12) then
+ echo "<<< Defines:"
+ echo "\tGUEST, REGR_FIFO_LARGE_GENERIC, WB_DECODE_MEDIUM, PCI_DECODE_MAX, "
+ echo "\tWB_DECODE_MED, PCI33, WB_CLK10, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
+ echo "\tNO_CNF_IMAGE, WB_IMAGE2, WB_IMAGE3, WB_IMAGE4, WB_IMAGE5. "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE REGR_FIFO_LARGE_GENERIC" >> ./defines.args
+ echo "-DEFINE WB_DECODE_MEDIUM " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MED " >> ./defines.args
+ echo "-DEFINE PCI33 " >> ./defines.args
+ echo "-DEFINE WB_CLK10 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO " >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE WB_IMAGE2 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE3 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE4 " >> ./defines.args
+ echo "-DEFINE WB_IMAGE5 " >> ./defines.args
+
+ endif
+
+ if ($iter == 13) then
+
+ echo "<<< Defines:"
+
+ if ($arg_xilinx == 0) then
+ echo "\tREGR_FIFO_SMALL_GENERIC, "
+ else
+ echo "\tREGR_FIFO_SMALL_XILINX, "
+ endif
+
+ echo "\tGUEST, WB_DECODE_FAST, PCI_DECODE_MAX, "
+ echo "\tWB_DECODE_MED, PCI66, WB_CLOCK_FOLLOWS_PCI_CLOCK, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
+ echo "\tNO_CNF_IMAGE "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ if ($arg_xilinx == 0) then
+ echo "-DEFINE REGR_FIFO_SMALL_GENERIC" >> ./defines.args
+ else
+ echo "-DEFINE REGR_FIFO_SMALL_XILINX" >> ./defines.args
+ endif
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MED " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK66 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO " >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE WB_CLOCK_FOLLOWS_PCI_CLOCK=2" >> ./defines.args
+
+ endif
+
+ if ($iter == 14) then
+
+ echo "<<< Defines:"
+
+ echo "\tREGR_FIFO_SMALL_GENERIC, "
+
+ echo "\tGUEST, WB_DECODE_FAST, PCI_DECODE_MAX, "
+ echo "\tWB_DECODE_MED, PCI66, WB_CLOCK_FOLLOWS_PCI_CLOCK, ACTIVE_HIGH_OE, WB_CNF_BASE_ZERO, "
+ echo "\tNO_CNF_IMAGE "
+
+ echo "-DEFINE REGRESSION" > ./defines.args
+
+ echo "-DEFINE REGR_FIFO_SMALL_GENERIC" >> ./defines.args
+
+ echo "-DEFINE GUEST " >> ./defines.args
+ echo "-DEFINE WB_DECODE_FAST " >> ./defines.args
+ echo "-DEFINE PCI_DECODE_MAX " >> ./defines.args
+ echo "-DEFINE WB_DECODE_MED " >> ./defines.args
+ echo "-DEFINE PCI66 " >> ./defines.args
+ echo "-DEFINE WB_CLK66 " >> ./defines.args
+ echo "-DEFINE ACTIVE_HIGH_OE " >> ./defines.args
+ echo "-DEFINE WB_CNF_BASE_ZERO " >> ./defines.args
+ echo "-DEFINE NO_CNF_IMAGE " >> ./defines.args
+ echo "-DEFINE PCI_CLOCK_FOLLOWS_WB_CLOCK=2" >> ./defines.args
+
+ endif
+
+ if ($arg_dis_comp_exp_test) then
+ echo "-DEFINE DISABLE_COMPLETION_EXPIRED_TESTS" >> ./defines.args
+ endif
+
+ if ($arg_wb_b3) then
+ echo "-DEFINE PCI_WB_REV_B3" >> ./defines.args
+ endif
+
+ if ($arg_wbs_non_alligned) then
+ echo "-DEFINE PCI_WBS_ALLOW_NON_ALLIGNED_CONFIG_ACCESS" >> ./defines.args
+ endif
+
+ endif
+endif
+
+
+# Run NC-Verilog compiler
+echo ""
+echo "\t@@@"
+echo "\t@@@ Compiling sources"
+echo "\t@@@"
+
+# creating .args file for ncvlog and adding main parameters
+echo "-cdslib ../bin/cds.lib" > ./ncvlog.args
+echo "-hdlvar ../bin/hdl.var" >> ./ncvlog.args
+echo "-logfile ../log/ncvlog.log" >> ./ncvlog.args
+echo "-update" >> ./ncvlog.args
+echo "-messages" >> ./ncvlog.args
+echo "-INCDIR ../../../bench/verilog" >> ./ncvlog.args
+echo "-INCDIR ../../../rtl/verilog" >> ./ncvlog.args
+# adding defines to .args file
+if (($arg_regression == 1) && ($iter <= $all_iterations)) then
+ cat ./defines.args >> ./ncvlog.args
+endif
+# adding RTL and Sim files to .args file
+cat ../bin/rtl_file_list.lst >> ./ncvlog.args
+cat ../bin/sim_file_list.lst >> ./ncvlog.args
+# adding device dependent files to .args file
+if ($arg_xilinx == 1) then
+ cat ../bin/xilinx_file_list.lst >> ./ncvlog.args
+endif
+
+if ($arg_artisan == 1) then
+ cat ../bin/artisan_file_list.lst >> ./ncvlog.args
+endif
+
+if ($arg_vs_hdtp == 1) then
+ cat ../bin/vs_file_list.lst >> ./ncvlog.args
+endif
+
+ncvlog -file ./ncvlog.args > /dev/null;
+echo ""
+
+
+# Run the NC-Verilog elaborator (build the design hierarchy)
+echo ""
+echo "\t@@@"
+echo "\t@@@ Building design hierarchy (elaboration)"
+echo "\t@@@"
+if ($arg_xilinx == 1) then
+ ncelab -file ../bin/ncelab_xilinx.args > /dev/null;
+else
+ ncelab -file ../bin/ncelab.args > /dev/null;
+endif
+echo ""
+
+
+# Run the NC-Verilog simulator (simulate the design)
+echo ""
+echo "\t###"
+echo "\t### Running tests (this takes a long time!)"
+echo "\t###"
+
+# creating ncsim.args file for ncsim and adding main parameters
+echo "-cdslib ../bin/cds.lib" > ./ncsim.args
+echo "-hdlvar ../bin/hdl.var" >> ./ncsim.args
+echo "-licqueue" >> ./ncsim.args
+echo "-logfile ../log/ncsim.log" >> ./ncsim.args
+echo "-messages" >> ./ncsim.args
+echo "-tcl" >> ./ncsim.args
+if ($arg_waves == 1) then
+ echo "-input ../bin/ncsim_waves.rc" >> ./ncsim.args
+else
+ echo "-input ../bin/ncsim.rc" >> ./ncsim.args
+endif
+echo "worklib.bridge32:fun" >> ./ncsim.args
+
+ncsim -file ./ncsim.args > /dev/null
+
+if ($status != 0) then
+ echo ""
+ echo "TESTS couldn't start due to Errors!"
+ echo ""
+ exit
+else
+ grep -c "FAILED" ../log/pci_tb.log > ./result_fail.out
+ grep -c "SUCCESSFULL" ../log/pci_tb.log > ./result_succ.out
+
+ set subtest_failed = `tail -1 result_fail.out`;
+ set sub_tests = `tail -1 result_succ.out`;
+ @ sub_tests = $sub_tests + $subtest_failed;
+
+ if ($subtest_failed != 0) then
+ echo "\t### FAILED $subtest_failed out of $sub_tests testcases of $iter. iteration!"
+ echo "\t###"
+ @ iter_failed += 1;
+ @ all_iters += 1;
+ else
+ echo "\t### Passed all $sub_tests testcases of $iter. iteration!"
+ echo "\t###"
+ @ all_iters += 1;
+ endif
+
+ if (($arg_regression == 1) && ($iter <= $all_iterations)) then
+ if ($arg_waves == 1) then
+ mv ../out/waves.shm ../out/i${iter}_waves.shm
+ endif
+ mv ../log/pci_mon.log ../log/i${iter}_pci_mon.log
+ mv ../log/pci_tb.log ../log/i${iter}_pci_tb.log
+ mv ../log/pciu_mon.log ../log/i${iter}_pciu_mon.log
+ mv ../log/wbu_mon.log ../log/i${iter}_wbu_mon.log
+ mv ../log/ncsim.log ../log/i${iter}_ncsim.log
+ mv ../log/ncvlog.log ../log/i${iter}_ncvlog.log
+ mv ../log/ncelab.log ../log/i${iter}_ncelab.log
+ endif
+endif
+echo ""
+
+@ test_failed = $test_failed + $subtest_failed;
+@ all_tests = $all_tests + $sub_tests;
+
+@ iter += 1;
+
+if (($arg_regression == 1) && ($iter <= $all_iterations)) then
+ rm -f ../bin/INCA_libs/worklib/*
+ rm -f ../bin/INCA_libs/worklib/.*
+ goto iteration
+else
+ rm ./defines.args
+ echo ""
+ echo "<<<"
+ echo "<<< End of Regression Iterations"
+ echo "<<<"
+ echo "<<<"
+ echo "<<< FAILED $iter_failed out of $all_iters iterations!"
+ echo "<<<"
+ echo "<<< FAILED $test_failed out of $all_tests testcases!"
+ echo "<<<"
+ echo "<<< -------------------------------------------------"
+ echo "<<<"
+ echo "<<< See following files for detailed test results:"
+ echo "<<< ../log/*pci_tb.log "
+ echo "<<< ../log/*pci_mon.log "
+ echo "<<< ../log/*pciu_mon.log "
+ echo "<<< ../log/*wbu_mon.log "
+ echo "<<< ../log/*ncsim.log "
+ echo "<<<"
+endif
+exit
+
+help:
+ echo ""
+ echo "Script arguments:"
+ echo ""
+ echo "regression : run all implemented regression iterations on PCI Bridge Design"
+ echo ""
+ echo "xilinx : if you want to run simulation with xilinx RAM primitives. You have to provide RAM16X1D.v, RAMB4_S16_S16.v and glbl.v simulation files."
+ echo " : you have to edit ../bin/xilinx_file_list.lst file with the correct paths to these files. Leave other paths as they are!"
+ echo ""
+ echo "artisan : if you want to run simulation with artisan ASIC library vendor RAM primitives. You have to provide simulation models for these, edit ../bin/artisan_file_list.lst,"
+ echo " : and optionaly ../../../rtl/verilog/pci_user_constants.v, ../../../bench/verilog/pci_regression_constants.v, ../../../rtl/verilog/wb_tpram.v and ../../../rtl/verilog/pci_tpram.v"
+ echo ""
+ echo "waves : if you want to dump all the signals in the testbench to the signalscan output file in ../out/ directory"
+ echo ""
+ echo "vs_two_port : if you want to run simulation with virtual silicon ASIC library vendor RAM primitives. You have to provide simulation models for these, edit ../bin/vs_file_list.lst,"
+ echo " : and optionaly ../../../rtl/verilog/pci_user_constants.v, ../../../bench/verilog/pci_regression_constants.v, ../../../rtl/verilog/wb_tpram.v and ../../../rtl/verilog/pci_tpram.v"
+ echo ""
+ echo "disable_completion_expired_tests : if you want to disable completion expiration testing during regression run, because these are time consuming tests"
+ echo ""
+exit
+
run_pci_sim_regr.scr
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncsim.key
===================================================================
--- ncsim.key (nonexistent)
+++ ncsim.key (revision 154)
@@ -0,0 +1 @@
+q
ncsim.key
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncsim.args
===================================================================
--- ncsim.args (nonexistent)
+++ ncsim.args (revision 154)
@@ -0,0 +1,8 @@
+-cdslib ../bin/cds.lib
+-hdlvar ../bin/hdl.var
+-licqueue
+-logfile ../log/ncsim.log
+-messages
+-tcl
+-input ../bin/ncsim.rc
+worklib.bridge32:fun
ncsim.args
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: clean
===================================================================
--- clean (nonexistent)
+++ clean (revision 154)
@@ -0,0 +1,61 @@
+#!/bin/csh -f
+
+if ($#argv < 1) then
+ echo "Missing required argument: all | log | wave | nc_out"
+ exit
+endif
+
+set cur_arg = 1
+set arg_chk = 0
+
+set log = 0
+set wave = 0
+set nc_out = 0
+
+while ($cur_arg <= $#argv)
+ if ($argv[$cur_arg] == "all") then
+ set log = 1
+ set wave = 1
+ set nc_out = 1
+
+ @ arg_chk = $arg_chk + 1
+ endif
+
+ if ($argv[$cur_arg] == "log") then
+ set log = 1
+
+ @ arg_chk = $arg_chk + 1
+ endif
+
+ if ($argv[$cur_arg] == "wave") then
+ set wave = 1
+
+ @ arg_chk = $arg_chk + 1
+ endif
+
+ if ($argv[$cur_arg] == "nc_out") then
+ set nc_out = 1
+
+ @ arg_chk = $arg_chk + 1
+ endif
+
+ if ($arg_chk != $cur_arg) then
+ echo "Invalid argument $argv[$cur_arg]"
+ exit
+ endif
+
+ @ cur_arg = $cur_arg + 1
+end
+
+if ($nc_out) then
+ rm ../bin/INCA_libs/worklib/*
+ rm ../bin/INCA_libs/worklib/.*
+endif
+
+if ($log) then
+ rm ../log/*.log
+endif
+
+if ($wave) then
+ rm -rf ../out/*.shm
+endif
clean
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: top_groups.do
===================================================================
--- top_groups.do (nonexistent)
+++ top_groups.do (revision 154)
@@ -0,0 +1,218 @@
+// Signalscan Version 6.7p1
+
+
+define noactivityindicator
+define analog waveform lines
+define add variable default overlay off
+define waveform window analogheight 1
+define terminal automatic
+define buttons control \
+ 1 opensimmulationfile \
+ 2 executedofile \
+ 3 designbrowser \
+ 4 waveform \
+ 5 source \
+ 6 breakpoints \
+ 7 definesourcessearchpath \
+ 8 exit \
+ 9 createbreakpoint \
+ 10 creategroup \
+ 11 createmarker \
+ 12 closesimmulationfile \
+ 13 renamesimmulationfile \
+ 14 replacesimulationfiledata \
+ 15 listopensimmulationfiles \
+ 16 savedofile
+define buttons waveform \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 zoomin \
+ 7 zoomout \
+ 8 zoomoutfull \
+ 9 expand \
+ 10 createmarker \
+ 11 designbrowser:1 \
+ 12 variableradixbinary \
+ 13 variableradixoctal \
+ 14 variableradixdecimal \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define buttons designbrowser \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 cdupscope \
+ 7 getallvariables \
+ 8 getdeepallvariables \
+ 9 addvariables \
+ 10 addvarsandclosewindow \
+ 11 closewindow \
+ 12 scopefiltermodule \
+ 13 scopefiltertask \
+ 14 scopefilterfunction \
+ 15 scopefilterblock \
+ 16 scopefilterprimitive
+define buttons event \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 move \
+ 7 closewindow \
+ 8 duplicate \
+ 9 defineasrisingedge \
+ 10 defineasfallingedge \
+ 11 defineasanyedge \
+ 12 variableradixbinary \
+ 13 variableradixoctal \
+ 14 variableradixdecimal \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define buttons source \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 createbreakpoint \
+ 7 creategroup \
+ 8 createmarker \
+ 9 createevent \
+ 10 createregisterpage \
+ 11 closewindow \
+ 12 opensimmulationfile \
+ 13 closesimmulationfile \
+ 14 renamesimmulationfile \
+ 15 replacesimulationfiledata \
+ 16 listopensimmulationfiles
+define buttons register \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 createregisterpage \
+ 7 closewindow \
+ 8 continuefor \
+ 9 continueuntil \
+ 10 continueforever \
+ 11 stop \
+ 12 previous \
+ 13 next \
+ 14 variableradixbinary \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define show related transactions
+define exit prompt
+define event search direction forward
+define variable nofullhierarchy
+define variable nofilenames
+define variable nofullpathfilenames
+include bookmark with filenames
+include scope history without filenames
+define waveform window listpane 5.78
+define waveform window namepane 13.93
+define multivalueindication
+define pattern curpos dot
+define pattern cursor1 dot
+define pattern cursor2 dot
+define pattern marker dot
+define print designer "Miha Dolenc"
+define print border
+define print color blackonwhite
+define print command "/usr/ucb/lpr -P%P"
+define print printer lp
+define print range visible
+define print variable visible
+define rise fall time low threshold percentage 10
+define rise fall time high threshold percentage 90
+define rise fall time low value 0
+define rise fall time high value 3.3
+define sendmail command "/usr/lib/sendmail"
+define sequence time width 30.00
+define snap
+
+define source noprompt
+define time units default
+define userdefinedbussymbol
+define user guide directory "/usr/local/designacc/signalscan-6.7p1/doc/html"
+define waveform window grid off
+define waveform window waveheight 14
+define waveform window wavespace 6
+define web browser command netscape
+define zoom outfull on initial add off
+add group \
+ A \
+
+add group \
+ "PCI signals" \
+ SYSTEM.pci_clock \
+ SYSTEM.MAS0_REQ \
+ SYSTEM.MAS0_GNT \
+ SYSTEM.MAS1_REQ \
+ SYSTEM.MAS1_GNT \
+ SYSTEM.MAS2_REQ \
+ SYSTEM.MAS2_GNT \
+ SYSTEM.FRAME \
+ SYSTEM.IRDY \
+ SYSTEM.DEVSEL \
+ SYSTEM.TRDY \
+ SYSTEM.STOP \
+ SYSTEM.AD[31:0]'h \
+ SYSTEM.CBE[3:0]'h \
+ SYSTEM.PAR \
+ SYSTEM.INTA \
+ SYSTEM.PERR \
+ SYSTEM.SERR \
+
+add group \
+ "WISHBONE slave signals" \
+ SYSTEM.wb_clock \
+ SYSTEM.CYC_I \
+ SYSTEM.STB_I \
+ SYSTEM.CAB_I \
+ SYSTEM.WE_I \
+ SYSTEM.ACK_O \
+ SYSTEM.RTY_O \
+ SYSTEM.ERR_O \
+ SYSTEM.ADR_I[31:0]'h \
+ SYSTEM.SDAT_I[31:0]'h \
+ SYSTEM.SDAT_O[31:0]'h \
+ SYSTEM.SEL_I[3:0]'h \
+ SYSTEM.INT_O \
+
+add group \
+ "WISHBONE master signals" \
+ SYSTEM.wb_clock \
+ SYSTEM.CYC_O \
+ SYSTEM.STB_O \
+ SYSTEM.CAB_O \
+ SYSTEM.WE_O \
+ SYSTEM.ACK_I \
+ SYSTEM.RTY_I \
+ SYSTEM.ERR_I \
+ SYSTEM.ADR_O[31:0]'h \
+ SYSTEM.MDAT_I[31:0]'h \
+ SYSTEM.MDAT_O[31:0]'h \
+ SYSTEM.SEL_O[3:0]'h \
+ SYSTEM.INT_I \
+
+add group \
+ "Clocks, resets" \
+ SYSTEM.wb_clock \
+ SYSTEM.pci_clock \
+ SYSTEM.RST \
+ SYSTEM.RST_O \
+ SYSTEM.RTY_I \
+ SYSTEM.test_name[799:0]'a \
+
+
+deselect all
+open window waveform 1 geometry 10 59 1368 926
+zoom at 815149.757(0)ns 0.00214844 0.00000000
top_groups.do
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncelab.args
===================================================================
--- ncelab.args (nonexistent)
+++ ncelab.args (revision 154)
@@ -0,0 +1,42 @@
+//
+// ncelab.args: Arguments passed to the NC-Verilog elaborator.
+// Created by ncprep on Tue Jan 29 18:18:34 2002
+
+// Turn on informative messages.
+-MESSAGES
+// -NOCOPYRIGHT
+
+// Uncomment the following line to generate a named log file
+// -LOGFILE ncelab.log
+
+// Top level module(s)
+CBE_EN_CRIT
+PCI_TPRAM
+CONF_CYC_ADDR_DEC
+FRAME_CRIT
+PCI_TARGET32_CLK_EN
+FRAME_EN_CRIT
+PAR_CRIT
+FRAME_LOAD_CRIT
+PCI_TARGET32_DEVS_CRIT
+PERR_CRIT
+PCI_DECODER
+PERR_EN_CRIT
+DECODER
+SERR_CRIT
+IRDY_OUT_CRIT
+PCI_IO_MUX
+PCI_IO_MUX_AD_EN_CRIT
+PCI_IO_MUX_AD_LOAD_CRIT
+SERR_EN_CRIT
+MAS_AD_EN_CRIT
+MAS_AD_LOAD_CRIT
+PCI_TARGET32_STOP_CRIT
+synchronizer_flop
+MAS_CH_STATE_CRIT
+PCI_TARGET32_TRDY_CRIT
+TOP
+PCI_RST_INT
+SYNC_MODULE
+WB_TPRAM
+
ncelab.args
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: regression_example
===================================================================
--- regression_example (nonexistent)
+++ regression_example (revision 154)
@@ -0,0 +1,173 @@
+#!/bin/csh -f
+
+set iter = 1;
+set failed = 0;
+set all_tests = 0;
+# List all test cases
+set simpletests=(buserr-nocache immu-nocache dmmu-nocache basic-nocache mul-nocache-O2 syscall-nocache cbasic-nocache-O2 ints1-nocache ints2-nocache \
+ buserr-icdc immu-icdc dmmu-icdc basic-icdc mul-icdc-O2 syscall-icdc cbasic-icdc-O2 ints1-icdc ints2-icdc)
+set complextests=(buserr-ic immu-ic dmmu-ic basic-ic mul-ic-O2 syscall-ic cbasic-ic-O2 ints1-ic ints2-ic \
+ buserr-dc immu-dc dmmu-dc basic-dc mul-dc-O2 syscall-dc cbasic-dc-O2 ints1-dc ints2-dc \
+ mul-nocache-O0 cbasic-nocache-O0 \
+ mul-icdc-O0 cbasic-icdc-O0 \
+ mul-ic-O0 cbasic-ic-O0 \
+ mul-dc-O0 cbasic-dc-O0)
+set simpletimes=(10 10 10 40 40 40 40 40 60 \
+ 10 10 10 40 40 40 40 40 40)
+set complextimes=(10 10 10 40 40 40 40 40 40 \
+ 10 10 10 40 40 40 40 40 100 \
+ 40 40 \
+ 40 40 \
+ 40 40 \
+ 40 40)
+set iterations=( \
+ "OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC" \
+ "OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+OR1200_REGISTERED_INPUTS" \
+ "OR1200_REGISTERED_OUTPUTS+OR1200_REGISTERED_INPUTS" \
+ "OR1200_REGISTERED_OUTPUTS+OR1200_REGISTERED_INPUTS+OR1200_CLMODE_1TO2" \
+ "OR1200_REGISTERED_OUTPUTS+OR1200_CLMODE_1TO2" \
+ "OR1200_REGISTERED_OUTPUTS+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+OR1200_CLMODE_1TO2" \
+ "OR1200_REGISTERED_OUTPUTS" \
+ "" \
+ "OR1200_REGISTERED_OUTPUTS+OR1200_REGISTERED_INPUTS+FLASH_GENERIC_REGISTERED" \
+ "")
+
+# Process arguments
+if ($1 == "simple") then
+ set tests=(${simpletests})
+ set maxtimes=(${simpletimes})
+else
+ set tests=(${simpletests} ${complextests})
+ set maxtimes=(${simpletimes} ${complextimes})
+endif
+if ($1 == "single") then
+ set tests=(${simpletests} ${complextests})
+ set maxtimes=(${simpletimes} ${complextimes})
+ set tests=${tests[$2]}
+ set maxtimes=${maxtimes[$2]}
+endif
+if ($1 == "clean") then
+ rm -rf ../log/*
+ rm -rf ../out/wave/*
+ exit 0;
+else if ($1 == "sim") then
+ goto sim;
+endif
+
+# List all selected tests
+set i = 0;
+foreach test ($tests)
+ @ i += 1;
+ echo -n " Test ${i}: ${test}, $maxtimes[$i] ms\t"
+ if ((${i} % 2) == 0) then
+ echo ""
+ endif
+end
+
+echo ""
+
+set i = 1;
+while ($iterations[$i] != "")
+ echo " Iteration ${i}: ${iterations[$i]}\t"
+ @ i += 1;
+end
+
+# Prepare all .args files
+iteration:
+echo ""
+echo "<<<"
+echo "<<< Iteration ${iter}: ${iterations[$iter]}"
+echo "<<<"
+if (${iterations[$iter]} != "") then
+ ncprep +define+${iterations[$iter]} -f ../bin/nc.scr > ncprep.out
+else
+ ncprep -f ../bin/nc.scr > ncprep.out
+endif
+if (`tail -1 ncprep.out | grep Failed` != "") then
+ echo ""
+ cat ncprep.out
+ exit
+endif
+
+# Run NC-Verilog compiler
+echo ""
+echo "\t@@@"
+echo "\t@@@ Compiling sources"
+echo "\t@@@"
+ncvlog -NOCOPYRIGHT -f ncvlog.args > ncvlog.out
+if ($status != 0) then
+ echo "\t@@@ FAILED"
+ echo ""
+ cat ncvlog.out
+ exit
+else
+ echo "\t@@@ Passed"
+endif
+
+# Run the NC-Verilog elaborator (build the design hierarchy)
+echo ""
+echo "\t@@@"
+echo "\t@@@ Building design hierarchy (elaboration)"
+echo "\t@@@"
+ncelab -NOTIMINGCHECKS -NOCOPYRIGHT -f ncelab.args > ncelab.out
+if ($status != 0) then
+ echo "\t@@@ FAILED"
+ echo ""
+ cat ncelab.out
+ exit
+else
+ echo "\t@@@ Passed"
+endif
+
+# Run the NC-Verilog simulator (simulate the design)
+sim:
+set i = 0;
+foreach test ($tests)
+ @ i += 1;
+ echo ""
+ echo "\t###"
+ echo "\t### Running test ${i}: ${test}, $maxtimes[$i] ms"
+ echo "\t###"
+
+ echo "database -open waves -into ../out/wave/i${iter}-${test} -default" > sim.tcl
+ echo "probe -create -shm xess_top -all -variables -depth all" >> sim.tcl
+ echo "stop -create -time $maxtimes[$i]ms -relative" >> sim.tcl
+ echo "run" >> sim.tcl
+ echo "quit" >> sim.tcl
+
+ cp ../src/${test}.mem ../src/flash.in
+ ncsim -NOCOPYRIGHT -f ncsim.args > ncsim.out
+ if ($status != 0) then
+ cat ncsim.out
+ exit
+ else
+ set magic=`tail -1 nop.log | cut -d'(' -f2 | cut -d')' -f1`
+ set magictime=`tail -1 nop.log | cut -d'n' -f1`
+ if ($magic == "deaddead") then
+ echo "\t### Passed (@time $magictime)"
+ @ all_tests += 1;
+ else
+ echo "\t### FAILED (@time $magictime, magic# 0x$magic)"
+ @ failed += 1;
+ @ all_tests += 1;
+ endif
+ mv flash.log ../log/i${iter}-${test}-flash.log
+ mv executed.log ../log/i${iter}-${test}-executed.log
+ mv sram.log ../log/i${iter}-${test}-sram.log
+ mv sprs.log ../log/i${iter}-${test}-sprs.log
+ mv nop.log ../log/i${iter}-${test}-nop.log
+ endif
+end
+
+@ iter += 1;
+if ($iterations[$iter] != "") then
+ goto iteration
+else
+ echo ""
+ echo "<<<"
+ echo "<<< End of Regression Iterations"
+ echo "<<<"
+ echo "<<< Failed $failed out of $all_tests"
+ echo "<<<"
+endif
+
regression_example
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property