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/verilog/pci_user_constants.v
0,0 → 1,211
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "pci_user_constants.v" ////
//// ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc (mihad@opencores.org) ////
//// - Tadej Markovic (tadej@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/02/22 20:14:13 tadej
// User defined constants used for Test Application
//
//
 
// Fifo implementation defines:
// If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.
// 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),
// then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used
// If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations )
// If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with
// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
// WB_FIFO_RAM_ADDR_LENGTH.
 
`define WBW_ADDR_LENGTH 3
`define WBR_ADDR_LENGTH 6
`define PCIW_ADDR_LENGTH 4
`define PCIR_ADDR_LENGTH 4
 
`define FPGA
`define XILINX
 
//`define WB_RAM_DONT_SHARE
`define PCI_RAM_DONT_SHARE
 
`ifdef FPGA
`ifdef XILINX
`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
//`define PCI_XILINX_RAMB4
`define WB_XILINX_RAMB4
`define PCI_XILINX_DIST_RAM
//`define WB_XILINX_DIST_RAM
`endif
`else
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
`define WB_ARTISAN_SDP
`define PCI_ARTISAN_SDP
`endif
 
// these two defines allow user to select active high or low output enables on PCI bus signals, depending on
// output buffers instantiated. Xilinx FPGAs use active low output enables.
`define ACTIVE_LOW_OE
//`define ACTIVE_HIGH_OE
 
// HOST/GUEST implementation selection - see design document and specification for description of each implementation
// only one can be defined at same time
`define GUEST
//`define HOST
 
// if NO_CNF_IMAGE is commented out, then READ-ONLY access to configuration space is ENABLED:
// - ENABLED Read-Only access from WISHBONE for GUEST bridges
// - ENABLED Read-Only access from PCI for HOST bridges
// with defining NO_CNF_IMAGE, one decoder and one multiplexer are saved
`define NO_CNF_IMAGE
 
// number defined here specifies how many MS bits in PCI address are compared with base address, to decode
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
// smaller the number here, faster the decoder operation
`define PCI_NUM_OF_DEC_ADDR_LINES 8
 
// no. of PCI Target IMAGES
// - PCI provides 6 base address registers for image implementation.
// PCI_IMAGE1 definition is not required and has no effect, since PCI image 1 is always implemented
// If GUEST is defined, PCI Image 0 is also always implemented and is used for configuration space
// access.
// If HOST is defined and NO_CNF_IMAGE is not, then PCI Image 0 is used for Read Only access to configuration
// space. If HOST is defined and NO_CNF_IMAGE is defined, then user can define PCI_IMAGE0 as normal image, and there
// is no access to Configuration space possible from PCI bus.
// Implementation of all other PCI images is selected by defining PCI_IMAGE2 through PCI_IMAGE5 regardles of HOST
// or GUEST implementation.
`ifdef HOST
`ifdef NO_CNF_IMAGE
//`define PCI_IMAGE0
`endif
`endif
 
//`define PCI_IMAGE2
//`define PCI_IMAGE3
//`define PCI_IMAGE4
//`define PCI_IMAGE5
 
// initial value for PCI image address masks. Address masks can be defined in enabled state,
// to allow device independent software to detect size of image and map base addresses to
// memory space. If initial mask for an image is defined as 0, then device independent software
// won't detect base address implemented and device dependent software will have to configure
// address masks as well as base addresses!
`define PCI_AM0 20'hffff_f
`define PCI_AM1 20'hffff_f
`define PCI_AM2 20'hffff_f
`define PCI_AM3 20'hffff_f
`define PCI_AM4 20'hffff_f
`define PCI_AM5 20'hffff_f
 
// initial value for PCI image maping to MEMORY or IO spaces. If initial define is set to 0,
// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D
// Device independent software sets the base addresses acording to MEMORY or IO maping!
`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
`define PCI_BA1_MEM_IO 1'b0
`define PCI_BA2_MEM_IO 1'b0
`define PCI_BA3_MEM_IO 1'b0
`define PCI_BA4_MEM_IO 1'b0
`define PCI_BA5_MEM_IO 1'b0
 
// number defined here specifies how many MS bits in WB address are compared with base address, to decode
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
// smaller the number here, faster the decoder operation
`define WB_NUM_OF_DEC_ADDR_LINES 1
 
// no. of WISHBONE Slave IMAGES
// WB image 0 is always used for access to configuration space. In case configuration space access is not implemented,
// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
// WB Image 1 is always implemented and user doesnt need to specify its definition
// WB images' 2 through 5 implementation by defining each one.
//`define WB_IMAGE2
//`define WB_IMAGE3
//`define WB_IMAGE4
//`define WB_IMAGE5
 
// If this define is commented out, then address translation will not be implemented.
// addresses will pass through bridge unchanged, regardles of address translation enable bits.
// Address translation also slows down the decoding
//`define ADDR_TRAN_IMPL
 
// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
// slower decode speed can be used, to provide enough time for address to be decoded.
`define WB_DECODE_FAST
//`define WB_DECODE_MEDIUM
//`define WB_DECODE_SLOW
 
// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
`define WB_CONFIGURATION_BASE 20'h0000_0
 
// Turn registered WISHBONE slave outputs on or off
// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
// outputs to internals of the core.
//`define REGISTER_WBS_OUTPUTS
 
/*-----------------------------------------------------------------------------------------------------------
Core speed definition - used for simulation and 66MHz Capable bit value in status register indicating 66MHz
capable device
-----------------------------------------------------------------------------------------------------------*/
`define PCI33
//`define PCI66
 
/*-----------------------------------------------------------------------------------------------------------
[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
together by application.
-----------------------------------------------------------------------------------------------------------*/
`define HEADER_VENDOR_ID 16'h1895
`define HEADER_DEVICE_ID 16'h0001
`define HEADER_REVISION_ID 8'h01
 
// Turn registered WISHBONE master outputs on or off
// all outputs from WB Master state machine are registered, if this is defined - WB bus outputs as well as
// outputs to internals of the core.
//`define REGISTER_WBM_OUTPUTS
 
// MAX Retry counter value for WISHBONE Master state-machine
// This value is 8-bit because of 8-bit retry counter !!!
`define WB_RTY_CNT_MAX 8'hff
verilog/pci_user_constants.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: verilog/top.v =================================================================== --- verilog/top.v (nonexistent) +++ verilog/top.v (revision 154) @@ -0,0 +1,568 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// File name "top.v" //// +//// //// +//// This file is part of the PCI bridge sample aplication //// +//// project (CRT controller). //// +//// http://www.opencores.org/cores/pci/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// All additional information is avaliable in the README //// +//// file. //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.3 2002/09/30 16:03:06 mihad +// Added meta flop module for easier meta stable FF identification during synthesis +// +// Revision 1.2 2002/02/01 15:24:46 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.1.1.1 2001/10/02 15:33:33 mihad +// New project directory structure +// +// + +// This top module is used for simulation and synthesys of CRT controller +// sample aplication. + +module TOP +( + CLK, + RST, + INTA, + REQ, + GNT, + FRAME, + IRDY, + IDSEL, + DEVSEL, + TRDY, + STOP, + PAR, + PERR, + SERR, + AD0, + AD1, + AD2, + AD3, + AD4, + AD5, + AD6, + AD7, + AD8, + AD9, + AD10, + AD11, + AD12, + AD13, + AD14, + AD15, + AD16, + AD17, + AD18, + AD19, + AD20, + AD21, + AD22, + AD23, + AD24, + AD25, + AD26, + AD27, + AD28, + AD29, + AD30, + AD31, + CBE0, + CBE1, + CBE2, + CBE3, + +/* CLK_I, + RST_I, + RST_O, + INT_I, + INT_O, + + // WISHBONE slave interface + ADR_I, + SDAT_I, + SDAT_O, + SEL_I, + CYC_I, + STB_I, + WE_I, + CAB_I, + ACK_O, + RTY_O, + ERR_O, + + // WISHBONE master interface + ADR_O, + MDAT_I, + MDAT_O, + SEL_O, + CYC_O, + STB_O, + WE_O, + CAB_O, + ACK_I, + RTY_I, + ERR_I */ + + CRT_CLK, + HSYNC, + VSYNC, + + RGB4, + RGB5, + RGB6, + RGB7, + RGB8, + RGB9, + RGB10, + RGB11, + RGB12, + RGB13, + RGB14, + RGB15, + + LED +); + +input CLK ; +inout AD0, + AD1, + AD2, + AD3, + AD4, + AD5, + AD6, + AD7, + AD8, + AD9, + AD10, + AD11, + AD12, + AD13, + AD14, + AD15, + AD16, + AD17, + AD18, + AD19, + AD20, + AD21, + AD22, + AD23, + AD24, + AD25, + AD26, + AD27, + AD28, + AD29, + AD30, + AD31 ; + +inout CBE0, + CBE1, + CBE2, + CBE3 ; + +inout RST ; +inout INTA ; +output REQ ; +input GNT ; +inout FRAME ; +inout IRDY ; +input IDSEL ; +inout DEVSEL ; +inout TRDY ; +inout STOP ; +inout PAR ; +inout PERR ; +output SERR ; + +input CRT_CLK ; +// CRT outputs +output HSYNC ; +output VSYNC ; +output RGB4, + RGB5, + RGB6, + RGB7, + RGB8, + RGB9, + RGB10, + RGB11, + RGB12, + RGB13, + RGB14, + RGB15 ; +output LED ; + +// WISHBONE system signals +wire RST_I = 1'b0 ; +wire RST_O ; +wire INT_I = 1'b0 ; +wire INT_O ; + +wire [15:0] rgb_int ; +// WISHBONE slave interface +wire [31:0] ADR_I ; +wire [31:0] SDAT_I ; +wire [31:0] SDAT_O ; +wire [3:0] SEL_I ; +wire CYC_I ; +wire STB_I ; +wire WE_I ; +wire CAB_I ; +wire ACK_O ; +wire RTY_O ; +wire ERR_O ; + +// WISHBONE master interface +wire [31:0] ADR_O ; +wire [31:0] MDAT_I ; +wire [31:0] MDAT_O ; +wire [3:0] SEL_O ; +wire CYC_O ; +wire STB_O ; +wire WE_O ; +wire CAB_O ; +wire ACK_I ; +wire RTY_I ; +wire ERR_I ; + +wire [31:0] AD_out ; +wire [31:0] AD_en ; + + +wire [31:0] AD_in = +{ + AD31, + AD30, + AD29, + AD28, + AD27, + AD26, + AD25, + AD24, + AD23, + AD22, + AD21, + AD20, + AD19, + AD18, + AD17, + AD16, + AD15, + AD14, + AD13, + AD12, + AD11, + AD10, + AD9, + AD8, + AD7, + AD6, + AD5, + AD4, + AD3, + AD2, + AD1, + AD0 +} ; + +wire [3:0] CBE_in = +{ + CBE3, + CBE2, + CBE1, + CBE0 +} ; + +wire [3:0] CBE_out ; +wire [3:0] CBE_en ; + + + +wire RST_in = RST ; +wire RST_out ; +wire RST_en ; + +wire INTA_in = INTA ; +wire INTA_en ; +wire INTA_out ; + +wire REQ_en ; +wire REQ_out ; + +wire FRAME_in = FRAME ; +wire FRAME_out ; +wire FRAME_en ; + +wire IRDY_in = IRDY ; +wire IRDY_out ; +wire IRDY_en ; + +wire DEVSEL_in = DEVSEL ; +wire DEVSEL_out ; +wire DEVSEL_en ; + +wire TRDY_in = TRDY ; +wire TRDY_out ; +wire TRDY_en ; + +wire STOP_in = STOP ; +wire STOP_out ; +wire STOP_en ; + +wire PAR_in = PAR ; +wire PAR_out ; +wire PAR_en ; + +wire PERR_in = PERR ; +wire PERR_out ; +wire PERR_en ; + +wire SERR_out ; +wire SERR_en ; + +pci_bridge32 bridge +( + // WISHBONE system signals + .wb_clk_i(CRT_CLK), + .wb_rst_i(RST_I), + .wb_rst_o(RST_O), + .wb_int_i(INT_I), + .wb_int_o(INT_O), + + // WISHBONE slave interface + .wbs_adr_i(ADR_I), + .wbs_dat_i(SDAT_I), + .wbs_dat_o(SDAT_O), + .wbs_sel_i(SEL_I), + .wbs_cyc_i(CYC_I), + .wbs_stb_i(STB_I), + .wbs_we_i (WE_I), + .wbs_cab_i(CAB_I), + .wbs_ack_o(ACK_O), + .wbs_rty_o(RTY_O), + .wbs_err_o(ERR_O), + + // WISHBONE master interface + .wbm_adr_o(ADR_O), + .wbm_dat_i(MDAT_I), + .wbm_dat_o(MDAT_O), + .wbm_sel_o(SEL_O), + .wbm_cyc_o(CYC_O), + .wbm_stb_o(STB_O), + .wbm_we_o (WE_O), + .wbm_cab_o(CAB_O), + .wbm_ack_i(ACK_I), + .wbm_rty_i(RTY_I), + .wbm_err_i(ERR_I), + + // pci interface - system pins + .pci_clk_i ( CLK ), + .pci_rst_i ( RST_in ), + .pci_rst_o ( RST_out ), + .pci_inta_i ( INTA_in ), + .pci_inta_o ( INTA_out), + .pci_rst_oe_o ( RST_en), + .pci_inta_oe_o( INTA_en ), + + // arbitration pins + .pci_req_o ( REQ_out ), + .pci_req_oe_o( REQ_en ), + + .pci_gnt_i ( GNT ), + + // protocol pins + .pci_frame_i ( FRAME_in), + .pci_frame_o ( FRAME_out ), + + .pci_frame_oe_o ( FRAME_en ), + .pci_irdy_oe_o ( IRDY_en ), + .pci_devsel_oe_o ( DEVSEL_en ), + .pci_trdy_oe_o ( TRDY_en ), + .pci_stop_oe_o ( STOP_en ), + .pci_ad_oe_o ( AD_en ), + .pci_cbe_oe_o ( CBE_en) , + + .pci_irdy_i ( IRDY_in ), + .pci_irdy_o ( IRDY_out ), + + .pci_idsel_i ( IDSEL ), + + .pci_devsel_i ( DEVSEL_in ), + .pci_devsel_o ( DEVSEL_out ), + + .pci_trdy_i ( TRDY_in ), + .pci_trdy_o ( TRDY_out ), + + .pci_stop_i ( STOP_in ), + .pci_stop_o ( STOP_out ), + + // data transfer pins + .pci_ad_i (AD_in), + .pci_ad_o (AD_out), + + .pci_cbe_i( CBE_in ), + .pci_cbe_o( CBE_out ), + + // parity generation and checking pins + .pci_par_i ( PAR_in ), + .pci_par_o ( PAR_out ), + .pci_par_oe_o ( PAR_en ), + + .pci_perr_i ( PERR_in ), + .pci_perr_o ( PERR_out ), + .pci_perr_oe_o( PERR_en ), + + // system error pin + .pci_serr_o ( SERR_out ), + .pci_serr_oe_o( SERR_en ) +); + +// PCI IO buffers instantiation +bufif0 AD_buf0 ( AD0, AD_out[0], AD_en[0]) ; +bufif0 AD_buf1 ( AD1, AD_out[1], AD_en[1]) ; +bufif0 AD_buf2 ( AD2, AD_out[2], AD_en[2]) ; +bufif0 AD_buf3 ( AD3, AD_out[3], AD_en[3]) ; +bufif0 AD_buf4 ( AD4, AD_out[4], AD_en[4]) ; +bufif0 AD_buf5 ( AD5, AD_out[5], AD_en[5]) ; +bufif0 AD_buf6 ( AD6, AD_out[6], AD_en[6]) ; +bufif0 AD_buf7 ( AD7, AD_out[7], AD_en[7]) ; +bufif0 AD_buf8 ( AD8, AD_out[8], AD_en[8]) ; +bufif0 AD_buf9 ( AD9, AD_out[9], AD_en[9]) ; +bufif0 AD_buf10 ( AD10, AD_out[10],AD_en[10] ) ; +bufif0 AD_buf11 ( AD11, AD_out[11],AD_en[11] ) ; +bufif0 AD_buf12 ( AD12, AD_out[12],AD_en[12] ) ; +bufif0 AD_buf13 ( AD13, AD_out[13],AD_en[13] ) ; +bufif0 AD_buf14 ( AD14, AD_out[14],AD_en[14] ) ; +bufif0 AD_buf15 ( AD15, AD_out[15],AD_en[15] ) ; +bufif0 AD_buf16 ( AD16, AD_out[16],AD_en[16] ) ; +bufif0 AD_buf17 ( AD17, AD_out[17],AD_en[17] ) ; +bufif0 AD_buf18 ( AD18, AD_out[18],AD_en[18] ) ; +bufif0 AD_buf19 ( AD19, AD_out[19],AD_en[19] ) ; +bufif0 AD_buf20 ( AD20, AD_out[20],AD_en[20] ) ; +bufif0 AD_buf21 ( AD21, AD_out[21],AD_en[21] ) ; +bufif0 AD_buf22 ( AD22, AD_out[22],AD_en[22] ) ; +bufif0 AD_buf23 ( AD23, AD_out[23],AD_en[23] ) ; +bufif0 AD_buf24 ( AD24, AD_out[24],AD_en[24] ) ; +bufif0 AD_buf25 ( AD25, AD_out[25],AD_en[25] ) ; +bufif0 AD_buf26 ( AD26, AD_out[26],AD_en[26] ) ; +bufif0 AD_buf27 ( AD27, AD_out[27],AD_en[27] ) ; +bufif0 AD_buf28 ( AD28, AD_out[28],AD_en[28] ) ; +bufif0 AD_buf29 ( AD29, AD_out[29],AD_en[29] ) ; +bufif0 AD_buf30 ( AD30, AD_out[30],AD_en[30] ) ; +bufif0 AD_buf31 ( AD31, AD_out[31],AD_en[31] ) ; + +bufif0 CBE_buf0 ( CBE0, CBE_out[0], CBE_en[0] ) ; +bufif0 CBE_buf1 ( CBE1, CBE_out[1], CBE_en[1] ) ; +bufif0 CBE_buf2 ( CBE2, CBE_out[2], CBE_en[2] ) ; +bufif0 CBE_buf3 ( CBE3, CBE_out[3], CBE_en[3] ) ; + +bufif0 FRAME_buf ( FRAME, FRAME_out, FRAME_en ) ; +bufif0 IRDY_buf ( IRDY, IRDY_out, IRDY_en ) ; +bufif0 DEVSEL_buf ( DEVSEL, DEVSEL_out, DEVSEL_en ) ; +bufif0 TRDY_buf ( TRDY, TRDY_out, TRDY_en ) ; +bufif0 STOP_buf ( STOP, STOP_out, STOP_en ) ; + +bufif0 RST_buf ( RST, RST_out, RST_en ) ; +bufif0 INTA_buf ( INTA, INTA_out, INTA_en) ; +bufif0 REQ_buf ( REQ, REQ_out, REQ_en ) ; +bufif0 PAR_buf ( PAR, PAR_out, PAR_en ) ; +bufif0 PERR_buf ( PERR, PERR_out, PERR_en ) ; +bufif0 SERR_buf ( SERR, SERR_out, SERR_en ) ; + +wire crt_hsync ; +wire crt_vsync ; + +// CRT controler instance +ssvga_top CRT +( + // Clock and reset + .wb_clk_i(CRT_CLK), + .wb_rst_i(RST_O), + + // WISHBONE Master I/F + .wbm_cyc_o (CYC_I), + .wbm_stb_o (STB_I), + .wbm_sel_o (SEL_I), + .wbm_we_o (WE_I), + .wbm_adr_o (ADR_I), + .wbm_dat_o (SDAT_I), + .wbm_cab_o (CAB_I), + .wbm_dat_i (SDAT_O), + .wbm_ack_i (ACK_O), + .wbm_err_i (ERR_O), + .wbm_rty_i (RTY_O), + + // WISHBONE Slave I/F + .wbs_cyc_i (CYC_O), + .wbs_stb_i (STB_O), + .wbs_sel_i (SEL_O), + .wbs_we_i (WE_O), + .wbs_adr_i (ADR_O), + .wbs_dat_i (MDAT_O), + .wbs_cab_i (CAB_O), + .wbs_dat_o (MDAT_I), + .wbs_ack_o (ACK_I), + .wbs_err_o (ERR_I), + .wbs_rty_o (RTY_I), + + // Signals to VGA display + .pad_hsync_o (crt_hsync), + .pad_vsync_o (crt_vsync), + .pad_rgb_o (rgb_int), + .led_o (LED) +); + +CRTC_IOB crt_out_reg +( + .reset_in(RST_O), + .clk_in(CRT_CLK), + .hsync_in(crt_hsync), + .vsync_in(crt_vsync), + .rgb_in(rgb_int[15:4]), + .hsync_out(HSYNC), + .vsync_out(VSYNC), + .rgb_out({RGB15, RGB14, RGB13, RGB12, RGB11, RGB10, RGB9, RGB8, RGB7, RGB6, RGB5, RGB4}) +) ; + +endmodule Index: verilog/ssvga_wbm_if.v =================================================================== --- verilog/ssvga_wbm_if.v (nonexistent) +++ verilog/ssvga_wbm_if.v (revision 154) @@ -0,0 +1,190 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Simple Small VGA IP Core //// +//// //// +//// This file is part of the Simple Small VGA project //// +//// //// +//// //// +//// Description //// +//// LITTLE-ENDIAN WISHBONE master interface. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2002/02/01 15:24:46 mihad +// Repaired a few bugs, updated specification, added test bench files and design document +// +// Revision 1.1.1.1 2001/10/02 15:33:33 mihad +// New project directory structure +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "ssvga_defines.v" + +module ssvga_wbm_if( + // Clock and reset + wb_clk_i, wb_rst_i, + + // WISHBONE Master I/F + wbm_cyc_o, wbm_stb_o, wbm_sel_o, wbm_we_o, + wbm_adr_o, wbm_dat_o, wbm_cab_o, + wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i, + + // Other signals + ssvga_en, fifo_full, + fifo_wr_en, fifo_dat, + pix_start_addr, resync +); + +// +// I/O ports +// + +// +// Clock and reset +// +input wb_clk_i; // Pixel Clock +input wb_rst_i; // Reset + +// +// WISHBONE Master I/F +// +output wbm_cyc_o; +output wbm_stb_o; +output [3:0] wbm_sel_o; +output wbm_we_o; +output [31:0] wbm_adr_o; +output [31:0] wbm_dat_o; +output wbm_cab_o; +input [31:0] wbm_dat_i; +input wbm_ack_i; +input wbm_err_i; +input wbm_rty_i; + +// +// Other signals +// +input ssvga_en; // Global enable +input fifo_full; // FIFO is full +output fifo_wr_en; // FIFO write enable +output [31:0] fifo_dat; // FIFO data +input [31:2] pix_start_addr ; +input resync ; // when pixel buffer underrun occures, master must resynchronize operation to start of screen + +// +// Internal regs and wires +// +reg [`SSVGA_VMCW-1:0] vmaddr_r; // Video memory address counter +//reg [31:0] shift_r; // Shift register +//reg [1:0] shift_empty_r; // Shift register empty flags + +// frame finished indicator - whenever video memory address shows 640x480 pixels read +reg frame_read ; +wire frame_read_in = ( vmaddr_r == `SSVGA_VMCW'h0_00_00 ) & wbm_ack_i & wbm_stb_o || ~ssvga_en || resync ; + +always@(posedge wb_clk_i or posedge wb_rst_i) +begin + if (wb_rst_i) + frame_read <= #1 1'b0 ; + else + frame_read <= #1 frame_read_in ; +end + +// +// Video memory address generation +// +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + vmaddr_r <= #1 ((`PIXEL_NUM/4)-1) ; + else if (frame_read) + vmaddr_r <= #1 ((`PIXEL_NUM/4)-1); + else if (wbm_ack_i & wbm_stb_o) + vmaddr_r <= #1 vmaddr_r - 1; + +reg [31:2] wbm_adr ; +always@(posedge wb_clk_i or posedge wb_rst_i) +begin + if (wb_rst_i) + wbm_adr <= #1 30'h0000_0000 ; + else if (frame_read) + wbm_adr <= #1 pix_start_addr ; + else if (wbm_ack_i & wbm_stb_o) + wbm_adr <= #1 wbm_adr + 1 ; +end + +// +// Shift register +// +/*always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + shift_r <= #1 32'h0000_0000; + else if (wbm_ack_i & wbm_cyc_o) + shift_r <= #1 wbm_dat_i; + else if (!fifo_full) + shift_r <= #1 {16'h00, shift_r[31:16]}; + +// +// Shift register empty flags +// +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + shift_empty_r <= #1 2'b11 ; + else if (wbm_ack_i & wbm_cyc_o) + shift_empty_r <= #1 2'b00; + else if (!fifo_full) + shift_empty_r <= #1 {1'b1, shift_empty_r[1]}; +*/ +// +// Generate WISHBONE output signals +// +assign wbm_cyc_o = ssvga_en & !frame_read ; +assign wbm_stb_o = wbm_cyc_o & !fifo_full; +assign wbm_sel_o = 4'b1111; +assign wbm_we_o = 1'b0; +assign wbm_adr_o = {wbm_adr, 2'b00}; +assign wbm_dat_o = 32'h0000_0000; +assign wbm_cab_o = 1'b1; + +// +// Generate other signals +// +assign fifo_wr_en = wbm_ack_i & wbm_stb_o ; +assign fifo_dat = wbm_dat_i ; + +endmodule Index: verilog/ssvga_wbs_if.v =================================================================== --- verilog/ssvga_wbs_if.v (nonexistent) +++ verilog/ssvga_wbs_if.v (revision 154) @@ -0,0 +1,177 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Simple Small VGA IP Core //// +//// //// +//// This file is part of the Simple Small VGA project //// +//// //// +//// //// +//// Description //// +//// LITTLE-ENDIAN WISHBONE slave interface. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2001/10/02 15:33:33 mihad +// New project directory structure +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`define SEL_PAL 10 +`define SEL_ADDRESS 2 + +module ssvga_wbs_if( + // Clock and reset + wb_clk_i, wb_rst_i, + + // WISHBONE Slave I/F + wbs_cyc_i, wbs_stb_i, wbs_sel_i, wbs_we_i, + wbs_adr_i, wbs_dat_i, wbs_cab_i, + wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o, + + // Other signals + ssvga_en, pal_wr_en, pal_rd_en, pal_dat, + pix_start_addr +); + +// +// I/O ports +// + +// +// Clock and reset +// +input wb_clk_i; // Pixel Clock +input wb_rst_i; // Reset + +// +// WISHBONE Slave I/F +// +input wbs_cyc_i; +input wbs_stb_i; +input [3:0] wbs_sel_i; +input wbs_we_i; +input [31:0] wbs_adr_i; +input [31:0] wbs_dat_i; +input wbs_cab_i; +output [31:0] wbs_dat_o; +output wbs_ack_o; +output wbs_err_o; +output wbs_rty_o; + +// +// Other signals +// +output ssvga_en; // Global enable +output pal_wr_en; // Palette write enable +output pal_rd_en; // Palette read enable +input [15:0] pal_dat; // Palette data +output [31:2] pix_start_addr ; + +// +// Internal regs and wires +// +reg wbs_ack_o; // WISHBONE ack +reg wbs_err_o; // WISHBONE err +reg [0:0] ctrl_r; // Control register +wire valid_access; // Access to SSVGA + +// +// Control register +// +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + ctrl_r <= #1 1'b0; + else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & !wbs_adr_i[`SEL_ADDRESS]) + ctrl_r <= #1 wbs_dat_i[0]; + +reg [31:2] pix_start_addr ; +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + pix_start_addr <= #1 30'h0000_0000 ; + else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & wbs_adr_i[`SEL_ADDRESS] ) + pix_start_addr <= #1 wbs_dat_i[31:2] ; + +// +// Generate delayed WISHBONE ack/err +// +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) begin + wbs_ack_o <= #1 1'b0; + wbs_err_o <= #1 1'b0; + end + else if (valid_access) begin + wbs_ack_o <= #1 1'b1; + wbs_err_o <= #1 1'b0; + end + else if (wbs_cyc_i & wbs_stb_i) begin + wbs_ack_o <= #1 1'b0; + wbs_err_o <= #1 1'b1; + end + else begin + wbs_ack_o <= #1 1'b0; + wbs_err_o <= #1 1'b0; + end + +// +// Generate WISHBONE output signals +// +reg [31:0] wbs_dat_o ; +always@(wbs_adr_i or pal_dat or ctrl_r or pix_start_addr) +begin + if ( wbs_adr_i[`SEL_PAL] ) + wbs_dat_o = {16'h0000, pal_dat} ; + else + if ( wbs_adr_i[`SEL_ADDRESS] ) + wbs_dat_o = {pix_start_addr, 2'b00} ; + else + wbs_dat_o = {{31{1'b0}}, ctrl_r}; +end + +assign wbs_rty_o = 1'b0; + +// +// Generate other signals +// +assign valid_access = wbs_cyc_i & wbs_stb_i & (wbs_sel_i == 4'b1111); +assign ssvga_en = ctrl_r[0]; +assign pal_wr_en = valid_access & wbs_we_i & wbs_adr_i[`SEL_PAL]; +assign pal_rd_en = valid_access & ~wbs_we_i & wbs_adr_i[`SEL_PAL]; + +endmodule Index: verilog/ssvga_defines.v =================================================================== --- verilog/ssvga_defines.v (nonexistent) +++ verilog/ssvga_defines.v (revision 154) @@ -0,0 +1,75 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Simple Small VGA IP Core //// +//// //// +//// This file is part of the Simple Small VGA project //// +//// //// +//// //// +//// Description //// +//// Definitions. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2001/10/02 15:33:33 mihad +// New project directory structure +// +// + +//`define XILINX_RAMB4 +`define SSVGA_640x480 + +`ifdef SSVGA_640x480 +`define PIXEL_NUM 'd307200 // 383330 +`define SSVGA_HCW 10 +`define SSVGA_VCW 10 +//`define SSVGA_HTOT `SSVGA_HCW'd3178 +//`define SSVGA_HPULSE `SSVGA_HCW'd381 +`define SSVGA_HTOT `SSVGA_HCW'd750 +`define SSVGA_HPULSE `SSVGA_HCW'd90 +`define SSVGA_HFRONTP `SSVGA_HCW'd10 +`define SSVGA_HBACKP `SSVGA_HCW'd10 + +//`define SSVGA_VTOT `SSVGA_VCW'd525 +//`define SSVGA_VPULSE `SSVGA_VCW'd3 +`define SSVGA_VTOT `SSVGA_VCW'd511 +`define SSVGA_VPULSE `SSVGA_VCW'd4 +`define SSVGA_VFRONTP `SSVGA_HCW'd12 +`define SSVGA_VBACKP `SSVGA_HCW'd15 +`define SSVGA_VMCW 17 +`endif + +`define XILINX_RAMB4 \ No newline at end of file Index: verilog/ssvga_top.v =================================================================== --- verilog/ssvga_top.v (nonexistent) +++ verilog/ssvga_top.v (revision 154) @@ -0,0 +1,303 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Simple Small VGA IP Core //// +//// //// +//// This file is part of the Simple Small VGA project //// +//// //// +//// //// +//// Description //// +//// Top level of SSVGA. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2001/10/02 15:33:33 mihad +// New project directory structure +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module ssvga_top( + // Clock and reset + wb_clk_i, wb_rst_i, + + // WISHBONE Master I/F + wbm_cyc_o, wbm_stb_o, wbm_sel_o, wbm_we_o, + wbm_adr_o, wbm_dat_o, wbm_cab_o, + wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i, + + // WISHBONE Slave I/F + wbs_cyc_i, wbs_stb_i, wbs_sel_i, wbs_we_i, + wbs_adr_i, wbs_dat_i, wbs_cab_i, + wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o, + + // Signals to VGA display + pad_hsync_o, pad_vsync_o, pad_rgb_o, led_o +); + +// +// I/O ports +// + +// +// Clock and reset +// +input wb_clk_i; // Write Clock +input wb_rst_i; // Reset + +// +// WISHBONE Master I/F +// +output wbm_cyc_o; +output wbm_stb_o; +output [3:0] wbm_sel_o; +output wbm_we_o; +output [31:0] wbm_adr_o; +output [31:0] wbm_dat_o; +output wbm_cab_o; +input [31:0] wbm_dat_i; +input wbm_ack_i; +input wbm_err_i; +input wbm_rty_i; + +// +// WISHBONE Slave I/F +// +input wbs_cyc_i; +input wbs_stb_i; +input [3:0] wbs_sel_i; +input wbs_we_i; +input [31:0] wbs_adr_i; +input [31:0] wbs_dat_i; +input wbs_cab_i; +output [31:0] wbs_dat_o; +output wbs_ack_o; +output wbs_err_o; +output wbs_rty_o; + +// +// VGA display +// +output pad_hsync_o; // H sync +output pad_vsync_o; // V sync +output [15:0] pad_rgb_o; // Digital RGB data +output led_o; + +// +// Internal wires and regs +// +wire ssvga_en; // Global enable +wire fifo_full; // FIFO full flag +wire fifo_empty; // FIFO empty flag +wire wbm_restart ; // indicator on when WISHBONE master should restart whole screen because of pixel buffer underrun +wire crtc_hblank; // H blank +wire crtc_vblank; // V blank +wire fifo_wr_en; // FIFO write enable +wire fifo_rd_en; // FIFO read enable +wire [31:0] fifo_in; // FIFO input data +wire [7:0] fifo_out; // FIFO output data +//wire [7:0] pal_indx; // Palette index +wire pal_wr_en; // Palette write enable +wire pal_rd_en; // Palette read enable +wire [15:0] pal_pix_dat ; // pixel output from pallete RAM + +reg go ; + +// rgb output assignment - when blank output transmits black pixels, otherwise it transmits pallete data +reg drive_blank_reg ; +always@(posedge wb_clk_i or posedge wb_rst_i) +begin + if ( wb_rst_i ) + drive_blank_reg <= #1 1'b0 ; + else + drive_blank_reg <= #1 ( crtc_hblank || crtc_vblank || ~go ) ; +end + +assign pad_rgb_o = drive_blank_reg ? 16'h0000 : pal_pix_dat ; + +assign led_o = ssvga_en ; + +// +// Read FIFO when blanks are not asserted and fifo has been filled once +// +always@(posedge wb_clk_i or posedge wb_rst_i) +begin + if ( wb_rst_i ) + go <= #1 1'b0 ; + else + if ( ~ssvga_en ) + go <= #1 1'b0 ; + else + go <= #1 ( fifo_full & crtc_hblank & crtc_vblank ) || ( go && ~fifo_empty ) ; +end + +assign fifo_rd_en = !crtc_hblank & !crtc_vblank & go ; + +assign wbm_restart = go & fifo_empty ; + +// +// Palette index is either color index from FIFO or +// address from WISHBONE slave when writing into palette +// +//assign pal_indx = (pal_wr_en || pal_rd_en) ? wbs_adr_i[9:2] : fifo_out; + +// +// Instantiation of WISHBONE Master block +// +wire [31:2] pix_start_addr ; +ssvga_wbm_if ssvga_wbm_if( + + // Clock and reset + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + + // WISHBONE Master I/F + .wbm_cyc_o(wbm_cyc_o), + .wbm_stb_o(wbm_stb_o), + .wbm_sel_o(wbm_sel_o), + .wbm_we_o(wbm_we_o), + .wbm_adr_o(wbm_adr_o), + .wbm_dat_o(wbm_dat_o), + .wbm_cab_o(wbm_cab_o), + .wbm_dat_i(wbm_dat_i), + .wbm_ack_i(wbm_ack_i), + .wbm_err_i(wbm_err_i), + .wbm_rty_i(wbm_rty_i), + + // FIFO control and other signals + .ssvga_en(ssvga_en), + .fifo_full(fifo_full), + .fifo_wr_en(fifo_wr_en), + .fifo_dat(fifo_in), + .pix_start_addr(pix_start_addr), + .resync(wbm_restart) +); + +// +// Instantiation of WISHBONE Slave block +// +wire [15:0] wbs_pal_data ; +ssvga_wbs_if ssvga_wbs_if( + + // Clock and reset + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + + // WISHBONE Slave I/F + .wbs_cyc_i(wbs_cyc_i), + .wbs_stb_i(wbs_stb_i), + .wbs_sel_i(wbs_sel_i), + .wbs_we_i(wbs_we_i), + .wbs_adr_i(wbs_adr_i), + .wbs_dat_i(wbs_dat_i), + .wbs_cab_i(wbs_cab_i), + .wbs_dat_o(wbs_dat_o), + .wbs_ack_o(wbs_ack_o), + .wbs_err_o(wbs_err_o), + .wbs_rty_o(wbs_rty_o), + + // Control for other SSVGA blocks + .ssvga_en(ssvga_en), + .pal_wr_en(pal_wr_en), + .pal_rd_en(pal_rd_en), + .pal_dat(wbs_pal_data), + .pix_start_addr(pix_start_addr) +); + +// +// Instantiation of line FIFO block +// +ssvga_fifo ssvga_fifo( + .clk(wb_clk_i), + .rst(wb_rst_i), + .wr_en(fifo_wr_en), + .rd_en(fifo_rd_en), + .dat_i(fifo_in), + .dat_o(fifo_out), + .full(fifo_full), + .empty(fifo_empty), + .ssvga_en(ssvga_en) +); + +// +// Instantiation of 256x16 Palette block +// +RAMB4_S16_S16 ssvga_pallete +( + .ADDRA(wbs_adr_i[9:2]), + .DIA(wbs_dat_i[15:0]), + .ENA(1'b1), + .RSTA(wb_rst_i), + .CLKA(wb_clk_i), + .WEA(pal_wr_en), + .DOA(wbs_pal_data), + .ADDRB(fifo_out), + .DIB(16'h0000), + .ENB(1'b1), + .RSTB(wb_rst_i), + .CLKB(wb_clk_i), + .WEB(1'b0), + .DOB(pal_pix_dat) +) ; + +/*generic_spram_256x16 ssvga_palette( + // Generic synchronous single-port RAM interface + .clk(wb_clk_i), + .rst(wb_rst_i), + .ce(1'b1), + .we(pal_wr_en), + .oe(1'b1), + .addr(pal_indx), + .di(wbs_dat_i[15:0]), + .do(pad_rgb_o) +); +*/ +// +// Instantiation of CRT controller block +// +ssvga_crtc ssvga_crtc( + .crt_clk(wb_clk_i), + .rst(wb_rst_i), + .hsync(pad_hsync_o), + .vsync(pad_vsync_o), + .hblank(crtc_hblank), + .vblank(crtc_vblank) +); + +endmodule Index: verilog/ssvga_fifo.v =================================================================== --- verilog/ssvga_fifo.v (nonexistent) +++ verilog/ssvga_fifo.v (revision 154) @@ -0,0 +1,187 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Simple Small VGA IP Core //// +//// //// +//// This file is part of the Simple Small VGA project //// +//// //// +//// //// +//// Description //// +//// 512 entry FIFO for storing line video data. It uses one //// +//// clock for reading and writing. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2001/10/02 15:33:33 mihad +// New project directory structure +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module ssvga_fifo( + clk, rst, dat_i, wr_en, rd_en, + dat_o, full, empty, ssvga_en +); + +// +// I/O ports +// +input clk; // Clock +input rst; // Reset +input [31:0] dat_i; // Input data +input wr_en; // Write enable +input rd_en; // Read enable +output [7:0] dat_o; // Output data +output full; // Full flag +output empty; // Empty flag +input ssvga_en ; // vga enable + +// +// Internal wires and regs +// +reg [7:0] wr_ptr; // Write pointer +reg [7:0] wr_ptr_plus1; // Write pointer +reg [9:0] rd_ptr; // Read pointer +reg [9:0] rd_ptr_plus1; // Read pointer plus1 +wire rd_en_int; // FIFO internal read enable + +// +// Write pointer + 1 +// + +always @(posedge clk or posedge rst) + if (rst) + wr_ptr_plus1 <= #1 8'b0000_0001 ; + else if (~ssvga_en) + wr_ptr_plus1 <= #1 8'b0000_0001 ; + else if (wr_en) + wr_ptr_plus1 <= #1 wr_ptr_plus1 + 1; + +// +// Write pointer +// +always @(posedge clk or posedge rst) + if (rst) + wr_ptr <= #1 8'b0000_0000; + else if (~ssvga_en) + wr_ptr <= #1 8'b0000_0000; + else if (wr_en) + wr_ptr <= #1 wr_ptr_plus1 ; + +// +// Read pointer +// +always @(posedge clk or posedge rst) + if (rst) + rd_ptr <= #1 10'b00_0000_0000; + else if (~ssvga_en) + rd_ptr <= #1 10'b00_0000_0000; + else if (rd_en_int) + rd_ptr <= #1 rd_ptr_plus1 ; + +always @(posedge clk or posedge rst) + if (rst) + rd_ptr_plus1 <= #1 10'b00_0000_0001; + else if (~ssvga_en) + rd_ptr_plus1 <= #1 10'b00_0000_0001; + else if (rd_en_int) + rd_ptr_plus1 <= #1 rd_ptr_plus1 + 1 ; + +// +// Empty is asserted when both pointers match +// +assign empty = ( rd_ptr == {wr_ptr, 2'b00} ) ; + +// +// Full is asserted when both pointers match +// and wr_ptr did increment in previous clock cycle +// +assign full = ( wr_ptr_plus1 == rd_ptr[9:2] ) ; + +wire valid_pix = 1'b1 ; + +// +// Read enable for FIFO +// +assign rd_en_int = rd_en & !empty & valid_pix; + +wire [8:0] ram_pix_address = rd_en_int ? {rd_ptr_plus1[9:2], rd_ptr_plus1[0]} : {rd_ptr[9:2], rd_ptr[0]} ; + +wire [7:0] dat_o_low ; +wire [7:0] dat_o_high ; + +assign dat_o = rd_ptr[1] ? dat_o_high : dat_o_low ; + +RAMB4_S8_S16 ramb4_s8_0( + .CLKA(clk), + .RSTA(rst), + .ADDRA(ram_pix_address), + .DIA(8'h00), + .ENA(1'b1), + .WEA(1'b0), + .DOA(dat_o_low), + + .CLKB(clk), + .RSTB(rst), + .ADDRB(wr_ptr), + .DIB(dat_i[15:0]), + .ENB(1'b1), + .WEB(wr_en), + .DOB() +); + +RAMB4_S8_S16 ramb4_s8_1( + .CLKA(clk), + .RSTA(rst), + .ADDRA(ram_pix_address), + .DIA(8'h00), + .ENA(1'b1), + .WEA(1'b0), + .DOA(dat_o_high), + + .CLKB(clk), + .RSTB(rst), + .ADDRB(wr_ptr), + .DIB(dat_i[31:16]), + .ENB(1'b1), + .WEB(wr_en), + .DOB() +); + +endmodule Index: verilog/crtc_iob.v =================================================================== --- verilog/crtc_iob.v (nonexistent) +++ verilog/crtc_iob.v (revision 154) @@ -0,0 +1,45 @@ +module CRTC_IOB +( + reset_in, + clk_in, + hsync_in, + vsync_in, + rgb_in, + hsync_out, + vsync_out, + rgb_out +) ; + +input reset_in, + clk_in ; + +input hsync_in, + vsync_in ; + +input [15:4] rgb_in ; + +output hsync_out, + vsync_out ; +output [15:4] rgb_out ; + +reg hsync_out, + vsync_out ; + +reg [15:4] rgb_out ; + +always@(posedge clk_in or posedge reset_in) +begin + if ( reset_in ) + begin + hsync_out <= #1 1'b0 ; + vsync_out <= #1 1'b0 ; + rgb_out <= #1 12'h000 ; + end + else + begin + hsync_out <= #1 hsync_in ; + vsync_out <= #1 vsync_in ; + rgb_out <= #1 rgb_in ; + end +end +endmodule \ No newline at end of file Index: verilog/ssvga_crtc.v =================================================================== --- verilog/ssvga_crtc.v (nonexistent) +++ verilog/ssvga_crtc.v (revision 154) @@ -0,0 +1,167 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Simple Small VGA IP Core //// +//// //// +//// This file is part of the Simple Small VGA project //// +//// //// +//// //// +//// Description //// +//// Hsync/Vsync generator. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "ssvga_defines.v" + +module ssvga_crtc( + crt_clk, rst, hsync, vsync, hblank, vblank +); + +// +// I/O ports +// +input crt_clk;// Pixel Clock +input rst; // Reset +output hsync; // H sync +output vsync; // V sync +output hblank; // H blank +output vblank; // V blank + +// +// Internal wires and regs +// +reg [`SSVGA_HCW-1:0] hcntr; // Horizontal counter +reg [`SSVGA_VCW-1:0] vcntr; // Vertical counter +reg hsync; // Horizontal sync +reg vsync; // Vertical sync + +// flip - flops for decoding end of one line +reg line_end1 ; +reg line_end2 ; + +always@(posedge crt_clk or posedge rst) +begin + if (rst) + begin + line_end1 <= #1 1'b0 ; + line_end2 <= #1 1'b0 ; + end + else + begin + line_end1 <= #1 hsync ; + line_end2 <= #1 line_end1 ; + end +end + +wire line_end = ~line_end2 && line_end1 ; + +// +// Assert hblank when hsync is not asserted +// +reg hblank ; +always@(posedge crt_clk or posedge rst) +begin + if (rst) + hblank <= #1 1'b0 ; + else + if ( hcntr == (`SSVGA_HPULSE + `SSVGA_HBACKP) ) + hblank <= #1 1'b0 ; + else + if ( hcntr == (`SSVGA_HTOT - `SSVGA_HFRONTP) ) + hblank <= #1 1'b1 ; +end + +reg vblank ; +always@(posedge crt_clk or posedge rst) +begin + if ( rst ) + vblank <= #1 1'b0 ; + else + if ((vcntr == (`SSVGA_VPULSE + `SSVGA_VBACKP)) && line_end) + vblank <= #1 1'b0 ; + else + if ((vcntr == (`SSVGA_VTOT - `SSVGA_VFRONTP)) && line_end) + vblank <= #1 1'b1 ; +end + +// +// Horizontal counter +// +always @(posedge crt_clk or posedge rst) + if (rst) + hcntr <= #1 `SSVGA_HCW'h0; + else if (hcntr == `SSVGA_HTOT - 1) + hcntr <= #1 `SSVGA_HCW'h0; + else + hcntr <= #1 hcntr + 1; +// +// Horizontal sync +// +always @(posedge crt_clk or posedge rst) + if (rst) + hsync <= #1 1'b0; + else if (hcntr == `SSVGA_HCW'h0) + hsync <= #1 1'b1; + else if (hcntr == `SSVGA_HPULSE) + hsync <= #1 1'b0 ; + +// +// Vertical counter +// +always @(posedge crt_clk or posedge rst) + if (rst) + vcntr <= #1 `SSVGA_VCW'h0; + else if ((vcntr == `SSVGA_VTOT - 1) && line_end) + vcntr <= #1 `SSVGA_VCW'h0; + else if ( line_end ) + vcntr <= #1 vcntr + 1; +// +// Vertical sync +// +always @(posedge crt_clk or posedge rst) + if (rst) + vsync <= #1 1'b0; + else if ((vcntr == `SSVGA_VCW'd0) && line_end) + vsync <= #1 1'b1; + else if ((vcntr == `SSVGA_VPULSE) && line_end) + vsync <= #1 1'b0; +endmodule Index: verilog/timescale.v =================================================================== --- verilog/timescale.v (nonexistent) +++ verilog/timescale.v (revision 154) @@ -0,0 +1 @@ +`timescale 1ns/10ps

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