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URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

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    /pci/tags/rel_8/apps/crt/syn/out
    from Rev 120 to Rev 154
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  •

Rev 120 → Rev 154

/bit/fe.log
0,0 → 1,742
ngdbuild -p xc2s150-5-pq208 -uc pci_crt.ucf -dd .. f:\mihad\fpga_t~1\pci_crt\pci_crt.edf pci_crt.ngd
Release 3.3.08i - ngdbuild D.27
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
 
Command Line: ngdbuild -p xc2s150-5-pq208 -uc pci_crt.ucf -dd ..
f:\mihad\fpga_t~1\pci_crt\pci_crt.edf pci_crt.ngd
 
Launcher: Executing edif2ngd "f:\mihad\fpga_t~1\pci_crt\pci_crt.edf"
"F:\mihad\fpga_t~1\pci_crt\xproj\ver2\pci_crt.ngo"
Release 3.3.08i - edif2ngd D.27
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
Writing the design to "F:/mihad/fpga_t~1/pci_crt/xproj/ver2/pci_crt.ngo"...
Reading NGO file "F:/mihad/fpga_t~1/pci_crt/xproj/ver2/pci_crt.ngo" ...
Reading component libraries for design expansion...
 
Annotating constraints to design from file "pci_crt.ucf" ...
 
Checking timing specifications ...
 
Checking expanded design ...
WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol "CRT/ssvga_pallete", the
following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
used.
WARNING:NgdBuild:526 - On the RAMB4_S8_S16 symbol "CRT/ssvga_fifo/ramb4_s8_1",
the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
used.
WARNING:NgdBuild:526 - On the RAMB4_S8_S16 symbol "CRT/ssvga_fifo/ramb4_s8_0",
the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
used.
WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol
"bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_0", the
following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
used.
WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol
"bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_1", the
following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
used.
WARNING:NgdBuild:526 - On the RAMB4_S16_S16 symbol
"bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2", the
following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03,
INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B,
INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be
used.
 
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 6
 
Writing NGD file "pci_crt.ngd" ...
 
Writing NGDBUILD log file "pci_crt.bld"...
 
NGDBUILD done.
 
==================================================
 
map -p xc2s150-5-pq208 -o map.ncd -pr b pci_crt.ngd pci_crt.pcf
Release 3.3.08i - Map D.27
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
Using target part "2s150pq208-5".
Reading NGD file "pci_crt.ngd"...
Processing FMAPs...
Removing unused or disabled logic...
Running cover...
Writing file map.ngm...
Running directed packing...
Running delay-based packing...
Running related packing...
Writing design file "map.ncd"...
 
Design Summary:
Number of errors: 0
Number of warnings: 72
Number of Slices: 1,402 out of 1,728 81%
Number of Slices containing
unrelated logic: 0 out of 1,402 0%
Number of Slice Flip Flops: 1,135 out of 3,456 32%
Total Number 4 input LUTs: 1,863 out of 3,456 53%
Number used as LUTs: 1,720
Number used as a route-thru: 1
Number used for Dual Port RAMs: 142
(Two LUTs used per Dual Port RAM)
Number of bonded IOBs: 64 out of 140 45%
IOB Flip Flops: 147
Number of Block RAMs: 6 out of 12 50%
Number of GCLKs: 2 out of 4 50%
Number of GCLKIOBs: 2 out of 4 50%
Total equivalent gate count for design: 129,333
Additional JTAG gate count for IOBs: 3,168
 
Removed Logic Summary:
11 block(s) removed
121 block(s) optimized away
1 signal(s) removed
 
Mapping completed.
See MAP report file "map.mrp" for details.
 
==================================================
 
par -w -ol 2 map.ncd pci_crt.ncd pci_crt.pcf
Release 3.3.08i - Par D.27
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
 
 
 
 
Constraints file: pci_crt.pcf
 
Loading design for application par from file map.ncd.
"TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5
Loading device for application par from file 'v150.nph' in environment
C:/Foundation.
Device speed data version: PRELIMINARY 1.21 2001-04-09.
 
 
Resolving physical constraints.
Finished resolving physical constraints.
 
Device utilization summary:
 
Number of External GCLKIOBs 2 out of 4 50%
Number of External IOBs 64 out of 140 45%
 
Number of BLOCKRAMs 6 out of 12 50%
Number of SLICEs 1402 out of 1728 81%
 
Number of GCLKs 2 out of 4 50%
 
 
 
Overall effort level (-ol): 2 (set by user)
Placer effort level (-pl): 2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl): 2 (set by user)
 
Starting initial Timing Analysis. REAL time: 14 secs
Finished initial Timing Analysis. REAL time: 40 secs
 
Design passed SelectIO DRC.
Starting the placer. REAL time: 43 secs
Placement pass 1 ...................
Placer score = 379658
Placement pass 2 .........................
Placer score = 368407
Placement pass 3 .....................
Placer score = 369308
Optimizing ...
Placer score = 301933
Improving the placement. REAL time: 1 mins 15 secs
Placer score = 474349
Placer score = 507794
Placer score = 471774
Placer score = 440616
Placer score = 418456
Placer score = 403030
Placer score = 390280
Placer score = 381864
Placer score = 372761
Placer score = 367215
Placer score = 361011
Placer score = 356024
Placer score = 346592
Placer score = 342238
Placer score = 339291
Placer score = 335589
Placer score = 332722
Placer score = 328768
Placer score = 324807
Placer score = 319970
Placer score = 316171
Placer score = 310589
Placer score = 305289
Placer score = 300126
Placer score = 295734
Placer score = 293094
Placer score = 290570
Placer score = 288768
Placer score = 287281
Placer score = 285736
Placer score = 284379
Placer score = 283262
Placer score = 282647
Placer score = 282077
Placer stage completed in real time: 2 mins 38 secs
 
All IOBs have been constrained to specific sites.
 
Select IO Utilization and Usage Summary
_______________________________________
 
NR - means Not Required.
Each Group of a specific Standard is listed.
 
IO standard (PCI33_5 Vref=NR Vcco=3.30) occupies 48 pads.
IO standard (LVTTL Vref=NR Vcco=3.30) occupies 18 pads.
 
Bank Summary
____________
If an IOB is placed in a Vref site, it will be indicated by the word 'Vref' at
the end of a summary row. IOBs can be placed in a bank's Vref sites when none of
the IOBs in the bank require a Vref site.
NR - means Not Required
 
Bank 0 has 17 pads and is 58% utilized.
Vref should be set to NR volts.
Vcco should be set to 3.30 volts.
Name IO Select Std Vref Vcco Pad Pin
---- -- ---------- ------ ------ ------ ------
AD<28> IO PCI33_5 NR 3.30 PAD2 P206
AD<29> IO PCI33_5 NR 3.30 PAD6 P205
AD<30> IO PCI33_5 NR 3.30 PAD10 P204
AD<31> IO PCI33_5 NR 3.30 PAD11 P203 Vref
LED O LVTTL 3.30 PAD12 P202
REQ O PCI33_5 3.30 PAD16 P201
GNT I PCI33_5 NR PAD18 P200 Vref
RST I PCI33_5 NR PAD19 P199
INTA O PCI33_5 3.30 PAD20 P195
CLK I LVTTL NR GCLKPAD3 P185
 
Bank 1 has 19 pads and is 68% utilized.
Vref should be set to NR volts.
Vcco should be set to 3.30 volts.
Name IO Select Std Vref Vcco Pad Pin
---- -- ---------- ------ ------ ------ ------
CRT_CLK I LVTTL NR GCLKPAD2 P182
RGB<15> O LVTTL 3.30 PAD38 P181
RGB<14> O LVTTL 3.30 PAD40 P180
RGB<13> O LVTTL 3.30 PAD42 P179
RGB<12> O LVTTL 3.30 PAD43 P178 Vref
RGB<11> O LVTTL 3.30 PAD44 P176
RGB<10> O LVTTL 3.30 PAD45 P175
RGB<9> O LVTTL 3.30 PAD48 P174
RGB<8> O LVTTL 3.30 PAD52 P173
RGB<7> O LVTTL 3.30 PAD53 P172
RGB<6> O LVTTL 3.30 PAD54 P168
RGB<5> O LVTTL 3.30 PAD55 P167 Vref
RGB<4> O LVTTL 3.30 PAD57 P166
 
Bank 4 has 19 pads and is 10% utilized.
Vcco should be set to 3.30 volts.
Name IO Select Std Vref Vcco Pad Pin
---- -- ---------- ------ ------ ------ ------
VSYNC O LVTTL 3.30 PAD174 P84 Vref
HSYNC O LVTTL 3.30 PAD175 P83
 
Bank 5 has 16 pads and is 43% utilized.
Vref should be set to NR volts.
Vcco should be set to 3.30 volts.
Name IO Select Std Vref Vcco Pad Pin
---- -- ---------- ------ ------ ------ ------
AD<0> IO PCI33_5 NR 3.30 PAD197 P67
AD<1> IO PCI33_5 NR 3.30 PAD198 P63
AD<2> IO PCI33_5 NR 3.30 PAD199 P62 Vref
AD<3> IO PCI33_5 NR 3.30 PAD201 P61
AD<4> IO PCI33_5 NR 3.30 PAD206 P59 Vref
AD<5> IO PCI33_5 NR 3.30 PAD207 P58
AD<6> IO PCI33_5 NR 3.30 PAD211 P57
 
Bank 6 has 18 pads and is 94% utilized.
Vref should be set to NR volts.
Vcco should be set to 3.30 volts.
Name IO Select Std Vref Vcco Pad Pin
---- -- ---------- ------ ------ ------ ------
AD<7> IO PCI33_5 NR 3.30 PAD217 P49
CBE<0> IO PCI33_5 NR 3.30 PAD218 P48
AD<8> IO PCI33_5 NR 3.30 PAD222 P47
AD<9> IO PCI33_5 NR 3.30 PAD226 P46
AD<10> IO PCI33_5 NR 3.30 PAD227 P45 Vref
AD<11> IO PCI33_5 NR 3.30 PAD232 P43
AD<12> IO PCI33_5 NR 3.30 PAD234 P42 Vref
AD<13> IO PCI33_5 NR 3.30 PAD235 P41
AD<14> IO PCI33_5 NR 3.30 PAD236 P37
AD<15> IO PCI33_5 NR 3.30 PAD237 P36
CBE<1> IO PCI33_5 NR 3.30 PAD241 P35
PAR IO PCI33_5 NR 3.30 PAD244 P34
SERR O PCI33_5 3.30 PAD245 P33
PERR IO PCI33_5 NR 3.30 PAD246 P31 Vref
STOP IO PCI33_5 NR 3.30 PAD247 P30
DEVSEL IO PCI33_5 NR 3.30 PAD249 P29
TRDY IO PCI33_5 NR 3.30 PAD252 P27
 
Bank 7 has 18 pads and is 94% utilized.
Vref should be set to NR volts.
Vcco should be set to 3.30 volts.
Name IO Select Std Vref Vcco Pad Pin
---- -- ---------- ------ ------ ------ ------
IRDY IO PCI33_5 NR 3.30 PAD253 P24
FRAME IO PCI33_5 NR 3.30 PAD254 P23
CBE<2> IO PCI33_5 NR 3.30 PAD256 P22
AD<16> IO PCI33_5 NR 3.30 PAD258 P21
AD<17> IO PCI33_5 NR 3.30 PAD259 P20 Vref
AD<18> IO PCI33_5 NR 3.30 PAD260 P18
AD<19> IO PCI33_5 NR 3.30 PAD261 P17
AD<20> IO PCI33_5 NR 3.30 PAD264 P16
AD<21> IO PCI33_5 NR 3.30 PAD268 P15
AD<22> IO PCI33_5 NR 3.30 PAD269 P14
AD<23> IO PCI33_5 NR 3.30 PAD270 P10
IDSEL I LVTTL NR PAD271 P9 Vref
CBE<3> IO PCI33_5 NR 3.30 PAD273 P8
AD<24> IO PCI33_5 NR 3.30 PAD278 P6 Vref
AD<25> IO PCI33_5 NR 3.30 PAD279 P5
AD<26> IO PCI33_5 NR 3.30 PAD283 P4
AD<27> IO PCI33_5 NR 3.30 PAD287 P3
 
Placer completed in real time: 2 mins 40 secs
 
Dumping design to file pci_crt.ncd.
 
Total REAL time to Placer completion: 2 mins 49 secs
Total CPU time to Placer completion: 2 mins 30 secs
 
0 connection(s) routed; 9789 unrouted active, 56 unrouted PWR/GND.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 3 mins 4 secs
Starting iterative routing.
Routing active signals.
.....................
End of iteration 1
9845 successful; 0 unrouted; (0) REAL time: 5 mins 31 secs
Constraints are met.
Total REAL time: 5 mins 36 secs
Total CPU time: 5 mins
End of route. 9845 routed (100.00%); 0 unrouted.
No errors found.
Completely routed.
 
Total REAL time to Router completion: 5 mins 43 secs
Total CPU time to Router completion: 5 mins 5 secs
 
Generating PAR statistics.
Timing Score: 0
 
Asterisk (*) preceding a constraint indicates it was not met.
 
--------------------------------------------------------------------------------
Constraint | Requested | Actual | Logic
| | | Levels
--------------------------------------------------------------------------------
TS_CLK = PERIOD TIMEGRP "CLK" 30 nS HI | 30.000ns | 23.294ns | 8
GH 50.000 % | | |
--------------------------------------------------------------------------------
TS_CRT_CLK = PERIOD TIMEGRP "CRT_CLK" 44 | 44.000ns | 23.360ns | 6
nS HIGH 50.000 % | | |
--------------------------------------------------------------------------------
TS_CLK_2_CRT_CLK = MAXDELAY FROM TIMEGRP | 30.000ns | 21.603ns | 9
"CLK" TO TIMEGRP "CRT_CLK" 30 nS | | |
--------------------------------------------------------------------------------
TS_CRT_CLK_2_CLK = MAXDELAY FROM TIMEGRP | 30.000ns | 16.423ns | 8
"CRT_CLK" TO TIMEGRP "CLK" 30 nS | | |
--------------------------------------------------------------------------------
COMP "REQ" OFFSET = OUT 12 nS AFTER COMP | 12.000ns | 9.486ns | 1
"CLK" | | |
--------------------------------------------------------------------------------
COMP "SERR" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.434ns | 1
P "CLK" | | |
--------------------------------------------------------------------------------
COMP "GNT" OFFSET = IN 10 nS BEFORE COMP | 10.000ns | 9.535ns | 5
"CLK" | | |
--------------------------------------------------------------------------------
COMP "FRAME" OFFSET = IN 7 nS BEFORE COM | 7.000ns | 6.287ns | 4
P "CLK" | | |
--------------------------------------------------------------------------------
COMP "FRAME" OFFSET = OUT 11 nS AFTER CO | 11.000ns | 9.432ns | 1
MP "CLK" | | |
--------------------------------------------------------------------------------
COMP "IRDY" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 6.442ns | 4
"CLK" | | |
--------------------------------------------------------------------------------
COMP "IRDY" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.432ns | 1
P "CLK" | | |
--------------------------------------------------------------------------------
COMP "DEVSEL" OFFSET = IN 7 nS BEFORE CO | 7.000ns | 3.800ns | 3
MP "CLK" | | |
--------------------------------------------------------------------------------
COMP "DEVSEL" OFFSET = OUT 11 nS AFTER C | 11.000ns | 9.432ns | 1
OMP "CLK" | | |
--------------------------------------------------------------------------------
COMP "TRDY" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 6.473ns | 3
"CLK" | | |
--------------------------------------------------------------------------------
COMP "TRDY" OFFSET = OUT 10 nS AFTER COM | 10.000ns | 9.435ns | 1
P "CLK" | | |
--------------------------------------------------------------------------------
COMP "STOP" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 5.665ns | 3
"CLK" | | |
--------------------------------------------------------------------------------
COMP "STOP" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.432ns | 1
P "CLK" | | |
--------------------------------------------------------------------------------
COMP "PAR" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 4.610ns | 4
"CLK" | | |
--------------------------------------------------------------------------------
COMP "PAR" OFFSET = OUT 11 nS AFTER COMP | 11.000ns | 9.434ns | 1
"CLK" | | |
--------------------------------------------------------------------------------
COMP "PERR" OFFSET = IN 7 nS BEFORE COMP | 7.000ns | 2.145ns | 2
"CLK" | | |
--------------------------------------------------------------------------------
COMP "PERR" OFFSET = OUT 11 nS AFTER COM | 11.000ns | 9.434ns | 1
P "CLK" | | |
--------------------------------------------------------------------------------
TIMEGRP "PCI_AD" OFFSET = IN 7 nS BEFORE | 7.000ns | 2.762ns | 1
COMP "CLK" | | |
--------------------------------------------------------------------------------
TIMEGRP "PCI_AD" OFFSET = OUT 11 nS AFTE | 11.000ns | 9.540ns | 1
R COMP "CLK" | | |
--------------------------------------------------------------------------------
TIMEGRP "PCI_CBE" OFFSET = IN 7 nS BEFOR | 7.000ns | 5.437ns | 4
E COMP "CLK" | | |
--------------------------------------------------------------------------------
TIMEGRP "PCI_CBE" OFFSET = OUT 11 nS AFT | 11.000ns | 9.435ns | 1
ER COMP "CLK" | | |
--------------------------------------------------------------------------------
 
 
All constraints were met.
Dumping design to file pci_crt.ncd.
 
 
All signals are completely routed.
 
Total REAL time to PAR completion: 7 mins 13 secs
Total CPU time to PAR completion: 6 mins 10 secs
 
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
 
PAR done.
 
==================================================
 
trce pci_crt.ncd pci_crt.pcf -e 3 -o pci_crt.twr -xml pci_crt_trce.xml
Release 3.3.08i - Trace D.27
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
 
 
 
Loading design for application trce from file pci_crt.ncd.
"TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5
Loading device for application trce from file 'v150.nph' in environment
C:/Foundation.
--------------------------------------------------------------------------------
Xilinx TRACE, Version D.27
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
 
trce pci_crt.ncd pci_crt.pcf -e 3 -o pci_crt.twr -xml pci_crt_trce.xml
 
Design file: pci_crt.ncd
Physical constraint file: pci_crt.pcf
Device,speed: xc2s150,-5 (PRELIMINARY 1.21 2001-04-09)
Report level: error report
--------------------------------------------------------------------------------
 
 
 
Timing summary:
---------------
 
Timing errors: 0 Score: 0
 
Constraints cover 97754 paths, 0 nets, and 8987 connections (91.8% coverage)
 
Design statistics:
Minimum period: 23.360ns (Maximum frequency: 42.808MHz)
Maximum path delay from/to any node: 21.603ns
Minimum input arrival time before clock: 9.535ns
Minimum output required time after clock: 9.540ns
 
 
Analysis completed Tue Jan 15 13:36:48 2002
--------------------------------------------------------------------------------
 
Total time: 1 mins 6 secs
 
==================================================
 
ngdanno pci_crt.ncd
Release 3.3.08i - ngdanno D.27
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
 
Loading design for application ngdanno from file pci_crt.ncd.
"TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5
Loading device for application ngdanno from file 'v150.nph' in environment
C:/Foundation.
Loading constraints from file "pci_crt.pcf"...
WARNING:Anno:12 - Since the .ngm file was not specified, the .nga will be
created from the .ncd.
Building NGA image...
Annotating NGA image...
Distributing delays...
Resolving logical and physical hierarchies...
Running NGD DRC...
WARNING:Ngd:333 - NOTE: This design contains the undriven net "GSR" which you
could drive during simulation to get valid results.
WARNING:Ngd:333 - NOTE: This design contains the undriven net "GTS" which you
could drive during simulation to get valid results.
Writing .nga file "pci_crt.nga"...
1476 physical models annotated
 
==================================================
 
ngd2ver -w pci_crt.nga pci_crt_time_sim.v
Release 3.3.08i - ngd2ver D.27
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
--- Initializing ...
--- Reading pci_crt.nga.
--- Running prep.
--- Initializing module list.
--- Processing netlist ...
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[10] not found for
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[9] not found for
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[8] not found for
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[7] not found for
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[6] not found for
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[5] not found for
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[4] not found for
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[3] not found for
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
WARNING:NetListWriters:106 - Wire bridge/pciu_err_addr_out[2] not found for
wire bus bridge/pciu_err_addr_out[31:0] on block TOP.
WARNING:NetListWriters:107 - Signal bus bridge/pciu_err_addr_out[31:0] on block
TOP is not reconstructed.
WARNING:NetListWriters:106 - Wire
bridge/pci_target_unit/pcit_if_pciw_fifo_control_out[1] not found for wire
bus bridge/pci_target_unit/pcit_if_pciw_fifo_control_out[2:0] on block TOP.
WARNING:NetListWriters:107 - Signal bus
bridge/pci_target_unit/pcit_if_pciw_fifo_control_out[2:0] on block TOP is not
reconstructed.
WARNING:NetListWriters:106 - Wire
bridge/pci_target_unit/fifos_pciw_control_out[1] not found for wire bus
bridge/pci_target_unit/fifos_pciw_control_out[2:0] on block TOP.
WARNING:NetListWriters:107 - Signal bus
bridge/pci_target_unit/fifos_pciw_control_out[2:0] on block TOP is not
reconstructed.
--- Generating ngd2ver output file(s) ...
--- Writing sdf file pci_crt_time_sim.sdf.
--- Writing netlist file pci_crt_time_sim.v.
WARNING:NetListWriters:108 - In order to compile this verilog file
successfully, please add $XILINX/verilog/src/glbl.v to your compile command.
--- ngd2ver is done !
 
==================================================
 
xcpy pci_crt_time_sim.v f:\mihad\fpga_t~1\pci_crt\pci_crt_time_sim.v
 
==================================================
 
xcpy pci_crt_time_sim.sdf f:\mihad\fpga_t~1\pci_crt\pci_crt_time_sim.sdf
 
==================================================
 
bitgen pci_crt.ncd -l -w -f bitgen.ut
Release 3.3.08i - Bitgen D.27
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
 
Loading design for application Bitgen from file pci_crt.ncd.
"TOP" is an NCD, version 2.35, device xc2s150, package pq208, speed -5
Loading device for application Bitgen from file 'v150.nph' in environment
C:/Foundation.
Opened constraints file pci_crt.pcf.
 
Tue Jan 15 13:40:02 2002
 
Running DRC.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA0 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA1 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA2 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA3 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA6 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA7 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA8 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA9 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA10 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA11 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA12 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA13 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA14 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOA15 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB5 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB6 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB7 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB8 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB9 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB10 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB11 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB12 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB13 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB14 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB15 of comp
bridge/wishbone_slave_unit/fifos/wbu_fifo_storage/ramb4_s16_s16_2 is not
connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB0 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB1 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB2 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB3 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB4 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB5 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB6 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB7 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB8 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB9 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB10 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB11 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB12 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB13 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB14 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB15 of comp
CRT/ssvga_fifo/ramb4_s8_0 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB0 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB1 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB2 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB3 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB4 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB5 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB6 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB7 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB8 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB9 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB10 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB11 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB12 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB13 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB14 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB15 of comp
CRT/ssvga_fifo/ramb4_s8_1 is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB0 of comp
CRT/ssvga_pallete is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB1 of comp
CRT/ssvga_pallete is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB2 of comp
CRT/ssvga_pallete is not connected.
WARNING:DesignRules:332 - Blockcheck: Dangling BLKRAM output. Pin DOB3 of comp
CRT/ssvga_pallete is not connected.
DRC detected 0 errors and 61 warnings.
Saving ll file in "pci_crt.ll".
Creating bit map...
Saving bit stream in "pci_crt.bit".
 
==================================================
 
xcpy pci_crt.bit f:\mihad\fpga_t~1\pci_crt\pci_crt.bit
 
==================================================
 
xcpy pci_crt.ll f:\mihad\fpga_t~1\pci_crt\pci_crt.ll
bit/fe.log Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: bit/pci_crt.bit =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: bit/pci_crt.bit =================================================================== --- bit/pci_crt.bit (nonexistent) +++ bit/pci_crt.bit (revision 154)
bit/pci_crt.bit Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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