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    /pci/tags/working_demo/apps/crt/rtl
    from Rev 8 to Rev 154
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Rev 8 → Rev 154

/verilog/ssvga_wbs_if.v
0,0 → 1,174
//////////////////////////////////////////////////////////////////////
//// ////
//// Simple Small VGA IP Core ////
//// ////
//// This file is part of the Simple Small VGA project ////
//// ////
//// ////
//// Description ////
//// LITTLE-ENDIAN WISHBONE slave interface. ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`define SEL_PAL 10
`define SEL_ADDRESS 2
 
module ssvga_wbs_if(
// Clock and reset
wb_clk_i, wb_rst_i,
// WISHBONE Slave I/F
wbs_cyc_i, wbs_stb_i, wbs_sel_i, wbs_we_i,
wbs_adr_i, wbs_dat_i, wbs_cab_i,
wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
 
// Other signals
ssvga_en, pal_wr_en, pal_rd_en, pal_dat,
pix_start_addr
);
 
//
// I/O ports
//
 
//
// Clock and reset
//
input wb_clk_i; // Pixel Clock
input wb_rst_i; // Reset
 
//
// WISHBONE Slave I/F
//
input wbs_cyc_i;
input wbs_stb_i;
input [3:0] wbs_sel_i;
input wbs_we_i;
input [31:0] wbs_adr_i;
input [31:0] wbs_dat_i;
input wbs_cab_i;
output [31:0] wbs_dat_o;
output wbs_ack_o;
output wbs_err_o;
output wbs_rty_o;
 
//
// Other signals
//
output ssvga_en; // Global enable
output pal_wr_en; // Palette write enable
output pal_rd_en; // Palette read enable
input [15:0] pal_dat; // Palette data
output [31:2] pix_start_addr ;
 
//
// Internal regs and wires
//
reg wbs_ack_o; // WISHBONE ack
reg wbs_err_o; // WISHBONE err
reg [0:0] ctrl_r; // Control register
wire valid_access; // Access to SSVGA
 
//
// Control register
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
ctrl_r <= #1 1'b0;
else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & !wbs_adr_i[`SEL_ADDRESS])
ctrl_r <= #1 wbs_dat_i[0];
 
reg [31:2] pix_start_addr ;
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
pix_start_addr <= #1 30'h0000_0000 ;
else if (valid_access & wbs_we_i & !wbs_adr_i[`SEL_PAL] & wbs_adr_i[`SEL_ADDRESS] )
pix_start_addr <= #1 wbs_dat_i[31:2] ;
 
//
// Generate delayed WISHBONE ack/err
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i) begin
wbs_ack_o <= #1 1'b0;
wbs_err_o <= #1 1'b0;
end
else if (valid_access) begin
wbs_ack_o <= #1 1'b1;
wbs_err_o <= #1 1'b0;
end
else if (wbs_cyc_i & wbs_stb_i) begin
wbs_ack_o <= #1 1'b0;
wbs_err_o <= #1 1'b1;
end
else begin
wbs_ack_o <= #1 1'b0;
wbs_err_o <= #1 1'b0;
end
 
//
// Generate WISHBONE output signals
//
reg [31:0] wbs_dat_o ;
always@(wbs_adr_i or pal_dat or ctrl_r or pix_start_addr)
begin
if ( wbs_adr_i[`SEL_PAL] )
wbs_dat_o = {16'h0000, pal_dat} ;
else
if ( wbs_adr_i[`SEL_ADDRESS] )
wbs_dat_o = {pix_start_addr, 2'b00} ;
else
wbs_dat_o = {{31{1'b0}}, ctrl_r};
end
 
assign wbs_rty_o = 1'b0;
 
//
// Generate other signals
//
assign valid_access = wbs_cyc_i & wbs_stb_i & (wbs_sel_i == 4'b1111);
assign ssvga_en = ctrl_r[0];
assign pal_wr_en = valid_access & wbs_we_i & wbs_adr_i[`SEL_PAL];
assign pal_rd_en = valid_access & ~wbs_we_i & wbs_adr_i[`SEL_PAL];
 
endmodule
/verilog/ssvga_crtc.v
0,0 → 1,167
//////////////////////////////////////////////////////////////////////
//// ////
//// Simple Small VGA IP Core ////
//// ////
//// This file is part of the Simple Small VGA project ////
//// ////
//// ////
//// Description ////
//// Hsync/Vsync generator. ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "ssvga_defines.v"
 
module ssvga_crtc(
crt_clk, rst, hsync, vsync, hblank, vblank
);
 
//
// I/O ports
//
input crt_clk;// Pixel Clock
input rst; // Reset
output hsync; // H sync
output vsync; // V sync
output hblank; // H blank
output vblank; // V blank
 
//
// Internal wires and regs
//
reg [`SSVGA_HCW-1:0] hcntr; // Horizontal counter
reg [`SSVGA_VCW-1:0] vcntr; // Vertical counter
reg hsync; // Horizontal sync
reg vsync; // Vertical sync
 
// flip - flops for decoding end of one line
reg line_end1 ;
reg line_end2 ;
 
always@(posedge crt_clk or posedge rst)
begin
if (rst)
begin
line_end1 <= #1 1'b0 ;
line_end2 <= #1 1'b0 ;
end
else
begin
line_end1 <= #1 hsync ;
line_end2 <= #1 line_end1 ;
end
end
 
wire line_end = ~line_end2 && line_end1 ;
 
//
// Assert hblank when hsync is not asserted
//
reg hblank ;
always@(posedge crt_clk or posedge rst)
begin
if (rst)
hblank <= #1 1'b0 ;
else
if ( hcntr == (`SSVGA_HPULSE + `SSVGA_HBACKP) )
hblank <= #1 1'b0 ;
else
if ( hcntr == (`SSVGA_HTOT - `SSVGA_HFRONTP) )
hblank <= #1 1'b1 ;
end
 
reg vblank ;
always@(posedge crt_clk or posedge rst)
begin
if ( rst )
vblank <= #1 1'b0 ;
else
if ((vcntr == (`SSVGA_VPULSE + `SSVGA_VBACKP)) && line_end)
vblank <= #1 1'b0 ;
else
if ((vcntr == (`SSVGA_VTOT - `SSVGA_VFRONTP)) && line_end)
vblank <= #1 1'b1 ;
end
 
//
// Horizontal counter
//
always @(posedge crt_clk or posedge rst)
if (rst)
hcntr <= #1 `SSVGA_HCW'h0;
else if (hcntr == `SSVGA_HTOT - 1)
hcntr <= #1 `SSVGA_HCW'h0;
else
hcntr <= #1 hcntr + 1;
//
// Horizontal sync
//
always @(posedge crt_clk or posedge rst)
if (rst)
hsync <= #1 1'b0;
else if (hcntr == `SSVGA_HCW'h0)
hsync <= #1 1'b1;
else if (hcntr == `SSVGA_HPULSE)
hsync <= #1 1'b0 ;
 
//
// Vertical counter
//
always @(posedge crt_clk or posedge rst)
if (rst)
vcntr <= #1 `SSVGA_VCW'h0;
else if ((vcntr == `SSVGA_VTOT - 1) && line_end)
vcntr <= #1 `SSVGA_VCW'h0;
else if ( line_end )
vcntr <= #1 vcntr + 1;
//
// Vertical sync
//
always @(posedge crt_clk or posedge rst)
if (rst)
vsync <= #1 1'b0;
else if ((vcntr == `SSVGA_VCW'd0) && line_end)
vsync <= #1 1'b1;
else if ((vcntr == `SSVGA_VPULSE) && line_end)
vsync <= #1 1'b0;
endmodule
/verilog/ssvga_defines.v
0,0 → 1,72
//////////////////////////////////////////////////////////////////////
//// ////
//// Simple Small VGA IP Core ////
//// ////
//// This file is part of the Simple Small VGA project ////
//// ////
//// ////
//// Description ////
//// Definitions. ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
//`define XILINX_RAMB4
`define SSVGA_640x480
 
`ifdef SSVGA_640x480
`define PIXEL_NUM 'd307200 // 383330
`define SSVGA_HCW 10
`define SSVGA_VCW 10
//`define SSVGA_HTOT `SSVGA_HCW'd3178
//`define SSVGA_HPULSE `SSVGA_HCW'd381
`define SSVGA_HTOT `SSVGA_HCW'd750
`define SSVGA_HPULSE `SSVGA_HCW'd90
`define SSVGA_HFRONTP `SSVGA_HCW'd10
`define SSVGA_HBACKP `SSVGA_HCW'd10
 
//`define SSVGA_VTOT `SSVGA_VCW'd525
//`define SSVGA_VPULSE `SSVGA_VCW'd3
`define SSVGA_VTOT `SSVGA_VCW'd511
`define SSVGA_VPULSE `SSVGA_VCW'd4
`define SSVGA_VFRONTP `SSVGA_HCW'd12
`define SSVGA_VBACKP `SSVGA_HCW'd15
`define SSVGA_VMCW 17
`endif
 
`define XILINX_RAMB4
/verilog/top.v
0,0 → 1,425
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "top.v" ////
//// ////
//// This file is part of the PCI bridge sample aplication ////
//// project (CRT controller). ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc (mihad@opencores.org) ////
//// ////
//// All additional information is avaliable in the README ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// This top module is used for simulation and synthesys of CRT controller
// sample aplication.
 
module TOP
(
CLK,
AD,
CBE,
RST,
INTA,
REQ,
GNT,
FRAME,
IRDY,
IDSEL,
DEVSEL,
TRDY,
STOP,
PAR,
PERR,
SERR,
/* CLK_I,
RST_I,
RST_O,
INT_I,
INT_O,
 
// WISHBONE slave interface
ADR_I,
SDAT_I,
SDAT_O,
SEL_I,
CYC_I,
STB_I,
WE_I,
CAB_I,
ACK_O,
RTY_O,
ERR_O,
 
// WISHBONE master interface
ADR_O,
MDAT_I,
MDAT_O,
SEL_O,
CYC_O,
STB_O,
WE_O,
CAB_O,
ACK_I,
RTY_I,
ERR_I */
 
CRT_CLK,
HSYNC,
VSYNC,
RGB,
LED
);
 
input CLK ;
inout [31:0] AD ;
inout [3:0] CBE ;
inout RST ;
inout INTA ;
output REQ ;
input GNT ;
inout FRAME ;
inout IRDY ;
input IDSEL ;
inout DEVSEL ;
inout TRDY ;
inout STOP ;
inout PAR ;
inout PERR ;
output SERR ;
 
input CRT_CLK ;
// CRT outputs
output HSYNC ;
output VSYNC ;
output [15:4] RGB ;
output LED ;
 
// WISHBONE system signals
wire RST_I = 1'b0 ;
wire RST_O ;
wire INT_I = 1'b0 ;
wire INT_O ;
 
wire [15:0] rgb_int ;
// WISHBONE slave interface
wire [31:0] ADR_I ;
wire [31:0] SDAT_I ;
wire [31:0] SDAT_O ;
wire [3:0] SEL_I ;
wire CYC_I ;
wire STB_I ;
wire WE_I ;
wire CAB_I ;
wire ACK_O ;
wire RTY_O ;
wire ERR_O ;
 
// WISHBONE master interface
wire [31:0] ADR_O ;
wire [31:0] MDAT_I ;
wire [31:0] MDAT_O ;
wire [3:0] SEL_O ;
wire CYC_O ;
wire STB_O ;
wire WE_O ;
wire CAB_O ;
wire ACK_I ;
wire RTY_I ;
wire ERR_I ;
 
wire [31:0] AD_out ;
wire [31:0] AD_en ;
 
 
wire [31:0] AD_in = AD ;
 
wire [3:0] CBE_in = CBE ;
wire [3:0] CBE_out ;
wire [3:0] CBE_en ;
 
 
 
wire RST_in = RST ;
wire RST_out ;
wire RST_en ;
 
wire INTA_in = INTA ;
wire INTA_en ;
wire INTA_out ;
 
wire REQ_en ;
wire REQ_out ;
 
wire FRAME_in = FRAME ;
wire FRAME_out ;
wire FRAME_en ;
 
wire IRDY_in = IRDY ;
wire IRDY_out ;
wire IRDY_en ;
 
wire DEVSEL_in = DEVSEL ;
wire DEVSEL_out ;
wire DEVSEL_en ;
 
wire TRDY_in = TRDY ;
wire TRDY_out ;
wire TRDY_en ;
 
wire STOP_in = STOP ;
wire STOP_out ;
wire STOP_en ;
 
wire PAR_in = PAR ;
wire PAR_out ;
wire PAR_en ;
 
wire PERR_in = PERR ;
wire PERR_out ;
wire PERR_en ;
 
wire SERR_out ;
wire SERR_en ;
 
PCI_BRIDGE32 bridge
(
// WISHBONE system signals
.CLK_I(CLK),
.RST_I(RST_I),
.RST_O(RST_O),
.INT_I(INT_I),
.INT_O(INT_O),
// WISHBONE slave interface
.ADR_I(ADR_I),
.SDAT_I(SDAT_I),
.SDAT_O(SDAT_O),
.SEL_I(SEL_I),
.CYC_I(CYC_I),
.STB_I(STB_I),
.WE_I(WE_I),
.CAB_I(CAB_I),
.ACK_O(ACK_O),
.RTY_O(RTY_O),
.ERR_O(ERR_O),
// WISHBONE master interface
.ADR_O(ADR_O),
.MDAT_I(MDAT_I),
.MDAT_O(MDAT_O),
.SEL_O(SEL_O),
.CYC_O(CYC_O),
.STB_O(STB_O),
.WE_O(WE_O),
.CAB_O(CAB_O),
.ACK_I(ACK_I),
.RTY_I(RTY_I),
.ERR_I(ERR_I),
// pci interface - system pins
.PCI_CLK_IN (CLK),
.PCI_RSTn_IN ( RST_in ),
.PCI_RSTn_OUT ( RST_out ),
.PCI_INTAn_IN ( INTA_in ),
.PCI_INTAn_OUT( INTA_out),
.PCI_RSTn_EN_OUT( RST_en),
.PCI_INTAn_EN_OUT(INTA_en),
// arbitration pins
.PCI_REQn_OUT( REQ_out ),
.PCI_REQn_EN_OUT ( REQ_en ),
.PCI_GNTn_IN( GNT ),
// protocol pins
.PCI_FRAMEn_IN( FRAME_in),
.PCI_FRAMEn_OUT( FRAME_out ),
 
.PCI_FRAMEn_EN_OUT( FRAME_en ),
.PCI_IRDYn_EN_OUT ( IRDY_en ),
.PCI_DEVSELn_EN_OUT ( DEVSEL_en ),
.PCI_TRDYn_EN_OUT ( TRDY_en ),
.PCI_STOPn_EN_OUT ( STOP_en ),
.PCI_AD_EN_OUT(AD_en),
.PCI_CBEn_EN_OUT ( CBE_en) ,
.PCI_IRDYn_IN ( IRDY_in ),
.PCI_IRDYn_OUT ( IRDY_out ),
.PCI_IDSEL_IN ( IDSEL ),
.PCI_DEVSELn_IN( DEVSEL_in ),
.PCI_DEVSELn_OUT ( DEVSEL_out ),
.PCI_TRDYn_IN ( TRDY_in ),
.PCI_TRDYn_OUT ( TRDY_out ),
.PCI_STOPn_IN( STOP_in ),
.PCI_STOPn_OUT ( STOP_out ),
// data transfer pins
.PCI_AD_IN(AD_in),
.PCI_AD_OUT (AD_out),
.PCI_CBEn_IN( CBE_in ),
.PCI_CBEn_OUT ( CBE_out ),
// parity generation and checking pins
.PCI_PAR_IN ( PAR_in ),
.PCI_PAR_OUT ( PAR_out ),
.PCI_PAR_EN_OUT ( PAR_en ),
.PCI_PERRn_IN ( PERR_in ),
.PCI_PERRn_OUT ( PERR_out ),
.PCI_PERRn_EN_OUT ( PERR_en ),
// system error pin
.PCI_SERRn_OUT ( SERR_out ),
.PCI_SERRn_EN_OUT ( SERR_en )
);
 
// PCI IO buffers instantiation
bufif0 AD_buf0 ( AD[0], AD_out[0], AD_en[0]) ;
bufif0 AD_buf1 ( AD[1], AD_out[1], AD_en[1]) ;
bufif0 AD_buf2 ( AD[2], AD_out[2], AD_en[2]) ;
bufif0 AD_buf3 ( AD[3], AD_out[3], AD_en[3]) ;
bufif0 AD_buf4 ( AD[4], AD_out[4], AD_en[4]) ;
bufif0 AD_buf5 ( AD[5], AD_out[5], AD_en[5]) ;
bufif0 AD_buf6 ( AD[6], AD_out[6], AD_en[6]) ;
bufif0 AD_buf7 ( AD[7], AD_out[7], AD_en[7]) ;
bufif0 AD_buf8 ( AD[8], AD_out[8], AD_en[8]) ;
bufif0 AD_buf9 ( AD[9], AD_out[9], AD_en[9]) ;
bufif0 AD_buf10 ( AD[10], AD_out[10],AD_en[10] ) ;
bufif0 AD_buf11 ( AD[11], AD_out[11],AD_en[11] ) ;
bufif0 AD_buf12 ( AD[12], AD_out[12],AD_en[12] ) ;
bufif0 AD_buf13 ( AD[13], AD_out[13],AD_en[13] ) ;
bufif0 AD_buf14 ( AD[14], AD_out[14],AD_en[14] ) ;
bufif0 AD_buf15 ( AD[15], AD_out[15],AD_en[15] ) ;
bufif0 AD_buf16 ( AD[16], AD_out[16],AD_en[16] ) ;
bufif0 AD_buf17 ( AD[17], AD_out[17],AD_en[17] ) ;
bufif0 AD_buf18 ( AD[18], AD_out[18],AD_en[18] ) ;
bufif0 AD_buf19 ( AD[19], AD_out[19],AD_en[19] ) ;
bufif0 AD_buf20 ( AD[20], AD_out[20],AD_en[20] ) ;
bufif0 AD_buf21 ( AD[21], AD_out[21],AD_en[21] ) ;
bufif0 AD_buf22 ( AD[22], AD_out[22],AD_en[22] ) ;
bufif0 AD_buf23 ( AD[23], AD_out[23],AD_en[23] ) ;
bufif0 AD_buf24 ( AD[24], AD_out[24],AD_en[24] ) ;
bufif0 AD_buf25 ( AD[25], AD_out[25],AD_en[25] ) ;
bufif0 AD_buf26 ( AD[26], AD_out[26],AD_en[26] ) ;
bufif0 AD_buf27 ( AD[27], AD_out[27],AD_en[27] ) ;
bufif0 AD_buf28 ( AD[28], AD_out[28],AD_en[28] ) ;
bufif0 AD_buf29 ( AD[29], AD_out[29],AD_en[29] ) ;
bufif0 AD_buf30 ( AD[30], AD_out[30],AD_en[30] ) ;
bufif0 AD_buf31 ( AD[31], AD_out[31],AD_en[31] ) ;
 
bufif0 CBE_buf0 ( CBE[0], CBE_out[0], CBE_en[0] ) ;
bufif0 CBE_buf1 ( CBE[1], CBE_out[1], CBE_en[1] ) ;
bufif0 CBE_buf2 ( CBE[2], CBE_out[2], CBE_en[2] ) ;
bufif0 CBE_buf3 ( CBE[3], CBE_out[3], CBE_en[3] ) ;
bufif0 FRAME_buf ( FRAME, FRAME_out, FRAME_en ) ;
bufif0 IRDY_buf ( IRDY, IRDY_out, IRDY_en ) ;
bufif0 DEVSEL_buf ( DEVSEL, DEVSEL_out, DEVSEL_en ) ;
bufif0 TRDY_buf ( TRDY, TRDY_out, TRDY_en ) ;
bufif0 STOP_buf ( STOP, STOP_out, STOP_en ) ;
bufif0 RST_buf ( RST, RST_out, RST_en ) ;
bufif0 INTA_buf ( INTA, INTA_out, INTA_en) ;
bufif0 REQ_buf ( REQ, REQ_out, REQ_en ) ;
bufif0 PAR_buf ( PAR, PAR_out, PAR_en ) ;
bufif0 PERR_buf ( PERR, PERR_out, PERR_en ) ;
bufif0 SERR_buf ( SERR, SERR_out, SERR_en ) ;
 
wire crt_hsync ;
wire crt_vsync ;
 
// CRT controler instance
ssvga_top CRT
(
// Clock and reset
.wb_clk_i(CLK),
.wb_rst_i(RST_O),
.crt_clk_i(CRT_CLK),
// WISHBONE Master I/F
.wbm_cyc_o (CYC_I),
.wbm_stb_o (STB_I),
.wbm_sel_o (SEL_I),
.wbm_we_o (WE_I),
.wbm_adr_o (ADR_I),
.wbm_dat_o (SDAT_I),
.wbm_cab_o (CAB_I),
.wbm_dat_i (SDAT_O),
.wbm_ack_i (ACK_O),
.wbm_err_i (ERR_O),
.wbm_rty_i (RTY_O),
 
// WISHBONE Slave I/F
.wbs_cyc_i (CYC_O),
.wbs_stb_i (STB_O),
.wbs_sel_i (SEL_O),
.wbs_we_i (WE_O),
.wbs_adr_i (ADR_O),
.wbs_dat_i (MDAT_O),
.wbs_cab_i (CAB_O),
.wbs_dat_o (MDAT_I),
.wbs_ack_o (ACK_I),
.wbs_err_o (ERR_I),
.wbs_rty_o (RTY_I),
 
// Signals to VGA display
.pad_hsync_o (crt_hsync),
.pad_vsync_o (crt_vsync),
.pad_rgb_o (rgb_int),
.led_o (LED)
);
 
CRTC_IOB crt_out_reg
(
.reset_in(RST_O),
.clk_in(CRT_CLK),
.hsync_in(crt_hsync),
.vsync_in(crt_vsync),
.rgb_in(rgb_int[15:4]),
.hsync_out(HSYNC),
.vsync_out(VSYNC),
.rgb_out(RGB)
) ;
 
endmodule
/verilog/ssvga_top.v
0,0 → 1,303
//////////////////////////////////////////////////////////////////////
//// ////
//// Simple Small VGA IP Core ////
//// ////
//// This file is part of the Simple Small VGA project ////
//// ////
//// ////
//// Description ////
//// Top level of SSVGA. ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module ssvga_top(
// Clock and reset
wb_clk_i, wb_rst_i,
crt_clk_i,
// WISHBONE Master I/F
wbm_cyc_o, wbm_stb_o, wbm_sel_o, wbm_we_o,
wbm_adr_o, wbm_dat_o, wbm_cab_o,
wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
 
// WISHBONE Slave I/F
wbs_cyc_i, wbs_stb_i, wbs_sel_i, wbs_we_i,
wbs_adr_i, wbs_dat_i, wbs_cab_i,
wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
 
// Signals to VGA display
pad_hsync_o, pad_vsync_o, pad_rgb_o, led_o
);
 
//
// I/O ports
//
 
//
// Clock and reset
//
input wb_clk_i; // Write Clock
input wb_rst_i; // Reset
input crt_clk_i; // Pixel Clock
 
//
// WISHBONE Master I/F
//
output wbm_cyc_o;
output wbm_stb_o;
output [3:0] wbm_sel_o;
output wbm_we_o;
output [31:0] wbm_adr_o;
output [31:0] wbm_dat_o;
output wbm_cab_o;
input [31:0] wbm_dat_i;
input wbm_ack_i;
input wbm_err_i;
input wbm_rty_i;
 
//
// WISHBONE Slave I/F
//
input wbs_cyc_i;
input wbs_stb_i;
input [3:0] wbs_sel_i;
input wbs_we_i;
input [31:0] wbs_adr_i;
input [31:0] wbs_dat_i;
input wbs_cab_i;
output [31:0] wbs_dat_o;
output wbs_ack_o;
output wbs_err_o;
output wbs_rty_o;
 
//
// VGA display
//
output pad_hsync_o; // H sync
output pad_vsync_o; // V sync
output [15:0] pad_rgb_o; // Digital RGB data
output led_o;
 
//
// Internal wires and regs
//
wire ssvga_en; // Global enable
wire fifo_full; // FIFO full flag
wire fifo_empty; // FIFO empty flag
wire wbm_restart ; // indicator on when WISHBONE master should restart whole screen because of pixel buffer underrun
wire crtc_hblank; // H blank
wire crtc_vblank; // V blank
wire fifo_wr_en; // FIFO write enable
wire fifo_rd_en; // FIFO read enable
wire [31:0] fifo_in; // FIFO input data
wire [7:0] fifo_out; // FIFO output data
//wire [7:0] pal_indx; // Palette index
wire pal_wr_en; // Palette write enable
wire pal_rd_en; // Palette read enable
wire [15:0] pal_pix_dat ; // pixel output from pallete RAM
 
reg go ;
 
// rgb output assignment - when blank output transmits black pixels, otherwise it transmits pallete data
reg drive_blank_reg ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
if ( wb_rst_i )
drive_blank_reg <= #1 1'b0 ;
else
drive_blank_reg <= #1 ( crtc_hblank || crtc_vblank || ~go ) ;
end
 
assign pad_rgb_o = drive_blank_reg ? 16'h0000 : pal_pix_dat ;
 
assign led_o = ssvga_en ;
 
//
// Read FIFO when blanks are not asserted and fifo has been filled once
//
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
if ( wb_rst_i )
go <= #1 1'b0 ;
else
if ( ~ssvga_en )
go <= #1 1'b0 ;
else
go <= #1 ( fifo_full & crtc_hblank & crtc_vblank ) || ( go && ~fifo_empty ) ;
end
 
assign fifo_rd_en = !crtc_hblank & !crtc_vblank & go ;
 
assign wbm_restart = go & fifo_empty ;
 
//
// Palette index is either color index from FIFO or
// address from WISHBONE slave when writing into palette
//
//assign pal_indx = (pal_wr_en || pal_rd_en) ? wbs_adr_i[9:2] : fifo_out;
 
//
// Instantiation of WISHBONE Master block
//
wire [31:2] pix_start_addr ;
ssvga_wbm_if ssvga_wbm_if(
 
// Clock and reset
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
 
// WISHBONE Master I/F
.wbm_cyc_o(wbm_cyc_o),
.wbm_stb_o(wbm_stb_o),
.wbm_sel_o(wbm_sel_o),
.wbm_we_o(wbm_we_o),
.wbm_adr_o(wbm_adr_o),
.wbm_dat_o(wbm_dat_o),
.wbm_cab_o(wbm_cab_o),
.wbm_dat_i(wbm_dat_i),
.wbm_ack_i(wbm_ack_i),
.wbm_err_i(wbm_err_i),
.wbm_rty_i(wbm_rty_i),
 
// FIFO control and other signals
.ssvga_en(ssvga_en),
.fifo_full(fifo_full),
.fifo_wr_en(fifo_wr_en),
.fifo_dat(fifo_in),
.pix_start_addr(pix_start_addr),
.resync(wbm_restart)
);
 
//
// Instantiation of WISHBONE Slave block
//
wire [15:0] wbs_pal_data ;
ssvga_wbs_if ssvga_wbs_if(
 
// Clock and reset
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
 
// WISHBONE Slave I/F
.wbs_cyc_i(wbs_cyc_i),
.wbs_stb_i(wbs_stb_i),
.wbs_sel_i(wbs_sel_i),
.wbs_we_i(wbs_we_i),
.wbs_adr_i(wbs_adr_i),
.wbs_dat_i(wbs_dat_i),
.wbs_cab_i(wbs_cab_i),
.wbs_dat_o(wbs_dat_o),
.wbs_ack_o(wbs_ack_o),
.wbs_err_o(wbs_err_o),
.wbs_rty_o(wbs_rty_o),
 
// Control for other SSVGA blocks
.ssvga_en(ssvga_en),
.pal_wr_en(pal_wr_en),
.pal_rd_en(pal_rd_en),
.pal_dat(wbs_pal_data),
.pix_start_addr(pix_start_addr)
);
 
//
// Instantiation of line FIFO block
//
ssvga_fifo ssvga_fifo(
.clk(wb_clk_i),
.crt_clk(crt_clk_i),
.rst(wb_rst_i),
.wr_en(fifo_wr_en),
.rd_en(fifo_rd_en),
.dat_i(fifo_in),
.dat_o(fifo_out),
.full(fifo_full),
.empty(fifo_empty),
.ssvga_en(ssvga_en)
);
 
//
// Instantiation of 256x16 Palette block
//
RAMB4_S16_S16 ssvga_pallete
(
.ADDRA(wbs_adr_i[9:2]),
.DIA(wbs_dat_i[15:0]),
.ENA(1'b1),
.RSTA(wb_rst_i),
.CLKA(wb_clk_i),
.WEA(pal_wr_en),
.DOA(wbs_pal_data),
.ADDRB(fifo_out),
.DIB(16'h0000),
.ENB(1'b1),
.RSTB(wb_rst_i),
.CLKB(wb_clk_i),
.WEB(1'b0),
.DOB(pal_pix_dat)
) ;
 
/*generic_spram_256x16 ssvga_palette(
// Generic synchronous single-port RAM interface
.clk(wb_clk_i),
.rst(wb_rst_i),
.ce(1'b1),
.we(pal_wr_en),
.oe(1'b1),
.addr(pal_indx),
.di(wbs_dat_i[15:0]),
.do(pad_rgb_o)
);
*/
//
// Instantiation of CRT controller block
//
ssvga_crtc ssvga_crtc(
.crt_clk(crt_clk_i),
.rst(wb_rst_i),
.hsync(pad_hsync_o),
.vsync(pad_vsync_o),
.hblank(crtc_hblank),
.vblank(crtc_vblank)
);
 
endmodule
/verilog/ssvga_fifo.v
0,0 → 1,239
//////////////////////////////////////////////////////////////////////
//// ////
//// Simple Small VGA IP Core ////
//// ////
//// This file is part of the Simple Small VGA project ////
//// ////
//// ////
//// Description ////
//// 512 entry FIFO for storing line video data. It uses one ////
//// clock for reading and writing. ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module ssvga_fifo(
clk, crt_clk, rst, dat_i, wr_en, rd_en,
dat_o, full, empty, ssvga_en
);
 
//
// I/O ports
//
input clk; // Clock
input crt_clk; // Clock for monitor
input rst; // Reset
input [31:0] dat_i; // Input data
input wr_en; // Write enable
input rd_en; // Read enable
output [7:0] dat_o; // Output data
output full; // Full flag
output empty; // Empty flag
input ssvga_en ; // vga enable
 
//
// Internal wires and regs
//
reg [7:0] wr_ptr; // Write pointer
reg [7:0] wr_ptr_plus1; // Write pointer
reg [9:0] rd_ptr; // Read pointer
reg [9:0] rd_ptr_plus1; // Read pointer plus1
wire rd_en_int; // FIFO internal read enable
 
wire [9:0] gray_rd_ptr; // gray code of read pointer
wire [9:0] gray_wr_ptr; // gray code of write pointer
wire [7:0] gray_wr_ptr_plus1;// gray code of write + 1 pointer
 
reg [9:0] gray_read_ptr; // sinchronized gray read pointer on clk clock
wire [9:0] sync_gray_rd_ptr; // intermediate sinc. of gray read pointer
 
reg rd_ssvga_en; // sinchronized ssvga enable on crt_clk clock
wire sync_ssvga_en; // intermediate sinc. of ssvga enable signal
 
//
// Write pointer + 1
//
 
always @(posedge clk or posedge rst)
if (rst)
wr_ptr_plus1 <= #1 8'b0000_0001 ;
else if (~ssvga_en)
wr_ptr_plus1 <= #1 8'b0000_0001 ;
else if (wr_en)
wr_ptr_plus1 <= #1 wr_ptr_plus1 + 1;
 
//
// Write pointer
//
always @(posedge clk or posedge rst)
if (rst)
wr_ptr <= #1 8'b0000_0000;
else if (~ssvga_en)
wr_ptr <= #1 8'b0000_0000;
else if (wr_en)
wr_ptr <= #1 wr_ptr_plus1 ;
 
//
// Read pointer
//
always @(posedge crt_clk or posedge rst)
if (rst)
rd_ptr <= #1 10'b00_0000_0000;
else if (~rd_ssvga_en)
rd_ptr <= #1 10'b00_0000_0000;
else if (rd_en_int)
rd_ptr <= #1 rd_ptr_plus1 ;
 
always @(posedge crt_clk or posedge rst)
if (rst)
rd_ptr_plus1 <= #1 10'b00_0000_0001;
else if (~rd_ssvga_en)
rd_ptr_plus1 <= #1 10'b00_0000_0001;
else if (rd_en_int)
rd_ptr_plus1 <= #1 rd_ptr_plus1 + 1 ;
 
//
// Empty is asserted when both pointers match
//
//assign empty = ( rd_ptr == {wr_ptr, 2'b00} ) ;
assign empty = ( gray_wr_ptr == gray_read_ptr ) ;
 
//
// Full is asserted when both pointers match
// and wr_ptr did increment in previous clock cycle
//
//assign full = ( wr_ptr_plus1 == rd_ptr[9:2] ) ;
assign full = ( gray_wr_ptr_plus1 == gray_read_ptr[9:2] ) ;
 
wire valid_pix = 1'b1 ;
 
//
// Read enable for FIFO
//
assign rd_en_int = rd_en & !empty & valid_pix;
 
wire [8:0] ram_pix_address = rd_en_int ? {rd_ptr_plus1[9:2], rd_ptr_plus1[0]} : {rd_ptr[9:2], rd_ptr[0]} ;
 
wire [7:0] dat_o_low ;
wire [7:0] dat_o_high ;
 
assign dat_o = rd_ptr[1] ? dat_o_high : dat_o_low ;
 
//#############################################################################
// binary to gray converters for counter of different clock domain comparison
assign gray_rd_ptr = (rd_ptr >> 1) ^ rd_ptr ;
assign gray_wr_ptr = ({1'b0, wr_ptr, 1'b0}) ^ ({wr_ptr, 2'b00}) ;
assign gray_wr_ptr_plus1 = (wr_ptr_plus1 >> 1) ^ wr_ptr_plus1 ;
 
//#############################################################################
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
synchronizer_flop #(10) read_ptr_sync
(
.data_in (gray_rd_ptr),
.clk_out (clk),
.sync_data_out (sync_gray_rd_ptr),
.async_reset (rst)
) ;
always@(posedge clk or posedge rst)
begin
if (rst)
gray_read_ptr <= #1 10'b0 ;
else
gray_read_ptr <= #1 sync_gray_rd_ptr ;
end
 
//##############################################################################
// interemediate stage ssvga_en synchronization flip - flop - this one is prone to metastability
synchronizer_flop ssvga_enable_sync
(
.data_in (ssvga_en),
.clk_out (crt_clk),
.sync_data_out (sync_ssvga_en),
.async_reset (rst)
) ;
// crt side ssvga enable flip flop - gets a value from intermediate stage sync flip flop
always@(posedge crt_clk or posedge rst)
begin
if (rst)
rd_ssvga_en <= #1 1'b0 ;
else
rd_ssvga_en <= #1 sync_ssvga_en ;
end
 
 
RAMB4_S8_S16 ramb4_s8_0(
.CLKA(crt_clk),
.RSTA(rst),
.ADDRA(ram_pix_address),
.DIA(8'h00),
.ENA(1'b1),
.WEA(1'b0),
.DOA(dat_o_low),
 
.CLKB(clk),
.RSTB(rst),
.ADDRB(wr_ptr),
.DIB(dat_i[15:0]),
.ENB(1'b1),
.WEB(wr_en),
.DOB()
);
 
RAMB4_S8_S16 ramb4_s8_1(
.CLKA(crt_clk),
.RSTA(rst),
.ADDRA(ram_pix_address),
.DIA(8'h00),
.ENA(1'b1),
.WEA(1'b0),
.DOA(dat_o_high),
 
.CLKB(clk),
.RSTB(rst),
.ADDRB(wr_ptr),
.DIB(dat_i[31:16]),
.ENB(1'b1),
.WEB(wr_en),
.DOB()
);
 
endmodule
/verilog/ssvga_wbm_if.v
0,0 → 1,184
//////////////////////////////////////////////////////////////////////
//// ////
//// Simple Small VGA IP Core ////
//// ////
//// This file is part of the Simple Small VGA project ////
//// ////
//// ////
//// Description ////
//// LITTLE-ENDIAN WISHBONE master interface. ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
`include "ssvga_defines.v"
// synopsys translate_on
 
module ssvga_wbm_if(
// Clock and reset
wb_clk_i, wb_rst_i,
// WISHBONE Master I/F
wbm_cyc_o, wbm_stb_o, wbm_sel_o, wbm_we_o,
wbm_adr_o, wbm_dat_o, wbm_cab_o,
wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
 
// Other signals
ssvga_en, fifo_full,
fifo_wr_en, fifo_dat,
pix_start_addr, resync
);
 
//
// I/O ports
//
 
//
// Clock and reset
//
input wb_clk_i; // Pixel Clock
input wb_rst_i; // Reset
 
//
// WISHBONE Master I/F
//
output wbm_cyc_o;
output wbm_stb_o;
output [3:0] wbm_sel_o;
output wbm_we_o;
output [31:0] wbm_adr_o;
output [31:0] wbm_dat_o;
output wbm_cab_o;
input [31:0] wbm_dat_i;
input wbm_ack_i;
input wbm_err_i;
input wbm_rty_i;
 
//
// Other signals
//
input ssvga_en; // Global enable
input fifo_full; // FIFO is full
output fifo_wr_en; // FIFO write enable
output [31:0] fifo_dat; // FIFO data
input [31:2] pix_start_addr ;
input resync ; // when pixel buffer underrun occures, master must resynchronize operation to start of screen
 
//
// Internal regs and wires
//
reg [`SSVGA_VMCW-1:0] vmaddr_r; // Video memory address counter
//reg [31:0] shift_r; // Shift register
//reg [1:0] shift_empty_r; // Shift register empty flags
 
// frame finished indicator - whenever video memory address shows 640x480 pixels read
reg frame_read ;
wire frame_read_in = ( vmaddr_r == `SSVGA_VMCW'h0_00_00 ) & wbm_ack_i & wbm_stb_o || ~ssvga_en || resync ;
 
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
frame_read <= #1 1'b0 ;
else
frame_read <= #1 frame_read_in ;
end
 
//
// Video memory address generation
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
vmaddr_r <= #1 ((`PIXEL_NUM/4)-1) ;
else if (frame_read)
vmaddr_r <= #1 ((`PIXEL_NUM/4)-1);
else if (wbm_ack_i & wbm_stb_o)
vmaddr_r <= #1 vmaddr_r - 1;
 
reg [31:2] wbm_adr ;
always@(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
wbm_adr <= #1 30'h0000_0000 ;
else if (frame_read)
wbm_adr <= #1 pix_start_addr ;
else if (wbm_ack_i & wbm_stb_o)
wbm_adr <= #1 wbm_adr + 1 ;
end
 
//
// Shift register
//
/*always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
shift_r <= #1 32'h0000_0000;
else if (wbm_ack_i & wbm_cyc_o)
shift_r <= #1 wbm_dat_i;
else if (!fifo_full)
shift_r <= #1 {16'h00, shift_r[31:16]};
 
//
// Shift register empty flags
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
shift_empty_r <= #1 2'b11 ;
else if (wbm_ack_i & wbm_cyc_o)
shift_empty_r <= #1 2'b00;
else if (!fifo_full)
shift_empty_r <= #1 {1'b1, shift_empty_r[1]};
*/
//
// Generate WISHBONE output signals
//
assign wbm_cyc_o = ssvga_en & !frame_read ;
assign wbm_stb_o = wbm_cyc_o & !fifo_full;
assign wbm_sel_o = 4'b1111;
assign wbm_we_o = 1'b0;
assign wbm_adr_o = {wbm_adr, 2'b00};
assign wbm_dat_o = 32'h0000_0000;
assign wbm_cab_o = 1'b1;
 
//
// Generate other signals
//
assign fifo_wr_en = wbm_ack_i & wbm_stb_o ;
assign fifo_dat = wbm_dat_i ;
 
endmodule
/verilog/timescale.v
0,0 → 1,184
`timescale 1ns/10ps

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