URL
https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk
Subversion Repositories pcie_ds_dma
Compare Revisions
- This comparison shows the changes necessary to convert path
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/components
- from Rev 32 to Rev 38
- ↔ Reverse comparison
Rev 32 → Rev 38
/pcie_core/pcie_core64_wishbone.vhd
167,9 → 167,12
------------------------------------------------------------------------------- |
-- |
-- Declare Global SYS_CON stuff: |
signal s_core_clk_out : std_logic; |
signal s_reset_out : std_logic; |
signal s_dcm_rst_out : std_logic; |
signal clk : std_logic; |
signal reset : std_logic; |
signal dcm_rst : std_logic; |
signal reset_p : std_logic; |
signal reset_p_z1 : std_logic; |
signal reset_p_z2 : std_logic; |
------------------------------------------------------------------------------- |
begin |
------------------------------------------------------------------------------- |
200,12 → 203,12
pcie_link_up => pcie_link_up, |
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clk_out => s_core_clk_out, -- S6 PCIE x1 module clock output |
reset_out => s_reset_out, -- |
dcm_rstp => s_dcm_rst_out, -- S6 PCIE x1 module INV trn_reset_n_c |
clk_out => clk, -- S6 PCIE x1 module clock output |
reset_out => reset, -- |
dcm_rstp => dcm_rst, -- S6 PCIE x1 module INV trn_reset_n_c |
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---- BAR1 (PB bus) ---- |
aclk => s_core_clk_out, -- !!! same clock as clk_out |
aclk => clk, -- !!! same clock as clk_out |
aclk_lock => '1', -- |
pb_master => pb_master, -- |
pb_slave => pb_slave, -- |
239,8 → 242,8
port map |
( |
---- Global ---- |
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---- HOST ---- |
252,7 → 255,13
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); |
); |
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reset_p <= (not reset) or (not brd_mode(3)); |
reset_p_z1 <= reset_p after 1 ns when rising_edge( clk ); |
reset_p_z2 <= reset_p_z1 after 1 ns when rising_edge( clk ); |
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------------------------------------------------------------------------------- |
-- |
-- Instantiate PB BUS <-> WB BUS translator module: |
260,8 → 269,8
PW_WB : core64_pb_wishbone |
port map |
( |
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---- BAR1 ---- |
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289,8 → 298,17
-- |
-- Module Output route: |
-- |
o_wb_clk <= s_core_clk_out; -- route from PW_WB wrk clock |
o_wb_clk <= clk; -- route from PW_WB wrk clock |
-- |
o_wb_rst <= s_dcm_rst_out; -- convert to POSITIVE LOGIC |
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pr_o_wb_rst: process( reset_p, clk ) begin |
if( reset_p='1' ) then |
o_wb_rst <= '1' after 1 ns; |
elsif( rising_edge( clk ) ) then |
o_wb_rst <= reset_p_z2 after 1 ns; |
end if; |
end process; |
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------------------------------------------------------------------------------- |
end pcie_core64_wishbone; |