OpenCores
URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /pcie_ds_dma/trunk/core/ds_dma64/pcie_src/components
    from Rev 42 to Rev 46
    Reverse comparison

Rev 42 → Rev 46

/pcie_core/pcie_core64_m5.vhd
5,7 → 5,7
-- Company : Instrumental Systems
-- E-mail : dsmv@insys.ru
--
-- Version : 1.0
-- Version : 1.1
--
-------------------------------------------------------------------------------
--
17,6 → 17,11
--
-------------------------------------------------------------------------------
--
-- Version 1.1 17.02.2014
 
--
-------------------------------------------------------------------------------
--
-- Version 1.0 15.08.2011
 
--
30,7 → 35,8
 
 
component pcie_core64_m5 is
generic (
generic (
CORE_NAME : in string:="pcie_core64_m4";
 
 
 
94,6 → 100,7
 
entity pcie_core64_m5 is
generic (
CORE_NAME : in string:="pcie_core64_m4";
 
 
 
145,6 → 152,61
 
architecture pcie_core64_m5 of pcie_core64_m5 is
 
component pcie_core64_m10 is
generic (
 
 
 
 
);
port (
---- PCI-Express ----
txp : out std_logic_vector( 3 downto 0 );
txn : out std_logic_vector( 3 downto 0 );
rxp : in std_logic_vector( 3 downto 0 );
rxn : in std_logic_vector( 3 downto 0 );
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
---- BAR1 ----
 
 
 
 
);
end component;
 
 
 
 
169,6 → 231,7
 
begin
gen_m4: if( CORE_NAME="pcie_core64_m4" ) generate
core: pcie_core64_m4
generic map(
218,8 → 281,66
bp_irq => bp_irq
);
);
end generate;
 
gen_m10: if( CORE_NAME="pcie_core64_m10" ) generate
core: pcie_core64_m10
generic map(
 
 
 
)
port map(
---- PCI-Express ----
txp => txp,
txn => txn,
rxp => rxp,
rxn => rxn,
mgt250 => mgt250,
perst => perst,
px => px,
pcie_lstatus => pcie_lstatus,
pcie_link_up => pcie_link_up,
 
clk_out => clk250,
reset_out => reset,
dcm_rstp => dcm_rstp,
 
---- BAR1 ----
aclk => clk,
aclk_lock => clk_lock,
pb_master => pb_master,
pb_slave => pb_slave,
 
 
bp_host_data => bp_host_data,
bp_data => bp_data,
bp_adr => bp_adr,
bp_we => bp_we,
bp_rd => bp_rd,
bp_sel => bp_sel,
bp_reg_we => bp_reg_we,
bp_reg_rd => bp_reg_rd,
bp_irq => bp_irq
);
end generate;
 
reset_out <= reset;
clk250_out <= clk250;
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.