URL
https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk
Subversion Repositories pcie_ds_dma
Compare Revisions
- This comparison shows the changes necessary to convert path
/pcie_ds_dma/trunk/core/ds_dma64/pcie_src/pcie_core64_m1
- from Rev 11 to Rev 18
- ↔ Reverse comparison
Rev 11 → Rev 18
/pcie_ctrl/core64_pb_disp.vhd
59,7 → 59,9
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library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
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library unisim; |
use unisim.vcomponents.all; |
132,6 → 134,9
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signal reg_complete : std_logic; |
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signal timeout_cnt : std_logic_vector( 12 downto 0 ); |
signal slave_timeout : std_logic; |
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attribute tig : string; |
attribute tig of master_adr : signal is ""; |
attribute tig of dmar : signal is ""; |
185,7 → 190,8
fifo_allow_wr <= '0' after 1 ns; |
reg_stb1 <= '0' after 1 ns; |
fifo_data_en <= '0' after 1 ns; |
ext_fifo_disp_back.complete <= '0' after 1 ns; |
ext_fifo_disp_back.complete <= '0' after 1 ns; |
timeout_cnt <= (others=>'0') after 1 ns; |
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if( reg_req_wr_z='1' or reg_req_rd_z='1' ) then |
stp <= sr1 after 1 ns; |
214,9 → 220,10
-- else |
-- stp <= sr5 after 1 ns; |
-- end if; |
-- end if; |
-- end if; |
timeout_cnt <= timeout_cnt + 1 after 1 ns; |
reg_data_we_set <= pb_slave.stb1 after 1 ns; |
if( pb_slave.complete='1' ) then |
if( pb_slave.complete='1' or slave_timeout='1') then |
stp <= sr5 after 1 ns; |
end if; |
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249,7 → 256,8
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fifo_allow_wr <= ext_fifo_disp.request_wr and pb_slave.ready after 1 ns; |
fifo_data_en <= '1' after 1 ns; |
if( pb_slave.complete='1' ) then |
timeout_cnt <= timeout_cnt + 1 after 1 ns; |
if( pb_slave.complete='1' or slave_timeout='1' ) then |
ext_fifo_disp_back.complete <= '1' after 1 ns; |
stp <= sf3 after 1 ns; |
end if; |
269,8 → 277,10
end if; |
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end if; |
end process; |
end process; |
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slave_timeout <= timeout_cnt(12) after 1 ns when rising_edge( clk ); |
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ext_fifo_disp_back.allow_wr <= fifo_allow_wr; |
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pb_slave_stb1_z <= pb_slave.stb1 after 1 ns when rising_edge( aclk ); |