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/ac701_a200t_core.vhd
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------------------------------------------------------------------------------- |
-- |
-- Title : ac701_a200t_core |
-- Author : Dmitry Smekhov |
-- Company : Instrumental Systems |
-- E-mail : dsmv@insys.ru |
-- |
-- Version : 1.0 |
-- |
------------------------------------------------------------------------------- |
-- |
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-- |
------------------------------------------------------------------------------- |
-- |
-- Version 1.0 17.02.2014 |
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-- |
------------------------------------------------------------------------------- |
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library ieee; |
use ieee.std_logic_1164.all; |
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package ac701_a200t_core_pkg is |
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component ac701_a200t_core is |
generic ( |
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); |
port( |
---- PCI-Express ---- |
pci_exp_txp : out std_logic_vector(3 downto 0); |
pci_exp_txn : out std_logic_vector(3 downto 0); |
pci_exp_rxp : in std_logic_vector(3 downto 0); |
pci_exp_rxn : in std_logic_vector(3 downto 0); |
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sys_clk_p : in std_logic; |
sys_clk_n : in std_logic; |
sys_reset_n : in std_logic; |
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gpio_led0 : out std_logic; |
gpio_led1 : out std_logic; |
gpio_led2 : out std_logic; |
gpio_led3 : out std_logic; |
gpio_led4 : out std_logic |
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); |
end component; |
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end package; |
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library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
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library unisim; |
use unisim.vcomponents.all; |
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use work.adm2_pkg.all; |
use work.cl_ac701_pkg.all; |
use work.trd_main_v8_pkg.all; |
use work.trd_pio_std_v4_pkg.all; |
use work.trd_admdio64_out_v4_pkg.all; |
use work.trd_admdio64_in_v6_pkg.all; |
use work.trd_test_ctrl_m1_pkg.all; |
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entity ac701_a200t_core is |
generic ( |
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); |
port( |
---- PCI-Express ---- |
pci_exp_txp : out std_logic_vector(3 downto 0); |
pci_exp_txn : out std_logic_vector(3 downto 0); |
pci_exp_rxp : in std_logic_vector(3 downto 0); |
pci_exp_rxn : in std_logic_vector(3 downto 0); |
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sys_clk_p : in std_logic; |
sys_clk_n : in std_logic; |
sys_reset_n : in std_logic; |
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gpio_led0 : out std_logic; |
gpio_led1 : out std_logic; |
gpio_led2 : out std_logic; |
gpio_led3 : out std_logic; |
gpio_led4 : out std_logic |
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); |
end ac701_a200t_core; |
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architecture ac701_a200t_core of ac701_a200t_core is |
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signal clk : std_logic; |
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signal reset_main : std_logic; |
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signal reset : std_logic; |
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signal trd_host_adr : std_logic_vector( 31 downto 0 ):=(others=>'0'); |
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signal trd_host_data : std_logic_array_16x64; |
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signal trd_host_cmd_data : std_logic_array_16x16; |
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signal trd_host_cmd : std_logic_array_16xbl_cmd; |
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signal trd_data : std_logic_array_16x64:=(others=>(others=>'0')); |
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signal trd_cmd_data : std_logic_array_16x16:=(others=>(others=>'1')); |
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signal trd_drq : std_logic_array_16xbl_drq:=(others=>(others=>'0')); |
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signal trd_irq : std_logic_array_16xbl_irq:=(others=>'0'); |
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signal trd_reset_fifo : std_logic_array_16xbl_reset_fifo:=(others=>'0'); |
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signal trd_main_drq : std_logic_array_16xbl_drq:=(others=>(others=>'0')); |
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signal trd_main_irq : std_logic_array_16xbl_irq:=(others=>'0'); |
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signal trd_main_sel_drq : std_logic_array_16x6:=(others=>(others=>'0')); |
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signal test_mode : std_logic; |
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signal trd_trd_cmd : std_logic_array_16xbl_cmd; |
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signal trd_flag_rd : std_logic_array_16xbl_fifo_flag; |
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signal di_mode1 : std_logic_vector( 15 downto 0 ); |
signal di_data : std_logic_vector( 63 downto 0 ); |
signal di_data_we : std_logic; |
signal di_flag_wr : bl_fifo_flag; |
signal di_start : std_logic; |
signal di_fifo_rst : std_logic; |
signal di_clk : std_logic; |
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signal do_mode1 : std_logic_vector( 15 downto 0 ); |
signal do_data : std_logic_vector( 63 downto 0 ); |
signal do_data_cs : std_logic; |
signal do_flag_rd : bl_fifo_flag; |
signal do_start : std_logic; |
signal do_fifo_rst : std_logic; |
signal do_clk : std_logic; |
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signal clk200 : std_logic; |
signal freq0 : std_logic; |
signal freq1 : std_logic; |
signal freq2 : std_logic; |
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signal led_h1 : std_logic; |
signal led_h2 : std_logic; |
signal led_h3 : std_logic; |
signal led_h4 : std_logic; |
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signal led_h1_p : std_logic; |
signal led_h2_p : std_logic; |
signal led_h3_p : std_logic; |
signal led_h4_p : std_logic; |
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signal tp1 : std_logic; |
signal tp2 : std_logic; |
signal tp3 : std_logic; |
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signal px : std_logic_vector( 3 downto 1 ); |
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signal clk30k : std_logic; |
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constant rom_main: bl_trd_rom:= |
( |
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31 downto 21 => x"0000" ); |
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constant rom_dio_in: bl_trd_rom:= |
( |
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constant rom_dio_out: bl_trd_rom:= |
( |
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constant rom_test_ctrl: bl_trd_rom:= |
( |
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constant trd_rom : std_logic_array_16xbl_trd_rom := |
( |
0 => rom_main, |
1 => rom_test_ctrl, |
2 => rom_empty, |
3 => rom_empty, |
4 => rom_empty, |
5 => rom_empty, |
6 => rom_dio_in, |
7 => rom_dio_out, |
others=> rom_empty ); |
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begin |
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xled0: obuf_s_16 port map( gpio_led0, '1' ); |
xled1: obuf_s_16 port map( gpio_led1, led_h1_p ); |
xled2: obuf_s_16 port map( gpio_led2, led_h2_p ); |
xled3: obuf_s_16 port map( gpio_led3, led_h3_p ); |
xled4: obuf_s_16 port map( gpio_led4, led_h4_p ); |
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led_h1_p <= not led_h1; |
led_h2_p <= not led_h2; |
led_h3_p <= not led_h3; |
led_h4_p <= not led_h4; |
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tp1 <= not tp1 when rising_edge( clk ); |
tp2 <= px(2); |
tp3 <= clk30k; |
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--btp1: obuf_f_16 port map( btp(1), tp1 ); |
--btp2: obuf_f_16 port map( btp(2), tp2 ); |
--btp3: obuf_f_16 port map( btp(3), tp3 ); |
-- |
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amb: cl_ac701 |
generic map( |
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trd_rom => trd_rom, |
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trd_in => "0000000001000001", |
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trd_st => "0000000011000011", |
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) |
port map( |
---- PCI-Express ---- |
txp => pci_exp_txp, |
txn => pci_exp_txn, |
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rxp => pci_exp_rxp, |
rxn => pci_exp_rxn, |
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mgt100_n => sys_clk_n, |
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p => px, |
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trd_host_adr => trd_host_adr( 15 downto 0 ), |
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trd_host_data => trd_host_data, |
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trd_host_cmd_data=>trd_host_cmd_data, |
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trd_host_cmd => trd_host_cmd, |
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trd_data => trd_data, |
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trd_cmd_data => trd_cmd_data, |
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trd_drq => trd_drq, |
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trd_main_drq => trd_main_drq, |
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trd_main_sel_drq=> trd_main_sel_drq, |
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trd_reset_fifo => trd_reset_fifo, |
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trd_main_irq => trd_main_irq |
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); |
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main: trd_main_v8 |
port map |
( |
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-- GLOBAL |
reset => reset_main, |
clk => clk, |
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-- T0 |
adr_in => trd_host_adr( 6 downto 0 ), |
data_in => trd_host_data(0), |
cmd_data_in => trd_host_cmd_data(0), |
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cmd => trd_host_cmd(0), |
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data_out => trd_data(0), |
cmd_data_out => trd_cmd_data(0), |
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test_mode => test_mode, |
test_mode_init => '1', |
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b1_irq => trd_irq(1), |
b2_irq => trd_irq(2), |
b3_irq => trd_irq(3), |
b4_irq => trd_irq(4), |
b5_irq => trd_irq(5), |
b6_irq => trd_irq(6), |
b7_irq => trd_irq(7), |
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b1_drq => trd_drq(1), |
b2_drq => trd_drq(2), |
b3_drq => trd_drq(3), |
b4_drq => trd_drq(4), |
b5_drq => trd_drq(5), |
b6_drq => trd_drq(6), |
b7_drq => trd_drq(7), |
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int1 => trd_main_irq(1), |
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drq0 => trd_main_drq(0), |
drq1 => trd_main_drq(1), |
drq2 => trd_main_drq(2), |
drq3 => trd_main_drq(3), |
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reset_out => reset, |
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fifo_rst_out => trd_reset_fifo(0), |
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b_clk => (others=>'0'), |
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b_start => (others=>'0'), |
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-- SYNX |
sn_rdy0 => '0', |
sn_rdy1 => '0', |
sn_start_en => '0', |
sn_sync0 => '0' |
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); |
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dio_in: trd_admdio64_in_v6 |
port map( |
-- GLOBAL |
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cmd_data_in => trd_host_cmd_data(6), |
cmd => trd_host_cmd(6), |
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data_out2 => trd_data(6), |
cmd_data_out2 => trd_cmd_data(6), |
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); |
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trd_reset_fifo(6) <= di_fifo_rst; |
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dio_out: trd_admdio64_out_v4 |
port map( |
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-- GLOBAL |
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data_in => trd_host_data(7), |
cmd_data_in => trd_host_cmd_data(7), |
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cmd => trd_host_cmd(7), |
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cmd_data_out2 => trd_cmd_data(7), |
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); |
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trd_reset_fifo(7) <= do_fifo_rst; |
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freq0 <= clk; |
freq1 <= '0'; |
freq2 <= '0'; |
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test_ctrl: trd_test_ctrl_m1 |
generic map( |
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) |
port map( |
-- GLOBAL |
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cmd_data_in => trd_host_cmd_data(1), |
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cmd => trd_host_cmd(1), |
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cmd_data_out2 => trd_cmd_data(1), |
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---- DIO_IN ---- |
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---- DIO_OUT ---- |
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); |
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end ac701_a200t_core; |