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URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

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Rev 15 → Rev 16

/testbench/test_pkg.vhd
0,0 → 1,1910
---------------------------------------------------------------------------------------------------
--
-- Title : test_pkg.vhd
-- Author : Dmitry Smekhov
-- Company : Instrumental System
--
-- Version : 1.0
--
---------------------------------------------------------------------------------------------------
--
 
--
---------------------------------------------------------------------------------------------------
--
-- Version 1.1 (25.10.2011) Kuzmi4
-- Description: add couple of simple tests for test WB stuff, let "test_num_1" unchanged.
--
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
library work;
use work.cmd_sim_pkg.all;
use work.block_pkg.all;
use work.wb_block_pkg.all;
 
package test_pkg is
--! Initialising
procedure test_init(
 
);
--! Finished
procedure test_close;
--! Start DMA with incorrect descriptor
procedure test_dsc_incorrect (
 
 
);
 
--! Start DMA for one block 4 kB
procedure test_read_4kb (
 
 
);
 
--! Read block_test_check 8 kB
procedure test_adm_read_8kb (
 
 
);
 
 
--procedure test_block_main (
 
 
-- );
--
 
--procedure test_adm_read_16kb (
 
 
-- );
--
 
procedure test_adm_write_16kb (
 
 
);
---------------------------------------------------------------------------------------------------
--
--
--
procedure test_num_1(
 
 
);
procedure test_num_2(
 
 
);
-- ==> TEST_CHECK.WB_CFG_SLAVE
procedure test_wb_1(
 
 
);
-- ==> TEST_GEN.WB_CFG_SLAVE
procedure test_wb_2(
 
 
);
end package test_pkg;
---------------------------------------------------------------------------------------------------
package body test_pkg is
FILE log: text;
shared variable cnt_ok, cnt_error: integer;
-- Initialising
procedure test_init(
fname: in string
) is
begin
file_open( log, fname, WRITE_MODE );
cnt_ok:=0;
cnt_error:=0;
end test_init;
--! Finished
procedure test_close is
variable str : LINE; -- pointer to string
begin
std.textio.write( str, string'(" " ));
writeline( log, str );
writeline( log, str );
write( str, string'("check completed" ));
writeline( log, str );
write( str, string'("the number of successful tests: " ));
write( str, cnt_ok );
writeline( log, str );
write( str, string'("the number of false test: " ));
write( str, cnt_error );
writeline( log, str );
file_close( log );
if( cnt_ok>0 and cnt_error=0 ) then
write( str, string'("TEST finished successfully") );
writeline( output, str );
else
write( str, string'("TEST finished with ERR") );
writeline( output, str );
end if;
end test_close;
--! Start DMA with incorrect descriptor
procedure test_dsc_incorrect (
 
 
)
is
 
variable adr : std_logic_vector( 31 downto 0 );
variable data : std_logic_vector( 31 downto 0 );
variable str : line;
begin
write( str, string'("TEST_DSC_INCORRECT" ));
writeline( log, str );
---- Init block of descriptor ---
for ii in 0 to 127 loop
adr:= x"00100000";
adr:=adr + ii*4;
int_mem_write( cmd, ret, adr, x"00000000" );
end loop;
int_mem_write( cmd, ret, x"00100000", x"03020100" );
int_mem_write( cmd, ret, x"001001FC", x"FF00AA00" );
---- DMA program ----
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
block_write( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
wait for 20 us;
block_read( cmd, ret, 4, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data( 15 downto 0 )=x"A021" ) then
write( str, string'(" - Ok" ));
cnt_ok := cnt_ok + 1;
else
write( str, string'(" - Error" ));
cnt_error := cnt_error + 1;
end if;
writeline( log, str );
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
end test_dsc_incorrect;
 
--! Start DMA for one block 4 kB
procedure test_read_4kb (
 
 
)
is
 
variable adr : std_logic_vector( 31 downto 0 );
variable data : std_logic_vector( 31 downto 0 );
variable str : line;
 
variable error : integer:=0;
variable dma_complete : integer;
 
begin
write( str, string'("TEST_READ_4KB" ));
writeline( log, str );
---- Init block of descriptor ---
for ii in 0 to 127 loop
adr:= x"00100000";
adr:=adr + ii*4;
int_mem_write( cmd, ret, adr, x"00000000" );
end loop;
int_mem_write( cmd, ret, x"00100000", x"00008000" );
int_mem_write( cmd, ret, x"00100004", x"00000100" );
 
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
int_mem_write( cmd, ret, x"001001FC", x"762C4953" );
--wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- read block id
write( str, string'("BLOCK TEST_GEN ID: " ));
hwrite( str, data );
writeline( log, str );
wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
 
---- DMA program ----
block_write( cmd, ret, 4, 8, x"00000025" ); -- DMA_MODE - without request
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
block_write( cmd, ret, 4, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
 
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
 
wait for 1 us;
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
--wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A2" );
wait for 20 us;
block_read( cmd, ret, 4, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data( 8 )='1' ) then
write( str, string'(" - descriptor is correct" ));
else
write( str, string'(" - descriptor is incorrect" ));
error := error + 1;
end if;
writeline( log, str );
if( error=0 ) then
---- Wait for DMA finished ----
dma_complete := 0;
for ii in 0 to 100 loop
block_read( cmd, ret, 4, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data(5)='1' ) then
write( str, string'(" - DMA finished " ));
dma_complete := 1;
end if;
writeline( log, str );
if( dma_complete=1 ) then
exit;
end if;
wait for 1 us;
end loop;
writeline( log, str );
if( dma_complete=0 ) then
write( str, string'("Error - DMA not finished" ));
writeline( log, str );
error:=error+1;
end if;
 
end if;
for ii in 0 to 3 loop
block_read( cmd, ret, 4, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
writeline( log, str );
wait for 500 ns;
end loop;
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
write( str, string'(" Read: " ));
writeline( log, str );
for ii in 0 to 15 loop
 
adr:= x"00800000";
adr:=adr + ii*4;
int_mem_read( cmd, ret, adr, data );
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
writeline( log, str );
end loop;
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
writeline( log, str );
if( error=0 ) then
write( str, string'("Test is correct" ));
cnt_ok := cnt_ok + 1;
else
write( str, string'("Test have ERRORS" ));
cnt_error := cnt_error + 1;
end if;
writeline( log, str );
writeline( log, str );
 
end test_read_4kb;
 
 
--! Read block_test_check 8 kB
procedure test_adm_read_8kb (
 
 
)
is
 
variable adr : std_logic_vector( 31 downto 0 );
variable data : std_logic_vector( 31 downto 0 );
variable str : line;
 
variable error : integer:=0;
variable dma_complete : integer;
 
begin
write( str, string'("TEST_ADM_READ_8KB" ));
writeline( log, str );
---- Init block of descriptor ---
for ii in 0 to 127 loop
adr:= x"00100000";
adr:=adr + ii*4;
int_mem_write( cmd, ret, adr, x"00000000" );
end loop;
--- Desctriptor 0 ---
int_mem_write( cmd, ret, x"00100000", x"00008000" );
int_mem_write( cmd, ret, x"00100004", x"00000111" ); -- jump to next descriptor
 
--- Desctriptor 1 ---
int_mem_write( cmd, ret, x"00100008", x"00008010" );
int_mem_write( cmd, ret, x"0010000C", x"00000110" ); -- stop
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
int_mem_write( cmd, ret, x"001001FC", x"D6644953" );
 
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
block_write( cmd, ret, 4, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000000" );
wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data ); -- read block id
write( str, string'("BLOCK TEST_GEN ID: " ));
hwrite( str, data );
writeline( log, str );
wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
 
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
wait for 20 us;
block_read( cmd, ret, 4, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data( 8 )='1' ) then
write( str, string'(" - descriptor is correct" ));
else
write( str, string'(" - descriptor is incorrect" ));
error := error + 1;
end if;
writeline( log, str );
if( error=0 ) then
 
dma_complete := 0;
for ii in 0 to 100 loop
block_read( cmd, ret, 4, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data(5)='1' ) then
write( str, string'(" - DMA finished " ));
dma_complete := 1;
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - reset EOT
end if;
writeline( log, str );
if( dma_complete=1 ) then
exit;
end if;
wait for 1 us;
end loop;
writeline( log, str );
if( dma_complete=0 ) then
write( str, string'("Error - DMA not finished " ));
writeline( log, str );
error:=error+1;
end if;
 
end if;
for ii in 0 to 3 loop
block_read( cmd, ret, 4, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
writeline( log, str );
wait for 500 ns;
end loop;
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
write( str, string'(" Block 0 - read: " ));
writeline( log, str );
for ii in 0 to 15 loop
 
adr:= x"00800000";
adr:=adr + ii*4;
int_mem_read( cmd, ret, adr, data );
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
writeline( log, str );
end loop;
 
writeline( log, str );
write( str, string'(" Block 1 - read: " ));
writeline( log, str );
for ii in 0 to 15 loop
 
adr:= x"00801000";
adr:=adr + ii*4;
int_mem_read( cmd, ret, adr, data );
write( str, ii ); write( str, string'(" " )); hwrite( str, data );
writeline( log, str );
end loop;
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
writeline( log, str );
if( error=0 ) then
write( str, string'(" Test is correct " ));
cnt_ok := cnt_ok + 1;
else
write( str, string'(" Test have ERRORS " ));
cnt_error := cnt_error + 1;
end if;
writeline( log, str );
writeline( log, str );
 
end test_adm_read_8kb;
--
--
 
--procedure test_block_main (
 
 
-- )
--is
--
--variable adr : std_logic_vector( 31 downto 0 );
--variable data : std_logic_vector( 31 downto 0 );
--variable str : line;
--
--variable error : integer:=0;
--variable dma_complete : integer;
--
--begin
--
-- write( str, string'("TEST_BLOCK_MAIN" ));
-- writeline( log, str );
--
-- block_read( cmd, ret, 4, 16#00#, data );
 
--
-- wait for 10 us;
--
 
---- writeline( log, str );
---- for ii in 0 to 5 loop
 
---- write( str, ii );
---- for jj in 0 to 7 loop
---- block_read( cmd, ret, ii, jj, data );
---- write( str, " " );
---- hwrite( str, data );
---- end loop;
---- writeline( log, str );
---- end loop;
----
----
---- writeline( log, str );
----
---- block_read( cmd, ret, 0, 16#10#, data );
---- write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
----
---- block_write( cmd, ret, 80, 16#08#, x"00000100" );
----
---- block_read( cmd, ret, 0, 16#10#, data );
---- write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
----
---- block_write( cmd, ret, 80, 16#08#, x"00000200" );
----
---- block_read( cmd, ret, 0, 16#10#, data );
---- write( str, "STATUS: " ); hwrite( str, data ); writeline( log, str );
----
----
---- writeline( log, str );
---- if( error=0 ) then
 
---- cnt_ok := cnt_ok + 1;
---- else
 
---- cnt_error := cnt_error + 1;
---- end if;
--
-- for ii in 0 to 127 loop
--
-- block_write( cmd, ret, 4, 16#08#, x"0000AA55" );
-- block_read( cmd, ret, 4, 8, data );
-- write( str, string'("READ: " )); hwrite( str, data( 15 downto 0 ) ); writeline( log, str );
-- if( data/=x"0000AA55" ) then
-- error:=error+1;
-- end if;
--
-- end loop;
--
--
--
--
-- writeline( log, str );
-- writeline( log, str );
--
--end test_block_main;
--
--
--
--
 
--procedure test_adm_read_16kb (
 
 
-- )
--is
--
--variable adr : std_logic_vector( 31 downto 0 );
--variable data : std_logic_vector( 31 downto 0 );
--variable str : line;
--
--variable error : integer:=0;
--variable dma_complete : integer;
--variable kk : integer;
--variable status : std_logic_vector( 15 downto 0 );
--
--begin
--
-- write( str, string'("TEST_ADM_READ_16KB" ));
-- writeline( log, str );
--
 
-- for ii in 0 to 256 loop
-- adr:= x"00100000";
-- adr:=adr + ii*4;
-- int_mem_write( cmd, ret, adr, x"00000000" );
-- end loop;
--
 
--
 
-- int_mem_write( cmd, ret, x"00100000", x"00008000" );
 
--
 
-- int_mem_write( cmd, ret, x"00100008", x"00008010" );
 
--
 
 
-- int_mem_write( cmd, ret, x"00100014", x"00000000" );
--
--
-- int_mem_write( cmd, ret, x"001001F8", x"00000000" );
-- int_mem_write( cmd, ret, x"001001FC", x"14644953" );
--
--
 
--
 
-- int_mem_write( cmd, ret, x"00100200", x"00008020" );
 
--
 
-- int_mem_write( cmd, ret, x"00100208", x"00008030" );
 
--
--
-- int_mem_write( cmd, ret, x"001003F8", x"00000000" );
-- int_mem_write( cmd, ret, x"001003FC", x"D67C4953" );
--
--
--
 
-- block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
--
-- block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
-- block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
-- block_write( cmd, ret, 4, 23, x"00019000" ); -- LOCAL_ADR
--
--
 
 
 
--
 
--
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
--
 
--
 
--
 
--
-- wait for 20 us;
--
-- block_read( cmd, ret, 4, 16, data ); -- STATUS
--
-- write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
-- if( data( 8 )='1' ) then
 
-- else
 
-- error := error + 1;
-- end if;
--
-- writeline( log, str );
--
-- if( error=0 ) then
--
-- kk:=0;
-- loop
--
-- trd_status( cmd, ret, 6, status );
-- write( str, string'("TRD_STATUS: " )); hwrite( str, status );
--
-- block_read( cmd, ret, 4, 16, data ); -- STATUS
-- write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
--
-- if( data(4)='1' ) then
 
 
-- kk:=kk+1;
-- if( kk=4 ) then
-- exit;
-- end if;
-- end if;
-- writeline( log, str );
--
-- wait for 500 ns;
--
--
-- end loop;
--
 
-- dma_complete := 0;
-- for ii in 0 to 100 loop
--
-- block_read( cmd, ret, 4, 16, data ); -- STATUS
-- write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
-- if( data(5)='1' ) then
 
-- dma_complete := 1;
--
 
--
-- end if;
-- writeline( log, str );
--
-- if( dma_complete=1 ) then
-- exit;
-- end if;
--
-- wait for 1 us;
--
-- end loop;
--
-- writeline( log, str );
--
-- if( dma_complete=0 ) then
 
-- writeline( log, str );
-- error:=error+1;
-- end if;
--
-- end if;
--
-- for ii in 0 to 3 loop
--
-- block_read( cmd, ret, 4, 16, data ); -- STATUS
-- write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
-- writeline( log, str );
-- wait for 500 ns;
--
-- end loop;
--
--
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
--
 
-- writeline( log, str );
--
-- for ii in 0 to 15 loop
--
-- adr:= x"00800000";
-- adr:=adr + ii*4;
-- int_mem_read( cmd, ret, adr, data );
--
-- write( str, ii ); write( str, string'(" " )); hwrite( str, data );
-- writeline( log, str );
--
-- end loop;
--
-- writeline( log, str );
--
 
-- writeline( log, str );
--
-- for ii in 0 to 15 loop
--
-- adr:= x"00801000";
-- adr:=adr + ii*4;
-- int_mem_read( cmd, ret, adr, data );
--
-- write( str, ii ); write( str, string'(" " )); hwrite( str, data );
-- writeline( log, str );
--
-- end loop;
--
 
-- writeline( log, str );
--
-- for ii in 0 to 15 loop
--
-- adr:= x"00802000";
-- adr:=adr + ii*4;
-- int_mem_read( cmd, ret, adr, data );
--
-- write( str, ii ); write( str, string'(" " )); hwrite( str, data );
-- writeline( log, str );
--
-- end loop;
--
--
 
-- writeline( log, str );
--
-- for ii in 0 to 15 loop
--
-- adr:= x"00803000";
-- adr:=adr + ii*4;
-- int_mem_read( cmd, ret, adr, data );
--
-- write( str, ii ); write( str, string'(" " )); hwrite( str, data );
-- writeline( log, str );
--
-- end loop;
--
---- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
---- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
---- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
--
--
-- writeline( log, str );
-- if( error=0 ) then
 
-- cnt_ok := cnt_ok + 1;
-- else
 
-- cnt_error := cnt_error + 1;
-- end if;
-- writeline( log, str );
-- writeline( log, str );
--
--end test_adm_read_16kb;
--
--
--
--
 
procedure test_adm_write_16kb (
 
 
)
is
 
variable adr : std_logic_vector( 31 downto 0 );
variable data : std_logic_vector( 31 downto 0 );
variable str : line;
 
variable error : integer:=0;
variable dma_complete : integer;
variable kk : integer;
variable status : std_logic_vector( 15 downto 0 );
 
variable data64 : std_logic_vector( 63 downto 0 );
variable data64n : std_logic_vector( 63 downto 0 );
 
begin
write( str, string'("TEST_ADM_WRITE_16KB" ));
writeline( log, str );
 
for ii in 0 to 256 loop
adr:= x"00100000";
adr:=adr + ii*4;
int_mem_write( cmd, ret, adr, x"00000000" );
end loop;
 
data64 :=x"0000000000000000";
data64n := not data64;
 
adr:= x"00800000";
data:=x"A5A50123";
int_mem_write( cmd, ret, adr, data );
adr:=adr + 4;
data:=x"00000000";
int_mem_write( cmd, ret, adr, data );
adr:=adr + 4;
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
adr:=adr + 4;
 
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
adr:=adr + 4;
 
data64:=data64 + 1;
data64n := not data64;
for ii in 0 to 254 loop
int_mem_write( cmd, ret, adr, data64( 31 downto 0 ) );
adr:=adr + 4;
int_mem_write( cmd, ret, adr, data64( 63 downto 32 ) );
adr:=adr + 4;
 
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
adr:=adr + 4;
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
adr:=adr + 4;
 
data64:=data64 + 1;
data64n := not data64;
end loop;
 
adr:= x"00801000";
data:=x"A5A50123";
int_mem_write( cmd, ret, adr, data );
adr:=adr + 4;
data:=x"00000001";
int_mem_write( cmd, ret, adr, data );
adr:=adr + 4;
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
adr:=adr + 4;
 
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
adr:=adr + 4;
 
data64:=data64 + 1;
data64n := not data64;
for ii in 0 to 254 loop
int_mem_write( cmd, ret, adr, data64( 31 downto 0 ) );
adr:=adr + 4;
int_mem_write( cmd, ret, adr, data64( 63 downto 32 ) );
adr:=adr + 4;
 
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
adr:=adr + 4;
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
adr:=adr + 4;
 
data64:=data64 + 1;
data64n := not data64;
end loop;
 
adr:= x"00802000";
data:=x"A5A50123";
int_mem_write( cmd, ret, adr, data );
adr:=adr + 4;
data:=x"00000002";
int_mem_write( cmd, ret, adr, data );
adr:=adr + 4;
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
adr:=adr + 4;
 
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
adr:=adr + 4;
 
data64:=data64 + 1;
data64n := not data64;
for ii in 0 to 254 loop
int_mem_write( cmd, ret, adr, data64( 31 downto 0 ) );
adr:=adr + 4;
int_mem_write( cmd, ret, adr, data64( 63 downto 32 ) );
adr:=adr + 4;
 
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
adr:=adr + 4;
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
adr:=adr + 4;
 
data64:=data64 + 1;
data64n := not data64;
end loop;
 
adr:= x"00803000";
data:=x"A5A50123";
int_mem_write( cmd, ret, adr, data );
adr:=adr + 4;
data:=x"00000003";
int_mem_write( cmd, ret, adr, data );
adr:=adr + 4;
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
adr:=adr + 4;
 
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
adr:=adr + 4;
 
data64:=data64 + 1;
data64n := not data64;
for ii in 0 to 254 loop
int_mem_write( cmd, ret, adr, data64( 31 downto 0 ) );
adr:=adr + 4;
int_mem_write( cmd, ret, adr, data64( 63 downto 32 ) );
adr:=adr + 4;
 
int_mem_write( cmd, ret, adr, data64n( 31 downto 0 ) );
adr:=adr + 4;
int_mem_write( cmd, ret, adr, data64n( 63 downto 32 ) );
adr:=adr + 4;
 
data64:=data64 + 1;
data64n := not data64;
end loop;
-- for ii in 0 to 256 loop
-- adr:= x"00802000";
-- adr:=adr + ii*4;
-- data:=x"00A20000";
-- data:=data + ii;
-- int_mem_write( cmd, ret, adr, data );
-- end loop;
--
-- for ii in 0 to 256 loop
-- adr:= x"00803000";
-- adr:=adr + ii*4;
-- data:=x"00A30000";
-- data:=data + ii;
-- int_mem_write( cmd, ret, adr, data );
-- end loop;
 
 
int_mem_write( cmd, ret, x"00100000", x"00008000" );
 
 
 
int_mem_write( cmd, ret, x"00100008", x"00008010" );
 
 
 
 
int_mem_write( cmd, ret, x"00100014", x"00000000" );
int_mem_write( cmd, ret, x"001001F8", x"00000000" );
int_mem_write( cmd, ret, x"001001FC", x"14A44953" );
 
 
 
int_mem_write( cmd, ret, x"00100200", x"00008020" );
 
 
 
int_mem_write( cmd, ret, x"00100208", x"00008030" );
 
int_mem_write( cmd, ret, x"001003F8", x"00000000" );
int_mem_write( cmd, ret, x"001003FC", x"D6BC4953" );
 
 
 
block_write( cmd, ret, 5, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
block_write( cmd, ret, 5, 20, x"00100000" ); -- PCI_ADRL
block_write( cmd, ret, 5, 21, x"00100000" ); -- PCI_ADRH
block_write( cmd, ret, 5, 23, x"00001000" ); -- LOCAL_ADR
 
 
 
--
 
 
 
wb_block_check_write( cmd, ret, REG_TEST_CHECK_CTRL, x"00000000" );
 
write( str, string'("BLOCK TEST_CHECK ID: " ));
hwrite( str, data );
writeline( log, str );
 
 
--
--
--
data:=wb_block_check_burst_ctrl_build('1', 40, 473);
wb_block_check_write( cmd, ret, REG_TEST_CHECK_WBS_BURST_CTRL, data);
--
--
--
block_write( cmd, ret, 5, 9, x"00000001" ); -- DMA_CTRL - START
 
 
--
 
--
 
wait for 20 us;
for ii in 0 to 20 loop
block_read( cmd, ret, 5, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data( 8 )='1' ) then
 
error := 0;
exit;
else
 
error := error + 1;
wait for 10 us;
end if;
writeline( log, str );
end loop;
if( error=0 ) then
kk:=0;
loop
-- trd_status( cmd, ret, 6, status );
-- write( str, string'("TRD_STATUS: " )); hwrite( str, status );
block_read( cmd, ret, 5, 16, data ); -- STATUS
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data(4)='1' ) then
 
 
kk:=kk+1;
if( kk=4 ) then
exit;
end if;
end if;
writeline( log, str );
wait for 500 ns;
end loop;
 
dma_complete := 0;
for ii in 0 to 100 loop
block_read( cmd, ret, 5, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data(4)='1' ) then
 
 
end if;
writeline( log, str );
if( data(5)='1' ) then
 
dma_complete := 1;
 
end if;
writeline( log, str );
if( dma_complete=1 ) then
exit;
end if;
wait for 1 us;
end loop;
writeline( log, str );
if( dma_complete=0 ) then
 
writeline( log, str );
error:=error+1;
end if;
 
end if;
for ii in 0 to 3 loop
block_read( cmd, ret, 5, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
writeline( log, str );
wait for 500 ns;
end loop;
wait for 10 us;
wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_RD, data );
 
hwrite( str, data );
kk := conv_integer( data );
if( 4/=kk ) then
 
error := error + 1;
else
write( str, string'( " - Ok" ) );
end if;
writeline( log, str );
wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_OK, data );
write( str, string'( "TEST_CHECK_BL_OK: " ) );
hwrite( str, data );
kk := conv_integer( data );
if( 3/=kk ) then
 
error := error + 1;
else
write( str, string'( " - Ok" ) );
end if;
writeline( log, str );
wb_block_check_read( cmd, ret, REG_TEST_CHECK_BL_ERROR, data );
write( str, string'( "TEST_CHECK_BL_ERROR: " ) );
hwrite( str, data );
kk := conv_integer( data );
if( 0/=kk ) then
 
error := error + 1;
else
write( str, string'( " - Ok" ) );
end if;
writeline( log, str );
block_write( cmd, ret, 5, 9, x"00000000" ); -- DMA_CTRL - STOP
-- block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
-- block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL
-- block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
writeline( log, str );
if( error=0 ) then
 
cnt_ok := cnt_ok + 1;
else
 
cnt_error := cnt_error + 1;
end if;
writeline( log, str );
writeline( log, str );
 
end test_adm_write_16kb;
---------------------------------------------------------------------------------------------------
--
-- My procedure for test Updated Design (test_read_4kb like refenernce)
--
procedure test_num_1 (
 
 
) is
variable adr : std_logic_vector( 31 downto 0 );
variable data : std_logic_vector( 31 downto 0 );
variable str : line;
variable error : integer:=0;
variable dma_complete : integer:=0;
begin
-- Init Header
write( str, string'("TEST#1: simple test of WB CORSS logic - read from empty place" ));
writeline( log, str );
--
 
for ii in 0 to 127 loop
adr:= x"00100000";
adr:=adr + ii*4;
int_mem_write( cmd, ret, adr, x"00000000" );
end loop;
-- HOST MEM Writes:
int_mem_write( cmd, ret, x"00100000", x"00008000" ); --
int_mem_write( cmd, ret, x"00100004", x"00000100" ); --
int_mem_write( cmd, ret, x"001001F8", x"00000000" ); --
int_mem_write( cmd, ret, x"001001FC", x"762C4953" ); --
--
 
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE - DEMAND_MODE==ON
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
block_write( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR : xA400 addr - check WB CROSS logic, rx value must be EQU to p_TEST_DATA_64BIT in current design
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
--
 
wait for 1 us;
block_write( cmd, ret, 4, 8, x"00000025" ); -- DMA_MODE - DEMAND_MODE==OFF
--
-- Delay for design
wait for 20 us;
--
-- Read STATUS
block_read( cmd, ret, 4, 16, data );
-- Construct LOG MSG in accordance to STATUS value and update ERR counter
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data( 8 )='1' ) then
write( str, string'(" - Descriptor==OK" ));
else
write( str, string'(" - Descriptor RD ERR" ));
error := error + 1;
end if;
writeline( log, str ); -- upd LOGFILE
--
-- Deal with STATUS Results:
if( error=0 ) then -- w8ing for DMA final
dma_complete := 0;
for ii in 0 to 100 loop -- 100 loop cycles of STATUS-process with 1us delay after
-- Read STATUS
block_read( cmd, ret, 4, 16, data );
-- Construct LOG MSG in accordance to STATUS value and update "dma_complete"
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data(5)='1' ) then
write( str, string'(" - DMA finished" ));
dma_complete := 1;
end if;
writeline( log, str );
-- Check "dma_complete"
if( dma_complete=1 ) then
exit; -- EXIT Loop on FINAL
else
wait for 1 us; -- DELAY in other case
end if;
end loop;
writeline( log, str ); -- upd LOGFILE
if( dma_complete=0 ) then -- check "dma_complete" after all
write( str, string'("ERR - DMA not finished " ));
writeline( log, str );
error:=error+1;
end if;
end if;
--
-- Print STATUS now
for ii in 0 to 3 loop -- print STATUS value 4 times with 0.5us delay after
-- Read STATUS
block_read( cmd, ret, 4, 16, data );
-- Construct LOG MSG in accordance to STATUS value
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
-- upd LOGFILE
writeline( log, str );
wait for 500 ns;
end loop;
--
-- Now STOP Design
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
--
-- Now print RX values:
--
-- Construct Header:
writeline( log, str );
write( str, string'("PRINT 1st 15 RX values: " ));
writeline( log, str );
-- Get first 15 DATA values and print it:
for ii in 0 to 15 loop
adr:= x"00800000"; -- init ADDR value
adr:=adr + ii*4; -- upd addr to curr idx
int_mem_read( cmd, ret, adr, data ); -- HOST MEM Read
-- Construct LOG MSG in accordance to HOST MEM Read value
--write( str, ii ); write( str, string'(" " )); hwrite( str, data );
hwrite( str, CONV_STD_LOGIC_VECTOR(ii, 8) );write( str, string'(" - " )); hwrite( str, data );
writeline( log, str ); -- upd LOGFILE
end loop;
writeline( log, str ); -- upd LOGFILE
--
-- Final CHECK errors:
if( error=0 ) then
write( str, string'("SUCCSESSFULL FINAL " ));
cnt_ok := cnt_ok + 1;
else
write( str, string'("FAILED FINAL " ));
cnt_error := cnt_error + 1;
end if;
writeline( log, str ); -- upd LOGFILE
writeline( log, str ); -- upd LOGFILE
--
-- END
end test_num_1;
--
--
--
procedure test_num_2 (
 
 
) is
variable adr : std_logic_vector( 31 downto 0 );
variable data : std_logic_vector( 31 downto 0 );
variable data64 : std_logic_vector( 63 downto 0 );
variable str : line;
variable error : integer:=0;
variable dma_complete : integer:=0;
begin
-- Init Header
write( str, string'("TEST#2: Get data from TEST_GEN.WB_BURST_SLAVE" ));
writeline( log, str );
--
 
for ii in 0 to 127 loop
adr:= x"00100000";
adr:=adr + ii*4;
int_mem_write( cmd, ret, adr, x"00000000" );
end loop;
-- HOST MEM Writes:
int_mem_write( cmd, ret, x"00100000", x"00008000" ); --
int_mem_write( cmd, ret, x"00100004", x"00000100" ); --
int_mem_write( cmd, ret, x"001001F8", x"00000000" ); --
int_mem_write( cmd, ret, x"001001FC", x"762C4953" ); --
--
-- TEST_GEN.WB_CFG_SLAVE: config TEST_GEN
adr :=x"20002048"; -- TEST_GEN.WB_CFG_SLAVE.TEST_GEN_SIZE
data64 :=x"0000000000000001"; -- TEST_GEN_SIZE=x01
data_write64(cmd, ret, adr, data64);-- PCIE WR
adr :=x"20002040"; -- TEST_GEN.WB_CFG_SLAVE.TEST_GEN_CTRL
data64 :=x"0000000000000022"; -- TEST_GEN_CTRL=x22 (START=1, TEST_GEN.di_start=1)
data_write64(cmd, ret, adr, data64);-- PCIE WR
-- PE_EXT_FIFO module config: --> have a bug in PE_EXT_FIFO, for check WB we will make a trick:
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE - DEMAND_MODE==ON
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
block_write( cmd, ret, 4, 23, x"00003000" ); -- LOCAL_ADR: TEST_GEN.WB_BURST_SLAVE
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
--
 
wait for 1 us;
block_write( cmd, ret, 4, 8, x"00000025" ); -- DMA_MODE - DEMAND_MODE==OFF
--
-- Delay for design
wait for 20 us;
--
-- Read STATUS (check RD DESCR status):
block_read( cmd, ret, 4, 16, data );
-- Construct LOG MSG in accordance to STATUS value and update ERR counter
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data( 8 )='1' ) then
write( str, string'(" - Descriptor==OK" ));
else
write( str, string'(" - Descriptor RD ERR" ));
error := error + 1;
end if;
writeline( log, str ); -- upd LOGFILE
--
-- W8ing for DMA finish:
if( error=0 ) then -- w8ing for DMA final
dma_complete := 0;
for ii in 0 to 100 loop -- 100 loop cycles of STATUS-process with 1us delay after
-- Read STATUS
block_read( cmd, ret, 4, 16, data );
-- Construct LOG MSG in accordance to STATUS value and update "dma_complete"
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data(5)='1' ) then
write( str, string'(" - DMA finished" ));
dma_complete := 1;
end if;
writeline( log, str );
-- Check "dma_complete"
if( dma_complete=1 ) then
exit; -- EXIT Loop on FINAL
else
wait for 1 us; -- DELAY in other case
end if;
end loop;
writeline( log, str ); -- upd LOGFILE
if( dma_complete=0 ) then -- check "dma_complete" after all
write( str, string'("ERR - DMA not finished " ));
writeline( log, str );
error:=error+1;
end if;
end if;
--
-- Print STATUS in ERR
if (error /= 0 ) then
for ii in 0 to 3 loop -- print STATUS value 4 times with 0.5us delay after
-- Read STATUS
block_read( cmd, ret, 4, 16, data );
-- Construct LOG MSG in accordance to STATUS value
write( str, string'(" STATUS: " )); hwrite( str, data( 15 downto 0 ) );
-- upd LOGFILE
writeline( log, str );
wait for 500 ns;
end loop;
end if;
--
-- Now STOP Design
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
--
-- Now print RX values:
--
-- Construct Header:
writeline( log, str );
write( str, string'("PRINT 1st 15 RX values: " ));
writeline( log, str );
-- Get first 15 DATA values and print it:
for ii in 0 to 15 loop
adr:= x"00800000"; -- init ADDR value
adr:=adr + ii*4; -- upd addr to curr idx
int_mem_read( cmd, ret, adr, data ); -- HOST MEM Read
-- Construct LOG MSG in accordance to HOST MEM Read value
--write( str, ii ); write( str, string'(" " )); hwrite( str, data );
hwrite( str, CONV_STD_LOGIC_VECTOR(ii, 8) );write( str, string'(" - " )); hwrite( str, data );
writeline( log, str ); -- upd LOGFILE
end loop;
writeline( log, str ); -- upd LOGFILE
--
-- Final CHECK errors:
if( error=0 ) then
write( str, string'(" stb SUCCSESSFULL FINAL " ));
cnt_ok := cnt_ok + 1;
else
write( str, string'(" stb FAILED FINAL " ));
cnt_error := cnt_error + 1;
end if;
writeline( log, str ); -- upd LOGFILE
writeline( log, str ); -- upd LOGFILE
--
-- END
end test_num_2;
---------------------------------------------------------------------------------------------------
--
-- My procedure for test WB stuff in Design:
-- ==> TEST_CHECK.WB_CFG_SLAVE
--
procedure test_wb_1 (
 
 
) is
variable adr : std_logic_vector( 31 downto 0 );
variable data32 : std_logic_vector( 31 downto 0 );
variable data64 : std_logic_vector( 63 downto 0 );
variable str : line;
variable error : integer:=0;
variable dma_complete : integer:=0;
--
--
type wb_cfg_slave_value is array (natural range<>) of std_logic_vector( 63 downto 0 );
type wb_cfg_slave_data is record
const : wb_cfg_slave_value(7 downto 0);
cmd : wb_cfg_slave_value(7 downto 0);
sts : wb_cfg_slave_value(7 downto 0);
end record;
--
--
variable st_wb_cfg_slave_data_0 : wb_cfg_slave_data;
variable st_wb_cfg_slave_data_1 : wb_cfg_slave_data;
variable st_wb_cfg_slave_data_2 : wb_cfg_slave_data;
begin
-- Init Header
write( str, string'("START TEST_WB#1: TEST_CHECK.WB_CFG_SLAVE"));
writeline( log, str );
--
-- Read "TEST_CHECK.WB_CFG_SLAVE"
write( str, string'("1) Read 'TEST_CHECK.WB_CFG_SLAVE'"));
writeline( log, str );
adr := x"20000000";
TEST_CHECK_WB_CFG_SLAVE_RD_00 : for i in 0 to 2 loop
TEST_CHECK_WB_CFG_SLAVE_RD_01 : for j in 0 to 7 loop
-- PCIE RD
data_read64(cmd, ret, adr, data64);
-- Put RD_Value to apropriate holder
if (i=0) then -- const
st_wb_cfg_slave_data_0.const(j) := data64;
elsif (i=1) then -- cmd
st_wb_cfg_slave_data_0.cmd(j) := data64;
else -- sts
st_wb_cfg_slave_data_0.sts(j) := data64;
end if;
-- Incr ADDR
adr := adr + x"00000008";
-- Print RD_Value
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
writeline( log, str );
end loop TEST_CHECK_WB_CFG_SLAVE_RD_01;
end loop TEST_CHECK_WB_CFG_SLAVE_RD_00;
--
-- Write
write( str, string'("2) Write 'TEST_CHECK.WB_CFG_SLAVE'"));
writeline( log, str );
adr := x"20000000";
TEST_CHECK_WB_CFG_SLAVE_WR_00 : for i in 0 to 2 loop
TEST_CHECK_WB_CFG_SLAVE_WR_01 : for j in 0 to 7 loop
-- Prepare WR_Value
data64 := conv_std_logic_vector(i*100+j*10+5, 64);
-- PCIE WR
data_write64(cmd, ret, adr, data64);
-- Put WR_Value to apropriate holder
if (i=0) then -- const
st_wb_cfg_slave_data_1.const(j) := data64;
elsif (i=1) then -- cmd
st_wb_cfg_slave_data_1.cmd(j) := data64;
else -- sts
st_wb_cfg_slave_data_1.sts(j) := data64;
end if;
-- Incr ADDR
adr := adr + x"00000008";
-- Print WR_Value
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
writeline( log, str );
end loop TEST_CHECK_WB_CFG_SLAVE_WR_01;
end loop TEST_CHECK_WB_CFG_SLAVE_WR_00;
--
-- Read
write( str, string'("3) Read 'TEST_CHECK.WB_CFG_SLAVE'"));
writeline( log, str );
adr := x"20000000";
TEST_CHECK_WB_CFG_SLAVE_RD_10 : for i in 0 to 2 loop
TEST_CHECK_WB_CFG_SLAVE_RD_11 : for j in 0 to 7 loop
-- PCIE RD
data_read64(cmd, ret, adr, data64);
-- Put RD_Value to apropriate holder
if (i=0) then -- const
st_wb_cfg_slave_data_2.const(j) := data64;
elsif (i=1) then -- cmd
st_wb_cfg_slave_data_2.cmd(j) := data64;
else -- sts
st_wb_cfg_slave_data_2.sts(j) := data64;
end if;
-- Incr ADDR
adr := adr + x"00000008";
-- Print RD_Value
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
writeline( log, str );
end loop TEST_CHECK_WB_CFG_SLAVE_RD_11;
end loop TEST_CHECK_WB_CFG_SLAVE_RD_10;
--
-- Compare results
write( str, string'("4) Process Results:"));
writeline( log, str );
-- cmp#0 - constants
CMP_CONST : for i in 0 to 7 loop
if (st_wb_cfg_slave_data_0.const(i) /= st_wb_cfg_slave_data_2.const(i) ) then -- before WR and afetr WR must be EQU (RO)
write( str, string'(" ==> CONST ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
writeline( log, str );
error := error + 1;
end if;
end loop CMP_CONST;
-- cmp#1 - commands
CMP_CMD : for i in 0 to 7 loop
if ( st_wb_cfg_slave_data_1.cmd(i) /= st_wb_cfg_slave_data_2.cmd(i) ) then -- WR value and RD value must be EQU (RW)
write( str, string'(" ==> CMD ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
writeline( log, str );
error := error + 1;
end if;
end loop CMP_CMD;
-- cmp#2 - status
CMP_STATUS : for i in 0 to 7 loop
if (st_wb_cfg_slave_data_0.sts(i) /= st_wb_cfg_slave_data_2.sts(i) ) then -- before WR and afetr WR must be EQU (RO)
write( str, string'(" ==> STATUS ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
writeline( log, str );
error := error + 1;
end if;
end loop CMP_STATUS;
-- print OK
if (error = 0) then
write( str, string'(" Results==OK"));
writeline( log, str );
cnt_ok := cnt_ok + 1;
else
cnt_error := cnt_error + 1;
end if;
-- Final Header
write( str, string'("STOP TEST_WB#1: TEST_CHECK.WB_CFG_SLAVE" ));
writeline( log, str ); -- upd LOGFILE
--
-- END
end test_wb_1;
---------------------------------------------------------------------------------------------------
--
-- My procedure for test WB stuff in Design:
-- ==> TEST_GEN.WB_CFG_SLAVE
--
procedure test_wb_2 (
 
 
) is
variable adr : std_logic_vector( 31 downto 0 );
variable data32 : std_logic_vector( 31 downto 0 );
variable data64 : std_logic_vector( 63 downto 0 );
variable str : line;
variable error : integer:=0;
variable dma_complete : integer:=0;
--
--
type wb_cfg_slave_value is array (natural range<>) of std_logic_vector( 63 downto 0 );
type wb_cfg_slave_data is record
const : wb_cfg_slave_value(7 downto 0);
cmd : wb_cfg_slave_value(7 downto 0);
sts : wb_cfg_slave_value(7 downto 0);
end record;
--
--
variable st_wb_cfg_slave_data_0 : wb_cfg_slave_data;
variable st_wb_cfg_slave_data_1 : wb_cfg_slave_data;
variable st_wb_cfg_slave_data_2 : wb_cfg_slave_data;
begin
-- Init Header
write( str, string'("START TEST_WB#2: TEST_GEN.WB_CFG_SLAVE"));
writeline( log, str );
--
-- Read "TEST_CHECK.WB_CFG_SLAVE"
write( str, string'("1) Read 'TEST_GEN.WB_CFG_SLAVE'"));
writeline( log, str );
adr := x"20002000";
TEST_CHECK_WB_CFG_SLAVE_RD_00 : for i in 0 to 2 loop
TEST_CHECK_WB_CFG_SLAVE_RD_01 : for j in 0 to 7 loop
-- PCIE RD
data_read64(cmd, ret, adr, data64);
-- Put RD_Value to apropriate holder
if (i=0) then -- const
st_wb_cfg_slave_data_0.const(j) := data64;
elsif (i=1) then -- cmd
st_wb_cfg_slave_data_0.cmd(j) := data64;
else -- sts
st_wb_cfg_slave_data_0.sts(j) := data64;
end if;
-- Incr ADDR
adr := adr + x"00000008";
-- Print RD_Value
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
writeline( log, str );
end loop TEST_CHECK_WB_CFG_SLAVE_RD_01;
end loop TEST_CHECK_WB_CFG_SLAVE_RD_00;
--
-- Write
write( str, string'("2) Write 'TEST_GEN.WB_CFG_SLAVE'"));
writeline( log, str );
adr := x"20002000";
TEST_GEN_WB_CFG_SLAVE_WR_00 : for i in 0 to 2 loop
TEST_GEN_WB_CFG_SLAVE_WR_01 : for j in 0 to 7 loop
-- Prepare WR_Value
data64 := conv_std_logic_vector(i*100+j*10+5, 64);
-- PCIE WR
data_write64(cmd, ret, adr, data64);
-- Put WR_Value to apropriate holder
if (i=0) then -- const
st_wb_cfg_slave_data_1.const(j) := data64;
elsif (i=1) then -- cmd
st_wb_cfg_slave_data_1.cmd(j) := data64;
else -- sts
st_wb_cfg_slave_data_1.sts(j) := data64;
end if;
-- Incr ADDR
adr := adr + x"00000008";
-- Print WR_Value
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
writeline( log, str );
end loop TEST_GEN_WB_CFG_SLAVE_WR_01;
end loop TEST_GEN_WB_CFG_SLAVE_WR_00;
--
-- Read
write( str, string'("3) Read 'TEST_GEN.WB_CFG_SLAVE'"));
writeline( log, str );
adr := x"20002000";
TEST_GEN_WB_CFG_SLAVE_RD_10 : for i in 0 to 2 loop
TEST_GEN_WB_CFG_SLAVE_RD_11 : for j in 0 to 7 loop
-- PCIE RD
data_read64(cmd, ret, adr, data64);
-- Put RD_Value to apropriate holder
if (i=0) then -- const
st_wb_cfg_slave_data_2.const(j) := data64;
elsif (i=1) then -- cmd
st_wb_cfg_slave_data_2.cmd(j) := data64;
else -- sts
st_wb_cfg_slave_data_2.sts(j) := data64;
end if;
-- Incr ADDR
adr := adr + x"00000008";
-- Print RD_Value
hwrite( str, data64); write( str, string'(" ==> ADDR=")); hwrite( str, (adr - x"00000008"));
writeline( log, str );
end loop TEST_GEN_WB_CFG_SLAVE_RD_11;
end loop TEST_GEN_WB_CFG_SLAVE_RD_10;
--
-- Compare results
write( str, string'("4) Process Results:"));
writeline( log, str );
-- cmp#0 - constants
CMP_CONST : for i in 0 to 7 loop
if (st_wb_cfg_slave_data_0.const(i) /= st_wb_cfg_slave_data_2.const(i) ) then -- before WR and afetr WR must be EQU (RO)
write( str, string'(" ==> CONST ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
writeline( log, str );
error := error + 1;
end if;
end loop CMP_CONST;
-- cmp#1 - commands
CMP_CMD : for i in 0 to 7 loop
if ( st_wb_cfg_slave_data_1.cmd(i) /= st_wb_cfg_slave_data_2.cmd(i) ) then -- WR value and RD value must be EQU (RW)
write( str, string'(" ==> CMD ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
writeline( log, str );
error := error + 1;
end if;
end loop CMP_CMD;
-- cmp#2 - status
CMP_STATUS : for i in 0 to 7 loop
if (st_wb_cfg_slave_data_0.sts(i) /= st_wb_cfg_slave_data_2.sts(i) ) then -- before WR and afetr WR must be EQU (RO)
write( str, string'(" ==> STATUS ERR, idx = ")); hwrite( str, CONV_STD_LOGIC_VECTOR(i, 8));
writeline( log, str );
error := error + 1;
end if;
end loop CMP_STATUS;
-- print OK
if (error = 0) then
write( str, string'(" Results==OK"));
writeline( log, str );
cnt_ok := cnt_ok + 1;
else
cnt_error := cnt_error + 1;
end if;
-- Final Header
write( str, string'("STOP TEST_WB#2: TEST_GEN.WB_CFG_SLAVE" ));
writeline( log, str ); -- upd LOGFILE
--
-- END
end test_wb_2;
---------------------------------------------------------------------------------------------------
end package body test_pkg;
/testbench/wb_block_pkg.vhd
0,0 → 1,168
---------------------------------------------------------------------------------------------------
--
-- Title : wb_block_pkg.vhd
-- Author : Dmitry Smekhov
-- Company : Instrumental Systems
-- E-mail : dsmv@insys.ru
--
-- Version : 1.0
---------------------------------------------------------------------------------------------------
--
 
--
---------------------------------------------------------------------------------------------------
--
-- Version 1.0 01.11.2011
 
--
---------------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;
 
library work;
use work.cmd_sim_pkg.all;
 
use std.textio.all;
use std.textio;
 
---------------------------------------------------------------------------------------------------
package wb_block_pkg is
--
-- Define TEST_CHECK reg id (addr in 64b cells)
--
constant REG_BLOCK_ID : integer:=0;
constant REG_BLOCK_VER : integer:=1;
 
constant REG_TEST_CHECK_CTRL : integer:=8;
constant REG_TEST_CHECK_SIZE : integer:=9;
constant REG_TEST_CHECK_ERR_ADR : integer:=16#0A#;
constant REG_TEST_CHECK_WBS_BURST_CTRL : integer:=16#0B#;
 
constant REG_TEST_CHECK_BL_RD : integer:=16#10#;
constant REG_TEST_CHECK_BL_OK : integer:=16#11#;
constant REG_TEST_CHECK_BL_ERROR : integer:=16#12#;
constant REG_TEST_CHECK_TOTAL_ERROR : integer:=16#13#;
constant REG_TEST_CHECK_ERR_DATA : integer:=16#14#;
--
-- Define TEST_GEN reg id (addr in 64b cells)
--
constant REG_TEST_GEN_CTRL : integer:=8;
constant REG_TEST_GEN_SIZE : integer:=9;
constant REG_TEST_GEN_CNT1 : integer:=16#0A#;
constant REG_TEST_GEN_CNT2 : integer:=16#0B#;
constant REG_TEST_GEN_BL_WR : integer:=16#11#;
--
-- Define SoPC ADDR (must be EQU to: ...\src\top\sp605_lx45t_wishbone_sopc_wb.vhd)
--
constant TEST_CHECK_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20000000";
constant TEST_CHECK_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20001000"; -- check data: write-only
constant TEST_GEN_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20002000";
constant TEST_GEN_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20003000"; -- generate data: read-only
 
 
procedure wb_block_check_write (
 
 
 
 
);
 
 
procedure wb_block_check_read (
 
 
 
 
);
 
 
procedure wb_block_gen_write (
 
 
 
 
);
 
 
procedure wb_block_gen_read (
 
 
 
 
);
-- Construct value for REG_TEST_CHECK_WBS_BURST_CTRL
function wb_block_check_burst_ctrl_build (i_ena : in std_logic; ii_ack_dly : in integer; ii_dly_pos : in integer) return std_logic_vector;
 
end package wb_block_pkg;
---------------------------------------------------------------------------------------------------
package body wb_block_pkg is
 
 
procedure wb_block_check_write (
 
 
 
 
) is
begin
data_write( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
end;
 
 
procedure wb_block_check_read (
 
 
 
 
) is
begin
data_read( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
end;
 
 
procedure wb_block_gen_write (
 
 
 
 
) is
begin
data_write( cmd, ret, TEST_GEN_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
end;
 
 
procedure wb_block_gen_read (
 
 
 
 
) is
begin
data_read( cmd, ret, TEST_GEN_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data );
end;
 
-- Construct value for REG_TEST_CHECK_WBS_BURST_CTRL
function wb_block_check_burst_ctrl_build (i_ena : in std_logic; ii_ack_dly : in integer; ii_dly_pos : in integer) return std_logic_vector is
variable iv_ret : std_logic_vector(31 downto 0):=(others => '0');
begin
iv_ret:= x"0000" & i_ena & conv_std_logic_vector( ii_ack_dly, 6) & conv_std_logic_vector( ii_dly_pos, 9);
return iv_ret;
end wb_block_check_burst_ctrl_build;
 
 
end package body wb_block_pkg;
 
/testbench/stend_ambpex5_wishbone.vhd
0,0 → 1,213
-------------------------------------------------------------------------------
--
-- Title : stend_ambpex5_wishbone
-- Author : Dmitry Smekhov
-- Company : Instrumental Systems
-- E-mail : dsmv@insys.ru
--
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : Stend for test ambpex5_sx50t_wishbone
--
-------------------------------------------------------------------------------
--
-- Version 1.2 20.04.2013
-- Created from stend_sp605_wishbone
--
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
 
library work;
 
use work.cmd_sim_pkg.all;
use work.block_pkg.all;
use work.ambpex5_sx50t_wishbone_pkg.all;
use work.xilinx_pcie_rport_m2_pkg.all;
 
use work.test_pkg.all;
 
use std.textio.all;
use std.textio;
 
entity stend_ambpex5_wishbone is
generic(
 
 
);
end stend_ambpex5_wishbone;
 
 
architecture stend_ambpex5_wishbone of stend_ambpex5_wishbone is
--
--function set_file_name( test_log : in string; test_id: in integer ) return string is
--variable str : line;
--variable ret : string( 255 downto 1 );
--begin
--
-- write( str, test_log );
-- write( str, string'("_id_") );
-- write( str, test_id );
--
-- ret:=conv_string( str );
-- return ret;
--
--
--end set_file_name;
 
constant fname_test_log : string:= test_log & integer'image(test_id) & ".log";
 
 
signal clk250 : std_logic:='0';
signal clk250p : std_logic;
signal clk250n : std_logic;
 
signal clk100 : std_logic:='0';
signal clk100p : std_logic;
signal clk100n : std_logic;
 
signal reset : std_logic;
 
signal txp : std_logic_vector( 7 downto 0 ):=(others=>'0');
signal txn : std_logic_vector( 7 downto 0 ):=(others=>'1');
signal rxp : std_logic_vector( 7 downto 0 ):=(others=>'0');
signal rxn : std_logic_vector( 7 downto 0 ):=(others=>'1');
 
signal rp_txp : std_logic_vector( 0 downto 0 ):=(others=>'0');
signal rp_txn : std_logic_vector( 0 downto 0 ):=(others=>'1');
signal rp_rxp : std_logic_vector( 0 downto 0 ):=(others=>'0');
signal rp_rxn : std_logic_vector( 0 downto 0 ):=(others=>'1');
 
signal tp : std_logic_vector( 3 downto 1 );
signal led1 : std_logic;
signal led2 : std_logic;
signal led3 : std_logic;
signal led4 : std_logic;
 
 
 
 
 
 
begin
 
dut: ambpex5_sx50t_wishbone
generic map(
 
)
port map(
---- PCI-Express ----
txp => txp,
txn => txn,
rxp => rxp,
rxn => rxn,
mgt251_p => clk250p,
mgt251_n => clk250n,
bperst => reset
);
rp : xilinx_pcie_rport_m2
generic map (
REF_CLK_FREQ => 0,
ALLOW_X8_GEN2 => FALSE,
PL_FAST_TRAIN => TRUE,
LINK_CAP_MAX_LINK_SPEED => X"1",
DEVICE_ID => X"6011",
LINK_CAP_MAX_LINK_WIDTH => X"01",
LINK_CAP_MAX_LINK_WIDTH_int => 1,
LINK_CTRL2_TARGET_LINK_SPEED => X"1",
LTSSM_MAX_LINK_WIDTH => X"01",
DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
VC0_TX_LASTPACKET => 29,
VC0_RX_RAM_LIMIT => X"7FF",
VC0_TOTAL_CREDITS_PD => (308),
VC0_TOTAL_CREDITS_CD => (308),
USER_CLK_FREQ => 1
)
port map (
 
sys_clk => clk100,
sys_reset_n => reset,
pci_exp_txn => rp_txn,
pci_exp_txp => rp_txp,
pci_exp_rxn => rp_rxn,
pci_exp_rxp => rp_rxp,
 
 
);
 
 
clk250 <= not clk250 after 2 ns;
 
clk250p <= clk250;
clk250n <= not clk250;
 
clk100 <= not clk100 after 5 ns;
 
clk100p <= clk100;
clk100n <= not clk100;
 
rxp(0) <= rp_txp(0);
rxn(0) <= rp_txn(0);
 
rp_rxp(0) <= txp(0);
rp_rxn(0) <= txn(0);
 
reset <= '0', '1' after 5002 ns;
 
pr_main: process
 
variable data : std_logic_vector( 31 downto 0 );
variable str : LINE; -- pointer to string
 
begin
-- test_init( "test.log" );
test_init( fname_test_log );
wait for 180 us;
case( test_id ) is
when 0 => test_dsc_incorrect( cmd, ret );
when 1 => test_read_4kb( cmd, ret ); -- was original
when 2 => test_adm_read_8kb( cmd, ret );
--when 3 => test_adm_read_16kb( cmd, ret );
--when 4 => test_adm_write_16kb( cmd, ret );
--when 5 => test_block_main( cmd, ret );
when others => null;
end case;
--test_num_1(cmd, ret);
--test_num_2(cmd, ret);
--test_wb_1(cmd, ret);
--test_wb_2(cmd, ret);
test_close;
--
-- Print Final Banner
-- report "Init END OF TEST" severity WARNING;
-- assert false
-- report "End of TEST; Ending simulation (not a Failure)"
-- severity FAILURE;
wait;
end process pr_main;
 
end stend_ambpex5_wishbone;
/top/ambpex5_sx50t_wishbone.vhd
0,0 → 1,158
-------------------------------------------------------------------------------
--
-- Title : ambpex5_sx50t_wishbone
-- Author : Dmitry Smekhov
-- Company : Instrumental Systems
-- E-mail : dsmv@insys.ru
--
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : Top-level module for PCIE_CORE64_WISHBONE_M8
--
-------------------------------------------------------------------------------
--
-- Version 1.0 20.04.2013
-- Created from sp605_lx45t_wishbone
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
package ambpex5_sx50t_wishbone_pkg is
 
component ambpex5_sx50t_wishbone is
generic
(
is_simulation : integer:=0 --! 0 - synthesis, 1 - simulation
);
port
(
---- PCI-Express ----
txp : out std_logic_vector( 7 downto 0 );
txn : out std_logic_vector( 7 downto 0 );
rxp : in std_logic_vector( 7 downto 0 ):=(others=>'0');
rxn : in std_logic_vector( 7 downto 0 ):=(others=>'0');
mgt251_p : in std_logic:='0'; -- reference clock 250 MHz from PCI_Express
mgt251_n : in std_logic:='0';
bperst : in std_logic:='0'; -- 0 - reset
--btp : out std_logic_vector(3 downto 1); -- testpoint
---- Led ----
bled1 : out std_logic;
bled2 : out std_logic;
bled3 : out std_logic;
bled4 : out std_logic
);
 
end component ambpex5_sx50t_wishbone;
 
end package ambpex5_sx50t_wishbone_pkg;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
 
library unisim;
use unisim.vcomponents.all;
 
library work;
use work.ambpex5_sx50t_wishbone_sopc_wb_pkg.all;
 
entity ambpex5_sx50t_wishbone is
generic
(
is_simulation : integer:=0 --! 0 - synthesis, 1 - simulation
);
port
(
---- PCI-Express ----
txp : out std_logic_vector( 7 downto 0 );
txn : out std_logic_vector( 7 downto 0 );
rxp : in std_logic_vector( 7 downto 0 ):=(others=>'0');
rxn : in std_logic_vector( 7 downto 0 ):=(others=>'0');
mgt251_p : in std_logic:='0'; -- reference clock 250 MHz from PCI_Express
mgt251_n : in std_logic:='0';
bperst : in std_logic:='0'; -- 0 - reset
--btp : out std_logic_vector(3 downto 1); -- testpoint
---- Led ----
bled1 : out std_logic;
bled2 : out std_logic;
bled3 : out std_logic;
bled4 : out std_logic
);
end ambpex5_sx50t_wishbone;
 
architecture rtl of ambpex5_sx50t_wishbone is
-------------------------------------------------------------------------------
--
-- PCIE SYS_CON stuff:
signal mgt250 : std_logic;
signal perst : std_logic;
-------------------------------------------------------------------------------
--
-- OUTRPUT LED stuff:
signal sv_led_h : std_logic_vector(3 downto 0);
signal sv_led_h_p : std_logic_vector(3 downto 0);
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
--
-- Module In/Out deal:
--
--
sv_led_h_p <= not sv_led_h;
--
xled1 : obuf_s_16 port map( bled1, sv_led_h_p(0) );
xled2 : obuf_s_16 port map( bled2, sv_led_h_p(1) );
xled3 : obuf_s_16 port map( bled3, sv_led_h_p(2) );
xled4 : obuf_s_16 port map( bled4, sv_led_h_p(3) );
 
--
xmgtclk : IBUFDS port map (O => mgt250, I => mgt251_p, IB => mgt251_n );
xmperst: ibuf port map( perst, bperst );
 
-------------------------------------------------------------------------------
--
-- Instantiate Wishbone SysteM (with all stuff inside)
--
WB_SOPC : ambpex5_sx50t_wishbone_sopc_wb
generic map
(
 
)
port map
(
 
---- PCI-Express ----
txp => txp,
txn => txn,
rxp => rxp,
rxn => rxn,
-- sys_con
mgt250 => mgt250,
perst => perst,
--
-- GPIO_LED outputs:
led => sv_led_h
);
-------------------------------------------------------------------------------
end rtl;
/top/ambpex5_sx50t_wishbone_sopc_wb.vhd
0,0 → 1,845
-------------------------------------------------------------------------------
--
-- Title : pcie_core64_m1
-- Author : Dmitry Smekhov
-- Company : Instrumental Systems
-- E-mail : dsmv@insys.ru
--
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : Top-level module for PCIE_CORE64 WB SoPC
-- (System have 32Bit ADDR BUS and 64bit DATA BUS)
--
-- Memory Map for SoPC (based on WB_CROSS setup):
-- 1) TEST_CHECK.WB_CFG_SLAVE:
-- ADDR Range ==> 0x0000_0000 : 0x0000_0FFF ( Valid 1st 256B only, detailed MM at test_check_wb_config_slave.vhd)
--
-- 2) TEST_CHECK.WB_BURST_SLAVE
-- ADDR Range ==> 0x0000_1000 : 0x0000_1FFF (support only Constant-Addr-Burst for 512x64bit cell (full 4KB range), Input ONLY)
--
-- 3) TEST_GEN.WB_CFG_SLAVE
-- ADDR Range ==> 0x0000_2000 : 0x0000_2FFF ( Valid 1st 256B only, detailed MM at test_generate_wb_config_slave.vhd)
--
-- 4) TEST_GEN.WB_BURST_SLAVE
-- ADDR Range ==> 0x0000_3000 : 0x0000_3FFF (support only Constant-Addr-Burst for 512x64bit cell (full 4KB range), Output ONLY)
--
-------------------------------------------------------------------------------
--
-- Version 1.0 20.04.2013
-- Created from sp605_lx45t_wishbone_sopc_wb
--
----------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
package ambpex5_sx50t_wishbone_sopc_wb_pkg is
 
component ambpex5_sx50t_wishbone_sopc_wb is
generic
(
is_simulation : integer --! 0 - synthesis, 1 - simulation
);
port
(
 
---- PCI-Express ----
txp : out std_logic_vector( 7 downto 0 );
txn : out std_logic_vector( 7 downto 0 );
rxp : in std_logic_vector( 7 downto 0 ):=(others=>'0');
rxn : in std_logic_vector( 7 downto 0 ):=(others=>'0');
mgt250 : in std_logic:='0'; -- reference clock 250 MHz from PCI_Express
perst : in std_logic:='0'; -- 0 - reset
tp : out std_logic_vector(3 downto 1); -- testpoint
---- Led ----
led : out std_logic_vector( 4 downto 1 )
);
end component ambpex5_sx50t_wishbone_sopc_wb;
 
end package ambpex5_sx50t_wishbone_sopc_wb_pkg;
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
library work;
use work.wb_conmax_top_pkg.all;
use work.pcie_core64_wishbone_m8_pkg.all;
use work.block_test_check_wb_pkg.all;
use work.block_test_generate_wb_pkg.all;
 
 
entity ambpex5_sx50t_wishbone_sopc_wb is
generic
(
is_simulation : integer --! 0 - synthesis, 1 - simulation
);
port
(
 
---- PCI-Express ----
txp : out std_logic_vector( 7 downto 0 );
txn : out std_logic_vector( 7 downto 0 );
rxp : in std_logic_vector( 7 downto 0 ):=(others=>'0');
rxn : in std_logic_vector( 7 downto 0 ):=(others=>'0');
mgt250 : in std_logic:='0'; -- reference clock 250 MHz from PCI_Express
perst : in std_logic:='0'; -- 0 - reset
tp : out std_logic_vector(3 downto 1); -- testpoint
---- Led ----
led : out std_logic_vector( 4 downto 1 )
);
end ambpex5_sx50t_wishbone_sopc_wb;
 
architecture rtl of ambpex5_sx50t_wishbone_sopc_wb is
----------------------------------------------------------------------------------
--
-- Declare PCIE_CORE64_WB stuff:
signal sv_control_points : std_logic_vector( 7 downto 0 );
signal sv_pcie_lstatus : std_logic_vector( 15 downto 0 );
signal s_pcie_link_up_n : std_logic;
-------------------------------------------------------------------------------
--
-- Declare WB_CROSS stuff:
signal st_master_port_data_in : wb_master_port_data;
signal st_master_port_data_out : wb_master_port_data;
signal st_master_port_addr : wb_master_port_addr;
signal st_master_port_sel : wb_master_port_sel;
signal st_master_port_we : wb_master_port_we;
signal st_master_port_cyc : wb_master_port_cyc;
signal st_master_port_stb : wb_master_port_stb;
signal st_master_port_ack : wb_master_port_ack;
signal st_master_port_err : wb_master_port_err;
signal st_master_port_rty : wb_master_port_rty;
signal st_master_port_cti : wb_master_port_cti;
signal st_master_port_bte : wb_master_port_bte;
 
signal st_slave_port_data_in : wb_slave_port_data;
signal st_slave_port_data_out : wb_slave_port_data;
signal st_slave_port_addr : wb_slave_port_addr;
signal st_slave_port_sel : wb_slave_port_sel;
signal st_slave_port_we : wb_slave_port_we;
signal st_slave_port_cyc : wb_slave_port_cyc;
signal st_slave_port_stb : wb_slave_port_stb;
signal st_slave_port_ack : wb_slave_port_ack;
signal st_slave_port_err : wb_slave_port_err;
signal st_slave_port_rty : wb_slave_port_rty;
signal st_slave_port_cti : wb_slave_port_cti;
signal st_slave_port_bte : wb_slave_port_bte;
-------------------------------------------------------------------------------
--
-- Declare Module Output Req stuff:
signal sv_pcie_line_num : std_logic_vector(2 downto 0);
-------------------------------------------------------------------------------
--
-- Declare WB stuff
-- SYS_CON
signal s_wb_clk : std_logic;
signal s_wb_rst : std_logic;
-- PCIE_CORE64 wb
signal sv_wbm_addr_pcie_core64_wb : std_logic_vector(p_WB_CROSS_ADDR_W-1 downto 0);
signal sv_wbm_data_out_pcie_core64_wb : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
signal sv_wbm_sel_pcie_core64_wb : std_logic_vector(p_WB_CROSS_DATA_W/8-1 downto 0);
signal s_wbm_we_pcie_core64_wb : std_logic;
signal s_wbm_cyc_pcie_core64_wb : std_logic;
signal s_wbm_stb_pcie_core64_wb : std_logic;
signal sv_wbm_cti_pcie_core64_wb : std_logic_vector(2 downto 0);
signal sv_wbm_bte_pcie_core64_wb : std_logic_vector(1 downto 0);
signal sv_wbm_data_in_pcie_core64_wb : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
signal s_wbm_ack_pcie_core64_wb : std_logic;
signal s_wbm_err_pcie_core64_wb : std_logic;
signal s_wbm_rty_pcie_core64_wb : std_logic;
signal sv_wbm_dmar_irq_pcie_core64_wb : std_logic_vector(1 downto 0);
-- TEST_CHECK.WB_CFG_SLAVE
signal sv_wbs_cfg_addr_test_check : std_logic_vector(p_WB_CROSS_ADDR_W-1 downto 0);
signal sv_wbs_cfg_data_in_test_check : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
signal sv_wbs_cfg_sel_test_check : std_logic_vector(p_WB_CROSS_DATA_W/8-1 downto 0);
signal s_wbs_cfg_we_test_check : std_logic;
signal s_wbs_cfg_cyc_test_check : std_logic;
signal s_wbs_cfg_stb_test_check : std_logic;
signal sv_wbs_cfg_cti_test_check : std_logic_vector(2 downto 0);
signal sv_wbs_cfg_bte_test_check : std_logic_vector(1 downto 0);
signal sv_wbs_cfg_data_out_test_check : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
signal s_wbs_cfg_ack_test_check : std_logic;
signal s_wbs_cfg_err_test_check : std_logic;
signal s_wbs_cfg_rty_test_check : std_logic;
signal s_wbs_irq_dmar_test_check : std_logic; -- TEST_CHECK WB DMAR IRQ
-- TEST_CHECK.WB_BURST_SLAVE
signal sv_wbs_burst_addr_test_check : std_logic_vector(p_WB_CROSS_ADDR_W-1 downto 0);
signal sv_wbs_burst_data_in_test_check : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
signal sv_wbs_burst_sel_test_check : std_logic_vector(p_WB_CROSS_DATA_W/8-1 downto 0);
signal s_wbs_burst_we_test_check : std_logic;
signal s_wbs_burst_cyc_test_check : std_logic;
signal s_wbs_burst_stb_test_check : std_logic;
signal sv_wbs_burst_cti_test_check : std_logic_vector(2 downto 0);
signal sv_wbs_burst_bte_test_check : std_logic_vector(1 downto 0);
signal s_wbs_burst_ack_test_check : std_logic;
signal s_wbs_burst_err_test_check : std_logic;
signal s_wbs_burst_rty_test_check : std_logic;
-- TEST_GEN.WB_CFG_SLAVE
signal sv_wbs_cfg_addr_test_gen : std_logic_vector(p_WB_CROSS_ADDR_W-1 downto 0);
signal sv_wbs_cfg_data_in_test_gen : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
signal sv_wbs_cfg_sel_test_gen : std_logic_vector(p_WB_CROSS_DATA_W/8-1 downto 0);
signal s_wbs_cfg_we_test_gen : std_logic;
signal s_wbs_cfg_cyc_test_gen : std_logic;
signal s_wbs_cfg_stb_test_gen : std_logic;
signal sv_wbs_cfg_cti_test_gen : std_logic_vector(2 downto 0);
signal sv_wbs_cfg_bte_test_gen : std_logic_vector(1 downto 0);
signal sv_wbs_cfg_data_out_test_gen : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
signal s_wbs_cfg_ack_test_gen : std_logic;
signal s_wbs_cfg_err_test_gen : std_logic;
signal s_wbs_cfg_rty_test_gen : std_logic;
signal s_wbs_irq_dmar_test_gen : std_logic; -- TEST_GEN WB DMAR IRQ
-- TEST_GEN.WB_BURST_SLAVE
signal sv_wbs_burst_addr_test_gen : std_logic_vector(p_WB_CROSS_ADDR_W-1 downto 0);
signal sv_wbs_burst_data_out_test_gen : std_logic_vector(p_WB_CROSS_DATA_W-1 downto 0);
signal sv_wbs_burst_sel_test_gen : std_logic_vector(p_WB_CROSS_DATA_W/8-1 downto 0);
signal s_wbs_burst_we_test_gen : std_logic;
signal s_wbs_burst_cyc_test_gen : std_logic;
signal s_wbs_burst_stb_test_gen : std_logic;
signal sv_wbs_burst_cti_test_gen : std_logic_vector(2 downto 0);
signal sv_wbs_burst_bte_test_gen : std_logic_vector(1 downto 0);
signal s_wbs_burst_ack_test_gen : std_logic;
signal s_wbs_burst_err_test_gen : std_logic;
signal s_wbs_burst_rty_test_gen : std_logic;
----------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
--
-- Instantiate PCIE_CORE64_WB module (provide main PCIE finctionality):
--
PCIE_CORE64_WB : pcie_core64_wishbone_m8
generic map
(
 
 
 
 
)
port map
(
---- PCI-Express ----
txp => txp,
txn => txn,
rxp => rxp,
rxn => rxn,
 
 
 
 
 
---- Wishbone SYS_CON -----
o_wb_clk => s_wb_clk,
o_wb_rst => s_wb_rst,
---- Wishbone BUS -----
ov_wbm_addr => sv_wbm_addr_pcie_core64_wb,
ov_wbm_data => sv_wbm_data_out_pcie_core64_wb,
ov_wbm_sel => sv_wbm_sel_pcie_core64_wb,
o_wbm_we => s_wbm_we_pcie_core64_wb,
o_wbm_cyc => s_wbm_cyc_pcie_core64_wb,
o_wbm_stb => s_wbm_stb_pcie_core64_wb,
ov_wbm_cti => sv_wbm_cti_pcie_core64_wb, -- Cycle Type Identifier Address Tag
ov_wbm_bte => sv_wbm_bte_pcie_core64_wb, -- Burst Type Extension Address Tag
iv_wbm_data => sv_wbm_data_in_pcie_core64_wb,
i_wbm_ack => s_wbm_ack_pcie_core64_wb,
i_wbm_err => s_wbm_err_pcie_core64_wb, -- error input - abnormal cycle termination
i_wbm_rty => s_wbm_rty_pcie_core64_wb, -- retry input - interface is not ready
i_wdm_irq_0 => '0', -- NC for now
iv_wbm_irq_dmar => sv_wbm_dmar_irq_pcie_core64_wb --
);
-- Construct DMAR WB IR Input:
sv_wbm_dmar_irq_pcie_core64_wb <= s_wbs_irq_dmar_test_check & s_wbs_irq_dmar_test_gen; -- Bit#1 - TEST_CHECK, Bit#0 - TEST_GEN
-------------------------------------------------------------------------------
--
-- Instantiate TEST_CHECK (provide check of input data):
--
TEST_CHECK : block_test_check_wb
port map
(
--
-- SYS_CON
i_clk => s_wb_clk,
i_rst => s_wb_rst,
--
-- WB CFG SLAVE IF
iv_wbs_cfg_addr => sv_wbs_cfg_addr_test_check( 7 downto 0), -- Route only req addr wires: 256B ADDR Range
iv_wbs_cfg_data => sv_wbs_cfg_data_in_test_check,
iv_wbs_cfg_sel => sv_wbs_cfg_sel_test_check,
i_wbs_cfg_we => s_wbs_cfg_we_test_check,
i_wbs_cfg_cyc => s_wbs_cfg_cyc_test_check,
i_wbs_cfg_stb => s_wbs_cfg_stb_test_check,
iv_wbs_cfg_cti => sv_wbs_cfg_cti_test_check,
iv_wbs_cfg_bte => sv_wbs_cfg_bte_test_check,
ov_wbs_cfg_data => sv_wbs_cfg_data_out_test_check,
o_wbs_cfg_ack => s_wbs_cfg_ack_test_check,
o_wbs_cfg_err => s_wbs_cfg_err_test_check,
o_wbs_cfg_rty => s_wbs_cfg_rty_test_check,
--
-- WB BURST SLAVE IF (WRITE-ONLY IF)
iv_wbs_burst_addr => sv_wbs_burst_addr_test_check( 11 downto 0), -- Route only req addr wires: 4KB ADDR Range
iv_wbs_burst_data => sv_wbs_burst_data_in_test_check,
iv_wbs_burst_sel => sv_wbs_burst_sel_test_check,
i_wbs_burst_we => s_wbs_burst_we_test_check,
i_wbs_burst_cyc => s_wbs_burst_cyc_test_check,
i_wbs_burst_stb => s_wbs_burst_stb_test_check,
iv_wbs_burst_cti => sv_wbs_burst_cti_test_check,
iv_wbs_burst_bte => sv_wbs_burst_bte_test_check,
o_wbs_burst_ack => s_wbs_burst_ack_test_check,
o_wbs_burst_err => s_wbs_burst_err_test_check,
o_wbs_burst_rty => s_wbs_burst_rty_test_check,
--
-- WB IRQ lines
o_wbs_irq_0 => OPEN, -- NC for now
o_wbs_irq_dmar => s_wbs_irq_dmar_test_check --
);
-------------------------------------------------------------------------------
--
-- Instantiate TEST_GEN (provide generation of test data):
--
TEST_GEN : block_test_generate_wb
port map
(
--
-- SYS_CON
i_clk => s_wb_clk,
i_rst => s_wb_rst,
--
-- WB CFG SLAVE IF
iv_wbs_cfg_addr => sv_wbs_cfg_addr_test_gen( 7 downto 0), -- Route only req addr wires: 256B ADDR Range
iv_wbs_cfg_data => sv_wbs_cfg_data_in_test_gen,
iv_wbs_cfg_sel => sv_wbs_cfg_sel_test_gen,
i_wbs_cfg_we => s_wbs_cfg_we_test_gen,
i_wbs_cfg_cyc => s_wbs_cfg_cyc_test_gen,
i_wbs_cfg_stb => s_wbs_cfg_stb_test_gen,
iv_wbs_cfg_cti => sv_wbs_cfg_cti_test_gen,
iv_wbs_cfg_bte => sv_wbs_cfg_bte_test_gen,
ov_wbs_cfg_data => sv_wbs_cfg_data_out_test_gen,
o_wbs_cfg_ack => s_wbs_cfg_ack_test_gen,
o_wbs_cfg_err => s_wbs_cfg_err_test_gen,
o_wbs_cfg_rty => s_wbs_cfg_rty_test_gen,
--
-- WB BURST SLAVE IF (READ-ONLY IF)
iv_wbs_burst_addr => sv_wbs_burst_addr_test_gen( 11 downto 0), -- Route only req addr wires: 4KB ADDR Range
iv_wbs_burst_sel => sv_wbs_burst_sel_test_gen,
i_wbs_burst_we => s_wbs_burst_we_test_gen,
i_wbs_burst_cyc => s_wbs_burst_cyc_test_gen,
i_wbs_burst_stb => s_wbs_burst_stb_test_gen,
iv_wbs_burst_cti => sv_wbs_burst_cti_test_gen,
iv_wbs_burst_bte => sv_wbs_burst_bte_test_gen,
ov_wbs_burst_data => sv_wbs_burst_data_out_test_gen,
o_wbs_burst_ack => s_wbs_burst_ack_test_gen,
o_wbs_burst_err => s_wbs_burst_err_test_gen,
o_wbs_burst_rty => s_wbs_burst_rty_test_gen,
--
-- WB IRQ lines
o_wbs_irq_0 => OPEN, -- NC for now
o_wbs_irq_dmar => s_wbs_irq_dmar_test_gen --
);
-------------------------------------------------------------------------------
--
-- Instantiate WB_CROSS
-- ==> MOST HEAVY PART of DESIGN (from port-quantity point of view)
--
WB_CROSS : wb_conmax_top
generic map
(
dw => p_WB_CROSS_DATA_W, -- WB_DATA_WIDTH==64bit (defined at wb_conmax_top_pkg.vhd)
aw => p_WB_CROSS_ADDR_W -- WB_ADDR_WIDTH==32bit (defined at wb_conmax_top_pkg.vhd)
)
port map
(
--
-- SYS_CON
clk_i => s_wb_clk,
rst_i => s_wb_rst,
--
-- Master 0 Interface
m0_data_i => st_master_port_data_in(0),
m0_data_o => st_master_port_data_out(0),
m0_addr_i => st_master_port_addr(0),
m0_sel_i => st_master_port_sel(0),
m0_we_i => st_master_port_we(0),
m0_cyc_i => st_master_port_cyc(0),
m0_stb_i => st_master_port_stb(0),
m0_ack_o => st_master_port_ack(0),
m0_err_o => st_master_port_err(0),
m0_rty_o => st_master_port_rty(0),
m0_cti_i => st_master_port_cti(0),
m0_bte_i => st_master_port_bte(0),
--
-- Master 1 Interface
m1_data_i => st_master_port_data_in(1),
m1_data_o => st_master_port_data_out(1),
m1_addr_i => st_master_port_addr(1),
m1_sel_i => st_master_port_sel(1),
m1_we_i => st_master_port_we(1),
m1_cyc_i => st_master_port_cyc(1),
m1_stb_i => st_master_port_stb(1),
m1_ack_o => st_master_port_ack(1),
m1_err_o => st_master_port_err(1),
m1_rty_o => st_master_port_rty(1),
m1_cti_i => st_master_port_cti(1),
m1_bte_i => st_master_port_bte(1),
--
-- Master 2 Interface
m2_data_i => st_master_port_data_in(2),
m2_data_o => st_master_port_data_out(2),
m2_addr_i => st_master_port_addr(2),
m2_sel_i => st_master_port_sel(2),
m2_we_i => st_master_port_we(2),
m2_cyc_i => st_master_port_cyc(2),
m2_stb_i => st_master_port_stb(2),
m2_ack_o => st_master_port_ack(2),
m2_err_o => st_master_port_err(2),
m2_rty_o => st_master_port_rty(2),
m2_cti_i => st_master_port_cti(2),
m2_bte_i => st_master_port_bte(2),
--
-- Master 3 Interface
m3_data_i => st_master_port_data_in(3),
m3_data_o => st_master_port_data_out(3),
m3_addr_i => st_master_port_addr(3),
m3_sel_i => st_master_port_sel(3),
m3_we_i => st_master_port_we(3),
m3_cyc_i => st_master_port_cyc(3),
m3_stb_i => st_master_port_stb(3),
m3_ack_o => st_master_port_ack(3),
m3_err_o => st_master_port_err(3),
m3_rty_o => st_master_port_rty(3),
m3_cti_i => st_master_port_cti(3),
m3_bte_i => st_master_port_bte(3),
--
-- Master 4 Interface
m4_data_i => st_master_port_data_in(4),
m4_data_o => st_master_port_data_out(4),
m4_addr_i => st_master_port_addr(4),
m4_sel_i => st_master_port_sel(4),
m4_we_i => st_master_port_we(4),
m4_cyc_i => st_master_port_cyc(4),
m4_stb_i => st_master_port_stb(4),
m4_ack_o => st_master_port_ack(4),
m4_err_o => st_master_port_err(4),
m4_rty_o => st_master_port_rty(4),
m4_cti_i => st_master_port_cti(4),
m4_bte_i => st_master_port_bte(4),
--
-- Master 5 Interface
m5_data_i => st_master_port_data_in(5),
m5_data_o => st_master_port_data_out(5),
m5_addr_i => st_master_port_addr(5),
m5_sel_i => st_master_port_sel(5),
m5_we_i => st_master_port_we(5),
m5_cyc_i => st_master_port_cyc(5),
m5_stb_i => st_master_port_stb(5),
m5_ack_o => st_master_port_ack(5),
m5_err_o => st_master_port_err(5),
m5_rty_o => st_master_port_rty(5),
m5_cti_i => st_master_port_cti(5),
m5_bte_i => st_master_port_bte(5),
--
-- Master 6 Interface
m6_data_i => st_master_port_data_in(6),
m6_data_o => st_master_port_data_out(6),
m6_addr_i => st_master_port_addr(6),
m6_sel_i => st_master_port_sel(6),
m6_we_i => st_master_port_we(6),
m6_cyc_i => st_master_port_cyc(6),
m6_stb_i => st_master_port_stb(6),
m6_ack_o => st_master_port_ack(6),
m6_err_o => st_master_port_err(6),
m6_rty_o => st_master_port_rty(6),
m6_cti_i => st_master_port_cti(6),
m6_bte_i => st_master_port_bte(6),
--
-- Master 7 Interface
m7_data_i => st_master_port_data_in(7),
m7_data_o => st_master_port_data_out(7),
m7_addr_i => st_master_port_addr(7),
m7_sel_i => st_master_port_sel(7),
m7_we_i => st_master_port_we(7),
m7_cyc_i => st_master_port_cyc(7),
m7_stb_i => st_master_port_stb(7),
m7_ack_o => st_master_port_ack(7),
m7_err_o => st_master_port_err(7),
m7_rty_o => st_master_port_rty(7),
m7_cti_i => st_master_port_cti(7),
m7_bte_i => st_master_port_bte(7),
--
--
-- Slave 0 Interface
s0_data_i => st_slave_port_data_in(0),
s0_data_o => st_slave_port_data_out(0),
s0_addr_o => st_slave_port_addr(0),
s0_sel_o => st_slave_port_sel(0),
s0_we_o => st_slave_port_we(0),
s0_cyc_o => st_slave_port_cyc(0),
s0_stb_o => st_slave_port_stb(0),
s0_ack_i => st_slave_port_ack(0),
s0_err_i => st_slave_port_err(0),
s0_rty_i => st_slave_port_rty(0),
s0_cti_o => st_slave_port_cti(0),
s0_bte_o => st_slave_port_bte(0),
--
-- Slave 1 Interface
s1_data_i => st_slave_port_data_in(1),
s1_data_o => st_slave_port_data_out(1),
s1_addr_o => st_slave_port_addr(1),
s1_sel_o => st_slave_port_sel(1),
s1_we_o => st_slave_port_we(1),
s1_cyc_o => st_slave_port_cyc(1),
s1_stb_o => st_slave_port_stb(1),
s1_ack_i => st_slave_port_ack(1),
s1_err_i => st_slave_port_err(1),
s1_rty_i => st_slave_port_rty(1),
s1_cti_o => st_slave_port_cti(1),
s1_bte_o => st_slave_port_bte(1),
--
-- Slave 2 Interface
s2_data_i => st_slave_port_data_in(2),
s2_data_o => st_slave_port_data_out(2),
s2_addr_o => st_slave_port_addr(2),
s2_sel_o => st_slave_port_sel(2),
s2_we_o => st_slave_port_we(2),
s2_cyc_o => st_slave_port_cyc(2),
s2_stb_o => st_slave_port_stb(2),
s2_ack_i => st_slave_port_ack(2),
s2_err_i => st_slave_port_err(2),
s2_rty_i => st_slave_port_rty(2),
s2_cti_o => st_slave_port_cti(2),
s2_bte_o => st_slave_port_bte(2),
--
-- Slave 3 Interface
s3_data_i => st_slave_port_data_in(3),
s3_data_o => st_slave_port_data_out(3),
s3_addr_o => st_slave_port_addr(3),
s3_sel_o => st_slave_port_sel(3),
s3_we_o => st_slave_port_we(3),
s3_cyc_o => st_slave_port_cyc(3),
s3_stb_o => st_slave_port_stb(3),
s3_ack_i => st_slave_port_ack(3),
s3_err_i => st_slave_port_err(3),
s3_rty_i => st_slave_port_rty(3),
s3_cti_o => st_slave_port_cti(3),
s3_bte_o => st_slave_port_bte(3),
--
-- Slave 4 Interface
s4_data_i => st_slave_port_data_in(4),
s4_data_o => st_slave_port_data_out(4),
s4_addr_o => st_slave_port_addr(4),
s4_sel_o => st_slave_port_sel(4),
s4_we_o => st_slave_port_we(4),
s4_cyc_o => st_slave_port_cyc(4),
s4_stb_o => st_slave_port_stb(4),
s4_ack_i => st_slave_port_ack(4),
s4_err_i => st_slave_port_err(4),
s4_rty_i => st_slave_port_rty(4),
s4_cti_o => st_slave_port_cti(4),
s4_bte_o => st_slave_port_bte(4),
--
-- Slave 5 Interface
s5_data_i => st_slave_port_data_in(5),
s5_data_o => st_slave_port_data_out(5),
s5_addr_o => st_slave_port_addr(5),
s5_sel_o => st_slave_port_sel(5),
s5_we_o => st_slave_port_we(5),
s5_cyc_o => st_slave_port_cyc(5),
s5_stb_o => st_slave_port_stb(5),
s5_ack_i => st_slave_port_ack(5),
s5_err_i => st_slave_port_err(5),
s5_rty_i => st_slave_port_rty(5),
s5_cti_o => st_slave_port_cti(5),
s5_bte_o => st_slave_port_bte(5),
--
-- Slave 6 Interface
s6_data_i => st_slave_port_data_in(6),
s6_data_o => st_slave_port_data_out(6),
s6_addr_o => st_slave_port_addr(6),
s6_sel_o => st_slave_port_sel(6),
s6_we_o => st_slave_port_we(6),
s6_cyc_o => st_slave_port_cyc(6),
s6_stb_o => st_slave_port_stb(6),
s6_ack_i => st_slave_port_ack(6),
s6_err_i => st_slave_port_err(6),
s6_rty_i => st_slave_port_rty(6),
s6_cti_o => st_slave_port_cti(6),
s6_bte_o => st_slave_port_bte(6),
--
-- Slave 7 Interface
s7_data_i => st_slave_port_data_in(7),
s7_data_o => st_slave_port_data_out(7),
s7_addr_o => st_slave_port_addr(7),
s7_sel_o => st_slave_port_sel(7),
s7_we_o => st_slave_port_we(7),
s7_cyc_o => st_slave_port_cyc(7),
s7_stb_o => st_slave_port_stb(7),
s7_ack_i => st_slave_port_ack(7),
s7_err_i => st_slave_port_err(7),
s7_rty_i => st_slave_port_rty(7),
s7_cti_o => st_slave_port_cti(7),
s7_bte_o => st_slave_port_bte(7),
--
-- Slave 8 Interface
s8_data_i => st_slave_port_data_in(8),
s8_data_o => st_slave_port_data_out(8),
s8_addr_o => st_slave_port_addr(8),
s8_sel_o => st_slave_port_sel(8),
s8_we_o => st_slave_port_we(8),
s8_cyc_o => st_slave_port_cyc(8),
s8_stb_o => st_slave_port_stb(8),
s8_ack_i => st_slave_port_ack(8),
s8_err_i => st_slave_port_err(8),
s8_rty_i => st_slave_port_rty(8),
s8_cti_o => st_slave_port_cti(8),
s8_bte_o => st_slave_port_bte(8),
--
-- Slave 9 Interface
s9_data_i => st_slave_port_data_in(9),
s9_data_o => st_slave_port_data_out(9),
s9_addr_o => st_slave_port_addr(9),
s9_sel_o => st_slave_port_sel(9),
s9_we_o => st_slave_port_we(9),
s9_cyc_o => st_slave_port_cyc(9),
s9_stb_o => st_slave_port_stb(9),
s9_ack_i => st_slave_port_ack(9),
s9_err_i => st_slave_port_err(9),
s9_rty_i => st_slave_port_rty(9),
s9_cti_o => st_slave_port_cti(9),
s9_bte_o => st_slave_port_bte(9),
--
-- Slave 10 Interface
s10_data_i => st_slave_port_data_in(10),
s10_data_o => st_slave_port_data_out(10),
s10_addr_o => st_slave_port_addr(10),
s10_sel_o => st_slave_port_sel(10),
s10_we_o => st_slave_port_we(10),
s10_cyc_o => st_slave_port_cyc(10),
s10_stb_o => st_slave_port_stb(10),
s10_ack_i => st_slave_port_ack(10),
s10_err_i => st_slave_port_err(10),
s10_rty_i => st_slave_port_rty(10),
s10_cti_o => st_slave_port_cti(10),
s10_bte_o => st_slave_port_bte(10),
--
-- Slave 11 Interface
s11_data_i => st_slave_port_data_in(11),
s11_data_o => st_slave_port_data_out(11),
s11_addr_o => st_slave_port_addr(11),
s11_sel_o => st_slave_port_sel(11),
s11_we_o => st_slave_port_we(11),
s11_cyc_o => st_slave_port_cyc(11),
s11_stb_o => st_slave_port_stb(11),
s11_ack_i => st_slave_port_ack(11),
s11_err_i => st_slave_port_err(11),
s11_rty_i => st_slave_port_rty(11),
s11_cti_o => st_slave_port_cti(11),
s11_bte_o => st_slave_port_bte(11),
--
-- Slave 12 Interface
s12_data_i => st_slave_port_data_in(12),
s12_data_o => st_slave_port_data_out(12),
s12_addr_o => st_slave_port_addr(12),
s12_sel_o => st_slave_port_sel(12),
s12_we_o => st_slave_port_we(12),
s12_cyc_o => st_slave_port_cyc(12),
s12_stb_o => st_slave_port_stb(12),
s12_ack_i => st_slave_port_ack(12),
s12_err_i => st_slave_port_err(12),
s12_rty_i => st_slave_port_rty(12),
s12_cti_o => st_slave_port_cti(12),
s12_bte_o => st_slave_port_bte(12),
--
-- Slave 13 Interface
s13_data_i => st_slave_port_data_in(13),
s13_data_o => st_slave_port_data_out(13),
s13_addr_o => st_slave_port_addr(13),
s13_sel_o => st_slave_port_sel(13),
s13_we_o => st_slave_port_we(13),
s13_cyc_o => st_slave_port_cyc(13),
s13_stb_o => st_slave_port_stb(13),
s13_ack_i => st_slave_port_ack(13),
s13_err_i => st_slave_port_err(13),
s13_rty_i => st_slave_port_rty(13),
s13_cti_o => st_slave_port_cti(13),
s13_bte_o => st_slave_port_bte(13),
--
-- Slave 14 Interface
s14_data_i => st_slave_port_data_in(14),
s14_data_o => st_slave_port_data_out(14),
s14_addr_o => st_slave_port_addr(14),
s14_sel_o => st_slave_port_sel(14),
s14_we_o => st_slave_port_we(14),
s14_cyc_o => st_slave_port_cyc(14),
s14_stb_o => st_slave_port_stb(14),
s14_ack_i => st_slave_port_ack(14),
s14_err_i => st_slave_port_err(14),
s14_rty_i => st_slave_port_rty(14),
s14_cti_o => st_slave_port_cti(14),
s14_bte_o => st_slave_port_bte(14),
--
-- Slave 15 Interface
s15_data_i => st_slave_port_data_in(15),
s15_data_o => st_slave_port_data_out(15),
s15_addr_o => st_slave_port_addr(15),
s15_sel_o => st_slave_port_sel(15),
s15_we_o => st_slave_port_we(15),
s15_cyc_o => st_slave_port_cyc(15),
s15_stb_o => st_slave_port_stb(15),
s15_ack_i => st_slave_port_ack(15),
s15_err_i => st_slave_port_err(15),
s15_rty_i => st_slave_port_rty(15),
s15_cti_o => st_slave_port_cti(15),
s15_bte_o => st_slave_port_bte(15)
);
-------------------------------------------------------------------------------
--
-- Module Inner route:
--
-- 1st route WB_CROSS MASTER signals:
-- ==> Deal with PCIE_CORE64_WB Ports:
st_master_port_data_in(0) <= sv_wbm_data_out_pcie_core64_wb; -- from WBM to WB_CROSS
st_master_port_addr(0) <= sv_wbm_addr_pcie_core64_wb; -- ...
st_master_port_sel(0) <= sv_wbm_sel_pcie_core64_wb; -- ...
st_master_port_we(0) <= s_wbm_we_pcie_core64_wb; -- ...
st_master_port_cyc(0) <= s_wbm_cyc_pcie_core64_wb; -- ...
st_master_port_stb(0) <= s_wbm_stb_pcie_core64_wb; -- ...
st_master_port_cti(0) <= sv_wbm_cti_pcie_core64_wb; -- ...
st_master_port_bte(0) <= sv_wbm_bte_pcie_core64_wb; -- ...
 
sv_wbm_data_in_pcie_core64_wb <= st_master_port_data_out(0); -- from WB_CROSS to WBM
s_wbm_ack_pcie_core64_wb <= st_master_port_ack(0); -- ...
s_wbm_err_pcie_core64_wb <= st_master_port_err(0); -- ...
s_wbm_rty_pcie_core64_wb <= st_master_port_rty(0); -- ...
-- ==> Deal with Unused Ports:
gen_conn_to_unused_mports : for i in (0+1) to p_WB_CROSS_MASTER_Q-1 generate
st_master_port_data_in(i) <= (others => '0');
st_master_port_addr(i) <= (others => '0');
st_master_port_sel(i) <= (others => '0');
st_master_port_we(i) <= '0';
st_master_port_cyc(i) <= '0';
st_master_port_stb(i) <= '0';
st_master_port_cti(i) <= (others => '0');
st_master_port_bte(i) <= (others => '0');
--st_master_port_data_out(i) <= ;
--st_master_port_ack(i) <= ;
--st_master_port_err(i) <= ;
--st_master_port_rty(i) <= ;
end generate gen_conn_to_unused_mports;
--
-- 2nd route WB_CROSS SLAVE signals:
-- Deal with TEST_CHECK.WB_CFG_SLAVE
sv_wbs_cfg_data_in_test_check <= st_slave_port_data_out(0); -- from WB_CROSS to WBS
sv_wbs_cfg_addr_test_check <= st_slave_port_addr(0); -- ...
sv_wbs_cfg_sel_test_check <= st_slave_port_sel(0); -- ...
s_wbs_cfg_we_test_check <= st_slave_port_we(0); -- ...
s_wbs_cfg_cyc_test_check <= st_slave_port_cyc(0); -- ...
s_wbs_cfg_stb_test_check <= st_slave_port_stb(0); -- ...
sv_wbs_cfg_cti_test_check <= st_slave_port_cti(0); -- ...
sv_wbs_cfg_bte_test_check <= st_slave_port_bte(0); -- ...
 
st_slave_port_data_in(0) <= sv_wbs_cfg_data_out_test_check; -- from WBS to WB_CROSS
st_slave_port_ack(0) <= s_wbs_cfg_ack_test_check; -- ...
st_slave_port_err(0) <= s_wbs_cfg_err_test_check; -- ...
st_slave_port_rty(0) <= s_wbs_cfg_rty_test_check; -- ...
-- Deal with TEST_CHECK.WB_BURST_SLAVE
sv_wbs_burst_data_in_test_check <= st_slave_port_data_out(1); -- from WB_CROSS to WBS
sv_wbs_burst_addr_test_check <= st_slave_port_addr(1); -- ...
sv_wbs_burst_sel_test_check <= st_slave_port_sel(1); -- ...
s_wbs_burst_we_test_check <= st_slave_port_we(1); -- ...
s_wbs_burst_cyc_test_check <= st_slave_port_cyc(1); -- ...
s_wbs_burst_stb_test_check <= st_slave_port_stb(1); -- ...
sv_wbs_burst_cti_test_check <= st_slave_port_cti(1);
sv_wbs_burst_bte_test_check <= st_slave_port_bte(1);
 
st_slave_port_data_in(1) <= (others => '0'); -- from WBS to WB_CROSS
st_slave_port_ack(1) <= s_wbs_burst_ack_test_check; -- ...
st_slave_port_err(1) <= s_wbs_burst_err_test_check; -- ...
st_slave_port_rty(1) <= s_wbs_burst_rty_test_check; -- ...
-- Deal with TEST_GEN.WB_CFG_SLAVE
sv_wbs_cfg_data_in_test_gen <= st_slave_port_data_out(2); -- from WB_CROSS to WBS
sv_wbs_cfg_addr_test_gen <= st_slave_port_addr(2); -- ...
sv_wbs_cfg_sel_test_gen <= st_slave_port_sel(2); -- ...
s_wbs_cfg_we_test_gen <= st_slave_port_we(2); -- ...
s_wbs_cfg_cyc_test_gen <= st_slave_port_cyc(2); -- ...
s_wbs_cfg_stb_test_gen <= st_slave_port_stb(2); -- ...
sv_wbs_cfg_cti_test_gen <= st_slave_port_cti(2); -- ...
sv_wbs_cfg_bte_test_gen <= st_slave_port_bte(2); -- ...
 
st_slave_port_data_in(2) <= sv_wbs_cfg_data_out_test_gen; -- from WBS to WB_CROSS
st_slave_port_ack(2) <= s_wbs_cfg_ack_test_gen; -- ...
st_slave_port_err(2) <= s_wbs_cfg_err_test_gen; -- ...
st_slave_port_rty(2) <= s_wbs_cfg_rty_test_gen; -- ...
-- Deal with TEST_GEN.WB_BURST_SLAVE
--st_slave_port_data_out(3)
sv_wbs_burst_addr_test_gen <= st_slave_port_addr(3);
sv_wbs_burst_sel_test_gen <= st_slave_port_sel(3);
s_wbs_burst_we_test_gen <= st_slave_port_we(3);
s_wbs_burst_cyc_test_gen <= st_slave_port_cyc(3);
s_wbs_burst_stb_test_gen <= st_slave_port_stb(3);
sv_wbs_burst_cti_test_gen <= st_slave_port_cti(3);
sv_wbs_burst_bte_test_gen <= st_slave_port_bte(3);
 
st_slave_port_data_in(3) <= sv_wbs_burst_data_out_test_gen;
st_slave_port_ack(3) <= s_wbs_burst_ack_test_gen;
st_slave_port_err(3) <= s_wbs_burst_err_test_gen;
st_slave_port_rty(3) <= s_wbs_burst_rty_test_gen;
-- Deal with Unused SALVE Ports
gen_conn_to_unused_sports : for i in (3+1) to p_WB_CROSS_SLAVE_Q-1 generate
--st_slave_port_data_out(i) <= ;
--st_slave_port_addr(i) <= ;
--st_slave_port_sel(i) <= ;
--st_slave_port_we(i) <= ;
--st_slave_port_cyc(i) <= ;
--st_slave_port_stb(i) <= ;
--st_slave_port_cti(i) <= ;
--st_slave_port_bte(i) <= ;
st_slave_port_data_in(i) <= p_TEST_DATA_64BIT;
st_slave_port_ack(i) <= '1'; -- ALWAYS READY (always answer to MASTER with "p_TEST_DATA_64BIT" value)
st_slave_port_err(i) <= '0';
st_slave_port_rty(i) <= '0';
end generate gen_conn_to_unused_sports;
--
-- Construct PCIE Line-width value:
sv_pcie_line_num <= sv_pcie_lstatus(6 downto 4) when s_pcie_link_up_n='0'
else "000";
 
-------------------------------------------------------------------------------
--
-- Module Outputs deal:
--
led(1) <= s_pcie_link_up_n after 1ns when rising_edge(s_wb_clk); -- LED#0 - PCIE_LINK_UP
--
led(3 downto 2) <= sv_pcie_line_num( 1 downto 0 ) after 1ns when rising_edge(s_wb_clk); -- LED#1 - show PCIE line-width: x1->1, x2->2, etc...
 
-------------------------------------------------------------------------------
end rtl;
/.
. Property changes : Added: svn:externals ## -0,0 +1,2 ## +pcie_src http://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk/core/ds_dma64/pcie_src +wishbone http://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk/core/wishbone

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