URL
https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk
Subversion Repositories pcie_ds_dma
Compare Revisions
- This comparison shows the changes necessary to convert path
/pcie_ds_dma/trunk/projects/sp605_lx45t_wishbone/src/testbench
- from Rev 10 to Rev 16
- ↔ Reverse comparison
Rev 10 → Rev 16
/ahdl/run_ahdl.tcl
0,0 → 1,87
# |
# AHDL regression script. |
# |
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# ROOT/TC folders, etc: |
# |
set ROOT [pwd] |
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set FAIL_MSG "TEST finished with ERR" |
set PASS_MSG "TEST finished successfully" |
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set glbl_log "src/testbench/log/global_tc_summary.log" |
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cd $dsn |
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set glbl_log_file [open $glbl_log w] |
puts $glbl_log_file "Global SP605_LX45T_WISHBONE TC log:" |
close $glbl_log_file |
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# |
# Procedure: |
# |
proc set_and_run {} { |
set StdArithNoWarnings 1 |
set NumericStdNoWarnings 1 |
set BreakOnAssertion 2 |
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run -all |
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quit -sim |
} |
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proc parse_log { filename tc_name } { |
set err_cnt 0 |
set openfile [open $filename r] |
set ret 0 |
while {[gets $openfile buffer] >= 0} { |
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set ret [string first $::PASS_MSG $buffer 1] |
#echo $ret |
if { $ret>0 } { |
incr err_cnt |
} |
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} |
if {$err_cnt>0} {return "$tc_name PASSED"} else {return "$tc_name FAILED"} |
close $openfile |
} |
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proc run_test { tc_name tc_id tc_time } { |
set log_name "src/testbench/log/console_" |
set log_name $log_name$tc_name.log |
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#set log_test "src\\testbench\\log\\file_" |
#set log_test $log_test$tc_name.log |
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transcript to $log_name |
asim -ieee_nowarn -O5 -g test_id=$tc_id +access +r +m+$tc_name stend_sp605_wishbone stend_sp605_wishbone |
#asim -ieee_nowarn -g test_id=$tc_id -g test_log=$log_test +access +r +m+$tc_name stend_sp605_wishbone stend_sp605_wishbone |
run $tc_time |
endsim; |
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set glog_file [open $::glbl_log a] |
puts $glog_file [parse_log $log_name $tc_name ] |
close $glog_file |
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} |
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# |
# Main BODY: |
# |
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# |
# |
cd $dsn |
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# |
# |
onerror {resume} |
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run_test "test_dsc_incorrect" 0 "300 us" |
run_test "test_read_4kB" 1 "300 us" |
run_test "test_adm_read_8kb" 2 "350 us" |
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exit |