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URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

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  • This comparison shows the changes necessary to convert path 
    /pcie_ds_dma/trunk/projects
    from Rev 21 to Rev 29
    ↔ Reverse comparison
  •

Rev 21 → Rev 29

/ambpex5_sx50t_wishbone/src/testbench/test_pkg.vhd
442,8 → 442,11
variable str : line;
 
variable error : integer:=0;
variable dma_complete : integer;
variable dma_complete : integer;
 
variable status : std_logic_vector( 31 downto 0 );
variable reg_block_wr : std_logic_vector( 31 downto 0 );
 
begin
write( str, string'("TEST_ADM_READ_8KB" ));
473,12 → 476,12
 
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
block_write( cmd, ret, 5, 8, x"00000027" ); -- DMA_MODE
block_write( cmd, ret, 5, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
block_write( cmd, ret, 4, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
block_write( cmd, ret, 5, 20, x"00100000" ); -- PCI_ADRL
block_write( cmd, ret, 5, 21, x"00100000" ); -- PCI_ADRH
block_write( cmd, ret, 5, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
490,13 → 493,19
wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
 
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
block_write( cmd, ret, 5, 9, x"00000001" ); -- DMA_CTRL - START
wb_block_gen_read( cmd, ret, REG_TEST_GEN_STATUS, status ); -- read status
write( str, string'("WB_GEN_STATUS: " )); hwrite( str, status( 31 downto 0 ) ); writeline( log, str );
wb_block_gen_read( cmd, ret, REG_TEST_GEN_BL_WR, reg_block_wr ); -- read block_wr
write( str, string'("WB_GEN_BL_WR: " )); hwrite( str, reg_block_wr( 31 downto 0 ) ); writeline( log, str );
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
wait for 20 us;
block_read( cmd, ret, 4, 16, data ); -- STATUS
block_read( cmd, ret, 5, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data( 8 )='1' ) then
514,13 → 523,13
dma_complete := 0;
for ii in 0 to 100 loop
block_read( cmd, ret, 4, 16, data ); -- STATUS
block_read( cmd, ret, 5, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data(5)='1' ) then
write( str, string'(" - DMA finished " ));
dma_complete := 1;
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - reset EOT
block_write( cmd, ret, 5, 16#11#, x"00000010" ); -- FLAG_CLR - reset EOT
end if;
writeline( log, str );
541,11 → 550,17
error:=error+1;
end if;
 
end if;
end if;
wb_block_gen_read( cmd, ret, REG_TEST_GEN_STATUS, status ); -- read status
write( str, string'("WB_GEN_STATUS: " )); hwrite( str, status( 31 downto 0 ) ); writeline( log, str );
wb_block_gen_read( cmd, ret, REG_TEST_GEN_BL_WR, reg_block_wr ); -- read block_wr
write( str, string'("WB_GEN_BL_WR: " )); hwrite( str, reg_block_wr( 31 downto 0 ) ); writeline( log, str );
for ii in 0 to 3 loop
block_read( cmd, ret, 4, 16, data ); -- STATUS
block_read( cmd, ret, 5, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
writeline( log, str );
wait for 500 ns;
553,7 → 568,7
end loop;
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
block_write( cmd, ret, 5, 9, x"00000000" ); -- DMA_CTRL - STOP
write( str, string'(" Block 0 - read: " ));
writeline( log, str );
/ambpex5_sx50t_wishbone/src/testbench/wb_block_pkg.vhd
55,6 → 55,7
constant REG_TEST_GEN_SIZE : integer:=9;
constant REG_TEST_GEN_CNT1 : integer:=16#0A#;
constant REG_TEST_GEN_CNT2 : integer:=16#0B#;
constant REG_TEST_GEN_STATUS : integer:=16#10#;
constant REG_TEST_GEN_BL_WR : integer:=16#11#;
--
-- Define SoPC ADDR (must be EQU to: ...\src\top\sp605_lx45t_wishbone_sopc_wb.vhd)
/ambpex5_sx50t_wishbone/src/testbench/ahdl/run_ahdl.tcl
80,8 → 80,8
#
onerror {resume}
run_test "test_dsc_incorrect" 0 "300 us"
run_test "test_read_4kB" 1 "300 us"
#run_test "test_dsc_incorrect" 0 "300 us"
#run_test "test_read_4kB" 1 "300 us"
run_test "test_adm_read_8kb" 2 "350 us"
 
exit
/ambpex5_sx50t_wishbone/src/top/ambpex5_sx50t_wishbone_sopc_wb.vhd
229,7 → 229,7
(
 
 
 
 
 
)
274,7 → 274,7
);
-- Construct DMAR WB IR Input:
sv_wbm_dmar_irq_pcie_core64_wb <= s_wbs_irq_dmar_test_check & s_wbs_irq_dmar_test_gen; -- Bit#1 - TEST_CHECK, Bit#0 - TEST_GEN
sv_wbm_dmar_irq_pcie_core64_wb <= s_wbs_irq_dmar_test_gen & s_wbs_irq_dmar_test_check; -- Bit#1 - TEST_GEN, Bit#0 - TEST_CHECK
-------------------------------------------------------------------------------
--
-- Instantiate TEST_CHECK (provide check of input data):

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