URL
https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk
Subversion Repositories pcie_ds_dma
Compare Revisions
- This comparison shows the changes necessary to convert path
/pcie_ds_dma/trunk/soft/linux/application/wb_test/src
- from Rev 19 to Rev 6
- ↔ Reverse comparison
Rev 19 → Rev 6
/work/wb_teststrm.h
173,7 → 173,7
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bool isFirstCallStep; |
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void PrepareWb( void ); |
void PrepareAdm( void ); |
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void PrepareAdmReg( char* fname ); |
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/work/main.cpp
59,23 → 59,13
//#include "tf_teststrm.h" |
//#include "tf_teststrmout.h" |
//#include "useful.h" |
#include "wb_teststrm.h" |
#include "wb_teststrmout.h" |
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CL_WBPEX g_Board; |
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U32 isTwoTest=0; |
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static volatile int exit_flag = 0; |
void ShowPldInfo( CL_WBPEX *pBrd ); |
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void signa_handler(int signo) |
{ |
exit_flag = 1; |
} |
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void ShowWishboneInfo( CL_WBPEX *pBrd ); |
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// |
//=== Console |
// |
87,8 → 77,8
// анализ командной строки |
setlocale( LC_ALL, "Russian" ); |
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TF_Test *pTest=NULL; |
TF_Test *pTest2=NULL; |
//TF_Test *pTest=NULL; |
//TF_Test *pTest2=NULL; |
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BRDCHAR* fname = argv[1]; |
BRDCHAR* fname2=NULL; |
103,7 → 93,7
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//printf( "Файл инициализации: %s\n", fname ); |
try |
// try |
{ |
CL_WBPEX *pBrd = &g_Board; |
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111,7 → 101,7
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if( 0==ret ) |
{ |
BRDC_fprintf( stderr, _BRDC("Board PEXDRV open succesfully\n") ); |
BRDC_fprintf( stderr, _BRDC("Модуль AMBPEX открыт успешно\n") ); |
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/* |
128,21 → 118,21
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} else |
{ |
BRDC_fprintf( stderr, _BRDC("Error during open PEXDRV: ret=0x%.8X\n"), ret ); |
BRDC_fprintf( stderr, _BRDC("Ошибка при открытии модуля AMBPEX: ret=0x%.8X\n"), ret ); |
//getch(); |
exit(-1); |
} |
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//printf( "\nShowPldInfo\n" ); |
ShowWishboneInfo( pBrd ); |
//} |
printf( "\nShowPldInfo\n" ); |
ShowPldInfo( pBrd ); |
} |
} |
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//#if 0 |
#if 0 |
if( fname[0]=='o' ) |
pTest = new WB_TestStrmOut( fname, pBrd ); |
pTest = new TF_TestStrmOut( fname, &g_AMBPEX ); |
else |
pTest = new WB_TestStrm( fname, pBrd ); |
pTest = new TF_TestStrm( fname, &g_AMBPEX ); |
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Sleep( 10 ); |
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150,9 → 140,9
{ |
isTwoTest=1; |
if( fname2[0]=='o' ) |
pTest2 = new WB_TestStrmOut( fname2, pBrd ); |
pTest2 = new TF_TestStrmOut( fname2, &g_AMBPEX ); |
else |
pTest2 = new WB_TestStrm( fname2, pBrd ); |
pTest2 = new TF_TestStrm( fname2, &g_AMBPEX ); |
} |
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pTest->Prepare(); |
167,46 → 157,60
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//int key; |
int isFirstCallStep=1; |
int isStopped = 0; |
for( ; ; ) |
{ |
if( kbhit() ) |
{ |
int key=getch(); |
if( key==0x1B ) |
{ |
|
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if( exit_flag ) |
{ |
if(!isStopped) { |
pTest->Stop(); |
if( pTest2 ) { |
if( pTest2 ) |
pTest2->Stop(); |
} |
BRDC_fprintf( stderr, _BRDC("\n\nCancel\n") ); |
isStopped = 1; |
BRDC_fprintf( stderr, _BRDC("\n\nОтмена\n") ); |
} |
} |
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if( exit_flag ) |
{ |
if(isStopped) { |
if( key=='i' ) |
{ |
pBrd->RegPokeInd( 4, TRDIND_DELAY_CTRL, 0x12 ); |
pBrd->RegPokeInd( 4, TRDIND_DELAY_CTRL, 0x10 ); |
g_DelayCnt--; BRDC_fprintf( stderr, "\n\ng_DelayCnt = %d ", g_DelayCnt ); |
} |
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if( pTest->isComplete() ) { |
if( key=='o' ) |
{ |
pBrd->RegPokeInd( 4, TRDIND_DELAY_CTRL, 0x13 ); |
pBrd->RegPokeInd( 4, TRDIND_DELAY_CTRL, 0x11 ); |
g_DelayCnt++; BRDC_fprintf( stderr, "\n\ng_DelayCnt = %d ", g_DelayCnt ); |
} |
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if( pTest2 ) { |
if( pTest2->isComplete() ) |
break; |
} else { |
break; |
} |
} |
} |
ret=pTest->isComplete(); |
if( ret ) |
{ |
if( pTest2 ) |
{ |
ret=pTest2->isComplete(); |
if( ret ) |
break; |
} else |
{ |
break; |
} |
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} |
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//SetConsoleCursorPosition(hConsoleOut, rCursorPosition); |
if( isFirstCallStep || isTwoTest ) |
{ |
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BRDC_fprintf( stdout, _BRDC("%10s %10s %10s %10s %10s %10s %10s %10s\n"), _BRDC(""), _BRDC("BLOCK_WR"), _BRDC("BLOCK_RD"), _BRDC("BLOCK_OK"), _BRDC("BLOCK_ERR"), _BRDC("SPD_CURR"), _BRDC("SPD_AVR"), _BRDC("STATUS")); |
BRDC_fprintf( stdout, _BRDC("\n")); |
BRDC_fprintf( stderr, _BRDC("%10s %10s %10s %10s %10s %10s %10s %10s\n"), _BRDC(""), _BRDC("BLOCK_WR"), _BRDC("BLOCK_RD"), _BRDC("BLOCK_OK"), _BRDC("BLOCK_ERR"), _BRDC("SPD_CURR"), _BRDC("SPD_AVR"), _BRDC("STATUS")); |
BRDC_fprintf( stderr, _BRDC("\n")); |
} |
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if (isFirstCallStep) |
255,12 → 259,11
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//} |
return 0; |
//#endif |
} |
#endif |
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void ShowWishboneInfo( CL_WBPEX *pBrd ) |
void ShowPldInfo( CL_WBPEX *pBrd ) |
{ |
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270,7 → 273,7
U32 block_ver_major, block_ver_minor; |
const char *str; |
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BRDC_fprintf( stderr, _BRDC("FPGA WB\r\n") ); |
BRDC_fprintf( stderr, _BRDC("Прошивка ПЛИС WB\r\n") ); |
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/* |
294,7 → 297,7
d=pBrd->RegPeekInd( 0, 0x114 ); BRDC_fprintf( stderr, " Номер сборки прошивки ПЛИС: 0x%.4X\n", d ); |
*/ |
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BRDC_fprintf( stderr, "\nWB block info:\n\n" ); |
BRDC_fprintf( stderr, "\nИнформация о блоках управления:\n\n" ); |
for( ii=0; ii<2; ii++ ) { |
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d= pBrd->wb_block_read( ii, 0 ); |
317,11 → 320,9
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default: str="UNKNOW "; break; |
} |
//BRDC_fprintf( stderr, " %d 0x%.8X 0x%.8X \n", ii, d, d1 ); |
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BRDC_fprintf( stderr, " %d 0x%.4X %s ", ii, block_id, str ); |
if( block_id>0 ) { |
BRDC_fprintf( stderr, " MOD: %-2d VER: %d.%d \n", block_id_mod, block_ver_major, block_ver_minor ); |
BRDC_fprintf( stderr, " MOD: %-2d VER: %d.%d ", block_id_mod, block_ver_major, block_ver_minor ); |
} else { |
BRDC_fprintf( stderr, "\n" ); |
} |
/work/wb_teststrm.cpp
64,14 → 64,14
{ |
|
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PrepareWb(); |
PrepareAdm(); |
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rd0.trd=trdNo; |
rd0.Strm=strmNo; |
// pBrd->StreamInit( rd0.Strm, CntBuffer, SizeBuferOfBytes, rd0.trd, 1, isCycle, isSystem, isAgreeMode ); |
pBrd->StreamInit( rd0.Strm, CntBuffer, SizeBuferOfBytes, rd0.trd, 1, isCycle, isSystem, isAgreeMode ); |
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bufIsvi = new U32[SizeBlockOfWords*2]; |
pBrd->StreamInit( rd0.Strm, CntBuffer, SizeBuferOfBytes, U32(0x3000),U32(1), 0, 1, U32(0) ); |
//pBrd->StreamInit( strm, CntBuffer, SizeBuferOfBytes, rd0.trd, 1, 0, 0 ); |
} |
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void WB_TestStrm::Start( void ) |
135,13 → 135,11
//BRDC_fprintf( stderr, "%10s %10d %10d %10d %10d\n", "FIFO_1 :", tr1.BlockWr, rd1.BlockRd, rd1.BlockOk, rd1.BlockError ); |
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U32 status = 0; //pBrd->RegPeekDir( rd0.trd, 0 ) & 0xFFFF; |
rd0.BlockWr=pBrd->wb_block_read( 1, 0x11 ); |
BRDC_fprintf( stderr, "%6s %3d %10d %10d %10d %10d %9.1f %10.1f 0x%.4X %d %4d %4f\r", "TRD :", rd0.trd, rd0.BlockWr, rd0.BlockRd, rd0.BlockOk, rd0.BlockError, rd0.VelocityCurrent, rd0.VelocityAvarage, status, IsviStatus, IsviCnt, rd0.fftTime_us ); |
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BRDC_fprintf( stdout, "%6s %3d %10d %10d %10d %10d %9.1f %10.1f 0x%.4X %d %4d %4f\r", "TRD :", rd0.trd, rd0.BlockWr, rd0.BlockRd, rd0.BlockOk, rd0.BlockError, rd0.VelocityCurrent, rd0.VelocityAvarage, status, IsviStatus, IsviCnt, rd0.fftTime_us ); |
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} |
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int WB_TestStrm::isComplete( void ) |
291,24 → 289,6
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pBrd->RegPokeInd( 4, 0, 0x2038 ); |
*/ |
pBrd->StreamStart( rd0.Strm ); |
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U32 val; |
val=pBrd->wb_block_read( 1, 0 ); |
BRDC_fprintf( stderr, "ID=0x%.4X \n", val ); |
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val=pBrd->wb_block_read( 1, 1 ); |
BRDC_fprintf( stderr, "VER=0x%.4X \n", val ); |
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val=pBrd->wb_block_read( 1, 8 ); |
BRDC_fprintf( stderr, "GEN_CTRL=0x%.4X \n", val ); |
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pBrd->wb_block_write( 1, 9, 5 ); |
pBrd->wb_block_write( 1, 8, 0x6A0 ); |
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val=pBrd->wb_block_read( 1, 8 ); |
BRDC_fprintf( stderr, "GEN_CTRL=0x%.4X \n", val ); |
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rd0.time_last=rd0.time_start=0 ;//GetTickCount(); |
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354,7 → 334,6
for( kk=0; kk<16; kk++ ) |
{ |
ret=pBrd->StreamGetBuf( pr->Strm, &ptr ); |
//ret=0; |
if( ret ) |
{ // Проверка буфера стрима |
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416,22 → 395,40
} |
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void WB_TestStrm::PrepareWb( void ) |
void WB_TestStrm::PrepareAdm( void ) |
{ |
/* |
U32 trd=trdNo; |
U32 id, id_mod, ver; |
BRDC_fprintf( stderr, "\nПодготовка тетрады\n" ); |
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BRDC_fprintf( stderr, "\nPrepare TEST_GENERATE\n" ); |
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id = pBrd->RegPeekInd( trd, 0x100 ); |
id_mod = pBrd->RegPeekInd( trd, 0x101 ); |
ver = pBrd->RegPeekInd( trd, 0x102 ); |
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//pBrd->RegPokeInd( trd, 0, 0x2038 ); |
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BRDC_fprintf( stderr, "\nТетрада %d ID: 0x%.2X MOD: %d VER: %d.%d \n\n", |
trd, id, id_mod, (ver>>8) & 0xFF, ver&0xFF ); |
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//if( fnameDDS ) |
// PrepareDDS(); |
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if( isMainTest ) |
PrepareMain(); |
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BlockMode = DataType <<8; |
BlockMode |= DataFix <<7; |
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//if( isTestCtrl ) |
{ |
pBrd->wb_block_write( 1, 9, 1 ); |
pBrd->wb_block_write( 1, 9, BlockMode ); |
} |
if( isTestCtrl ) |
PrepareTestCtrl(); |
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if( isAdmReg ) |
PrepareAdmReg( fnameAdmReg ); |
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IsviStatus=0; |
443,6 → 440,7
isIsvi=1; |
} |
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*/ |
} |
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