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URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /pcie_ds_dma/trunk/soft/linux
    from Rev 9 to Rev 19
    ↔ Reverse comparison
  •

Rev 9 → Rev 19

/application/wb_test/src/work/wb_teststrm.h
173,7 → 173,7
 
bool isFirstCallStep;
 
void PrepareAdm( void );
void PrepareWb( void );
 
void PrepareAdmReg( char* fname );
 
/application/wb_test/src/work/main.cpp
59,13 → 59,23
//#include "tf_teststrm.h"
//#include "tf_teststrmout.h"
//#include "useful.h"
#include "wb_teststrm.h"
#include "wb_teststrmout.h"
 
CL_WBPEX g_Board;
 
U32 isTwoTest=0;
 
void ShowPldInfo( CL_WBPEX *pBrd );
static volatile int exit_flag = 0;
 
void signa_handler(int signo)
{
exit_flag = 1;
}
 
 
void ShowWishboneInfo( CL_WBPEX *pBrd );
 
//
//=== Console
//
77,8 → 87,8
// анализ командной строки
setlocale( LC_ALL, "Russian" );
 
//TF_Test *pTest=NULL;
//TF_Test *pTest2=NULL;
TF_Test *pTest=NULL;
TF_Test *pTest2=NULL;
 
BRDCHAR* fname = argv[1];
BRDCHAR* fname2=NULL;
93,7 → 103,7
 
 
//printf( "Файл инициализации: %s\n", fname );
// try
try
{
CL_WBPEX *pBrd = &g_Board;
 
101,7 → 111,7
 
if( 0==ret )
{
BRDC_fprintf( stderr, _BRDC("Модуль AMBPEX открыт успешно\n") );
BRDC_fprintf( stderr, _BRDC("Board PEXDRV open succesfully\n") );
 
 
/*
118,21 → 128,21
 
} else
{
BRDC_fprintf( stderr, _BRDC("Ошибка при открытии модуля AMBPEX: ret=0x%.8X\n"), ret );
BRDC_fprintf( stderr, _BRDC("Error during open PEXDRV: ret=0x%.8X\n"), ret );
//getch();
exit(-1);
}
 
printf( "\nShowPldInfo\n" );
ShowPldInfo( pBrd );
}
}
//printf( "\nShowPldInfo\n" );
ShowWishboneInfo( pBrd );
//}
 
#if 0
 
//#if 0
if( fname[0]=='o' )
pTest = new TF_TestStrmOut( fname, &g_AMBPEX );
pTest = new WB_TestStrmOut( fname, pBrd );
else
pTest = new TF_TestStrm( fname, &g_AMBPEX );
pTest = new WB_TestStrm( fname, pBrd );
 
Sleep( 10 );
 
140,9 → 150,9
{
isTwoTest=1;
if( fname2[0]=='o' )
pTest2 = new TF_TestStrmOut( fname2, &g_AMBPEX );
pTest2 = new WB_TestStrmOut( fname2, pBrd );
else
pTest2 = new TF_TestStrm( fname2, &g_AMBPEX );
pTest2 = new WB_TestStrm( fname2, pBrd );
}
 
pTest->Prepare();
157,60 → 167,46
 
//int key;
int isFirstCallStep=1;
int isStopped = 0;
for( ; ; )
{
if( kbhit() )
{
int key=getch();
if( key==0x1B )
{
 
 
if( exit_flag )
{
if(!isStopped) {
pTest->Stop();
if( pTest2 )
if( pTest2 ) {
pTest2->Stop();
BRDC_fprintf( stderr, _BRDC("\n\nОтмена\n") );
}
BRDC_fprintf( stderr, _BRDC("\n\nCancel\n") );
isStopped = 1;
}
}
 
if( key=='i' )
{
pBrd->RegPokeInd( 4, TRDIND_DELAY_CTRL, 0x12 );
pBrd->RegPokeInd( 4, TRDIND_DELAY_CTRL, 0x10 );
g_DelayCnt--; BRDC_fprintf( stderr, "\n\ng_DelayCnt = %d ", g_DelayCnt );
}
if( exit_flag )
{
if(isStopped) {
 
if( key=='o' )
{
pBrd->RegPokeInd( 4, TRDIND_DELAY_CTRL, 0x13 );
pBrd->RegPokeInd( 4, TRDIND_DELAY_CTRL, 0x11 );
g_DelayCnt++; BRDC_fprintf( stderr, "\n\ng_DelayCnt = %d ", g_DelayCnt );
}
if( pTest->isComplete() ) {
 
}
ret=pTest->isComplete();
if( ret )
{
if( pTest2 )
{
ret=pTest2->isComplete();
if( ret )
break;
} else
{
break;
if( pTest2 ) {
if( pTest2->isComplete() )
break;
} else {
break;
}
}
}
 
}
 
 
 
 
//SetConsoleCursorPosition(hConsoleOut, rCursorPosition);
if( isFirstCallStep || isTwoTest )
{
 
BRDC_fprintf( stderr, _BRDC("%10s %10s %10s %10s %10s %10s %10s %10s\n"), _BRDC(""), _BRDC("BLOCK_WR"), _BRDC("BLOCK_RD"), _BRDC("BLOCK_OK"), _BRDC("BLOCK_ERR"), _BRDC("SPD_CURR"), _BRDC("SPD_AVR"), _BRDC("STATUS"));
BRDC_fprintf( stderr, _BRDC("\n"));
BRDC_fprintf( stdout, _BRDC("%10s %10s %10s %10s %10s %10s %10s %10s\n"), _BRDC(""), _BRDC("BLOCK_WR"), _BRDC("BLOCK_RD"), _BRDC("BLOCK_OK"), _BRDC("BLOCK_ERR"), _BRDC("SPD_CURR"), _BRDC("SPD_AVR"), _BRDC("STATUS"));
BRDC_fprintf( stdout, _BRDC("\n"));
}
 
if (isFirstCallStep)
259,11 → 255,12
 
//}
return 0;
#endif
//#endif
}
 
 
 
void ShowPldInfo( CL_WBPEX *pBrd )
void ShowWishboneInfo( CL_WBPEX *pBrd )
{
 
 
273,7 → 270,7
U32 block_ver_major, block_ver_minor;
const char *str;
 
BRDC_fprintf( stderr, _BRDC("Прошивка ПЛИС WB\r\n") );
BRDC_fprintf( stderr, _BRDC("FPGA WB\r\n") );
 
 
/*
297,7 → 294,7
d=pBrd->RegPeekInd( 0, 0x114 ); BRDC_fprintf( stderr, " Номер сборки прошивки ПЛИС: 0x%.4X\n", d );
*/
 
BRDC_fprintf( stderr, "\nИнформация о блоках управления:\n\n" );
BRDC_fprintf( stderr, "\nWB block info:\n\n" );
for( ii=0; ii<2; ii++ ) {
 
d= pBrd->wb_block_read( ii, 0 );
320,9 → 317,11
 
default: str="UNKNOW "; break;
}
//BRDC_fprintf( stderr, " %d 0x%.8X 0x%.8X \n", ii, d, d1 );
BRDC_fprintf( stderr, " %d 0x%.4X %s ", ii, block_id, str );
if( block_id>0 ) {
BRDC_fprintf( stderr, " MOD: %-2d VER: %d.%d ", block_id_mod, block_ver_major, block_ver_minor );
BRDC_fprintf( stderr, " MOD: %-2d VER: %d.%d \n", block_id_mod, block_ver_major, block_ver_minor );
} else {
BRDC_fprintf( stderr, "\n" );
}
/application/wb_test/src/work/wb_teststrm.cpp
64,14 → 64,14
{
 
 
PrepareAdm();
PrepareWb();
 
rd0.trd=trdNo;
rd0.Strm=strmNo;
pBrd->StreamInit( rd0.Strm, CntBuffer, SizeBuferOfBytes, rd0.trd, 1, isCycle, isSystem, isAgreeMode );
// pBrd->StreamInit( rd0.Strm, CntBuffer, SizeBuferOfBytes, rd0.trd, 1, isCycle, isSystem, isAgreeMode );
 
bufIsvi = new U32[SizeBlockOfWords*2];
//pBrd->StreamInit( strm, CntBuffer, SizeBuferOfBytes, rd0.trd, 1, 0, 0 );
pBrd->StreamInit( rd0.Strm, CntBuffer, SizeBuferOfBytes, U32(0x3000),U32(1), 0, 1, U32(0) );
}
 
void WB_TestStrm::Start( void )
135,11 → 135,13
//BRDC_fprintf( stderr, "%10s %10d %10d %10d %10d\n", "FIFO_1 :", tr1.BlockWr, rd1.BlockRd, rd1.BlockOk, rd1.BlockError );
 
U32 status = 0; //pBrd->RegPeekDir( rd0.trd, 0 ) & 0xFFFF;
BRDC_fprintf( stderr, "%6s %3d %10d %10d %10d %10d %9.1f %10.1f 0x%.4X %d %4d %4f\r", "TRD :", rd0.trd, rd0.BlockWr, rd0.BlockRd, rd0.BlockOk, rd0.BlockError, rd0.VelocityCurrent, rd0.VelocityAvarage, status, IsviStatus, IsviCnt, rd0.fftTime_us );
rd0.BlockWr=pBrd->wb_block_read( 1, 0x11 );
 
BRDC_fprintf( stdout, "%6s %3d %10d %10d %10d %10d %9.1f %10.1f 0x%.4X %d %4d %4f\r", "TRD :", rd0.trd, rd0.BlockWr, rd0.BlockRd, rd0.BlockOk, rd0.BlockError, rd0.VelocityCurrent, rd0.VelocityAvarage, status, IsviStatus, IsviCnt, rd0.fftTime_us );
 
 
 
 
}
 
int WB_TestStrm::isComplete( void )
289,6 → 291,24
 
pBrd->RegPokeInd( 4, 0, 0x2038 );
*/
pBrd->StreamStart( rd0.Strm );
 
U32 val;
val=pBrd->wb_block_read( 1, 0 );
BRDC_fprintf( stderr, "ID=0x%.4X \n", val );
 
val=pBrd->wb_block_read( 1, 1 );
BRDC_fprintf( stderr, "VER=0x%.4X \n", val );
 
val=pBrd->wb_block_read( 1, 8 );
BRDC_fprintf( stderr, "GEN_CTRL=0x%.4X \n", val );
 
pBrd->wb_block_write( 1, 9, 5 );
pBrd->wb_block_write( 1, 8, 0x6A0 );
 
val=pBrd->wb_block_read( 1, 8 );
BRDC_fprintf( stderr, "GEN_CTRL=0x%.4X \n", val );
 
rd0.time_last=rd0.time_start=0 ;//GetTickCount();
 
 
334,6 → 354,7
for( kk=0; kk<16; kk++ )
{
ret=pBrd->StreamGetBuf( pr->Strm, &ptr );
//ret=0;
if( ret )
{ // Проверка буфера стрима
 
395,40 → 416,22
}
 
 
void WB_TestStrm::PrepareAdm( void )
void WB_TestStrm::PrepareWb( void )
{
/*
U32 trd=trdNo;
U32 id, id_mod, ver;
BRDC_fprintf( stderr, "\nПодготовка тетрады\n" );
 
BRDC_fprintf( stderr, "\nPrepare TEST_GENERATE\n" );
 
id = pBrd->RegPeekInd( trd, 0x100 );
id_mod = pBrd->RegPeekInd( trd, 0x101 );
ver = pBrd->RegPeekInd( trd, 0x102 );
 
//pBrd->RegPokeInd( trd, 0, 0x2038 );
 
BRDC_fprintf( stderr, "\nТетрада %d ID: 0x%.2X MOD: %d VER: %d.%d \n\n",
trd, id, id_mod, (ver>>8) & 0xFF, ver&0xFF );
 
 
//if( fnameDDS )
// PrepareDDS();
 
 
if( isMainTest )
PrepareMain();
 
 
BlockMode = DataType <<8;
BlockMode |= DataFix <<7;
 
if( isTestCtrl )
PrepareTestCtrl();
//if( isTestCtrl )
{
pBrd->wb_block_write( 1, 9, 1 );
pBrd->wb_block_write( 1, 9, BlockMode );
}
 
if( isAdmReg )
PrepareAdmReg( fnameAdmReg );
 
 
IsviStatus=0;
440,7 → 443,6
isIsvi=1;
}
 
*/
}
 
 
/common/utils/cl_wbpex.cpp File deleted
/common/utils/cl_wbpex.h
4,9 → 4,9
#define TF_CheckItem_CL_WBPEXH
 
#include "utypes.h"
//#include "brd.h"
//#include "time.h"
//#include "ctrlstrm.h"
#include "board.h"
#include "time.h"
#include "ctrlstrm.h"
 
//#include <string.h>
 
25,7 → 25,7
virtual void cleanup( void );
 
 
int StreamInit( U32 strm, U32 cnt_buf, U32 size_one_buf_of_bytes, U32 wb_adr, U32 dir, U32 cycle, U32 system, U32 agree_mode );
int StreamInit( U32 strm, U32 cnt_buf, U32 size_one_buf_of_bytes, U32 loc_wb_adr, U32 dir, U32 cycle, U32 system, U32 agree_mode );
 
void StreamDestroy( U32 strm );
 
68,7 → 68,7
U32 strm;
U32 cnt_buf;
U32 size_one_buf_of_bytes;
U32 trd;
U32 loc_wb_adr;
U32 cycle;
U32 system;
U32 dir;
78,7 → 78,7
U32 agree_mode;
 
//BRD_Handle hStream;
//BRDstrm_Stub *pStub;
BRDstrm_Stub *pStub;
U08 *pBlk[256]; //!< Массив указателей на блоки памяти
 
StreamParam()
/common/utils/tf_workparam.cpp
134,7 → 134,7
if( ps!=NULL )
free( ps );
ps = (char*)malloc( 128 );
*(cfg->ptr)=(U32)ps;
//*(cfg->ptr)=(U32)ps;
sprintf( ps, "%s", val );
 
}
171,7 → 171,7
int total=0;
U32 ii;
STR_CFG *cfg;
 
/*
*((U32*)ptr)=max_item;
total=4;
 
209,6 → 209,7
total+=len;
}
}
*/
return total;
}
 
221,7 → 222,7
n=*((U32*)ptr);
U32 ii;
int total=4;
 
/*
for( ii=0; ii<n; ii++ )
{
src=ptr+total;
228,7 → 229,7
len=GetParamFromStr( src );
total+=len;
}
 
*/
}
 
 
/common/pex/pex_board.cpp
473,7 → 473,7
 
void pex_board::core_bar1_write( u32 offset, u32 val )
{
bar1[offset] = val;
bar1[2*offset] = val;
}
 
//-----------------------------------------------------------------------------
682,6 → 682,8
 
u32 pex_board::core_start_dma(int DmaChan, int IsCycling)
{
 
fprintf(stderr, "%s(): DmaChan=%d IsCycling=%d \n", __FUNCTION__, DmaChan, IsCycling );
if(m_Descr[DmaChan])
{
AMB_START_DMA_CHANNEL StartDescrip;
688,10 → 690,13
StartDescrip.DmaChanNum = DmaChan;
StartDescrip.IsCycling = IsCycling;
 
fprintf(stderr, "%s(): IOCTL_AMB_START_MEMIO ", __FUNCTION__ );
 
if (ioctl(fd,IOCTL_AMB_START_MEMIO,&StartDescrip) < 0) {
fprintf(stderr, "%s(): Error start DMA\n", __FUNCTION__ );
return -1;
}
fprintf(stderr, " %s - OK \n", __FUNCTION__ );
}
return 0;
}
801,6 → 806,9
DmaParam.DmaChanNum = DmaChan;
DmaParam.Param = addr;
 
fprintf(stderr, "%s(): DmaChan=%d addr=0x%.8X \n", __FUNCTION__, DmaChan, addr );
 
 
if(m_Descr[DmaChan])
{
if (0 > ioctl(fd, IOCTL_AMB_SET_SRC_MEM, &DmaParam)) {
807,6 → 815,16
fprintf(stderr, "%s(): Error set source for DMA\n", __FUNCTION__ );
return -1;
}
 
 
DmaParam.Param = m_Descr[DmaChan]->Direction;
 
if (0 > ioctl(fd, IOCTL_AMB_SET_DIR_MEM, &DmaParam)) {
fprintf(stderr, "%s(): Error set dir for DMA\n", __FUNCTION__ );
return -1;
}
 
 
}
 
return 0;
/driver/pexdrv/ioctlrw.c
291,9 → 291,9
TetrNumber = pKernMemDscr->LocalAddr & 0xff;
Address = AdmNumber*ADM_SIZE + TetrNumber*TETRAD_SIZE + TRDadr_DATA*REG_SIZE;
 
SetDmaLocalAddress(dma, Address);
SetAdmTetr(dma, AdmNumber, TetrNumber);
error = SetDmaMode(brd, i, AdmNumber, TetrNumber);
//SetDmaLocalAddress(dma, Address);
//SetAdmTetr(dma, AdmNumber, TetrNumber);
//error = SetDmaMode(brd, i, AdmNumber, TetrNumber);
 
dbg_msg(dbg_trace, "%s(): 4\n", __FUNCTION__);
 
367,6 → 367,7
AMB_START_DMA_CHANNEL StartDscr;
PAMB_START_DMA_CHANNEL pStartDscr = &StartDscr;
 
printk("<0>ioctl_start_mem: Entered.\n");
down(&brd->m_BoardSem);
 
if( copy_from_user((void *)&StartDscr, (void *)arg, sizeof(AMB_START_DMA_CHANNEL))) {
391,6 → 392,7
Status = HwStartDmaTransfer(brd, pStartDscr->DmaChanNum);
 
up(&brd->m_BoardSem);
printk("<0>ioctl_start_mem: exit Status=0x%.8X \n", Status );
 
return Status;
}
508,7 → 510,7
AMB_SET_DMA_CHANNEL MemDscr;
PAMB_SET_DMA_CHANNEL pMemDscr = &MemDscr;
 
//printk("<0>IoctlSetDirMem: Entered.\n");
printk("<0>IoctlSetDirMem: Entered.\n");
down(&brd->m_BoardSem);
 
// get the user buffer
545,6 → 547,7
AMB_SET_DMA_CHANNEL MemDscr;
PAMB_SET_DMA_CHANNEL pMemDscr = &MemDscr;
 
printk("<0>IoctlSetSrcMem: Entered.\n");
down(&brd->m_BoardSem);
 
// get the user buffer
562,12 → 565,17
}
 
i = pMemDscr->DmaChanNum;
AdmNumber = pMemDscr->Param >> 16;
TetrNumber = pMemDscr->Param & 0xff;
Address = AdmNumber * ADM_SIZE + TetrNumber * TETRAD_SIZE + TRDadr_DATA * REG_SIZE;
//AdmNumber = pMemDscr->Param >> 16;
//TetrNumber = pMemDscr->Param & 0xff;
//Address = AdmNumber * ADM_SIZE + TetrNumber * TETRAD_SIZE + TRDadr_DATA * REG_SIZE;
 
AdmNumber=0;
TetrNumber=0;
Address = pMemDscr->Param;
SetDmaLocalAddress(brd->m_DmaChannel[i], Address);
SetAdmTetr(brd->m_DmaChannel[i], AdmNumber, TetrNumber);
Status = SetDmaMode(brd, i, AdmNumber, TetrNumber);
//Status = SetDmaMode(brd, i, AdmNumber, TetrNumber);
Status=0;
 
up(&brd->m_BoardSem);
 
/driver/pexdrv/dmachan.c
875,7 → 875,7
 
int SetDmaDirection(struct CDmaChannel *dma, u32 DmaDirection)
{
//printk("<0>%s()\n", __FUNCTION__);
printk("<0>%s()\n", __FUNCTION__);
switch(DmaDirection)
{
case 1:
/driver/pexdrv/hardware.c
565,6 → 565,7
ModeExt.AsWhole = ReadOperationWordReg(brd, PEFIFOadr_FIFO_CTRL + FifoAddr);
ModeExt.ByBits.SGModeEnbl = 1;
ModeExt.ByBits.DemandMode = 1;
//ModeExt.ByBits.DemandMode = 0;
ModeExt.ByBits.IntEnbl = 1;
ModeExt.ByBits.Dir = DmaDirection;
WriteOperationWordReg(brd, PEFIFOadr_FIFO_CTRL + FifoAddr, ModeExt.AsWhole);
578,7 → 579,7
 
adm_num = GetAdmNum(brd->m_DmaChannel[NumberOfChannel]);
tetr_num = GetTetrNum(brd->m_DmaChannel[NumberOfChannel]);
Status = DmaEnable(brd, adm_num, tetr_num);
//Status = DmaEnable(brd, adm_num, tetr_num);
 
return Status;
}

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