URL
https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk
Subversion Repositories pcie_ds_dma
Compare Revisions
- This comparison shows the changes necessary to convert path
/pcie_ds_dma/trunk
- from Rev 17 to Rev 18
- ↔ Reverse comparison
Rev 17 → Rev 18
/core/ds_dma64/pcie_src/pcie_core64_m1/pcie_ctrl/core64_pb_disp.vhd
59,7 → 59,9
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|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
library unisim; |
use unisim.vcomponents.all; |
132,6 → 134,9
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signal reg_complete : std_logic; |
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signal timeout_cnt : std_logic_vector( 12 downto 0 ); |
signal slave_timeout : std_logic; |
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attribute tig : string; |
attribute tig of master_adr : signal is ""; |
attribute tig of dmar : signal is ""; |
185,7 → 190,8
fifo_allow_wr <= '0' after 1 ns; |
reg_stb1 <= '0' after 1 ns; |
fifo_data_en <= '0' after 1 ns; |
ext_fifo_disp_back.complete <= '0' after 1 ns; |
ext_fifo_disp_back.complete <= '0' after 1 ns; |
timeout_cnt <= (others=>'0') after 1 ns; |
|
if( reg_req_wr_z='1' or reg_req_rd_z='1' ) then |
stp <= sr1 after 1 ns; |
214,9 → 220,10
-- else |
-- stp <= sr5 after 1 ns; |
-- end if; |
-- end if; |
-- end if; |
timeout_cnt <= timeout_cnt + 1 after 1 ns; |
reg_data_we_set <= pb_slave.stb1 after 1 ns; |
if( pb_slave.complete='1' ) then |
if( pb_slave.complete='1' or slave_timeout='1') then |
stp <= sr5 after 1 ns; |
end if; |
|
249,7 → 256,8
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fifo_allow_wr <= ext_fifo_disp.request_wr and pb_slave.ready after 1 ns; |
fifo_data_en <= '1' after 1 ns; |
if( pb_slave.complete='1' ) then |
timeout_cnt <= timeout_cnt + 1 after 1 ns; |
if( pb_slave.complete='1' or slave_timeout='1' ) then |
ext_fifo_disp_back.complete <= '1' after 1 ns; |
stp <= sf3 after 1 ns; |
end if; |
269,8 → 277,10
end if; |
|
end if; |
end process; |
end process; |
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slave_timeout <= timeout_cnt(12) after 1 ns when rising_edge( clk ); |
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ext_fifo_disp_back.allow_wr <= fifo_allow_wr; |
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pb_slave_stb1_z <= pb_slave.stb1 after 1 ns when rising_edge( aclk ); |
/core/ds_dma64/pcie_src/components/pcie_core/pcie_core64_wishbone_m8.vhd
219,7 → 219,7
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); |
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reset_p <= not reset; |
reset_p <= (not reset) or (not brd_mode(3)); |
reset_p_z1 <= reset_p after 1 ns when rising_edge( clk ); |
reset_p_z2 <= reset_p_z1 after 1 ns when rising_edge( clk ); |
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/core/wishbone/block_test_generate/block_test_generate_wb.vhd
151,7 → 151,7
WB_CFG_SLAVE : block_generate_wb_config_slave |
generic map |
( |
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|
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) |
port map |
/core/wishbone/block_test_check/block_test_check_wb.vhd
149,7 → 149,7
WB_CFG_SLAVE : block_check_wb_config_slave |
generic map |
( |
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) |
port map |
/projects/ambpex5_sx50t_wishbone/src/testbench/test_pkg.vhd
32,49 → 32,54
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--! Initialising |
procedure test_init( |
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fname: in string --! file name for report |
); |
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--! Finished |
procedure test_close; |
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--! Read registers |
procedure test_read_reg ( |
signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
); |
|
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--! Start DMA with incorrect descriptor |
procedure test_dsc_incorrect ( |
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signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
); |
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--! Start DMA for one block 4 kB |
procedure test_read_4kb ( |
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signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
); |
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--! Read block_test_check 8 kB |
procedure test_adm_read_8kb ( |
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signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
); |
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--procedure test_block_main ( |
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-- signal cmd: out bh_cmd; --! command |
-- signal ret: in bh_ret --! answer |
-- ); |
-- |
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--procedure test_adm_read_16kb ( |
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-- signal cmd: out bh_cmd; --! command |
-- signal ret: in bh_ret --! answer |
-- ); |
-- |
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procedure test_adm_write_16kb ( |
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signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
); |
--------------------------------------------------------------------------------------------------- |
-- |
81,22 → 86,22
-- |
-- |
procedure test_num_1( |
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|
signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
); |
procedure test_num_2( |
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signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
); |
-- ==> TEST_CHECK.WB_CFG_SLAVE |
procedure test_wb_1( |
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signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
); |
-- ==> TEST_GEN.WB_CFG_SLAVE |
procedure test_wb_2( |
|
|
signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
); |
end package test_pkg; |
--------------------------------------------------------------------------------------------------- |
151,11 → 156,70
end test_close; |
|
|
--! Read registers |
procedure test_read_reg ( |
signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
) |
is |
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variable adr : std_logic_vector( 31 downto 0 ); |
variable data1 : std_logic_vector( 31 downto 0 ); |
variable data2 : std_logic_vector( 31 downto 0 ); |
variable str : line; |
begin |
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write( str, string'("TEST_READ_REG" )); |
writeline( log, str ); |
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block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE |
wait for 100 ns; |
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--block_read( cmd, ret, 4, 23, x"0000A400" ); -- LOCAL_ADR |
wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data1 ); -- read block id |
wb_block_check_read( cmd, ret, REG_BLOCK_ID, data2 ); -- read block id |
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write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) ); |
writeline( log, str ); |
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write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) ); |
writeline( log, str ); |
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wb_read( cmd, ret, 16#1000#, data1 ); |
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wb_read( cmd, ret, 16#3000#, data1 ); |
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write( str, string'("0x1000: " )); hwrite( str, data1( 15 downto 0 ) ); |
writeline( log, str ); |
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write( str, string'("0x3000: " )); hwrite( str, data2( 15 downto 0 ) ); |
writeline( log, str ); |
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block_write( cmd, ret, 0, 8, x"00000000" ); -- BRD_MODE |
wait for 100 ns; |
block_write( cmd, ret, 0, 8, x"0000000F" ); -- BRD_MODE |
wait for 100 ns; |
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wb_block_gen_read( cmd, ret, REG_BLOCK_ID, data1 ); -- read block id |
wb_block_check_read( cmd, ret, REG_BLOCK_ID, data2 ); -- read block id |
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write( str, string'("BLOCK 0 ID: " )); hwrite( str, data1( 15 downto 0 ) ); |
writeline( log, str ); |
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write( str, string'("BLOCK 1 ID: " )); hwrite( str, data2( 15 downto 0 ) ); |
writeline( log, str ); |
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end test_read_reg; |
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--! Start DMA with incorrect descriptor |
procedure test_dsc_incorrect ( |
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signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
) |
is |
|
209,8 → 273,8
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--! Start DMA for one block 4 kB |
procedure test_read_4kb ( |
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signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
) |
is |
|
361,8 → 425,8
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--! Read block_test_check 8 kB |
procedure test_adm_read_8kb ( |
|
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signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
) |
is |
|
533,8 → 597,8
-- |
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--procedure test_block_main ( |
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-- signal cmd: out bh_cmd; --! command |
-- signal ret: in bh_ret --! answer |
-- ) |
--is |
-- |
618,8 → 682,8
-- |
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--procedure test_adm_read_16kb ( |
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-- signal cmd: out bh_cmd; --! command |
-- signal ret: in bh_ret --! answer |
-- ) |
--is |
-- |
869,8 → 933,8
-- |
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procedure test_adm_write_16kb ( |
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signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
) |
is |
|
1298,8 → 1362,8
-- My procedure for test Updated Design (test_read_4kb like refenernce) |
-- |
procedure test_num_1 ( |
|
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signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
) is |
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variable adr : std_logic_vector( 31 downto 0 ); |
1435,8 → 1499,8
-- |
-- |
procedure test_num_2 ( |
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signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
) is |
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variable adr : std_logic_vector( 31 downto 0 ); |
1586,8 → 1650,8
-- ==> TEST_CHECK.WB_CFG_SLAVE |
-- |
procedure test_wb_1 ( |
|
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signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
) is |
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variable adr : std_logic_vector( 31 downto 0 ); |
1749,8 → 1813,8
-- ==> TEST_GEN.WB_CFG_SLAVE |
-- |
procedure test_wb_2 ( |
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signal cmd: out bh_cmd; --! command |
signal ret: in bh_ret --! answer |
) is |
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variable adr : std_logic_vector( 31 downto 0 ); |
/projects/ambpex5_sx50t_wishbone/src/testbench/wb_block_pkg.vhd
1,168 → 1,205
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : wb_block_pkg.vhd |
-- Author : Dmitry Smekhov |
-- Company : Instrumental Systems |
-- E-mail : dsmv@insys.ru |
-- |
-- Version : 1.0 |
--------------------------------------------------------------------------------------------------- |
-- |
|
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Version 1.0 01.11.2011 |
|
-- |
--------------------------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_unsigned.all; |
|
library work; |
use work.cmd_sim_pkg.all; |
|
use std.textio.all; |
use std.textio; |
|
--------------------------------------------------------------------------------------------------- |
package wb_block_pkg is |
|
-- |
-- Define TEST_CHECK reg id (addr in 64b cells) |
-- |
constant REG_BLOCK_ID : integer:=0; |
constant REG_BLOCK_VER : integer:=1; |
|
constant REG_TEST_CHECK_CTRL : integer:=8; |
constant REG_TEST_CHECK_SIZE : integer:=9; |
constant REG_TEST_CHECK_ERR_ADR : integer:=16#0A#; |
constant REG_TEST_CHECK_WBS_BURST_CTRL : integer:=16#0B#; |
|
constant REG_TEST_CHECK_BL_RD : integer:=16#10#; |
constant REG_TEST_CHECK_BL_OK : integer:=16#11#; |
constant REG_TEST_CHECK_BL_ERROR : integer:=16#12#; |
constant REG_TEST_CHECK_TOTAL_ERROR : integer:=16#13#; |
constant REG_TEST_CHECK_ERR_DATA : integer:=16#14#; |
-- |
-- Define TEST_GEN reg id (addr in 64b cells) |
-- |
constant REG_TEST_GEN_CTRL : integer:=8; |
constant REG_TEST_GEN_SIZE : integer:=9; |
constant REG_TEST_GEN_CNT1 : integer:=16#0A#; |
constant REG_TEST_GEN_CNT2 : integer:=16#0B#; |
constant REG_TEST_GEN_BL_WR : integer:=16#11#; |
-- |
-- Define SoPC ADDR (must be EQU to: ...\src\top\sp605_lx45t_wishbone_sopc_wb.vhd) |
-- |
constant TEST_CHECK_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20000000"; |
constant TEST_CHECK_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20001000"; -- check data: write-only |
constant TEST_GEN_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20002000"; |
constant TEST_GEN_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20003000"; -- generate data: read-only |
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procedure wb_block_check_write ( |
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); |
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procedure wb_block_check_read ( |
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); |
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procedure wb_block_gen_write ( |
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); |
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procedure wb_block_gen_read ( |
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); |
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-- Construct value for REG_TEST_CHECK_WBS_BURST_CTRL |
function wb_block_check_burst_ctrl_build (i_ena : in std_logic; ii_ack_dly : in integer; ii_dly_pos : in integer) return std_logic_vector; |
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end package wb_block_pkg; |
--------------------------------------------------------------------------------------------------- |
package body wb_block_pkg is |
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procedure wb_block_check_write ( |
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) is |
begin |
data_write( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data ); |
end; |
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procedure wb_block_check_read ( |
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) is |
begin |
data_read( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data ); |
end; |
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procedure wb_block_gen_write ( |
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) is |
begin |
data_write( cmd, ret, TEST_GEN_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data ); |
end; |
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procedure wb_block_gen_read ( |
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) is |
begin |
data_read( cmd, ret, TEST_GEN_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data ); |
end; |
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-- Construct value for REG_TEST_CHECK_WBS_BURST_CTRL |
function wb_block_check_burst_ctrl_build (i_ena : in std_logic; ii_ack_dly : in integer; ii_dly_pos : in integer) return std_logic_vector is |
variable iv_ret : std_logic_vector(31 downto 0):=(others => '0'); |
begin |
iv_ret:= x"0000" & i_ena & conv_std_logic_vector( ii_ack_dly, 6) & conv_std_logic_vector( ii_dly_pos, 9); |
return iv_ret; |
end wb_block_check_burst_ctrl_build; |
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end package body wb_block_pkg; |
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--------------------------------------------------------------------------------------------------- |
-- |
-- Title : wb_block_pkg.vhd |
-- Author : Dmitry Smekhov |
-- Company : Instrumental Systems |
-- E-mail : dsmv@insys.ru |
-- |
-- Version : 1.0 |
--------------------------------------------------------------------------------------------------- |
-- |
|
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Version 1.0 01.11.2011 |
|
-- |
--------------------------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_unsigned.all; |
|
library work; |
use work.cmd_sim_pkg.all; |
|
use std.textio.all; |
use std.textio; |
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--------------------------------------------------------------------------------------------------- |
package wb_block_pkg is |
|
-- |
-- Define TEST_CHECK reg id (addr in 64b cells) |
-- |
constant REG_BLOCK_ID : integer:=0; |
constant REG_BLOCK_VER : integer:=1; |
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constant REG_TEST_CHECK_CTRL : integer:=8; |
constant REG_TEST_CHECK_SIZE : integer:=9; |
constant REG_TEST_CHECK_ERR_ADR : integer:=16#0A#; |
constant REG_TEST_CHECK_WBS_BURST_CTRL : integer:=16#0B#; |
|
constant REG_TEST_CHECK_BL_RD : integer:=16#10#; |
constant REG_TEST_CHECK_BL_OK : integer:=16#11#; |
constant REG_TEST_CHECK_BL_ERROR : integer:=16#12#; |
constant REG_TEST_CHECK_TOTAL_ERROR : integer:=16#13#; |
constant REG_TEST_CHECK_ERR_DATA : integer:=16#14#; |
-- |
-- Define TEST_GEN reg id (addr in 64b cells) |
-- |
constant REG_TEST_GEN_CTRL : integer:=8; |
constant REG_TEST_GEN_SIZE : integer:=9; |
constant REG_TEST_GEN_CNT1 : integer:=16#0A#; |
constant REG_TEST_GEN_CNT2 : integer:=16#0B#; |
constant REG_TEST_GEN_BL_WR : integer:=16#11#; |
-- |
-- Define SoPC ADDR (must be EQU to: ...\src\top\sp605_lx45t_wishbone_sopc_wb.vhd) |
-- |
constant TEST_CHECK_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20000000"; |
constant TEST_CHECK_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20001000"; -- check data: write-only |
constant TEST_GEN_WB_CFG_SLAVE : std_logic_vector( 31 downto 0) := x"20002000"; |
constant TEST_GEN_WB_BURST_SLAVE : std_logic_vector( 31 downto 0) := x"20003000"; -- generate data: read-only |
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---- Write to wishbone ---- |
procedure wb_write ( |
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); |
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---- Read from wishbone ---- |
procedure wb_read ( |
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); |
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procedure wb_block_check_write ( |
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); |
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procedure wb_block_check_read ( |
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); |
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procedure wb_block_gen_write ( |
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); |
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procedure wb_block_gen_read ( |
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); |
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-- Construct value for REG_TEST_CHECK_WBS_BURST_CTRL |
function wb_block_check_burst_ctrl_build (i_ena : in std_logic; ii_ack_dly : in integer; ii_dly_pos : in integer) return std_logic_vector; |
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end package wb_block_pkg; |
--------------------------------------------------------------------------------------------------- |
package body wb_block_pkg is |
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---- Write to wishbone ---- |
procedure wb_write ( |
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) is |
begin |
data_write( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(adr, 32), data ); |
end; |
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---- Read from wishbone ---- |
procedure wb_read ( |
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) is |
begin |
data_read( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(adr, 32), data ); |
end; |
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procedure wb_block_check_write ( |
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) is |
begin |
data_write( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data ); |
end; |
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procedure wb_block_check_read ( |
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) is |
begin |
data_read( cmd, ret, TEST_CHECK_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data ); |
end; |
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procedure wb_block_gen_write ( |
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) is |
begin |
data_write( cmd, ret, TEST_GEN_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data ); |
end; |
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procedure wb_block_gen_read ( |
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) is |
begin |
data_read( cmd, ret, TEST_GEN_WB_CFG_SLAVE+conv_std_logic_vector(reg*8+0, 32), data ); |
end; |
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-- Construct value for REG_TEST_CHECK_WBS_BURST_CTRL |
function wb_block_check_burst_ctrl_build (i_ena : in std_logic; ii_ack_dly : in integer; ii_dly_pos : in integer) return std_logic_vector is |
variable iv_ret : std_logic_vector(31 downto 0):=(others => '0'); |
begin |
iv_ret:= x"0000" & i_ena & conv_std_logic_vector( ii_ack_dly, 6) & conv_std_logic_vector( ii_dly_pos, 9); |
return iv_ret; |
end wb_block_check_burst_ctrl_build; |
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end package body wb_block_pkg; |
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/projects/ambpex5_sx50t_wishbone/src/testbench/stend_ambpex5_wishbone.vhd
37,7 → 37,7
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entity stend_ambpex5_wishbone is |
generic( |
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|
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); |
end stend_ambpex5_wishbone; |
185,7 → 185,8
case( test_id ) is |
when 0 => test_dsc_incorrect( cmd, ret ); |
when 1 => test_read_4kb( cmd, ret ); -- was original |
when 2 => test_adm_read_8kb( cmd, ret ); |
when 2 => test_adm_read_8kb( cmd, ret ); |
when 3 => test_read_reg( cmd, ret ); |
--when 3 => test_adm_read_16kb( cmd, ret ); |
--when 4 => test_adm_write_16kb( cmd, ret ); |
--when 5 => test_block_main( cmd, ret ); |
/projects/sp605_lx45t_wishbone/sp605_lx45t_wishbone.aws
7,9 → 7,9
[Settings] |
Active=ambpex5_sx50t_wishbone |
[Expand] |
sp605_lx45t_wishbone=1 |
sp605_lx45t_wishbone=0 |
ambpex5_sx50t_wishbone=1 |
ambpex5_v20_sx50t_core=0 |
ambpex5_v20_sx50t_core=1 |
[Browser] |
sort=order |
mode=none |