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URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

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  • This comparison shows the changes necessary to convert path 
    /pcie_ds_dma/trunk
    from Rev 28 to Rev 29
    ↔ Reverse comparison
  •

Rev 28 → Rev 29

/core/wishbone/block_test_generate/block_generate_wb_config_slave.vhd
36,8 → 36,10
-- ADDR=x70 - RSVD (COMMAND REGs)
-- ADDR=x78 - RSVD (COMMAND REGs)
-- 3) STS REGs, etc:
-- ADDR=x80 - TEST_GEN_BL_WR
-- ADDR=x88 - RSVD (STS REGs, etc)
-- ADDR=x80 - TEST_GEN_STATUS
-- ADDR=x88 - TEST_GEN_BL_WR
-- ADDR=x90 - 0xAAAAAAAA
-- ADDR=x98 - RSVD (STS REGs, etc)
-- ....
-- ADDR=xFF - RSVD (STS REGs, etc)
--
89,7 → 91,8
ov_test_gen_cnt1 : out std_logic_vector( 15 downto 0 );
ov_test_gen_cnt2 : out std_logic_vector( 15 downto 0 );
--
-- STATUS Input
-- STATUS Input
iv_test_gen_status : in std_logic_vector( 31 downto 0 );
iv_test_gen_bl_wr : in std_logic_vector( 31 downto 0 )
);
end component block_generate_wb_config_slave;
139,7 → 142,8
ov_test_gen_cnt1 : out std_logic_vector( 15 downto 0 );
ov_test_gen_cnt2 : out std_logic_vector( 15 downto 0 );
--
-- STATUS Input
-- STATUS Input
iv_test_gen_status : in std_logic_vector( 31 downto 0 );
iv_test_gen_bl_wr : in std_logic_vector( 31 downto 0 )
);
end block_generate_wb_config_slave;
225,21 → 229,37
--
-- WB Read process
--
WB_READ : process (i_clk, i_rst)
begin
if (i_rst='1') then -- RST
ov_wbs_cfg_data <= (others => '0');
elsif (rising_edge(i_clk)) then -- WRK
if (s_wbs_active_rd='1') then
case(iv_wbs_cfg_addr(7 downto 0)) is
-- STS MM region
when x"80" => ov_wbs_cfg_data(31 downto 0) <= iv_test_gen_bl_wr;
-- BL_RAM MM region
when others => ov_wbs_cfg_data(15 downto 0) <= sv_bl_ram_data_out;
end case;
end if;
end if;
end process WB_READ;
--WB_READ : process (i_clk, i_rst)
-- begin
-- if (i_rst='1') then -- RST
-- ov_wbs_cfg_data <= (others => '0');
-- elsif (rising_edge(i_clk)) then -- WRK
-- if (s_wbs_active_rd='1') then
-- case(iv_wbs_cfg_addr(7 downto 0)) is
-- -- STS MM region
-- when x"80" => ov_wbs_cfg_data(31 downto 0) <= iv_test_gen_status;
-- when x"88" => ov_wbs_cfg_data(31 downto 0) <= iv_test_gen_bl_wr;
-- when x"90" | x"98" | x"A0" | x"A" | x"86" | x"87" | x"88"
-- when x"89" | x"8A" | x"8B" | x"8C" | x"8D" | x"8E" | x"8F"
-- -- BL_RAM MM region
-- when others => ov_wbs_cfg_data(15 downto 0) <= sv_bl_ram_data_out;
-- end case;
-- end if;
-- end if;
--end process WB_READ;
 
WB_READ: process( iv_test_gen_status, iv_test_gen_bl_wr, iv_wbs_cfg_addr ) begin
if( iv_wbs_cfg_addr(7)='0' ) then
ov_wbs_cfg_data <= x"000000000000" & sv_bl_ram_data_out;
else
case( iv_wbs_cfg_addr( 6 downto 3 ) ) is
when "0000" => ov_wbs_cfg_data <= x"00000000" & iv_test_gen_status;
when "0001" => ov_wbs_cfg_data <= x"00000000" & iv_test_gen_bl_wr;
when "0010" => ov_wbs_cfg_data <= x"00000000" & x"AAAAAAAA";
when others => ov_wbs_cfg_data <= (others=>'0');
end case;
end if;
end process;
----------------------------------------------------------------------------------
--
-- WB ACK process
/core/wishbone/block_test_generate/block_test_generate_wb.vhd
141,7 → 141,10
signal s_test_gen_fifo_rd : std_logic;
signal s_test_gen_fifo_full : std_logic;
signal s_test_gen_fifo_empty : std_logic;
signal s_test_gen_fifo_prog_full : std_logic;
signal s_test_gen_fifo_prog_full : std_logic;
signal iv_test_gen_status : std_logic_vector( 31 downto 0 );
signal rstp : std_logic;
signal dmar : std_logic;
----------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------
182,7 → 185,8
ov_test_gen_cnt1 => sv_test_gen_cnt1,
ov_test_gen_cnt2 => sv_test_gen_cnt2,
--
-- STATUS Input
-- STATUS Input
iv_test_gen_status => iv_test_gen_status,
iv_test_gen_bl_wr => sv_test_gen_bl_wr
);
----------------------------------------------------------------------------------
222,7 → 226,7
--
-- SYS_CON
clk => i_clk,
rst => i_rst,
rst => rstp,
--
-- DATA_IN
din => sv_di_data,
280,14 → 284,38
-- define TEST_GEN.di_start like TEST_GEN.sv_test_gen_ctrl[1] ( 1-> RSVD )
s_di_start <= sv_test_gen_ctrl(5);
-- define TEST_GEN.di_fifo_rst - it is RST_n signal
s_di_fifo_rst <= not i_rst;
s_di_fifo_rst <= not rstp;
 
rstp <= i_rst or sv_test_gen_ctrl(0) after 1 ns when rising_edge( i_clk );
 
iv_test_gen_status(0) <= '1';
iv_test_gen_status(1) <= '0';
iv_test_gen_status(2) <= s_test_gen_fifo_empty;
iv_test_gen_status(3) <= s_test_gen_fifo_prog_full;
iv_test_gen_status(4) <= s_test_gen_fifo_full;
iv_test_gen_status(5) <= '0';
iv_test_gen_status(6) <= '0';
iv_test_gen_status(7) <= '0';
iv_test_gen_status(8) <= sv_test_gen_ctrl(5);
iv_test_gen_status(9) <= dmar;
iv_test_gen_status(10) <= rstp;
iv_test_gen_status(11) <= '0';
iv_test_gen_status(12) <= '0';
iv_test_gen_status(13) <= '0';
iv_test_gen_status(14) <= '0';
iv_test_gen_status(15) <= '0';
 
iv_test_gen_status( 31 downto 16 ) <= (others=>'0');
 
 
 
----------------------------------------------------------------------------------
--
-- MODULE OUTPUTs routing:
--
-- DMAR WB IRQ deal
 
-- DMAR WB IRQ deal
 
o_wbs_irq_dmar <= dmar;
-- WB IRQ deal
o_wbs_irq_0 <= '0'; -- No EVENTs for now
----------------------------------------------------------------------------------
/projects/ambpex5_sx50t_wishbone/src/testbench/test_pkg.vhd
442,8 → 442,11
variable str : line;
 
variable error : integer:=0;
variable dma_complete : integer;
variable dma_complete : integer;
 
variable status : std_logic_vector( 31 downto 0 );
variable reg_block_wr : std_logic_vector( 31 downto 0 );
 
begin
write( str, string'("TEST_ADM_READ_8KB" ));
473,12 → 476,12
 
block_write( cmd, ret, 4, 8, x"00000027" ); -- DMA_MODE
block_write( cmd, ret, 4, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
block_write( cmd, ret, 5, 8, x"00000027" ); -- DMA_MODE
block_write( cmd, ret, 5, 9, x"00000010" ); -- DMA_CTRL - RESET FIFO
block_write( cmd, ret, 4, 20, x"00100000" ); -- PCI_ADRL
block_write( cmd, ret, 4, 21, x"00100000" ); -- PCI_ADRH
block_write( cmd, ret, 4, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
block_write( cmd, ret, 5, 20, x"00100000" ); -- PCI_ADRL
block_write( cmd, ret, 5, 21, x"00100000" ); -- PCI_ADRH
block_write( cmd, ret, 5, 23, TEST_GEN_WB_BURST_SLAVE ); -- LOCAL_ADR
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"00000001" ); -- reset
490,13 → 493,19
wb_block_gen_write( cmd, ret, REG_TEST_GEN_SIZE, x"00000001" ); -- size of block = 4 kByte
 
block_write( cmd, ret, 4, 9, x"00000001" ); -- DMA_CTRL - START
block_write( cmd, ret, 5, 9, x"00000001" ); -- DMA_CTRL - START
wb_block_gen_read( cmd, ret, REG_TEST_GEN_STATUS, status ); -- read status
write( str, string'("WB_GEN_STATUS: " )); hwrite( str, status( 31 downto 0 ) ); writeline( log, str );
wb_block_gen_read( cmd, ret, REG_TEST_GEN_BL_WR, reg_block_wr ); -- read block_wr
write( str, string'("WB_GEN_BL_WR: " )); hwrite( str, reg_block_wr( 31 downto 0 ) ); writeline( log, str );
wb_block_gen_write( cmd, ret, REG_TEST_GEN_CTRL, x"000006A0" ); -- start test sequence
wait for 20 us;
block_read( cmd, ret, 4, 16, data ); -- STATUS
block_read( cmd, ret, 5, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data( 8 )='1' ) then
514,13 → 523,13
dma_complete := 0;
for ii in 0 to 100 loop
block_read( cmd, ret, 4, 16, data ); -- STATUS
block_read( cmd, ret, 5, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
if( data(5)='1' ) then
write( str, string'(" - DMA finished " ));
dma_complete := 1;
block_write( cmd, ret, 4, 16#11#, x"00000010" ); -- FLAG_CLR - reset EOT
block_write( cmd, ret, 5, 16#11#, x"00000010" ); -- FLAG_CLR - reset EOT
end if;
writeline( log, str );
541,11 → 550,17
error:=error+1;
end if;
 
end if;
end if;
wb_block_gen_read( cmd, ret, REG_TEST_GEN_STATUS, status ); -- read status
write( str, string'("WB_GEN_STATUS: " )); hwrite( str, status( 31 downto 0 ) ); writeline( log, str );
wb_block_gen_read( cmd, ret, REG_TEST_GEN_BL_WR, reg_block_wr ); -- read block_wr
write( str, string'("WB_GEN_BL_WR: " )); hwrite( str, reg_block_wr( 31 downto 0 ) ); writeline( log, str );
for ii in 0 to 3 loop
block_read( cmd, ret, 4, 16, data ); -- STATUS
block_read( cmd, ret, 5, 16, data ); -- STATUS
write( str, string'("STATUS: " )); hwrite( str, data( 15 downto 0 ) );
writeline( log, str );
wait for 500 ns;
553,7 → 568,7
end loop;
block_write( cmd, ret, 4, 9, x"00000000" ); -- DMA_CTRL - STOP
block_write( cmd, ret, 5, 9, x"00000000" ); -- DMA_CTRL - STOP
write( str, string'(" Block 0 - read: " ));
writeline( log, str );
/projects/ambpex5_sx50t_wishbone/src/testbench/wb_block_pkg.vhd
55,6 → 55,7
constant REG_TEST_GEN_SIZE : integer:=9;
constant REG_TEST_GEN_CNT1 : integer:=16#0A#;
constant REG_TEST_GEN_CNT2 : integer:=16#0B#;
constant REG_TEST_GEN_STATUS : integer:=16#10#;
constant REG_TEST_GEN_BL_WR : integer:=16#11#;
--
-- Define SoPC ADDR (must be EQU to: ...\src\top\sp605_lx45t_wishbone_sopc_wb.vhd)
/projects/ambpex5_sx50t_wishbone/src/testbench/ahdl/run_ahdl.tcl
80,8 → 80,8
#
onerror {resume}
run_test "test_dsc_incorrect" 0 "300 us"
run_test "test_read_4kB" 1 "300 us"
#run_test "test_dsc_incorrect" 0 "300 us"
#run_test "test_read_4kB" 1 "300 us"
run_test "test_adm_read_8kb" 2 "350 us"
 
exit
/projects/ambpex5_sx50t_wishbone/src/top/ambpex5_sx50t_wishbone_sopc_wb.vhd
229,7 → 229,7
(
 
 
 
 
 
)
274,7 → 274,7
);
-- Construct DMAR WB IR Input:
sv_wbm_dmar_irq_pcie_core64_wb <= s_wbs_irq_dmar_test_check & s_wbs_irq_dmar_test_gen; -- Bit#1 - TEST_CHECK, Bit#0 - TEST_GEN
sv_wbm_dmar_irq_pcie_core64_wb <= s_wbs_irq_dmar_test_gen & s_wbs_irq_dmar_test_check; -- Bit#1 - TEST_GEN, Bit#0 - TEST_CHECK
-------------------------------------------------------------------------------
--
-- Instantiate TEST_CHECK (provide check of input data):

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