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    /pcie_sg_dma/trunk/cores
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Rev 2 → Rev 3

/afifo_8x8.ngc File deleted \ No newline at end of file
/afifo_1024x72.ngc File deleted \ No newline at end of file
/afifo_256x36c_fwft.ngc File deleted \ No newline at end of file
/afifo_256x36.ngc File deleted \ No newline at end of file
/pkt_counter_1024.ngc File deleted \ No newline at end of file
/v5sfifo_15x128.xco
0,0 → 1,81
##############################################################
#
# Xilinx Core Generator version 11.5
# Date: Wed May 19 15:18:27 2010
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc5vlx110t
SET devicefamily = virtex5
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff1136
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 4.4
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=v5sfifo_15x128
CSET data_count=false
CSET data_count_width=4
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_negate_value=3
CSET enable_ecc=false
CSET enable_int_clk=false
CSET fifo_implementation=Common_Clock_Shift_Register
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=12
CSET full_threshold_negate_value=11
CSET input_data_width=128
CSET input_depth=16
CSET output_data_width=128
CSET output_depth=16
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=4
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=4
# END Parameters
GENERATE
# CRC: b514ccec
/eb_fifo_counted.xco
0,0 → 1,81
##############################################################
#
# Xilinx Core Generator version 11.5
# Date: Wed May 19 15:19:37 2010
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc5vlx110t
SET devicefamily = virtex5
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff1136
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 4.4
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=eb_fifo_counted
CSET data_count=false
CSET data_count_width=14
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4096
CSET empty_threshold_negate_value=4097
CSET enable_ecc=false
CSET enable_int_clk=false
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=12287
CSET full_threshold_negate_value=12286
CSET input_data_width=72
CSET input_depth=16384
CSET output_data_width=72
CSET output_depth=16384
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET read_clock_frequency=1
CSET read_data_count=true
CSET read_data_count_width=14
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=14
# END Parameters
GENERATE
# CRC: 9ba94312
/prim_FIFO_plain.xco
0,0 → 1,81
##############################################################
#
# Xilinx Core Generator version 11.5
# Date: Wed May 19 15:17:44 2010
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc5vlx110t
SET devicefamily = virtex5
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff1136
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -1
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 4.4
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=prim_FIFO_plain
CSET data_count=false
CSET data_count_width=9
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=5
CSET empty_threshold_negate_value=6
CSET enable_ecc=false
CSET enable_int_clk=false
CSET fifo_implementation=Independent_Clocks_Builtin_FIFO
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=496
CSET full_threshold_negate_value=495
CSET input_data_width=72
CSET input_depth=512
CSET output_data_width=72
CSET output_depth=512
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET read_clock_frequency=175
CSET read_data_count=false
CSET read_data_count_width=9
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=false
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=175
CSET write_data_count=false
CSET write_data_count_width=9
# END Parameters
GENERATE
# CRC: eccbbd21
/mBuf_128x72.xco
0,0 → 1,81
##############################################################
#
# Xilinx Core Generator version 11.5
# Date: Wed May 19 15:20:14 2010
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc5vlx110t
SET devicefamily = virtex5
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff1136
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -1
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 4.4
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=mBuf_128x72
CSET data_count=false
CSET data_count_width=9
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=1
CSET empty_threshold_negate_value=2
CSET enable_ecc=false
CSET enable_int_clk=false
CSET fifo_implementation=Common_Clock_Builtin_FIFO
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=128
CSET full_threshold_negate_value=127
CSET input_data_width=72
CSET input_depth=512
CSET output_data_width=72
CSET output_depth=512
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=9
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=false
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=9
# END Parameters
GENERATE
# CRC: 863a6167
/v5pcie_ep_blk_plus_4x.xco
0,0 → 1,144
##############################################################
#
# Xilinx Core Generator version 11.5
# Date: Wed May 19 15:23:06 2010
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc5vlx110t
SET devicefamily = virtex5
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff1136
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -1
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Endpoint_Block_Plus_for_PCI_Express family Xilinx,_Inc. 1.9
# END Select
# BEGIN Parameters
CSET acceptable_l0_latency=No_limit
CSET acceptable_l1_latency=No_limit
CSET advanced_flow_control_credit=Header_Credit
CSET aux_max_current=0mA
CSET bar0_64bit=false
CSET bar0_enabled=true
CSET bar0_prefetchable=false
CSET bar0_scale=Kilobytes
CSET bar0_size=64
CSET bar0_type=Memory
CSET bar0_value=FFFF0000
CSET bar1_64bit=false
CSET bar1_enabled=true
CSET bar1_prefetchable=false
CSET bar1_scale=Megabytes
CSET bar1_size=1
CSET bar1_type=Memory
CSET bar1_value=FFF00000
CSET bar2_64bit=false
CSET bar2_enabled=true
CSET bar2_prefetchable=false
CSET bar2_scale=Kilobytes
CSET bar2_size=4
CSET bar2_type=Memory
CSET bar2_value=FFFFF000
CSET bar3_64bit=false
CSET bar3_enabled=false
CSET bar3_prefetchable=false
CSET bar3_scale=Kilobytes
CSET bar3_size=64
CSET bar3_type=IO
CSET bar3_value=00000000
CSET bar4_64bit=false
CSET bar4_enabled=false
CSET bar4_prefetchable=false
CSET bar4_scale=Kilobytes
CSET bar4_size=64
CSET bar4_type=IO
CSET bar4_value=00000000
CSET bar5_enabled=false
CSET bar5_prefetchable=false
CSET bar5_scale=Kilobytes
CSET bar5_size=64
CSET bar5_type=IO
CSET bar5_value=00000000
CSET capabilities_register=0001
CSET capability_version=1
CSET cardbus_cis_pointer=00000000
CSET class_code_base=05
CSET class_code_interface=00
CSET class_code_sub=00
CSET class_code_value=050000
CSET component_name=v5pcie_ep_blk_plus_4x
CSET d0_pme_support=true
CSET d0_power_consumed=0
CSET d0_power_consumed_factor=0
CSET d0_power_dissipated=0
CSET d0_power_dissipated_factor=0
CSET d1_pme_support=false
CSET d1_power_consumed=0
CSET d1_power_consumed_factor=0
CSET d1_power_dissipated=0
CSET d1_power_dissipated_factor=0
CSET d1_support=false
CSET d2_pme_support=false
CSET d2_power_consumed=0
CSET d2_power_consumed_factor=0
CSET d2_power_dissipated=0
CSET d2_power_dissipated_factor=0
CSET d2_support=false
CSET d3_power_consumed=0
CSET d3_power_consumed_factor=0
CSET d3_power_dissipated=0
CSET d3_power_dissipated_factor=0
CSET d3cold_pme_support=false
CSET d3hot_pme_support=false
CSET device_capabilities_register=00000FC2
CSET device_id=0153
CSET device_port_type=PCI_Express_Endpoint_device
CSET device_specific_initialization=false
CSET enable_aspm_l1_support=false
CSET enable_slot_clock_cfg=true
CSET expansion_rom_bar=FFF00001
CSET expansion_rom_enabled=true
CSET expansion_rom_scale=Megabytes
CSET expansion_rom_size=1
CSET force_no_scrambling=false
CSET gt_debug_ports=false
CSET interface_freq=125_default
CSET lane_width=X4
CSET link_capabilities_register=0003F441
CSET max_payload_size=512_bytes
CSET maximum_link_speed=1
CSET maximum_link_width=4
CSET msi=1_vector
CSET reference_freq=100
CSET revision_id=06
CSET subsystem_id=ABB2
CSET subsystem_vendor_id=0084
CSET trim_tlp_digest=true
CSET tx_diff_boost=true
CSET tx_diff_ctrl=800
CSET tx_pre_emphasis=52
CSET vendor_id=10DC
# END Parameters
GENERATE
# CRC: ad3b4333
/bram4096x64.xco
0,0 → 1,77
##############################################################
#
# Xilinx Core Generator version 11.5
# Date: Wed May 19 15:18:09 2010
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc5vlx110t
SET devicefamily = virtex5
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff1136
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -1
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 2.8
# END Select
# BEGIN Parameters
CSET algorithm=Fixed_Primitives
CSET assume_synchronous_clk=false
CSET byte_size=8
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=bram4096x64
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET fill_remaining_memory_locations=false
CSET load_init_file=false
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=READ_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET primitive=2kx9
CSET read_width_a=64
CSET read_width_b=64
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=true
CSET remaining_memory_locations=0
CSET single_bit_ecc=false
CSET use_byte_write_enable=true
CSET use_ramb16bwer_reset_behavior=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_ssra_pin=false
CSET use_ssrb_pin=false
CSET write_depth_a=4096
CSET write_width_a=64
CSET write_width_b=64
# END Parameters
GENERATE
# CRC: 75f39f6f

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