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/branches/Virtex6/ML605/rx_Transact.vhd
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/branches/Virtex6/ML605/rx_dsDMA_Channel.vhd
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Index: branches/Virtex6/ML605/bram_DDRs_Control.vhd
===================================================================
--- branches/Virtex6/ML605/bram_DDRs_Control.vhd (revision 9)
+++ branches/Virtex6/ML605/bram_DDRs_Control.vhd (nonexistent)
@@ -1,1091 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: ZITI
--- Engineer: wgao
---
--- Create Date: 12:29:46 04/15/2008
--- Design Name:
--- Module Name: bram_DDRs_Control - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.abb64Package.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity bram_DDRs_Control is
- Generic (
- C_ASYNFIFO_WIDTH : integer := 72 ;
- P_SIMULATION : boolean := TRUE
- );
- Port (
-
--- -- Pins
--- DDR_CLKn : OUT std_logic;
--- DDR_CLK : OUT std_logic;
--- DDR_CKE : OUT std_logic;
--- DDR_CSn : OUT std_logic;
--- DDR_RASn : OUT std_logic;
--- DDR_CASn : OUT std_logic;
--- DDR_WEn : OUT std_logic;
--- DDR_BankAddr : OUT std_logic_vector(C_DDR_BANK_AWIDTH-1 downto 0);
--- DDR_Addr : OUT std_logic_vector(C_DDR_AWIDTH-1 downto 0);
--- DDR_DM : OUT std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
--- DDR_DQ : INOUT std_logic_vector(C_DDR_DWIDTH-1 downto 0);
--- DDR_DQS : INOUT std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
-
- -- DMA interface
- DDR_wr_sof : IN std_logic;
- DDR_wr_eof : IN std_logic;
- DDR_wr_v : IN std_logic;
- DDR_wr_FA : IN std_logic;
- DDR_wr_Shift : IN std_logic;
- DDR_wr_Mask : IN std_logic_vector(2-1 downto 0);
- DDR_wr_din : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- DDR_wr_full : OUT std_logic;
-
- DDR_rdc_sof : IN std_logic;
- DDR_rdc_eof : IN std_logic;
- DDR_rdc_v : IN std_logic;
- DDR_rdc_FA : IN std_logic;
- DDR_rdc_Shift : IN std_logic;
- DDR_rdc_din : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- DDR_rdc_full : OUT std_logic;
-
--- DDR_rdD_sof : OUT std_logic;
--- DDR_rdD_eof : OUT std_logic;
--- DDR_rdDout_V : OUT std_logic;
--- DDR_rdDout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- DDR payload FIFO Read Port
- DDR_FIFO_RdEn : IN std_logic;
- DDR_FIFO_Empty : OUT std_logic;
- DDR_FIFO_RdQout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- Common interface
- DDR_Ready : OUT std_logic;
- DDR_blinker : OUT std_logic;
- Sim_Zeichen : OUT std_logic;
-
- mem_clk : IN std_logic;
- trn_clk : IN std_logic;
- trn_reset_n : IN std_logic
- );
-end entity bram_DDRs_Control;
-
-
-architecture Behavioral of bram_DDRs_Control is
-
- -- ----------------------------------------------------------------------------
- --
- -- ----------------------------------------------------------------------------
- COMPONENT DDR_ClkGen
- PORT(
- ddr_Clock : OUT std_logic;
- ddr_Clock_n : OUT std_logic;
- ddr_Clock90 : OUT std_logic;
- ddr_Clock90_n : OUT std_logic;
- Clk_ddr_rddata : OUT std_logic;
- Clk_ddr_rddata_n : OUT std_logic;
-
- ddr_DCM_locked : OUT std_logic;
-
- clk_in : IN std_logic;
- trn_reset_n : IN std_logic
- );
- END COMPONENT;
-
-
- -- ----------------------------------------------------------------------------
- --
- -- ----------------------------------------------------------------------------
-
- COMPONENT asyn_rw_FIFO72
--- GENERIC (
--- OUTPUT_REGISTERED : BOOLEAN
--- );
- PORT(
- wClk : IN std_logic;
- wEn : IN std_logic;
- Din : IN std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
- aFull : OUT std_logic;
- Full : OUT std_logic;
-
- rClk : IN std_logic;
- rEn : IN std_logic;
- Qout : OUT std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
- aEmpty : OUT std_logic;
- Empty : OUT std_logic;
-
- Rst : IN std_logic
- );
- END COMPONENT;
-
-
- component v6_prime_FIFO_plain
- port (
- wr_clk : IN std_logic;
- wr_en : IN std_logic;
- din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
- full : OUT std_logic;
- prog_full: OUT std_logic;
- rd_clk : IN std_logic;
- rd_en : IN std_logic;
- dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
- empty : OUT std_logic;
- rst : IN std_logic
- );
- end component;
-
--- component fifo_512x36_v4_2
--- port (
--- wr_clk : IN std_logic;
--- wr_en : IN std_logic;
--- din : IN std_logic_VECTOR(35 downto 0);
--- prog_full : OUT std_logic;
--- full : OUT std_logic;
---
--- rd_clk : IN std_logic;
--- rd_en : IN std_logic;
--- dout : OUT std_logic_VECTOR(35 downto 0);
--- prog_empty : OUT std_logic;
--- empty : OUT std_logic;
---
--- rst : IN std_logic
--- );
--- end component;
-
- component fifo_512x72_v4_4
- port (
- wr_clk : IN std_logic;
- wr_en : IN std_logic;
- din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
- prog_full : OUT std_logic;
- full : OUT std_logic;
-
- rd_clk : IN std_logic;
- rd_en : IN std_logic;
- dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
--- prog_empty : OUT std_logic;
- empty : OUT std_logic;
-
- rst : IN std_logic
- );
- end component;
-
-
- ---- Dual-port block RAM for packets
- --- Core output registered
- --
--- component v5bram4096x32
--- port (
--- clka : IN std_logic;
--- addra : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
--- wea : IN std_logic_vector(0 downto 0);
--- dina : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
--- douta : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
---
--- clkb : IN std_logic;
--- addrb : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
--- web : IN std_logic_vector(0 downto 0);
--- dinb : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
--- doutb : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
--- );
--- end component;
-
- component v6_bram4096x64
- port (
- clka : IN std_logic;
- addra : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
- wea : IN std_logic_vector(7 downto 0);
- dina : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- douta : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- clkb : IN std_logic;
- addrb : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
- web : IN std_logic_vector(7 downto 0);
- dinb : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- doutb : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
- );
- end component;
-
- -- Blinking -_-_-_-_-_-_-_-_-_-_-_-_-_-_-
- COMPONENT DDR_Blink
- PORT(
- DDR_Blinker : OUT std_logic;
-
- DDR_Write : IN std_logic;
- DDR_Read : IN std_logic;
- DDR_Both : IN std_logic;
-
- ddr_Clock : IN std_logic;
- DDr_Rst_n : IN std_logic
- );
- END COMPONENT;
-
- -- ---------------------------------------------------------------------
- signal ddr_DCM_locked : std_logic;
- -- -- ---------------------------------------------------------------------
- signal Rst_i : std_logic;
- -- -- ---------------------------------------------------------------------
- signal DDR_Ready_i : std_logic;
- -- -- ---------------------------------------------------------------------
- signal ddr_Clock : std_logic;
- signal ddr_Clock_n : std_logic;
- signal ddr_Clock90 : std_logic;
- signal ddr_Clock90_n : std_logic;
-
- signal Clk_ddr_rddata : std_logic;
- signal Clk_ddr_rddata_n : std_logic;
-
- -- -- -- Write Pipe Channel
- signal wpipe_wEn : std_logic;
- signal wpipe_Din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
- signal wpipe_aFull : std_logic;
- signal wpipe_Full : std_logic;
- -- Earlier calculate for better timing
- signal DDR_wr_Cross_Row : std_logic;
- signal DDR_wr_din_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal DDR_write_ALC : std_logic_vector(11-1 downto 0);
-
- signal wpipe_rEn : std_logic;
- signal wpipe_Qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
--- signal wpipe_aEmpty : std_logic;
- signal wpipe_Empty : std_logic;
- signal wpipe_Qout_latch : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-
- -- -- -- Read Pipe Command Channel
- signal rpipec_wEn : std_logic;
- signal rpipec_Din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
- signal rpipec_aFull : std_logic;
- signal rpipec_Full : std_logic;
- -- Earlier calculate for better timing
- signal DDR_rd_Cross_Row : std_logic;
- signal DDR_rdc_din_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal DDR_read_ALC : std_logic_vector(11-1 downto 0);
-
- signal rpipec_rEn : std_logic;
- signal rpipec_Qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
--- signal rpipec_aEmpty : std_logic;
- signal rpipec_Empty : std_logic;
-
- -- -- -- Read Pipe Data Channel
- signal rpiped_wEn : std_logic;
- signal rpiped_Din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
- signal rpiped_aFull : std_logic;
- signal rpiped_Full : std_logic;
-
--- signal rpiped_rEn : std_logic;
- signal rpiped_Qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
--- signal rpiped_aEmpty : std_logic;
--- signal rpiped_Empty : std_logic;
-
-
- -- write State machine
- type bram_wrStates is ( wrST_bram_RESET
- , wrST_bram_IDLE
--- , wrST_bram_Address
- , wrST_bram_1st_Data
- , wrST_bram_1st_Data_b2b
- , wrST_bram_more_Data
- , wrST_bram_last_DW
- );
-
- -- State variables
- signal pseudo_DDR_wr_State : bram_wrStates;
-
- -- Block RAM
- signal pRAM_weA : std_logic_vector(7 downto 0);
- signal pRAM_addrA : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
- signal pRAM_dinA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal pRAM_doutA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- signal pRAM_weB : std_logic_vector(7 downto 0);
- signal pRAM_addrB : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
- signal pRAM_dinB : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal pRAM_doutB : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal pRAM_doutB_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal pRAM_doutB_shifted : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- signal wpipe_qout_lo32b : std_logic_vector(33-1 downto 0);
- signal wpipe_QW_Aligned : std_logic;
- signal pRAM_AddrA_Inc : std_logic;
- signal wpipe_read_valid : std_logic;
-
-
- -- read State machine
- type bram_rdStates is ( rdST_bram_RESET
- , rdST_bram_IDLE
- , rdST_bram_b4_LA
- , rdST_bram_LA
--- , rdST_bram_b4_Length
--- , rdST_bram_Length
--- , rdST_bram_b4_Address
--- , rdST_bram_Address
- , rdST_bram_Data
--- , rdST_bram_Data_shift
- );
-
- -- State variables
- signal pseudo_DDR_rd_State : bram_rdStates;
-
- signal rpiped_rd_counter : std_logic_vector(10-1 downto 0);
- signal rpiped_wEn_b3 : std_logic;
- signal rpiped_wEn_b2 : std_logic;
- signal rpiped_wEn_b1 : std_logic;
- signal rpiped_wr_EOF : std_logic;
- signal rpipec_read_valid : std_logic;
- signal rpiped_wr_skew : std_logic;
- signal rpiped_wr_postpone : std_logic;
-
-
-begin
-
-
- Rst_i <= not trn_reset_n;
- DDR_Ready <= DDR_Ready_i;
-
- pRAM_doutB_shifted <= pRAM_doutB_r1(32-1 downto 0) & pRAM_doutB(64-1 downto 32);
-
- -- Delay
- Syn_Shifting_pRAM_doutB:
- process ( trn_clk)
- begin
- if trn_clk'event and trn_clk = '1' then
- pRAM_doutB_r1 <= pRAM_doutB;
- end if;
- end process;
-
- -- -----------------------------------------------
- --
- Syn_DDR_CKE:
- process (trn_clk, Rst_i)
- begin
- if Rst_i = '1' then
- DDR_Ready_i <= '0';
- elsif trn_clk'event and trn_clk = '1' then
- DDR_Ready_i <= '1'; -- ddr_DCM_locked;
- end if;
- end process;
-
- -- ----------------------------------------------------------------------------
- --
- -- ----------------------------------------------------------------------------
--- DDR_Clock_Generator:
--- DDR_ClkGen
--- PORT MAP(
--- ddr_Clock => ddr_Clock , -- OUT std_logic;
--- ddr_Clock_n => ddr_Clock_n , -- OUT std_logic;
--- ddr_Clock90 => ddr_Clock90 , -- OUT std_logic;
--- ddr_Clock90_n => ddr_Clock90_n , -- OUT std_logic;
--- Clk_ddr_rddata => Clk_ddr_rddata , -- OUT std_logic;
--- Clk_ddr_rddata_n => Clk_ddr_rddata_n , -- OUT std_logic;
--- ddr_DCM_locked => ddr_DCM_locked , -- OUT std_logic;
---
--- clk_in => mem_clk , -- IN std_logic;
--- trn_reset_n => trn_reset_n -- IN std_logic
--- );
-
-
- -- ----------------------------------------------------------------------------
- --
- -- ----------------------------------------------------------------------------
--- DDR_pipe_write_fifo:
--- asyn_rw_FIFO
--- GENERIC MAP (
--- OUTPUT_REGISTERED => TRUE
--- )
--- PORT MAP(
--- wClk => trn_clk ,
--- wEn => wpipe_wEn ,
--- Din => wpipe_Din ,
--- aFull => wpipe_aFull ,
--- Full => wpipe_Full ,
---
--- rClk => ddr_Clock , -- ddr_Clock_n ,
--- rEn => wpipe_rEn ,
--- Qout => wpipe_Qout ,
--- aEmpty => wpipe_aEmpty ,
--- Empty => wpipe_Empty ,
---
--- Rst => Rst_i
--- );
-
--- DDR_pipe_write_fifo:
--- asyn_rw_FIFO72
--- PORT MAP(
--- wClk => trn_clk ,
--- wEn => wpipe_wEn ,
--- Din => wpipe_Din ,
--- aFull => wpipe_aFull ,
--- Full => open ,
---
--- rClk => ddr_Clock ,
--- rEn => wpipe_rEn ,
--- Qout => wpipe_Qout ,
--- aEmpty => open ,
--- Empty => wpipe_Empty ,
---
--- Rst => Rst_i
--- );
-
- DDR_pipe_write_fifo:
- v6_prime_FIFO_plain
- PORT MAP(
- wr_clk => trn_clk , -- IN std_logic;
- wr_en => wpipe_wEn , -- IN std_logic;
- din => wpipe_Din , -- IN std_logic_VECTOR(35 downto 0);
- prog_full => wpipe_aFull , -- OUT std_logic;
- full => wpipe_Full , -- OUT std_logic;
-
- rd_clk => trn_clk , -- IN std_logic;
- rd_en => wpipe_rEn , -- IN std_logic;
- dout => wpipe_Qout , -- OUT std_logic_VECTOR(35 downto 0);
- empty => wpipe_Empty , -- OUT std_logic;
-
- rst => Rst_i -- IN std_logic
- );
-
-
- wpipe_wEn <= DDR_wr_v;
- wpipe_Din <= DDR_wr_Mask & DDR_wr_Shift & '0' & DDR_wr_sof & DDR_wr_eof & DDR_wr_Cross_Row & DDR_wr_FA & DDR_wr_din;
- DDR_wr_full <= wpipe_aFull;
- Sim_Zeichen <= wpipe_Empty;
-
-
- Syn_DDR_wrD_Cross_Row:
- process (trn_clk)
- begin
- if trn_clk'event and trn_clk = '1' then
- DDR_wr_din_r1(64-1 downto 10) <= (OTHERS=>'0');
- DDR_wr_din_r1( 9 downto 0) <= DDR_wr_din(9 downto 0) - "100";
- end if;
- end process;
-
- DDR_write_ALC <= (DDR_wr_din_r1(10 downto 2) &"00") + ('0' & DDR_wr_din(9 downto 2) &"00");
- DDR_wr_Cross_Row <= '0'; -- DDR_write_ALC(10);
-
- -- ----------------------------------------------------------------------------
- --
- -- ----------------------------------------------------------------------------
-
--- DDR_pipe_read_C_fifo:
--- asyn_rw_FIFO
--- GENERIC MAP (
--- OUTPUT_REGISTERED => TRUE
--- )
--- PORT MAP(
--- wClk => trn_clk ,
--- wEn => rpipec_wEn ,
--- Din => rpipec_Din ,
--- aFull => rpipec_aFull ,
--- Full => rpipec_Full ,
---
--- rClk => ddr_Clock , -- ddr_Clock_n ,
--- rEn => rpipec_rEn ,
--- Qout => rpipec_Qout ,
--- aEmpty => rpipec_aEmpty ,
--- Empty => rpipec_Empty ,
---
--- Rst => Rst_i
--- );
---
-
--- DDR_pipe_read_C_fifo:
--- asyn_rw_FIFO72
--- PORT MAP(
--- wClk => trn_clk ,
--- wEn => rpipec_wEn ,
--- Din => rpipec_Din ,
--- aFull => rpipec_aFull ,
--- Full => open ,
---
--- rClk => ddr_Clock ,
--- rEn => rpipec_rEn ,
--- Qout => rpipec_Qout ,
--- aEmpty => open ,
--- Empty => rpipec_Empty ,
---
--- Rst => Rst_i
--- );
-
- DDR_pipe_read_C_fifo:
- v6_prime_FIFO_plain
- PORT MAP(
- wr_clk => trn_clk , -- IN std_logic;
- wr_en => rpipec_wEn , -- IN std_logic;
- din => rpipec_Din , -- IN std_logic_VECTOR(35 downto 0);
- prog_full => rpipec_aFull , -- OUT std_logic;
- full => open, --rpipec_Full , -- OUT std_logic;
-
- rd_clk => trn_clk , -- IN std_logic;
- rd_en => rpipec_rEn , -- IN std_logic;
- dout => rpipec_Qout , -- OUT std_logic_VECTOR(35 downto 0);
- empty => rpipec_Empty , -- OUT std_logic;
-
- rst => Rst_i -- IN std_logic
- );
-
-
- rpipec_wEn <= DDR_rdc_v;
- rpipec_Din <= "00" & DDR_rdc_Shift & '0' & DDR_rdc_sof & DDR_rdc_eof & DDR_rd_Cross_Row & DDR_rdc_FA & DDR_rdc_din;
- DDR_rdc_full <= rpipec_aFull;
-
-
- Syn_DDR_rdC_Cross_Row:
- process (trn_clk)
- begin
- if trn_clk'event and trn_clk = '1' then
- DDR_rdc_din_r1(64-1 downto 10) <= (OTHERS=>'0');
- DDR_rdc_din_r1( 9 downto 0) <= DDR_rdc_din(9 downto 0) - "100";
- end if;
- end process;
-
- DDR_read_ALC <= (DDR_rdc_din_r1(10 downto 2) &"00") + ('0' & DDR_rdc_din(9 downto 2) &"00");
- DDR_rd_Cross_Row <= '0'; -- DDR_read_ALC(10);
-
- -- ----------------------------------------------------------------------------
- --
- -- ----------------------------------------------------------------------------
--- DDR_pipe_read_D_fifo:
--- asyn_rw_FIFO
--- GENERIC MAP (
--- OUTPUT_REGISTERED => TRUE
--- )
--- PORT MAP(
--- wClk => ddr_Clock, -- Clk_ddr_rddata , -- ddr_Clock , -- ddr_Clock_n ,
--- wEn => rpiped_wEn ,
--- Din => rpiped_Din ,
--- aFull => rpiped_aFull ,
--- Full => rpiped_Full ,
---
--- rClk => trn_clk ,
--- rEn => DDR_FIFO_RdEn , -- rpiped_rEn ,
--- Qout => rpiped_Qout ,
--- aEmpty => open , -- rpiped_aEmpty ,
--- Empty => DDR_FIFO_Empty , -- rpiped_Empty ,
---
--- Rst => Rst_i
--- );
-
--- DDR_pipe_read_D_fifo:
--- asyn_rw_FIFO72
--- PORT MAP(
--- wClk => ddr_Clock ,
--- wEn => rpiped_wEn ,
--- Din => rpiped_Din ,
--- aFull => rpiped_aFull ,
--- Full => open ,
---
--- rClk => trn_clk ,
--- rEn => DDR_FIFO_RdEn ,
--- Qout => rpiped_Qout ,
--- aEmpty => open ,
--- Empty => DDR_FIFO_Empty ,
---
--- Rst => Rst_i
--- );
-
- DDR_pipe_read_D_fifo:
- v6_prime_FIFO_plain
- PORT MAP(
- wr_clk => trn_clk , -- IN std_logic;
- wr_en => rpiped_wEn , -- IN std_logic;
- din => rpiped_Din , -- IN std_logic_VECTOR(35 downto 0);
- prog_full => rpiped_aFull , -- OUT std_logic;
- full => open, -- rpiped_Full , -- OUT std_logic;
-
- rd_clk => trn_clk , -- IN std_logic;
- rd_en => DDR_FIFO_RdEn , -- IN std_logic;
- dout => rpiped_Qout , -- OUT std_logic_VECTOR(35 downto 0);
- empty => DDR_FIFO_Empty , -- OUT std_logic;
-
- rst => Rst_i -- IN std_logic
- );
-
-
- DDR_FIFO_RdQout <= rpiped_Qout(C_DBUS_WIDTH-1 downto 0);
-
-
-
- -- -------------------------------------------------
- -- pkt_RAM instantiate
- --
- pkt_RAM:
- v6_bram4096x64
- port map (
- clka => trn_clk ,
- addra => pRAM_addrA ,
- wea => pRAM_weA ,
- dina => pRAM_dinA ,
- douta => pRAM_doutA ,
-
- clkb => trn_clk ,
- addrb => pRAM_addrB ,
- web => pRAM_weB ,
- dinb => pRAM_dinB ,
- doutb => pRAM_doutB
- );
-
- pRAM_weB <= X"00";
- pRAM_dinB <= (Others =>'0');
-
-
--- ------------------------------------------------
--- write States synchronous
---
- Syn_Pseudo_DDR_wr_States:
- process ( trn_clk, trn_reset_n)
- begin
- if trn_reset_n = '0' then
- pseudo_DDR_wr_State <= wrST_bram_RESET;
- pRAM_addrA <= (OTHERS=>'1');
- pRAM_weA <= (OTHERS=>'0');
- pRAM_dinA <= (OTHERS=>'0');
- wpipe_qout_lo32b <= (OTHERS=>'0');
- wpipe_QW_Aligned <= '1';
- pRAM_AddrA_Inc <= '1';
-
- elsif trn_clk'event and trn_clk = '1' then
-
- case pseudo_DDR_wr_State is
-
- when wrST_bram_RESET =>
- pseudo_DDR_wr_State <= wrST_bram_IDLE;
- pRAM_addrA <= (OTHERS=>'1');
- wpipe_QW_Aligned <= '1';
- wpipe_qout_lo32b <= (OTHERS=>'0');
- pRAM_weA <= (OTHERS=>'0');
- pRAM_dinA <= (OTHERS=>'0');
- pRAM_AddrA_Inc <= '1';
-
- when wrST_bram_IDLE =>
- pRAM_addrA <= wpipe_Qout(14 downto 3);
- pRAM_AddrA_Inc <= wpipe_Qout(2);
- wpipe_QW_Aligned <= not wpipe_Qout(69);
- wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
- pRAM_weA <= (OTHERS=>'0');
- pRAM_dinA <= pRAM_dinA;
- if wpipe_read_valid = '1' then
- pseudo_DDR_wr_State <= wrST_bram_1st_Data; -- wrST_bram_Address;
- else
- pseudo_DDR_wr_State <= wrST_bram_IDLE;
- end if;
-
-
- when wrST_bram_1st_Data =>
- pRAM_addrA <= pRAM_addrA;
- if wpipe_read_valid = '0' then
- pseudo_DDR_wr_State <= wrST_bram_1st_Data;
- pRAM_weA <= (OTHERS=>'0'); --pRAM_weA;
- pRAM_dinA <= pRAM_dinA;
- elsif wpipe_Qout(66)='1' then -- eof
- if wpipe_QW_Aligned='1' then
- pseudo_DDR_wr_State <= wrST_bram_IDLE;
- pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
- & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
- );
- pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
- elsif wpipe_Qout(70)='1' then -- mask(0)
- pseudo_DDR_wr_State <= wrST_bram_IDLE;
- pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
- & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
- );
- pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
- elsif wpipe_Qout(71)='1' then -- mask(1)
- pseudo_DDR_wr_State <= wrST_bram_IDLE;
- pRAM_weA <= X"F0";
- pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
- else
- pseudo_DDR_wr_State <= wrST_bram_last_DW;
- pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
- & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
- );
- pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
- wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
- end if;
- else
- if wpipe_QW_Aligned='1' then
- pseudo_DDR_wr_State <= wrST_bram_more_Data;
- pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
- & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
- );
- pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
- elsif pRAM_AddrA_Inc='1' then
- pseudo_DDR_wr_State <= wrST_bram_more_Data;
- pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
- & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
- );
- pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
- wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
- else
- pseudo_DDR_wr_State <= wrST_bram_1st_Data;
- pRAM_AddrA_Inc <= '1';
- pRAM_weA <= X"00";
- pRAM_dinA <= pRAM_dinA;
- wpipe_qout_lo32b <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
- end if;
- end if;
-
- when wrST_bram_more_Data =>
- if wpipe_read_valid = '0' then
- pseudo_DDR_wr_State <= wrST_bram_more_Data; -- wrST_bram_1st_Data;
- pRAM_weA <= (OTHERS=>'0'); --pRAM_weA;
- pRAM_addrA <= pRAM_addrA;
- pRAM_dinA <= pRAM_dinA;
- elsif wpipe_Qout(66)='1' then -- eof
- if wpipe_QW_Aligned='1' then
- pseudo_DDR_wr_State <= wrST_bram_IDLE;
- pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
- & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
- );
- pRAM_addrA <= pRAM_addrA + '1';
- pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
- elsif wpipe_Qout(70)='1' then -- mask(0)
- pseudo_DDR_wr_State <= wrST_bram_IDLE;
- pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
- & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
- );
- pRAM_addrA <= pRAM_addrA + '1';
- pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
- else
- pseudo_DDR_wr_State <= wrST_bram_last_DW;
- pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
- & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
- );
- pRAM_addrA <= pRAM_addrA + '1';
- pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
- wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
- end if;
- else
- if wpipe_QW_Aligned='1' then
- pseudo_DDR_wr_State <= wrST_bram_more_Data;
- pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
- & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
- );
- pRAM_addrA <= pRAM_addrA + '1';
- pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
- else
- pseudo_DDR_wr_State <= wrST_bram_more_Data;
- pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
- & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
- );
- pRAM_addrA <= pRAM_addrA + '1';
- pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
- wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
- end if;
- end if;
-
-
- when wrST_bram_last_DW =>
--- pseudo_DDR_wr_State <= wrST_bram_IDLE;
- pRAM_weA <= X"F0";
- pRAM_addrA <= pRAM_addrA + '1';
- pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & X"00000000";
- if wpipe_read_valid = '1' then
- pseudo_DDR_wr_State <= wrST_bram_1st_Data_b2b; -- wrST_bram_Address;
- wpipe_Qout_latch <= wpipe_Qout;
- else
- pseudo_DDR_wr_State <= wrST_bram_IDLE;
- wpipe_Qout_latch <= wpipe_Qout;
- end if;
-
-
- when wrST_bram_1st_Data_b2b =>
- pRAM_addrA <= wpipe_Qout_latch(14 downto 3);
- wpipe_QW_Aligned <= not wpipe_Qout_latch(69);
- if wpipe_read_valid = '0' then
- pseudo_DDR_wr_State <= wrST_bram_1st_Data;
- pRAM_weA <= (OTHERS=>'0'); --pRAM_weA;
- pRAM_dinA <= pRAM_dinA;
- pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
- wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
- elsif wpipe_Qout(66)='1' then -- eof
- if wpipe_Qout_latch(69)='0' then -- wpipe_QW_Aligned
- pseudo_DDR_wr_State <= wrST_bram_IDLE;
- pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
- & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
- );
- pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
- pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
- wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
- elsif wpipe_Qout(70)='1' then -- mask(0)
- pseudo_DDR_wr_State <= wrST_bram_IDLE;
- pRAM_weA <= not ( X"f"
- & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
- );
- pRAM_dinA <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
- pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
- wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
- elsif wpipe_Qout(71)='1' then -- mask(1)
- pseudo_DDR_wr_State <= wrST_bram_IDLE;
- pRAM_weA <= X"F0";
- pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
- pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
- wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
- else
- pseudo_DDR_wr_State <= wrST_bram_last_DW;
- pRAM_weA <= not ( X"f"
- & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
- );
- pRAM_dinA <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
- pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
- wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
- end if;
- else
- if wpipe_Qout_latch(69)='0' then -- wpipe_QW_Aligned
- pseudo_DDR_wr_State <= wrST_bram_more_Data;
- pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
- & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
- );
- pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
- pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
- wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
- elsif wpipe_Qout_latch(2)='1' then -- pRAM_AddrA_Inc
- pseudo_DDR_wr_State <= wrST_bram_more_Data;
- pRAM_weA <= not ( X"f"
- & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
- );
- pRAM_dinA <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
- pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
- wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
- else
- pseudo_DDR_wr_State <= wrST_bram_1st_Data;
- pRAM_AddrA_Inc <= '1';
- pRAM_weA <= X"00";
- pRAM_dinA <= pRAM_dinA;
- wpipe_qout_lo32b <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
- end if;
- end if;
-
-
- when OTHERS =>
- pseudo_DDR_wr_State <= wrST_bram_RESET;
- pRAM_addrA <= (OTHERS=>'1');
- pRAM_weA <= (OTHERS=>'0');
- pRAM_dinA <= (OTHERS=>'0');
- wpipe_qout_lo32b <= (OTHERS=>'0');
- wpipe_QW_Aligned <= '1';
- pRAM_AddrA_Inc <= '1';
-
- end case;
-
- end if;
- end process;
-
-
- --
- Syn_wPipe_read:
- process ( trn_clk, DDR_Ready_i)
- begin
- if DDR_Ready_i = '0' then
- wpipe_rEn <= '0';
- wpipe_read_valid <= '0';
-
- elsif trn_clk'event and trn_clk = '1' then
-
- wpipe_rEn <= '1';
- wpipe_read_valid <= wpipe_rEn and not wpipe_Empty;
-
- end if;
- end process;
-
-
-
- --
- Syn_rPipeC_read:
- process ( trn_clk, DDR_Ready_i)
- begin
- if DDR_Ready_i = '0' then
- rpipec_read_valid <= '0';
- rpiped_wr_postpone <= '0';
- rpiped_wr_skew <= '0';
-
- elsif trn_clk'event and trn_clk = '1' then
-
- rpipec_read_valid <= rpipec_rEn and not rpipec_Empty;
- if rpipec_read_valid='1' then
- rpiped_wr_postpone <= rpipec_Qout(2) and not rpipec_Qout(69);
- rpiped_wr_skew <= rpipec_Qout(69) xor rpipec_Qout(2);
- else
- rpiped_wr_postpone <= rpiped_wr_postpone;
- rpiped_wr_skew <= rpiped_wr_skew;
- end if;
-
- end if;
- end process;
-
--- ------------------------------------------------
--- Read States synchronous
---
- Syn_Pseudo_DDR_rd_States:
- process ( trn_clk, DDR_Ready_i)
- begin
- if DDR_Ready_i = '0' then
- pseudo_DDR_rd_State <= rdST_bram_RESET;
- rpipec_rEn <= '0';
- pRAM_addrB <= (OTHERS=>'1');
- rpiped_rd_counter <= (OTHERS=>'0');
- rpiped_wEn_b3 <= '0';
- rpiped_wr_EOF <= '0';
-
- elsif trn_clk'event and trn_clk = '1' then
-
- case pseudo_DDR_rd_State is
-
- when rdST_bram_RESET =>
- pseudo_DDR_rd_State <= rdST_bram_IDLE;
- rpipec_rEn <= '0';
- pRAM_addrB <= (OTHERS=>'1');
- rpiped_rd_counter <= (OTHERS=>'0');
- rpiped_wEn_b3 <= '0';
- rpiped_wr_EOF <= '0';
-
- when rdST_bram_IDLE =>
- pRAM_addrB <= pRAM_addrB;
- rpiped_rd_counter <= (OTHERS=>'0');
- rpiped_wEn_b3 <= '0';
- rpiped_wr_EOF <= '0';
- if rpipec_Empty = '0' then
- rpipec_rEn <= '1';
- pseudo_DDR_rd_State <= rdST_bram_b4_LA; --rdST_bram_b4_Length;
- else
- rpipec_rEn <= '0';
- pseudo_DDR_rd_State <= rdST_bram_IDLE;
- end if;
-
- when rdST_bram_b4_LA =>
- pRAM_addrB <= pRAM_addrB;
- rpiped_rd_counter <= (OTHERS=>'0');
- rpiped_wEn_b3 <= '0';
- rpiped_wr_EOF <= '0';
- rpipec_rEn <= '0';
- pseudo_DDR_rd_State <= rdST_bram_LA;
-
- when rdST_bram_LA =>
- rpipec_rEn <= '0';
- pRAM_addrB <= rpipec_Qout(14 downto 3);
- rpiped_wr_EOF <= '0';
- rpiped_wEn_b3 <= '0';
- if rpipec_Qout(2+32)='1' then
- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + '1';
- elsif rpipec_Qout(2)='1' and rpipec_Qout(69)='1' then
- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
- elsif rpipec_Qout(2)='0' and rpipec_Qout(69)='1' then
- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
- elsif rpipec_Qout(2)='1' and rpipec_Qout(69)='0' then
- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32);
- else
- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32);
- end if;
-
--- elsif rpipec_Qout(2)='1' then
--- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
--- elsif rpipec_Qout(69)='1' then
--- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
--- else
--- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32);
--- end if;
- pseudo_DDR_rd_State <= rdST_bram_Data;
-
-
- when rdST_bram_Data =>
- rpipec_rEn <= '0';
- if rpiped_rd_counter = CONV_STD_LOGIC_VECTOR(2, 10) then
- pRAM_addrB <= pRAM_addrB + '1';
- rpiped_rd_counter <= rpiped_rd_counter;
- rpiped_wEn_b3 <= '1';
- rpiped_wr_EOF <= '1';
- pseudo_DDR_rd_State <= rdST_bram_IDLE;
- elsif rpiped_aFull = '1' then
- pRAM_addrB <= pRAM_addrB;
- rpiped_rd_counter <= rpiped_rd_counter;
- rpiped_wEn_b3 <= '0';
- rpiped_wr_EOF <= '0';
- pseudo_DDR_rd_State <= rdST_bram_Data;
- else
- pRAM_addrB <= pRAM_addrB + '1';
- rpiped_rd_counter <= rpiped_rd_counter - "10";
- rpiped_wEn_b3 <= '1';
- rpiped_wr_EOF <= '0';
- pseudo_DDR_rd_State <= rdST_bram_Data;
- end if;
-
-
- when OTHERS =>
- rpipec_rEn <= '0';
- pRAM_addrB <= pRAM_addrB;
- rpiped_rd_counter <= rpiped_rd_counter;
- rpiped_wEn_b3 <= '0';
- rpiped_wr_EOF <= '0';
- pseudo_DDR_rd_State <= rdST_bram_RESET;
-
- end case;
-
- end if;
- end process;
-
-
-
- Syn_Pseudo_DDR_rdd_write:
- process ( trn_clk, DDR_Ready_i)
- begin
- if DDR_Ready_i = '0' then
- rpiped_wEn_b1 <= '0';
- rpiped_wEn_b2 <= '0';
- rpiped_wEn <= '0';
- rpiped_Din <= (OTHERS=>'0');
-
- elsif trn_clk'event and trn_clk = '1' then
-
- rpiped_wEn_b2 <= rpiped_wEn_b3;
- rpiped_wEn_b1 <= rpiped_wEn_b2;
- if rpiped_wr_skew='1' then
--- rpiped_wEn <= rpiped_wEn_b2;
- rpiped_wEn <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
- or (rpiped_wEn_b1 and rpiped_wr_postpone);
- rpiped_Din <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB_shifted;
- else
--- rpiped_wEn <= rpiped_wEn_b2;
- rpiped_wEn <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
- or (rpiped_wEn_b1 and rpiped_wr_postpone);
- rpiped_Din <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB;
- end if;
-
- end if;
- end process;
-
-
- --
- DDR_Blinker_Module:
- DDR_Blink
- PORT MAP(
- DDR_Blinker => DDR_Blinker ,
-
- DDR_Write => wpipe_rEn ,
- DDR_Read => rpiped_wEn ,
- DDR_Both => '0' ,
-
- ddr_Clock => trn_clk ,
- DDr_Rst_n => DDR_Ready_i -- DDR_CKE_i
- );
-
-
-end architecture Behavioral;
Index: branches/Virtex6/ML605/Tx_Output_Arbitor.vhd
===================================================================
--- branches/Virtex6/ML605/Tx_Output_Arbitor.vhd (revision 9)
+++ branches/Virtex6/ML605/Tx_Output_Arbitor.vhd (nonexistent)
@@ -1,305 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer : wgao, LI5, Univ. Mannheim
---
--- Create Date: 07.12.2006
--- Design Name:
--- Module Name: Tx_Output_Arbitor - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision 2.00 - Dimension elastized by GENERATE. 10.07.2007
---
--- Revision 1.30 - abbPackage used. 26.06.2007
---
--- Revision 1.20 - Timing better. 29.01.2007
---
--- Revision 1.10 - Current States drive. 12.01.2007
---
--- Revision 1.00 - first release. 14.12.2006
---
--- Additional Comments:
--- Dimension can be easily expanded.
---
-----------------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_ARITH.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.abb64Package.all;
-
-
------------ Top entity ---------------
-entity Tx_Output_Arbitor is
- port (
- rst_n : IN std_logic;
- clk : IN std_logic;
-
- arbtake : IN std_logic; -- take a valid arbitration by the user
- Req : IN std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0); -- similar to FIFO not-empty
-
- bufread : OUT std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0); -- Read FIFO
- Ack : OUT std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0) -- tells who is the winner
- );
-end Tx_Output_Arbitor;
-
-
-architecture Behavioral of Tx_Output_Arbitor is
-
- TYPE ArbStates is (
- aSt_Reset
- , aSt_Idle
- , aSt_ReadOne
- , aSt_Ready
- );
-
- signal Arb_FSM : ArbStates;
- signal Arb_FSM_NS : ArbStates;
-
-
- TYPE PriorMatrix is ARRAY (C_ARBITRATE_WIDTH-1 downto 0)
- of std_logic_vector (C_ARBITRATE_WIDTH-1 downto 0);
-
- signal ChPriority : PriorMatrix;
-
- signal Prior_Init_Value : PriorMatrix;
-
- signal Wide_Req : PriorMatrix;
-
- signal Wide_Req_turned : PriorMatrix;
-
-
- signal take_i : std_logic;
- signal Req_i : std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
-
- signal Req_r1 : std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
-
- signal read_prep : std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
- signal read_i : std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
- signal Indice_prep : std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
- signal Indice_i : std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
-
- signal Champion_Vector : std_logic_vector (C_ARBITRATE_WIDTH-1 downto 0);
-
-
-begin
-
- bufread <= read_i;
- Ack <= Indice_i;
-
- take_i <= arbtake;
- Req_i <= Req;
-
- -- ------------------------------------------------------------
- Prior_Init_Value(0) <= C_LOWEST_PRIORITY;
- Gen_Prior_Init_Values:
- FOR i IN 1 TO C_ARBITRATE_WIDTH-1 generate
- Prior_Init_Value(i) <= Prior_Init_Value(i-1)(C_ARBITRATE_WIDTH-2 downto 0) & '1';
- end generate;
-
-
- -- ------------------------------------------------------------
- -- Mask the requests
- --
- Gen_Wide_Requests:
- FOR i IN 0 TO C_ARBITRATE_WIDTH-1 generate
- Wide_Req(i) <= ChPriority(i) when Req_i(i)='1'
- else C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
- end generate;
-
-
--- ------------------------------------
--- Synchronous Delay: Req
---
- Synch_Delay_Req:
- process(clk)
- begin
- if clk'event and clk = '1' then
- Req_r1 <= Req_i;
- end if;
- end process;
-
-
--- ------------------------------------
--- Synchronous: States
---
- Seq_FSM_NextState:
- process(clk, rst_n)
- begin
- if (rst_n = '0') then
- Arb_FSM <= aSt_Reset;
- elsif clk'event and clk = '1' then
- Arb_FSM <= Arb_FSM_NS;
- end if;
- end process;
-
-
--- ------------------------------------
--- Combinatorial: Next States
---
- Comb_FSM_NextState:
- process (
- Arb_FSM
- , take_i
- , Req_r1
- )
- begin
- case Arb_FSM is
-
- when aSt_Reset =>
- Arb_FSM_NS <= aSt_Idle;
-
- when aSt_Idle =>
- if Req_r1 = C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0) then
- Arb_FSM_NS <= aSt_Idle;
- else
- Arb_FSM_NS <= aSt_ReadOne;
- end if;
-
- when aSt_ReadOne =>
- if Req_r1 = C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0) then -- Ghost Request !!!
- Arb_FSM_NS <= aSt_Idle;
- else
- Arb_FSM_NS <= aSt_Ready;
- end if;
-
- when aSt_Ready =>
- if take_i = '0' then
- Arb_FSM_NS <= aSt_Ready;
- elsif Req_r1 = C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0) then
- Arb_FSM_NS <= aSt_Idle;
- else
- Arb_FSM_NS <= aSt_ReadOne;
- end if;
-
- when Others =>
- Arb_FSM_NS <= aSt_Reset;
-
- end case;
-
- end process;
-
-
--- --------------------------------------------------
--- Turn the Request-Array Around
---
- Turn_the_Request_Array_Around:
- FOR i IN 0 TO C_ARBITRATE_WIDTH-1 generate
- Dimension_2nd:
- FOR j IN 0 TO C_ARBITRATE_WIDTH-1 generate
- Wide_Req_turned(i)(j) <= Wide_Req(j)(i);
- END generate;
- END generate;
-
-
--- --------------------------------------------------
--- Synchronous Calculation: Champion_Vector
---
- Sync_Champion_Vector:
- process(clk)
- begin
- if clk'event and clk = '1' then
-
- FOR i IN 0 TO C_ARBITRATE_WIDTH-1 LOOP
- if Wide_Req_turned(i)=C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0) then
- Champion_Vector(i) <= '0';
- else
- Champion_Vector(i) <= '1';
- end if;
- END LOOP;
-
- end if;
- end process;
-
-
--- --------------------------------------------------
--- Prepare the buffer read signal: read_i
---
- Gen_Read_Signals:
- FOR i IN 0 TO C_ARBITRATE_WIDTH-1 generate
- read_prep(i) <= '1' when Champion_Vector=ChPriority(i) else '0';
- end generate;
-
-
--- --------------------------------------------------
--- FSM Output : Buffer read_i and Indice_i
---
- FSM_Output_read_Indice:
- process (clk, rst_n)
- begin
- if (rst_n = '0') then
- read_i <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
- Indice_prep <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
- Indice_i <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
- elsif clk'event and clk = '1' then
-
- case Arb_FSM is
-
- when aSt_ReadOne =>
- read_i <= read_prep;
- Indice_prep <= read_prep;
- Indice_i <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
-
- when aSt_Ready =>
- read_i <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
- Indice_prep <= Indice_prep;
- if take_i ='1' then
- Indice_i <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
- else
- Indice_i <= Indice_prep;
- end if;
-
- when Others =>
- read_i <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
- Indice_prep <= Indice_prep;
- Indice_i <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
-
- end case;
-
- end if;
- end process;
-
-
--- --------------------------------------------------
---
- Gen_Modify_Priorities:
-
- FOR i IN 0 TO C_ARBITRATE_WIDTH-1 generate
-
- Proc_Priority_Cycling:
- process (clk, rst_n)
- begin
- if (rst_n = '0') then
- ChPriority(i) <= Prior_Init_Value(i);
- elsif clk'event and clk = '1' then
-
- case Arb_FSM is
-
- when aSt_ReadOne =>
- if ChPriority(i) = Champion_Vector then
- ChPriority(i) <= C_LOWEST_PRIORITY;
- elsif (ChPriority(i) and Champion_Vector) = Champion_Vector then
- ChPriority(i) <= ChPriority(i);
- else
- ChPriority(i) <= ChPriority(i)(C_ARBITRATE_WIDTH-2 downto 0) & '1';
- end if;
-
- when Others =>
- ChPriority(i) <= ChPriority(i);
-
- end case;
-
- end if;
- end process;
-
- end generate;
-
-
-end architecture Behavioral;
Index: branches/Virtex6/ML605/v6eb_pcie.vhd
===================================================================
--- branches/Virtex6/ML605/v6eb_pcie.vhd (revision 9)
+++ branches/Virtex6/ML605/v6eb_pcie.vhd (nonexistent)
@@ -1,1929 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 09:12:51 01 Feb 2010
--- Design Name:
--- Module Name: v6pcieDMA - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
---
--- Revision 1.00 - File Released
---
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.abb64Package.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
-library UNISIM;
-use UNISIM.VComponents.all;
-
-entity v6pcieDMA is
- generic (
- constant pcieLanes : integer := C_NUM_PCIE_LANES
- );
- Port (
-
- -- Optical links
- TILE0_REFCLK_PAD_N_IN : IN std_logic;
- TILE0_REFCLK_PAD_P_IN : IN std_logic;
-
- RXN_IN : IN std_logic;
- RXP_IN : IN std_logic;
- TXN_OUT : OUT std_logic;
- TXP_OUT : OUT std_logic;
-
- SFP_LOS : IN std_logic;
-
-
- -- DDR interface
-
--- ddr2_sys_clk : IN std_logic;
---v6 Button_Rst : IN std_logic;
-
- -- dummy pin input !!!! not really exists
---v6 dummy_pin_in : IN std_logic_vector(3-1 downto 0);
-
- -- DPR blinker
- LEDs_IO_pin : OUT std_logic_vector(7 downto 0);
-
-
---v6 refclkout : OUT std_logic;
-
- -- PCIe transceivers
- pci_exp_rxp : IN std_logic_vector(pcieLanes - 1 downto 0);
- pci_exp_rxn : IN std_logic_vector(pcieLanes - 1 downto 0);
- pci_exp_txp : OUT std_logic_vector(pcieLanes - 1 downto 0);
- pci_exp_txn : OUT std_logic_vector(pcieLanes - 1 downto 0);
-
- -- Necessity signals
- sys_clk_p : IN std_logic;
- sys_clk_n : IN std_logic;
- sys_reset_n : IN std_logic
- );
-
-end entity v6pcieDMA;
-
-
-architecture Behavioral of v6pcieDMA is
-
-
-
--- signal dlm_rec0 : std_logic_vector(3 downto 0);
--- signal dlm_rec_valid0 : std_logic;
---
--- signal dlm_rec1 : std_logic_vector(3 downto 0);
--- signal dlm_rec_valid1 : std_logic;
-
-
-
-------------- COMPONENT Declaration: v6_pcie_v1_3 x4 ------
- component v6_pcie_v1_3
- generic (
- PL_FAST_TRAIN : boolean
- );
- port (
- ---------------------------------------------------------
- -- 1. PCI Express (pci_exp) Interface
- ---------------------------------------------------------
-
- -- Tx
- pci_exp_txn : out STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
- pci_exp_txp : out STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
-
- -- Rx
- pci_exp_rxn : in STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
- pci_exp_rxp : in STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
-
- ---------------------------------------------------------
- -- 2. Transaction (TRN) Interface
- ---------------------------------------------------------
-
- -- Common
- trn_clk : out STD_LOGIC;
- trn_reset_n : out STD_LOGIC;
- trn_lnk_up_n : out STD_LOGIC;
-
- -- Tx
- trn_tbuf_av : out STD_LOGIC_vector (6-1 downto 0);
- trn_tcfg_req_n : out STD_LOGIC;
- trn_terr_drop_n : out STD_LOGIC;
- trn_tdst_rdy_n : out STD_LOGIC;
- trn_td : in STD_LOGIC_vector (64-1 downto 0);
- trn_trem_n : in STD_LOGIC;
- trn_tsof_n : in STD_LOGIC;
- trn_teof_n : in STD_LOGIC;
- trn_tsrc_rdy_n : in STD_LOGIC;
- trn_tsrc_dsc_n : in STD_LOGIC;
- trn_terrfwd_n : in STD_LOGIC;
- trn_tcfg_gnt_n : in STD_LOGIC;
- trn_tstr_n : in STD_LOGIC;
-
- -- Rx
- trn_rd : out STD_LOGIC_vector (64-1 downto 0);
- trn_rrem_n : out STD_LOGIC;
- trn_rsof_n : out STD_LOGIC;
- trn_reof_n : out STD_LOGIC;
- trn_rsrc_rdy_n : out STD_LOGIC;
- trn_rsrc_dsc_n : out STD_LOGIC;
- trn_rerrfwd_n : out STD_LOGIC;
- trn_rbar_hit_n : out STD_LOGIC_vector (7-1 downto 0);
- trn_rdst_rdy_n : in STD_LOGIC;
- trn_rnp_ok_n : in STD_LOGIC;
-
- -- Flow Control
- trn_fc_cpld : out STD_LOGIC_vector (12-1 downto 0);
- trn_fc_cplh : out STD_LOGIC_vector (8-1 downto 0);
- trn_fc_npd : out STD_LOGIC_vector (12-1 downto 0);
- trn_fc_nph : out STD_LOGIC_vector (8-1 downto 0);
- trn_fc_pd : out STD_LOGIC_vector (12-1 downto 0);
- trn_fc_ph : out STD_LOGIC_vector (8-1 downto 0);
- trn_fc_sel : in STD_LOGIC_vector (3-1 downto 0);
-
-
- ---------------------------------------------------------
- -- 3. Configuration (CFG) Interface
- ---------------------------------------------------------
-
- cfg_do : out STD_LOGIC_vector (32-1 downto 0);
- cfg_rd_wr_done_n : out STD_LOGIC;
- cfg_di : in STD_LOGIC_vector (32-1 downto 0);
- cfg_byte_en_n : in STD_LOGIC_vector (4-1 downto 0);
- cfg_dwaddr : in STD_LOGIC_vector (10-1 downto 0);
- cfg_wr_en_n : in STD_LOGIC;
- cfg_rd_en_n : in STD_LOGIC;
-
- cfg_err_cor_n : in STD_LOGIC;
- cfg_err_ur_n : in STD_LOGIC;
- cfg_err_ecrc_n : in STD_LOGIC;
- cfg_err_cpl_timeout_n : in STD_LOGIC;
- cfg_err_cpl_abort_n : in STD_LOGIC;
- cfg_err_cpl_unexpect_n : in STD_LOGIC;
- cfg_err_posted_n : in STD_LOGIC;
- cfg_err_locked_n : in STD_LOGIC;
- cfg_err_tlp_cpl_header : in STD_LOGIC_vector (48-1 downto 0);
- cfg_err_cpl_rdy_n : out STD_LOGIC;
- cfg_interrupt_n : in STD_LOGIC;
- cfg_interrupt_rdy_n : out STD_LOGIC;
- cfg_interrupt_assert_n : in STD_LOGIC;
- cfg_interrupt_di : in STD_LOGIC_vector (8-1 downto 0);
- cfg_interrupt_do : out STD_LOGIC_vector (8-1 downto 0);
- cfg_interrupt_mmenable : out STD_LOGIC_vector (3-1 downto 0);
- cfg_interrupt_msienable : out STD_LOGIC;
- cfg_interrupt_msixenable : out STD_LOGIC;
- cfg_interrupt_msixfm : out STD_LOGIC;
- cfg_turnoff_ok_n : in STD_LOGIC;
- cfg_to_turnoff_n : out STD_LOGIC;
- cfg_trn_pending_n : in STD_LOGIC;
- cfg_pm_wake_n : in STD_LOGIC;
- cfg_bus_number : out STD_LOGIC_vector (8-1 downto 0);
- cfg_device_number : out STD_LOGIC_vector (5-1 downto 0);
- cfg_function_number : out STD_LOGIC_vector (3-1 downto 0);
- cfg_status : out STD_LOGIC_vector (16-1 downto 0);
- cfg_command : out STD_LOGIC_vector (16-1 downto 0);
- cfg_dstatus : out STD_LOGIC_vector (16-1 downto 0);
- cfg_dcommand : out STD_LOGIC_vector (16-1 downto 0);
- cfg_lstatus : out STD_LOGIC_vector (16-1 downto 0);
- cfg_lcommand : out STD_LOGIC_vector (16-1 downto 0);
- cfg_dcommand2 : out STD_LOGIC_vector (16-1 downto 0);
- cfg_pcie_link_state_n : out STD_LOGIC_vector (3-1 downto 0);
- cfg_dsn : in STD_LOGIC_vector (64-1 downto 0);
- cfg_pmcsr_pme_en : out STD_LOGIC;
- cfg_pmcsr_pme_status : out STD_LOGIC;
- cfg_pmcsr_powerstate : out STD_LOGIC_vector (2-1 downto 0);
- lnk_clk_en : out STD_LOGIC;
-
-
- ---------------------------------------------------------
- -- 4. Physical Layer Control and Status (PL) Interface
- ---------------------------------------------------------
-
- pl_initial_link_width : out STD_LOGIC_vector (3-1 downto 0);
- pl_lane_reversal_mode : out STD_LOGIC_vector (2-1 downto 0);
- pl_link_gen2_capable : out STD_LOGIC;
- pl_link_partner_gen2_supported : out STD_LOGIC;
- pl_link_upcfg_capable : out STD_LOGIC;
- pl_ltssm_state : out STD_LOGIC_vector (6-1 downto 0);
- pl_received_hot_rst : out STD_LOGIC;
- pl_sel_link_rate : out STD_LOGIC;
- pl_sel_link_width : out STD_LOGIC_vector (2-1 downto 0);
- pl_directed_link_auton : in STD_LOGIC;
- pl_directed_link_change : in STD_LOGIC_vector (2-1 downto 0);
- pl_directed_link_speed : in STD_LOGIC;
- pl_directed_link_width : in STD_LOGIC_vector (2-1 downto 0);
- pl_upstream_prefer_deemph : in STD_LOGIC;
-
-
- ---------------------------------------------------------
- -- 5. System (SYS) Interface
- ---------------------------------------------------------
-
- sys_clk : in STD_LOGIC;
- sys_reset_n : in STD_LOGIC
- );
- end component;
-
-
-
-------------- COMPONENT Declaration: v6_pcie_v1_3 x8 ------
- component v6_pcie_v1_3x8
- generic (
- PL_FAST_TRAIN : boolean
- );
- port (
- ---------------------------------------------------------
- -- 1. PCI Express (pci_exp) Interface
- ---------------------------------------------------------
-
- -- Tx
- pci_exp_txn : out STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
- pci_exp_txp : out STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
-
- -- Rx
- pci_exp_rxn : in STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
- pci_exp_rxp : in STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
-
- ---------------------------------------------------------
- -- 2. Transaction (TRN) Interface
- ---------------------------------------------------------
-
- -- Common
- trn_clk : out STD_LOGIC;
- trn_reset_n : out STD_LOGIC;
- trn_lnk_up_n : out STD_LOGIC;
-
- -- Tx
- trn_tbuf_av : out STD_LOGIC_vector (6-1 downto 0);
- trn_tcfg_req_n : out STD_LOGIC;
- trn_terr_drop_n : out STD_LOGIC;
- trn_tdst_rdy_n : out STD_LOGIC;
- trn_td : in STD_LOGIC_vector (64-1 downto 0);
- trn_trem_n : in STD_LOGIC;
- trn_tsof_n : in STD_LOGIC;
- trn_teof_n : in STD_LOGIC;
- trn_tsrc_rdy_n : in STD_LOGIC;
- trn_tsrc_dsc_n : in STD_LOGIC;
- trn_terrfwd_n : in STD_LOGIC;
- trn_tcfg_gnt_n : in STD_LOGIC;
- trn_tstr_n : in STD_LOGIC;
-
- -- Rx
- trn_rd : out STD_LOGIC_vector (64-1 downto 0);
- trn_rrem_n : out STD_LOGIC;
- trn_rsof_n : out STD_LOGIC;
- trn_reof_n : out STD_LOGIC;
- trn_rsrc_rdy_n : out STD_LOGIC;
- trn_rsrc_dsc_n : out STD_LOGIC;
- trn_rerrfwd_n : out STD_LOGIC;
- trn_rbar_hit_n : out STD_LOGIC_vector (7-1 downto 0);
- trn_rdst_rdy_n : in STD_LOGIC;
- trn_rnp_ok_n : in STD_LOGIC;
-
- -- Flow Control
- trn_fc_cpld : out STD_LOGIC_vector (12-1 downto 0);
- trn_fc_cplh : out STD_LOGIC_vector (8-1 downto 0);
- trn_fc_npd : out STD_LOGIC_vector (12-1 downto 0);
- trn_fc_nph : out STD_LOGIC_vector (8-1 downto 0);
- trn_fc_pd : out STD_LOGIC_vector (12-1 downto 0);
- trn_fc_ph : out STD_LOGIC_vector (8-1 downto 0);
- trn_fc_sel : in STD_LOGIC_vector (3-1 downto 0);
-
-
- ---------------------------------------------------------
- -- 3. Configuration (CFG) Interface
- ---------------------------------------------------------
-
- cfg_do : out STD_LOGIC_vector (32-1 downto 0);
- cfg_rd_wr_done_n : out STD_LOGIC;
- cfg_di : in STD_LOGIC_vector (32-1 downto 0);
- cfg_byte_en_n : in STD_LOGIC_vector (4-1 downto 0);
- cfg_dwaddr : in STD_LOGIC_vector (10-1 downto 0);
- cfg_wr_en_n : in STD_LOGIC;
- cfg_rd_en_n : in STD_LOGIC;
-
- cfg_err_cor_n : in STD_LOGIC;
- cfg_err_ur_n : in STD_LOGIC;
- cfg_err_ecrc_n : in STD_LOGIC;
- cfg_err_cpl_timeout_n : in STD_LOGIC;
- cfg_err_cpl_abort_n : in STD_LOGIC;
- cfg_err_cpl_unexpect_n : in STD_LOGIC;
- cfg_err_posted_n : in STD_LOGIC;
- cfg_err_locked_n : in STD_LOGIC;
- cfg_err_tlp_cpl_header : in STD_LOGIC_vector (48-1 downto 0);
- cfg_err_cpl_rdy_n : out STD_LOGIC;
- cfg_interrupt_n : in STD_LOGIC;
- cfg_interrupt_rdy_n : out STD_LOGIC;
- cfg_interrupt_assert_n : in STD_LOGIC;
- cfg_interrupt_di : in STD_LOGIC_vector (8-1 downto 0);
- cfg_interrupt_do : out STD_LOGIC_vector (8-1 downto 0);
- cfg_interrupt_mmenable : out STD_LOGIC_vector (3-1 downto 0);
- cfg_interrupt_msienable : out STD_LOGIC;
- cfg_interrupt_msixenable : out STD_LOGIC;
- cfg_interrupt_msixfm : out STD_LOGIC;
- cfg_turnoff_ok_n : in STD_LOGIC;
- cfg_to_turnoff_n : out STD_LOGIC;
- cfg_trn_pending_n : in STD_LOGIC;
- cfg_pm_wake_n : in STD_LOGIC;
- cfg_bus_number : out STD_LOGIC_vector (8-1 downto 0);
- cfg_device_number : out STD_LOGIC_vector (5-1 downto 0);
- cfg_function_number : out STD_LOGIC_vector (3-1 downto 0);
- cfg_status : out STD_LOGIC_vector (16-1 downto 0);
- cfg_command : out STD_LOGIC_vector (16-1 downto 0);
- cfg_dstatus : out STD_LOGIC_vector (16-1 downto 0);
- cfg_dcommand : out STD_LOGIC_vector (16-1 downto 0);
- cfg_lstatus : out STD_LOGIC_vector (16-1 downto 0);
- cfg_lcommand : out STD_LOGIC_vector (16-1 downto 0);
- cfg_dcommand2 : out STD_LOGIC_vector (16-1 downto 0);
- cfg_pcie_link_state_n : out STD_LOGIC_vector (3-1 downto 0);
- cfg_dsn : in STD_LOGIC_vector (64-1 downto 0);
- cfg_pmcsr_pme_en : out STD_LOGIC;
- cfg_pmcsr_pme_status : out STD_LOGIC;
- cfg_pmcsr_powerstate : out STD_LOGIC_vector (2-1 downto 0);
- lnk_clk_en : out STD_LOGIC;
-
-
- ---------------------------------------------------------
- -- 4. Physical Layer Control and Status (PL) Interface
- ---------------------------------------------------------
-
- pl_initial_link_width : out STD_LOGIC_vector (3-1 downto 0);
- pl_lane_reversal_mode : out STD_LOGIC_vector (2-1 downto 0);
- pl_link_gen2_capable : out STD_LOGIC;
- pl_link_partner_gen2_supported : out STD_LOGIC;
- pl_link_upcfg_capable : out STD_LOGIC;
- pl_ltssm_state : out STD_LOGIC_vector (6-1 downto 0);
- pl_received_hot_rst : out STD_LOGIC;
- pl_sel_link_rate : out STD_LOGIC;
- pl_sel_link_width : out STD_LOGIC_vector (2-1 downto 0);
- pl_directed_link_auton : in STD_LOGIC;
- pl_directed_link_change : in STD_LOGIC_vector (2-1 downto 0);
- pl_directed_link_speed : in STD_LOGIC;
- pl_directed_link_width : in STD_LOGIC_vector (2-1 downto 0);
- pl_upstream_prefer_deemph : in STD_LOGIC;
-
-
- ---------------------------------------------------------
- -- 5. System (SYS) Interface
- ---------------------------------------------------------
-
- sys_clk : in STD_LOGIC;
- sys_reset_n : in STD_LOGIC
- );
- end component;
-
-
---
--- signal ddr2_sys_clk_i : std_logic;
--- signal idelay_value_counter : std_logic_vector(6-1 downto 0);
--- signal idelay_calibrate_successful : std_logic;
- signal fifo_reset_done : std_logic;
--- signal failure_read : std_logic;
- signal pio_reading_status : std_logic;
-
-
--- -----------------------------------------------------------------------
--- DDR SDRAM control module
--- 1 or 2 DDR RAM modules are used
---
- COMPONENT bram_DDRs_Control
- GENERIC (
- C_ASYNFIFO_WIDTH : integer ;
- P_SIMULATION : boolean
- );
- PORT (
-
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- DDR_wr_sof : IN std_logic;
- DDR_wr_eof : IN std_logic;
- DDR_wr_v : IN std_logic;
- DDR_wr_FA : IN std_logic;
- DDR_wr_Shift : IN std_logic;
- DDR_wr_Mask : IN std_logic_vector(2-1 downto 0);
- DDR_wr_din : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- DDR_wr_full : OUT std_logic;
-
- DDR_rdc_sof : IN std_logic;
- DDR_rdc_eof : IN std_logic;
- DDR_rdc_v : IN std_logic;
- DDR_rdc_FA : IN std_logic;
- DDR_rdc_Shift : IN std_logic;
- DDR_rdc_din : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- DDR_rdc_full : OUT std_logic;
-
- -- DDR payload FIFO Read Port
- DDR_FIFO_RdEn : IN std_logic;
- DDR_FIFO_Empty : OUT std_logic;
- DDR_FIFO_RdQout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
--- DDR_rdD_sof : OUT std_logic;
--- DDR_rdD_eof : OUT std_logic;
--- DDR_rdDout_V : OUT std_logic;
--- DDR_rdDout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- Common interface
- DDR_Ready : OUT std_logic;
- DDR_Blinker : OUT std_logic;
- mem_clk : IN std_logic;
- trn_clk : IN std_logic;
- trn_reset_n : IN std_logic
- );
- END COMPONENT;
-
- signal DDR_wr_sof : std_logic;
- signal DDR_wr_eof : std_logic;
- signal DDR_wr_v : std_logic;
- signal DDR_wr_FA : std_logic;
- signal DDR_wr_Shift : std_logic;
- signal DDR_wr_Mask : std_logic_vector(2-1 downto 0);
- signal DDR_wr_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal DDR_wr_full : std_logic;
-
- signal DDR_rdc_sof : std_logic;
- signal DDR_rdc_eof : std_logic;
- signal DDR_rdc_v : std_logic;
- signal DDR_rdc_FA : std_logic;
- signal DDR_rdc_Shift : std_logic;
- signal DDR_rdc_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal DDR_rdc_full : std_logic;
-
- signal DDR_FIFO_RdEn : std_logic;
- signal DDR_FIFO_Empty : std_logic;
- signal DDR_FIFO_RdQout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
--- signal DDR_rdD_sof : std_logic;
--- signal DDR_rdD_eof : std_logic;
--- signal DDR_rdDout_V : std_logic;
--- signal DDR_rdDout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- signal DDR_Ready : std_logic;
- signal DDR_Blinker : std_logic;
-
--- signal mem_clk : std_logic;
-
- -- -----------------------------------------------------------------------
- -- FIFO module
- -- 16K x 8B
- component eb_wrapper
- port (
- wr_clk : IN std_logic;
- wr_en : IN std_logic;
- din : IN std_logic_VECTOR(72-1 downto 0);
- pfull : OUT std_logic;
- full : OUT std_logic;
-
- rd_clk : IN std_logic;
- rd_en : IN std_logic;
- dout : OUT std_logic_VECTOR(72-1 downto 0);
- pempty : OUT std_logic;
- empty : OUT std_logic;
-
- data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
- rst : IN std_logic
- );
- end component;
-
- signal eb_wclk : std_logic;
- signal eb_we : std_logic;
- signal eb_wsof : std_logic;
- signal eb_weof : std_logic;
- signal eb_din : std_logic_VECTOR(72-1 downto 0);
- signal eb_pfull : std_logic;
- signal eb_full : std_logic;
- signal eb_rclk : std_logic;
- signal eb_re : std_logic;
- signal eb_dout : std_logic_VECTOR(72-1 downto 0);
- signal eb_pempty : std_logic;
- signal eb_empty : std_logic;
- signal eb_rst : std_logic;
- signal eb_FIFO_Status : std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
- signal eb_data_count : std_logic_vector(C_FIFO_DC_WIDTH downto 0);
- signal pio_read_status : std_logic;
- signal eb_FIFO_ow : std_logic;
-
- signal eb_we_up : std_logic;
- signal eb_din_up : std_logic_VECTOR(72-1 downto 0);
-
-
- signal tab_sel : STD_LOGIC;
- signal tab_we : STD_LOGIC_VECTOR (2-1 downto 0);
- signal tab_wa : STD_LOGIC_VECTOR (12-1 downto 0);
- signal tab_wd : STD_LOGIC_VECTOR (C_DBUS_WIDTH-1 downto 0);
-
- signal dg_running : STD_LOGIC;
- signal dg_mask : STD_LOGIC;
- signal dg_rst : STD_LOGIC;
-
- -- debug signal
- signal dg_debug_led : STD_LOGIC;
-
- -- Protocol Interface module
- COMPONENT protocol_IF
- PORT (
- -- DAQ Tx
- data2send_start : OUT std_logic;
- data2send_end : OUT std_logic;
- data2send : OUT std_logic_vector(64-1 downto 0);
- crc_error_send : OUT std_logic;
- data2send_stop : IN std_logic;
-
- -- DAQ Rx
- data_rec_start : IN std_logic;
- data_rec_end : IN std_logic;
- data_rec : IN std_logic_vector(64-1 downto 0);
- crc_error_rec : IN std_logic;
- data_rec_stop : OUT std_logic;
-
- -- CTL Tx
- ctrl2send_start : OUT std_logic;
- ctrl2send_end : OUT std_logic;
- ctrl2send : OUT std_logic_vector(16-1 downto 0);
- ctrl2send_stop : IN std_logic;
-
- -- CTL Rx
- ctrl_rec_start : IN std_logic;
- ctrl_rec_end : IN std_logic;
- ctrl_rec : IN std_logic_vector(16-1 downto 0);
- ctrl_rec_stop : OUT std_logic;
-
- -- DLM Tx
- dlm2send_va : OUT std_logic;
- dlm2send_type : OUT std_logic_vector(4-1 downto 0);
-
- -- DLM Rx
- dlm_rec_va : IN std_logic;
- dlm_rec_type : IN std_logic_vector(4-1 downto 0);
-
- -- Common signals
- link_tx_clk : IN std_logic;
- link_rx_clk : IN std_logic;
- link_active : IN std_logic_vector(2-1 downto 0);
- protocol_clk : OUT std_logic;
- protocol_res_n : OUT std_logic;
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-
- -- Fabric side: DAQ Rx
- daq_rv : IN std_logic;
- daq_rsof : IN std_logic;
- daq_reof : IN std_logic;
- daq_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- daq_rstop : OUT std_logic;
-
- -- Fabric side: DAQ Tx
- daq_tv : OUT std_logic;
- daq_tsof : OUT std_logic;
- daq_teof : OUT std_logic;
- daq_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- daq_tstop : IN std_logic;
-
- -- Fabric side: DLM Rx
- dlm_rv : IN std_logic;
- dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Fabric side: DLM Tx
- dlm_tv : OUT std_logic;
- dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Fabric side: CTL Rx
- ctl_rv : IN std_logic;
- ctl_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
- ctl_rstop : OUT std_logic;
-
- -- Fabric side: CTL Tx
- ctl_ttake : IN std_logic;
- ctl_tv : OUT std_logic;
- ctl_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
- ctl_tstop : IN std_logic;
-
- ctl_reset : IN std_logic;
- ctl_status : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Interrupter triggers
- DAQ_irq : OUT std_logic;
- CTL_irq : OUT std_logic;
- DLM_irq : OUT std_logic;
-
- -- Data generator table write port
- tab_sel : IN STD_LOGIC;
- tab_we : IN STD_LOGIC_VECTOR (2-1 downto 0);
- tab_wa : IN STD_LOGIC_VECTOR (12-1 downto 0);
- tab_wd : IN STD_LOGIC_VECTOR (64-1 downto 0);
-
- -- DG control/status signal
- dg_running : OUT STD_LOGIC;
- dg_mask : IN STD_LOGIC;
- dg_rst : IN STD_LOGIC;
-
- -- DG debug signal
- daq_start_led : OUT STD_LOGIC;
-
- -- Fabric side: Common signals
- trn_clk : IN std_logic;
- protocol_link_act : OUT std_logic_vector(2-1 downto 0);
- protocol_rst : IN std_logic
- );
- END COMPONENT;
-
- -- DAQ Tx
- signal data2send_start : std_logic;
- signal data2send_end : std_logic;
- signal data2send : std_logic_vector(64-1 downto 0);
- signal crc_error_send : std_logic;
- signal data2send_stop : std_logic
- := '0';
-
- -- DAQ Rx
- signal data_rec_start : std_logic;
- signal data_rec_end : std_logic;
- signal data_rec : std_logic_vector(64-1 downto 0);
- signal crc_error_rec : std_logic;
- signal data_rec_stop : std_logic;
-
- -- CTL Tx
- signal ctrl2send_start : std_logic;
- signal ctrl2send_end : std_logic;
- signal ctrl2send : std_logic_vector(16-1 downto 0);
- signal ctrl2send_stop : std_logic;
-
- -- CTL Rx
- signal ctrl_rec_start : std_logic;
- signal ctrl_rec_end : std_logic;
- signal ctrl_rec : std_logic_vector(16-1 downto 0);
- signal ctrl_rec_stop : std_logic;
-
- -- DLM Tx
- signal dlm2send_va : std_logic;
- signal dlm2send_type : std_logic_vector(4-1 downto 0);
-
- -- DLM Rx
- signal dlm_rec_va : std_logic;
- signal dlm_rec_type : std_logic_vector(4-1 downto 0);
-
-
- -- Common signals
- signal link_rx_clk : std_logic;
- signal link_tx_clk : std_logic;
- signal link_active : std_logic_vector(2-1 downto 0);
- signal protocol_clk : std_logic;
- signal protocol_res_n : std_logic;
-
-
- -- Fabric side: DAQ Rx
- signal daq_rv : std_logic;
- signal daq_rsof : std_logic;
- signal daq_reof : std_logic;
- signal daq_rd : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal daq_rstop : std_logic;
-
- -- Fabric side: DAQ Tx
- signal daq_tv : std_logic;
- signal daq_tsof : std_logic;
- signal daq_teof : std_logic;
- signal daq_td : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal daq_tstop : std_logic;
-
- -- Fabric side: DLM Rx
- signal dlm_rv : std_logic;
- signal dlm_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Fabric side: DLM Tx
- signal dlm_tv : std_logic;
- signal dlm_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Fabric side: CTL Rx
- signal ctl_rv : std_logic;
- signal ctl_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
- signal ctl_rstop : std_logic;
-
- -- Fabric side: CTL Tx
- signal ctl_ttake : std_logic;
- signal ctl_tv : std_logic;
- signal ctl_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
- signal ctl_tstop : std_logic;
-
- signal ctl_reset : std_logic;
- signal ctl_status : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Interrupter triggers
- signal DAQ_irq : std_logic;
- signal CTL_irq : std_logic;
- signal DLM_irq : std_logic;
-
- -- Fabric side: Common signals
- signal protocol_link_act : std_logic_vector(2-1 downto 0);
- signal protocol_rst : std_logic;
-
-
- -- Pseudo link module, to be replaced by the real optical link
- COMPONENT pseudo_protocol_module
- PORT (
- -- DAQ Tx
- data2send_start : IN std_logic;
- data2send_end : IN std_logic;
- data2send : IN std_logic_vector(64-1 downto 0);
- crc_error_send : IN std_logic;
- data2send_stop : OUT std_logic;
-
- -- DAQ Rx
- data_rec_start : OUT std_logic;
- data_rec_end : OUT std_logic;
- data_rec : OUT std_logic_vector(64-1 downto 0);
- crc_error_rec : OUT std_logic;
- data_rec_stop : IN std_logic;
-
- -- CTL Tx
- ctrl2send_start : IN std_logic;
- ctrl2send_end : IN std_logic;
- ctrl2send : IN std_logic_vector(16-1 downto 0);
- ctrl2send_stop : OUT std_logic;
-
- -- CTL Rx
- ctrl_rec_start : OUT std_logic;
- ctrl_rec_end : OUT std_logic;
- ctrl_rec : OUT std_logic_vector(16-1 downto 0);
- ctrl_rec_stop : IN std_logic;
-
- -- DLM Tx
- dlm2send_va : IN std_logic;
- dlm2send_type : IN std_logic_vector(4-1 downto 0);
-
- -- DLM Rx
- dlm_rec_va : OUT std_logic;
- dlm_rec_type : OUT std_logic_vector(4-1 downto 0);
-
- -- dummy pin input
- dummy_pin_in : IN std_logic_vector(3-1 downto 0);
-
- -- Common interface
- link_tx_clk : OUT std_logic;
- link_rx_clk : OUT std_logic;
- link_active : OUT std_logic_vector(2-1 downto 0);
- clk : IN std_logic;
- res_n : IN std_logic
- );
- END COMPONENT;
-
-
- signal Link_Buf_full : std_logic;
-
-
-------------- COMPONENT Declaration: tlpControl ------
---
- component tlpControl
- port (
- -- Test pin, emulating DDR data flow discontinuity
- mbuf_UserFull : IN std_logic;
- trn_Blinker : OUT std_logic;
-
- -- DCB protocol interface
- protocol_link_act : IN std_logic_vector(2-1 downto 0);
- protocol_rst : OUT std_logic;
-
- -- Interrupter triggers
- DAQ_irq : IN std_logic;
- CTL_irq : IN std_logic;
- DLM_irq : IN std_logic;
-
- -- Fabric side: CTL Rx
- ctl_rv : OUT std_logic;
- ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Fabric side: CTL Tx
- ctl_ttake : OUT std_logic;
- ctl_tv : IN std_logic;
- ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
- ctl_tstop : OUT std_logic;
-
- ctl_reset : OUT std_logic;
- ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Fabric side: DLM Rx
- dlm_rv : OUT std_logic;
- dlm_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Fabric side: DLM Tx
- dlm_tv : IN std_logic;
- dlm_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- Link_Buf_full : IN std_logic;
-
- -- Event Buffer FIFO interface
- eb_FIFO_we : OUT std_logic;
- eb_FIFO_wsof : OUT std_logic;
- eb_FIFO_weof : OUT std_logic;
- eb_FIFO_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- eb_FIFO_re : OUT std_logic;
- eb_FIFO_empty : IN std_logic;
- eb_FIFO_qout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- eb_FIFO_data_count : IN std_logic_vector(C_FIFO_DC_WIDTH downto 0);
-
- eb_FIFO_ow : IN std_logic;
-
- pio_reading_status : OUT std_logic;
- eb_FIFO_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- eb_FIFO_Rst : OUT std_logic;
-
- -- Debugging signals
- DMA_us_Done : OUT std_logic;
- DMA_us_Busy : OUT std_logic;
- DMA_us_Busy_LED : OUT std_logic;
- DMA_ds_Done : OUT std_logic;
- DMA_ds_Busy : OUT std_logic;
- DMA_ds_Busy_LED : OUT std_logic;
-
- -- DDR control interface
- DDR_Ready : IN std_logic;
-
- DDR_wr_sof : OUT std_logic;
- DDR_wr_eof : OUT std_logic;
- DDR_wr_v : OUT std_logic;
- DDR_wr_FA : OUT std_logic;
- DDR_wr_Shift : OUT std_logic;
- DDR_wr_Mask : OUT std_logic_vector(2-1 downto 0);
- DDR_wr_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- DDR_wr_full : IN std_logic;
-
- DDR_rdc_sof : OUT std_logic;
- DDR_rdc_eof : OUT std_logic;
- DDR_rdc_v : OUT std_logic;
- DDR_rdc_FA : OUT std_logic;
- DDR_rdc_Shift : OUT std_logic;
- DDR_rdc_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- DDR_rdc_full : IN std_logic;
-
--- DDR_rdD_sof : IN std_logic;
--- DDR_rdD_eof : IN std_logic;
--- DDR_rdDout_V : IN std_logic;
--- DDR_rdDout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- DDR payload FIFO Read Port
- DDR_FIFO_RdEn : OUT std_logic;
- DDR_FIFO_Empty : IN std_logic;
- DDR_FIFO_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- Data generator table write
- tab_we : OUT std_logic_vector(2-1 downto 0);
- tab_wa : OUT std_logic_vector(12-1 downto 0);
- tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- Data generator control
- DG_is_Running : IN std_logic;
- DG_Reset : OUT std_logic;
- DG_Mask : OUT std_logic;
-
- -- Transaction layer interface
- trn_lnk_up_n : IN std_logic;
- trn_rsrc_dsc_n : IN std_logic;
- trn_rnp_ok_n : OUT std_logic;
- trn_tsrc_dsc_n : OUT std_logic;
- trn_tdst_dsc_n : IN std_logic;
- trn_tbuf_av : IN std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
- trn_terrfwd_n : OUT std_logic;
-
- trn_clk : IN std_logic;
- trn_reset_n : IN std_logic;
- trn_rsrc_rdy_n : IN std_logic;
- trn_tdst_rdy_n : IN std_logic;
- trn_rsof_n : IN std_logic;
- trn_reof_n : IN std_logic;
- trn_rerrfwd_n : IN std_logic;
- trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
- trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- cfg_dcommand : IN std_logic_vector(15 downto 0);
- pcie_link_width : IN std_logic_vector( 5 downto 0);
- localId : IN std_logic_vector(15 downto 0);
-
- cfg_interrupt_n : OUT std_logic;
- cfg_interrupt_rdy_n : IN std_logic;
- cfg_interrupt_mmenable : IN std_logic_vector(2 downto 0);
- cfg_interrupt_msienable : IN std_logic;
- cfg_interrupt_di : OUT std_logic_vector(7 downto 0);
- cfg_interrupt_do : IN std_logic_vector(7 downto 0);
- cfg_interrupt_assert_n : OUT std_logic;
-
- Format_Shower : OUT std_logic;
-
- trn_rbar_hit_n : IN std_logic_vector(6 downto 0);
- trn_tsrc_rdy_n : OUT std_logic;
- trn_rdst_rdy_n : OUT std_logic;
- trn_tsof_n : OUT std_logic;
- trn_teof_n : OUT std_logic;
- trn_trem_n : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
- trn_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
- );
- end component;
-
- signal Format_Shower : std_logic;
-
--- component BUFG is
--- port(
--- I : IN std_logic;
--- O : OUT std_logic
--- );
--- end component;
---
--- component IBUF is
--- port(
--- i : IN std_logic;
--- o : OUT std_logic
--- );
--- end component;
---
--- component IBUFDS is
--- port(
--- i : IN std_logic;
--- ib : IN std_logic;
--- o : OUT std_logic
--- );
--- end component;
---
--- component GT11CLK_MGT is
--- port(
--- mgtclkp : IN std_logic;
--- mgtclkn : IN std_logic;
--- synclk1out : OUT std_logic;
--- synclk2out : OUT std_logic
--- );
--- end component;
-
-
- -- TRN Layer signals
-
- signal trn_terr_drop_n : std_logic;
- signal trn_tcfg_gnt_n : std_logic;
- signal trn_tstr_n : std_logic;
- signal trn_fc_cpld : STD_LOGIC_vector (12-1 downto 0);
- signal trn_fc_cplh : STD_LOGIC_vector (8-1 downto 0);
- signal trn_fc_npd : STD_LOGIC_vector (12-1 downto 0);
- signal trn_fc_nph : STD_LOGIC_vector (8-1 downto 0);
- signal trn_fc_pd : STD_LOGIC_vector (12-1 downto 0);
- signal trn_fc_ph : STD_LOGIC_vector (8-1 downto 0);
- signal trn_fc_sel : STD_LOGIC_vector (3-1 downto 0);
-
- signal cfg_interrupt_msixenable : std_logic;
- signal cfg_interrupt_msixfm : std_logic;
- signal cfg_dcommand2 : std_logic_vector (16-1 downto 0);
- signal trn_tcfg_req_n : std_logic;
-
-
- signal pl_initial_link_width : STD_LOGIC_vector (3-1 downto 0);
- signal pl_lane_reversal_mode : STD_LOGIC_vector (2-1 downto 0);
- signal pl_link_gen2_capable : STD_LOGIC;
- signal pl_link_partner_gen2_supported : STD_LOGIC;
- signal pl_link_upcfg_capable : STD_LOGIC;
- signal pl_ltssm_state : STD_LOGIC_vector (6-1 downto 0);
- signal pl_received_hot_rst : STD_LOGIC;
- signal pl_sel_link_rate : STD_LOGIC;
- signal pl_sel_link_width : STD_LOGIC_vector (2-1 downto 0);
- signal pl_directed_link_auton : STD_LOGIC;
- signal pl_directed_link_change : STD_LOGIC_vector (2-1 downto 0);
- signal pl_directed_link_speed : STD_LOGIC;
- signal pl_directed_link_width : STD_LOGIC_vector (2-1 downto 0);
- signal pl_upstream_prefer_deemph : STD_LOGIC;
-
- signal trn_reset_n_int1 : STD_LOGIC;
- signal trn_lnk_up_n_int1 : STD_LOGIC;
-
-
-
- signal trn_clk : std_logic;
- signal trn_reset_n : std_logic;
- signal trn_lnk_up_n : std_logic;
- signal trn_td : std_logic_vector(63 downto 0);
- signal trn_trem_n : std_logic_vector(7 downto 0);
- signal trn_tsof_n : std_logic;
- signal trn_teof_n : std_logic;
- signal trn_tsrc_rdy_n : std_logic;
- signal trn_tdst_rdy_n : std_logic;
- signal trn_tdst_dsc_n : std_logic;
- signal trn_tsrc_dsc_n : std_logic;
- signal trn_terrfwd_n : std_logic;
- signal trn_tbuf_av : std_logic_vector(5 downto 0);
- signal trn_rd : std_logic_vector(63 downto 0);
- signal trn_rrem_n : std_logic_vector(7 downto 0);
- signal trn_rsof_n : std_logic;
- signal trn_reof_n : std_logic;
- signal trn_rsrc_rdy_n : std_logic;
- signal trn_rsrc_dsc_n : std_logic;
- signal trn_rdst_rdy_n : std_logic;
- signal trn_rerrfwd_n : std_logic;
- signal trn_rnp_ok_n : std_logic;
- signal trn_rbar_hit_n : std_logic_vector(6 downto 0);
- signal trn_rfc_nph_av : std_logic_vector(7 downto 0);
- signal trn_rfc_npd_av : std_logic_vector(11 downto 0);
- signal trn_rfc_ph_av : std_logic_vector(7 downto 0);
- signal trn_rfc_pd_av : std_logic_vector(11 downto 0);
- signal trn_rfc_cplh_av : std_logic_vector(7 downto 0);
- signal trn_rfc_cpld_av : std_logic_vector(11 downto 0);
- signal trn_rcpl_streaming_n : std_logic;
- signal cfg_do : std_logic_vector(31 downto 0);
- signal cfg_rd_wr_done_n : std_logic;
- signal cfg_di : std_logic_vector(31 downto 0);
- signal cfg_byte_en_n : std_logic_vector(3 downto 0);
- signal cfg_dwaddr : std_logic_vector(9 downto 0);
- signal cfg_wr_en_n : std_logic;
- signal cfg_rd_en_n : std_logic;
- signal cfg_err_cor_n : std_logic;
- signal cfg_err_ur_n : std_logic;
- signal cfg_err_cpl_rdy_n : std_logic;
- signal cfg_err_ecrc_n : std_logic;
- signal cfg_err_cpl_timeout_n : std_logic;
- signal cfg_err_cpl_abort_n : std_logic;
- signal cfg_err_cpl_unexpect_n : std_logic;
- signal cfg_err_posted_n : std_logic;
- signal cfg_err_locked_n : std_logic;
- signal cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
- signal cfg_interrupt_n : std_logic;
- signal cfg_interrupt_rdy_n : std_logic;
- signal cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
- signal cfg_interrupt_msienable : std_logic;
- signal cfg_interrupt_di : std_logic_vector(7 downto 0);
- signal cfg_interrupt_do : std_logic_vector(7 downto 0);
- signal cfg_interrupt_assert_n : std_logic;
- signal cfg_turnoff_ok_n : std_logic;
- signal cfg_to_turnoff_n : std_logic;
- signal cfg_pm_wake_n : std_logic;
- signal cfg_pcie_link_state_n : std_logic_vector(2 downto 0);
- signal cfg_trn_pending_n : std_logic;
- signal cfg_bus_number : std_logic_vector(7 downto 0);
- signal cfg_device_number : std_logic_vector(4 downto 0);
- signal cfg_function_number : std_logic_vector(2 downto 0);
- signal cfg_dsn : std_logic_vector(63 downto 0);
- signal cfg_status : std_logic_vector(15 downto 0);
- signal cfg_command : std_logic_vector(15 downto 0);
- signal cfg_dstatus : std_logic_vector(15 downto 0);
- signal cfg_dcommand : std_logic_vector(15 downto 0);
- signal cfg_lstatus : std_logic_vector(15 downto 0);
- signal cfg_lcommand : std_logic_vector(15 downto 0);
- signal fast_train_simulation_only : std_logic;
- signal two_plm_auto_config : std_logic_vector(1 downto 0);
- signal sys_clk_c : std_logic;
- signal sys_reset_n_c : std_logic;
- signal reset_n : std_logic;
-
- signal localId : std_logic_vector(15 downto 0);
- signal pcie_link_width : std_logic_vector( 5 downto 0);
-
- signal synclk2out : std_logic;
-
-
- --
- signal trn_Blinker : std_logic;
-
-
-begin
-
-
- sys_reset_n_ibuf : IBUF
- port map (
- O => sys_reset_n_c,
- I => sys_reset_n
- );
-
- refclk_ibuf : IBUFDS_GTXE1
- port map (
- O => sys_clk_c,
- ODIV2 => open,
- I => sys_clk_p,
- IB => sys_clk_n,
- CEB => '0'
- );
-
--- refclk_ibuf : IBUFDS
--- port map (
--- O => sys_clk,
--- I => sys_clk_p,
--- IB => sys_clk_n
--- );
-
--- ddr_sys_clk_bufg : BUFG
--- PORT MAP ( I => ddr2_sys_clk,
--- O => ddr2_sys_clk_i
--- );
-
-
---
---
- cfg_err_cor_n <= '1';
- cfg_err_ur_n <= '1';
- cfg_err_ecrc_n <= '1';
- cfg_err_cpl_timeout_n <= '1';
- cfg_err_cpl_abort_n <= '1';
- cfg_err_cpl_unexpect_n <= '1';
- cfg_err_posted_n <= '0';
- cfg_err_locked_n <= '0';
- cfg_err_tlp_cpl_header <= (OTHERS=>'0');
- cfg_trn_pending_n <= '1';
- cfg_pm_wake_n <= '1';
-
-
---
- trn_fc_sel <= (OTHERS=>'0');
-
- pl_directed_link_auton <= '0';
- pl_directed_link_change <= (OTHERS=>'0');
- pl_directed_link_speed <= '0';
- pl_directed_link_width <= (OTHERS=>'0');
- pl_upstream_prefer_deemph <= '0';
-
- trn_tcfg_gnt_n <= '0';
- trn_tstr_n <= '0'; -- '1';
-
---
-
- trn_tdst_dsc_n <= '1';
-
---
- cfg_di <= (OTHERS=>'0');
- cfg_dwaddr <= (OTHERS=>'1');
- cfg_byte_en_n <= (OTHERS=>'1');
- cfg_wr_en_n <= '1';
- cfg_rd_en_n <= '1';
- cfg_dsn <= X"00000001" & X"01" & X"000A35"; -- //this is taken from GUI -
-
- cfg_turnoff_ok_n <= '0';
-
-
- localId <= cfg_bus_number & cfg_device_number & cfg_function_number;
-
- pcie_link_width <= cfg_lstatus(9 downto 4);
-
-
-
- trn_lnk_up_n_int_i: FDCP
- generic map (
- INIT => '1'
- )
- port map (
- Q => trn_lnk_up_n,
- D => trn_lnk_up_n_int1,
- C => trn_clk,
- CLR => '0',
- PRE => '0'
- );
-
-
- trn_reset_n_i: FDCP
- generic map (
- INIT => '1'
- )
- port map (
- Q => trn_reset_n,
- D => trn_reset_n_int1,
- C => trn_clk,
- CLR => '0',
- PRE => '0'
- );
-
-
--- --------------------------------------------------------------
--- --------------------------------------------------------------
-
-make4Lanes: if pcieLanes = 4 generate
- pcieCore : v6_pcie_v1_3
- generic map (
- PL_FAST_TRAIN => FALSE
- )
- port map (
-
- ---------------------------------------------------------
- -- 1. PCI Express (pci_exp) Interface
- ---------------------------------------------------------
-
- -- Tx
- pci_exp_txp => pci_exp_txp ,
- pci_exp_txn => pci_exp_txn ,
-
- -- Rx
- pci_exp_rxp => pci_exp_rxp ,
- pci_exp_rxn => pci_exp_rxn ,
-
- ---------------------------------------------------------
- -- 2. Transaction (TRN) Interface
- ---------------------------------------------------------
-
- -- Common
- trn_clk => trn_clk ,
- trn_reset_n => trn_reset_n_int1 ,
- trn_lnk_up_n => trn_lnk_up_n_int1 ,
-
- -- Tx
- trn_tbuf_av => trn_tbuf_av ,
- trn_tcfg_req_n => trn_tcfg_req_n ,
- trn_terr_drop_n => trn_terr_drop_n ,
- trn_tdst_rdy_n => trn_tdst_rdy_n ,
- trn_td => trn_td ,
- trn_trem_n => trn_trem_n(0) ,
- trn_tsof_n => trn_tsof_n ,
- trn_teof_n => trn_teof_n ,
- trn_tsrc_rdy_n => trn_tsrc_rdy_n ,
- trn_tsrc_dsc_n => trn_tsrc_dsc_n ,
- trn_terrfwd_n => trn_terrfwd_n ,
- trn_tcfg_gnt_n => trn_tcfg_gnt_n ,
- trn_tstr_n => trn_tstr_n ,
-
- -- Rx
- trn_rd => trn_rd ,
- trn_rrem_n => trn_rrem_n(0) ,
- trn_rsof_n => trn_rsof_n ,
- trn_reof_n => trn_reof_n ,
- trn_rsrc_rdy_n => trn_rsrc_rdy_n ,
- trn_rsrc_dsc_n => trn_rsrc_dsc_n ,
- trn_rerrfwd_n => trn_rerrfwd_n ,
- trn_rbar_hit_n => trn_rbar_hit_n ,
- trn_rdst_rdy_n => trn_rdst_rdy_n ,
- trn_rnp_ok_n => trn_rnp_ok_n ,
-
- -- Flow Control
- trn_fc_cpld => trn_fc_cpld ,
- trn_fc_cplh => trn_fc_cplh ,
- trn_fc_npd => trn_fc_npd ,
- trn_fc_nph => trn_fc_nph ,
- trn_fc_pd => trn_fc_pd ,
- trn_fc_ph => trn_fc_ph ,
- trn_fc_sel => trn_fc_sel ,
-
-
- ---------------------------------------------------------
- -- 3. Configuration (CFG) Interface
- ---------------------------------------------------------
-
- cfg_do => cfg_do ,
- cfg_rd_wr_done_n => cfg_rd_wr_done_n ,
- cfg_di => cfg_di ,
- cfg_byte_en_n => cfg_byte_en_n ,
- cfg_dwaddr => cfg_dwaddr ,
- cfg_wr_en_n => cfg_wr_en_n ,
- cfg_rd_en_n => cfg_rd_en_n ,
-
- cfg_err_cor_n => cfg_err_cor_n ,
- cfg_err_ur_n => cfg_err_ur_n ,
- cfg_err_ecrc_n => cfg_err_ecrc_n ,
- cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n ,
- cfg_err_cpl_abort_n => cfg_err_cpl_abort_n ,
- cfg_err_cpl_unexpect_n => cfg_err_cpl_unexpect_n ,
- cfg_err_posted_n => cfg_err_posted_n ,
- cfg_err_locked_n => cfg_err_locked_n ,
- cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header ,
- cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n ,
- cfg_interrupt_n => cfg_interrupt_n ,
- cfg_interrupt_rdy_n => cfg_interrupt_rdy_n ,
- cfg_interrupt_assert_n => cfg_interrupt_assert_n ,
- cfg_interrupt_di => cfg_interrupt_di ,
- cfg_interrupt_do => cfg_interrupt_do ,
- cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
- cfg_interrupt_msienable => cfg_interrupt_msienable ,
- cfg_interrupt_msixenable => cfg_interrupt_msixenable ,
- cfg_interrupt_msixfm => cfg_interrupt_msixfm ,
- cfg_turnoff_ok_n => cfg_turnoff_ok_n ,
- cfg_to_turnoff_n => cfg_to_turnoff_n ,
- cfg_trn_pending_n => cfg_trn_pending_n ,
- cfg_pm_wake_n => cfg_pm_wake_n ,
- cfg_bus_number => cfg_bus_number ,
- cfg_device_number => cfg_device_number ,
- cfg_function_number => cfg_function_number ,
- cfg_status => cfg_status ,
- cfg_command => cfg_command ,
- cfg_dstatus => cfg_dstatus ,
- cfg_dcommand => cfg_dcommand ,
- cfg_lstatus => cfg_lstatus ,
- cfg_lcommand => cfg_lcommand ,
- cfg_dcommand2 => cfg_dcommand2 ,
- cfg_pcie_link_state_n => cfg_pcie_link_state_n ,
- cfg_dsn => cfg_dsn ,
-
- ---------------------------------------------------------
- -- 4. Physical Layer Control and Status (PL) Interface
- ---------------------------------------------------------
-
- pl_initial_link_width => pl_initial_link_width ,
- pl_lane_reversal_mode => pl_lane_reversal_mode ,
- pl_link_gen2_capable => pl_link_gen2_capable ,
- pl_link_partner_gen2_supported => pl_link_partner_gen2_supported ,
- pl_link_upcfg_capable => pl_link_upcfg_capable ,
- pl_ltssm_state => pl_ltssm_state ,
- pl_received_hot_rst => pl_received_hot_rst ,
- pl_sel_link_rate => pl_sel_link_rate ,
- pl_sel_link_width => pl_sel_link_width ,
- pl_directed_link_auton => pl_directed_link_auton ,
- pl_directed_link_change => pl_directed_link_change ,
- pl_directed_link_speed => pl_directed_link_speed ,
- pl_directed_link_width => pl_directed_link_width ,
- pl_upstream_prefer_deemph => pl_upstream_prefer_deemph ,
-
- ---------------------------------------------------------
- -- 5. System (SYS) Interface
- ---------------------------------------------------------
-
- sys_clk => sys_clk_c ,
- sys_reset_n => sys_reset_n_c
-
-);
-
- end generate;
-
-
-make8Lanes: if pcieLanes = 8 generate
- pcieCore : v6_pcie_v1_3x8
- generic map (
- PL_FAST_TRAIN => FALSE
- )
- port map (
-
- ---------------------------------------------------------
- -- 1. PCI Express (pci_exp) Interface
- ---------------------------------------------------------
-
- -- Tx
- pci_exp_txp => pci_exp_txp ,
- pci_exp_txn => pci_exp_txn ,
-
- -- Rx
- pci_exp_rxp => pci_exp_rxp ,
- pci_exp_rxn => pci_exp_rxn ,
-
- ---------------------------------------------------------
- -- 2. Transaction (TRN) Interface
- ---------------------------------------------------------
-
- -- Common
- trn_clk => trn_clk ,
- trn_reset_n => trn_reset_n_int1 ,
- trn_lnk_up_n => trn_lnk_up_n_int1 ,
-
- -- Tx
- trn_tbuf_av => trn_tbuf_av ,
- trn_tcfg_req_n => trn_tcfg_req_n ,
- trn_terr_drop_n => trn_terr_drop_n ,
- trn_tdst_rdy_n => trn_tdst_rdy_n ,
- trn_td => trn_td ,
- trn_trem_n => trn_trem_n(0) ,
- trn_tsof_n => trn_tsof_n ,
- trn_teof_n => trn_teof_n ,
- trn_tsrc_rdy_n => trn_tsrc_rdy_n ,
- trn_tsrc_dsc_n => trn_tsrc_dsc_n ,
- trn_terrfwd_n => trn_terrfwd_n ,
- trn_tcfg_gnt_n => trn_tcfg_gnt_n ,
- trn_tstr_n => trn_tstr_n ,
-
- -- Rx
- trn_rd => trn_rd ,
- trn_rrem_n => trn_rrem_n(0) ,
- trn_rsof_n => trn_rsof_n ,
- trn_reof_n => trn_reof_n ,
- trn_rsrc_rdy_n => trn_rsrc_rdy_n ,
- trn_rsrc_dsc_n => trn_rsrc_dsc_n ,
- trn_rerrfwd_n => trn_rerrfwd_n ,
- trn_rbar_hit_n => trn_rbar_hit_n ,
- trn_rdst_rdy_n => trn_rdst_rdy_n ,
- trn_rnp_ok_n => trn_rnp_ok_n ,
-
- -- Flow Control
- trn_fc_cpld => trn_fc_cpld ,
- trn_fc_cplh => trn_fc_cplh ,
- trn_fc_npd => trn_fc_npd ,
- trn_fc_nph => trn_fc_nph ,
- trn_fc_pd => trn_fc_pd ,
- trn_fc_ph => trn_fc_ph ,
- trn_fc_sel => trn_fc_sel ,
-
-
- ---------------------------------------------------------
- -- 3. Configuration (CFG) Interface
- ---------------------------------------------------------
-
- cfg_do => cfg_do ,
- cfg_rd_wr_done_n => cfg_rd_wr_done_n ,
- cfg_di => cfg_di ,
- cfg_byte_en_n => cfg_byte_en_n ,
- cfg_dwaddr => cfg_dwaddr ,
- cfg_wr_en_n => cfg_wr_en_n ,
- cfg_rd_en_n => cfg_rd_en_n ,
-
- cfg_err_cor_n => cfg_err_cor_n ,
- cfg_err_ur_n => cfg_err_ur_n ,
- cfg_err_ecrc_n => cfg_err_ecrc_n ,
- cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n ,
- cfg_err_cpl_abort_n => cfg_err_cpl_abort_n ,
- cfg_err_cpl_unexpect_n => cfg_err_cpl_unexpect_n ,
- cfg_err_posted_n => cfg_err_posted_n ,
- cfg_err_locked_n => cfg_err_locked_n ,
- cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header ,
- cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n ,
- cfg_interrupt_n => cfg_interrupt_n ,
- cfg_interrupt_rdy_n => cfg_interrupt_rdy_n ,
- cfg_interrupt_assert_n => cfg_interrupt_assert_n ,
- cfg_interrupt_di => cfg_interrupt_di ,
- cfg_interrupt_do => cfg_interrupt_do ,
- cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
- cfg_interrupt_msienable => cfg_interrupt_msienable ,
- cfg_interrupt_msixenable => cfg_interrupt_msixenable ,
- cfg_interrupt_msixfm => cfg_interrupt_msixfm ,
- cfg_turnoff_ok_n => cfg_turnoff_ok_n ,
- cfg_to_turnoff_n => cfg_to_turnoff_n ,
- cfg_trn_pending_n => cfg_trn_pending_n ,
- cfg_pm_wake_n => cfg_pm_wake_n ,
- cfg_bus_number => cfg_bus_number ,
- cfg_device_number => cfg_device_number ,
- cfg_function_number => cfg_function_number ,
- cfg_status => cfg_status ,
- cfg_command => cfg_command ,
- cfg_dstatus => cfg_dstatus ,
- cfg_dcommand => cfg_dcommand ,
- cfg_lstatus => cfg_lstatus ,
- cfg_lcommand => cfg_lcommand ,
- cfg_dcommand2 => cfg_dcommand2 ,
- cfg_pcie_link_state_n => cfg_pcie_link_state_n ,
- cfg_dsn => cfg_dsn ,
-
- ---------------------------------------------------------
- -- 4. Physical Layer Control and Status (PL) Interface
- ---------------------------------------------------------
-
- pl_initial_link_width => pl_initial_link_width ,
- pl_lane_reversal_mode => pl_lane_reversal_mode ,
- pl_link_gen2_capable => pl_link_gen2_capable ,
- pl_link_partner_gen2_supported => pl_link_partner_gen2_supported ,
- pl_link_upcfg_capable => pl_link_upcfg_capable ,
- pl_ltssm_state => pl_ltssm_state ,
- pl_received_hot_rst => pl_received_hot_rst ,
- pl_sel_link_rate => pl_sel_link_rate ,
- pl_sel_link_width => pl_sel_link_width ,
- pl_directed_link_auton => pl_directed_link_auton ,
- pl_directed_link_change => pl_directed_link_change ,
- pl_directed_link_speed => pl_directed_link_speed ,
- pl_directed_link_width => pl_directed_link_width ,
- pl_upstream_prefer_deemph => pl_upstream_prefer_deemph ,
-
- ---------------------------------------------------------
- -- 5. System (SYS) Interface
- ---------------------------------------------------------
-
- sys_clk => sys_clk_c ,
- sys_reset_n => sys_reset_n_c
-
-);
-
- end generate;
-
-
- DAQ_irq <= eb_empty;
-
-
--- ---------------------------------------------------------------
--- tlp control module
---
- trn_rrem_n(7 downto 1) <= X"0" & trn_rrem_n(0) & trn_rrem_n(0) & trn_rrem_n(0);
-
- theTlpControl:
- tlpControl
- port map (
-
- mbuf_UserFull => '0' ,
- trn_Blinker => trn_Blinker ,
-
- -- DCB protocol interface
- protocol_link_act => protocol_link_act , -- IN std_logic_vector(2-1 downto 0);
- protocol_rst => protocol_rst , -- OUT std_logic;
-
- Link_Buf_Full => daq_rstop , -- IN std_logic;
-
- -- Interrupter triggers
- DAQ_irq => DAQ_irq , -- IN std_logic;
- CTL_irq => CTL_irq , -- IN std_logic;
- DLM_irq => DLM_irq , -- IN std_logic;
-
- -- Fabric side: CTL Rx
- ctl_rv => ctl_rv , -- OUT std_logic;
- ctl_rd => ctl_rd , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Fabric side: CTL Tx
- ctl_ttake => ctl_ttake , -- OUT std_logic;
- ctl_tv => ctl_tv , -- IN std_logic;
- ctl_td => ctl_td , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
- ctl_tstop => ctl_tstop , -- OUT std_logic;
-
- ctl_reset => ctl_reset , -- OUT std_logic;
- ctl_status => ctl_status , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Fabric side: DLM Rx
- dlm_rv => dlm_rv , -- OUT std_logic;
- dlm_rd => dlm_rd , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Fabric side: DLM Tx
- dlm_tv => dlm_tv , -- IN std_logic;
- dlm_td => dlm_td , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Event Buffer FIFO interface
- eb_FIFO_we => eb_we , -- OUT std_logic;
- eb_FIFO_wsof => eb_wsof , -- OUT std_logic;
- eb_FIFO_weof => eb_weof , -- OUT std_logic;
- eb_FIFO_din => eb_din(C_DBUS_WIDTH-1 downto 0) , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- eb_FIFO_re => eb_re , -- OUT std_logic;
- eb_FIFO_empty => eb_empty , -- IN std_logic;
- eb_FIFO_qout => eb_dout(C_DBUS_WIDTH-1 downto 0) , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- eb_FIFO_data_count => eb_data_count , -- IN std_logic_vector(C_FIFO_DC_WIDTH downto 0);
-
- eb_FIFO_ow => eb_FIFO_ow , -- IN std_logic;
-
- pio_reading_status => pio_reading_status , -- OUT std_logic;
-
- eb_FIFO_Status => eb_FIFO_Status , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- eb_FIFO_Rst => eb_rst , -- OUT std_logic;
-
- -- Debugging signals
- DMA_us_Done => LEDs_IO_pin(7) , -- OUT std_logic;
- DMA_us_Busy => open , -- OUT std_logic;
- DMA_us_Busy_LED => LEDs_IO_pin(6) , -- OUT std_logic;
- DMA_ds_Done => LEDs_IO_pin(5) , -- OUT std_logic;
- DMA_ds_Busy => open , -- OUT std_logic;
- DMA_ds_Busy_LED => LEDs_IO_pin(4) , -- OUT std_logic;
-
- -------------------
- -- DDR Interface
- DDR_Ready => DDR_Ready , -- IN std_logic;
-
- DDR_wr_sof => DDR_wr_sof , -- OUT std_logic;
- DDR_wr_eof => DDR_wr_eof , -- OUT std_logic;
- DDR_wr_v => DDR_wr_v , -- OUT std_logic;
- DDR_wr_FA => DDR_wr_FA , -- OUT std_logic;
- DDR_wr_Shift => DDR_wr_Shift , -- OUT std_logic;
- DDR_wr_Mask => DDR_wr_Mask , -- OUT std_logic_vector(2-1 downto 0);
- DDR_wr_din => DDR_wr_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- DDR_wr_full => DDR_wr_full , -- IN std_logic;
-
- DDR_rdc_sof => DDR_rdc_sof , -- OUT std_logic;
- DDR_rdc_eof => DDR_rdc_eof , -- OUT std_logic;
- DDR_rdc_v => DDR_rdc_v , -- OUT std_logic;
- DDR_rdc_FA => DDR_rdc_FA , -- OUT std_logic;
- DDR_rdc_Shift => DDR_rdc_Shift , -- OUT std_logic;
- DDR_rdc_din => DDR_rdc_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- DDR_rdc_full => DDR_rdc_full , -- IN std_logic;
-
--- DDR_rdD_sof => DDR_rdD_sof , -- IN std_logic;
--- DDR_rdD_eof => DDR_rdD_eof , -- IN std_logic;
--- DDR_rdDout_V => DDR_rdDout_V , -- IN std_logic;
--- DDR_rdDout => DDR_rdDout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- DDR payload FIFO Read Port
- DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- OUT std_logic;
- DDR_FIFO_Empty => DDR_FIFO_Empty , -- IN std_logic;
- DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- Data generator table write
- tab_we => tab_we , -- OUT std_logic_vector(2-1 downto 0);
- tab_wa => tab_wa , -- OUT std_logic_vector(12-1 downto 0);
- tab_wd => tab_wd , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- DG_is_Running => dg_running , -- IN std_logic;
- DG_Reset => dg_rst , -- OUT STD_LOGIC;
- DG_Mask => dg_mask , -- OUT STD_LOGIC
-
- -------------------
- -- Transaction Interface
- trn_lnk_up_n => trn_lnk_up_n ,
- trn_rsrc_dsc_n => trn_rsrc_dsc_n ,
- trn_rnp_ok_n => trn_rnp_ok_n ,
- trn_tsrc_dsc_n => trn_tsrc_dsc_n ,
- trn_tdst_dsc_n => trn_tdst_dsc_n ,
- trn_tbuf_av => trn_tbuf_av ,
- trn_terrfwd_n => trn_terrfwd_n ,
-
- trn_clk => trn_clk ,
- trn_reset_n => trn_reset_n ,
- trn_rsrc_rdy_n => trn_rsrc_rdy_n ,
- trn_tdst_rdy_n => trn_tdst_rdy_n ,
- trn_rsof_n => trn_rsof_n ,
- trn_reof_n => trn_reof_n ,
- trn_rerrfwd_n => trn_rerrfwd_n ,
- trn_rrem_n => trn_rrem_n ,
- trn_rd => trn_rd ,
-
- cfg_interrupt_n => cfg_interrupt_n ,
- cfg_interrupt_rdy_n => cfg_interrupt_rdy_n ,
- cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
- cfg_interrupt_msienable => cfg_interrupt_msienable ,
- cfg_interrupt_di => cfg_interrupt_di ,
- cfg_interrupt_do => cfg_interrupt_do ,
- cfg_interrupt_assert_n => cfg_interrupt_assert_n ,
-
- trn_rbar_hit_n => trn_rbar_hit_n ,
- trn_tsrc_rdy_n => trn_tsrc_rdy_n ,
- trn_rdst_rdy_n => trn_rdst_rdy_n ,
- trn_tsof_n => trn_tsof_n ,
- trn_teof_n => trn_teof_n ,
- trn_trem_n => trn_trem_n ,
- trn_td => trn_td ,
-
- Format_Shower => Format_Shower ,
-
- cfg_dcommand => cfg_dcommand ,
- pcie_link_width => pcie_link_width ,
- localId => localId
- );
-
-
- -- -----------------------------------------------------------------------
- -- DDR SDRAM control module
- --
- DDRs_ctrl_module:
- bram_DDRs_Control
- GENERIC MAP (
- C_ASYNFIFO_WIDTH => 72 ,
- P_SIMULATION => FALSE
- )
- PORT MAP(
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- DDR_wr_sof => DDR_wr_sof , -- IN std_logic;
- DDR_wr_eof => DDR_wr_eof , -- IN std_logic;
- DDR_wr_v => DDR_wr_v , -- IN std_logic;
- DDR_wr_FA => DDR_wr_FA , -- IN std_logic;
- DDR_wr_Shift => DDR_wr_Shift , -- IN std_logic;
- DDR_wr_Mask => DDR_wr_Mask , -- IN std_logic_vector(2-1 downto 0);
- DDR_wr_din => DDR_wr_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- DDR_wr_full => DDR_wr_full , -- OUT std_logic;
-
- DDR_rdc_sof => DDR_rdc_sof , -- IN std_logic;
- DDR_rdc_eof => DDR_rdc_eof , -- IN std_logic;
- DDR_rdc_v => DDR_rdc_v , -- IN std_logic;
- DDR_rdc_FA => DDR_rdc_FA , -- IN std_logic;
- DDR_rdc_Shift => DDR_rdc_Shift , -- IN std_logic;
- DDR_rdc_din => DDR_rdc_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- DDR_rdc_full => DDR_rdc_full , -- OUT std_logic;
-
--- DDR_rdD_sof => DDR_rdD_sof , -- OUT std_logic;
--- DDR_rdD_eof => DDR_rdD_eof , -- OUT std_logic;
--- DDR_rdDout_V => DDR_rdDout_V , -- OUT std_logic;
--- DDR_rdDout => DDR_rdDout , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- DDR payload FIFO Read Port
- DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- IN std_logic;
- DDR_FIFO_Empty => DDR_FIFO_Empty , -- OUT std_logic;
- DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- Common interface
- DDR_Ready => DDR_Ready , -- OUT std_logic;
- DDR_Blinker => DDR_Blinker , -- OUT std_logic;
- mem_clk => trn_clk, -- mem_clk , -- IN
- trn_clk => trn_clk , -- IN std_logic;
- trn_reset_n => trn_reset_n -- IN std_logic
- );
-
-
-
- --
- -- Event Buffer wrapper
- --
- Pseudo_EB: if not USE_DDR2_MODULE generate
-
-
- LEDs_IO_pin(0) <= trn_reset_n xor Format_Shower;
- LEDs_IO_pin(1) <= trn_lnk_up_n;
- LEDs_IO_pin(2) <= link_active(0);
- LEDs_IO_pin(3) <= trn_Blinker ; -- link_active(1); -- dg_debug_led;
-
-
- event_buffer0:
- eb_wrapper
- port map (
- wr_clk => trn_clk , -- eb_wclk ,
- wr_en => eb_we_up ,
- din => eb_din_up ,
- pfull => eb_pfull ,
- full => eb_full ,
-
- rd_clk => trn_clk , -- eb_rclk ,
- rd_en => eb_re ,
- dout => eb_dout ,
- pempty => eb_pempty ,
- empty => eb_empty ,
-
- data_count => eb_data_count(C_EMU_FIFO_DC_WIDTH-1+1 downto 1) ,
- rst => eb_rst
- );
-
--- eb_FIFO_Status(C_FIFO_DC_WIDTH+2) <= '0';
- eb_data_count(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1)
- <= C_ALL_ZEROS(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1);
- eb_data_count(0) -- 64 bits to 32 bits transformation
- <= '0';
- fifo_reset_done <= not eb_rst;
-
- end generate;
-
-
-
--- eb_wclk <= trn_clk;
--- eb_rclk <= trn_clk;
- eb_din(72-1 downto C_DBUS_WIDTH) <= (OTHERS=>'0');
- eb_FIFO_Status(C_DBUS_WIDTH-1 downto C_FIFO_DC_WIDTH+3)
- <= (OTHERS=>'0');
- eb_FIFO_Status(C_FIFO_DC_WIDTH+2 downto 3)
- <= eb_data_count(C_FIFO_DC_WIDTH downto 1);
- eb_FIFO_Status(2) <= '0'; -- daq_rstop;
- eb_FIFO_Status(1) <= eb_pfull;
- eb_FIFO_Status(0) <= eb_empty and fifo_reset_done;
- eb_FIFO_ow <= eb_we_up and eb_full;
-
-
- --
- -- .......................
- --
-
- daq_rv <= eb_we;
- daq_rsof <= eb_wsof;
- daq_reof <= eb_weof;
- daq_rd <= eb_din(C_DBUS_WIDTH-1 downto 0);
-
- eb_we_up <= daq_tv;
- eb_din_up <= C_ALL_ZEROS(72-1 downto C_DBUS_WIDTH+2) & daq_tsof & daq_teof & daq_td;
- daq_tstop <= eb_pfull;
-
-
- --
- -- Protocol Interface
- --
- ABB_DCB_Interface0:
- protocol_IF
- port map (
- -- DAQ Tx
- data2send_start => data2send_start , -- OUT std_logic;
- data2send_end => data2send_end , -- OUT std_logic;
- data2send => data2send , -- OUT std_logic_vector(16-1 downto 0);
- crc_error_send => crc_error_send , -- OUT std_logic;
- data2send_stop => data2send_stop , -- IN std_logic;
-
- -- DAQ Rx
- data_rec_start => data_rec_start , -- IN std_logic;
- data_rec_end => data_rec_end , -- IN std_logic;
- data_rec => data_rec , -- IN std_logic_vector(16-1 downto 0);
- crc_error_rec => crc_error_rec , -- IN std_logic;
- data_rec_stop => data_rec_stop , -- OUT std_logic;
-
- -- CTL Tx
- ctrl2send_start => ctrl2send_start , -- OUT std_logic;
- ctrl2send_end => ctrl2send_end , -- OUT std_logic;
- ctrl2send => ctrl2send , -- OUT std_logic_vector(16-1 downto 0);
- ctrl2send_stop => ctrl2send_stop , -- IN std_logic;
-
- -- CTL Rx
- ctrl_rec_start => ctrl_rec_start , -- IN std_logic;
- ctrl_rec_end => ctrl_rec_end , -- IN std_logic;
- ctrl_rec => ctrl_rec , -- IN std_logic_vector(16-1 downto 0);
- ctrl_rec_stop => ctrl_rec_stop , -- OUT std_logic;
-
- -- DLM Tx
- dlm2send_va => dlm2send_va , -- OUT std_logic;
- dlm2send_type => dlm2send_type , -- OUT std_logic_vector(4-1 downto 0);
-
- -- DLM Rx
- dlm_rec_va => dlm_rec_va , -- IN std_logic;
- dlm_rec_type => dlm_rec_type , -- IN std_logic_vector(4-1 downto 0);
-
- -- Common signals
- link_tx_clk => link_tx_clk , -- IN std_logic;
- link_rx_clk => link_rx_clk , -- IN std_logic;
- link_active => link_active , -- IN std_logic_vector(2-1 downto 0);
- protocol_clk => protocol_clk , -- OUT std_logic;
- protocol_res_n => protocol_res_n , -- OUT std_logic;
-
-
- -- Fabric side: DAQ Rx
- daq_rv => daq_rv , -- IN std_logic;
- daq_rsof => daq_rsof , -- IN std_logic;
- daq_reof => daq_reof , -- IN std_logic;
- daq_rd => daq_rd , -- IN std_logic_vector(64-1 downto 0);
- daq_rstop => daq_rstop , -- OUT std_logic;
-
- -- Fabric side: DAQ Tx
- daq_tv => daq_tv , -- OUT std_logic;
- daq_tsof => daq_tsof , -- OUT std_logic;
- daq_teof => daq_teof , -- OUT std_logic;
- daq_td => daq_td , -- OUT std_logic_vector(64-1 downto 0);
- daq_tstop => daq_tstop , -- IN std_logic;
-
- -- Fabric side: CTL Rx
- ctl_rv => ctl_rv , -- IN std_logic;
- ctl_rd => ctl_rd , -- IN std_logic_vector(32-1 downto 0);
- ctl_rstop => ctl_rstop , -- OUT std_logic;
-
- -- Fabric side: CTL Tx
- ctl_ttake => ctl_ttake , -- IN std_logic;
- ctl_tv => ctl_tv , -- OUT std_logic;
- ctl_td => ctl_td , -- OUT std_logic_vector(32-1 downto 0);
- ctl_tstop => ctl_tstop , -- IN std_logic;
-
- ctl_reset => ctl_reset , -- IN std_logic;
- ctl_status => ctl_status , -- OUT std_logic_vector(32-1 downto 0);
-
- -- Fabric side: DLM Rx
- dlm_rv => dlm_rv , -- IN std_logic;
- dlm_rd => dlm_rd , -- IN std_logic_vector(4-1 downto 0);
-
- -- Fabric side: DLM Tx
- dlm_tv => dlm_tv , -- OUT std_logic;
- dlm_td => dlm_td , -- OUT std_logic_vector(4-1 downto 0);
-
- -- Interrupter triggers
- DAQ_irq => open, -- DAQ_irq , -- OUT std_logic;
- CTL_irq => CTL_irq , -- OUT std_logic;
- DLM_irq => DLM_irq , -- OUT std_logic;
-
- -- Data generator table write port
- tab_sel => '1' , -- IN STD_LOGIC;
- tab_we => tab_we , -- IN STD_LOGIC_VECTOR (2-1 downto 0);
- tab_wa => tab_wa , -- IN STD_LOGIC_VECTOR (12-1 downto 0);
- tab_wd => tab_wd , -- IN STD_LOGIC_VECTOR (64-1 downto 0);
-
- -- DG control/status signal
- dg_running => dg_running , -- OUT STD_LOGIC;
- dg_mask => dg_mask , -- IN STD_LOGIC;
- dg_rst => dg_rst , -- IN STD_LOGIC
-
- -- DG debug signal
- daq_start_led => dg_debug_led , -- OUT STD_LOGIC;
-
- -- Fabric side: Common signals
- trn_clk => trn_clk , -- IN std_logic;
- protocol_link_act => protocol_link_act , -- OUT std_logic_vector(2-1 downto 0);
- protocol_rst => protocol_rst -- IN std_logic
- );
-
-
- --
- -- Module emulating the link
- --
- Gen_EMU_Links: if not USE_OPTO_LINKS generate
-
- DCB_Link_module0:
- pseudo_protocol_module
- port map (
- -- DAQ Tx
- data2send_start => data2send_start , -- IN std_logic;
- data2send_end => data2send_end , -- IN std_logic;
- data2send => data2send , -- IN std_logic_vector(16-1 downto 0);
- crc_error_send => crc_error_send , -- IN std_logic;
- data2send_stop => data2send_stop , -- OUT std_logic;
-
- -- DAQ Rx
- data_rec_start => data_rec_start , -- OUT std_logic;
- data_rec_end => data_rec_end , -- OUT std_logic;
- data_rec => data_rec , -- OUT std_logic_vector(16-1 downto 0);
- crc_error_rec => crc_error_rec , -- OUT std_logic;
- data_rec_stop => data_rec_stop , -- IN std_logic;
-
- -- CTL Tx
- ctrl2send_start => ctrl2send_start , -- IN std_logic;
- ctrl2send_end => ctrl2send_end , -- IN std_logic;
- ctrl2send => ctrl2send , -- IN std_logic_vector(16-1 downto 0);
- ctrl2send_stop => ctrl2send_stop , -- OUT std_logic;
-
- -- CTL Rx
- ctrl_rec_start => ctrl_rec_start , -- OUT std_logic;
- ctrl_rec_end => ctrl_rec_end , -- OUT std_logic;
- ctrl_rec => ctrl_rec , -- OUT std_logic_vector(16-1 downto 0);
- ctrl_rec_stop => ctrl_rec_stop , -- IN std_logic;
-
- -- DLM Tx
- dlm2send_va => dlm2send_va , -- IN std_logic;
- dlm2send_type => dlm2send_type , -- IN std_logic_vector(4-1 downto 0);
-
- -- DLM Rx
- dlm_rec_va => dlm_rec_va , -- OUT std_logic;
- dlm_rec_type => dlm_rec_type , -- OUT std_logic_vector(4-1 downto 0);
-
- -- dummy pin input !!!! not really exists
- dummy_pin_in => "000", -- dummy_pin_in , -- IN std_logic_vector(3-1 downto 0);
--- dummy_pin_in => dummy_pin_in , -- IN std_logic_vector(3-1 downto 0);
-
- -- Common interface
- link_tx_clk => link_tx_clk , -- OUT std_logic;
- link_rx_clk => link_rx_clk , -- OUT std_logic;
- link_active => link_active , -- OUT std_logic_vector(2-1 downto 0);
- clk => protocol_clk , -- IN std_logic;
- res_n => protocol_res_n -- IN std_logic
- );
-
-
- end generate;
-
-
-end Behavioral;
Index: branches/Virtex6/ML605/v6_pcie_v1_3/v6_pcie_readme.txt
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/v6_pcie_readme.txt (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/v6_pcie_readme.txt (nonexistent)
@@ -1,239 +0,0 @@
-
- Core name: Xilinx Virtex-6 Integrated Block for PCI Express
- Version: 1.3
- Release Date: September 16, 2009
-
-
-================================================================================
-
-This document contains the following sections:
-
-1. Introduction
-2. New Features
-3. Resolved Issues
-4. Known Issues
-5. Technical Support
-6. Other Information
-7. Core Release History
-8. Legal Disclaimer
-
-================================================================================
-
-1. INTRODUCTION
-
-For the most recent updates to the IP installation instructions for this core,
-please go to:
-
- http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
-
-
-For system requirements:
-
- http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
-
-
-This file contains release notes for the Xilinx LogiCORE(TM) IP Virtex-6
-Integrated Block for PCI Express v1.3 solution. For the latest core updates,
-see the product page at:
-
- http://www.xilinx.com/products/ipcenter/V6_PCI_Express_Block.htm
-
-
-2. NEW FEATURES
-
- - ISE 11.3 software support
- - Virtex-6 Integrated Block for PCI Express Root Port support
- - Implementation support for 512 Bytes MPS configuration for the 8-lane Gen2
- product.
- - Implementation support for all part/packages for the 8-lane Gen2 product
- - Added support for 6VHX380T-FF1155-1.
-
-
-3. RESOLVED ISSUES
-
- - Error in generating core from ISE New source Wizard
- o CR 517195
-
- Issue resolved where ProjNav would error out with a Tcl scripting error when
- attempting to generate the core from ISE New Source Wizard.
-
- - Incorrect UCF path in implement.bat file
- o CR 523072
-
- Issue resolved where the relative path to UCF in implement.bat is incorrect,
- when design is generated and implemented on Windows operating systems.
-
- - BUFG driving MMCM clkin removed
- o CR 511334
-
- The BUFG driving the MMCM clkin was removed, to reduce the number of BUFGs
- used in the design.
-
- - Root Port operation now supported in this release.
- o CR 509679
-
- Support added for Root Port operation of the PCIe Integrated Block.
-
- - FIFO_LIMIT setting could cause throttling on Transaction Transmit interface
- for the 8-lane Gen2 operation only
- o CR 524324
-
- Issue resolved where the FIFO_LIMIT setting in the 8-lane Gen2 product
- was not high enough and could cause throttling on the Transaction transmit
- interface.
-
- - Incorrect cfg_trn_pending_n functionality
- o CR 524835
-
- Issue resolved where the cfg_trn_pending_n output of the core was inverted.
-
- - Implementation support for the 8-lane Gen2 product with 512 Bytes Max
- Payload Size Configuration
- o CR 522979
-
- Implementation support is now available for the 8-lane Gen 2 product with
- 512 Bytes Max Payload Size Configuration
-
- - Support for Non-default User Interface frequency when the Xilinx Development
- Board selected is "ML 605"
- o CR 522735
-
- Implementation support is now available for non-default User Interface
- frequency when the Xilinx Development Board selected is "ML 605".
-
- - Support for Programmed Power Management (PPM) state L1 for the 8-lane Gen2
- product
- o CR 522902
-
- Programmed Power Management (PPM) state L1 is now supported for the 8-lane
- Gen2 product
-
- - trn_reof_n assertion without a trn_rsof_n assertion on Receive Transaction
- Interface in the 8-lane Gen2 product, when receiving back-to-back
- Transactions.
- o CR 522593
-
- Issue resolved where trn_reof_n might assert without trn_rsof_n assertion
- if trn_rsrc_rdy_n were deasserted while a packet was being written into
- the internal FIFO.
-
- - Requirement added for trn_tsrc_dsc_n assertion to be accompanied by
- trn_teof_n assertion in the 8-lane Gen2 product
- o CR 525136
-
- The 8-lane Gen2 product now requires trn_tsrc_dsc_n assertion to be
- accompanied by trn_teof_n assertion.
-
- - Transmit Transaction interface lock-up in the 8-lane Gen2 product.
- o CR 525691
-
- Issue resolved where the Transmit Transaction interface locks up on an
- assertion of trn_teof_n, which is not qualified by trn_tsrc_rdy_n, in the
- 8-lane Gen2 product.
-
-4. KNOWN ISSUES
-
- The following are known issues for v1.3 of this core at time of release:
-
- - Virtex-6 solutions are pending hardware validation.
-
- - trn_rnp_ok_n not supported in the 8-lane Gen2 Integrated Block
- o CR 518631
-
- Use of trn_rnp_ok_n is not supported in the 8-lane Gen 2 Integrated Block
- for PCI Express product.
-
- Workaround : None
-
- - Gen2 operation only supported with 250 MHz Reference Clock.
- o CR 522983
-
- Gen 2 operation is only supported with 250 MHz Reference Clock.
-
- Workaround : Use an external PLL to convert 100 MHz clock to 250 MHz.
- Contact Xilinx Support.
-
- - VHDL example design / testbench not supported.
- o CR 510476
-
- VHDL example design and testbench are not supported in the 11.2 release
-
- Workaround : None. Planned release in 11.4.
-
- The most recent information, including known issues, workarounds, and
- resolutions for this version is provided in the IP Release Notes Guide located at
-
- http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf
-
-5. TECHNICAL SUPPORT
-
- To obtain technical support, create a WebCase at www.xilinx.com/support.
- Questions are routed to a team with expertise using this product.
-
- Xilinx provides technical support for use of this product when used
- according to the guidelines described in the core documentation, and
- cannot guarantee timing, functionality, or support of this product for
- designs that do not follow specified guidelines.
-
-
-6. OTHER INFORMATION
-
- In this release, the only supported synthesis tool is XST.
- Additionally, only Verilog simulation and example design files are provided.
-
-7. CORE RELEASE HISTORY
-
-Date By Version Description
-================================================================================
-09/16/2009 Xilinx, Inc. 1.3 11.3 support
-06/24/2009 Xilinx, Inc. 1.2 11.2 support
-04/24/2009 Xilinx, Inc. 1.1 Initial release (BETA)
-================================================================================
-
-8. Legal Disclaimer
-
-(c) Copyright 2009 Xilinx, Inc. All rights reserved.
-
-This file contains confidential and proprietary information
-of Xilinx, Inc. and is protected under U.S. and
-international copyright and other intellectual property
-laws.
---
-DISCLAIMER
-This disclaimer is not a license and does not grant any
-rights to the materials distributed herewith. Except as
-otherwise provided in a valid license issued to you by
-Xilinx, and to the maximum extent permitted by applicable
-law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-(2) Xilinx shall not be liable (whether in contract or tort,
-including negligence, or under any other theory of
-liability) for any loss or damage of any kind or nature
-related to, arising under or in connection with these
-materials, including for any direct, or any indirect,
-special, incidental, or consequential loss or damage
-(including loss of data, profits, goodwill, or any type of
-loss or damage suffered as a result of any action brought
-by a third party) even if such damage or loss was
-reasonably foreseeable or Xilinx had been advised of the
-possibility of the same.
---
-CRITICAL APPLICATIONS
-Xilinx products are not designed or intended to be fail-
-safe, or for use in any application requiring fail-safe
-performance, such as life-support or safety devices or
-systems, Class III medical devices, nuclear facilities,
-applications related to the deployment of airbags, or any
-other applications that could lead to death, personal
-injury, or severe property or environmental damage
-individually and collectively, "Critical
-Applications"). Customer assumes the sole risk and
-liability of any use of Xilinx products in Critical
-Applications, subject only to applicable laws and
-regulations governing limitations on product liability.
---
-THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-PART OF THIS FILE AT ALL TIMES.
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_2_0_v6.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_2_0_v6.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_2_0_v6.v (nonexistent)
@@ -1,1914 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : pcie_2_0_v6.v
-//-- Description: Solution wrapper for Virtex6 Hard Block for PCI Express
-//--
-//--
-//--
-//--------------------------------------------------------------------------------
-`timescale 1ps/1ps
-
-(* X_CORE_INFO = "v6_pcie_v1_3, Coregen 11.3" *)
-module pcie_2_0_v6 #(
- parameter TCQ = 1,
- parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
- parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
- parameter AER_BASE_PTR = 12'h128,
- parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
- parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
- parameter AER_CAP_ID = 16'h0001,
- parameter AER_CAP_INT_MSG_NUM_MSI = 5'h0a,
- parameter AER_CAP_INT_MSG_NUM_MSIX = 5'h15,
- parameter AER_CAP_NEXTPTR = 12'h160,
- parameter AER_CAP_ON = "FALSE",
- parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
- parameter AER_CAP_VERSION = 4'h1,
- parameter ALLOW_X8_GEN2 = "TRUE",
- parameter BAR0 = 32'hffffff00,
- parameter BAR1 = 32'hffff0000,
- parameter BAR2 = 32'hffff000c,
- parameter BAR3 = 32'hffffffff,
- parameter BAR4 = 32'h00000000,
- parameter BAR5 = 32'h00000000,
- parameter CAPABILITIES_PTR = 8'h40,
- parameter CARDBUS_CIS_POINTER = 32'h00000000,
- parameter CLASS_CODE = 24'h000000,
- parameter CMD_INTX_IMPLEMENTED = "TRUE",
- parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
- parameter CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0,
- parameter CRM_MODULE_RSTS = 7'h00,
- parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
- parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
- parameter DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
- parameter DEV_CAP_ENDPOINT_L1_LATENCY = 0,
- parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
- parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
- parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
- parameter DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
- parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
- parameter DEV_CAP_RSVD_14_12 = 0,
- parameter DEV_CAP_RSVD_17_16 = 0,
- parameter DEV_CAP_RSVD_31_29 = 0,
- parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
- parameter DEVICE_ID = 16'h0007,
- parameter DISABLE_ASPM_L1_TIMER = "FALSE",
- parameter DISABLE_BAR_FILTERING = "FALSE",
- parameter DISABLE_ID_CHECK = "FALSE",
- parameter DISABLE_LANE_REVERSAL = "FALSE",
- parameter DISABLE_RX_TC_FILTER = "FALSE",
- parameter DISABLE_SCRAMBLING = "FALSE",
- parameter DNSTREAM_LINK_NUM = 8'h00,
- parameter DSN_BASE_PTR = 12'h100,
- parameter DSN_CAP_ID = 16'h0003,
- parameter DSN_CAP_NEXTPTR = 12'h000,
- parameter DSN_CAP_ON = "TRUE",
- parameter DSN_CAP_VERSION = 4'h1,
- parameter ENABLE_MSG_ROUTE = 11'h000,
- parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
- parameter ENTER_RVRY_EI_L0 = "TRUE",
- parameter EXPANSION_ROM = 32'hfffff001,
- parameter EXT_CFG_CAP_PTR = 6'h3f,
- parameter EXT_CFG_XP_CAP_PTR = 10'h3ff,
- parameter HEADER_TYPE = 8'h00,
- parameter INFER_EI = 5'h00,
- parameter INTERRUPT_PIN = 8'h01,
- parameter IS_SWITCH = "FALSE",
- parameter LAST_CONFIG_DWORD = 10'h042,
- parameter LINK_CAP_ASPM_SUPPORT = 1,
- parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
- parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
- parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
- parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
- parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
- parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
- parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
- parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
- parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
- parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
- parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
- parameter LINK_CAP_MAX_LINK_SPEED = 4'h1,
- parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08,
- parameter LINK_CAP_RSVD_23_22 = 0,
- parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
- parameter LINK_CONTROL_RCB = 0,
- parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
- parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
- parameter LINK_CTRL2_TARGET_LINK_SPEED = 4'h0,
- parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
- parameter LL_ACK_TIMEOUT = 15'h0204,
- parameter LL_ACK_TIMEOUT_EN = "FALSE",
- parameter LL_ACK_TIMEOUT_FUNC = 0,
- parameter LL_REPLAY_TIMEOUT = 15'h060d,
- parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
- parameter LL_REPLAY_TIMEOUT_FUNC = 0,
- parameter LTSSM_MAX_LINK_WIDTH = LINK_CAP_MAX_LINK_WIDTH,
- parameter MSI_BASE_PTR = 8'h48,
- parameter MSI_CAP_ID = 8'h05,
- parameter MSI_CAP_MULTIMSGCAP = 0,
- parameter MSI_CAP_MULTIMSG_EXTENSION = 0,
- parameter MSI_CAP_NEXTPTR = 8'h60,
- parameter MSI_CAP_ON = "FALSE",
- parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE",
- parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
- parameter MSIX_BASE_PTR = 8'h9c,
- parameter MSIX_CAP_ID = 8'h11,
- parameter MSIX_CAP_NEXTPTR = 8'h00,
- parameter MSIX_CAP_ON = "FALSE",
- parameter MSIX_CAP_PBA_BIR = 0,
- parameter MSIX_CAP_PBA_OFFSET = 29'h00000050,
- parameter MSIX_CAP_TABLE_BIR = 0,
- parameter MSIX_CAP_TABLE_OFFSET = 29'h00000040,
- parameter MSIX_CAP_TABLE_SIZE = 11'h000,
- parameter N_FTS_COMCLK_GEN1 = 255,
- parameter N_FTS_COMCLK_GEN2 = 255,
- parameter N_FTS_GEN1 = 255,
- parameter N_FTS_GEN2 = 255,
- parameter PCIE_BASE_PTR = 8'h60,
- parameter PCIE_CAP_CAPABILITY_ID = 8'h10,
- parameter PCIE_CAP_CAPABILITY_VERSION = 4'h2,
- parameter PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
- parameter PCIE_CAP_INT_MSG_NUM = 5'h00,
- parameter PCIE_CAP_NEXTPTR = 8'h00,
- parameter PCIE_CAP_ON = "TRUE",
- parameter PCIE_CAP_RSVD_15_14 = 0,
- parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
- parameter PCIE_REVISION = 2,
- parameter PGL0_LANE = 0,
- parameter PGL1_LANE = 1,
- parameter PGL2_LANE = 2,
- parameter PGL3_LANE = 3,
- parameter PGL4_LANE = 4,
- parameter PGL5_LANE = 5,
- parameter PGL6_LANE = 6,
- parameter PGL7_LANE = 7,
- parameter PL_AUTO_CONFIG = 0,
- parameter PL_FAST_TRAIN = "FALSE",
- parameter PM_BASE_PTR = 8'h40,
- parameter PM_CAP_AUXCURRENT = 0,
- parameter PM_CAP_DSI = "FALSE",
- parameter PM_CAP_D1SUPPORT = "TRUE",
- parameter PM_CAP_D2SUPPORT = "TRUE",
- parameter PM_CAP_ID = 8'h01,
- parameter PM_CAP_NEXTPTR = 8'h48,
- parameter PM_CAP_ON = "TRUE",
- parameter PM_CAP_PME_CLOCK = "FALSE",
- parameter PM_CAP_PMESUPPORT = 5'h0f,
- parameter PM_CAP_RSVD_04 = 0,
- parameter PM_CAP_VERSION = 3,
- parameter PM_CSR_BPCCEN = "FALSE",
- parameter PM_CSR_B2B3 = "FALSE",
- parameter PM_CSR_NOSOFTRST = "TRUE",
- parameter PM_DATA_SCALE0 = 2'h1,
- parameter PM_DATA_SCALE1 = 2'h1,
- parameter PM_DATA_SCALE2 = 2'h1,
- parameter PM_DATA_SCALE3 = 2'h1,
- parameter PM_DATA_SCALE4 = 2'h1,
- parameter PM_DATA_SCALE5 = 2'h1,
- parameter PM_DATA_SCALE6 = 2'h1,
- parameter PM_DATA_SCALE7 = 2'h1,
- parameter PM_DATA0 = 8'h01,
- parameter PM_DATA1 = 8'h01,
- parameter PM_DATA2 = 8'h01,
- parameter PM_DATA3 = 8'h01,
- parameter PM_DATA4 = 8'h01,
- parameter PM_DATA5 = 8'h01,
- parameter PM_DATA6 = 8'h01,
- parameter PM_DATA7 = 8'h01,
- parameter RECRC_CHK = 0,
- parameter RECRC_CHK_TRIM = "FALSE",
- parameter REVISION_ID = 8'h00,
- parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
- parameter SELECT_DLL_IF = "FALSE",
- parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
- parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
- parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
- parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
- parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
- parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
- parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
- parameter SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
- parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
- parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
- parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
- parameter SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
- parameter SPARE_BIT0 = 0,
- parameter SPARE_BIT1 = 0,
- parameter SPARE_BIT2 = 0,
- parameter SPARE_BIT3 = 0,
- parameter SPARE_BIT4 = 0,
- parameter SPARE_BIT5 = 0,
- parameter SPARE_BIT6 = 0,
- parameter SPARE_BIT7 = 0,
- parameter SPARE_BIT8 = 0,
- parameter SPARE_BYTE0 = 8'h00,
- parameter SPARE_BYTE1 = 8'h00,
- parameter SPARE_BYTE2 = 8'h00,
- parameter SPARE_BYTE3 = 8'h00,
- parameter SPARE_WORD0 = 32'h00000000,
- parameter SPARE_WORD1 = 32'h00000000,
- parameter SPARE_WORD2 = 32'h00000000,
- parameter SPARE_WORD3 = 32'h00000000,
- parameter SUBSYSTEM_ID = 16'h0007,
- parameter SUBSYSTEM_VENDOR_ID = 16'h10ee,
- parameter TL_RBYPASS = "FALSE",
- parameter TL_RX_RAM_RADDR_LATENCY = 0,
- parameter TL_RX_RAM_RDATA_LATENCY = 2,
- parameter TL_RX_RAM_WRITE_LATENCY = 0,
- parameter TL_TFC_DISABLE = "FALSE",
- parameter TL_TX_CHECKS_DISABLE = "FALSE",
- parameter TL_TX_RAM_RADDR_LATENCY = 0,
- parameter TL_TX_RAM_RDATA_LATENCY = 2,
- parameter TL_TX_RAM_WRITE_LATENCY = 0,
- parameter UPCONFIG_CAPABLE = "TRUE",
- parameter UPSTREAM_FACING = "TRUE",
- parameter EXIT_LOOPBACK_ON_EI = "TRUE",
- parameter UR_INV_REQ = "TRUE",
- parameter USER_CLK_FREQ = 3,
- parameter VC_BASE_PTR = 12'h10c,
- parameter VC_CAP_ID = 16'h0002,
- parameter VC_CAP_NEXTPTR = 12'h000,
- parameter VC_CAP_ON = "FALSE",
- parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
- parameter VC_CAP_VERSION = 4'h1,
- parameter VC0_CPL_INFINITE = "TRUE",
- parameter VC0_RX_RAM_LIMIT = 13'h03ff,
- parameter VC0_TOTAL_CREDITS_CD = 127,
- parameter VC0_TOTAL_CREDITS_CH = 31,
- parameter VC0_TOTAL_CREDITS_NPH = 12,
- parameter VC0_TOTAL_CREDITS_PD = 288,
- parameter VC0_TOTAL_CREDITS_PH = 32,
- parameter VC0_TX_LASTPACKET = 31,
- parameter VENDOR_ID = 16'h10ee,
- parameter VSEC_BASE_PTR = 12'h160,
- parameter VSEC_CAP_HDR_ID = 16'h1234,
- parameter VSEC_CAP_HDR_LENGTH = 12'h018,
- parameter VSEC_CAP_HDR_REVISION = 4'h1,
- parameter VSEC_CAP_ID = 16'h000b,
- parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
- parameter VSEC_CAP_NEXTPTR = 12'h000,
- parameter VSEC_CAP_ON = "FALSE",
- parameter VSEC_CAP_VERSION = 4'h1
-
-)
-(
-
- input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPRXN,
- input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPRXP,
- output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPTXN,
- output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PCIEXPTXP,
-
- input SYSCLK,
- input FUNDRSTN,
-
- output TRNLNKUPN,
- output TRNCLK,
-
- output PHYRDYN,
- output USERRSTN,
- output RECEIVEDFUNCLVLRSTN,
- output LNKCLKEN,
- input SYSRSTN,
- input PLRSTN,
- input DLRSTN,
- input TLRSTN,
- input FUNCLVLRSTN,
- input CMRSTN,
- input CMSTICKYRSTN,
-
- output [6:0] TRNRBARHITN,
- output [63:0] TRNRD,
- output TRNRECRCERRN,
- output TRNREOFN,
- output TRNRERRFWDN,
- output TRNRREMN,
- output TRNRSOFN,
- output TRNRSRCDSCN,
- output TRNRSRCRDYN,
- input TRNRDSTRDYN,
- input TRNRNPOKN,
-
- output [5:0] TRNTBUFAV,
- output TRNTCFGREQN,
-
- output TRNTDLLPDSTRDYN,
- output TRNTDSTRDYN,
- output TRNTERRDROPN,
-
- input TRNTCFGGNTN,
-
- input [63:0] TRNTD,
- input [31:0] TRNTDLLPDATA,
- input TRNTDLLPSRCRDYN,
- input TRNTECRCGENN,
- input TRNTEOFN,
- input TRNTERRFWDN,
- input TRNTREMN,
-
-
- input TRNTSOFN,
- input TRNTSRCDSCN,
- input TRNTSRCRDYN,
- input TRNTSTRN,
-
- output [11:0] TRNFCCPLD,
- output [7:0] TRNFCCPLH,
- output [11:0] TRNFCNPD,
- output [7:0] TRNFCNPH,
- output [11:0] TRNFCPD,
- output [7:0] TRNFCPH,
- input [2:0] TRNFCSEL,
-
- output CFGAERECRCCHECKEN,
- output CFGAERECRCGENEN,
- output CFGCOMMANDBUSMASTERENABLE,
- output CFGCOMMANDINTERRUPTDISABLE,
- output CFGCOMMANDIOENABLE,
- output CFGCOMMANDMEMENABLE,
- output CFGCOMMANDSERREN,
- output CFGDEVCONTROLAUXPOWEREN,
- output CFGDEVCONTROLCORRERRREPORTINGEN,
- output CFGDEVCONTROLENABLERO,
- output CFGDEVCONTROLEXTTAGEN,
- output CFGDEVCONTROLFATALERRREPORTINGEN,
- output [2:0] CFGDEVCONTROLMAXPAYLOAD,
- output [2:0] CFGDEVCONTROLMAXREADREQ,
- output CFGDEVCONTROLNONFATALREPORTINGEN,
- output CFGDEVCONTROLNOSNOOPEN,
- output CFGDEVCONTROLPHANTOMEN,
- output CFGDEVCONTROLURERRREPORTINGEN,
- output CFGDEVCONTROL2CPLTIMEOUTDIS,
- output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL,
- output CFGDEVSTATUSCORRERRDETECTED,
- output CFGDEVSTATUSFATALERRDETECTED,
- output CFGDEVSTATUSNONFATALERRDETECTED,
- output CFGDEVSTATUSURDETECTED,
- output [31:0] CFGDO,
- output CFGERRAERHEADERLOGSETN,
- output CFGERRCPLRDYN,
- output [7:0] CFGINTERRUPTDO,
- output [2:0] CFGINTERRUPTMMENABLE,
- output CFGINTERRUPTMSIENABLE,
- output CFGINTERRUPTMSIXENABLE,
- output CFGINTERRUPTMSIXFM,
- output CFGINTERRUPTRDYN,
- output CFGLINKCONTROLRCB,
- output [1:0] CFGLINKCONTROLASPMCONTROL,
- output CFGLINKCONTROLAUTOBANDWIDTHINTEN,
- output CFGLINKCONTROLBANDWIDTHINTEN,
- output CFGLINKCONTROLCLOCKPMEN,
- output CFGLINKCONTROLCOMMONCLOCK,
- output CFGLINKCONTROLEXTENDEDSYNC,
- output CFGLINKCONTROLHWAUTOWIDTHDIS,
- output CFGLINKCONTROLLINKDISABLE,
- output CFGLINKCONTROLRETRAINLINK,
- output CFGLINKSTATUSAUTOBANDWIDTHSTATUS,
- output CFGLINKSTATUSBANDWITHSTATUS,
- output [1:0] CFGLINKSTATUSCURRENTSPEED,
- output CFGLINKSTATUSDLLACTIVE,
- output CFGLINKSTATUSLINKTRAINING,
- output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH,
- output [15:0] CFGMSGDATA,
- output CFGMSGRECEIVED,
- output CFGMSGRECEIVEDASSERTINTA,
- output CFGMSGRECEIVEDASSERTINTB,
- output CFGMSGRECEIVEDASSERTINTC,
- output CFGMSGRECEIVEDASSERTINTD,
- output CFGMSGRECEIVEDDEASSERTINTA,
- output CFGMSGRECEIVEDDEASSERTINTB,
- output CFGMSGRECEIVEDDEASSERTINTC,
- output CFGMSGRECEIVEDDEASSERTINTD,
- output CFGMSGRECEIVEDERRCOR,
- output CFGMSGRECEIVEDERRFATAL,
- output CFGMSGRECEIVEDERRNONFATAL,
- output CFGMSGRECEIVEDPMASNAK,
- output CFGMSGRECEIVEDPMETO,
- output CFGMSGRECEIVEDPMETOACK,
- output CFGMSGRECEIVEDPMPME,
- output CFGMSGRECEIVEDSETSLOTPOWERLIMIT,
- output CFGMSGRECEIVEDUNLOCK,
- output [2:0] CFGPCIELINKSTATE,
- output CFGPMCSRPMEEN,
- output CFGPMCSRPMESTATUS,
- output [1:0] CFGPMCSRPOWERSTATE,
- output CFGPMRCVASREQL1N,
- output CFGPMRCVENTERL1N,
- output CFGPMRCVENTERL23N,
- output CFGPMRCVREQACKN,
- output CFGRDWRDONEN,
- output CFGSLOTCONTROLELECTROMECHILCTLPULSE,
- output CFGTRANSACTION,
- output [6:0] CFGTRANSACTIONADDR,
- output CFGTRANSACTIONTYPE,
- output [6:0] CFGVCTCVCMAP,
- input [3:0] CFGBYTEENN,
- input [31:0] CFGDI,
- input [7:0] CFGDSBUSNUMBER,
- input [4:0] CFGDSDEVICENUMBER,
- input [2:0] CFGDSFUNCTIONNUMBER,
- input [63:0] CFGDSN,
- input [9:0] CFGDWADDR,
- input CFGERRACSN,
- input [127:0] CFGERRAERHEADERLOG,
- input CFGERRCORN,
- input CFGERRCPLABORTN,
- input CFGERRCPLTIMEOUTN,
- input CFGERRCPLUNEXPECTN,
- input CFGERRECRCN,
- input CFGERRLOCKEDN,
- input CFGERRPOSTEDN,
- input [47:0] CFGERRTLPCPLHEADER,
- input CFGERRURN,
- input CFGINTERRUPTASSERTN,
- input [7:0] CFGINTERRUPTDI,
- input CFGINTERRUPTN,
- input CFGPMDIRECTASPML1N,
- input CFGPMSENDPMACKN,
- input CFGPMSENDPMETON,
- input CFGPMSENDPMNAKN,
- input CFGPMTURNOFFOKN,
- input CFGPMWAKEN,
- input [7:0] CFGPORTNUMBER,
- input CFGRDENN,
- input CFGTRNPENDINGN,
- input CFGWRENN,
- input CFGWRREADONLYN,
- input CFGWRRW1CASRWN,
-
- output [2:0] PLINITIALLINKWIDTH,
- output [1:0] PLLANEREVERSALMODE,
- output PLLINKGEN2CAP,
- output PLLINKPARTNERGEN2SUPPORTED,
- output PLLINKUPCFGCAP,
- output [5:0] PLLTSSMSTATE,
- output PLPHYLNKUPN,
- output PLRECEIVEDHOTRST,
- output [1:0] PLRXPMSTATE,
- output PLSELLNKRATE,
- output [1:0] PLSELLNKWIDTH,
- output [2:0] PLTXPMSTATE,
- input PLDIRECTEDLINKAUTON,
- input [1:0] PLDIRECTEDLINKCHANGE,
- input PLDIRECTEDLINKSPEED,
- input [1:0] PLDIRECTEDLINKWIDTH,
- input PLDOWNSTREAMDEEMPHSOURCE,
- input PLUPSTREAMPREFERDEEMPH,
- input PLTRANSMITHOTRST,
-
- output DBGSCLRA,
- output DBGSCLRB,
- output DBGSCLRC,
- output DBGSCLRD,
- output DBGSCLRE,
- output DBGSCLRF,
- output DBGSCLRG,
- output DBGSCLRH,
- output DBGSCLRI,
- output DBGSCLRJ,
- output DBGSCLRK,
- output [63:0] DBGVECA,
- output [63:0] DBGVECB,
- output [11:0] DBGVECC,
- output [11:0] PLDBGVEC,
- input [1:0] DBGMODE,
- input DBGSUBMODE,
- input [2:0] PLDBGMODE,
- output [15:0] DRPDO,
- output DRPDRDY,
- input DRPCLK,
- input [8:0] DRPDADDR,
- input DRPDEN,
- input [15:0] DRPDI,
- input DRPDWE,
-
- output GTPLLLOCK,
- input PIPECLK,
- input USERCLK,
- input CLOCKLOCKED
-
-
- );
-
- // wire declarations
-
- wire LL2BADDLLPERRN;
- wire LL2BADTLPERRN;
- wire LL2PROTOCOLERRN;
- wire LL2REPLAYROERRN;
- wire LL2REPLAYTOERRN;
- wire LL2SUSPENDOKN;
- wire LL2TFCINIT1SEQN;
- wire LL2TFCINIT2SEQN;
- wire [12:0] MIMRXRADDR;
- wire MIMRXRCE;
- wire MIMRXREN;
- wire [12:0] MIMRXWADDR;
- wire [67:0] MIMRXWDATA;
- wire MIMRXWEN;
- wire [12:0] MIMTXRADDR;
- wire MIMTXRCE;
- wire MIMTXREN;
- wire [12:0] MIMTXWADDR;
- wire [68:0] MIMTXWDATA;
- wire MIMTXWEN;
- wire PIPERX0POLARITY;
- wire PIPERX1POLARITY;
- wire PIPERX2POLARITY;
- wire PIPERX3POLARITY;
- wire PIPERX4POLARITY;
- wire PIPERX5POLARITY;
- wire PIPERX6POLARITY;
- wire PIPERX7POLARITY;
- wire PIPETXDEEMPH;
- wire [2:0] PIPETXMARGIN;
- wire PIPETXRATE;
- wire PIPETXRCVRDET;
- wire PIPETXRESET;
- wire [1:0] PIPETX0CHARISK;
- wire PIPETX0COMPLIANCE;
- wire [15:0] PIPETX0DATA;
- wire PIPETX0ELECIDLE;
- wire [1:0] PIPETX0POWERDOWN;
- wire [1:0] PIPETX1CHARISK;
- wire PIPETX1COMPLIANCE;
- wire [15:0] PIPETX1DATA;
- wire PIPETX1ELECIDLE;
- wire [1:0] PIPETX1POWERDOWN;
- wire [1:0] PIPETX2CHARISK;
- wire PIPETX2COMPLIANCE;
- wire [15:0] PIPETX2DATA;
- wire PIPETX2ELECIDLE;
- wire [1:0] PIPETX2POWERDOWN;
- wire [1:0] PIPETX3CHARISK;
- wire PIPETX3COMPLIANCE;
- wire [15:0] PIPETX3DATA;
- wire PIPETX3ELECIDLE;
- wire [1:0] PIPETX3POWERDOWN;
- wire [1:0] PIPETX4CHARISK;
- wire PIPETX4COMPLIANCE;
- wire [15:0] PIPETX4DATA;
- wire PIPETX4ELECIDLE;
- wire [1:0] PIPETX4POWERDOWN;
- wire [1:0] PIPETX5CHARISK;
- wire PIPETX5COMPLIANCE;
- wire [15:0] PIPETX5DATA;
- wire PIPETX5ELECIDLE;
- wire [1:0] PIPETX5POWERDOWN;
- wire [1:0] PIPETX6CHARISK;
- wire PIPETX6COMPLIANCE;
- wire [15:0] PIPETX6DATA;
- wire PIPETX6ELECIDLE;
- wire [1:0] PIPETX6POWERDOWN;
- wire [1:0] PIPETX7CHARISK;
- wire PIPETX7COMPLIANCE;
- wire [15:0] PIPETX7DATA;
- wire PIPETX7ELECIDLE;
- wire [1:0] PIPETX7POWERDOWN;
- wire PL2LINKUPN;
- wire PL2RECEIVERERRN;
- wire PL2RECOVERYN;
- wire PL2RXELECIDLE;
- wire PL2SUSPENDOK;
- wire TL2ASPMSUSPENDCREDITCHECKOKN;
- wire TL2ASPMSUSPENDREQN;
- wire TL2PPMSUSPENDOKN;
- wire LL2SENDASREQL1N = 1'b1;
- wire LL2SENDENTERL1N = 1'b1;
- wire LL2SENDENTERL23N = 1'b1;
- wire LL2SUSPENDNOWN = 1'b1;
- wire LL2TLPRCVN = 1'b1;
- wire [67:0] MIMRXRDATA;
- wire [68:0] MIMTXRDATA;
- wire [4:0] PL2DIRECTEDLSTATE = 5'b0;
- wire TL2ASPMSUSPENDCREDITCHECKN;
- wire TL2PPMSUSPENDREQN;
- wire PIPERX0CHANISALIGNED;
- wire [1:0] PIPERX0CHARISK;
- wire [15:0] PIPERX0DATA;
- wire PIPERX0ELECIDLE;
- wire PIPERX0PHYSTATUS;
- wire [2:0] PIPERX0STATUS;
- wire PIPERX0VALID;
- wire PIPERX1CHANISALIGNED;
- wire [1:0] PIPERX1CHARISK;
- wire [15:0] PIPERX1DATA;
- wire PIPERX1ELECIDLE;
- wire PIPERX1PHYSTATUS;
- wire [2:0] PIPERX1STATUS;
- wire PIPERX1VALID;
- wire PIPERX2CHANISALIGNED;
- wire [1:0] PIPERX2CHARISK;
- wire [15:0] PIPERX2DATA;
- wire PIPERX2ELECIDLE;
- wire PIPERX2PHYSTATUS;
- wire [2:0] PIPERX2STATUS;
- wire PIPERX2VALID;
- wire PIPERX3CHANISALIGNED;
- wire [1:0] PIPERX3CHARISK;
- wire [15:0] PIPERX3DATA;
- wire PIPERX3ELECIDLE;
- wire PIPERX3PHYSTATUS;
- wire [2:0] PIPERX3STATUS;
- wire PIPERX3VALID;
- wire PIPERX4CHANISALIGNED;
- wire [1:0] PIPERX4CHARISK;
- wire [15:0] PIPERX4DATA;
- wire PIPERX4ELECIDLE;
- wire PIPERX4PHYSTATUS;
- wire [2:0] PIPERX4STATUS;
- wire PIPERX4VALID;
- wire PIPERX5CHANISALIGNED;
- wire [1:0] PIPERX5CHARISK;
- wire [15:0] PIPERX5DATA;
- wire PIPERX5ELECIDLE;
- wire PIPERX5PHYSTATUS;
- wire [2:0] PIPERX5STATUS;
- wire PIPERX5VALID;
- wire PIPERX6CHANISALIGNED;
- wire [1:0] PIPERX6CHARISK;
- wire [15:0] PIPERX6DATA;
- wire PIPERX6ELECIDLE;
- wire PIPERX6PHYSTATUS;
- wire [2:0] PIPERX6STATUS;
- wire PIPERX6VALID;
- wire PIPERX7CHANISALIGNED;
- wire [1:0] PIPERX7CHARISK;
- wire [15:0] PIPERX7DATA;
- wire PIPERX7ELECIDLE;
- wire PIPERX7PHYSTATUS;
- wire [2:0] PIPERX7STATUS;
- wire PIPERX7VALID;
-
- wire PIPERX0POLARITYGT;
- wire PIPERX1POLARITYGT;
- wire PIPERX2POLARITYGT;
- wire PIPERX3POLARITYGT;
- wire PIPERX4POLARITYGT;
- wire PIPERX5POLARITYGT;
- wire PIPERX6POLARITYGT;
- wire PIPERX7POLARITYGT;
- wire PIPETXDEEMPHGT;
- wire [2:0] PIPETXMARGINGT;
- wire PIPETXRATEGT;
- wire PIPETXRCVRDETGT;
- wire [1:0] PIPETX0CHARISKGT;
- wire PIPETX0COMPLIANCEGT;
- wire [15:0] PIPETX0DATAGT;
- wire PIPETX0ELECIDLEGT;
- wire [1:0] PIPETX0POWERDOWNGT;
- wire [1:0] PIPETX1CHARISKGT;
- wire PIPETX1COMPLIANCEGT;
- wire [15:0] PIPETX1DATAGT;
- wire PIPETX1ELECIDLEGT;
- wire [1:0] PIPETX1POWERDOWNGT;
- wire [1:0] PIPETX2CHARISKGT;
- wire PIPETX2COMPLIANCEGT;
- wire [15:0] PIPETX2DATAGT;
- wire PIPETX2ELECIDLEGT;
- wire [1:0] PIPETX2POWERDOWNGT;
- wire [1:0] PIPETX3CHARISKGT;
- wire PIPETX3COMPLIANCEGT;
- wire [15:0] PIPETX3DATAGT;
- wire PIPETX3ELECIDLEGT;
- wire [1:0] PIPETX3POWERDOWNGT;
- wire [1:0] PIPETX4CHARISKGT;
- wire PIPETX4COMPLIANCEGT;
- wire [15:0] PIPETX4DATAGT;
- wire PIPETX4ELECIDLEGT;
- wire [1:0] PIPETX4POWERDOWNGT;
- wire [1:0] PIPETX5CHARISKGT;
- wire PIPETX5COMPLIANCEGT;
- wire [15:0] PIPETX5DATAGT;
- wire PIPETX5ELECIDLEGT;
- wire [1:0] PIPETX5POWERDOWNGT;
- wire [1:0] PIPETX6CHARISKGT;
- wire PIPETX6COMPLIANCEGT;
- wire [15:0] PIPETX6DATAGT;
- wire PIPETX6ELECIDLEGT;
- wire [1:0] PIPETX6POWERDOWNGT;
- wire [1:0] PIPETX7CHARISKGT;
- wire PIPETX7COMPLIANCEGT;
- wire [15:0] PIPETX7DATAGT;
- wire PIPETX7ELECIDLEGT;
- wire [1:0] PIPETX7POWERDOWNGT;
-
- wire PIPERX0CHANISALIGNEDGT;
- wire [1:0] PIPERX0CHARISKGT;
- wire [15:0] PIPERX0DATAGT;
- wire PIPERX0ELECIDLEGT;
- wire PIPERX0PHYSTATUSGT;
- wire [2:0] PIPERX0STATUSGT;
- wire PIPERX0VALIDGT;
- wire PIPERX1CHANISALIGNEDGT;
- wire [1:0] PIPERX1CHARISKGT;
- wire [15:0] PIPERX1DATAGT;
- wire PIPERX1ELECIDLEGT;
- wire PIPERX1PHYSTATUSGT;
- wire [2:0] PIPERX1STATUSGT;
- wire PIPERX1VALIDGT;
- wire PIPERX2CHANISALIGNEDGT;
- wire [1:0] PIPERX2CHARISKGT;
- wire [15:0] PIPERX2DATAGT;
- wire PIPERX2ELECIDLEGT;
- wire PIPERX2PHYSTATUSGT;
- wire [2:0] PIPERX2STATUSGT;
- wire PIPERX2VALIDGT;
- wire PIPERX3CHANISALIGNEDGT;
- wire [1:0] PIPERX3CHARISKGT;
- wire [15:0] PIPERX3DATAGT;
- wire PIPERX3ELECIDLEGT;
- wire PIPERX3PHYSTATUSGT;
- wire [2:0] PIPERX3STATUSGT;
- wire PIPERX3VALIDGT;
- wire PIPERX4CHANISALIGNEDGT;
- wire [1:0] PIPERX4CHARISKGT;
- wire [15:0] PIPERX4DATAGT;
- wire PIPERX4ELECIDLEGT;
- wire PIPERX4PHYSTATUSGT;
- wire [2:0] PIPERX4STATUSGT;
- wire PIPERX4VALIDGT;
- wire PIPERX5CHANISALIGNEDGT;
- wire [1:0] PIPERX5CHARISKGT;
- wire [15:0] PIPERX5DATAGT;
- wire PIPERX5ELECIDLEGT;
- wire PIPERX5PHYSTATUSGT;
- wire [2:0] PIPERX5STATUSGT;
- wire PIPERX5VALIDGT;
- wire PIPERX6CHANISALIGNEDGT;
- wire [1:0] PIPERX6CHARISKGT;
- wire [15:0] PIPERX6DATAGT;
- wire PIPERX6ELECIDLEGT;
- wire PIPERX6PHYSTATUSGT;
- wire [2:0] PIPERX6STATUSGT;
- wire PIPERX6VALIDGT;
- wire PIPERX7CHANISALIGNEDGT;
- wire [1:0] PIPERX7CHARISKGT;
- wire [15:0] PIPERX7DATAGT;
- wire PIPERX7ELECIDLEGT;
- wire PIPERX7PHYSTATUSGT;
- wire [2:0] PIPERX7STATUSGT;
- wire PIPERX7VALIDGT;
-
- wire filter_pipe_upconfig_fix_3451;
-
-
-// Assignments to outputs
-
- assign TRNCLK = USERCLK;
-
-
-
-
-//-------------------------------------------------------
-// Virtex6 PCI Express Block Module
-//-------------------------------------------------------
-PCIE_2_0 #(
-
- .AER_BASE_PTR ( AER_BASE_PTR ),
- .AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
- .AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
- .AER_CAP_ID ( AER_CAP_ID ),
- .AER_CAP_INT_MSG_NUM_MSI ( AER_CAP_INT_MSG_NUM_MSI ),
- .AER_CAP_INT_MSG_NUM_MSIX ( AER_CAP_INT_MSG_NUM_MSIX ),
- .AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
- .AER_CAP_ON ( AER_CAP_ON ),
- .AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
- .AER_CAP_VERSION ( AER_CAP_VERSION ),
- .ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
- .BAR0 ( BAR0 ),
- .BAR1 ( BAR1 ),
- .BAR2 ( BAR2 ),
- .BAR3 ( BAR3 ),
- .BAR4 ( BAR4 ),
- .BAR5 ( BAR5 ),
- .CAPABILITIES_PTR ( CAPABILITIES_PTR ),
- .CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
- .CLASS_CODE ( CLASS_CODE ),
- .CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
- .CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
- .CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
- .CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
- .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
- .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
- .DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
- .DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
- .DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
- .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
- .DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
- .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
- .DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
- .DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
- .DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
- .DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
- .DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
- .DEVICE_ID ( DEVICE_ID ),
- .DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
- .DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
- .DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
- .DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
- .DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
- .DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
- .DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
- .DSN_BASE_PTR ( DSN_BASE_PTR ),
- .DSN_CAP_ID ( DSN_CAP_ID ),
- .DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
- .DSN_CAP_ON ( DSN_CAP_ON ),
- .DSN_CAP_VERSION ( DSN_CAP_VERSION ),
- .ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
- .ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
- .ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
- .EXPANSION_ROM ( EXPANSION_ROM ),
- .EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
- .EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
- .HEADER_TYPE ( HEADER_TYPE ),
- .INFER_EI ( INFER_EI ),
- .INTERRUPT_PIN ( INTERRUPT_PIN ),
- .IS_SWITCH ( IS_SWITCH ),
- .LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
- .LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
- .LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
- .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
- .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
- .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
- .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
- .LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
- .LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
- .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
- .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
- .LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
- .LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
- .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
- .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
- .LINK_CAP_RSVD_23_22 ( LINK_CAP_RSVD_23_22 ),
- .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
- .LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
- .LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
- .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
- .LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
- .LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
- .LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
- .LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
- .LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
- .LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
- .LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
- .LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
- .LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
- .MSI_BASE_PTR ( MSI_BASE_PTR ),
- .MSI_CAP_ID ( MSI_CAP_ID ),
- .MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
- .MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
- .MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
- .MSI_CAP_ON ( MSI_CAP_ON ),
- .MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
- .MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
- .MSIX_BASE_PTR ( MSIX_BASE_PTR ),
- .MSIX_CAP_ID ( MSIX_CAP_ID ),
- .MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
- .MSIX_CAP_ON ( MSIX_CAP_ON ),
- .MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
- .MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
- .MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
- .MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
- .MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
- .N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
- .N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
- .N_FTS_GEN1 ( N_FTS_GEN1 ),
- .N_FTS_GEN2 ( N_FTS_GEN2 ),
- .PCIE_BASE_PTR ( PCIE_BASE_PTR ),
- .PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
- .PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
- .PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
- .PCIE_CAP_INT_MSG_NUM ( PCIE_CAP_INT_MSG_NUM ),
- .PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
- .PCIE_CAP_ON ( PCIE_CAP_ON ),
- .PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
- .PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
- .PCIE_REVISION ( PCIE_REVISION ),
- .PGL0_LANE ( PGL0_LANE ),
- .PGL1_LANE ( PGL1_LANE ),
- .PGL2_LANE ( PGL2_LANE ),
- .PGL3_LANE ( PGL3_LANE ),
- .PGL4_LANE ( PGL4_LANE ),
- .PGL5_LANE ( PGL5_LANE ),
- .PGL6_LANE ( PGL6_LANE ),
- .PGL7_LANE ( PGL7_LANE ),
- .PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
- .PL_FAST_TRAIN ( PL_FAST_TRAIN ),
- .PM_BASE_PTR ( PM_BASE_PTR ),
- .PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
- .PM_CAP_DSI ( PM_CAP_DSI ),
- .PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
- .PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
- .PM_CAP_ID ( PM_CAP_ID ),
- .PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
- .PM_CAP_ON ( PM_CAP_ON ),
- .PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
- .PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
- .PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
- .PM_CAP_VERSION ( PM_CAP_VERSION ),
- .PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
- .PM_CSR_B2B3 ( PM_CSR_B2B3 ),
- .PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
- .PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
- .PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
- .PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
- .PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
- .PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
- .PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
- .PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
- .PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
- .PM_DATA0 ( PM_DATA0 ),
- .PM_DATA1 ( PM_DATA1 ),
- .PM_DATA2 ( PM_DATA2 ),
- .PM_DATA3 ( PM_DATA3 ),
- .PM_DATA4 ( PM_DATA4 ),
- .PM_DATA5 ( PM_DATA5 ),
- .PM_DATA6 ( PM_DATA6 ),
- .PM_DATA7 ( PM_DATA7 ),
- .RECRC_CHK ( RECRC_CHK ),
- .RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
- .REVISION_ID ( REVISION_ID ),
- .ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
- .SELECT_DLL_IF ( SELECT_DLL_IF ),
- .SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
- .SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
- .SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
- .SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
- .SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
- .SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
- .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
- .SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
- .SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
- .SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
- .SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
- .SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
- .SPARE_BIT0 ( SPARE_BIT0 ),
- .SPARE_BIT1 ( SPARE_BIT1 ),
- .SPARE_BIT2 ( SPARE_BIT2 ),
- .SPARE_BIT3 ( SPARE_BIT3 ),
- .SPARE_BIT4 ( SPARE_BIT4 ),
- .SPARE_BIT5 ( SPARE_BIT5 ),
- .SPARE_BIT6 ( SPARE_BIT6 ),
- .SPARE_BIT7 ( SPARE_BIT7 ),
- .SPARE_BIT8 ( SPARE_BIT8 ),
- .SPARE_BYTE0 ( SPARE_BYTE0 ),
- .SPARE_BYTE1 ( SPARE_BYTE1 ),
- .SPARE_BYTE2 ( SPARE_BYTE2 ),
- .SPARE_BYTE3 ( SPARE_BYTE3 ),
- .SPARE_WORD0 ( SPARE_WORD0 ),
- .SPARE_WORD1 ( SPARE_WORD1 ),
- .SPARE_WORD2 ( SPARE_WORD2 ),
- .SPARE_WORD3 ( SPARE_WORD3 ),
- .SUBSYSTEM_ID ( SUBSYSTEM_ID ),
- .SUBSYSTEM_VENDOR_ID ( SUBSYSTEM_VENDOR_ID ),
- .TL_RBYPASS ( TL_RBYPASS ),
- .TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
- .TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
- .TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
- .TL_TFC_DISABLE ( TL_TFC_DISABLE ),
- .TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
- .TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
- .TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
- .TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
- .UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
- .UPSTREAM_FACING ( UPSTREAM_FACING ),
- .EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
- .UR_INV_REQ ( UR_INV_REQ ),
- .USER_CLK_FREQ ( USER_CLK_FREQ ),
- .VC_BASE_PTR ( VC_BASE_PTR ),
- .VC_CAP_ID ( VC_CAP_ID ),
- .VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
- .VC_CAP_ON ( VC_CAP_ON ),
- .VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
- .VC_CAP_VERSION ( VC_CAP_VERSION ),
- .VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
- .VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
- .VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
- .VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
- .VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
- .VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
- .VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
- .VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
- .VENDOR_ID ( VENDOR_ID ),
- .VSEC_BASE_PTR ( VSEC_BASE_PTR ),
- .VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
- .VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
- .VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
- .VSEC_CAP_ID ( VSEC_CAP_ID ),
- .VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
- .VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
- .VSEC_CAP_ON ( VSEC_CAP_ON ),
- .VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
-
-)
-pcie_block_i (
-
- .CFGAERECRCCHECKEN ( CFGAERECRCCHECKEN ),
- .CFGAERECRCGENEN ( CFGAERECRCGENEN ),
- .CFGCOMMANDBUSMASTERENABLE ( CFGCOMMANDBUSMASTERENABLE ),
- .CFGCOMMANDINTERRUPTDISABLE ( CFGCOMMANDINTERRUPTDISABLE ),
- .CFGCOMMANDIOENABLE ( CFGCOMMANDIOENABLE ),
- .CFGCOMMANDMEMENABLE ( CFGCOMMANDMEMENABLE ),
- .CFGCOMMANDSERREN ( CFGCOMMANDSERREN ),
- .CFGDEVCONTROLAUXPOWEREN ( CFGDEVCONTROLAUXPOWEREN ),
- .CFGDEVCONTROLCORRERRREPORTINGEN ( CFGDEVCONTROLCORRERRREPORTINGEN ),
- .CFGDEVCONTROLENABLERO ( CFGDEVCONTROLENABLERO ),
- .CFGDEVCONTROLEXTTAGEN ( CFGDEVCONTROLEXTTAGEN ),
- .CFGDEVCONTROLFATALERRREPORTINGEN ( CFGDEVCONTROLFATALERRREPORTINGEN ),
- .CFGDEVCONTROLMAXPAYLOAD ( CFGDEVCONTROLMAXPAYLOAD ),
- .CFGDEVCONTROLMAXREADREQ ( CFGDEVCONTROLMAXREADREQ ),
- .CFGDEVCONTROLNONFATALREPORTINGEN ( CFGDEVCONTROLNONFATALREPORTINGEN ),
- .CFGDEVCONTROLNOSNOOPEN ( CFGDEVCONTROLNOSNOOPEN ),
- .CFGDEVCONTROLPHANTOMEN ( CFGDEVCONTROLPHANTOMEN ),
- .CFGDEVCONTROLURERRREPORTINGEN ( CFGDEVCONTROLURERRREPORTINGEN ),
- .CFGDEVCONTROL2CPLTIMEOUTDIS ( CFGDEVCONTROL2CPLTIMEOUTDIS ),
- .CFGDEVCONTROL2CPLTIMEOUTVAL ( CFGDEVCONTROL2CPLTIMEOUTVAL ),
- .CFGDEVSTATUSCORRERRDETECTED ( CFGDEVSTATUSCORRERRDETECTED ),
- .CFGDEVSTATUSFATALERRDETECTED ( CFGDEVSTATUSFATALERRDETECTED ),
- .CFGDEVSTATUSNONFATALERRDETECTED ( CFGDEVSTATUSNONFATALERRDETECTED ),
- .CFGDEVSTATUSURDETECTED ( CFGDEVSTATUSURDETECTED ),
- .CFGDO ( CFGDO ),
- .CFGERRAERHEADERLOGSETN ( CFGERRAERHEADERLOGSETN ),
-
- .CFGERRCPLRDYN ( CFGERRCPLRDYN ),
- .CFGINTERRUPTDO ( CFGINTERRUPTDO ),
- .CFGINTERRUPTMMENABLE ( CFGINTERRUPTMMENABLE ),
- .CFGINTERRUPTMSIENABLE ( CFGINTERRUPTMSIENABLE ),
- .CFGINTERRUPTMSIXENABLE ( CFGINTERRUPTMSIXENABLE ),
- .CFGINTERRUPTMSIXFM ( CFGINTERRUPTMSIXFM ),
- .CFGINTERRUPTRDYN ( CFGINTERRUPTRDYN ),
- .CFGLINKCONTROLRCB ( CFGLINKCONTROLRCB ),
- .CFGLINKCONTROLASPMCONTROL ( CFGLINKCONTROLASPMCONTROL ),
- .CFGLINKCONTROLAUTOBANDWIDTHINTEN ( CFGLINKCONTROLAUTOBANDWIDTHINTEN ),
- .CFGLINKCONTROLBANDWIDTHINTEN ( CFGLINKCONTROLBANDWIDTHINTEN ),
- .CFGLINKCONTROLCLOCKPMEN ( CFGLINKCONTROLCLOCKPMEN ),
- .CFGLINKCONTROLCOMMONCLOCK ( CFGLINKCONTROLCOMMONCLOCK ),
- .CFGLINKCONTROLEXTENDEDSYNC ( CFGLINKCONTROLEXTENDEDSYNC ),
- .CFGLINKCONTROLHWAUTOWIDTHDIS ( CFGLINKCONTROLHWAUTOWIDTHDIS ),
- .CFGLINKCONTROLLINKDISABLE ( CFGLINKCONTROLLINKDISABLE ),
- .CFGLINKCONTROLRETRAINLINK ( CFGLINKCONTROLRETRAINLINK ),
- .CFGLINKSTATUSAUTOBANDWIDTHSTATUS ( CFGLINKSTATUSAUTOBANDWIDTHSTATUS ),
- .CFGLINKSTATUSBANDWITHSTATUS ( CFGLINKSTATUSBANDWITHSTATUS ),
- .CFGLINKSTATUSCURRENTSPEED ( CFGLINKSTATUSCURRENTSPEED ),
- .CFGLINKSTATUSDLLACTIVE ( CFGLINKSTATUSDLLACTIVE ),
- .CFGLINKSTATUSLINKTRAINING ( CFGLINKSTATUSLINKTRAINING ),
- .CFGLINKSTATUSNEGOTIATEDWIDTH ( CFGLINKSTATUSNEGOTIATEDWIDTH ),
- .CFGMSGDATA ( CFGMSGDATA ),
- .CFGMSGRECEIVED ( CFGMSGRECEIVED ),
-
- .CFGMSGRECEIVEDASSERTINTA ( CFGMSGRECEIVEDASSERTINTA ),
- .CFGMSGRECEIVEDASSERTINTB ( CFGMSGRECEIVEDASSERTINTB ),
- .CFGMSGRECEIVEDASSERTINTC ( CFGMSGRECEIVEDASSERTINTC ),
- .CFGMSGRECEIVEDASSERTINTD ( CFGMSGRECEIVEDASSERTINTD ),
- .CFGMSGRECEIVEDDEASSERTINTA ( CFGMSGRECEIVEDDEASSERTINTA ),
- .CFGMSGRECEIVEDDEASSERTINTB ( CFGMSGRECEIVEDDEASSERTINTB ),
- .CFGMSGRECEIVEDDEASSERTINTC ( CFGMSGRECEIVEDDEASSERTINTC ),
- .CFGMSGRECEIVEDDEASSERTINTD ( CFGMSGRECEIVEDDEASSERTINTD ),
- .CFGMSGRECEIVEDERRCOR ( CFGMSGRECEIVEDERRCOR ),
- .CFGMSGRECEIVEDERRFATAL ( CFGMSGRECEIVEDERRFATAL ),
- .CFGMSGRECEIVEDERRNONFATAL ( CFGMSGRECEIVEDERRNONFATAL ),
-
- .CFGMSGRECEIVEDPMASNAK ( CFGMSGRECEIVEDPMASNAK ),
- .CFGMSGRECEIVEDPMETO ( CFGMSGRECEIVEDPMETO ),
-
-
- .CFGMSGRECEIVEDPMETOACK ( CFGMSGRECEIVEDPMETOACK ),
- .CFGMSGRECEIVEDPMPME ( CFGMSGRECEIVEDPMPME ),
-
-
- .CFGMSGRECEIVEDSETSLOTPOWERLIMIT ( CFGMSGRECEIVEDSETSLOTPOWERLIMIT ),
- .CFGMSGRECEIVEDUNLOCK ( CFGMSGRECEIVEDUNLOCK ),
- .CFGPCIELINKSTATE ( CFGPCIELINKSTATE ),
-
-
- .CFGPMRCVASREQL1N ( CFGPMRCVASREQL1N ),
- .CFGPMRCVENTERL1N ( CFGPMRCVENTERL1N ),
- .CFGPMRCVENTERL23N ( CFGPMRCVENTERL23N ),
-
- .CFGPMRCVREQACKN ( CFGPMRCVREQACKN ),
- .CFGPMCSRPMEEN( CFGPMCSRPMEEN ),
- .CFGPMCSRPMESTATUS( CFGPMCSRPMESTATUS ),
- .CFGPMCSRPOWERSTATE( CFGPMCSRPOWERSTATE ),
- .CFGRDWRDONEN ( CFGRDWRDONEN ),
-
- .CFGSLOTCONTROLELECTROMECHILCTLPULSE ( CFGSLOTCONTROLELECTROMECHILCTLPULSE ),
-
- .CFGTRANSACTION ( CFGTRANSACTION ),
- .CFGTRANSACTIONADDR ( CFGTRANSACTIONADDR ),
- .CFGTRANSACTIONTYPE ( CFGTRANSACTIONTYPE ),
-
- .CFGVCTCVCMAP ( CFGVCTCVCMAP ),
- .DBGSCLRA ( DBGSCLRA ),
- .DBGSCLRB ( DBGSCLRB ),
- .DBGSCLRC ( DBGSCLRC ),
- .DBGSCLRD ( DBGSCLRD ),
- .DBGSCLRE ( DBGSCLRE ),
- .DBGSCLRF ( DBGSCLRF ),
- .DBGSCLRG ( DBGSCLRG ),
- .DBGSCLRH ( DBGSCLRH ),
- .DBGSCLRI ( DBGSCLRI ),
- .DBGSCLRJ ( DBGSCLRJ ),
- .DBGSCLRK ( DBGSCLRK ),
- .DBGVECA ( DBGVECA ),
- .DBGVECB ( DBGVECB ),
- .DBGVECC ( DBGVECC ),
- .DRPDO ( DRPDO ),
- .DRPDRDY ( DRPDRDY ),
- .LL2BADDLLPERRN ( LL2BADDLLPERRN ),
- .LL2BADTLPERRN ( LL2BADTLPERRN ),
- .LL2PROTOCOLERRN ( LL2PROTOCOLERRN ),
- .LL2REPLAYROERRN ( LL2REPLAYROERRN ),
- .LL2REPLAYTOERRN ( LL2REPLAYTOERRN ),
- .LL2SUSPENDOKN ( LL2SUSPENDOKN ),
- .LL2TFCINIT1SEQN ( LL2TFCINIT1SEQN ),
- .LL2TFCINIT2SEQN ( LL2TFCINIT2SEQN ),
- .MIMRXRADDR ( MIMRXRADDR ),
- .MIMRXRCE ( MIMRXRCE ),
- .MIMRXREN ( MIMRXREN ),
- .MIMRXWADDR ( MIMRXWADDR ),
- .MIMRXWDATA ( MIMRXWDATA ),
- .MIMRXWEN ( MIMRXWEN ),
- .MIMTXRADDR ( MIMTXRADDR ),
- .MIMTXRCE ( MIMTXRCE ),
- .MIMTXREN ( MIMTXREN ),
- .MIMTXWADDR ( MIMTXWADDR ),
- .MIMTXWDATA ( MIMTXWDATA ),
- .MIMTXWEN ( MIMTXWEN ),
- .PIPERX0POLARITY ( PIPERX0POLARITY ),
- .PIPERX1POLARITY ( PIPERX1POLARITY ),
- .PIPERX2POLARITY ( PIPERX2POLARITY ),
- .PIPERX3POLARITY ( PIPERX3POLARITY ),
- .PIPERX4POLARITY ( PIPERX4POLARITY ),
- .PIPERX5POLARITY ( PIPERX5POLARITY ),
- .PIPERX6POLARITY ( PIPERX6POLARITY ),
- .PIPERX7POLARITY ( PIPERX7POLARITY ),
- .PIPETXDEEMPH ( PIPETXDEEMPH ),
- .PIPETXMARGIN ( PIPETXMARGIN ),
- .PIPETXRATE ( PIPETXRATE ),
- .PIPETXRCVRDET ( PIPETXRCVRDET ),
- .PIPETXRESET ( PIPETXRESET ),
- .PIPETX0CHARISK ( PIPETX0CHARISK ),
- .PIPETX0COMPLIANCE ( PIPETX0COMPLIANCE ),
- .PIPETX0DATA ( PIPETX0DATA ),
- .PIPETX0ELECIDLE ( PIPETX0ELECIDLE ),
- .PIPETX0POWERDOWN ( PIPETX0POWERDOWN ),
- .PIPETX1CHARISK ( PIPETX1CHARISK ),
- .PIPETX1COMPLIANCE ( PIPETX1COMPLIANCE ),
- .PIPETX1DATA ( PIPETX1DATA ),
- .PIPETX1ELECIDLE ( PIPETX1ELECIDLE ),
- .PIPETX1POWERDOWN ( PIPETX1POWERDOWN ),
- .PIPETX2CHARISK ( PIPETX2CHARISK ),
- .PIPETX2COMPLIANCE ( PIPETX2COMPLIANCE ),
- .PIPETX2DATA ( PIPETX2DATA ),
- .PIPETX2ELECIDLE ( PIPETX2ELECIDLE ),
- .PIPETX2POWERDOWN ( PIPETX2POWERDOWN ),
- .PIPETX3CHARISK ( PIPETX3CHARISK ),
- .PIPETX3COMPLIANCE ( PIPETX3COMPLIANCE ),
- .PIPETX3DATA ( PIPETX3DATA ),
- .PIPETX3ELECIDLE ( PIPETX3ELECIDLE ),
- .PIPETX3POWERDOWN ( PIPETX3POWERDOWN ),
- .PIPETX4CHARISK ( PIPETX4CHARISK ),
- .PIPETX4COMPLIANCE ( PIPETX4COMPLIANCE ),
- .PIPETX4DATA ( PIPETX4DATA ),
- .PIPETX4ELECIDLE ( PIPETX4ELECIDLE ),
- .PIPETX4POWERDOWN ( PIPETX4POWERDOWN ),
- .PIPETX5CHARISK ( PIPETX5CHARISK ),
- .PIPETX5COMPLIANCE ( PIPETX5COMPLIANCE ),
- .PIPETX5DATA ( PIPETX5DATA ),
- .PIPETX5ELECIDLE ( PIPETX5ELECIDLE ),
- .PIPETX5POWERDOWN ( PIPETX5POWERDOWN ),
- .PIPETX6CHARISK ( PIPETX6CHARISK ),
- .PIPETX6COMPLIANCE ( PIPETX6COMPLIANCE ),
- .PIPETX6DATA ( PIPETX6DATA ),
- .PIPETX6ELECIDLE ( PIPETX6ELECIDLE ),
- .PIPETX6POWERDOWN ( PIPETX6POWERDOWN ),
- .PIPETX7CHARISK ( PIPETX7CHARISK ),
- .PIPETX7COMPLIANCE ( PIPETX7COMPLIANCE ),
- .PIPETX7DATA ( PIPETX7DATA ),
- .PIPETX7ELECIDLE ( PIPETX7ELECIDLE ),
- .PIPETX7POWERDOWN ( PIPETX7POWERDOWN ),
- .PLDBGVEC ( PLDBGVEC ),
- .PLINITIALLINKWIDTH ( PLINITIALLINKWIDTH ),
- .PLLANEREVERSALMODE ( PLLANEREVERSALMODE ),
- .PLLINKGEN2CAP ( PLLINKGEN2CAP ),
- .PLLINKPARTNERGEN2SUPPORTED ( PLLINKPARTNERGEN2SUPPORTED ),
- .PLLINKUPCFGCAP ( PLLINKUPCFGCAP ),
- .PLLTSSMSTATE ( PLLTSSMSTATE ),
- .PLPHYLNKUPN ( PLPHYLNKUPN ),
- .PLRECEIVEDHOTRST ( PLRECEIVEDHOTRST ),
- .PLRXPMSTATE ( PLRXPMSTATE ),
- .PLSELLNKRATE ( PLSELLNKRATE ),
- .PLSELLNKWIDTH ( PLSELLNKWIDTH ),
- .PLTXPMSTATE ( PLTXPMSTATE ),
- .PL2LINKUPN ( PL2LINKUPN ),
- .PL2RECEIVERERRN ( PL2RECEIVERERRN ),
- .PL2RECOVERYN ( PL2RECOVERYN ),
- .PL2RXELECIDLE ( PL2RXELECIDLE ),
- .PL2SUSPENDOK ( PL2SUSPENDOK ),
- .RECEIVEDFUNCLVLRSTN ( RECEIVEDFUNCLVLRSTN ),
- .LNKCLKEN ( LNKCLKEN ),
- .TL2ASPMSUSPENDCREDITCHECKOKN ( TL2ASPMSUSPENDCREDITCHECKOKN ),
- .TL2ASPMSUSPENDREQN ( TL2ASPMSUSPENDREQN ),
- .TL2PPMSUSPENDOKN ( TL2PPMSUSPENDOKN ),
- .TRNFCCPLD ( TRNFCCPLD ),
- .TRNFCCPLH ( TRNFCCPLH ),
- .TRNFCNPD ( TRNFCNPD ),
- .TRNFCNPH ( TRNFCNPH ),
- .TRNFCPD ( TRNFCPD ),
- .TRNFCPH ( TRNFCPH ),
- .TRNLNKUPN ( TRNLNKUPN ),
- .TRNRBARHITN ( TRNRBARHITN ),
- .TRNRD ( TRNRD ),
-
- .TRNRDLLPDATA ( ),
- .TRNRDLLPSRCRDYN ( TRNRDLLPSRCRDYN ),
- .TRNRECRCERRN ( TRNRECRCERRN ),
- .TRNREOFN ( TRNREOFN ),
- .TRNRERRFWDN ( TRNRERRFWDN ),
- .TRNRREMN ( TRNRREMN ),
- .TRNRSOFN ( TRNRSOFN ),
- .TRNRSRCDSCN ( TRNRSRCDSCN ),
- .TRNRSRCRDYN ( TRNRSRCRDYN ),
- .TRNTBUFAV ( TRNTBUFAV ),
- .TRNTCFGREQN ( TRNTCFGREQN ),
- .TRNTDLLPDSTRDYN ( TRNTDLLPDSTRDYN ),
- .TRNTDSTRDYN ( TRNTDSTRDYN ),
- .TRNTERRDROPN ( TRNTERRDROPN ),
- .USERRSTN ( USERRSTN ),
- .CFGBYTEENN ( CFGBYTEENN ),
- .CFGDI ( CFGDI ),
- .CFGDSBUSNUMBER ( CFGDSBUSNUMBER ),
- .CFGDSDEVICENUMBER ( CFGDSDEVICENUMBER ),
- .CFGDSFUNCTIONNUMBER ( CFGDSFUNCTIONNUMBER ),
- .CFGDSN ( CFGDSN ),
- .CFGDWADDR ( CFGDWADDR ),
- .CFGERRACSN ( CFGERRACSN ),
- .CFGERRAERHEADERLOG ( CFGERRAERHEADERLOG ),
- .CFGERRCORN ( CFGERRCORN ),
- .CFGERRCPLABORTN ( CFGERRCPLABORTN ),
- .CFGERRCPLTIMEOUTN ( CFGERRCPLTIMEOUTN ),
- .CFGERRCPLUNEXPECTN ( CFGERRCPLUNEXPECTN ),
- .CFGERRECRCN ( CFGERRECRCN ),
- .CFGERRLOCKEDN ( CFGERRLOCKEDN ),
- .CFGERRPOSTEDN ( CFGERRPOSTEDN ),
- .CFGERRTLPCPLHEADER ( CFGERRTLPCPLHEADER ),
- .CFGERRURN ( CFGERRURN ),
- .CFGINTERRUPTASSERTN ( CFGINTERRUPTASSERTN ),
- .CFGINTERRUPTDI ( CFGINTERRUPTDI ),
- .CFGINTERRUPTN ( CFGINTERRUPTN ),
- .CFGPMDIRECTASPML1N ( CFGPMDIRECTASPML1N ),
- .CFGPMSENDPMACKN ( CFGPMSENDPMACKN ),
- .CFGPMSENDPMETON ( CFGPMSENDPMETON ),
- .CFGPMSENDPMNAKN ( CFGPMSENDPMNAKN ),
- .CFGPMTURNOFFOKN ( CFGPMTURNOFFOKN ),
- .CFGPMWAKEN ( CFGPMWAKEN ),
- .CFGPORTNUMBER ( CFGPORTNUMBER ),
- .CFGRDENN ( CFGRDENN ),
- .CFGTRNPENDINGN ( CFGTRNPENDINGN ),
- .CFGWRENN ( CFGWRENN ),
- .CFGWRREADONLYN ( CFGWRREADONLYN ),
- .CFGWRRW1CASRWN ( CFGWRRW1CASRWN ),
- .CMRSTN ( CMRSTN ),
- .CMSTICKYRSTN ( CMSTICKYRSTN ),
- .DBGMODE ( DBGMODE ),
- .DBGSUBMODE ( DBGSUBMODE ),
- .DLRSTN ( DLRSTN ),
- .DRPCLK ( DRPCLK ),
- .DRPDADDR ( DRPDADDR ),
- .DRPDEN ( DRPDEN ),
- .DRPDI ( DRPDI ),
- .DRPDWE ( DRPDWE ),
- .FUNCLVLRSTN ( FUNCLVLRSTN ),
- .LL2SENDASREQL1N ( LL2SENDASREQL1N ),
- .LL2SENDENTERL1N ( LL2SENDENTERL1N ),
- .LL2SENDENTERL23N ( LL2SENDENTERL23N ),
- .LL2SUSPENDNOWN ( LL2SUSPENDNOWN ),
- .LL2TLPRCVN ( LL2TLPRCVN ),
- .MIMRXRDATA ( MIMRXRDATA ),
- .MIMTXRDATA ( MIMTXRDATA ),
- .PIPECLK ( PIPECLK ),
- .PIPERX0CHANISALIGNED ( PIPERX0CHANISALIGNED ),
- .PIPERX0CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX0CHARISK ),
- .PIPERX0DATA ( PIPERX0DATA ),
- .PIPERX0ELECIDLE ( PIPERX0ELECIDLE ),
- .PIPERX0PHYSTATUS ( PIPERX0PHYSTATUS ),
- .PIPERX0STATUS ( PIPERX0STATUS ),
- .PIPERX0VALID ( PIPERX0VALID ),
- .PIPERX1CHANISALIGNED ( PIPERX1CHANISALIGNED ),
- .PIPERX1CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX1CHARISK ),
- .PIPERX1DATA ( PIPERX1DATA ),
- .PIPERX1ELECIDLE ( PIPERX1ELECIDLE ),
- .PIPERX1PHYSTATUS ( PIPERX1PHYSTATUS ),
- .PIPERX1STATUS ( PIPERX1STATUS ),
- .PIPERX1VALID ( PIPERX1VALID ),
- .PIPERX2CHANISALIGNED ( PIPERX2CHANISALIGNED ),
- .PIPERX2CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX2CHARISK ),
- .PIPERX2DATA ( PIPERX2DATA ),
- .PIPERX2ELECIDLE ( PIPERX2ELECIDLE ),
- .PIPERX2PHYSTATUS ( PIPERX2PHYSTATUS ),
- .PIPERX2STATUS ( PIPERX2STATUS ),
- .PIPERX2VALID ( PIPERX2VALID ),
- .PIPERX3CHANISALIGNED ( PIPERX3CHANISALIGNED ),
- .PIPERX3CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX3CHARISK ),
- .PIPERX3DATA ( PIPERX3DATA ),
- .PIPERX3ELECIDLE ( PIPERX3ELECIDLE ),
- .PIPERX3PHYSTATUS ( PIPERX3PHYSTATUS ),
- .PIPERX3STATUS ( PIPERX3STATUS ),
- .PIPERX3VALID ( PIPERX3VALID ),
- .PIPERX4CHANISALIGNED ( PIPERX4CHANISALIGNED ),
- .PIPERX4CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX4CHARISK ),
- .PIPERX4DATA ( PIPERX4DATA ),
- .PIPERX4ELECIDLE ( PIPERX4ELECIDLE ),
- .PIPERX4PHYSTATUS ( PIPERX4PHYSTATUS ),
- .PIPERX4STATUS ( PIPERX4STATUS ),
- .PIPERX4VALID ( PIPERX4VALID ),
- .PIPERX5CHANISALIGNED ( PIPERX5CHANISALIGNED ),
- .PIPERX5CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX5CHARISK ),
- .PIPERX5DATA ( PIPERX5DATA ),
- .PIPERX5ELECIDLE ( PIPERX5ELECIDLE ),
- .PIPERX5PHYSTATUS ( PIPERX5PHYSTATUS ),
- .PIPERX5STATUS ( PIPERX5STATUS ),
- .PIPERX5VALID ( PIPERX5VALID ),
- .PIPERX6CHANISALIGNED ( PIPERX6CHANISALIGNED ),
- .PIPERX6CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX6CHARISK ),
- .PIPERX6DATA ( PIPERX6DATA ),
- .PIPERX6ELECIDLE ( PIPERX6ELECIDLE ),
- .PIPERX6PHYSTATUS ( PIPERX6PHYSTATUS ),
- .PIPERX6STATUS ( PIPERX6STATUS ),
- .PIPERX6VALID ( PIPERX6VALID ),
- .PIPERX7CHANISALIGNED ( PIPERX7CHANISALIGNED ),
- .PIPERX7CHARISK ( filter_pipe_upconfig_fix_3451 ? 2'b11 : PIPERX7CHARISK ),
- .PIPERX7DATA ( PIPERX7DATA ),
- .PIPERX7ELECIDLE ( PIPERX7ELECIDLE ),
- .PIPERX7PHYSTATUS ( PIPERX7PHYSTATUS ),
- .PIPERX7STATUS ( PIPERX7STATUS ),
- .PIPERX7VALID ( PIPERX7VALID ),
- .PLDBGMODE ( PLDBGMODE ),
- .PLDIRECTEDLINKAUTON ( PLDIRECTEDLINKAUTON ),
- .PLDIRECTEDLINKCHANGE ( PLDIRECTEDLINKCHANGE ),
- .PLDIRECTEDLINKSPEED ( PLDIRECTEDLINKSPEED ),
- .PLDIRECTEDLINKWIDTH ( PLDIRECTEDLINKWIDTH ),
- .PLDOWNSTREAMDEEMPHSOURCE ( PLDOWNSTREAMDEEMPHSOURCE ),
- .PLRSTN ( PLRSTN ),
- .PLTRANSMITHOTRST ( PLTRANSMITHOTRST ),
- .PLUPSTREAMPREFERDEEMPH ( PLUPSTREAMPREFERDEEMPH ),
- .PL2DIRECTEDLSTATE ( PL2DIRECTEDLSTATE ),
- .SYSRSTN ( SYSRSTN ),
- .TLRSTN ( TLRSTN ),
- .TL2ASPMSUSPENDCREDITCHECKN ( 1'b1),
- .TL2PPMSUSPENDREQN ( 1'b1 ),
- .TRNFCSEL ( TRNFCSEL ),
- .TRNRDSTRDYN ( TRNRDSTRDYN ),
- .TRNRNPOKN ( TRNRNPOKN ),
- .TRNTCFGGNTN ( TRNTCFGGNTN ),
- .TRNTD ( TRNTD ),
- .TRNTDLLPDATA ( TRNTDLLPDATA ),
- .TRNTDLLPSRCRDYN ( TRNTDLLPSRCRDYN ),
- .TRNTECRCGENN ( TRNTECRCGENN ),
- .TRNTEOFN ( TRNTEOFN ),
- .TRNTERRFWDN ( TRNTERRFWDN ),
- .TRNTREMN ( TRNTREMN ),
- .TRNTSOFN ( TRNTSOFN ),
- .TRNTSRCDSCN ( TRNTSRCDSCN ),
- .TRNTSRCRDYN ( TRNTSRCRDYN ),
- .TRNTSTRN ( TRNTSTRN ),
- .USERCLK ( USERCLK )
-
-);
-
-//-------------------------------------------------------
-// Virtex6 PIPE Module
-//-------------------------------------------------------
-
-pcie_pipe_v6 # (
-
- .NO_OF_LANES(LINK_CAP_MAX_LINK_WIDTH),
- .LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
- .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
-
-)
-pcie_pipe_i (
-
- // Pipe Per-Link Signals
- .pipe_tx_rcvr_det_i (PIPETXRCVRDET),
- .pipe_tx_reset_i (PIPETXRESET),
- .pipe_tx_rate_i (PIPETXRATE),
- .pipe_tx_deemph_i (PIPETXDEEMPH),
- .pipe_tx_margin_i (PIPETXMARGIN),
- .pipe_tx_swing_i (1'b0),
-
- .pipe_tx_rcvr_det_o (PIPETXRCVRDETGT),
- .pipe_tx_reset_o ( ),
- .pipe_tx_rate_o (PIPETXRATEGT),
- .pipe_tx_deemph_o (PIPETXDEEMPHGT),
- .pipe_tx_margin_o (PIPETXMARGINGT),
- .pipe_tx_swing_o ( ),
-
- // Pipe Per-Lane Signals - Lane 0
- .pipe_rx0_char_is_k_o (PIPERX0CHARISK ),
- .pipe_rx0_data_o (PIPERX0DATA ),
- .pipe_rx0_valid_o (PIPERX0VALID ),
- .pipe_rx0_chanisaligned_o (PIPERX0CHANISALIGNED ),
- .pipe_rx0_status_o (PIPERX0STATUS ),
- .pipe_rx0_phy_status_o (PIPERX0PHYSTATUS ),
- .pipe_rx0_elec_idle_i (PIPERX0ELECIDLEGT ),
- .pipe_rx0_polarity_i (PIPERX0POLARITY ),
- .pipe_tx0_compliance_i (PIPETX0COMPLIANCE ),
- .pipe_tx0_char_is_k_i (PIPETX0CHARISK ),
- .pipe_tx0_data_i (PIPETX0DATA ),
- .pipe_tx0_elec_idle_i (PIPETX0ELECIDLE ),
- .pipe_tx0_powerdown_i (PIPETX0POWERDOWN ),
-
- .pipe_rx0_char_is_k_i (PIPERX0CHARISKGT ),
- .pipe_rx0_data_i (PIPERX0DATAGT ),
- .pipe_rx0_valid_i (PIPERX0VALIDGT ),
- .pipe_rx0_chanisaligned_i (PIPERX0CHANISALIGNEDGT ),
- .pipe_rx0_status_i (PIPERX0STATUSGT ),
- .pipe_rx0_phy_status_i (PIPERX0PHYSTATUSGT ),
- .pipe_rx0_elec_idle_o (PIPERX0ELECIDLE ),
- .pipe_rx0_polarity_o (PIPERX0POLARITYGT ),
- .pipe_tx0_compliance_o (PIPETX0COMPLIANCEGT ),
- .pipe_tx0_char_is_k_o (PIPETX0CHARISKGT ),
- .pipe_tx0_data_o (PIPETX0DATAGT ),
- .pipe_tx0_elec_idle_o (PIPETX0ELECIDLEGT ),
- .pipe_tx0_powerdown_o (PIPETX0POWERDOWNGT ),
-
- // Pipe Per-Lane Signals - Lane 1
- .pipe_rx1_char_is_k_o (PIPERX1CHARISK ),
- .pipe_rx1_data_o (PIPERX1DATA ),
- .pipe_rx1_valid_o (PIPERX1VALID ),
- .pipe_rx1_chanisaligned_o (PIPERX1CHANISALIGNED ),
- .pipe_rx1_status_o (PIPERX1STATUS ),
- .pipe_rx1_phy_status_o (PIPERX1PHYSTATUS ),
- .pipe_rx1_elec_idle_i (PIPERX1ELECIDLEGT ),
- .pipe_rx1_polarity_i (PIPERX1POLARITY ),
- .pipe_tx1_compliance_i (PIPETX1COMPLIANCE ),
- .pipe_tx1_char_is_k_i (PIPETX1CHARISK ),
- .pipe_tx1_data_i (PIPETX1DATA ),
- .pipe_tx1_elec_idle_i (PIPETX1ELECIDLE ),
- .pipe_tx1_powerdown_i (PIPETX1POWERDOWN ),
-
- .pipe_rx1_char_is_k_i (PIPERX1CHARISKGT ),
- .pipe_rx1_data_i (PIPERX1DATAGT ),
- .pipe_rx1_valid_i (PIPERX1VALIDGT ),
- .pipe_rx1_chanisaligned_i (PIPERX1CHANISALIGNEDGT ),
- .pipe_rx1_status_i (PIPERX1STATUSGT ),
- .pipe_rx1_phy_status_i (PIPERX1PHYSTATUSGT ),
- .pipe_rx1_elec_idle_o (PIPERX1ELECIDLE ),
- .pipe_rx1_polarity_o (PIPERX1POLARITYGT ),
- .pipe_tx1_compliance_o (PIPETX1COMPLIANCEGT ),
- .pipe_tx1_char_is_k_o (PIPETX1CHARISKGT ),
- .pipe_tx1_data_o (PIPETX1DATAGT ),
- .pipe_tx1_elec_idle_o (PIPETX1ELECIDLEGT ),
- .pipe_tx1_powerdown_o (PIPETX1POWERDOWNGT ),
-
- // Pipe Per-Lane Signals - Lane 2
- .pipe_rx2_char_is_k_o (PIPERX2CHARISK ),
- .pipe_rx2_data_o (PIPERX2DATA ),
- .pipe_rx2_valid_o (PIPERX2VALID ),
- .pipe_rx2_chanisaligned_o (PIPERX2CHANISALIGNED ),
- .pipe_rx2_status_o (PIPERX2STATUS ),
- .pipe_rx2_phy_status_o (PIPERX2PHYSTATUS ),
- .pipe_rx2_elec_idle_i (PIPERX2ELECIDLEGT ),
- .pipe_rx2_polarity_i (PIPERX2POLARITY ),
- .pipe_tx2_compliance_i (PIPETX2COMPLIANCE ),
- .pipe_tx2_char_is_k_i (PIPETX2CHARISK ),
- .pipe_tx2_data_i (PIPETX2DATA ),
- .pipe_tx2_elec_idle_i (PIPETX2ELECIDLE ),
- .pipe_tx2_powerdown_i (PIPETX2POWERDOWN ),
-
- .pipe_rx2_char_is_k_i (PIPERX2CHARISKGT ),
- .pipe_rx2_data_i (PIPERX2DATAGT ),
- .pipe_rx2_valid_i (PIPERX2VALIDGT ),
- .pipe_rx2_chanisaligned_i (PIPERX2CHANISALIGNEDGT ),
- .pipe_rx2_status_i (PIPERX2STATUSGT ),
- .pipe_rx2_phy_status_i (PIPERX2PHYSTATUSGT ),
- .pipe_rx2_elec_idle_o (PIPERX2ELECIDLE ),
- .pipe_rx2_polarity_o (PIPERX2POLARITYGT ),
- .pipe_tx2_compliance_o (PIPETX2COMPLIANCEGT ),
- .pipe_tx2_char_is_k_o (PIPETX2CHARISKGT ),
- .pipe_tx2_data_o (PIPETX2DATAGT ),
- .pipe_tx2_elec_idle_o (PIPETX2ELECIDLEGT ),
- .pipe_tx2_powerdown_o (PIPETX2POWERDOWNGT ),
-
- // Pipe Per-Lane Signals - Lane 3
- .pipe_rx3_char_is_k_o (PIPERX3CHARISK ),
- .pipe_rx3_data_o (PIPERX3DATA ),
- .pipe_rx3_valid_o (PIPERX3VALID ),
- .pipe_rx3_chanisaligned_o (PIPERX3CHANISALIGNED ),
- .pipe_rx3_status_o (PIPERX3STATUS ),
- .pipe_rx3_phy_status_o (PIPERX3PHYSTATUS ),
- .pipe_rx3_elec_idle_i (PIPERX3ELECIDLEGT ),
- .pipe_rx3_polarity_i (PIPERX3POLARITY ),
- .pipe_tx3_compliance_i (PIPETX3COMPLIANCE ),
- .pipe_tx3_char_is_k_i (PIPETX3CHARISK ),
- .pipe_tx3_data_i (PIPETX3DATA ),
- .pipe_tx3_elec_idle_i (PIPETX3ELECIDLE ),
- .pipe_tx3_powerdown_i (PIPETX3POWERDOWN ),
-
- .pipe_rx3_char_is_k_i (PIPERX3CHARISKGT ),
- .pipe_rx3_data_i (PIPERX3DATAGT ),
- .pipe_rx3_valid_i (PIPERX3VALIDGT ),
- .pipe_rx3_chanisaligned_i (PIPERX3CHANISALIGNEDGT ),
- .pipe_rx3_status_i (PIPERX3STATUSGT ),
- .pipe_rx3_phy_status_i (PIPERX3PHYSTATUSGT ),
- .pipe_rx3_elec_idle_o (PIPERX3ELECIDLE ),
- .pipe_rx3_polarity_o (PIPERX3POLARITYGT ),
- .pipe_tx3_compliance_o (PIPETX3COMPLIANCEGT ),
- .pipe_tx3_char_is_k_o (PIPETX3CHARISKGT ),
- .pipe_tx3_data_o (PIPETX3DATAGT ),
- .pipe_tx3_elec_idle_o (PIPETX3ELECIDLEGT ),
- .pipe_tx3_powerdown_o (PIPETX3POWERDOWNGT ),
-
- // Pipe Per-Lane Signals - Lane 4
- .pipe_rx4_char_is_k_o (PIPERX4CHARISK ),
- .pipe_rx4_data_o (PIPERX4DATA ),
- .pipe_rx4_valid_o (PIPERX4VALID ),
- .pipe_rx4_chanisaligned_o (PIPERX4CHANISALIGNED ),
- .pipe_rx4_status_o (PIPERX4STATUS ),
- .pipe_rx4_phy_status_o (PIPERX4PHYSTATUS ),
- .pipe_rx4_elec_idle_i (PIPERX4ELECIDLEGT ),
- .pipe_rx4_polarity_i (PIPERX4POLARITY ),
- .pipe_tx4_compliance_i (PIPETX4COMPLIANCE ),
- .pipe_tx4_char_is_k_i (PIPETX4CHARISK ),
- .pipe_tx4_data_i (PIPETX4DATA ),
- .pipe_tx4_elec_idle_i (PIPETX4ELECIDLE ),
- .pipe_tx4_powerdown_i (PIPETX4POWERDOWN ),
-
- .pipe_rx4_char_is_k_i (PIPERX4CHARISKGT ),
- .pipe_rx4_data_i (PIPERX4DATAGT ),
- .pipe_rx4_valid_i (PIPERX4VALIDGT ),
- .pipe_rx4_chanisaligned_i (PIPERX4CHANISALIGNEDGT ),
- .pipe_rx4_status_i (PIPERX4STATUSGT ),
- .pipe_rx4_phy_status_i (PIPERX4PHYSTATUSGT ),
- .pipe_rx4_elec_idle_o (PIPERX4ELECIDLE ),
- .pipe_rx4_polarity_o (PIPERX4POLARITYGT ),
- .pipe_tx4_compliance_o (PIPETX4COMPLIANCEGT ),
- .pipe_tx4_char_is_k_o (PIPETX4CHARISKGT ),
- .pipe_tx4_data_o (PIPETX4DATAGT ),
- .pipe_tx4_elec_idle_o (PIPETX4ELECIDLEGT ),
- .pipe_tx4_powerdown_o (PIPETX4POWERDOWNGT ),
-
- // Pipe Per-Lane Signals - Lane 5
- .pipe_rx5_char_is_k_o (PIPERX5CHARISK ),
- .pipe_rx5_data_o (PIPERX5DATA ),
- .pipe_rx5_valid_o (PIPERX5VALID ),
- .pipe_rx5_chanisaligned_o (PIPERX5CHANISALIGNED ),
- .pipe_rx5_status_o (PIPERX5STATUS ),
- .pipe_rx5_phy_status_o (PIPERX5PHYSTATUS ),
- .pipe_rx5_elec_idle_i (PIPERX5ELECIDLEGT ),
- .pipe_rx5_polarity_i (PIPERX5POLARITY ),
- .pipe_tx5_compliance_i (PIPETX5COMPLIANCE ),
- .pipe_tx5_char_is_k_i (PIPETX5CHARISK ),
- .pipe_tx5_data_i (PIPETX5DATA ),
- .pipe_tx5_elec_idle_i (PIPETX5ELECIDLE ),
- .pipe_tx5_powerdown_i (PIPETX5POWERDOWN ),
-
- .pipe_rx5_char_is_k_i (PIPERX5CHARISKGT ),
- .pipe_rx5_data_i (PIPERX5DATAGT ),
- .pipe_rx5_valid_i (PIPERX5VALIDGT ),
- .pipe_rx5_chanisaligned_i (PIPERX5CHANISALIGNEDGT ),
- .pipe_rx5_status_i (PIPERX5STATUSGT ),
- .pipe_rx5_phy_status_i (PIPERX5PHYSTATUSGT ),
- .pipe_rx5_elec_idle_o (PIPERX5ELECIDLE ),
- .pipe_rx5_polarity_o (PIPERX5POLARITYGT ),
- .pipe_tx5_compliance_o (PIPETX5COMPLIANCEGT ),
- .pipe_tx5_char_is_k_o (PIPETX5CHARISKGT ),
- .pipe_tx5_data_o (PIPETX5DATAGT ),
- .pipe_tx5_elec_idle_o (PIPETX5ELECIDLEGT ),
- .pipe_tx5_powerdown_o (PIPETX5POWERDOWNGT ),
-
- // Pipe Per-Lane Signals - Lane 6
- .pipe_rx6_char_is_k_o (PIPERX6CHARISK ),
- .pipe_rx6_data_o (PIPERX6DATA ),
- .pipe_rx6_valid_o (PIPERX6VALID ),
- .pipe_rx6_chanisaligned_o (PIPERX6CHANISALIGNED ),
- .pipe_rx6_status_o (PIPERX6STATUS ),
- .pipe_rx6_phy_status_o (PIPERX6PHYSTATUS ),
- .pipe_rx6_elec_idle_i (PIPERX6ELECIDLEGT ),
- .pipe_rx6_polarity_i (PIPERX6POLARITY ),
- .pipe_tx6_compliance_i (PIPETX6COMPLIANCE ),
- .pipe_tx6_char_is_k_i (PIPETX6CHARISK ),
- .pipe_tx6_data_i (PIPETX6DATA ),
- .pipe_tx6_elec_idle_i (PIPETX6ELECIDLE ),
- .pipe_tx6_powerdown_i (PIPETX6POWERDOWN ),
-
- .pipe_rx6_char_is_k_i (PIPERX6CHARISKGT ),
- .pipe_rx6_data_i (PIPERX6DATAGT ),
- .pipe_rx6_valid_i (PIPERX6VALIDGT ),
- .pipe_rx6_chanisaligned_i (PIPERX6CHANISALIGNEDGT ),
- .pipe_rx6_status_i (PIPERX6STATUSGT ),
- .pipe_rx6_phy_status_i (PIPERX6PHYSTATUSGT ),
- .pipe_rx6_elec_idle_o (PIPERX6ELECIDLE ),
- .pipe_rx6_polarity_o (PIPERX6POLARITYGT ),
- .pipe_tx6_compliance_o (PIPETX6COMPLIANCEGT ),
- .pipe_tx6_char_is_k_o (PIPETX6CHARISKGT ),
- .pipe_tx6_data_o (PIPETX6DATAGT ),
- .pipe_tx6_elec_idle_o (PIPETX6ELECIDLEGT ),
- .pipe_tx6_powerdown_o (PIPETX6POWERDOWNGT ),
-
- // Pipe Per-Lane Signals - Lane 7
- .pipe_rx7_char_is_k_o (PIPERX7CHARISK ),
- .pipe_rx7_data_o (PIPERX7DATA ),
- .pipe_rx7_valid_o (PIPERX7VALID ),
- .pipe_rx7_chanisaligned_o (PIPERX7CHANISALIGNED ),
- .pipe_rx7_status_o (PIPERX7STATUS ),
- .pipe_rx7_phy_status_o (PIPERX7PHYSTATUS ),
- .pipe_rx7_elec_idle_i (PIPERX7ELECIDLEGT ),
- .pipe_rx7_polarity_i (PIPERX7POLARITY ),
- .pipe_tx7_compliance_i (PIPETX7COMPLIANCE ),
- .pipe_tx7_char_is_k_i (PIPETX7CHARISK ),
- .pipe_tx7_data_i (PIPETX7DATA ),
- .pipe_tx7_elec_idle_i (PIPETX7ELECIDLE ),
- .pipe_tx7_powerdown_i (PIPETX7POWERDOWN ),
-
- .pipe_rx7_char_is_k_i (PIPERX7CHARISKGT ),
- .pipe_rx7_data_i (PIPERX7DATAGT ),
- .pipe_rx7_valid_i (PIPERX7VALIDGT ),
- .pipe_rx7_chanisaligned_i (PIPERX7CHANISALIGNEDGT ),
- .pipe_rx7_status_i (PIPERX7STATUSGT ),
- .pipe_rx7_phy_status_i (PIPERX7PHYSTATUSGT ),
- .pipe_rx7_elec_idle_o (PIPERX7ELECIDLE ),
- .pipe_rx7_polarity_o (PIPERX7POLARITYGT ),
- .pipe_tx7_compliance_o (PIPETX7COMPLIANCEGT ),
- .pipe_tx7_char_is_k_o (PIPETX7CHARISKGT ),
- .pipe_tx7_data_o (PIPETX7DATAGT ),
- .pipe_tx7_elec_idle_o (PIPETX7ELECIDLEGT ),
- .pipe_tx7_powerdown_o (PIPETX7POWERDOWNGT ),
-
- // Non PIPE signals
- .pl_ltssm_state (PLLTSSMSTATE ),
- .pipe_clk (PIPECLK ),
- .rst_n (PHYRDYN )
-);
-
-//-------------------------------------------------------
-// Virtex6 GTX Module
-//-------------------------------------------------------
-
-pcie_gtx_v6 #(
-
- .NO_OF_LANES(LINK_CAP_MAX_LINK_WIDTH),
- .LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
- .REF_CLK_FREQ(REF_CLK_FREQ),
- .PL_FAST_TRAIN(PL_FAST_TRAIN)
-
-)
-pcie_gt_i (
-
- // Pipe Common Signals
- .pipe_tx_rcvr_det (PIPETXRCVRDETGT ),
- .pipe_tx_reset (1'b0 ),
- .pipe_tx_rate (PIPETXRATEGT ),
- .pipe_tx_deemph (PIPETXDEEMPHGT ),
- .pipe_tx_margin (PIPETXMARGINGT ),
- .pipe_tx_swing (1'b0),
-
- // Pipe Per-Lane Signals - Lane 0
- .pipe_rx0_char_is_k (PIPERX0CHARISKGT ),
- .pipe_rx0_data (PIPERX0DATAGT ),
- .pipe_rx0_valid (PIPERX0VALIDGT ),
- .pipe_rx0_chanisaligned (PIPERX0CHANISALIGNEDGT ),
- .pipe_rx0_status (PIPERX0STATUSGT ),
- .pipe_rx0_phy_status (PIPERX0PHYSTATUSGT ),
- .pipe_rx0_elec_idle (PIPERX0ELECIDLEGT ),
- .pipe_rx0_polarity (PIPERX0POLARITYGT ),
- .pipe_tx0_compliance (PIPETX0COMPLIANCEGT ),
- .pipe_tx0_char_is_k (PIPETX0CHARISKGT ),
- .pipe_tx0_data (PIPETX0DATAGT ),
- .pipe_tx0_elec_idle (PIPETX0ELECIDLEGT ),
- .pipe_tx0_powerdown (PIPETX0POWERDOWNGT ),
-
- // Pipe Per-Lane Signals - Lane 1
- .pipe_rx1_char_is_k (PIPERX1CHARISKGT ),
- .pipe_rx1_data (PIPERX1DATAGT ),
- .pipe_rx1_valid (PIPERX1VALIDGT ),
- .pipe_rx1_chanisaligned (PIPERX1CHANISALIGNEDGT ),
- .pipe_rx1_status (PIPERX1STATUSGT ),
- .pipe_rx1_phy_status (PIPERX1PHYSTATUSGT ),
- .pipe_rx1_elec_idle (PIPERX1ELECIDLEGT ),
- .pipe_rx1_polarity (PIPERX1POLARITYGT ),
- .pipe_tx1_compliance (PIPETX1COMPLIANCEGT ),
- .pipe_tx1_char_is_k (PIPETX1CHARISKGT ),
- .pipe_tx1_data (PIPETX1DATAGT ),
- .pipe_tx1_elec_idle (PIPETX1ELECIDLEGT ),
- .pipe_tx1_powerdown (PIPETX1POWERDOWNGT ),
-
- // Pipe Per-Lane Signals - Lane 2
- .pipe_rx2_char_is_k (PIPERX2CHARISKGT ),
- .pipe_rx2_data (PIPERX2DATAGT ),
- .pipe_rx2_valid (PIPERX2VALIDGT ),
- .pipe_rx2_chanisaligned (PIPERX2CHANISALIGNEDGT ),
- .pipe_rx2_status (PIPERX2STATUSGT ),
- .pipe_rx2_phy_status (PIPERX2PHYSTATUSGT ),
- .pipe_rx2_elec_idle (PIPERX2ELECIDLEGT ),
- .pipe_rx2_polarity (PIPERX2POLARITYGT ),
- .pipe_tx2_compliance (PIPETX2COMPLIANCEGT ),
- .pipe_tx2_char_is_k (PIPETX2CHARISKGT ),
- .pipe_tx2_data (PIPETX2DATAGT ),
- .pipe_tx2_elec_idle (PIPETX2ELECIDLEGT ),
- .pipe_tx2_powerdown (PIPETX2POWERDOWNGT ),
-
- // Pipe Per-Lane Signals - Lane 3
- .pipe_rx3_char_is_k (PIPERX3CHARISKGT ),
- .pipe_rx3_data (PIPERX3DATAGT ),
- .pipe_rx3_valid (PIPERX3VALIDGT ),
- .pipe_rx3_chanisaligned (PIPERX3CHANISALIGNEDGT ),
- .pipe_rx3_status (PIPERX3STATUSGT ),
- .pipe_rx3_phy_status (PIPERX3PHYSTATUSGT ),
- .pipe_rx3_elec_idle (PIPERX3ELECIDLEGT ),
- .pipe_rx3_polarity (PIPERX3POLARITYGT ),
- .pipe_tx3_compliance (PIPETX3COMPLIANCEGT ),
- .pipe_tx3_char_is_k (PIPETX3CHARISKGT ),
- .pipe_tx3_data (PIPETX3DATAGT ),
- .pipe_tx3_elec_idle (PIPETX3ELECIDLEGT ),
- .pipe_tx3_powerdown (PIPETX3POWERDOWNGT ),
-
- // Pipe Per-Lane Signals - Lane 4
- .pipe_rx4_char_is_k (PIPERX4CHARISKGT ),
- .pipe_rx4_data (PIPERX4DATAGT ),
- .pipe_rx4_valid (PIPERX4VALIDGT ),
- .pipe_rx4_chanisaligned (PIPERX4CHANISALIGNEDGT ),
- .pipe_rx4_status (PIPERX4STATUSGT ),
- .pipe_rx4_phy_status (PIPERX4PHYSTATUSGT ),
- .pipe_rx4_elec_idle (PIPERX4ELECIDLEGT ),
- .pipe_rx4_polarity (PIPERX4POLARITYGT ),
- .pipe_tx4_compliance (PIPETX4COMPLIANCEGT ),
- .pipe_tx4_char_is_k (PIPETX4CHARISKGT ),
- .pipe_tx4_data (PIPETX4DATAGT ),
- .pipe_tx4_elec_idle (PIPETX4ELECIDLEGT ),
- .pipe_tx4_powerdown (PIPETX4POWERDOWNGT ),
-
- // Pipe Per-Lane Signals - Lane 5
- .pipe_rx5_char_is_k (PIPERX5CHARISKGT ),
- .pipe_rx5_data (PIPERX5DATAGT ),
- .pipe_rx5_valid (PIPERX5VALIDGT ),
- .pipe_rx5_chanisaligned (PIPERX5CHANISALIGNEDGT ),
- .pipe_rx5_status (PIPERX5STATUSGT ),
- .pipe_rx5_phy_status (PIPERX5PHYSTATUSGT ),
- .pipe_rx5_elec_idle (PIPERX5ELECIDLEGT ),
- .pipe_rx5_polarity (PIPERX5POLARITYGT ),
- .pipe_tx5_compliance (PIPETX5COMPLIANCEGT ),
- .pipe_tx5_char_is_k (PIPETX5CHARISKGT ),
- .pipe_tx5_data (PIPETX5DATAGT ),
- .pipe_tx5_elec_idle (PIPETX5ELECIDLEGT ),
- .pipe_tx5_powerdown (PIPETX5POWERDOWNGT ),
-
- // Pipe Per-Lane Signals - Lane 6
- .pipe_rx6_char_is_k (PIPERX6CHARISKGT ),
- .pipe_rx6_data (PIPERX6DATAGT ),
- .pipe_rx6_valid (PIPERX6VALIDGT ),
- .pipe_rx6_chanisaligned (PIPERX6CHANISALIGNEDGT ),
- .pipe_rx6_status (PIPERX6STATUSGT ),
- .pipe_rx6_phy_status (PIPERX6PHYSTATUSGT ),
- .pipe_rx6_elec_idle (PIPERX6ELECIDLEGT ),
- .pipe_rx6_polarity (PIPERX6POLARITYGT ),
- .pipe_tx6_compliance (PIPETX6COMPLIANCEGT ),
- .pipe_tx6_char_is_k (PIPETX6CHARISKGT ),
- .pipe_tx6_data (PIPETX6DATAGT ),
- .pipe_tx6_elec_idle (PIPETX6ELECIDLEGT ),
- .pipe_tx6_powerdown (PIPETX6POWERDOWNGT ),
-
- // Pipe Per-Lane Signals - Lane 7
- .pipe_rx7_char_is_k (PIPERX7CHARISKGT ),
- .pipe_rx7_data (PIPERX7DATAGT ),
- .pipe_rx7_valid (PIPERX7VALIDGT ),
- .pipe_rx7_chanisaligned (PIPERX7CHANISALIGNEDGT ),
- .pipe_rx7_status (PIPERX7STATUSGT ),
- .pipe_rx7_phy_status (PIPERX7PHYSTATUSGT ),
- .pipe_rx7_elec_idle (PIPERX7ELECIDLEGT ),
- .pipe_rx7_polarity (PIPERX7POLARITYGT ),
- .pipe_tx7_compliance (PIPETX7COMPLIANCEGT ),
- .pipe_tx7_char_is_k (PIPETX7CHARISKGT ),
- .pipe_tx7_data (PIPETX7DATAGT ),
- .pipe_tx7_elec_idle (PIPETX7ELECIDLEGT ),
- .pipe_tx7_powerdown (PIPETX7POWERDOWNGT ),
-
- // PCI Express Signals
- .pci_exp_txn (PCIEXPTXN ),
- .pci_exp_txp (PCIEXPTXP ),
- .pci_exp_rxn (PCIEXPRXN ),
- .pci_exp_rxp (PCIEXPRXP ),
-
- // Non PIPE Signals
- .sys_clk (SYSCLK ),
- .sys_rst_n (FUNDRSTN ),
- .pipe_clk (PIPECLK ),
- .clock_locked (CLOCKLOCKED ),
- .pl_ltssm_state (PLLTSSMSTATE ),
-
- .gt_pll_lock (GTPLLLOCK ),
- .phy_rdy_n (PHYRDYN )
-
-);
-
-//-------------------------------------------------------
-// PCI Express BRAM Module
-//-------------------------------------------------------
-
-pcie_bram_top_v6 #(
-
- .DEV_CAP_MAX_PAYLOAD_SUPPORTED(DEV_CAP_MAX_PAYLOAD_SUPPORTED),
-
- .VC0_TX_LASTPACKET(VC0_TX_LASTPACKET),
- .TL_TX_RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),
- .TL_TX_RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),
- .TL_TX_RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY),
-
- .VC0_RX_LIMIT(VC0_RX_RAM_LIMIT),
- .TL_RX_RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),
- .TL_RX_RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),
- .TL_RX_RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY)
-
-)
-pcie_bram_i (
-
- .user_clk_i( USERCLK ),
- .reset_i( PHYRDYN ),
-
- .mim_tx_waddr( MIMTXWADDR ),
- .mim_tx_wen( MIMTXWEN ),
- .mim_tx_ren( MIMTXREN ),
- .mim_tx_rce( MIMTXRCE ),
- .mim_tx_wdata( MIMTXWDATA ),
- .mim_tx_raddr( MIMTXRADDR ),
- .mim_tx_rdata( MIMTXRDATA ),
-
- .mim_rx_waddr( MIMRXWADDR ),
- .mim_rx_wen( MIMRXWEN ),
- .mim_rx_ren( MIMRXREN ),
- .mim_rx_rce( MIMRXRCE ),
- .mim_rx_wdata( MIMRXWDATA ),
- .mim_rx_raddr( MIMRXRADDR ),
- .mim_rx_rdata( MIMRXRDATA )
-
-);
-
-
-//-------------------------------------------------------
-// PCI Express Port Workarounds
-//-------------------------------------------------------
-
-pcie_upconfig_fix_3451_v6 # (
-
- .UPSTREAM_FACING ( UPSTREAM_FACING ),
- .PL_FAST_TRAIN ( PL_FAST_TRAIN ),
- .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH )
-
-)
-pcie_upconfig_fix_3451_v6_i (
-
- .pipe_clk(PIPECLK),
- .pl_phy_lnkup_n(PLPHYLNKUPN),
-
- .pl_ltssm_state(PLLTSSMSTATE),
- .pl_sel_lnk_rate(PLSELLNKRATE),
- .pl_directed_link_change(PLDIRECTEDLINKCHANGE),
-
- .cfg_link_status_negotiated_width(CFGLINKSTATUSNEGOTIATEDWIDTH),
-
- .filter_pipe(filter_pipe_upconfig_fix_3451)
-
-);
-
-endmodule
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_bram_v6.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_bram_v6.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_bram_v6.v (nonexistent)
@@ -1,287 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : pcie_bram_v6.v
-//--
-//-- Description: BlockRAM module for Virtex6 PCIe Block
-//--
-//--
-//--
-//--------------------------------------------------------------------------------
-
-`timescale 1ns/1ns
-
-module pcie_bram_v6
- #(
- parameter DOB_REG = 0,// 1 use the output register 0 don't use the output register
- parameter WIDTH = 0 // supported WIDTH's are: 4, 9, 18, 36 (uses RAMB36) and 72 (uses RAMB36SDP)
- )
- (
- input user_clk_i,// user clock
- input reset_i, // bram reset
-
- input wen_i, // write enable
- input [12:0] waddr_i, // write address
- input [WIDTH - 1:0] wdata_i, // write data
-
- input ren_i, // read enable
- input rce_i, // output register clock enable
- input [12:0] raddr_i, // read address
-
- output [WIDTH - 1:0] rdata_o // read data
- );
-
- // map the address bits
- localparam ADDR_MSB = ((WIDTH == 4) ? 12 :
- (WIDTH == 9) ? 11 :
- (WIDTH == 18) ? 10 :
- (WIDTH == 36) ? 9 :
- 8
- );
-
- // set the width of the tied off low address bits
- localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
- (WIDTH == 9) ? 3 :
- (WIDTH == 18) ? 4 :
- (WIDTH == 36) ? 5 :
- 0 // for WIDTH 72 use RAMB36SDP
- );
-
- // map the data bits
- localparam D_MSB = ((WIDTH == 4) ? 3 :
- (WIDTH == 9) ? 7 :
- (WIDTH == 18) ? 15 :
- (WIDTH == 36) ? 31 :
- 63
- );
-
- // map the data parity bits
- localparam DP_LSB = D_MSB + 1;
-
- localparam DP_MSB = ((WIDTH == 4) ? 4 :
- (WIDTH == 9) ? 8 :
- (WIDTH == 18) ? 17 :
- (WIDTH == 36) ? 35 :
- 71
- );
-
- localparam DPW = DP_MSB - DP_LSB + 1;
-
- localparam WRITE_MODE = "NO_CHANGE";
-
- //synthesis translate_off
- initial begin
- //$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
- // $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
-
- case (WIDTH)
- 4,9,18,36,72:;
- default:
- begin
- $display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
- $finish;
- end
- endcase // case (WIDTH)
- end
- //synthesis translate_on
-
- generate
- if (WIDTH == 72) begin : use_ramb36sdp
-
- // use RAMB36SDP if the width is 72
- RAMB36SDP #(
- .DO_REG (DOB_REG)
- )
- ramb36sdp(
- .WRCLK (user_clk_i),
- .SSR (1'b0),
- .WRADDR (waddr_i[ADDR_MSB:0]),
- .DI (wdata_i[D_MSB:0]),
- .DIP (wdata_i[DP_MSB:DP_LSB]),
- .WREN (wen_i),
- .WE ({8{wen_i}}),
-
- .RDCLK (user_clk_i),
- .RDADDR (raddr_i[ADDR_MSB:0]),
- .DO (rdata_o[D_MSB:0]),
- .DOP (rdata_o[DP_MSB:DP_LSB]),
- .RDEN (ren_i),
- .REGCE (rce_i)
- );
-
- // use RAMB36's if the width is 4, 9, 18, or 36
- end else if (WIDTH == 36) begin : use_ramb36
-
- RAMB36 #(
- .DOA_REG (0),
- .DOB_REG (DOB_REG),
- .READ_WIDTH_A (0),
- .READ_WIDTH_B (WIDTH),
- .WRITE_WIDTH_A (WIDTH),
- .WRITE_WIDTH_B (0),
- .WRITE_MODE_A (WRITE_MODE)
- )
- ramb36(
- .CLKA (user_clk_i),
- .SSRA (1'b0),
- .REGCEA (1'b0),
- .CASCADEINLATA (1'b0),
- .CASCADEINREGA (1'b0),
- .CASCADEOUTLATA (),
- .CASCADEOUTREGA (),
- .DOA (),
- .DOPA (),
- .ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
- .DIA (wdata_i[D_MSB:0]),
- .DIPA (wdata_i[DP_MSB:DP_LSB]),
- .ENA (wen_i),
- .WEA ({4{wen_i}}),
-
- .CLKB (user_clk_i),
- .SSRB (1'b0),
- .WEB (4'b0),
- .CASCADEINLATB (1'b0),
- .CASCADEINREGB (1'b0),
- .CASCADEOUTLATB (),
- .CASCADEOUTREGB (),
- .DIB (32'b0),
- .DIPB ( 4'b0),
- .ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
- .DOB (rdata_o[D_MSB:0]),
- .DOPB (rdata_o[DP_MSB:DP_LSB]),
- .ENB (ren_i),
- .REGCEB (rce_i)
- );
-
- end else if (WIDTH < 36 && WIDTH > 4) begin : use_ramb36
-
- wire [31 - D_MSB - 1 : 0] dob_unused;
- wire [ 4 - DPW - 1 : 0] dopb_unused;
-
- RAMB36 #(
- .DOA_REG (0),
- .DOB_REG (DOB_REG),
- .READ_WIDTH_A (0),
- .READ_WIDTH_B (WIDTH),
- .WRITE_WIDTH_A (WIDTH),
- .WRITE_WIDTH_B (0),
- .WRITE_MODE_A (WRITE_MODE)
- )
- ramb36(
- .CLKA (user_clk_i),
- .SSRA (1'b0),
- .REGCEA (1'b0),
- .CASCADEINLATA (1'b0),
- .CASCADEINREGA (1'b0),
- .CASCADEOUTLATA (),
- .CASCADEOUTREGA (),
- .DOA (),
- .DOPA (),
- .ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
- .DIA ({{31 - D_MSB{1'b0}},wdata_i[D_MSB:0]}),
- .DIPA ({{ 4 - DPW {1'b0}},wdata_i[DP_MSB:DP_LSB]}),
- .ENA (wen_i),
- .WEA ({4{wen_i}}),
-
- .CLKB (user_clk_i),
- .SSRB (1'b0),
- .WEB (4'b0),
- .CASCADEINLATB (1'b0),
- .CASCADEINREGB (1'b0),
- .CASCADEOUTLATB (),
- .CASCADEOUTREGB (),
- .DIB (32'b0),
- .DIPB ( 4'b0),
- .ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
- .DOB ({dob_unused, rdata_o[D_MSB:0]}),
- .DOPB ({dopb_unused, rdata_o[DP_MSB:DP_LSB]}),
- .ENB (ren_i),
- .REGCEB (rce_i)
- );
-
- end else if (WIDTH == 4) begin : use_ramb36
-
- wire [31 - D_MSB - 1 : 0] dob_unused;
-
- RAMB36 #(
- .DOB_REG (DOB_REG),
- .READ_WIDTH_A (0),
- .READ_WIDTH_B (WIDTH),
- .WRITE_WIDTH_A (WIDTH),
- .WRITE_WIDTH_B (0),
- .WRITE_MODE_A (WRITE_MODE)
- )
- ramb36(
- .CLKA (user_clk_i),
- .SSRA (1'b0),
- .REGCEA (1'b0),
- .CASCADEINLATA (1'b0),
- .CASCADEINREGA (1'b0),
- .CASCADEOUTLATA (),
- .CASCADEOUTREGA (),
- .DOA (),
- .DOPA (),
- .ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
- .DIA ({{31 - D_MSB{1'b0}},wdata_i[D_MSB:0]}),
- //.DIPA (wdata_i[DP_MSB:DP_LSB]),
- .ENA (wen_i),
- .WEA ({4{wen_i}}),
-
- .CLKB (user_clk_i),
- .SSRB (1'b0),
- .WEB (4'b0),
- .CASCADEINLATB (1'b0),
- .CASCADEINREGB (1'b0),
- .CASCADEOUTLATB (),
- .CASCADEOUTREGB (),
- .ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
- .DOB ({dob_unused,rdata_o[D_MSB:0]}),
- //.DOPB (rdata_o[DP_MSB:DP_LSB]),
- .ENB (ren_i),
- .REGCEB (rce_i)
- );
-
- end // block: use_ramb36
- endgenerate
-
-endmodule // pcie_bram_v6
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_tx_sync_rate_v6.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_tx_sync_rate_v6.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_tx_sync_rate_v6.v (nonexistent)
@@ -1,413 +0,0 @@
-
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : gtx_tx_sync_rate_v6.v
-//////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-`define DLY #1
-
-module GTX_TX_SYNC_RATE_V6
-#(
- parameter C_SIMULATION = 0 // Set to 1 for simulation
-)
-(
- output ENPMAPHASEALIGN,
- output PMASETPHASE,
- output SYNC_DONE,
- output OUT_DIV_RESET,
- output PCS_RESET,
- output USER_PHYSTATUS,
- output RATE_CLK_SEL,
- input USER_CLK,
- input RESET,
- input RATE,
- input RATEDONE,
- input GT_PHYSTATUS,
- input RESETDONE,
-
- // Test bits / status
- output [53:0] DEBUG_STATUS,
- input [2:0] ENPMA_STATE_MASK,
- input [2:0] OUTDIV_STATE_MASK
-
-);
-
-// synthesis attribute X_CORE_INFO of TX_SYNC is "v6_gtxwizard_v1_0, Coregen v11.1_ip1";
-
-//*******************************Register Declarations************************
-
- reg begin_r;
- reg phase_align_r;
- reg ready_r;
- reg [15:0] sync_counter_r;
- reg [5:0] count_32_cycles_r;
- reg wait_stable_r;
- reg phase_align_reset_r;
- reg out_div_reset_r;
- reg wait_phase_align_reset_r;
- reg pcs_reset_r;
- reg wait_reset_done_r;
- reg gen_phystatus_r;
- reg rate_r;
- reg guard_r;
- reg resetdone_r;
- reg resetdone_r2;
- reg ratedone_r;
- reg ratedone_r2;
- reg rate_sel_r;
-
- reg enpmaphasealign_r;
- reg reg_out_div_reset_r;
- reg [24:0] rate_duration_count_r;
-
-
-//*******************************Wire Declarations****************************
-
- wire count_setphase_complete_i;
- wire count_32_complete_i;
- wire next_phase_align_c;
- wire next_ready_c;
- wire next_wait_stable_c;
- wire next_phase_align_reset_c;
- wire next_out_div_reset_c;
- wire next_wait_phase_align_reset_c;
- wire next_pcs_reset_c;
- wire next_wait_reset_done_c;
- wire next_gen_phystatus_c;
- wire ratedone_pulse_i;
-
- wire enpmaphasealign_i;
- wire out_div_reset_i;
-
-//*******************************Main Body of Code****************************
-
-
-
-
- //________________________________ State machine __________________________
- // This state machine manages the phase alingment procedure of the GTX.
- // The module is held in reset till the usrclk source is stable. In the
- // case of buffer bypass where the refclkout is used to clock the usrclks,
- // the usrclk stable indication is given the pll_locked signal.
- // Once the pll_lock is asserted, state machine goes into the
- // wait_stable_r for 32 clock cycles to allow some time to ensure the pll
- // is stable. After this, it goes into the phase_align_r state where the
- // phase alignment procedure is executed. This involves asserting the
- // ENPMAPHASEALIGN and PMASETPHASE for 32768 clock cycles.
- //
- // If there is a line rate change, the module resets the output divider by
- // asserting the signal for 16 clock cycles and resets the phase alignment
- // block by de-asserting ENPMAPHASEALIGN signal for 16 clock cycles. The
- // phase alignment procedure as stated above is repeated. Afterwards, the
- // PCS is reset and a user PHYSTATUS is generated to notify the completion
- // of a line rate change procedure.
-
- // State registers
- always @(posedge USER_CLK)
- if(RESET)
- {begin_r, wait_stable_r, phase_align_r, ready_r,
- phase_align_reset_r, out_div_reset_r, wait_phase_align_reset_r,
- pcs_reset_r, wait_reset_done_r,
- gen_phystatus_r} <= `DLY 10'b10_0000_0000;
- else
- begin
- begin_r <= `DLY 1'b0;
- wait_stable_r <= `DLY next_wait_stable_c;
- phase_align_r <= `DLY next_phase_align_c;
- ready_r <= `DLY next_ready_c;
- phase_align_reset_r <= `DLY next_phase_align_reset_c;
- out_div_reset_r <= `DLY next_out_div_reset_c;
- wait_phase_align_reset_r <= `DLY next_wait_phase_align_reset_c;
- pcs_reset_r <= `DLY next_pcs_reset_c;
- wait_reset_done_r <= `DLY next_wait_reset_done_c;
- gen_phystatus_r <= `DLY next_gen_phystatus_c;
- end
-
- // Next state logic
- assign next_ready_c = (((phase_align_r & count_setphase_complete_i) & !guard_r) | gen_phystatus_r) |
- (!ratedone_pulse_i & ready_r);
-
- assign next_phase_align_reset_c = (ratedone_pulse_i & ready_r) |
- (phase_align_reset_r & !count_32_complete_i);
-
- assign next_out_div_reset_c = (phase_align_reset_r & count_32_complete_i)|
- (out_div_reset_r & !count_32_complete_i);
-
- assign next_wait_phase_align_reset_c = (out_div_reset_r & count_32_complete_i) |
- (wait_phase_align_reset_r & !count_32_complete_i);
-
- assign next_wait_stable_c = begin_r | (wait_phase_align_reset_r & count_32_complete_i) |
- (wait_stable_r & !count_32_complete_i);
-
- assign next_phase_align_c = (wait_stable_r & count_32_complete_i) |
- (phase_align_r & !count_setphase_complete_i);
-
- assign next_pcs_reset_c = ((phase_align_r & count_setphase_complete_i) & guard_r);
-
- assign next_wait_reset_done_c = pcs_reset_r |
- (!resetdone_r2 & wait_reset_done_r);
-
- assign next_gen_phystatus_c = resetdone_r2 & wait_reset_done_r;
-
-
- //_________ Counter for to wait for pll to be stable before sync __________
- always @(posedge USER_CLK)
- begin
- if (RESET || count_32_complete_i)
- count_32_cycles_r <= `DLY 6'b000000;
- else if (wait_stable_r || out_div_reset_r || phase_align_reset_r || wait_phase_align_reset_r)
- count_32_cycles_r <= `DLY count_32_cycles_r + 1'b1;
- end
-
- assign count_32_complete_i = count_32_cycles_r[5];
-
- //_______________ Counter for holding SYNC for SYNC_CYCLES ________________
- always @(posedge USER_CLK)
- begin
- if (!phase_align_r)
- sync_counter_r <= `DLY 16'h0000;
- else
- sync_counter_r <= `DLY sync_counter_r + 1'b1;
- end
-
- generate
- if (C_SIMULATION) begin: for_simulation
- // Shorten the cycle to 32 clock cycles for simulation
- assign count_setphase_complete_i = sync_counter_r[5];
- end
- else begin: for_hardware
- // For TXPMASETPHASE:
- // - If RATE[0] = 0, PLL_DIVSEL_OUT = 2 => 16,384 USRCLK2 cycles
- // - If RATE[0] = 1, PLL_DIVSEL_OUT = 1 => 8,192 USRCLK2 cycles
- assign count_setphase_complete_i = (rate_r) ? sync_counter_r[13] :
- sync_counter_r[14];
- end
- endgenerate
-
-
- //_______________ Assign the phase align ports into the GTX _______________
-
- // Assert the ENPMAPHASEALIGN signal when the reset of this module
- // gets de-asserted and after a reset of the output dividers. Disabling
- // this signal after reset of the output dividers will reset the phase
- // alignment module.
- //assign ENPMAPHASEALIGN = !(begin_r | phase_align_reset_r | out_div_reset_r | wait_phase_align_reset_r);
-
- // Masking the bits of each state to play around with the pulse of the
- // TXENPMAPHASEALIGN reset (active low signal)
- assign enpmaphasealign_i = ~((begin_r ||
- (phase_align_reset_r && ENPMA_STATE_MASK[2]) ||
- (out_div_reset_r && ENPMA_STATE_MASK[1]) ||
- (wait_phase_align_reset_r && ENPMA_STATE_MASK[0])));
-
- always @(posedge USER_CLK)
- if (RESET)
- enpmaphasealign_r <= `DLY 1'b0;
- else
- enpmaphasealign_r <= enpmaphasealign_i;
-
- assign ENPMAPHASEALIGN = enpmaphasealign_r;
-
- assign PMASETPHASE = phase_align_r;
-
-
- //_______________________ Assign the sync_done port _______________________
-
- // Assert the SYNC_DONE signal when the phase alignment procedure is
- // complete after initialization and when line rate change procedure
- // is complete.
- assign SYNC_DONE = ready_r & !guard_r;
-
-
- //_______________________ Assign the rest of the ports ____________________
- // Assert the output divider reset for 32 USRCLK2 clock cycles
- //assign OUT_DIV_RESET = out_div_reset_r;
-
- // Masking the bits of each state to play around with the pulse of the
- // output divider reset
- assign out_div_reset_i= (phase_align_reset_r && OUTDIV_STATE_MASK[2]) ||
- (out_div_reset_r && OUTDIV_STATE_MASK[1]) ||
- (wait_phase_align_reset_r && OUTDIV_STATE_MASK[0]);
-
- always @(posedge USER_CLK)
- if (RESET)
- reg_out_div_reset_r <= `DLY 1'b0;
- else
- reg_out_div_reset_r <= out_div_reset_i;
-
- assign OUT_DIV_RESET = reg_out_div_reset_r;
-
- // Assert the PCS reset for 1 USRCLK2 clock cycle
- assign PCS_RESET = pcs_reset_r;
-
-
- // Assert user phystatus at the end of the line rate change. It is also
- // a pass through signal from the GTX when the pulse is not associated
- // with a line rate change (in this module this signal is gated by
- // guard_r signal)
- assign USER_PHYSTATUS = gen_phystatus_r | (GT_PHYSTATUS & !guard_r);
-
-
- //////////////////////////////////////////////////////////////////////////
- // Register the RESETDONE input
- //////////////////////////////////////////////////////////////////////////
- always @(posedge USER_CLK)
-
- begin
- if (RESET | pcs_reset_r)
- begin
- resetdone_r <= `DLY 1'b0;
- resetdone_r2 <= `DLY 1'b0;
- end
- else
- begin
- resetdone_r <= `DLY RESETDONE;
- resetdone_r2 <= `DLY resetdone_r;
- end
- end
-
- //////////////////////////////////////////////////////////////////////////
- // Detect an edge on the RATEDONE signal and generate a pulse from it.
- // The RATEDONE signal by default is initialized to 1'b1.
- //////////////////////////////////////////////////////////////////////////
- always @(posedge USER_CLK)
-
- begin
- if (RESET)
- begin
- ratedone_r <= `DLY 1'b0;
- ratedone_r2 <= `DLY 1'b0;
- end
- else
- begin
- ratedone_r <= `DLY RATEDONE;
- ratedone_r2 <= `DLY ratedone_r;
- end
- end
-
- assign ratedone_pulse_i = ratedone_r & !ratedone_r2;
-
- //////////////////////////////////////////////////////////////////////////
- // Detect a line rate change. Since this is targeted for PCIe, we only
- // need to detect a change on TXRATE[0]/RXRATE[0]:
- // TXRATE[1:0] / RXRATE[1:0] = 10 for output divider /2
- // TXRATE[1:0] / RXRATE[1:0] = 11 for output divider /1
- //////////////////////////////////////////////////////////////////////////
- always @(posedge USER_CLK)
- begin
- rate_r <= `DLY RATE;
- end
-
- assign rate_change_i = rate_r ^ RATE;
-
-
- //////////////////////////////////////////////////////////////////////////
- // Generate an internal "guard" signal to denote that the line rate
- // sequence of operation initiated. This signal is driven High when the
- // there is a rate change trigger by a change in TXRATE or RXRATE ports.
- //////////////////////////////////////////////////////////////////////////
- always @(posedge USER_CLK)
- begin
- if (RESET | gen_phystatus_r)
- guard_r <= `DLY 1'b0;
- else if (rate_change_i == 1'b1)
- guard_r <= `DLY 1'b1;
- end
-
-
- //////////////////////////////////////////////////////////////////////////
- // Generate the BUFGMUX select signal that selects the correct clock to
- // used based on a rate change. For PCIe:
- // - RATE[0] = 0 => Use 125 MHz USRCLK2 with RATE_CLK_SEL = 0
- // - RATE[0] = 1 => Use 250 MHz USRCLK2 with RATE_CLK_SEL = 1
- // The RATE_CLK_SEL changes based on the RATEDONE signal from the GTX.
- // The default of this pin is set to 1'b0. Someone can change it to grab
- // the value from a parameter if the reset value has to be another value
- // other than 1'b0.
- //////////////////////////////////////////////////////////////////////////
- always @(posedge USER_CLK)
- begin
- if (RESET)
- rate_sel_r <= `DLY 1'b0;
- else if (ratedone_pulse_i == 1'b1)
- rate_sel_r <= `DLY rate_r;
- end
-
- assign RATE_CLK_SEL = rate_sel_r;
-
- //////////////////////////////////////////////////////////////////////////
- // Create a counter that starts when guard_r is High. After
- // guard_r gets de-asserted, the counter stops counting. The counter gets
- // reset when there is a rate change applied from the user; this rate
- // change pulse occurs one USER_CLK cycle earlier than guard_r.
- //////////////////////////////////////////////////////////////////////////
- always @(posedge USER_CLK)
- begin
- if (RESET | rate_change_i)
- rate_duration_count_r <= `DLY 25'b0_0000_0000_0000_0000_0000_0000;
- else if (guard_r)
- rate_duration_count_r <= `DLY rate_duration_count_r + 1'b1;
- else
- rate_duration_count_r <= `DLY rate_duration_count_r;
- end
-
-
- //Monitoring the signals on ILa
- assign DEBUG_STATUS= {sync_counter_r[15:0], //[53:38]
- rate_r, //[37]
- rate_duration_count_r[24:0],//[36:12]
- begin_r, //[11]
- wait_stable_r, //[10]
- phase_align_r, //[9]
- ready_r, //[8]
- phase_align_reset_r, //[7]
- out_div_reset_r, //[6]
- wait_phase_align_reset_r, //[5]
- pcs_reset_r, //[4]
- wait_reset_done_r, //[3]
- gen_phystatus_r, //[2]
- guard_r, //[1]
- rate_change_i}; //[0]
-endmodule
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/v6_pcie_v1_3x8.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/v6_pcie_v1_3x8.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/v6_pcie_v1_3x8.v (nonexistent)
@@ -1,1191 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : v6_pcie_v1_3x8.v
-//--
-//-- Description: Virtex6 solution wrapper : Endpoint for PCI Express
-//--
-//--
-//--
-//--------------------------------------------------------------------------------
-
-`timescale 1ns/1ns
-
-module v6_pcie_v1_3x8 # (
- parameter ALLOW_X8_GEN2 = "FALSE",
- parameter BAR0 = 32'hFFFF0000,
- parameter BAR1 = 32'hFFF00000,
- parameter BAR2 = 32'hFFFFF000,
- parameter BAR3 = 32'h00000000,
- parameter BAR4 = 32'h00000000,
- parameter BAR5 = 32'h00000000,
-
- parameter CARDBUS_CIS_POINTER = 32'h00000000,
- parameter CLASS_CODE = 24'h050000,
- parameter CMD_INTX_IMPLEMENTED = "TRUE",
- parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
- parameter CPL_TIMEOUT_RANGES_SUPPORTED = 4'h2,
-
- parameter DEV_CAP_ENDPOINT_L0S_LATENCY = 7,
- parameter DEV_CAP_ENDPOINT_L1_LATENCY = 7,
- parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE",
- parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
- parameter DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
- parameter DEVICE_ID = 16'h0153,
-
- parameter DISABLE_LANE_REVERSAL = "TRUE",
- parameter DISABLE_SCRAMBLING = "FALSE",
- parameter DSN_BASE_PTR = 12'h100,
- parameter DSN_CAP_NEXTPTR = 12'h000,
- parameter DSN_CAP_ON = "TRUE",
-
- parameter ENABLE_MSG_ROUTE = 11'h00000000000,
- parameter ENABLE_RX_TD_ECRC_TRIM = "TRUE",
- parameter EXPANSION_ROM = 32'h00000000,
- parameter EXT_CFG_CAP_PTR = 6'h3F,
- parameter EXT_CFG_XP_CAP_PTR = 10'h3FF,
- parameter HEADER_TYPE = 8'h00,
- parameter INTERRUPT_PIN = 8'h1,
-
- parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
- parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
- parameter LINK_CAP_MAX_LINK_SPEED = 4'h1,
- parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08,
- parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
-
- parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
- parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
- parameter LINK_CTRL2_TARGET_LINK_SPEED = 4'h0,
- parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE",
-
- parameter LL_ACK_TIMEOUT = 15'h0000,
- parameter LL_ACK_TIMEOUT_EN = "FALSE",
- parameter LL_ACK_TIMEOUT_FUNC = 0,
- parameter LL_REPLAY_TIMEOUT = 15'h0000,
- parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
- parameter LL_REPLAY_TIMEOUT_FUNC = 0,
-
- parameter LTSSM_MAX_LINK_WIDTH = LINK_CAP_MAX_LINK_WIDTH,
- parameter MSI_CAP_MULTIMSGCAP = 0,
- parameter MSI_CAP_MULTIMSG_EXTENSION = 0,
- parameter MSI_CAP_ON = "TRUE",
- parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE",
- parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
-
- parameter MSIX_CAP_ON = "FALSE",
- parameter MSIX_CAP_PBA_BIR = 0,
- parameter MSIX_CAP_PBA_OFFSET = 29'h0,
- parameter MSIX_CAP_TABLE_BIR = 0,
- parameter MSIX_CAP_TABLE_OFFSET = 29'h0,
- parameter MSIX_CAP_TABLE_SIZE = 11'h000,
-
- parameter PCIE_CAP_DEVICE_PORT_TYPE = 4'b0000,
- parameter PCIE_CAP_INT_MSG_NUM = 5'h1,
- parameter PCIE_CAP_NEXTPTR = 8'h00,
- parameter PCIE_DRP_ENABLE = "FALSE",
- parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
-
- parameter PM_CAP_DSI = "FALSE",
- parameter PM_CAP_D1SUPPORT = "FALSE",
- parameter PM_CAP_D2SUPPORT = "FALSE",
- parameter PM_CAP_NEXTPTR = 8'h48,
- parameter PM_CAP_PMESUPPORT = 5'h0F,
- parameter PM_CSR_NOSOFTRST = "TRUE",
-
- parameter PM_DATA_SCALE0 = 2'h0,
- parameter PM_DATA_SCALE1 = 2'h0,
- parameter PM_DATA_SCALE2 = 2'h0,
- parameter PM_DATA_SCALE3 = 2'h0,
- parameter PM_DATA_SCALE4 = 2'h0,
- parameter PM_DATA_SCALE5 = 2'h0,
- parameter PM_DATA_SCALE6 = 2'h0,
- parameter PM_DATA_SCALE7 = 2'h0,
-
- parameter PM_DATA0 = 8'h00,
- parameter PM_DATA1 = 8'h00,
- parameter PM_DATA2 = 8'h00,
- parameter PM_DATA3 = 8'h00,
- parameter PM_DATA4 = 8'h00,
- parameter PM_DATA5 = 8'h00,
- parameter PM_DATA6 = 8'h00,
- parameter PM_DATA7 = 8'h00,
-
- parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
- parameter REVISION_ID = 8'h06,
- parameter SUBSYSTEM_ID = 16'hABB3,
- parameter SUBSYSTEM_VENDOR_ID = 16'h0084,
-
- parameter TL_RX_RAM_RADDR_LATENCY = 0,
- parameter TL_RX_RAM_RDATA_LATENCY = 2,
- parameter TL_RX_RAM_WRITE_LATENCY = 0,
- parameter TL_TX_RAM_RADDR_LATENCY = 0,
- parameter TL_TX_RAM_RDATA_LATENCY = 2,
- parameter TL_TX_RAM_WRITE_LATENCY = 0,
-
- parameter UPCONFIG_CAPABLE = "TRUE",
- parameter USER_CLK_FREQ = 3,
- parameter VC_BASE_PTR = 12'h0,
- parameter VC_CAP_NEXTPTR = 12'h000,
- parameter VC_CAP_ON = "FALSE",
- parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
-
- parameter VC0_CPL_INFINITE = "TRUE",
- parameter VC0_RX_RAM_LIMIT = 13'h7FF,
- parameter VC0_TOTAL_CREDITS_CD = 308,
- parameter VC0_TOTAL_CREDITS_CH = 36,
- parameter VC0_TOTAL_CREDITS_NPH = 12,
- parameter VC0_TOTAL_CREDITS_PD = 308,
- parameter VC0_TOTAL_CREDITS_PH = 32,
- parameter VC0_TX_LASTPACKET = 29,
-
- parameter VENDOR_ID = 16'h10DC,
- parameter VSEC_BASE_PTR = 12'h0,
- parameter VSEC_CAP_NEXTPTR = 12'h000,
- parameter VSEC_CAP_ON = "FALSE",
-
- parameter AER_BASE_PTR = 12'h128,
- parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
- parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
- parameter AER_CAP_ID = 16'h0001,
- parameter AER_CAP_INT_MSG_NUM_MSI = 5'h0a,
- parameter AER_CAP_INT_MSG_NUM_MSIX = 5'h15,
- parameter AER_CAP_NEXTPTR = 12'h160,
- parameter AER_CAP_ON = "FALSE",
- parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
- parameter AER_CAP_VERSION = 4'h1,
-
- parameter CAPABILITIES_PTR = 8'h40,
- parameter CRM_MODULE_RSTS = 7'h00,
- parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
- parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
- parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
- parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
- parameter DEV_CAP_RSVD_14_12 = 0,
- parameter DEV_CAP_RSVD_17_16 = 0,
- parameter DEV_CAP_RSVD_31_29 = 0,
- parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
-
- parameter DISABLE_ASPM_L1_TIMER = "FALSE",
- parameter DISABLE_BAR_FILTERING = "FALSE",
- parameter DISABLE_ID_CHECK = "FALSE",
- parameter DISABLE_RX_TC_FILTER = "FALSE",
- parameter DNSTREAM_LINK_NUM = 8'h00,
-
- parameter DSN_CAP_ID = 16'h0003,
- parameter DSN_CAP_VERSION = 4'h1,
- parameter ENTER_RVRY_EI_L0 = "TRUE",
- parameter INFER_EI = 5'h0c,
- parameter IS_SWITCH = "FALSE",
-
- parameter LAST_CONFIG_DWORD = 10'h3FF,
- parameter LINK_CAP_ASPM_SUPPORT = 1,
- parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
- parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
- parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
- parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
- parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
- parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
- parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
- parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
- parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
- parameter LINK_CAP_RSVD_23_22 = 0,
- parameter LINK_CONTROL_RCB = 0,
-
- parameter MSI_BASE_PTR = 8'h48,
- parameter MSI_CAP_ID = 8'h05,
- parameter MSI_CAP_NEXTPTR = 8'h60,
- parameter MSIX_BASE_PTR = 8'h9c,
- parameter MSIX_CAP_ID = 8'h11,
- parameter MSIX_CAP_NEXTPTR = 8'h00,
- parameter N_FTS_COMCLK_GEN1 = 255,
- parameter N_FTS_COMCLK_GEN2 = 254,
- parameter N_FTS_GEN1 = 255,
- parameter N_FTS_GEN2 = 255,
-
- parameter PCIE_BASE_PTR = 8'h60,
- parameter PCIE_CAP_CAPABILITY_ID = 8'h10,
- parameter PCIE_CAP_CAPABILITY_VERSION = 4'h2,
- parameter PCIE_CAP_ON = "TRUE",
- parameter PCIE_CAP_RSVD_15_14 = 0,
- parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
- parameter PCIE_REVISION = 2,
- parameter PGL0_LANE = 0,
- parameter PGL1_LANE = 1,
- parameter PGL2_LANE = 2,
- parameter PGL3_LANE = 3,
- parameter PGL4_LANE = 4,
- parameter PGL5_LANE = 5,
- parameter PGL6_LANE = 6,
- parameter PGL7_LANE = 7,
- parameter PL_AUTO_CONFIG = 0,
- parameter PL_FAST_TRAIN = "FALSE",
-
- parameter PM_BASE_PTR = 8'h40,
- parameter PM_CAP_AUXCURRENT = 0,
- parameter PM_CAP_ID = 8'h01,
- parameter PM_CAP_ON = "TRUE",
- parameter PM_CAP_PME_CLOCK = "FALSE",
- parameter PM_CAP_RSVD_04 = 0,
- parameter PM_CAP_VERSION = 3,
- parameter PM_CSR_BPCCEN = "FALSE",
- parameter PM_CSR_B2B3 = "FALSE",
-
- parameter RECRC_CHK = 0,
- parameter RECRC_CHK_TRIM = "FALSE",
- parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
- parameter SELECT_DLL_IF = "FALSE",
- parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
- parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
- parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
- parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
- parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
- parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
- parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
- parameter SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
- parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
- parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
- parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
- parameter SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
- parameter SPARE_BIT0 = 0,
- parameter SPARE_BIT1 = 0,
- parameter SPARE_BIT2 = 0,
- parameter SPARE_BIT3 = 0,
- parameter SPARE_BIT4 = 0,
- parameter SPARE_BIT5 = 0,
- parameter SPARE_BIT6 = 0,
- parameter SPARE_BIT7 = 0,
- parameter SPARE_BIT8 = 0,
- parameter SPARE_BYTE0 = 8'h00,
- parameter SPARE_BYTE1 = 8'h00,
- parameter SPARE_BYTE2 = 8'h00,
- parameter SPARE_BYTE3 = 8'h00,
- parameter SPARE_WORD0 = 32'h00000000,
- parameter SPARE_WORD1 = 32'h00000000,
- parameter SPARE_WORD2 = 32'h00000000,
- parameter SPARE_WORD3 = 32'h00000000,
-
- parameter TL_RBYPASS = "FALSE",
- parameter TL_TFC_DISABLE = "FALSE",
- parameter TL_TX_CHECKS_DISABLE = "FALSE",
- parameter EXIT_LOOPBACK_ON_EI = "TRUE",
- parameter UPSTREAM_FACING = "TRUE",
- parameter UR_INV_REQ = "TRUE",
-
- parameter VC_CAP_ID = 16'h0002,
- parameter VC_CAP_VERSION = 4'h1,
- parameter VSEC_CAP_HDR_ID = 16'h1234,
- parameter VSEC_CAP_HDR_LENGTH = 12'h018,
- parameter VSEC_CAP_HDR_REVISION = 4'h1,
- parameter VSEC_CAP_ID = 16'h000b,
- parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
- parameter VSEC_CAP_VERSION = 4'h1
-)
-(
- //-------------------------------------------------------
- // 1. PCI Express (pci_exp) Interface
- //-------------------------------------------------------
-
- // Tx
- output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txp,
- output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txn,
-
- // Rx
- input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxp,
- input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxn,
-
- //-------------------------------------------------------
- // 2. Transaction (TRN) Interface
- //-------------------------------------------------------
-
- // Common
- output trn_clk,
- output trn_reset_n,
- output trn_lnk_up_n,
-
- // Tx
- output [5:0] trn_tbuf_av,
- output trn_tcfg_req_n,
- output trn_terr_drop_n,
- output trn_tdst_rdy_n,
- input [63:0] trn_td,
- input trn_trem_n,
- input trn_tsof_n,
- input trn_teof_n,
- input trn_tsrc_rdy_n,
- input trn_tsrc_dsc_n,
- input trn_terrfwd_n,
- input trn_tcfg_gnt_n,
- input trn_tstr_n,
-
- // Rx
- output [63:0] trn_rd,
- output trn_rrem_n,
- output trn_rsof_n,
- output trn_reof_n,
- output trn_rsrc_rdy_n,
- output trn_rsrc_dsc_n,
- output trn_rerrfwd_n,
- output [6:0] trn_rbar_hit_n,
- input trn_rdst_rdy_n,
- input trn_rnp_ok_n,
-
- // Flow Control
- output [11:0] trn_fc_cpld,
- output [7:0] trn_fc_cplh,
- output [11:0] trn_fc_npd,
- output [7:0] trn_fc_nph,
- output [11:0] trn_fc_pd,
- output [7:0] trn_fc_ph,
- input [2:0] trn_fc_sel,
-
-
- //-------------------------------------------------------
- // 3. Configuration (CFG) Interface
- //-------------------------------------------------------
-
- output [31:0] cfg_do,
- output cfg_rd_wr_done_n,
- input [31:0] cfg_di,
- input [3:0] cfg_byte_en_n,
- input [9:0] cfg_dwaddr,
- input cfg_wr_en_n,
- input cfg_rd_en_n,
-
- input cfg_err_cor_n,
- input cfg_err_ur_n,
- input cfg_err_ecrc_n,
- input cfg_err_cpl_timeout_n,
- input cfg_err_cpl_abort_n,
- input cfg_err_cpl_unexpect_n,
- input cfg_err_posted_n,
- input cfg_err_locked_n,
- input [47:0] cfg_err_tlp_cpl_header,
- output cfg_err_cpl_rdy_n,
- input cfg_interrupt_n,
- output cfg_interrupt_rdy_n,
- input cfg_interrupt_assert_n,
- input [7:0] cfg_interrupt_di,
- output [7:0] cfg_interrupt_do,
- output [2:0] cfg_interrupt_mmenable,
- output cfg_interrupt_msienable,
- output cfg_interrupt_msixenable,
- output cfg_interrupt_msixfm,
- input cfg_turnoff_ok_n,
- output cfg_to_turnoff_n,
- input cfg_trn_pending_n,
- input cfg_pm_wake_n,
- output [7:0] cfg_bus_number,
- output [4:0] cfg_device_number,
- output [2:0] cfg_function_number,
- output [15:0] cfg_status,
- output [15:0] cfg_command,
- output [15:0] cfg_dstatus,
- output [15:0] cfg_dcommand,
- output [15:0] cfg_lstatus,
- output [15:0] cfg_lcommand,
- output [15:0] cfg_dcommand2,
- output [2:0] cfg_pcie_link_state_n,
- input [63:0] cfg_dsn,
- output cfg_pmcsr_pme_en,
- output cfg_pmcsr_pme_status,
- output [1:0] cfg_pmcsr_powerstate,
- output lnk_clk_en,
-
- //-------------------------------------------------------
- // 4. Physical Layer Control and Status (PL) Interface
- //-------------------------------------------------------
-
- output [2:0] pl_initial_link_width,
- output [1:0] pl_lane_reversal_mode,
- output pl_link_gen2_capable,
- output pl_link_partner_gen2_supported,
- output pl_link_upcfg_capable,
- output [5:0] pl_ltssm_state,
- output pl_received_hot_rst,
- output pl_sel_link_rate,
- output [1:0] pl_sel_link_width,
- input pl_directed_link_auton,
- input [1:0] pl_directed_link_change,
- input pl_directed_link_speed,
- input [1:0] pl_directed_link_width,
- input pl_upstream_prefer_deemph,
-
- //-------------------------------------------------------
- // 5. System (SYS) Interface
- //-------------------------------------------------------
-
- input sys_clk,
- input sys_reset_n
-
-
-);
-
-
- wire rx_func_level_reset_n;
- wire cfg_msg_received;
- wire cfg_msg_received_pme_to;
-
- wire cfg_cmd_bme;
- wire cfg_cmd_intdis;
- wire cfg_cmd_io_en;
- wire cfg_cmd_mem_en;
- wire cfg_cmd_serr_en;
- wire cfg_dev_control_aux_power_en ;
- wire cfg_dev_control_corr_err_reporting_en ;
- wire cfg_dev_control_enable_relaxed_order ;
- wire cfg_dev_control_ext_tag_en ;
- wire cfg_dev_control_fatal_err_reporting_en ;
- wire [2:0] cfg_dev_control_maxpayload ;
- wire [2:0] cfg_dev_control_max_read_req ;
- wire cfg_dev_control_non_fatal_reporting_en ;
- wire cfg_dev_control_nosnoop_en ;
- wire cfg_dev_control_phantom_en ;
- wire cfg_dev_control_ur_err_reporting_en ;
- wire cfg_dev_control2_cpltimeout_dis ;
- wire [3:0] cfg_dev_control2_cpltimeout_val ;
- wire cfg_dev_status_corr_err_detected ;
- wire cfg_dev_status_fatal_err_detected ;
- wire cfg_dev_status_nonfatal_err_detected ;
- wire cfg_dev_status_ur_detected ;
- wire cfg_link_control_auto_bandwidth_int_en ;
- wire cfg_link_control_bandwidth_int_en ;
- wire cfg_link_control_hw_auto_width_dis ;
- wire cfg_link_control_clock_pm_en ;
- wire cfg_link_control_extended_sync ;
- wire cfg_link_control_common_clock ;
- wire cfg_link_control_retrain_link ;
- wire cfg_link_control_linkdisable ;
- wire cfg_link_control_rcb ;
- wire [1:0] cfg_link_control_aspm_control ;
- wire cfg_link_status_autobandwidth_status ;
- wire cfg_link_status_bandwidth_status ;
- wire cfg_link_status_dll_active ;
- wire cfg_link_status_link_training ;
- wire [3:0] cfg_link_status_negotiated_link_width ;
- wire [1:0] cfg_link_status_current_speed ;
- wire [15:0] cfg_msg_data;
-
- wire sys_reset_n_d;
- wire phy_rdy_n;
-
- wire trn_lnk_up_n_int;
- wire trn_lnk_up_n_int1;
-
- wire trn_reset_n_int;
- wire trn_reset_n_int1;
-
- reg [7:0] cfg_bus_number_d;
- reg [4:0] cfg_device_number_d;
- reg [2:0] cfg_function_number_d;
-
- // assigns to outputs
-
- assign cfg_to_turnoff_n = ~cfg_msg_received_pme_to;
-
- assign cfg_status = {16'b0};
-
- assign cfg_command = {5'b0,
- cfg_cmd_intdis,
- 1'b0,
- cfg_cmd_serr_en,
- 5'b0,
- cfg_cmd_bme,
- cfg_cmd_mem_en,
- cfg_cmd_io_en};
-
- assign cfg_dstatus = {10'h0,
- ~cfg_trn_pending_n,
- 1'b0,
- cfg_dev_status_ur_detected,
- cfg_dev_status_fatal_err_detected,
- cfg_dev_status_nonfatal_err_detected,
- cfg_dev_status_corr_err_detected};
-
- assign cfg_dcommand = {1'b0,
- cfg_dev_control_max_read_req,
- cfg_dev_control_nosnoop_en,
- cfg_dev_control_aux_power_en,
- cfg_dev_control_phantom_en,
- cfg_dev_control_ext_tag_en,
- cfg_dev_control_maxpayload,
- cfg_dev_control_enable_relaxed_order,
- cfg_dev_control_ur_err_reporting_en,
- cfg_dev_control_fatal_err_reporting_en,
- cfg_dev_control_non_fatal_reporting_en,
- cfg_dev_control_corr_err_reporting_en };
-
- assign cfg_lstatus = {cfg_link_status_autobandwidth_status,
- cfg_link_status_bandwidth_status,
- cfg_link_status_dll_active,
- (LINK_STATUS_SLOT_CLOCK_CONFIG == "TRUE") ? 1'b1 : 1'b0,
- cfg_link_status_link_training,
- 1'b0,
- {2'b00, cfg_link_status_negotiated_link_width},
- {2'b00, cfg_link_status_current_speed} };
-
- assign cfg_lcommand = {cfg_link_control_auto_bandwidth_int_en,
- cfg_link_control_bandwidth_int_en,
- cfg_link_control_hw_auto_width_dis,
- cfg_link_control_clock_pm_en,
- cfg_link_control_extended_sync,
- cfg_link_control_common_clock,
- cfg_link_control_retrain_link,
- cfg_link_control_linkdisable,
- cfg_link_control_rcb,
- 1'b0,
- cfg_link_control_aspm_control};
-
- assign cfg_bus_number = cfg_bus_number_d;
-
- assign cfg_device_number = cfg_device_number_d;
-
- assign cfg_function_number = cfg_function_number_d;
-
- assign cfg_dcommand2 = {11'b0,
- cfg_dev_control2_cpltimeout_dis,
- cfg_dev_control2_cpltimeout_val};
-
- // Capture Bus/Device/Function number
-
- always @(posedge trn_clk) begin
- if (trn_lnk_up_n) cfg_bus_number_d <= 8'b0;
- else if (~cfg_msg_received) cfg_bus_number_d <= cfg_msg_data[15:8];
- end
-
- always @(posedge trn_clk) begin
- if (trn_lnk_up_n) cfg_device_number_d <= 5'b0;
- else if (~cfg_msg_received) cfg_device_number_d <= cfg_msg_data[7:3];
- end
-
- always @(posedge trn_clk) begin
- if (trn_lnk_up_n) cfg_function_number_d <= 3'b0;
- else if (~cfg_msg_received) cfg_function_number_d <= cfg_msg_data[2:0];
- end
-
- // Generate trn_lnk_up_n
-
-FDCP #(
-
- .INIT(1'b1)
-
-) trn_lnk_up_n_i (
-
- .Q (trn_lnk_up_n),
- .D (trn_lnk_up_n_int1),
- .C (trn_clk),
- .CLR (1'b0),
- .PRE (1'b0)
-
-);
-
-FDCP #(
-
- .INIT(1'b1)
-
-) trn_lnk_up_n_int_i (
-
- .Q (trn_lnk_up_n_int1),
- .D (trn_lnk_up_n_int),
- .C (trn_clk),
- .CLR (1'b0),
- .PRE (1'b0)
-
-);
-
- // Generate trn_reset_n
-
-FDCP #(
-
- .INIT(1'b0)
-
-) trn_reset_n_i (
-
- .Q (trn_reset_n),
- .D (trn_reset_n_int1 & ~phy_rdy_n),
- .C (trn_clk),
- .CLR (~sys_reset_n_d),
- .PRE (1'b0)
-
-);
-
-FDCP #(
-
- .INIT(1'b0)
-
-) trn_reset_n_int_i (
-
- .Q (trn_reset_n_int1 ),
- .D (trn_reset_n_int & ~phy_rdy_n),
- .C (trn_clk),
- .CLR (~sys_reset_n_d),
- .PRE (1'b0)
-
-);
-
-
-
-//-------------------------------------------------------
-// PCI Express Reset Delay Module
-//-------------------------------------------------------
-
-pcie_reset_delay_v6 #(
-
- .PL_FAST_TRAIN ( PL_FAST_TRAIN ),
- .REF_CLK_FREQ ( REF_CLK_FREQ )
-
-)
-pcie_reset_delay_i (
-
- .ref_clk ( sys_clk_bufg ),
- .sys_reset_n ( sys_reset_n ),
- .delayed_sys_reset_n ( sys_reset_n_d )
-
-);
-
-//-------------------------------------------------------
-// PCI Express Clocking Module
-//-------------------------------------------------------
-
-pcie_clocking_v6 #(
-
- .CAP_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH),
- .CAP_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
- .REF_CLK_FREQ(REF_CLK_FREQ),
- .USER_CLK_FREQ(USER_CLK_FREQ)
-
-)
-pcie_clocking_i (
-
- .sys_clk ( sys_clk ),
- .gt_pll_lock ( gt_pll_lock ),
- .sel_lnk_rate ( pl_sel_link_rate ),
- .sel_lnk_width ( pl_sel_link_width ),
-
- .sys_clk_bufg ( sys_clk_bufg ),
- .pipe_clk ( pipe_clk ),
- .user_clk ( user_clk ),
- .block_clk ( block_clk ),
- .clock_locked ( clock_locked )
-
-);
-
-//-------------------------------------------------------
-// Virtex6 PCI Express Block Module
-//-------------------------------------------------------
-
-pcie_2_0_v6 #(
-
- .REF_CLK_FREQ ( REF_CLK_FREQ ),
- .PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ),
- .AER_BASE_PTR ( AER_BASE_PTR ),
- .AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
- .AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
- .AER_CAP_ID ( AER_CAP_ID ),
- .AER_CAP_INT_MSG_NUM_MSI ( AER_CAP_INT_MSG_NUM_MSI ),
- .AER_CAP_INT_MSG_NUM_MSIX ( AER_CAP_INT_MSG_NUM_MSIX ),
- .AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
- .AER_CAP_ON ( AER_CAP_ON ),
- .AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
- .AER_CAP_VERSION ( AER_CAP_VERSION ),
- .ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
- .BAR0 ( BAR0 ),
- .BAR1 ( BAR1 ),
- .BAR2 ( BAR2 ),
- .BAR3 ( BAR3 ),
- .BAR4 ( BAR4 ),
- .BAR5 ( BAR5 ),
- .CAPABILITIES_PTR ( CAPABILITIES_PTR ),
- .CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
- .CLASS_CODE ( CLASS_CODE ),
- .CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
- .CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
- .CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
- .CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
- .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
- .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
- .DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
- .DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
- .DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
- .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
- .DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
- .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
- .DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
- .DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
- .DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
- .DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
- .DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
- .DEVICE_ID ( DEVICE_ID ),
- .DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
- .DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
- .DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
- .DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
- .DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
- .DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
- .DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
- .DSN_BASE_PTR ( DSN_BASE_PTR ),
- .DSN_CAP_ID ( DSN_CAP_ID ),
- .DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
- .DSN_CAP_ON ( DSN_CAP_ON ),
- .DSN_CAP_VERSION ( DSN_CAP_VERSION ),
- .ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
- .ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
- .ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
- .EXPANSION_ROM ( EXPANSION_ROM ),
- .EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
- .EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
- .HEADER_TYPE ( HEADER_TYPE ),
- .INFER_EI ( INFER_EI ),
- .INTERRUPT_PIN ( INTERRUPT_PIN ),
- .IS_SWITCH ( IS_SWITCH ),
- .LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
- .LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
- .LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
- .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
- .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
- .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
- .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
- .LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
- .LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
- .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
- .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
- .LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
- .LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
- .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
- .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
- .LINK_CAP_RSVD_23_22 ( LINK_CAP_RSVD_23_22 ),
- .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
- .LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
- .LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
- .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
- .LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
- .LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
- .LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
- .LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
- .LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
- .LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
- .LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
- .LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
- .LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
- .MSI_BASE_PTR ( MSI_BASE_PTR ),
- .MSI_CAP_ID ( MSI_CAP_ID ),
- .MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
- .MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
- .MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
- .MSI_CAP_ON ( MSI_CAP_ON ),
- .MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
- .MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
- .MSIX_BASE_PTR ( MSIX_BASE_PTR ),
- .MSIX_CAP_ID ( MSIX_CAP_ID ),
- .MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
- .MSIX_CAP_ON ( MSIX_CAP_ON ),
- .MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
- .MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
- .MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
- .MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
- .MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
- .N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
- .N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
- .N_FTS_GEN1 ( N_FTS_GEN1 ),
- .N_FTS_GEN2 ( N_FTS_GEN2 ),
- .PCIE_BASE_PTR ( PCIE_BASE_PTR ),
- .PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
- .PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
- .PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
- .PCIE_CAP_INT_MSG_NUM ( PCIE_CAP_INT_MSG_NUM ),
- .PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
- .PCIE_CAP_ON ( PCIE_CAP_ON ),
- .PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
- .PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
- .PCIE_REVISION ( PCIE_REVISION ),
- .PGL0_LANE ( PGL0_LANE ),
- .PGL1_LANE ( PGL1_LANE ),
- .PGL2_LANE ( PGL2_LANE ),
- .PGL3_LANE ( PGL3_LANE ),
- .PGL4_LANE ( PGL4_LANE ),
- .PGL5_LANE ( PGL5_LANE ),
- .PGL6_LANE ( PGL6_LANE ),
- .PGL7_LANE ( PGL7_LANE ),
- .PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
- .PL_FAST_TRAIN ( PL_FAST_TRAIN ),
- .PM_BASE_PTR ( PM_BASE_PTR ),
- .PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
- .PM_CAP_DSI ( PM_CAP_DSI ),
- .PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
- .PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
- .PM_CAP_ID ( PM_CAP_ID ),
- .PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
- .PM_CAP_ON ( PM_CAP_ON ),
- .PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
- .PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
- .PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
- .PM_CAP_VERSION ( PM_CAP_VERSION ),
- .PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
- .PM_CSR_B2B3 ( PM_CSR_B2B3 ),
- .PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
- .PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
- .PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
- .PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
- .PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
- .PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
- .PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
- .PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
- .PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
- .PM_DATA0 ( PM_DATA0 ),
- .PM_DATA1 ( PM_DATA1 ),
- .PM_DATA2 ( PM_DATA2 ),
- .PM_DATA3 ( PM_DATA3 ),
- .PM_DATA4 ( PM_DATA4 ),
- .PM_DATA5 ( PM_DATA5 ),
- .PM_DATA6 ( PM_DATA6 ),
- .PM_DATA7 ( PM_DATA7 ),
- .RECRC_CHK ( RECRC_CHK ),
- .RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
- .REVISION_ID ( REVISION_ID ),
- .ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
- .SELECT_DLL_IF ( SELECT_DLL_IF ),
- .SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
- .SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
- .SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
- .SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
- .SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
- .SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
- .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
- .SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
- .SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
- .SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
- .SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
- .SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
- .SPARE_BIT0 ( SPARE_BIT0 ),
- .SPARE_BIT1 ( SPARE_BIT1 ),
- .SPARE_BIT2 ( SPARE_BIT2 ),
- .SPARE_BIT3 ( SPARE_BIT3 ),
- .SPARE_BIT4 ( SPARE_BIT4 ),
- .SPARE_BIT5 ( SPARE_BIT5 ),
- .SPARE_BIT6 ( SPARE_BIT6 ),
- .SPARE_BIT7 ( SPARE_BIT7 ),
- .SPARE_BIT8 ( SPARE_BIT8 ),
- .SPARE_BYTE0 ( SPARE_BYTE0 ),
- .SPARE_BYTE1 ( SPARE_BYTE1 ),
- .SPARE_BYTE2 ( SPARE_BYTE2 ),
- .SPARE_BYTE3 ( SPARE_BYTE3 ),
- .SPARE_WORD0 ( SPARE_WORD0 ),
- .SPARE_WORD1 ( SPARE_WORD1 ),
- .SPARE_WORD2 ( SPARE_WORD2 ),
- .SPARE_WORD3 ( SPARE_WORD3 ),
- .SUBSYSTEM_ID ( SUBSYSTEM_ID ),
- .SUBSYSTEM_VENDOR_ID ( SUBSYSTEM_VENDOR_ID ),
- .TL_RBYPASS ( TL_RBYPASS ),
- .TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
- .TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
- .TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
- .TL_TFC_DISABLE ( TL_TFC_DISABLE ),
- .TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
- .TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
- .TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
- .TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
- .UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
- .UPSTREAM_FACING ( UPSTREAM_FACING ),
- .EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
- .UR_INV_REQ ( UR_INV_REQ ),
- .USER_CLK_FREQ ( USER_CLK_FREQ ),
- .VC_BASE_PTR ( VC_BASE_PTR ),
- .VC_CAP_ID ( VC_CAP_ID ),
- .VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
- .VC_CAP_ON ( VC_CAP_ON ),
- .VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
- .VC_CAP_VERSION ( VC_CAP_VERSION ),
- .VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
- .VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
- .VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
- .VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
- .VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
- .VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
- .VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
- .VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
- .VENDOR_ID ( VENDOR_ID ),
- .VSEC_BASE_PTR ( VSEC_BASE_PTR ),
- .VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
- .VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
- .VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
- .VSEC_CAP_ID ( VSEC_CAP_ID ),
- .VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
- .VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
- .VSEC_CAP_ON ( VSEC_CAP_ON ),
- .VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
-
-)
-pcie_2_0_i (
-
- .PCIEXPRXN( pci_exp_rxn ),
- .PCIEXPRXP( pci_exp_rxp ),
- .PCIEXPTXN( pci_exp_txn ),
- .PCIEXPTXP( pci_exp_txp ),
-
- .SYSCLK( sys_clk ),
- .TRNLNKUPN( trn_lnk_up_n_int ),
- .TRNCLK( trn_clk ),
-
- .FUNDRSTN (sys_reset_n_d),
- .PHYRDYN( phy_rdy_n ),
-
- .LNKCLKEN ( lnk_clk_en ),
- .USERRSTN( trn_reset_n_int ),
- .RECEIVEDFUNCLVLRSTN( rx_func_level_reset_n ),
- .SYSRSTN( ~phy_rdy_n ),
- .PLRSTN( 1'b1 ),
- .DLRSTN( 1'b1 ),
- .TLRSTN( 1'b1 ),
- .FUNCLVLRSTN( 1'b1 ),
- .CMRSTN( 1'b1 ),
- .CMSTICKYRSTN( 1'b1 ),
-
- .TRNRBARHITN( trn_rbar_hit_n ),
- .TRNRD( trn_rd ),
- .TRNRECRCERRN( ),
- .TRNREOFN( trn_reof_n ),
- .TRNRERRFWDN( trn_rerrfwd_n ),
- .TRNRREMN( trn_rrem_n ),
- .TRNRSOFN( trn_rsof_n ),
- .TRNRSRCDSCN( trn_rsrc_dsc_n ),
- .TRNRSRCRDYN( trn_rsrc_rdy_n ),
- .TRNRDSTRDYN( trn_rdst_rdy_n ),
- .TRNRNPOKN( trn_rnp_ok_n ),
-
- .TRNTBUFAV( trn_tbuf_av ),
- .TRNTCFGREQN( trn_tcfg_req_n ),
- .TRNTDLLPDSTRDYN( ),
- .TRNTDSTRDYN( trn_tdst_rdy_n ),
- .TRNTERRDROPN( trn_terr_drop_n ),
- .TRNTCFGGNTN( trn_tcfg_gnt_n ),
- .TRNTD( trn_td ),
- .TRNTDLLPDATA( 32'b0 ),
- .TRNTDLLPSRCRDYN( 1'b1 ),
- .TRNTECRCGENN( 1'b1 ),
- .TRNTEOFN( trn_teof_n ),
- .TRNTERRFWDN( trn_terrfwd_n ),
- .TRNTREMN( trn_trem_n ),
- .TRNTSOFN( trn_tsof_n ),
- .TRNTSRCDSCN( trn_tsrc_dsc_n ),
- .TRNTSRCRDYN( trn_tsrc_rdy_n ),
- .TRNTSTRN( trn_tstr_n ),
-
- .TRNFCCPLD( trn_fc_cpld ),
- .TRNFCCPLH( trn_fc_cplh ),
- .TRNFCNPD( trn_fc_npd ),
- .TRNFCNPH( trn_fc_nph ),
- .TRNFCPD( trn_fc_pd ),
- .TRNFCPH( trn_fc_ph ),
- .TRNFCSEL( trn_fc_sel ),
-
- .CFGAERECRCCHECKEN(),
- .CFGAERECRCGENEN(),
- .CFGCOMMANDBUSMASTERENABLE( cfg_cmd_bme ),
- .CFGCOMMANDINTERRUPTDISABLE( cfg_cmd_intdis ),
- .CFGCOMMANDIOENABLE( cfg_cmd_io_en ),
- .CFGCOMMANDMEMENABLE( cfg_cmd_mem_en ),
- .CFGCOMMANDSERREN( cfg_cmd_serr_en ),
- .CFGDEVCONTROLAUXPOWEREN( cfg_dev_control_aux_power_en ),
- .CFGDEVCONTROLCORRERRREPORTINGEN( cfg_dev_control_corr_err_reporting_en ),
- .CFGDEVCONTROLENABLERO( cfg_dev_control_enable_relaxed_order ),
- .CFGDEVCONTROLEXTTAGEN( cfg_dev_control_ext_tag_en ),
- .CFGDEVCONTROLFATALERRREPORTINGEN( cfg_dev_control_fatal_err_reporting_en ),
- .CFGDEVCONTROLMAXPAYLOAD( cfg_dev_control_maxpayload ),
- .CFGDEVCONTROLMAXREADREQ( cfg_dev_control_max_read_req ),
- .CFGDEVCONTROLNONFATALREPORTINGEN( cfg_dev_control_non_fatal_reporting_en ),
- .CFGDEVCONTROLNOSNOOPEN( cfg_dev_control_nosnoop_en ),
- .CFGDEVCONTROLPHANTOMEN( cfg_dev_control_phantom_en ),
- .CFGDEVCONTROLURERRREPORTINGEN( cfg_dev_control_ur_err_reporting_en ),
- .CFGDEVCONTROL2CPLTIMEOUTDIS( cfg_dev_control2_cpltimeout_dis ),
- .CFGDEVCONTROL2CPLTIMEOUTVAL( cfg_dev_control2_cpltimeout_val ),
- .CFGDEVSTATUSCORRERRDETECTED( cfg_dev_status_corr_err_detected ),
- .CFGDEVSTATUSFATALERRDETECTED( cfg_dev_status_fatal_err_detected ),
- .CFGDEVSTATUSNONFATALERRDETECTED( cfg_dev_status_nonfatal_err_detected ),
- .CFGDEVSTATUSURDETECTED( cfg_dev_status_ur_detected ),
- .CFGDO( cfg_do ),
- .CFGERRAERHEADERLOGSETN(),
- .CFGERRCPLRDYN( cfg_err_cpl_rdy_n ),
- .CFGINTERRUPTDO( cfg_interrupt_do ),
- .CFGINTERRUPTMMENABLE( cfg_interrupt_mmenable ),
- .CFGINTERRUPTMSIENABLE( cfg_interrupt_msienable ),
- .CFGINTERRUPTMSIXENABLE( cfg_interrupt_msixenable ),
- .CFGINTERRUPTMSIXFM( cfg_interrupt_msixfm ),
- .CFGINTERRUPTRDYN( cfg_interrupt_rdy_n ),
- .CFGLINKCONTROLRCB( cfg_link_control_rcb ),
- .CFGLINKCONTROLASPMCONTROL( cfg_link_control_aspm_control ),
- .CFGLINKCONTROLAUTOBANDWIDTHINTEN( cfg_link_control_auto_bandwidth_int_en ),
- .CFGLINKCONTROLBANDWIDTHINTEN( cfg_link_control_bandwidth_int_en ),
- .CFGLINKCONTROLCLOCKPMEN( cfg_link_control_clock_pm_en ),
- .CFGLINKCONTROLCOMMONCLOCK( cfg_link_control_common_clock ),
- .CFGLINKCONTROLEXTENDEDSYNC( cfg_link_control_extended_sync ),
- .CFGLINKCONTROLHWAUTOWIDTHDIS( cfg_link_control_hw_auto_width_dis ),
- .CFGLINKCONTROLLINKDISABLE( cfg_link_control_linkdisable ),
- .CFGLINKCONTROLRETRAINLINK( cfg_link_control_retrain_link ),
- .CFGLINKSTATUSAUTOBANDWIDTHSTATUS( cfg_link_status_autobandwidth_status ),
- .CFGLINKSTATUSBANDWITHSTATUS( cfg_link_status_bandwidth_status ),
- .CFGLINKSTATUSCURRENTSPEED( cfg_link_status_current_speed ),
- .CFGLINKSTATUSDLLACTIVE( cfg_link_status_dll_active ),
- .CFGLINKSTATUSLINKTRAINING( cfg_link_status_link_training ),
- .CFGLINKSTATUSNEGOTIATEDWIDTH( cfg_link_status_negotiated_link_width ),
- .CFGMSGDATA( cfg_msg_data ),
- .CFGMSGRECEIVED( cfg_msg_received ),
- .CFGMSGRECEIVEDASSERTINTA(),
- .CFGMSGRECEIVEDASSERTINTB(),
- .CFGMSGRECEIVEDASSERTINTC(),
- .CFGMSGRECEIVEDASSERTINTD(),
- .CFGMSGRECEIVEDDEASSERTINTA(),
- .CFGMSGRECEIVEDDEASSERTINTB(),
- .CFGMSGRECEIVEDDEASSERTINTC(),
- .CFGMSGRECEIVEDDEASSERTINTD(),
- .CFGMSGRECEIVEDERRCOR(),
- .CFGMSGRECEIVEDERRFATAL(),
- .CFGMSGRECEIVEDERRNONFATAL(),
- .CFGMSGRECEIVEDPMASNAK(),
- .CFGMSGRECEIVEDPMETO( cfg_msg_received_pme_to ),
- .CFGMSGRECEIVEDPMETOACK(),
- .CFGMSGRECEIVEDPMPME(),
- .CFGMSGRECEIVEDSETSLOTPOWERLIMIT(),
- .CFGMSGRECEIVEDUNLOCK(),
- .CFGPCIELINKSTATE( cfg_pcie_link_state_n ),
- .CFGPMCSRPMEEN ( cfg_pmcsr_pme_en ),
- .CFGPMCSRPMESTATUS ( cfg_pmcsr_pme_status ),
- .CFGPMCSRPOWERSTATE ( cfg_pmcsr_powerstate ),
- .CFGPMRCVASREQL1N(),
- .CFGPMRCVENTERL1N(),
- .CFGPMRCVENTERL23N(),
- .CFGPMRCVREQACKN(),
- .CFGRDWRDONEN( cfg_rd_wr_done_n ),
- .CFGSLOTCONTROLELECTROMECHILCTLPULSE(),
- .CFGTRANSACTION(),
- .CFGTRANSACTIONADDR(),
- .CFGTRANSACTIONTYPE(),
- .CFGVCTCVCMAP(),
- .CFGBYTEENN( cfg_byte_en_n ),
- .CFGDI( cfg_di ),
- .CFGDSBUSNUMBER( 8'b0 ),
- .CFGDSDEVICENUMBER( 5'b0 ),
- .CFGDSFUNCTIONNUMBER( 3'b0 ),
- .CFGDSN( cfg_dsn ),
- .CFGDWADDR( cfg_dwaddr ),
- .CFGERRACSN( 1'b1 ),
- .CFGERRAERHEADERLOG( 128'h0 ),
- .CFGERRCORN( cfg_err_cor_n ),
- .CFGERRCPLABORTN( cfg_err_cpl_abort_n ),
- .CFGERRCPLTIMEOUTN( cfg_err_cpl_timeout_n ),
- .CFGERRCPLUNEXPECTN( cfg_err_cpl_unexpect_n ),
- .CFGERRECRCN( cfg_err_ecrc_n ),
- .CFGERRLOCKEDN( cfg_err_locked_n ),
- .CFGERRPOSTEDN( cfg_err_posted_n ),
- .CFGERRTLPCPLHEADER( cfg_err_tlp_cpl_header ),
- .CFGERRURN( cfg_err_ur_n ),
- .CFGINTERRUPTASSERTN( cfg_interrupt_assert_n ),
- .CFGINTERRUPTDI( cfg_interrupt_di ),
- .CFGINTERRUPTN( cfg_interrupt_n ),
- .CFGPMDIRECTASPML1N( 1'b1 ),
- .CFGPMSENDPMACKN( 1'b1 ),
- .CFGPMSENDPMETON( 1'b1 ),
- .CFGPMSENDPMNAKN( 1'b1 ),
- .CFGPMTURNOFFOKN( cfg_turnoff_ok_n ),
- .CFGPMWAKEN( cfg_pm_wake_n ),
- .CFGPORTNUMBER( 8'h0 ),
- .CFGRDENN( cfg_rd_en_n ),
- .CFGTRNPENDINGN( cfg_trn_pending_n ),
- .CFGWRENN( cfg_wr_en_n ),
- .CFGWRREADONLYN( 1'b1 ),
- .CFGWRRW1CASRWN( 1'b1 ),
-
- .PLINITIALLINKWIDTH( pl_initial_link_width ),
- .PLLANEREVERSALMODE( pl_lane_reversal_mode ),
- .PLLINKGEN2CAP( pl_link_gen2_capable ),
- .PLLINKPARTNERGEN2SUPPORTED( pl_link_partner_gen2_supported ),
- .PLLINKUPCFGCAP( pl_link_upcfg_capable ),
- .PLLTSSMSTATE( pl_ltssm_state ),
- .PLPHYLNKUPN( ), // Debug
- .PLRECEIVEDHOTRST( pl_received_hot_rst ),
- .PLRXPMSTATE(), // Debug
- .PLSELLNKRATE( pl_sel_link_rate ),
- .PLSELLNKWIDTH( pl_sel_link_width ),
- .PLTXPMSTATE(), // Debug
- .PLDIRECTEDLINKAUTON( pl_directed_link_auton ),
- .PLDIRECTEDLINKCHANGE( pl_directed_link_change ),
- .PLDIRECTEDLINKSPEED( pl_directed_link_speed ),
- .PLDIRECTEDLINKWIDTH( pl_directed_link_width ),
- .PLDOWNSTREAMDEEMPHSOURCE( 1'b0 ),
- .PLUPSTREAMPREFERDEEMPH( pl_upstream_prefer_deemph ),
- .PLTRANSMITHOTRST( 1'b0 ),
-
- .DBGSCLRA(),
- .DBGSCLRB(),
- .DBGSCLRC(),
- .DBGSCLRD(),
- .DBGSCLRE(),
- .DBGSCLRF(),
- .DBGSCLRG(),
- .DBGSCLRH(),
- .DBGSCLRI(),
- .DBGSCLRJ(),
- .DBGSCLRK(),
- .DBGVECA(),
- .DBGVECB(),
- .DBGVECC(),
- .PLDBGVEC(),
- .DBGMODE( 2'b0 ),
- .DBGSUBMODE( 1'b0 ),
- .PLDBGMODE( 3'b0 ),
-
- .DRPDO(),
- .DRPDRDY(),
- .DRPCLK(1'b0),
- .DRPDADDR(9'b0),
- .DRPDEN(1'b0),
- .DRPDI(16'b0),
- .DRPDWE(1'b0),
-
- .GTPLLLOCK( gt_pll_lock ),
- .PIPECLK( pipe_clk ),
- .USERCLK( user_clk ),
- .CLOCKLOCKED( clock_locked )
-
-
-);
-
-endmodule
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_clocking_v6.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_clocking_v6.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_clocking_v6.v (nonexistent)
@@ -1,282 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : pcie_clocking_v6.v
-//-- Description: Clocking module for Virtex6 PCIe Block
-//--
-//--
-//--
-//--------------------------------------------------------------------------------
-
-`timescale 1ns/1ns
-
-module pcie_clocking_v6 # (
-
- parameter CAP_LINK_WIDTH = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
- parameter CAP_LINK_SPEED = 4'h1, // 1 - Gen1 , 2 - Gen2
- parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
- parameter USER_CLK_FREQ = 3 // 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz
-
-)
-(
-
- input wire sys_clk,
- input wire gt_pll_lock,
- input wire sel_lnk_rate,
- input wire [1:0] sel_lnk_width,
-
- output wire sys_clk_bufg,
- output wire pipe_clk,
- output wire user_clk,
- output wire block_clk,
- output wire clock_locked
-
-);
-
-
- wire mmcm_locked;
- wire mmcm_clkfbin;
- wire mmcm_clkfbout;
- wire clk_500;
- wire clk_250;
- wire clk_125;
- wire user_clk_prebuf;
- wire sel_lnk_rate_d;
-
- assign clock_locked = mmcm_locked;
-
- // MMCM Configuration
-
-
- localparam mmcm_clockin_period = (REF_CLK_FREQ == 0) ? 10 :
- (REF_CLK_FREQ == 1) ? 8 :
- (REF_CLK_FREQ == 2) ? 4 : 0;
-
- localparam mmcm_clockfb_mult = (REF_CLK_FREQ == 0) ? 10 :
- (REF_CLK_FREQ == 1) ? 8 :
- (REF_CLK_FREQ == 2) ? 8 : 0;
-
-
- localparam mmcm_divclk_divide = (REF_CLK_FREQ == 0) ? 1 :
- (REF_CLK_FREQ == 1) ? 1 :
- (REF_CLK_FREQ == 2) ? 2 : 0;
-
- localparam mmcm_clock0_div = 4;
- localparam mmcm_clock1_div = 8;
- localparam mmcm_clock2_div = ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 0)) ? 32 :
- ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) ? 16 :
- ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 1)) ? 16 :
- ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) ? 16 : 2;
- localparam mmcm_clock3_div = 2;
- generate
-
- // PIPE Clock BUFG.
-
- if (CAP_LINK_SPEED == 4'h1) begin : GEN1_LINK
-
- BUFG pipe_clk_bufg (.O(pipe_clk),.I(clk_125));
-
- end else if (CAP_LINK_SPEED == 4'h2) begin : GEN2_LINK
-
- SRL16E #(.INIT(0)) sel_lnk_rate_delay (.Q(sel_lnk_rate_d),
- .D(sel_lnk_rate), .CLK(pipe_clk),.CE(mmcm_locked), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));
-
- BUFGMUX pipe_clk_bufgmux (.O(pipe_clk), .I0(clk_125),.I1(clk_250),.S(sel_lnk_rate_d));
-
- end else begin : ILLEGAL_LINK_SPEED
-
- //$display("Confiuration Error : CAP_LINK_SPEED = %d, must be either 1 or 2.", CAP_LINK_SPEED);
- //$finish;
-
- end
-
- // User Clock BUFG.
-
- if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 0)) begin : x1_GEN1_31_25
-
- BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));
-
- end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) begin : x1_GEN1_62_50
-
- BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));
-
- end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 2)) begin : x1_GEN1_125_00
-
- BUFG user_clk_bufg (.O(user_clk),.I(clk_125));
-
- end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x1_GEN1_250_00
-
- BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
-
- end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 1)) begin : x1_GEN2_62_50
-
- BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));
-
- end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 2)) begin : x1_GEN2_125_00
-
- BUFG user_clk_bufg (.O(user_clk),.I(clk_125));
-
- end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 3)) begin : x1_GEN2_250_00
-
- BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
-
- end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) begin : x2_GEN1_62_50
-
- BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));
-
- end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 2)) begin : x2_GEN1_125_00
-
- BUFG user_clk_bufg (.O(user_clk),.I(clk_125));
-
- end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x2_GEN1_250_00
-
- BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
-
- end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 2)) begin : x2_GEN2_125_00
-
- BUFG user_clk_bufg (.O(user_clk),.I(clk_125));
-
- end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 3)) begin : x2_GEN2_250_00
-
- BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
-
- end else if ((CAP_LINK_WIDTH == 6'h04) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 2)) begin : x4_GEN1_125_00
-
- BUFG user_clk_bufg (.O(user_clk),.I(clk_125));
-
- end else if ((CAP_LINK_WIDTH == 6'h04) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x4_GEN1_250_00
-
- BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
-
- end else if ((CAP_LINK_WIDTH == 6'h04) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 3)) begin : x4_GEN2_250_00
-
- BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
-
- end else if ((CAP_LINK_WIDTH == 6'h08) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x8_GEN1_250_00
-
- BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
-
- end else if ((CAP_LINK_WIDTH == 6'h08) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 4)) begin : x8_GEN2_250_00
-
- BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
- BUFG block_clk_bufg (.O(block_clk),.I(clk_500));
-
- end else begin : ILLEGAL_CONFIGURATION
-
- //$display("Confiuration Error : Unsupported Link Width, Link Speed and User Clock Frequency Combination");
- //$finish;
-
- end
-
- endgenerate
-
- // Feedback BUFG. Required for Temp Compensation
- BUFG clkfbin_bufg_i (.O(mmcm_clkfbin), .I(mmcm_clkfbout));
-
- // sys_clk BUFG. Required for routability from IBUFDS_GTXE1
- BUFG sys_clk_bufg_i (.O(sys_clk_bufg), .I(sys_clk));
-
- MMCM_ADV # (
-
- // 5 for 100 MHz , 4 for 125 MHz , 2 for 250 MHz
- .CLKFBOUT_MULT_F (mmcm_clockfb_mult),
- .DIVCLK_DIVIDE (mmcm_divclk_divide),
- .CLKFBOUT_PHASE(0),
-
- // 10 for 100 MHz, 4 for 250 MHz
- .CLKIN1_PERIOD (mmcm_clockin_period),
- .CLKIN2_PERIOD (mmcm_clockin_period),
-
- // 500 MHz / mmcm_clockx_div
- .CLKOUT0_DIVIDE_F (mmcm_clock0_div),
- .CLKOUT0_PHASE (0),
-
- .CLKOUT1_DIVIDE (mmcm_clock1_div),
- .CLKOUT1_PHASE (0),
-
- .CLKOUT2_DIVIDE (mmcm_clock2_div),
- .CLKOUT2_PHASE (0),
-
- .CLKOUT3_DIVIDE (mmcm_clock3_div),
- .CLKOUT3_PHASE (0)
-
- ) mmcm_adv_i (
-
- .CLKFBOUT (mmcm_clkfbout),
- .CLKOUT0 (clk_250), // 250 MHz for pipe_clk
- .CLKOUT1 (clk_125), // 125 MHz for pipe_clk
- .CLKOUT2 (user_clk_prebuf), // user clk
- .CLKOUT3 (clk_500),
- .CLKOUT4 (),
- .CLKOUT5 (),
- .CLKOUT6 (),
- .DO (),
- .DRDY (),
- .CLKFBOUTB (),
- .CLKFBSTOPPED (),
- .CLKINSTOPPED (),
- .CLKOUT0B (),
- .CLKOUT1B (),
- .CLKOUT2B (),
- .CLKOUT3B (),
- .PSDONE (),
- .LOCKED (mmcm_locked),
- .CLKFBIN (mmcm_clkfbin),
- .CLKIN1 (sys_clk),
- .CLKIN2 (1'b0),
- .CLKINSEL (1'b1),
- .DADDR (7'b0),
- .DCLK (1'b0),
- .DEN (1'b0),
- .DI (16'b0),
- .DWE (1'b0),
- .PSEN (1'b0),
- .PSINCDEC (1'b0),
- .PWRDWN (1'b0),
- .PSCLK (1'b0),
- .RST (~gt_pll_lock)
- );
-
-
-endmodule
-
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_lane_v6.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_lane_v6.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_lane_v6.v (nonexistent)
@@ -1,294 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : pcie_pipe_lane_v6.v
-//--
-//-- Description: PIPE per lane module for Virtex6 PCIe Block
-//--
-//--
-//--
-//--------------------------------------------------------------------------------
-
-`timescale 1ns/1ns
-
-module pcie_pipe_lane_v6 #
-(
- parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
-)
-(
- output wire [ 1:0] pipe_rx_char_is_k_o ,
- output wire [15:0] pipe_rx_data_o ,
- output wire pipe_rx_valid_o ,
- output wire pipe_rx_chanisaligned_o ,
- output wire [ 2:0] pipe_rx_status_o ,
- output wire pipe_rx_phy_status_o ,
- output wire pipe_rx_elec_idle_o ,
- input wire pipe_rx_polarity_i ,
- input wire pipe_tx_compliance_i ,
- input wire [ 1:0] pipe_tx_char_is_k_i ,
- input wire [15:0] pipe_tx_data_i ,
- input wire pipe_tx_elec_idle_i ,
- input wire [ 1:0] pipe_tx_powerdown_i ,
-
- input wire [ 1:0] pipe_rx_char_is_k_i ,
- input wire [15:0] pipe_rx_data_i ,
- input wire pipe_rx_valid_i ,
- input wire pipe_rx_chanisaligned_i ,
- input wire [ 2:0] pipe_rx_status_i ,
- input wire pipe_rx_phy_status_i ,
- input wire pipe_rx_elec_idle_i ,
- output wire pipe_rx_polarity_o ,
- output wire pipe_tx_compliance_o ,
- output wire [ 1:0] pipe_tx_char_is_k_o ,
- output wire [15:0] pipe_tx_data_o ,
- output wire pipe_tx_elec_idle_o ,
- output wire [ 1:0] pipe_tx_powerdown_o ,
-
- input wire pipe_clk ,
- input wire rst_n
-);
-
-//******************************************************************//
-// Reality check. //
-//******************************************************************//
-
- parameter TCQ = 1; // clock to out delay model
-
- reg [ 1:0] pipe_rx_char_is_k_q ;
- reg [15:0] pipe_rx_data_q ;
- reg pipe_rx_valid_q ;
- reg pipe_rx_chanisaligned_q ;
- reg [ 2:0] pipe_rx_status_q ;
- reg pipe_rx_phy_status_q ;
- reg pipe_rx_elec_idle_q ;
-
- reg pipe_rx_polarity_q ;
- reg pipe_tx_compliance_q ;
- reg [ 1:0] pipe_tx_char_is_k_q ;
- reg [15:0] pipe_tx_data_q ;
- reg pipe_tx_elec_idle_q ;
- reg [ 1:0] pipe_tx_powerdown_q ;
-
- reg [ 1:0] pipe_rx_char_is_k_qq ;
- reg [15:0] pipe_rx_data_qq ;
- reg pipe_rx_valid_qq ;
- reg pipe_rx_chanisaligned_qq;
- reg [ 2:0] pipe_rx_status_qq ;
- reg pipe_rx_phy_status_qq ;
- reg pipe_rx_elec_idle_qq ;
-
- reg pipe_rx_polarity_qq ;
- reg pipe_tx_compliance_qq ;
- reg [ 1:0] pipe_tx_char_is_k_qq ;
- reg [15:0] pipe_tx_data_qq ;
- reg pipe_tx_elec_idle_qq ;
- reg [ 1:0] pipe_tx_powerdown_qq ;
-
- generate
-
- if (PIPE_PIPELINE_STAGES == 0) begin
-
- assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_i;
- assign pipe_rx_data_o = pipe_rx_data_i;
- assign pipe_rx_valid_o = pipe_rx_valid_i;
- assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_i;
- assign pipe_rx_status_o = pipe_rx_status_i;
- assign pipe_rx_phy_status_o = pipe_rx_phy_status_i;
- assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_i;
-
- assign pipe_rx_polarity_o = pipe_rx_polarity_i;
- assign pipe_tx_compliance_o = pipe_tx_compliance_i;
- assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_i;
- assign pipe_tx_data_o = pipe_tx_data_i;
- assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_i;
- assign pipe_tx_powerdown_o = pipe_tx_powerdown_i;
-
- end else if (PIPE_PIPELINE_STAGES == 1) begin
-
- always @(posedge pipe_clk) begin
-
- if (rst_n) begin
-
- pipe_rx_char_is_k_q <= #TCQ 0;
- pipe_rx_data_q <= #TCQ 0;
- pipe_rx_valid_q <= #TCQ 0;
- pipe_rx_chanisaligned_q <= #TCQ 0;
- pipe_rx_status_q <= #TCQ 0;
- pipe_rx_phy_status_q <= #TCQ 0;
- pipe_rx_elec_idle_q <= #TCQ 0;
-
- pipe_rx_polarity_q <= #TCQ 0;
- pipe_tx_compliance_q <= #TCQ 0;
- pipe_tx_char_is_k_q <= #TCQ 0;
- pipe_tx_data_q <= #TCQ 0;
- pipe_tx_elec_idle_q <= #TCQ 1'b1;
- pipe_tx_powerdown_q <= #TCQ 2'b10;
-
- end else begin
-
- pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i;
- pipe_rx_data_q <= #TCQ pipe_rx_data_i;
- pipe_rx_valid_q <= #TCQ pipe_rx_valid_i;
- pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i;
- pipe_rx_status_q <= #TCQ pipe_rx_status_i;
- pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i;
- pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i;
-
- pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i;
- pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i;
- pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i;
- pipe_tx_data_q <= #TCQ pipe_tx_data_i;
- pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i;
- pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i;
-
- end
-
- end
-
- assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_q;
- assign pipe_rx_data_o = pipe_rx_data_q;
- assign pipe_rx_valid_o = pipe_rx_valid_q;
- assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_q;
- assign pipe_rx_status_o = pipe_rx_status_q;
- assign pipe_rx_phy_status_o = pipe_rx_phy_status_q;
- assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_q;
-
- assign pipe_rx_polarity_o = pipe_rx_polarity_q;
- assign pipe_tx_compliance_o = pipe_tx_compliance_q;
- assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_q;
- assign pipe_tx_data_o = pipe_tx_data_q;
- assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_q;
- assign pipe_tx_powerdown_o = pipe_tx_powerdown_q;
-
- end else if (PIPE_PIPELINE_STAGES == 2) begin
-
- always @(posedge pipe_clk) begin
-
- if (rst_n) begin
-
- pipe_rx_char_is_k_q <= #TCQ 0;
- pipe_rx_data_q <= #TCQ 0;
- pipe_rx_valid_q <= #TCQ 0;
- pipe_rx_chanisaligned_q <= #TCQ 0;
- pipe_rx_status_q <= #TCQ 0;
- pipe_rx_phy_status_q <= #TCQ 0;
- pipe_rx_elec_idle_q <= #TCQ 0;
-
- pipe_rx_polarity_q <= #TCQ 0;
- pipe_tx_compliance_q <= #TCQ 0;
- pipe_tx_char_is_k_q <= #TCQ 0;
- pipe_tx_data_q <= #TCQ 0;
- pipe_tx_elec_idle_q <= #TCQ 1'b1;
- pipe_tx_powerdown_q <= #TCQ 2'b10;
-
- pipe_rx_char_is_k_qq <= #TCQ 0;
- pipe_rx_data_qq <= #TCQ 0;
- pipe_rx_valid_qq <= #TCQ 0;
- pipe_rx_chanisaligned_qq <= #TCQ 0;
- pipe_rx_status_qq <= #TCQ 0;
- pipe_rx_phy_status_qq <= #TCQ 0;
- pipe_rx_elec_idle_qq <= #TCQ 0;
-
- pipe_rx_polarity_qq <= #TCQ 0;
- pipe_tx_compliance_qq <= #TCQ 0;
- pipe_tx_char_is_k_qq <= #TCQ 0;
- pipe_tx_data_qq <= #TCQ 0;
- pipe_tx_elec_idle_qq <= #TCQ 1'b1;
- pipe_tx_powerdown_qq <= #TCQ 2'b10;
-
- end else begin
-
- pipe_rx_char_is_k_q <= #TCQ pipe_rx_char_is_k_i;
- pipe_rx_data_q <= #TCQ pipe_rx_data_i;
- pipe_rx_valid_q <= #TCQ pipe_rx_valid_i;
- pipe_rx_chanisaligned_q <= #TCQ pipe_rx_chanisaligned_i;
- pipe_rx_status_q <= #TCQ pipe_rx_status_i;
- pipe_rx_phy_status_q <= #TCQ pipe_rx_phy_status_i;
- pipe_rx_elec_idle_q <= #TCQ pipe_rx_elec_idle_i;
-
- pipe_rx_polarity_q <= #TCQ pipe_rx_polarity_i;
- pipe_tx_compliance_q <= #TCQ pipe_tx_compliance_i;
- pipe_tx_char_is_k_q <= #TCQ pipe_tx_char_is_k_i;
- pipe_tx_data_q <= #TCQ pipe_tx_data_i;
- pipe_tx_elec_idle_q <= #TCQ pipe_tx_elec_idle_i;
- pipe_tx_powerdown_q <= #TCQ pipe_tx_powerdown_i;
-
- pipe_rx_char_is_k_qq <= #TCQ pipe_rx_char_is_k_q;
- pipe_rx_data_qq <= #TCQ pipe_rx_data_q;
- pipe_rx_valid_qq <= #TCQ pipe_rx_valid_q;
- pipe_rx_chanisaligned_qq <= #TCQ pipe_rx_chanisaligned_q;
- pipe_rx_status_qq <= #TCQ pipe_rx_status_q;
- pipe_rx_phy_status_qq <= #TCQ pipe_rx_phy_status_q;
- pipe_rx_elec_idle_qq <= #TCQ pipe_rx_elec_idle_q;
-
- pipe_rx_polarity_qq <= #TCQ pipe_rx_polarity_q;
- pipe_tx_compliance_qq <= #TCQ pipe_tx_compliance_q;
- pipe_tx_char_is_k_qq <= #TCQ pipe_tx_char_is_k_q;
- pipe_tx_data_qq <= #TCQ pipe_tx_data_q;
- pipe_tx_elec_idle_qq <= #TCQ pipe_tx_elec_idle_q;
- pipe_tx_powerdown_qq <= #TCQ pipe_tx_powerdown_q;
-
- end
-
- end
-
- assign pipe_rx_char_is_k_o = pipe_rx_char_is_k_qq;
- assign pipe_rx_data_o = pipe_rx_data_qq;
- assign pipe_rx_valid_o = pipe_rx_valid_qq;
- assign pipe_rx_chanisaligned_o = pipe_rx_chanisaligned_qq;
- assign pipe_rx_status_o = pipe_rx_status_qq;
- assign pipe_rx_phy_status_o = pipe_rx_phy_status_qq;
- assign pipe_rx_elec_idle_o = pipe_rx_elec_idle_qq;
-
- assign pipe_rx_polarity_o = pipe_rx_polarity_qq;
- assign pipe_tx_compliance_o = pipe_tx_compliance_qq;
- assign pipe_tx_char_is_k_o = pipe_tx_char_is_k_qq;
- assign pipe_tx_data_o = pipe_tx_data_qq;
- assign pipe_tx_elec_idle_o = pipe_tx_elec_idle_qq;
- assign pipe_tx_powerdown_o = pipe_tx_powerdown_qq;
-
- end
-
- endgenerate
-
-endmodule
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_upconfig_fix_3451_v6.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_upconfig_fix_3451_v6.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_upconfig_fix_3451_v6.v (nonexistent)
@@ -1,142 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : pcie_upconfig_fix_3451_v6.v
-//--
-//-- Description: Virtex6 Workaround for Root Port Upconfigurability Bug
-//--
-//--
-//--------------------------------------------------------------------------------
-
-`timescale 1ns/1ns
-
-module pcie_upconfig_fix_3451_v6 # (
-
- parameter UPSTREAM_FACING = "TRUE",
- parameter PL_FAST_TRAIN = "FALSE",
- parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08
-
-)
-(
-
- input pipe_clk,
- input pl_phy_lnkup_n,
-
- input [5:0] pl_ltssm_state,
- input pl_sel_lnk_rate,
- input [1:0] pl_directed_link_change,
-
- input [3:0] cfg_link_status_negotiated_width,
-
- output filter_pipe
-
-);
-
- parameter TCQ = 1;
-
- reg reg_filter_pipe;
-
- reg [5:0] reg_prev_pl_ltssm_state;
- wire [5:0] prev_pl_ltssm_state;
-
- reg [15:0] reg_tsx_counter;
- wire [15:0] tsx_counter;
-
- wire [5:0] cap_link_width;
-
- // Corrupting all Tsx on all lanes as soon as we do R.RC->R.RI transition to allow time for
- // the core to see the TS1s on all the lanes being configured at the same time
- // R.RI has a 2ms timeout.Corrupting tsxs for ~1/4 of that time
- // 225 pipe_clk cycles-sim_fast_train
- // 60000 pipe_clk cycles-without sim_fast_train
- // Not taking any action when PLDIRECTEDLINKCHANGE is set
-
- always @ (posedge pipe_clk) begin
-
- if (pl_phy_lnkup_n) begin
-
- reg_tsx_counter <= #TCQ 16'h0;
- reg_filter_pipe <= #TCQ 1'b0;
-
- end else if ((pl_ltssm_state == 6'h20) &&
- (prev_pl_ltssm_state == 6'h1d) &&
- (cfg_link_status_negotiated_width != cap_link_width) &&
- (pl_directed_link_change[1:0] == 2'b00)) begin
-
- reg_tsx_counter <= #TCQ 16'h0;
- reg_filter_pipe <= #TCQ 1'b1;
-
- end else if (filter_pipe == 1'b1) begin
-
- if (tsx_counter < ((PL_FAST_TRAIN == "TRUE") ? 16'd225: pl_sel_lnk_rate ? 16'd30000 : 16'd60000)) begin
-
- reg_tsx_counter <= #TCQ tsx_counter + 1'b1;
- reg_filter_pipe <= #TCQ 1'b1;
-
- end else begin
-
- reg_tsx_counter <= #TCQ 16'h0;
- reg_filter_pipe <= #TCQ 1'b0;
-
- end
-
- end
-
- end
-
- assign filter_pipe = (UPSTREAM_FACING == "TRUE") ? 1'b0 : reg_filter_pipe;
- assign tsx_counter = reg_tsx_counter;
-
- always @(posedge pipe_clk) begin
-
- if (pl_phy_lnkup_n)
- reg_prev_pl_ltssm_state <= #TCQ 6'h0;
- else
- reg_prev_pl_ltssm_state <= #TCQ pl_ltssm_state;
-
- end
- assign prev_pl_ltssm_state = reg_prev_pl_ltssm_state;
-
- assign cap_link_width = LINK_CAP_MAX_LINK_WIDTH;
-
-endmodule
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_v6.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_v6.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_v6.v (nonexistent)
@@ -1,957 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : pcie_pipe_v6.v
-//-- Description: PIPE module for Virtex6 PCIe Block
-//--
-//--
-//--
-//--------------------------------------------------------------------------------
-
-`timescale 1ns/1ns
-
-module pcie_pipe_v6 #
-(
- parameter NO_OF_LANES = 8,
- parameter LINK_CAP_MAX_LINK_SPEED = 4'h1,
- parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
-)
-(
- // Pipe Per-Link Signals
- input wire pipe_tx_rcvr_det_i ,
- input wire pipe_tx_reset_i ,
- input wire pipe_tx_rate_i ,
- input wire pipe_tx_deemph_i ,
- input wire [2:0] pipe_tx_margin_i ,
- input wire pipe_tx_swing_i ,
-
- output wire pipe_tx_rcvr_det_o ,
- output wire pipe_tx_reset_o ,
- output wire pipe_tx_rate_o ,
- output wire pipe_tx_deemph_o ,
- output wire [2:0] pipe_tx_margin_o ,
- output wire pipe_tx_swing_o ,
-
- // Pipe Per-Lane Signals - Lane 0
- output wire [ 1:0] pipe_rx0_char_is_k_o ,
- output wire [15:0] pipe_rx0_data_o ,
- output wire pipe_rx0_valid_o ,
- output wire pipe_rx0_chanisaligned_o ,
- output wire [ 2:0] pipe_rx0_status_o ,
- output wire pipe_rx0_phy_status_o ,
- output wire pipe_rx0_elec_idle_o ,
- input wire pipe_rx0_polarity_i ,
- input wire pipe_tx0_compliance_i ,
- input wire [ 1:0] pipe_tx0_char_is_k_i ,
- input wire [15:0] pipe_tx0_data_i ,
- input wire pipe_tx0_elec_idle_i ,
- input wire [ 1:0] pipe_tx0_powerdown_i ,
-
- input wire [ 1:0] pipe_rx0_char_is_k_i ,
- input wire [15:0] pipe_rx0_data_i ,
- input wire pipe_rx0_valid_i ,
- input wire pipe_rx0_chanisaligned_i ,
- input wire [ 2:0] pipe_rx0_status_i ,
- input wire pipe_rx0_phy_status_i ,
- input wire pipe_rx0_elec_idle_i ,
- output wire pipe_rx0_polarity_o ,
- output wire pipe_tx0_compliance_o ,
- output wire [ 1:0] pipe_tx0_char_is_k_o ,
- output wire [15:0] pipe_tx0_data_o ,
- output wire pipe_tx0_elec_idle_o ,
- output wire [ 1:0] pipe_tx0_powerdown_o ,
-
- // Pipe Per-Lane Signals - Lane 1
- output wire [ 1:0] pipe_rx1_char_is_k_o ,
- output wire [15:0] pipe_rx1_data_o ,
- output wire pipe_rx1_valid_o ,
- output wire pipe_rx1_chanisaligned_o ,
- output wire [ 2:0] pipe_rx1_status_o ,
- output wire pipe_rx1_phy_status_o ,
- output wire pipe_rx1_elec_idle_o ,
- input wire pipe_rx1_polarity_i ,
- input wire pipe_tx1_compliance_i ,
- input wire [ 1:0] pipe_tx1_char_is_k_i ,
- input wire [15:0] pipe_tx1_data_i ,
- input wire pipe_tx1_elec_idle_i ,
- input wire [ 1:0] pipe_tx1_powerdown_i ,
-
- input wire [ 1:0] pipe_rx1_char_is_k_i ,
- input wire [15:0] pipe_rx1_data_i ,
- input wire pipe_rx1_valid_i ,
- input wire pipe_rx1_chanisaligned_i ,
- input wire [ 2:0] pipe_rx1_status_i ,
- input wire pipe_rx1_phy_status_i ,
- input wire pipe_rx1_elec_idle_i ,
- output wire pipe_rx1_polarity_o ,
- output wire pipe_tx1_compliance_o ,
- output wire [ 1:0] pipe_tx1_char_is_k_o ,
- output wire [15:0] pipe_tx1_data_o ,
- output wire pipe_tx1_elec_idle_o ,
- output wire [ 1:0] pipe_tx1_powerdown_o ,
-
- // Pipe Per-Lane Signals - Lane 2
- output wire [ 1:0] pipe_rx2_char_is_k_o ,
- output wire [15:0] pipe_rx2_data_o ,
- output wire pipe_rx2_valid_o ,
- output wire pipe_rx2_chanisaligned_o ,
- output wire [ 2:0] pipe_rx2_status_o ,
- output wire pipe_rx2_phy_status_o ,
- output wire pipe_rx2_elec_idle_o ,
- input wire pipe_rx2_polarity_i ,
- input wire pipe_tx2_compliance_i ,
- input wire [ 1:0] pipe_tx2_char_is_k_i ,
- input wire [15:0] pipe_tx2_data_i ,
- input wire pipe_tx2_elec_idle_i ,
- input wire [ 1:0] pipe_tx2_powerdown_i ,
-
- input wire [ 1:0] pipe_rx2_char_is_k_i ,
- input wire [15:0] pipe_rx2_data_i ,
- input wire pipe_rx2_valid_i ,
- input wire pipe_rx2_chanisaligned_i ,
- input wire [ 2:0] pipe_rx2_status_i ,
- input wire pipe_rx2_phy_status_i ,
- input wire pipe_rx2_elec_idle_i ,
- output wire pipe_rx2_polarity_o ,
- output wire pipe_tx2_compliance_o ,
- output wire [ 1:0] pipe_tx2_char_is_k_o ,
- output wire [15:0] pipe_tx2_data_o ,
- output wire pipe_tx2_elec_idle_o ,
- output wire [ 1:0] pipe_tx2_powerdown_o ,
-
- // Pipe Per-Lane Signals - Lane 3
- output wire [ 1:0] pipe_rx3_char_is_k_o ,
- output wire [15:0] pipe_rx3_data_o ,
- output wire pipe_rx3_valid_o ,
- output wire pipe_rx3_chanisaligned_o ,
- output wire [ 2:0] pipe_rx3_status_o ,
- output wire pipe_rx3_phy_status_o ,
- output wire pipe_rx3_elec_idle_o ,
- input wire pipe_rx3_polarity_i ,
- input wire pipe_tx3_compliance_i ,
- input wire [ 1:0] pipe_tx3_char_is_k_i ,
- input wire [15:0] pipe_tx3_data_i ,
- input wire pipe_tx3_elec_idle_i ,
- input wire [ 1:0] pipe_tx3_powerdown_i ,
-
- input wire [ 1:0] pipe_rx3_char_is_k_i ,
- input wire [15:0] pipe_rx3_data_i ,
- input wire pipe_rx3_valid_i ,
- input wire pipe_rx3_chanisaligned_i ,
- input wire [ 2:0] pipe_rx3_status_i ,
- input wire pipe_rx3_phy_status_i ,
- input wire pipe_rx3_elec_idle_i ,
- output wire pipe_rx3_polarity_o ,
- output wire pipe_tx3_compliance_o ,
- output wire [ 1:0] pipe_tx3_char_is_k_o ,
- output wire [15:0] pipe_tx3_data_o ,
- output wire pipe_tx3_elec_idle_o ,
- output wire [ 1:0] pipe_tx3_powerdown_o ,
-
- // Pipe Per-Lane Signals - Lane 4
- output wire [ 1:0] pipe_rx4_char_is_k_o ,
- output wire [15:0] pipe_rx4_data_o ,
- output wire pipe_rx4_valid_o ,
- output wire pipe_rx4_chanisaligned_o ,
- output wire [ 2:0] pipe_rx4_status_o ,
- output wire pipe_rx4_phy_status_o ,
- output wire pipe_rx4_elec_idle_o ,
- input wire pipe_rx4_polarity_i ,
- input wire pipe_tx4_compliance_i ,
- input wire [ 1:0] pipe_tx4_char_is_k_i ,
- input wire [15:0] pipe_tx4_data_i ,
- input wire pipe_tx4_elec_idle_i ,
- input wire [ 1:0] pipe_tx4_powerdown_i ,
-
- input wire [ 1:0] pipe_rx4_char_is_k_i ,
- input wire [15:0] pipe_rx4_data_i ,
- input wire pipe_rx4_valid_i ,
- input wire pipe_rx4_chanisaligned_i ,
- input wire [ 2:0] pipe_rx4_status_i ,
- input wire pipe_rx4_phy_status_i ,
- input wire pipe_rx4_elec_idle_i ,
- output wire pipe_rx4_polarity_o ,
- output wire pipe_tx4_compliance_o ,
- output wire [ 1:0] pipe_tx4_char_is_k_o ,
- output wire [15:0] pipe_tx4_data_o ,
- output wire pipe_tx4_elec_idle_o ,
- output wire [ 1:0] pipe_tx4_powerdown_o ,
-
- // Pipe Per-Lane Signals - Lane 5
- output wire [ 1:0] pipe_rx5_char_is_k_o ,
- output wire [15:0] pipe_rx5_data_o ,
- output wire pipe_rx5_valid_o ,
- output wire pipe_rx5_chanisaligned_o ,
- output wire [ 2:0] pipe_rx5_status_o ,
- output wire pipe_rx5_phy_status_o ,
- output wire pipe_rx5_elec_idle_o ,
- input wire pipe_rx5_polarity_i ,
- input wire pipe_tx5_compliance_i ,
- input wire [ 1:0] pipe_tx5_char_is_k_i ,
- input wire [15:0] pipe_tx5_data_i ,
- input wire pipe_tx5_elec_idle_i ,
- input wire [ 1:0] pipe_tx5_powerdown_i ,
-
- input wire [ 1:0] pipe_rx5_char_is_k_i ,
- input wire [15:0] pipe_rx5_data_i ,
- input wire pipe_rx5_valid_i ,
- input wire pipe_rx5_chanisaligned_i ,
- input wire [ 2:0] pipe_rx5_status_i ,
- input wire pipe_rx5_phy_status_i ,
- input wire pipe_rx5_elec_idle_i ,
- output wire pipe_rx5_polarity_o ,
- output wire pipe_tx5_compliance_o ,
- output wire [ 1:0] pipe_tx5_char_is_k_o ,
- output wire [15:0] pipe_tx5_data_o ,
- output wire pipe_tx5_elec_idle_o ,
- output wire [ 1:0] pipe_tx5_powerdown_o ,
-
- // Pipe Per-Lane Signals - Lane 6
- output wire [ 1:0] pipe_rx6_char_is_k_o ,
- output wire [15:0] pipe_rx6_data_o ,
- output wire pipe_rx6_valid_o ,
- output wire pipe_rx6_chanisaligned_o ,
- output wire [ 2:0] pipe_rx6_status_o ,
- output wire pipe_rx6_phy_status_o ,
- output wire pipe_rx6_elec_idle_o ,
- input wire pipe_rx6_polarity_i ,
- input wire pipe_tx6_compliance_i ,
- input wire [ 1:0] pipe_tx6_char_is_k_i ,
- input wire [15:0] pipe_tx6_data_i ,
- input wire pipe_tx6_elec_idle_i ,
- input wire [ 1:0] pipe_tx6_powerdown_i ,
-
- input wire [ 1:0] pipe_rx6_char_is_k_i ,
- input wire [15:0] pipe_rx6_data_i ,
- input wire pipe_rx6_valid_i ,
- input wire pipe_rx6_chanisaligned_i ,
- input wire [ 2:0] pipe_rx6_status_i ,
- input wire pipe_rx6_phy_status_i ,
- input wire pipe_rx6_elec_idle_i ,
- output wire pipe_rx6_polarity_o ,
- output wire pipe_tx6_compliance_o ,
- output wire [ 1:0] pipe_tx6_char_is_k_o ,
- output wire [15:0] pipe_tx6_data_o ,
- output wire pipe_tx6_elec_idle_o ,
- output wire [ 1:0] pipe_tx6_powerdown_o ,
-
- // Pipe Per-Lane Signals - Lane 7
- output wire [ 1:0] pipe_rx7_char_is_k_o ,
- output wire [15:0] pipe_rx7_data_o ,
- output wire pipe_rx7_valid_o ,
- output wire pipe_rx7_chanisaligned_o ,
- output wire [ 2:0] pipe_rx7_status_o ,
- output wire pipe_rx7_phy_status_o ,
- output wire pipe_rx7_elec_idle_o ,
- input wire pipe_rx7_polarity_i ,
- input wire pipe_tx7_compliance_i ,
- input wire [ 1:0] pipe_tx7_char_is_k_i ,
- input wire [15:0] pipe_tx7_data_i ,
- input wire pipe_tx7_elec_idle_i ,
- input wire [ 1:0] pipe_tx7_powerdown_i ,
-
- input wire [ 1:0] pipe_rx7_char_is_k_i ,
- input wire [15:0] pipe_rx7_data_i ,
- input wire pipe_rx7_valid_i ,
- input wire pipe_rx7_chanisaligned_i ,
- input wire [ 2:0] pipe_rx7_status_i ,
- input wire pipe_rx7_phy_status_i ,
- input wire pipe_rx7_elec_idle_i ,
- output wire pipe_rx7_polarity_o ,
- output wire pipe_tx7_compliance_o ,
- output wire [ 1:0] pipe_tx7_char_is_k_o ,
- output wire [15:0] pipe_tx7_data_o ,
- output wire pipe_tx7_elec_idle_o ,
- output wire [ 1:0] pipe_tx7_powerdown_o ,
-
- // Non PIPE signals
- input wire [ 5:0] pl_ltssm_state ,
- input wire pipe_clk ,
- input wire rst_n
-);
-
-//******************************************************************//
-// Reality check. //
-//******************************************************************//
-
- parameter Tc2o = 1; // clock to out delay model
-
-
- wire [ 1:0] pipe_rx0_char_is_k_q ;
- wire [15:0] pipe_rx0_data_q ;
- wire [ 1:0] pipe_rx1_char_is_k_q ;
- wire [15:0] pipe_rx1_data_q ;
- wire [ 1:0] pipe_rx2_char_is_k_q ;
- wire [15:0] pipe_rx2_data_q ;
- wire [ 1:0] pipe_rx3_char_is_k_q ;
- wire [15:0] pipe_rx3_data_q ;
- wire [ 1:0] pipe_rx4_char_is_k_q ;
- wire [15:0] pipe_rx4_data_q ;
- wire [ 1:0] pipe_rx5_char_is_k_q ;
- wire [15:0] pipe_rx5_data_q ;
- wire [ 1:0] pipe_rx6_char_is_k_q ;
- wire [15:0] pipe_rx6_data_q ;
- wire [ 1:0] pipe_rx7_char_is_k_q ;
- wire [15:0] pipe_rx7_data_q ;
-
-//synthesis translate_off
-// initial begin
-// $display("[%t] %m NO_OF_LANES %0d PIPE_PIPELINE_STAGES %0d", $time, NO_OF_LANES, PIPE_PIPELINE_STAGES);
-// end
-//synthesis translate_on
-
- generate
-
- pcie_pipe_misc_v6 # (
-
- .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
-
- )
- pipe_misc_i (
-
- .pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i),
- .pipe_tx_reset_i(pipe_tx_reset_i),
- .pipe_tx_rate_i(pipe_tx_rate_i),
- .pipe_tx_deemph_i(pipe_tx_deemph_i),
- .pipe_tx_margin_i(pipe_tx_margin_i),
- .pipe_tx_swing_i(pipe_tx_swing_i),
-
- .pipe_tx_rcvr_det_o(pipe_tx_rcvr_det_o),
- .pipe_tx_reset_o(pipe_tx_reset_o),
- .pipe_tx_rate_o(pipe_tx_rate_o),
- .pipe_tx_deemph_o(pipe_tx_deemph_o),
- .pipe_tx_margin_o(pipe_tx_margin_o),
- .pipe_tx_swing_o(pipe_tx_swing_o) ,
-
- .pipe_clk(pipe_clk),
- .rst_n(rst_n)
- );
-
-
- pcie_pipe_lane_v6 # (
-
- .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
-
- )
- pipe_lane_0_i (
-
- .pipe_rx_char_is_k_o(pipe_rx0_char_is_k_q),
- .pipe_rx_data_o(pipe_rx0_data_q),
- .pipe_rx_valid_o(pipe_rx0_valid_o),
- .pipe_rx_chanisaligned_o(pipe_rx0_chanisaligned_o),
- .pipe_rx_status_o(pipe_rx0_status_o),
- .pipe_rx_phy_status_o(pipe_rx0_phy_status_o),
- .pipe_rx_elec_idle_o(pipe_rx0_elec_idle_o),
- .pipe_rx_polarity_i(pipe_rx0_polarity_i),
- .pipe_tx_compliance_i(pipe_tx0_compliance_i),
- .pipe_tx_char_is_k_i(pipe_tx0_char_is_k_i),
- .pipe_tx_data_i(pipe_tx0_data_i),
- .pipe_tx_elec_idle_i(pipe_tx0_elec_idle_i),
- .pipe_tx_powerdown_i(pipe_tx0_powerdown_i),
-
- .pipe_rx_char_is_k_i(pipe_rx0_char_is_k_i),
- .pipe_rx_data_i(pipe_rx0_data_i),
- .pipe_rx_valid_i(pipe_rx0_valid_i),
- .pipe_rx_chanisaligned_i(pipe_rx0_chanisaligned_i),
- .pipe_rx_status_i(pipe_rx0_status_i),
- .pipe_rx_phy_status_i(pipe_rx0_phy_status_i),
- .pipe_rx_elec_idle_i(pipe_rx0_elec_idle_i),
- .pipe_rx_polarity_o(pipe_rx0_polarity_o),
- .pipe_tx_compliance_o(pipe_tx0_compliance_o),
- .pipe_tx_char_is_k_o(pipe_tx0_char_is_k_o),
- .pipe_tx_data_o(pipe_tx0_data_o),
- .pipe_tx_elec_idle_o(pipe_tx0_elec_idle_o),
- .pipe_tx_powerdown_o(pipe_tx0_powerdown_o),
-
- .pipe_clk(pipe_clk),
- .rst_n(rst_n)
-
- );
-
- if (NO_OF_LANES >= 2) begin
-
- pcie_pipe_lane_v6 # (
-
- .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
-
- )
- pipe_lane_1_i (
-
- .pipe_rx_char_is_k_o(pipe_rx1_char_is_k_q),
- .pipe_rx_data_o(pipe_rx1_data_q),
- .pipe_rx_valid_o(pipe_rx1_valid_o),
- .pipe_rx_chanisaligned_o(pipe_rx1_chanisaligned_o),
- .pipe_rx_status_o(pipe_rx1_status_o),
- .pipe_rx_phy_status_o(pipe_rx1_phy_status_o),
- .pipe_rx_elec_idle_o(pipe_rx1_elec_idle_o),
- .pipe_rx_polarity_i(pipe_rx1_polarity_i),
- .pipe_tx_compliance_i(pipe_tx1_compliance_i),
- .pipe_tx_char_is_k_i(pipe_tx1_char_is_k_i),
- .pipe_tx_data_i(pipe_tx1_data_i),
- .pipe_tx_elec_idle_i(pipe_tx1_elec_idle_i),
- .pipe_tx_powerdown_i(pipe_tx1_powerdown_i),
-
- .pipe_rx_char_is_k_i(pipe_rx1_char_is_k_i),
- .pipe_rx_data_i(pipe_rx1_data_i),
- .pipe_rx_valid_i(pipe_rx1_valid_i),
- .pipe_rx_chanisaligned_i(pipe_rx1_chanisaligned_i),
- .pipe_rx_status_i(pipe_rx1_status_i),
- .pipe_rx_phy_status_i(pipe_rx1_phy_status_i),
- .pipe_rx_elec_idle_i(pipe_rx1_elec_idle_i),
- .pipe_rx_polarity_o(pipe_rx1_polarity_o),
- .pipe_tx_compliance_o(pipe_tx1_compliance_o),
- .pipe_tx_char_is_k_o(pipe_tx1_char_is_k_o),
- .pipe_tx_data_o(pipe_tx1_data_o),
- .pipe_tx_elec_idle_o(pipe_tx1_elec_idle_o),
- .pipe_tx_powerdown_o(pipe_tx1_powerdown_o),
-
- .pipe_clk(pipe_clk),
- .rst_n(rst_n)
-
- );
-
- end
- else begin
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-// start remove before release
-`ifndef PIPE_RX_ERR_INJ
-// end remove before release
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
- assign pipe_rx1_char_is_k_o = 2'b00;
- assign pipe_rx1_data_o = 16'h0000;
- assign pipe_rx1_valid_o = 1'b0;
- assign pipe_rx1_chanisaligned_o = 1'b0;
- assign pipe_rx1_status_o = 3'b000;
- assign pipe_rx1_phy_status_o = 1'b0;
- assign pipe_rx1_elec_idle_o = 1'b1;
- assign pipe_rx1_polarity_o = 1'b0;
- assign pipe_tx1_compliance_o = 1'b0;
- assign pipe_tx1_char_is_k_o = 2'b00;
- assign pipe_tx1_data_o = 16'h0000;
- assign pipe_tx1_elec_idle_o = 1'b1;
- assign pipe_tx1_powerdown_o = 2'b00;
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-// start remove before release
-`endif // PIPE_RX_ERR_INJ
-// end remove before release
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
- end
-
- if (NO_OF_LANES >= 4) begin
-
- pcie_pipe_lane_v6 # (
-
- .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
- )
- pipe_lane_2_i (
-
- .pipe_rx_char_is_k_o(pipe_rx2_char_is_k_q),
- .pipe_rx_data_o(pipe_rx2_data_q),
- .pipe_rx_valid_o(pipe_rx2_valid_o),
- .pipe_rx_chanisaligned_o(pipe_rx2_chanisaligned_o),
- .pipe_rx_status_o(pipe_rx2_status_o),
- .pipe_rx_phy_status_o(pipe_rx2_phy_status_o),
- .pipe_rx_elec_idle_o(pipe_rx2_elec_idle_o),
- .pipe_rx_polarity_i(pipe_rx2_polarity_i),
- .pipe_tx_compliance_i(pipe_tx2_compliance_i),
- .pipe_tx_char_is_k_i(pipe_tx2_char_is_k_i),
- .pipe_tx_data_i(pipe_tx2_data_i),
- .pipe_tx_elec_idle_i(pipe_tx2_elec_idle_i),
- .pipe_tx_powerdown_i(pipe_tx2_powerdown_i),
-
- .pipe_rx_char_is_k_i(pipe_rx2_char_is_k_i),
- .pipe_rx_data_i(pipe_rx2_data_i),
- .pipe_rx_valid_i(pipe_rx2_valid_i),
- .pipe_rx_chanisaligned_i(pipe_rx2_chanisaligned_i),
- .pipe_rx_status_i(pipe_rx2_status_i),
- .pipe_rx_phy_status_i(pipe_rx2_phy_status_i),
- .pipe_rx_elec_idle_i(pipe_rx2_elec_idle_i),
- .pipe_rx_polarity_o(pipe_rx2_polarity_o),
- .pipe_tx_compliance_o(pipe_tx2_compliance_o),
- .pipe_tx_char_is_k_o(pipe_tx2_char_is_k_o),
- .pipe_tx_data_o(pipe_tx2_data_o),
- .pipe_tx_elec_idle_o(pipe_tx2_elec_idle_o),
- .pipe_tx_powerdown_o(pipe_tx2_powerdown_o),
-
- .pipe_clk(pipe_clk),
- .rst_n(rst_n)
-
- );
-
- pcie_pipe_lane_v6 # (
-
- .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
-
- )
- pipe_lane_3_i (
-
- .pipe_rx_char_is_k_o(pipe_rx3_char_is_k_q),
- .pipe_rx_data_o(pipe_rx3_data_q),
- .pipe_rx_valid_o(pipe_rx3_valid_o),
- .pipe_rx_chanisaligned_o(pipe_rx3_chanisaligned_o),
- .pipe_rx_status_o(pipe_rx3_status_o),
- .pipe_rx_phy_status_o(pipe_rx3_phy_status_o),
- .pipe_rx_elec_idle_o(pipe_rx3_elec_idle_o),
- .pipe_rx_polarity_i(pipe_rx3_polarity_i),
- .pipe_tx_compliance_i(pipe_tx3_compliance_i),
- .pipe_tx_char_is_k_i(pipe_tx3_char_is_k_i),
- .pipe_tx_data_i(pipe_tx3_data_i),
- .pipe_tx_elec_idle_i(pipe_tx3_elec_idle_i),
- .pipe_tx_powerdown_i(pipe_tx3_powerdown_i),
-
- .pipe_rx_char_is_k_i(pipe_rx3_char_is_k_i),
- .pipe_rx_data_i(pipe_rx3_data_i),
- .pipe_rx_valid_i(pipe_rx3_valid_i),
- .pipe_rx_chanisaligned_i(pipe_rx3_chanisaligned_i),
- .pipe_rx_status_i(pipe_rx3_status_i),
- .pipe_rx_phy_status_i(pipe_rx3_phy_status_i),
- .pipe_rx_elec_idle_i(pipe_rx3_elec_idle_i),
- .pipe_rx_polarity_o(pipe_rx3_polarity_o),
- .pipe_tx_compliance_o(pipe_tx3_compliance_o),
- .pipe_tx_char_is_k_o(pipe_tx3_char_is_k_o),
- .pipe_tx_data_o(pipe_tx3_data_o),
- .pipe_tx_elec_idle_o(pipe_tx3_elec_idle_o),
- .pipe_tx_powerdown_o(pipe_tx3_powerdown_o),
-
- .pipe_clk(pipe_clk),
- .rst_n(rst_n)
-
- );
-
- end
- else begin
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-// start remove before release
-`ifndef PIPE_RX_ERR_INJ
-// end remove before release
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
- assign pipe_rx2_char_is_k_o = 2'b00;
- assign pipe_rx2_data_o = 16'h0000;
- assign pipe_rx2_valid_o = 1'b0;
- assign pipe_rx2_chanisaligned_o = 1'b0;
- assign pipe_rx2_status_o = 3'b000;
- assign pipe_rx2_phy_status_o = 1'b0;
- assign pipe_rx2_elec_idle_o = 1'b1;
- assign pipe_rx2_polarity_o = 1'b0;
- assign pipe_tx2_compliance_o = 1'b0;
- assign pipe_tx2_char_is_k_o = 2'b00;
- assign pipe_tx2_data_o = 16'h0000;
- assign pipe_tx2_elec_idle_o = 1'b1;
- assign pipe_tx2_powerdown_o = 2'b00;
-
- assign pipe_rx3_char_is_k_o = 2'b00;
- assign pipe_rx3_data_o = 16'h0000;
- assign pipe_rx3_valid_o = 1'b0;
- assign pipe_rx3_chanisaligned_o = 1'b0;
- assign pipe_rx3_status_o = 3'b000;
- assign pipe_rx3_phy_status_o = 1'b0;
- assign pipe_rx3_elec_idle_o = 1'b1;
- assign pipe_rx3_polarity_o = 1'b0;
- assign pipe_tx3_compliance_o = 1'b0;
- assign pipe_tx3_char_is_k_o = 2'b00;
- assign pipe_tx3_data_o = 16'h0000;
- assign pipe_tx3_elec_idle_o = 1'b1;
- assign pipe_tx3_powerdown_o = 2'b00;
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-// start remove before release
-`endif // PIPE_RX_ERR_INJ
-// end remove before release
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
- end
-
- if (NO_OF_LANES >= 8) begin
-
- pcie_pipe_lane_v6 # (
-
- .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
-
- )
- pipe_lane_4_i (
-
- .pipe_rx_char_is_k_o(pipe_rx4_char_is_k_q),
- .pipe_rx_data_o(pipe_rx4_data_q),
- .pipe_rx_valid_o(pipe_rx4_valid_o),
- .pipe_rx_chanisaligned_o(pipe_rx4_chanisaligned_o),
- .pipe_rx_status_o(pipe_rx4_status_o),
- .pipe_rx_phy_status_o(pipe_rx4_phy_status_o),
- .pipe_rx_elec_idle_o(pipe_rx4_elec_idle_o),
- .pipe_rx_polarity_i(pipe_rx4_polarity_i),
- .pipe_tx_compliance_i(pipe_tx4_compliance_i),
- .pipe_tx_char_is_k_i(pipe_tx4_char_is_k_i),
- .pipe_tx_data_i(pipe_tx4_data_i),
- .pipe_tx_elec_idle_i(pipe_tx4_elec_idle_i),
- .pipe_tx_powerdown_i(pipe_tx4_powerdown_i),
-
- .pipe_rx_char_is_k_i(pipe_rx4_char_is_k_i),
- .pipe_rx_data_i(pipe_rx4_data_i),
- .pipe_rx_valid_i(pipe_rx4_valid_i),
- .pipe_rx_chanisaligned_i(pipe_rx4_chanisaligned_i),
- .pipe_rx_status_i(pipe_rx4_status_i),
- .pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
- .pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),
- .pipe_rx_polarity_o(pipe_rx4_polarity_o),
- .pipe_tx_compliance_o(pipe_tx4_compliance_o),
- .pipe_tx_char_is_k_o(pipe_tx4_char_is_k_o),
- .pipe_tx_data_o(pipe_tx4_data_o),
- .pipe_tx_elec_idle_o(pipe_tx4_elec_idle_o),
- .pipe_tx_powerdown_o(pipe_tx4_powerdown_o),
-
- .pipe_clk(pipe_clk),
- .rst_n(rst_n)
-
- );
-
- pcie_pipe_lane_v6 # (
-
- .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
-
- )
- pipe_lane_5_i (
-
- .pipe_rx_char_is_k_o(pipe_rx5_char_is_k_q),
- .pipe_rx_data_o(pipe_rx5_data_q),
- .pipe_rx_valid_o(pipe_rx5_valid_o),
- .pipe_rx_chanisaligned_o(pipe_rx5_chanisaligned_o),
- .pipe_rx_status_o(pipe_rx5_status_o),
- .pipe_rx_phy_status_o(pipe_rx5_phy_status_o),
- .pipe_rx_elec_idle_o(pipe_rx5_elec_idle_o),
- .pipe_rx_polarity_i(pipe_rx5_polarity_i),
- .pipe_tx_compliance_i(pipe_tx5_compliance_i),
- .pipe_tx_char_is_k_i(pipe_tx5_char_is_k_i),
- .pipe_tx_data_i(pipe_tx5_data_i),
- .pipe_tx_elec_idle_i(pipe_tx5_elec_idle_i),
- .pipe_tx_powerdown_i(pipe_tx5_powerdown_i),
-
- .pipe_rx_char_is_k_i(pipe_rx5_char_is_k_i),
- .pipe_rx_data_i(pipe_rx5_data_i),
- .pipe_rx_valid_i(pipe_rx5_valid_i),
- .pipe_rx_chanisaligned_i(pipe_rx5_chanisaligned_i),
- .pipe_rx_status_i(pipe_rx5_status_i),
- .pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
- .pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),
- .pipe_rx_polarity_o(pipe_rx5_polarity_o),
- .pipe_tx_compliance_o(pipe_tx5_compliance_o),
- .pipe_tx_char_is_k_o(pipe_tx5_char_is_k_o),
- .pipe_tx_data_o(pipe_tx5_data_o),
- .pipe_tx_elec_idle_o(pipe_tx5_elec_idle_o),
- .pipe_tx_powerdown_o(pipe_tx5_powerdown_o),
-
- .pipe_clk(pipe_clk),
- .rst_n(rst_n)
-
- );
-
- pcie_pipe_lane_v6 # (
-
- .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
-
- )
- pipe_lane_6_i (
-
- .pipe_rx_char_is_k_o(pipe_rx6_char_is_k_q),
- .pipe_rx_data_o(pipe_rx6_data_q),
- .pipe_rx_valid_o(pipe_rx6_valid_o),
- .pipe_rx_chanisaligned_o(pipe_rx6_chanisaligned_o),
- .pipe_rx_status_o(pipe_rx6_status_o),
- .pipe_rx_phy_status_o(pipe_rx6_phy_status_o),
- .pipe_rx_elec_idle_o(pipe_rx6_elec_idle_o),
- .pipe_rx_polarity_i(pipe_rx6_polarity_i),
- .pipe_tx_compliance_i(pipe_tx6_compliance_i),
- .pipe_tx_char_is_k_i(pipe_tx6_char_is_k_i),
- .pipe_tx_data_i(pipe_tx6_data_i),
- .pipe_tx_elec_idle_i(pipe_tx6_elec_idle_i),
- .pipe_tx_powerdown_i(pipe_tx6_powerdown_i),
-
- .pipe_rx_char_is_k_i(pipe_rx6_char_is_k_i),
- .pipe_rx_data_i(pipe_rx6_data_i),
- .pipe_rx_valid_i(pipe_rx6_valid_i),
- .pipe_rx_chanisaligned_i(pipe_rx6_chanisaligned_i),
- .pipe_rx_status_i(pipe_rx6_status_i),
- .pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
- .pipe_rx_elec_idle_i(pipe_rx6_elec_idle_i),
- .pipe_rx_polarity_o(pipe_rx6_polarity_o),
- .pipe_tx_compliance_o(pipe_tx6_compliance_o),
- .pipe_tx_char_is_k_o(pipe_tx6_char_is_k_o),
- .pipe_tx_data_o(pipe_tx6_data_o),
- .pipe_tx_elec_idle_o(pipe_tx6_elec_idle_o),
- .pipe_tx_powerdown_o(pipe_tx6_powerdown_o),
-
- .pipe_clk(pipe_clk),
- .rst_n(rst_n)
-
- );
-
- pcie_pipe_lane_v6 # (
-
- .PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
-
- )
- pipe_lane_7_i (
-
- .pipe_rx_char_is_k_o(pipe_rx7_char_is_k_q),
- .pipe_rx_data_o(pipe_rx7_data_q),
- .pipe_rx_valid_o(pipe_rx7_valid_o),
- .pipe_rx_chanisaligned_o(pipe_rx7_chanisaligned_o),
- .pipe_rx_status_o(pipe_rx7_status_o),
- .pipe_rx_phy_status_o(pipe_rx7_phy_status_o),
- .pipe_rx_elec_idle_o(pipe_rx7_elec_idle_o),
- .pipe_rx_polarity_i(pipe_rx7_polarity_i),
- .pipe_tx_compliance_i(pipe_tx7_compliance_i),
- .pipe_tx_char_is_k_i(pipe_tx7_char_is_k_i),
- .pipe_tx_data_i(pipe_tx7_data_i),
- .pipe_tx_elec_idle_i(pipe_tx7_elec_idle_i),
- .pipe_tx_powerdown_i(pipe_tx7_powerdown_i),
-
- .pipe_rx_char_is_k_i(pipe_rx7_char_is_k_i),
- .pipe_rx_data_i(pipe_rx7_data_i),
- .pipe_rx_valid_i(pipe_rx7_valid_i),
- .pipe_rx_chanisaligned_i(pipe_rx7_chanisaligned_i),
- .pipe_rx_status_i(pipe_rx7_status_i),
- .pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
- .pipe_rx_elec_idle_i(pipe_rx7_elec_idle_i),
- .pipe_rx_polarity_o(pipe_rx7_polarity_o),
- .pipe_tx_compliance_o(pipe_tx7_compliance_o),
- .pipe_tx_char_is_k_o(pipe_tx7_char_is_k_o),
- .pipe_tx_data_o(pipe_tx7_data_o),
- .pipe_tx_elec_idle_o(pipe_tx7_elec_idle_o),
- .pipe_tx_powerdown_o(pipe_tx7_powerdown_o),
-
- .pipe_clk(pipe_clk),
- .rst_n(rst_n)
-
- );
-
- end
- else begin
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-// start remove before release
-`ifndef PIPE_RX_ERR_INJ
-// end remove before release
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
- assign pipe_rx4_char_is_k_o = 2'b00;
- assign pipe_rx4_data_o = 16'h0000;
- assign pipe_rx4_valid_o = 1'b0;
- assign pipe_rx4_chanisaligned_o = 1'b0;
- assign pipe_rx4_status_o = 3'b000;
- assign pipe_rx4_phy_status_o = 1'b0;
- assign pipe_rx4_elec_idle_o = 1'b1;
- assign pipe_rx4_polarity_o = 1'b0;
- assign pipe_tx4_compliance_o = 1'b0;
- assign pipe_tx4_char_is_k_o = 2'b00;
- assign pipe_tx4_data_o = 16'h0000;
- assign pipe_tx4_elec_idle_o = 1'b1;
- assign pipe_tx4_powerdown_o = 2'b00;
-
- assign pipe_rx5_char_is_k_o = 2'b00;
- assign pipe_rx5_data_o = 16'h0000;
- assign pipe_rx5_valid_o = 1'b0;
- assign pipe_rx5_chanisaligned_o = 1'b0;
- assign pipe_rx5_status_o = 3'b000;
- assign pipe_rx5_phy_status_o = 1'b0;
- assign pipe_rx5_elec_idle_o = 1'b1;
- assign pipe_rx5_polarity_o = 1'b0;
- assign pipe_tx5_compliance_o = 1'b0;
- assign pipe_tx5_char_is_k_o = 2'b00;
- assign pipe_tx5_data_o = 16'h0000;
- assign pipe_tx5_elec_idle_o = 1'b1;
- assign pipe_tx5_powerdown_o = 2'b00;
-
- assign pipe_rx6_char_is_k_o = 2'b00;
- assign pipe_rx6_data_o = 16'h0000;
- assign pipe_rx6_valid_o = 1'b0;
- assign pipe_rx6_chanisaligned_o = 1'b0;
- assign pipe_rx6_status_o = 3'b000;
- assign pipe_rx6_phy_status_o = 1'b0;
- assign pipe_rx6_elec_idle_o = 1'b1;
- assign pipe_rx6_polarity_o = 1'b0;
- assign pipe_tx6_compliance_o = 1'b0;
- assign pipe_tx6_char_is_k_o = 2'b00;
- assign pipe_tx6_data_o = 16'h0000;
- assign pipe_tx6_elec_idle_o = 1'b1;
- assign pipe_tx6_powerdown_o = 2'b00;
-
- assign pipe_rx7_char_is_k_o = 2'b00;
- assign pipe_rx7_data_o = 16'h0000;
- assign pipe_rx7_valid_o = 1'b0;
- assign pipe_rx7_chanisaligned_o = 1'b0;
- assign pipe_rx7_status_o = 3'b000;
- assign pipe_rx7_phy_status_o = 1'b0;
- assign pipe_rx7_elec_idle_o = 1'b1;
- assign pipe_rx7_polarity_o = 1'b0;
- assign pipe_tx7_compliance_o = 1'b0;
- assign pipe_tx7_char_is_k_o = 2'b00;
- assign pipe_tx7_data_o = 16'h0000;
- assign pipe_tx7_elec_idle_o = 1'b1;
- assign pipe_tx7_powerdown_o = 2'b00;
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-// start remove before release
-`endif // PIPE_RX_ERR_INJ
-// end remove before release
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
- end
-
- endgenerate
-
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-// start remove before release
-`ifdef PIPE_RX_ERR_INJ
-
-generate
-
-if (LINK_CAP_MAX_LINK_SPEED == 4'h2) begin
-
-reg [5:0] pl_ltssm_state_q;
-
-always @(posedge pipe_clk) begin
-
- if (rst_n)
- pl_ltssm_state_q <= 0;
- else
- pl_ltssm_state_q <= pl_ltssm_state;
-
-end
-
-wire plm_in_l0 = (pl_ltssm_state_q == 6'h16);
-
-
-pcie_pipe_err_inject # (
- .NO_OF_LANES(NO_OF_LANES)
-)
-rx_err_inj(
-
- .enable(plm_in_l0),
- .pipe_clk(pipe_clk),
- .pipe_rst(!rst_n),
-
- .o_ln0_cisk(pipe_rx0_char_is_k_o),
- .o_ln0_data(pipe_rx0_data_o),
- .i_ln0_cisk(pipe_rx0_char_is_k_q),
- .i_ln0_data(pipe_rx0_data_q),
- .o_ln1_cisk(pipe_rx1_char_is_k_o),
- .o_ln1_data(pipe_rx1_data_o),
- .i_ln1_cisk((NO_OF_LANES >= 2 ) ? pipe_rx1_char_is_k_q : 2'b0),
- .i_ln1_data((NO_OF_LANES >= 2 ) ? pipe_rx1_data_q : 16'h0),
- .o_ln2_cisk(pipe_rx2_char_is_k_o),
- .o_ln2_data(pipe_rx2_data_o),
- .i_ln2_cisk((NO_OF_LANES >= 4 ) ? pipe_rx2_char_is_k_q : 2'b0),
- .i_ln2_data((NO_OF_LANES >= 4 ) ? pipe_rx2_data_q : 16'h0),
- .o_ln3_cisk(pipe_rx3_char_is_k_o),
- .o_ln3_data(pipe_rx3_data_o),
- .i_ln3_cisk((NO_OF_LANES >= 4 ) ? pipe_rx3_char_is_k_q : 2'b0),
- .i_ln3_data((NO_OF_LANES >= 4 ) ? pipe_rx3_data_q : 16'h0),
- .o_ln4_cisk(pipe_rx4_char_is_k_o),
- .o_ln4_data(pipe_rx4_data_o),
- .i_ln4_cisk((NO_OF_LANES >= 8 ) ? pipe_rx4_char_is_k_q : 2'b0),
- .i_ln4_data((NO_OF_LANES >= 8 ) ? pipe_rx4_data_q : 16'h0),
- .o_ln5_cisk(pipe_rx5_char_is_k_o),
- .o_ln5_data(pipe_rx5_data_o),
- .i_ln5_cisk((NO_OF_LANES >= 8 ) ? pipe_rx5_char_is_k_q : 2'b0),
- .i_ln5_data((NO_OF_LANES >= 8 ) ? pipe_rx5_data_q : 16'h0),
- .o_ln6_cisk(pipe_rx6_char_is_k_o),
- .o_ln6_data(pipe_rx6_data_o),
- .i_ln6_cisk((NO_OF_LANES >= 8 ) ? pipe_rx6_char_is_k_q : 2'b0),
- .i_ln6_data((NO_OF_LANES >= 8 ) ? pipe_rx6_data_q : 16'h0),
- .o_ln7_cisk(pipe_rx7_char_is_k_o),
- .o_ln7_data(pipe_rx7_data_o),
- .i_ln7_cisk((NO_OF_LANES >= 8 ) ? pipe_rx7_char_is_k_q : 2'b0),
- .i_ln7_data((NO_OF_LANES >= 8 ) ? pipe_rx7_data_q : 16'h0)
-);
-
-end else begin
-
-assign pipe_rx0_char_is_k_o = pipe_rx0_char_is_k_q;
-assign pipe_rx0_data_o = pipe_rx0_data_q;
-assign pipe_rx1_char_is_k_o = pipe_rx1_char_is_k_q;
-assign pipe_rx1_data_o = pipe_rx1_data_q;
-assign pipe_rx2_char_is_k_o = pipe_rx2_char_is_k_q;
-assign pipe_rx2_data_o = pipe_rx2_data_q;
-assign pipe_rx3_char_is_k_o = pipe_rx3_char_is_k_q;
-assign pipe_rx3_data_o = pipe_rx3_data_q;
-assign pipe_rx4_char_is_k_o = pipe_rx4_char_is_k_q;
-assign pipe_rx4_data_o = pipe_rx4_data_q;
-assign pipe_rx5_char_is_k_o = pipe_rx5_char_is_k_q;
-assign pipe_rx5_data_o = pipe_rx5_data_q;
-assign pipe_rx6_char_is_k_o = pipe_rx6_char_is_k_q;
-assign pipe_rx6_data_o = pipe_rx6_data_q;
-assign pipe_rx7_char_is_k_o = pipe_rx7_char_is_k_q;
-assign pipe_rx7_data_o = pipe_rx7_data_q;
-
-end
-
-endgenerate
-
-
-`endif // PIPE_RX_ERR_INJ
-// end remove before release
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-// start remove before release
-`ifndef PIPE_RX_ERR_INJ
-// end remove before release
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-
- assign pipe_rx0_char_is_k_o = pipe_rx0_char_is_k_q;
- assign pipe_rx0_data_o = pipe_rx0_data_q;
- assign pipe_rx1_char_is_k_o = pipe_rx1_char_is_k_q;
- assign pipe_rx1_data_o = pipe_rx1_data_q;
- assign pipe_rx2_char_is_k_o = pipe_rx2_char_is_k_q;
- assign pipe_rx2_data_o = pipe_rx2_data_q;
- assign pipe_rx3_char_is_k_o = pipe_rx3_char_is_k_q;
- assign pipe_rx3_data_o = pipe_rx3_data_q;
- assign pipe_rx4_char_is_k_o = pipe_rx4_char_is_k_q;
- assign pipe_rx4_data_o = pipe_rx4_data_q;
- assign pipe_rx5_char_is_k_o = pipe_rx5_char_is_k_q;
- assign pipe_rx5_data_o = pipe_rx5_data_q;
- assign pipe_rx6_char_is_k_o = pipe_rx6_char_is_k_q;
- assign pipe_rx6_data_o = pipe_rx6_data_q;
- assign pipe_rx7_char_is_k_o = pipe_rx7_char_is_k_q;
- assign pipe_rx7_data_o = pipe_rx7_data_q;
-
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-// start remove before release
-`endif // PIPE_RX_ERR_INJ
-// end remove before release
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-
-endmodule
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_rx_valid_filter_v6.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_rx_valid_filter_v6.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_rx_valid_filter_v6.v (nonexistent)
@@ -1,320 +0,0 @@
-
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : gtx_rx_valid_filter_v6.v
-
-`timescale 1ns / 1ns
-
-module GTX_RX_VALID_FILTER_V6 #(
-
- parameter CLK_COR_MIN_LAT = 28
-
-)
-(
- output [1:0] USER_RXCHARISK,
- output [15:0] USER_RXDATA,
- output USER_RXVALID,
- output USER_RXELECIDLE,
- output [ 2:0] USER_RX_STATUS,
- output USER_RX_PHY_STATUS,
-
- input [1:0] GT_RXCHARISK,
- input [15:0] GT_RXDATA,
- input GT_RXVALID,
- input GT_RXELECIDLE,
- input [ 2:0] GT_RX_STATUS,
- input GT_RX_PHY_STATUS,
-
-
- input USER_CLK,
- input RESET
-
-);
-
- parameter TCQ = 1;
-
- parameter EIOS_DET_IDL = 5'b00001;
- parameter EIOS_DET_NO_STR0 = 5'b00010;
- parameter EIOS_DET_STR0 = 5'b00100;
- parameter EIOS_DET_STR1 = 5'b01000;
- parameter EIOS_DET_DONE = 5'b10000;
-
- parameter EIOS_COM = 8'hBC;
- parameter EIOS_IDL = 8'h7C;
-
- reg [4:0] reg_state_eios_det;
- wire [4:0] state_eios_det;
-
- reg reg_eios_detected;
- wire eios_detected;
-
- reg reg_symbol_after_eios;
- wire symbol_after_eios;
-
- parameter USER_RXVLD_IDL = 4'b0001;
- parameter USER_RXVLD_EI = 4'b0010;
- parameter USER_RXVLD_EI_DB0 = 4'b0100;
- parameter USER_RXVLD_EI_DB1 = 4'b1000;
-
- reg [3:0] reg_state_rxvld_ei;
- wire [3:0] state_rxvld_ei;
-
- reg [4:0] reg_rxvld_count;
- wire [4:0] rxvld_count;
-
- reg [3:0] reg_rxvld_fallback;
- wire [3:0] rxvld_fallback;
-
- reg [1:0] gt_rxcharisk_q;
- reg [15:0] gt_rxdata_q;
- reg gt_rxvalid_q;
- reg gt_rxelecidle_q;
-
- reg [ 2:0] gt_rx_status_q;
- reg gt_rx_phy_status_q;
-
- // EIOS detector
-
- always @(posedge USER_CLK) begin
-
- if (RESET) begin
-
- reg_eios_detected <= #TCQ 1'b0;
- reg_state_eios_det <= #TCQ EIOS_DET_IDL;
- reg_symbol_after_eios <= #TCQ 1'b0;
- gt_rxcharisk_q <= #TCQ 2'b00;
- gt_rxdata_q <= #TCQ 16'h0;
- gt_rxvalid_q <= #TCQ 1'b0;
- gt_rxelecidle_q <= #TCQ 1'b0;
- gt_rx_status_q <= #TCQ 3'b000;
- gt_rx_phy_status_q <= #TCQ 1'b0;
-
- end else begin
-
- reg_eios_detected <= #TCQ 1'b0;
- reg_symbol_after_eios <= #TCQ 1'b0;
- gt_rxcharisk_q <= #TCQ GT_RXCHARISK;
- gt_rxdata_q <= #TCQ GT_RXDATA;
- gt_rxvalid_q <= #TCQ GT_RXVALID;
- gt_rxelecidle_q <= #TCQ GT_RXELECIDLE;
- gt_rx_status_q <= #TCQ GT_RX_STATUS;
- gt_rx_phy_status_q <= #TCQ GT_RX_PHY_STATUS;
-
- case ( state_eios_det )
-
- EIOS_DET_IDL : begin
-
- if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_COM) &&
- (gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_IDL)) begin
-
- reg_state_eios_det <= #TCQ EIOS_DET_NO_STR0;
- reg_eios_detected <= #TCQ 1'b1;
-
- end else if ((gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_COM))
- reg_state_eios_det <= #TCQ EIOS_DET_STR0;
- else
- reg_state_eios_det <= #TCQ EIOS_DET_IDL;
-
- end
-
- EIOS_DET_NO_STR0 : begin
-
- if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
- (gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL)))
- reg_state_eios_det <= #TCQ EIOS_DET_DONE;
- else
- reg_state_eios_det <= #TCQ EIOS_DET_IDL;
-
- end
-
- EIOS_DET_STR0 : begin
-
- if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
- (gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) begin
-
- reg_state_eios_det <= #TCQ EIOS_DET_STR1;
- reg_eios_detected <= #TCQ 1'b1;
- reg_symbol_after_eios <= #TCQ 1'b1;
-
- end else
- reg_state_eios_det <= #TCQ EIOS_DET_IDL;
-
- end
-
- EIOS_DET_STR1 : begin
-
- if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_IDL))
- reg_state_eios_det <= #TCQ EIOS_DET_DONE;
- else
- reg_state_eios_det <= #TCQ EIOS_DET_IDL;
-
- end
-
- EIOS_DET_DONE : begin
-
- reg_state_eios_det <= #TCQ EIOS_DET_IDL;
-
- end
-
- endcase
-
- end
-
- end
- assign state_eios_det = reg_state_eios_det;
- assign eios_detected = reg_eios_detected;
- assign symbol_after_eios = reg_symbol_after_eios;
-
- // user_rxvalid generation
-
- always @(posedge USER_CLK) begin
-
- if (RESET) begin
-
- reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL;
-
- end else begin
-
- case ( state_rxvld_ei )
-
- USER_RXVLD_IDL : begin
-
- if (eios_detected)
- reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI;
- else
- reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL;
-
- end
-
- USER_RXVLD_EI : begin
-
- if (!gt_rxvalid_q)
- reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB0;
- else if (rxvld_fallback == 4'b1111)
- reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL;
- else
- reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI;
-
- end
-
- USER_RXVLD_EI_DB0 : begin
-
- if (gt_rxvalid_q)
- reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB1;
- else
- reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB0;
-
- end
-
- USER_RXVLD_EI_DB1 : begin
-
- if (rxvld_count > CLK_COR_MIN_LAT)
- reg_state_rxvld_ei <= #TCQ USER_RXVLD_IDL;
- else
- reg_state_rxvld_ei <= #TCQ USER_RXVLD_EI_DB1;
-
- end
-
- endcase
-
- end
-
- end
- assign state_rxvld_ei = reg_state_rxvld_ei;
-
- // RxValid counter
-
- always @(posedge USER_CLK) begin
-
- if (RESET) begin
-
- reg_rxvld_count <= #TCQ 5'b00000;
-
- end else begin
-
- if ((gt_rxvalid_q) && (state_rxvld_ei == USER_RXVLD_EI_DB1))
- reg_rxvld_count <= #TCQ reg_rxvld_count + 1'b1;
- else
- reg_rxvld_count <= #TCQ 5'b00000;
-
- end
-
- end
- assign rxvld_count = reg_rxvld_count;
-
- // RxValid fallback
-
- always @(posedge USER_CLK) begin
-
- if (RESET) begin
-
- reg_rxvld_fallback <= #TCQ 4'b0000;
-
- end else begin
-
- if (state_rxvld_ei == USER_RXVLD_EI)
- reg_rxvld_fallback <= #TCQ reg_rxvld_fallback + 1'b1;
- else
- reg_rxvld_fallback <= #TCQ 4'b0000;
-
- end
-
- end
- assign rxvld_fallback = reg_rxvld_fallback;
-
- // Delay pipe_rx_elec_idle
-
- SRL16E #(.INIT(0)) rx_elec_idle_delay (.Q(USER_RXELECIDLE),
- .D(gt_rxelecidle_q),
- .CLK(USER_CLK),
- .CE(1'b1), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));
-
- assign USER_RXVALID = (state_rxvld_ei == USER_RXVLD_IDL) ? gt_rxvalid_q : 1'b0;
- assign USER_RXCHARISK[0] = USER_RXVALID ? gt_rxcharisk_q[0] : 1'b0;
- assign USER_RXCHARISK[1] = (USER_RXVALID && !symbol_after_eios) ? gt_rxcharisk_q[1] : 1'b0;
- assign USER_RXDATA = gt_rxdata_q;
- assign USER_RX_STATUS = (state_rxvld_ei == USER_RXVLD_IDL) ? gt_rx_status_q : 3'b000;
- assign USER_RX_PHY_STATUS = gt_rx_phy_status_q;
-
-endmodule
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_reset_delay_v6.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_reset_delay_v6.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_reset_delay_v6.v (nonexistent)
@@ -1,104 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : pcie_reset_delay_v6.v
-//--
-//-- Description: sys_reset_n delay (20ms) for Virtex6 PCIe Block
-//--
-//--
-//--
-//--------------------------------------------------------------------------------
-
-`timescale 1ns/1ns
-
-module pcie_reset_delay_v6 # (
-
- parameter PL_FAST_TRAIN = "FALSE",
- parameter REF_CLK_FREQ = 0 // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
-
-)
-(
-
- input wire ref_clk,
- input wire sys_reset_n,
- output delayed_sys_reset_n
-
-);
-
- parameter TCQ = 1;
-
- localparam TBIT = (PL_FAST_TRAIN == "FALSE") ? ((REF_CLK_FREQ == 1) ? 20: (REF_CLK_FREQ == 0) ? 20 : 21) : 2;
-
- reg [7:0] reg_count_7_0;
- reg [7:0] reg_count_15_8;
- reg [7:0] reg_count_23_16;
- wire [23:0] concat_count;
-
- assign concat_count = {reg_count_23_16, reg_count_15_8, reg_count_7_0};
-
- always @(posedge ref_clk or negedge sys_reset_n) begin
-
- if (!sys_reset_n) begin
-
- reg_count_7_0 <= #TCQ 8'h0;
- reg_count_15_8 <= #TCQ 8'h0;
- reg_count_23_16 <= #TCQ 8'h0;
-
- end else begin
-
- if (delayed_sys_reset_n != 1'b1) begin
-
- reg_count_7_0 <= #TCQ reg_count_7_0 + 1'b1;
- reg_count_15_8 <= #TCQ (reg_count_7_0 == 8'hff)? reg_count_15_8 + 1'b1 : reg_count_15_8 ;
- reg_count_23_16 <= #TCQ ((reg_count_15_8 == 8'hff) & (reg_count_7_0 == 8'hff)) ? reg_count_23_16 + 1'b1 : reg_count_23_16;
-
- end
-
- end
-
- end
-
- assign delayed_sys_reset_n = concat_count[TBIT];
-
-endmodule
-
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_gtx_v6.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_gtx_v6.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_gtx_v6.v (nonexistent)
@@ -1,477 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : pcie_gtx_v6.v
-//-- Description: GTX module for Virtex6 PCIe Block
-//--
-//--
-//--
-//--------------------------------------------------------------------------------
-
-`timescale 1ns/1ns
-
-module pcie_gtx_v6 #
-(
- parameter NO_OF_LANES = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
- parameter LINK_CAP_MAX_LINK_SPEED = 4'h1, // 1 - Gen1, 2 - Gen2
- parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
- parameter PL_FAST_TRAIN = "FALSE"
-)
-(
- // Pipe Per-Link Signals
- input wire pipe_tx_rcvr_det ,
- input wire pipe_tx_reset ,
- input wire pipe_tx_rate ,
- input wire pipe_tx_deemph ,
- input wire [2:0] pipe_tx_margin ,
- input wire pipe_tx_swing ,
-
- // Pipe Per-Lane Signals - Lane 0
- output wire [ 1:0] pipe_rx0_char_is_k ,
- output wire [15:0] pipe_rx0_data ,
- output wire pipe_rx0_valid ,
- output wire pipe_rx0_chanisaligned ,
- output wire [ 2:0] pipe_rx0_status ,
- output wire pipe_rx0_phy_status ,
- output wire pipe_rx0_elec_idle ,
- input wire pipe_rx0_polarity ,
- input wire pipe_tx0_compliance ,
- input wire [ 1:0] pipe_tx0_char_is_k ,
- input wire [15:0] pipe_tx0_data ,
- input wire pipe_tx0_elec_idle ,
- input wire [ 1:0] pipe_tx0_powerdown ,
-
- // Pipe Per-Lane Signals - Lane 1
- output wire [ 1:0] pipe_rx1_char_is_k ,
- output wire [15:0] pipe_rx1_data ,
- output wire pipe_rx1_valid ,
- output wire pipe_rx1_chanisaligned ,
- output wire [ 2:0] pipe_rx1_status ,
- output wire pipe_rx1_phy_status ,
- output wire pipe_rx1_elec_idle ,
- input wire pipe_rx1_polarity ,
- input wire pipe_tx1_compliance ,
- input wire [ 1:0] pipe_tx1_char_is_k ,
- input wire [15:0] pipe_tx1_data ,
- input wire pipe_tx1_elec_idle ,
- input wire [ 1:0] pipe_tx1_powerdown ,
-
- // Pipe Per-Lane Signals - Lane 2
- output wire [ 1:0] pipe_rx2_char_is_k ,
- output wire [15:0] pipe_rx2_data ,
- output wire pipe_rx2_valid ,
- output wire pipe_rx2_chanisaligned ,
- output wire [ 2:0] pipe_rx2_status ,
- output wire pipe_rx2_phy_status ,
- output wire pipe_rx2_elec_idle ,
- input wire pipe_rx2_polarity ,
- input wire pipe_tx2_compliance ,
- input wire [ 1:0] pipe_tx2_char_is_k ,
- input wire [15:0] pipe_tx2_data ,
- input wire pipe_tx2_elec_idle ,
- input wire [ 1:0] pipe_tx2_powerdown ,
-
- // Pipe Per-Lane Signals - Lane 3
- output wire [ 1:0] pipe_rx3_char_is_k ,
- output wire [15:0] pipe_rx3_data ,
- output wire pipe_rx3_valid ,
- output wire pipe_rx3_chanisaligned ,
- output wire [ 2:0] pipe_rx3_status ,
- output wire pipe_rx3_phy_status ,
- output wire pipe_rx3_elec_idle ,
- input wire pipe_rx3_polarity ,
- input wire pipe_tx3_compliance ,
- input wire [ 1:0] pipe_tx3_char_is_k ,
- input wire [15:0] pipe_tx3_data ,
- input wire pipe_tx3_elec_idle ,
- input wire [ 1:0] pipe_tx3_powerdown ,
-
- // Pipe Per-Lane Signals - Lane 4
- output wire [ 1:0] pipe_rx4_char_is_k ,
- output wire [15:0] pipe_rx4_data ,
- output wire pipe_rx4_valid ,
- output wire pipe_rx4_chanisaligned ,
- output wire [ 2:0] pipe_rx4_status ,
- output wire pipe_rx4_phy_status ,
- output wire pipe_rx4_elec_idle ,
- input wire pipe_rx4_polarity ,
- input wire pipe_tx4_compliance ,
- input wire [ 1:0] pipe_tx4_char_is_k ,
- input wire [15:0] pipe_tx4_data ,
- input wire pipe_tx4_elec_idle ,
- input wire [ 1:0] pipe_tx4_powerdown ,
-
- // Pipe Per-Lane Signals - Lane 5
- output wire [ 1:0] pipe_rx5_char_is_k ,
- output wire [15:0] pipe_rx5_data ,
- output wire pipe_rx5_valid ,
- output wire pipe_rx5_chanisaligned ,
- output wire [ 2:0] pipe_rx5_status ,
- output wire pipe_rx5_phy_status ,
- output wire pipe_rx5_elec_idle ,
- input wire pipe_rx5_polarity ,
- input wire pipe_tx5_compliance ,
- input wire [ 1:0] pipe_tx5_char_is_k ,
- input wire [15:0] pipe_tx5_data ,
- input wire pipe_tx5_elec_idle ,
- input wire [ 1:0] pipe_tx5_powerdown ,
-
- // Pipe Per-Lane Signals - Lane 6
- output wire [ 1:0] pipe_rx6_char_is_k ,
- output wire [15:0] pipe_rx6_data ,
- output wire pipe_rx6_valid ,
- output wire pipe_rx6_chanisaligned ,
- output wire [ 2:0] pipe_rx6_status ,
- output wire pipe_rx6_phy_status ,
- output wire pipe_rx6_elec_idle ,
- input wire pipe_rx6_polarity ,
- input wire pipe_tx6_compliance ,
- input wire [ 1:0] pipe_tx6_char_is_k ,
- input wire [15:0] pipe_tx6_data ,
- input wire pipe_tx6_elec_idle ,
- input wire [ 1:0] pipe_tx6_powerdown ,
-
- // Pipe Per-Lane Signals - Lane 7
- output wire [ 1:0] pipe_rx7_char_is_k ,
- output wire [15:0] pipe_rx7_data ,
- output wire pipe_rx7_valid ,
- output wire pipe_rx7_chanisaligned ,
- output wire [ 2:0] pipe_rx7_status ,
- output wire pipe_rx7_phy_status ,
- output wire pipe_rx7_elec_idle ,
- input wire pipe_rx7_polarity ,
- input wire pipe_tx7_compliance ,
- input wire [ 1:0] pipe_tx7_char_is_k ,
- input wire [15:0] pipe_tx7_data ,
- input wire pipe_tx7_elec_idle ,
- input wire [ 1:0] pipe_tx7_powerdown ,
-
- // PCI Express signals
- output wire [ (NO_OF_LANES-1):0] pci_exp_txn ,
- output wire [ (NO_OF_LANES-1):0] pci_exp_txp ,
- input wire [ (NO_OF_LANES-1):0] pci_exp_rxn ,
- input wire [ (NO_OF_LANES-1):0] pci_exp_rxp ,
-
- // Non PIPE signals
- input wire sys_clk ,
- input wire sys_rst_n ,
- input wire pipe_clk ,
- input wire clock_locked ,
-
- output wire gt_pll_lock ,
- input wire [ 5:0] pl_ltssm_state ,
- output reg phy_rdy_n
-);
-
- parameter TCQ = 1; // clock to out delay model
-
- wire [ 7:0] gt_rx_phy_status_wire ;
- wire [ 7:0] gt_rxchanisaligned_wire ;
- wire [127:0] gt_rx_data_k_wire ;
- wire [127:0] gt_rx_data_wire ;
- wire [ 7:0] gt_rx_elec_idle_wire ;
- wire [ 23:0] gt_rx_status_wire ;
- wire [ 7:0] gt_rx_valid_wire ;
- wire [ 7:0] gt_rx_polarity ;
- wire [ 15:0] gt_power_down ;
- wire [ 7:0] gt_tx_char_disp_mode ;
- wire [ 15:0] gt_tx_data_k ;
- wire [127:0] gt_tx_data ;
- wire gt_tx_detect_rx_loopback ;
- wire [ 7:0] gt_tx_elec_idle ;
- wire [ 7:0] gt_rx_elec_idle_reset ;
-
- wire [NO_OF_LANES-1:0] plllkdet;
- wire RxResetDone;
- wire plm_in_l0 = (pl_ltssm_state == 6'h16);
-
- reg local_pcs_reset;
- reg local_pcs_reset_done;
- reg [3:0] cnt_local_pcs_reset;
- reg [4:0] phy_rdy_pre_cnt;
-
-gtx_wrapper_v6 #(
-
- .NO_OF_LANES(NO_OF_LANES),
- .REF_CLK_FREQ(REF_CLK_FREQ),
- .PL_FAST_TRAIN(PL_FAST_TRAIN)
-
-)
-gtx_v6_i (
-
- // TX
-
- .TX(pci_exp_txp[((NO_OF_LANES)-1):0]),
- .TX_(pci_exp_txn[((NO_OF_LANES)-1):0]),
- .TxData(gt_tx_data[((16*NO_OF_LANES)-1):0]),
- .TxDataK(gt_tx_data_k[((2*NO_OF_LANES)-1):0]),
- .TxElecIdle(gt_tx_elec_idle[((NO_OF_LANES)-1):0]),
- .TxCompliance(gt_tx_char_disp_mode[((NO_OF_LANES)-1):0]),
-
- // RX
-
- .RX(pci_exp_rxp[((NO_OF_LANES)-1):0]),
- .RX_(pci_exp_rxn[((NO_OF_LANES)-1):0]),
- .RxData(gt_rx_data_wire[((16*NO_OF_LANES)-1):0]),
- .RxDataK(gt_rx_data_k_wire[((2*NO_OF_LANES)-1):0]),
- .RxPolarity(gt_rx_polarity[((NO_OF_LANES)-1):0]),
- .RxValid(gt_rx_valid_wire[((NO_OF_LANES)-1):0]),
- .RxElecIdle(gt_rx_elec_idle_wire[((NO_OF_LANES)-1):0]),
- .RxStatus(gt_rx_status_wire[((3*NO_OF_LANES)-1):0]),
-
- // other
- .GTRefClkout(),
- .RxPLLLkDet(plllkdet),
- .ChanIsAligned(gt_rxchanisaligned_wire[((NO_OF_LANES)-1):0]),
- .TxDetectRx(gt_tx_detect_rx_loopback),
- .PhyStatus(gt_rx_phy_status_wire[((NO_OF_LANES)-1):0]),
- .TXPdownAsynch(~clock_locked),
- .PowerDown(gt_power_down[((2*NO_OF_LANES)-1):0]),
- .Rate(pipe_tx_rate),
- .Reset_n(clock_locked),
- .GTReset_n(sys_rst_n),
- .PCLK(pipe_clk),
- .REFCLK(sys_clk),
- .TxDeemph(pipe_tx_deemph),
- .TxMargin(pipe_tx_margin[2]),
- .TxSwing(pipe_tx_swing),
- .local_pcs_reset(local_pcs_reset),
- .RxResetDone(RxResetDone),
- .SyncDone(SyncDone)
-);
-
-assign pipe_rx0_phy_status = gt_rx_phy_status_wire[0] ;
-assign pipe_rx1_phy_status = (NO_OF_LANES >= 2 ) ? gt_rx_phy_status_wire[1] : 1'b0;
-assign pipe_rx2_phy_status = (NO_OF_LANES >= 4 ) ? gt_rx_phy_status_wire[2] : 1'b0;
-assign pipe_rx3_phy_status = (NO_OF_LANES >= 4 ) ? gt_rx_phy_status_wire[3] : 1'b0;
-assign pipe_rx4_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[4] : 1'b0;
-assign pipe_rx5_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[5] : 1'b0;
-assign pipe_rx6_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[6] : 1'b0;
-assign pipe_rx7_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[7] : 1'b0;
-
-assign pipe_rx0_chanisaligned = gt_rxchanisaligned_wire[0];
-assign pipe_rx1_chanisaligned = (NO_OF_LANES >= 2 ) ? gt_rxchanisaligned_wire[1] : 1'b0 ;
-assign pipe_rx2_chanisaligned = (NO_OF_LANES >= 4 ) ? gt_rxchanisaligned_wire[2] : 1'b0 ;
-assign pipe_rx3_chanisaligned = (NO_OF_LANES >= 4 ) ? gt_rxchanisaligned_wire[3] : 1'b0 ;
-assign pipe_rx4_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[4] : 1'b0 ;
-assign pipe_rx5_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[5] : 1'b0 ;
-assign pipe_rx6_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[6] : 1'b0 ;
-assign pipe_rx7_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[7] : 1'b0 ;
-
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-
-assign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]};
-assign pipe_rx1_char_is_k = (NO_OF_LANES >= 2 ) ? {gt_rx_data_k_wire[3], gt_rx_data_k_wire[2]} : 2'b0 ;
-assign pipe_rx2_char_is_k = (NO_OF_LANES >= 4 ) ? {gt_rx_data_k_wire[5], gt_rx_data_k_wire[4]} : 2'b0 ;
-assign pipe_rx3_char_is_k = (NO_OF_LANES >= 4 ) ? {gt_rx_data_k_wire[7], gt_rx_data_k_wire[6]} : 2'b0 ;
-assign pipe_rx4_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[9], gt_rx_data_k_wire[8]} : 2'b0 ;
-assign pipe_rx5_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[11], gt_rx_data_k_wire[10]} : 2'b0 ;
-assign pipe_rx6_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[13], gt_rx_data_k_wire[12]} : 2'b0 ;
-assign pipe_rx7_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[15], gt_rx_data_k_wire[14]} : 2'b0 ;
-
-assign pipe_rx0_data = {gt_rx_data_wire[ 15: 8], gt_rx_data_wire[ 7: 0]};
-assign pipe_rx1_data = (NO_OF_LANES >= 2 ) ? {gt_rx_data_wire[31:24], gt_rx_data_wire[23:16]} : 16'h0 ;
-assign pipe_rx2_data = (NO_OF_LANES >= 4 ) ? {gt_rx_data_wire[47:40], gt_rx_data_wire[39:32]} : 16'h0 ;
-assign pipe_rx3_data = (NO_OF_LANES >= 4 ) ? {gt_rx_data_wire[63:56], gt_rx_data_wire[55:48]} : 16'h0 ;
-assign pipe_rx4_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[79:72], gt_rx_data_wire[71:64]} : 16'h0 ;
-assign pipe_rx5_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[95:88], gt_rx_data_wire[87:80]} : 16'h0 ;
-assign pipe_rx6_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[111:104], gt_rx_data_wire[103:96]} : 16'h0 ;
-assign pipe_rx7_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[127:120], gt_rx_data_wire[119:112]} : 16'h0 ;
-
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-
-assign pipe_rx0_elec_idle = gt_rx_elec_idle_wire[0];
-assign pipe_rx1_elec_idle = (NO_OF_LANES >= 2 ) ? gt_rx_elec_idle_wire[1] : 1'b1 ;
-assign pipe_rx2_elec_idle = (NO_OF_LANES >= 4 ) ? gt_rx_elec_idle_wire[2] : 1'b1 ;
-assign pipe_rx3_elec_idle = (NO_OF_LANES >= 4 ) ? gt_rx_elec_idle_wire[3] : 1'b1 ;
-assign pipe_rx4_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[4] : 1'b1 ;
-assign pipe_rx5_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[5] : 1'b1 ;
-assign pipe_rx6_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[6] : 1'b1 ;
-assign pipe_rx7_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[7] : 1'b1 ;
-
-assign pipe_rx0_status = gt_rx_status_wire[ 2: 0];
-assign pipe_rx1_status = (NO_OF_LANES >= 2 ) ? gt_rx_status_wire[ 5: 3] : 3'b0 ;
-assign pipe_rx2_status = (NO_OF_LANES >= 4 ) ? gt_rx_status_wire[ 8: 6] : 3'b0 ;
-assign pipe_rx3_status = (NO_OF_LANES >= 4 ) ? gt_rx_status_wire[11: 9] : 3'b0 ;
-assign pipe_rx4_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[14:12] : 3'b0 ;
-assign pipe_rx5_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[17:15] : 3'b0 ;
-assign pipe_rx6_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[20:18] : 3'b0 ;
-assign pipe_rx7_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[23:21] : 3'b0 ;
-
-assign pipe_rx0_valid = gt_rx_valid_wire[0];
-assign pipe_rx1_valid = (NO_OF_LANES >= 2 ) ? gt_rx_valid_wire[1] : 1'b0 ;
-assign pipe_rx2_valid = (NO_OF_LANES >= 4 ) ? gt_rx_valid_wire[2] : 1'b0 ;
-assign pipe_rx3_valid = (NO_OF_LANES >= 4 ) ? gt_rx_valid_wire[3] : 1'b0 ;
-assign pipe_rx4_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[4] : 1'b0 ;
-assign pipe_rx5_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[5] : 1'b0 ;
-assign pipe_rx6_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[6] : 1'b0 ;
-assign pipe_rx7_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[7] : 1'b0 ;
-
-assign gt_rx_polarity[0] = pipe_rx0_polarity;
-assign gt_rx_polarity[1] = pipe_rx1_polarity;
-assign gt_rx_polarity[2] = pipe_rx2_polarity;
-assign gt_rx_polarity[3] = pipe_rx3_polarity;
-assign gt_rx_polarity[4] = pipe_rx4_polarity;
-assign gt_rx_polarity[5] = pipe_rx5_polarity;
-assign gt_rx_polarity[6] = pipe_rx6_polarity;
-assign gt_rx_polarity[7] = pipe_rx7_polarity;
-
-assign gt_power_down[ 1: 0] = pipe_tx0_powerdown;
-assign gt_power_down[ 3: 2] = pipe_tx1_powerdown;
-assign gt_power_down[ 5: 4] = pipe_tx2_powerdown;
-assign gt_power_down[ 7: 6] = pipe_tx3_powerdown;
-assign gt_power_down[ 9: 8] = pipe_tx4_powerdown;
-assign gt_power_down[11:10] = pipe_tx5_powerdown;
-assign gt_power_down[13:12] = pipe_tx6_powerdown;
-assign gt_power_down[15:14] = pipe_tx7_powerdown;
-
-assign gt_tx_char_disp_mode = {pipe_tx7_compliance,
- pipe_tx6_compliance,
- pipe_tx5_compliance,
- pipe_tx4_compliance,
- pipe_tx3_compliance,
- pipe_tx2_compliance,
- pipe_tx1_compliance,
- pipe_tx0_compliance};
-
-
-assign gt_tx_data_k = {pipe_tx7_char_is_k,
- pipe_tx6_char_is_k,
- pipe_tx5_char_is_k,
- pipe_tx4_char_is_k,
- pipe_tx3_char_is_k,
- pipe_tx2_char_is_k,
- pipe_tx1_char_is_k,
- pipe_tx0_char_is_k};
-
-assign gt_tx_data = {pipe_tx7_data,
- pipe_tx6_data,
- pipe_tx5_data,
- pipe_tx4_data,
- pipe_tx3_data,
- pipe_tx2_data,
- pipe_tx1_data,
- pipe_tx0_data};
-
-assign gt_tx_detect_rx_loopback = pipe_tx_rcvr_det;
-
-assign gt_tx_elec_idle = {pipe_tx7_elec_idle,
- pipe_tx6_elec_idle,
- pipe_tx5_elec_idle,
- pipe_tx4_elec_idle,
- pipe_tx3_elec_idle,
- pipe_tx2_elec_idle,
- pipe_tx1_elec_idle,
- pipe_tx0_elec_idle};
-
-assign gt_pll_lock = &plllkdet[NO_OF_LANES-1:0] | ~phy_rdy_pre_cnt[4];
-
-// Asserted after all workarounds have completed.
-
-always @(posedge pipe_clk or negedge clock_locked) begin
-
- if (!clock_locked) begin
-
- phy_rdy_n <= #TCQ 1'b1;
-
- end else begin
-
- if (~&plllkdet[NO_OF_LANES-1:0])
- phy_rdy_n <= #TCQ 1'b1;
- else if (local_pcs_reset_done && RxResetDone && phy_rdy_n && SyncDone)
- phy_rdy_n <= #TCQ 1'b0;
-
- end
-
-end
-
-// Handle the warm reset case, where sys_rst_n is asseted when
-// phy_rdy_n is asserted. phy_rdy_n is to be de-asserted
-// before gt_pll_lock is de-asserted so that synnchronous
-// logic see reset de-asset before clock is lost.
-
-always @(posedge pipe_clk or negedge clock_locked) begin
-
- if (!clock_locked) begin
-
- phy_rdy_pre_cnt <= #TCQ 5'b11111;
-
- end else begin
-
- if (gt_pll_lock && phy_rdy_n)
- phy_rdy_pre_cnt <= #TCQ phy_rdy_pre_cnt + 1'b1;
-
- end
-
-end
-
-always @(posedge pipe_clk or negedge clock_locked) begin
-
- if (!clock_locked) begin
-
- cnt_local_pcs_reset <= #TCQ 4'hF;
- local_pcs_reset <= #TCQ 1'b0;
- local_pcs_reset_done <= #TCQ 1'b0;
-
- end else begin
-
- if ((local_pcs_reset == 1'b0) && (cnt_local_pcs_reset == 4'hF))
- local_pcs_reset <= #TCQ 1'b1;
- else if ((local_pcs_reset == 1'b1) && (cnt_local_pcs_reset != 4'h0)) begin
- local_pcs_reset <= #TCQ 1'b1;
- cnt_local_pcs_reset <= #TCQ cnt_local_pcs_reset - 1'b1;
- end else if ((local_pcs_reset == 1'b1) && (cnt_local_pcs_reset == 4'h0)) begin
- local_pcs_reset <= #TCQ 1'b0;
- local_pcs_reset_done <= #TCQ 1'b1;
- end
-
- end
-
-end
-
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
-
-endmodule
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_wrapper_v6.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_wrapper_v6.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/gtx_wrapper_v6.v (nonexistent)
@@ -1,579 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : gtx_wrapper_v6.v
-//-- Description: GTX module for Virtex6 PCIe Block
-//--
-//--
-//--
-//--------------------------------------------------------------------------------
-
-`timescale 1ns/1ns
-
-module gtx_wrapper_v6 (
-
- // TX
- TX,
- TX_,
- TxData,
- TxDataK,
- TxElecIdle,
- TxCompliance,
-
- // RX
- RX,
- RX_,
- RxData,
- RxDataK,
- RxPolarity,
- RxValid,
- RxElecIdle,
- RxStatus,
-
- // other
- GTRefClkout,
- RxPLLLkDet,
- TxDetectRx,
- PhyStatus,
- TXPdownAsynch,
- PowerDown,
- Rate,
- Reset_n,
- GTReset_n,
- PCLK,
- REFCLK,
- TxDeemph,
- TxMargin,
- TxSwing,
- ChanIsAligned,
- local_pcs_reset,
- RxResetDone,
- SyncDone
-
- );
-
- parameter NO_OF_LANES = 1;
- parameter REF_CLK_FREQ = 0;
- parameter PL_FAST_TRAIN = "FALSE";
-
- localparam GTX_PLL_DIVSEL_FB = (REF_CLK_FREQ == 0) ? 5 :
- (REF_CLK_FREQ == 1) ? 4 :
- (REF_CLK_FREQ == 2) ? 2 : 0;
- localparam SIMULATION = (PL_FAST_TRAIN == "TRUE") ? 1 : 0;
-
- localparam RXPLL_CP_CFG = (REF_CLK_FREQ == 0) ? 8'h09 :
- (REF_CLK_FREQ == 1) ? 8'h09 :
- (REF_CLK_FREQ == 2) ? 8'h0D : 8'h09;
-
- localparam TXPLL_CP_CFG = (REF_CLK_FREQ == 0) ? 8'h09 :
- (REF_CLK_FREQ == 1) ? 8'h09 :
- (REF_CLK_FREQ == 2) ? 8'h0D : 8'h09;
-
- localparam RX_CLK25_DIVIDER = (REF_CLK_FREQ == 0) ? 4 :
- (REF_CLK_FREQ == 1) ? 5 :
- (REF_CLK_FREQ == 2) ? 10 : 10 ;
-
- localparam TX_CLK25_DIVIDER = (REF_CLK_FREQ == 0) ? 4 :
- (REF_CLK_FREQ == 1) ? 5 :
- (REF_CLK_FREQ == 2) ? 10 : 10 ;
-
- // TX
- output [NO_OF_LANES-1:0] TX;
- output [NO_OF_LANES-1:0] TX_;
- input [(NO_OF_LANES*16)-1:0] TxData;
- input [(NO_OF_LANES*2)-1:0] TxDataK;
- input [NO_OF_LANES-1:0] TxElecIdle;
- input [NO_OF_LANES-1:0] TxCompliance;
-
- // RX
- input [NO_OF_LANES-1:0] RX;
- input [NO_OF_LANES-1:0] RX_;
- output [(NO_OF_LANES*16)-1:0] RxData;
- output [(NO_OF_LANES*2)-1:0] RxDataK;
- input [NO_OF_LANES-1:0] RxPolarity;
- output [NO_OF_LANES-1:0] RxValid;
- output [NO_OF_LANES-1:0] RxElecIdle;
- output [(NO_OF_LANES*3)-1:0] RxStatus;
-
- // other
- output [NO_OF_LANES-1:0] GTRefClkout;
- output [NO_OF_LANES-1:0] RxPLLLkDet;
- input TxDetectRx;
- output [NO_OF_LANES-1:0] PhyStatus;
- input PCLK;
- output [NO_OF_LANES-1:0] ChanIsAligned;
- input TXPdownAsynch;
-
- input [(NO_OF_LANES*2)-1:0] PowerDown;
- input Rate;
- input Reset_n;
- input GTReset_n;
- input REFCLK;
- input TxDeemph;
- input TxMargin;
- input TxSwing;
- input local_pcs_reset;
- output RxResetDone;
- output SyncDone;
-
- genvar i;
-
- // dummy signals to avoid port mismatch with DUAL_GTX
- wire [15:0] RxData_dummy;
- wire [1:0] RxDataK_dummy;
- wire [15:0] TxData_dummy;
- wire [1:0] TxDataK_dummy;
-
- // inputs
- wire [(NO_OF_LANES*16)-1:0] GTX_TxData = TxData;
- wire [(NO_OF_LANES*2)-1:0] GTX_TxDataK = TxDataK;
- wire [(NO_OF_LANES)-1:0] GTX_TxElecIdle = TxElecIdle;
- wire [(NO_OF_LANES-1):0] GTX_TxCompliance = TxCompliance;
- wire [(NO_OF_LANES)-1:0] GTX_RXP = RX[(NO_OF_LANES)-1:0];
- wire [(NO_OF_LANES)-1:0] GTX_RXN = RX_[(NO_OF_LANES)-1:0];
-
- // outputs
- wire [(NO_OF_LANES)-1:0] GTX_TXP;
- wire [(NO_OF_LANES)-1:0] GTX_TXN;
- wire [(NO_OF_LANES*16)-1:0] GTX_RxData;
- wire [(NO_OF_LANES*2)-1:0] GTX_RxDataK;
- wire [(NO_OF_LANES)-1:0] GTX_RxPolarity = RxPolarity ;
- wire [(NO_OF_LANES)-1:0] GTX_RxValid;
- wire [(NO_OF_LANES)-1:0] GTX_RxElecIdle;
- wire [(NO_OF_LANES-1):0] GTX_RxResetDone;
- wire [(NO_OF_LANES*3)-1:0] GTX_RxChbondLevel;
- wire [(NO_OF_LANES*3)-1:0] GTX_RxStatus;
-
-
- wire [3:0] RXCHBOND [NO_OF_LANES+1:0];
- wire [3:0] TXBYPASS8B10B = 4'b0000;
- wire RXDEC8B10BUSE = 1'b1;
- wire [NO_OF_LANES-1:0] GTX_PhyStatus;
- wire RESETDONE [NO_OF_LANES-1:0];
- wire REFCLK;
- wire GTXRESET = 1'b0;
-
- wire [NO_OF_LANES-1:0] SYNC_DONE;
- wire [NO_OF_LANES-1:0] OUT_DIV_RESET;
- wire [NO_OF_LANES-1:0] PCS_RESET;
- wire [NO_OF_LANES-1:0] TXENPMAPHASEALIGN;
- wire [NO_OF_LANES-1:0] TXPMASETPHASE;
- wire [NO_OF_LANES-1:0] TXRESETDONE;
- wire [NO_OF_LANES-1:0] TXRATEDONE;
- wire [NO_OF_LANES-1:0] PHYSTATUS;
- wire [NO_OF_LANES-1:0] RXVALID;
- wire [NO_OF_LANES-1:0] RATE_CLK_SEL;
-
-
- reg [(NO_OF_LANES-1):0] GTX_RxResetDone_q;
- reg [(NO_OF_LANES-1):0] TXRESETDONE_q;
-
- wire [NO_OF_LANES-1:0] RxValid;
-
- assign RxResetDone = &(GTX_RxResetDone_q[(NO_OF_LANES)-1:0]);
- assign TX[(NO_OF_LANES)-1:0] = GTX_TXP[(NO_OF_LANES)-1:0];
- assign TX_[(NO_OF_LANES)-1:0] = GTX_TXN[(NO_OF_LANES)-1:0];
- assign RXCHBOND[0] = 4'b0000;
- assign TxData_dummy = 16'b0;
- assign TxDataK_dummy = 2'b0;
- assign SyncDone = &(SYNC_DONE[(NO_OF_LANES)-1:0]);
-
- // pipeline to improve timing
- always @ (posedge PCLK) begin
-
- GTX_RxResetDone_q[(NO_OF_LANES)-1:0] <= GTX_RxResetDone[(NO_OF_LANES)-1:0];
- TXRESETDONE_q[(NO_OF_LANES)-1:0] <= TXRESETDONE[(NO_OF_LANES)-1:0];
-
- end
-
- generate
-
- for (i=0; i < NO_OF_LANES; i=i+1) begin: GTXD
-
- assign GTX_RxChbondLevel[(3*i)+2:(3*i)] = (NO_OF_LANES-(i+1));
-
-
- GTX_RX_VALID_FILTER_V6 # (
- .CLK_COR_MIN_LAT(28)
- )
- GTX_RX_VALID_FILTER (
-
- .USER_RXCHARISK ( RxDataK[(2*i)+1:2*i] ), //O
- .USER_RXDATA ( RxData[(16*i)+15:(16*i)+0] ), //O
- .USER_RXVALID ( RxValid[i] ), //O
- .USER_RXELECIDLE ( RxElecIdle[i] ), //O
- .USER_RX_STATUS ( RxStatus[(3*i)+2:(3*i)] ), //O
- .USER_RX_PHY_STATUS ( PhyStatus[i] ), //O
-
-
- .GT_RXCHARISK ( GTX_RxDataK[(2*i)+1:2*i] ), //I
- .GT_RXDATA ( GTX_RxData[(16*i)+15:(16*i)+0] ), //I
- .GT_RXVALID ( GTX_RxValid[i] ), //I
- .GT_RXELECIDLE ( GTX_RxElecIdle[i] ), //I
- .GT_RX_STATUS ( GTX_RxStatus[(3*i)+2:(3*i)] ), //I
- .GT_RX_PHY_STATUS ( PHYSTATUS[i] ),
-
- .USER_CLK ( PCLK ), //I
- .RESET ( !Reset_n ) //I
-
- );
-
- GTX_TX_SYNC_RATE_V6 # (
- .C_SIMULATION(SIMULATION)
- )
- GTX_TX_SYNC (
-
- .ENPMAPHASEALIGN ( TXENPMAPHASEALIGN[i] ), //O
- .PMASETPHASE ( TXPMASETPHASE[i] ), //O
- .SYNC_DONE ( SYNC_DONE[i] ), //O
- .OUT_DIV_RESET ( OUT_DIV_RESET[i] ), //O
- .PCS_RESET ( PCS_RESET[i] ), //O
- .USER_PHYSTATUS ( PHYSTATUS[i] ), //O
- .RATE_CLK_SEL ( RATE_CLK_SEL[i] ), //0
-
- .USER_CLK ( PCLK ), //I
- .RESET ( !Reset_n ), //I
- .RATE ( Rate ), //I
- .RATEDONE ( TXRATEDONE[i] ), //I
- .GT_PHYSTATUS ( GTX_PhyStatus[i] ), //I
- .RESETDONE ( TXRESETDONE_q[i] & GTX_RxResetDone_q[i] ), //I
-
- .DEBUG_STATUS ( ), // O
- .ENPMA_STATE_MASK ( 3'b000 ), // I
- .OUTDIV_STATE_MASK( 3'b010 ) // I
-
- );
-
- GTXE1 # (
-
- .TX_DRIVE_MODE("PIPE"),
- .TX_CLK_SOURCE("RXPLL"),
- .POWER_SAVE(10'b0000000100),
- .CM_TRIM ( 2'b01 ),
- .PMA_CDR_SCAN ( 27'h640404C ),
- .PMA_CFG( 76'h0040000040000000003 ),
- .RCV_TERM_GND ("TRUE"),
- .RCV_TERM_VTTRX ("FALSE"),
- .RX_DLYALIGN_EDGESET(5'b00010),
- .RX_DLYALIGN_LPFINC(4'b0110),
- .RX_DLYALIGN_OVRDSETTING(8'b10000000),
- .TERMINATION_CTRL(5'b10101),
- .TERMINATION_OVRD("TRUE"),
- .TX_DLYALIGN_LPFINC(4'b0110),
- .TX_DLYALIGN_OVRDSETTING(8'b10000000),
- .TXPLL_CP_CFG( TXPLL_CP_CFG ),
- .OOBDETECT_THRESHOLD( 3'b011 ),
- .RXPLL_CP_CFG ( RXPLL_CP_CFG ),
- //.TX_DETECT_RX_CFG( 14'h1832 ),
- .TX_TDCC_CFG ( 2'b11 ),
- .BIAS_CFG ( 17'h00014 ),
- .AC_CAP_DIS ( "FALSE" ),
- .DFE_CFG ( 8'b00011011 ),
- .SIM_TX_ELEC_IDLE_LEVEL("1"),
- .SIM_RECEIVER_DETECT_PASS("TRUE"),
- .RX_EN_REALIGN_RESET_BUF("TRUE"),
- .TX_IDLE_ASSERT_DELAY(3'b100), // TX-idle-set-to-idle (13 UI)
- .TX_IDLE_DEASSERT_DELAY(3'b010), // TX-idle-to-diff (7 UI)
- .CHAN_BOND_SEQ_2_CFG(5'b11111), // 5'b11111 for PCIE mode, 5'b00000 for other modes
- .CHAN_BOND_KEEP_ALIGN("TRUE"),
- .RX_IDLE_HI_CNT(4'b1000),
- .RX_IDLE_LO_CNT(4'b0000),
- .RX_EN_IDLE_RESET_BUF("TRUE"),
- .TX_DATA_WIDTH(20),
- .RX_DATA_WIDTH(20),
- .ALIGN_COMMA_WORD(1),
- .CHAN_BOND_1_MAX_SKEW(7),
- .CHAN_BOND_2_MAX_SKEW(1),
- .CHAN_BOND_SEQ_1_1(10'b0001000101), // D5.2 (end TS2)
- .CHAN_BOND_SEQ_1_2(10'b0001000101), // D5.2 (end TS2)
- .CHAN_BOND_SEQ_1_3(10'b0001000101), // D5.2 (end TS2)
- .CHAN_BOND_SEQ_1_4(10'b0110111100), // K28.5 (COM)
- .CHAN_BOND_SEQ_1_ENABLE(4'b1111), // order is 4321
- .CHAN_BOND_SEQ_2_1(10'b0100111100), // K28.1 (FTS)
- .CHAN_BOND_SEQ_2_2(10'b0100111100), // K28.1 (FTS)
- .CHAN_BOND_SEQ_2_3(10'b0110111100), // K28.5 (COM)
- .CHAN_BOND_SEQ_2_4(10'b0100111100), // K28.1 (FTS)
- .CHAN_BOND_SEQ_2_ENABLE(4'b1111), // order is 4321
- .CHAN_BOND_SEQ_2_USE("TRUE"),
- .CHAN_BOND_SEQ_LEN(4), // 1..4
- .RX_CLK25_DIVIDER(RX_CLK25_DIVIDER),
- .TX_CLK25_DIVIDER(TX_CLK25_DIVIDER),
- .CLK_COR_ADJ_LEN(1), // 1..4
- .CLK_COR_DET_LEN(1), // 1..4
- .CLK_COR_INSERT_IDLE_FLAG("FALSE"),
- .CLK_COR_KEEP_IDLE("FALSE"),
- .CLK_COR_MAX_LAT(30),
- .CLK_COR_MIN_LAT(28),
- .CLK_COR_PRECEDENCE("TRUE"),
- .CLK_CORRECT_USE("TRUE"),
- .CLK_COR_REPEAT_WAIT(0),
- .CLK_COR_SEQ_1_1(10'b0100011100), // K28.0 (SKP)
- .CLK_COR_SEQ_1_2(10'b0000000000),
- .CLK_COR_SEQ_1_3(10'b0000000000),
- .CLK_COR_SEQ_1_4(10'b0000000000),
- .CLK_COR_SEQ_1_ENABLE(4'b1111),
- .CLK_COR_SEQ_2_1(10'b0000000000),
- .CLK_COR_SEQ_2_2(10'b0000000000),
- .CLK_COR_SEQ_2_3(10'b0000000000),
- .CLK_COR_SEQ_2_4(10'b0000000000),
- .CLK_COR_SEQ_2_ENABLE(4'b1111),
- .CLK_COR_SEQ_2_USE("FALSE"),
- .COMMA_10B_ENABLE(10'b1111111111),
- .COMMA_DOUBLE("FALSE"),
- .DEC_MCOMMA_DETECT("TRUE"),
- .DEC_PCOMMA_DETECT("TRUE"),
- .DEC_VALID_COMMA_ONLY("TRUE"),
- .MCOMMA_10B_VALUE(10'b1010000011),
- .MCOMMA_DETECT("TRUE"),
- .PCI_EXPRESS_MODE("TRUE"),
- .PCOMMA_10B_VALUE(10'b0101111100),
- .PCOMMA_DETECT("TRUE"),
- .RXPLL_DIVSEL_FB(GTX_PLL_DIVSEL_FB), // 1..5, 8, 10
- .TXPLL_DIVSEL_FB(GTX_PLL_DIVSEL_FB), // 1..5, 8, 10
- .RXPLL_DIVSEL_REF(1), // 1..6, 8, 10, 12, 16, 20
- .TXPLL_DIVSEL_REF(1), // 1..6, 8, 10, 12, 16, 20
- .RXPLL_DIVSEL_OUT(2), // 1, 2, 4
- .TXPLL_DIVSEL_OUT(2), // 1, 2, 4
- .RXPLL_DIVSEL45_FB(5),
- .TXPLL_DIVSEL45_FB(5),
- .RX_BUFFER_USE("TRUE"),
- .RX_DECODE_SEQ_MATCH("TRUE"),
- .RX_LOS_INVALID_INCR(8), // power of 2: 1..128
- .RX_LOSS_OF_SYNC_FSM("FALSE"),
- .RX_LOS_THRESHOLD(128), // power of 2: 4..512
- .RX_SLIDE_MODE("AUTO"), // 00=OFF 01=AUTO 10=PCS 11=PMA
- .RX_XCLK_SEL ("RXREC"),
- .TX_BUFFER_USE("FALSE"), // Must be set to FALSE for use by PCIE
- .TX_XCLK_SEL ("TXUSR"), // Must be set to TXUSR for use by PCIE
- .TXPLL_LKDET_CFG (3'b101),
- .RX_EYE_SCANMODE (2'b00),
- .RX_EYE_OFFSET (8'h4C),
- .PMA_RX_CFG ( 25'h05ce048 ),
- .TRANS_TIME_NON_P2(8'h19), // Reduced simulation time
- .TRANS_TIME_FROM_P2(12'h03c), // Reduced simulation time
- .TRANS_TIME_TO_P2(10'h064), // Reduced simulation time
- .TRANS_TIME_RATE(8'hD7), // Reduced simulation time
- .SHOW_REALIGN_COMMA("FALSE"),
- .TX_PMADATA_OPT(1'b0), // Lockup latch between PCS and PMA
- .PMA_TX_CFG( 20'h00082 ) // Aligns posedge of USRCLK
-
- )
- GTX (
-
- .COMFINISH (),
- .COMINITDET (),
- .COMSASDET (),
- .COMWAKEDET (),
- .DADDR (),
- .DCLK (),
- .DEN (),
- .DFECLKDLYADJ (),
- .DFECLKDLYADJMON (),
- .DFEDLYOVRD ( 1'b1 ),
- .DFEEYEDACMON (),
- .DFESENSCAL (),
- .DFETAP1 (),
- .DFETAP1MONITOR (),
- .DFETAP2 (),
- .DFETAP2MONITOR (),
- .DFETAP3 (),
- .DFETAP3MONITOR (),
- .DFETAP4 (),
- .DFETAP4MONITOR (),
- .DFETAPOVRD ( 1'b1 ),
- .DI (),
- .DRDY (),
- .DRPDO (),
- .DWE (),
- .GATERXELECIDLE ( 1'b0 ),
- .GREFCLKRX (),
- .GREFCLKTX (),
- .GTXRXRESET ( ~GTReset_n ),
- .GTXTEST ( {11'b10000000000,OUT_DIV_RESET[i],1'b0} ),
- .GTXTXRESET ( ~GTReset_n ),
- .LOOPBACK ( 3'b000 ),
- .MGTREFCLKFAB (),
- .MGTREFCLKRX ( {1'b0,REFCLK} ),
- .MGTREFCLKTX ( {1'b0,REFCLK} ),
- .NORTHREFCLKRX (),
- .NORTHREFCLKTX (),
- .PHYSTATUS ( GTX_PhyStatus[i] ),
- .PLLRXRESET ( 1'b0 ),
- .PLLTXRESET ( 1'b0 ),
- .PRBSCNTRESET ( 1'b0 ),
- .RXBUFRESET ( 1'b0 ),
- .RXBUFSTATUS (),
- .RXBYTEISALIGNED (),
- .RXBYTEREALIGN (),
- .RXCDRRESET ( 1'b0 ),
- .RXCHANBONDSEQ (),
- .RXCHANISALIGNED ( ChanIsAligned[i] ),
- .RXCHANREALIGN (),
- .RXCHARISCOMMA (),
- .RXCHARISK ( {RxDataK_dummy[1:0], GTX_RxDataK[(2*i)+1:2*i]} ),
- .RXCHBONDI ( RXCHBOND[i] ),
- .RXCHBONDLEVEL ( GTX_RxChbondLevel[(3*i)+2:(3*i)] ),
- .RXCHBONDMASTER ( (i == 0) ),
- .RXCHBONDO ( RXCHBOND[i+1] ),
- .RXCHBONDSLAVE ( (i > 0) ),
- .RXCLKCORCNT (),
- .RXCOMMADET (),
- .RXCOMMADETUSE ( 1'b1 ),
- .RXDATA ( {RxData_dummy[15:0],GTX_RxData[(16*i)+15:(16*i)+0]} ),
- .RXDATAVALID (),
- .RXDEC8B10BUSE ( RXDEC8B10BUSE ),
- .RXDISPERR (),
- .RXDLYALIGNDISABLE ( 1'b1),
- .RXELECIDLE ( GTX_RxElecIdle[i] ),
- .RXENCHANSYNC ( 1'b1 ),
- .RXENMCOMMAALIGN ( 1'b1 ),
- .RXENPCOMMAALIGN ( 1'b1 ),
- .RXENPMAPHASEALIGN ( 1'b0 ),
- .RXENPRBSTST ( 3'b0 ),
- .RXENSAMPLEALIGN ( 1'b0 ),
- .RXEQMIX ( 10'b0110000110 ),
- .RXGEARBOXSLIP ( 1'b0 ),
- .RXHEADER (),
- .RXHEADERVALID (),
- .RXLOSSOFSYNC (),
- .RXN ( GTX_RXN[i] ),
- .RXNOTINTABLE (),
- .RXOVERSAMPLEERR (),
- .RXP ( GTX_RXP[i] ),
- .RXPLLLKDET ( RxPLLLkDet[i] ),
- .RXPLLLKDETEN ( 1'b1 ),
- .RXPLLPOWERDOWN ( 1'b0 ),
- .RXPLLREFSELDY ( 3'b000 ),
- .RXPMASETPHASE ( 1'b0 ),
- .RXPOLARITY ( GTX_RxPolarity[i] ),
- .RXPOWERDOWN ( PowerDown[(2*i)+1:(2*i)] ),
- .RXPRBSERR (),
- .RXRATE ( {1'b1, Rate} ),
- .RXRATEDONE ( ),
- .RXRECCLK ( RXRECCLK ),
- .RXRECCLKPCS ( ),
- .RXRESET ( ~GTReset_n | local_pcs_reset | PCS_RESET[i] ),
- .RXRESETDONE ( GTX_RxResetDone[i] ),
- .RXRUNDISP (),
- .RXSLIDE ( 1'b0 ),
- .RXSTARTOFSEQ (),
- .RXSTATUS ( GTX_RxStatus[(3*i)+2:(3*i)] ),
- .RXUSRCLK ( PCLK ),
- .RXUSRCLK2 ( PCLK ),
- .RXVALID (GTX_RxValid[i]),
- .SOUTHREFCLKRX (),
- .SOUTHREFCLKTX (),
- .TSTCLK0 ( 1'b0 ),
- .TSTCLK1 ( 1'b0 ),
- .TSTIN ( {20{1'b1}} ),
- .TSTOUT (),
- .TXBUFDIFFCTRL ( 3'b111 ),
- .TXBUFSTATUS (),
- .TXBYPASS8B10B ( TXBYPASS8B10B[3:0] ),
- .TXCHARDISPMODE ( {3'b000, GTX_TxCompliance[i]} ),
- .TXCHARDISPVAL ( 4'b0000 ),
- .TXCHARISK ( {TxDataK_dummy[1:0], GTX_TxDataK[(2*i)+1:2*i]} ),
- .TXCOMINIT ( 1'b0 ),
- .TXCOMSAS ( 1'b0 ),
- .TXCOMWAKE ( 1'b0 ),
- .TXDATA ( {TxData_dummy[15:0], GTX_TxData[(16*i)+15:(16*i)+0]} ),
- .TXDEEMPH ( TxDeemph ),
- .TXDETECTRX ( TxDetectRx ),
- .TXDIFFCTRL ( 4'b1111 ),
- .TXDLYALIGNDISABLE ( 1'b1 ),
- .TXELECIDLE ( GTX_TxElecIdle[i] ),
- .TXENC8B10BUSE ( 1'b1 ),
- .TXENPMAPHASEALIGN ( TXENPMAPHASEALIGN[i] ),
- .TXENPRBSTST (),
- .TXGEARBOXREADY (),
- .TXHEADER (),
- .TXINHIBIT ( 1'b0 ),
- .TXKERR (),
- .TXMARGIN ( {TxMargin, 2'b00} ),
- .TXN ( GTX_TXN[i] ),
- .TXOUTCLK (),
- .TXOUTCLKPCS (),
- .TXP ( GTX_TXP[i] ),
- .TXPDOWNASYNCH ( TXPdownAsynch ),
- .TXPLLLKDET ( ),
- .TXPLLLKDETEN ( 1'b0 ),
- .TXPLLPOWERDOWN ( 1'b0 ),
- .TXPLLREFSELDY ( 3'b000 ),
- .TXPMASETPHASE ( TXPMASETPHASE[i] ),
- .TXPOLARITY ( 1'b0 ),
- .TXPOSTEMPHASIS (),
- .TXPOWERDOWN ( PowerDown[(2*i)+1:(2*i)] ),
- .TXPRBSFORCEERR (),
- .TXPREEMPHASIS (),
- .TXRATE ( {1'b1, Rate} ),
- .TXRESET ( ~GTReset_n | local_pcs_reset | PCS_RESET[i] ),
- .TXRESETDONE ( TXRESETDONE[i] ),
- .TXRUNDISP (),
- .TXSEQUENCE (),
- .TXSTARTSEQ (),
- .TXSWING ( TxSwing ),
- .TXUSRCLK ( PCLK ),
- .TXUSRCLK2 ( PCLK ),
- .USRCODEERR (),
- .IGNORESIGDET (),
- .PERFCLKRX (),
- .PERFCLKTX (),
- .RXDLYALIGNMONITOR (),
- .RXDLYALIGNOVERRIDE ( 1'b0 ),
- .RXDLYALIGNRESET (),
- .RXDLYALIGNSWPPRECURB ( 1'b1 ),
- .RXDLYALIGNUPDSW ( 1'b0 ),
- .TXDLYALIGNMONITOR (),
- .TXDLYALIGNOVERRIDE ( 1'b0 ),
- .TXDLYALIGNRESET (),
- .TXDLYALIGNUPDSW ( 1'b1 ),
- .TXRATEDONE ( TXRATEDONE[i] )
-
-
- );
- end
-
- endgenerate
-
-
-endmodule
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_bram_top_v6.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_bram_top_v6.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_bram_top_v6.v (nonexistent)
@@ -1,158 +0,0 @@
-
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : pcie_bram_top_v6.v
-//--
-//-- Description: BlockRAM top level module for Virtex6 PCIe Block
-//--
-//--
-//--
-//--------------------------------------------------------------------------------
-
-`timescale 1ns/1ns
-
-module pcie_bram_top_v6
-#(
- parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0,
-
- parameter VC0_TX_LASTPACKET = 31,
- parameter TLM_TX_OVERHEAD = 24,
- parameter TL_TX_RAM_RADDR_LATENCY = 1,
- parameter TL_TX_RAM_RDATA_LATENCY = 2,
- parameter TL_TX_RAM_WRITE_LATENCY = 1,
-
- parameter VC0_RX_LIMIT = 'h1FFF,
- parameter TL_RX_RAM_RADDR_LATENCY = 1,
- parameter TL_RX_RAM_RDATA_LATENCY = 2,
- parameter TL_RX_RAM_WRITE_LATENCY = 1
-)
- (
- input user_clk_i,
- input reset_i,
-
- input mim_tx_wen,
- input [12:0] mim_tx_waddr,
- input [71:0] mim_tx_wdata,
- input mim_tx_ren,
- input mim_tx_rce,
- input [12:0] mim_tx_raddr,
- output [71:0] mim_tx_rdata,
-
- input mim_rx_wen,
- input [12:0] mim_rx_waddr,
- input [71:0] mim_rx_wdata,
- input mim_rx_ren,
- input mim_rx_rce,
- input [12:0] mim_rx_raddr,
- output [71:0] mim_rx_rdata
- );
-
- // TX calculations
- localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :
- (DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :
- (DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 :
- 1024 );
-
- localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);
-
- localparam ROWS_TX = 1;
- localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 :
- (BYTES_TX <= 8192) ? 2 :
- (BYTES_TX <= 16384) ? 4 :
- (BYTES_TX <= 32768) ? 8 :
- 18
- );
-
- // RX calculations
- localparam ROWS_RX = 1;
-
- localparam COLS_RX = ((VC0_RX_LIMIT < 'h0200) ? 1 :
- (VC0_RX_LIMIT < 'h0400) ? 2 :
- (VC0_RX_LIMIT < 'h0800) ? 4 :
- (VC0_RX_LIMIT < 'h1000) ? 8 :
- 18
- );
-
- initial begin
- $display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX);
- $display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX);
- end
-
- pcie_brams_v6 #(.NUM_BRAMS (COLS_TX),
- .RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),
- .RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),
- .RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY))
- pcie_brams_tx
- (
- .user_clk_i(user_clk_i),
- .reset_i(reset_i),
-
- .waddr(mim_tx_waddr),
- .wen(mim_tx_wen),
- .ren(mim_tx_ren),
- .rce(mim_tx_rce),
- .wdata(mim_tx_wdata),
- .raddr(mim_tx_raddr),
- .rdata(mim_tx_rdata)
- );
-
- pcie_brams_v6 #(.NUM_BRAMS (COLS_RX),
- .RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),
- .RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),
- .RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY))
- pcie_brams_rx
- (
- .user_clk_i(user_clk_i),
- .reset_i(reset_i),
-
- .waddr(mim_rx_waddr),
- .wen(mim_rx_wen),
- .ren(mim_rx_ren),
- .rce(mim_rx_rce),
- .wdata(mim_rx_wdata),
- .raddr(mim_rx_raddr),
- .rdata(mim_rx_rdata)
- );
-
-endmodule // pcie_bram_top
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_brams_v6.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_brams_v6.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_brams_v6.v (nonexistent)
@@ -1,253 +0,0 @@
-
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : pcie_brams_v6.v
-//--
-//-- Description: BlockRAM module for Virtex6 PCIe Block
-//--
-//--
-//--
-//--------------------------------------------------------------------------------
-
-`timescale 1ns/1ns
-
-module pcie_brams_v6
-#(
- // the number of BRAMs to use
- // supported values are:
- // 1,2,4,8,18
- parameter NUM_BRAMS = 0,
-
- // BRAM read address latency
- //
- // value meaning
- // ====================================================
- // 0 BRAM read address port sample
- // 1 BRAM read address port sample and a pipeline stage on the address port
- parameter RAM_RADDR_LATENCY = 1,
-
- // BRAM read data latency
- //
- // value meaning
- // ====================================================
- // 1 no BRAM OREG
- // 2 use BRAM OREG
- // 3 use BRAM OREG and a pipeline stage on the data port
- parameter RAM_RDATA_LATENCY = 1,
-
- // BRAM write latency
- // The BRAM write port is synchronous
- //
- // value meaning
- // ====================================================
- // 0 BRAM write port sample
- // 1 BRAM write port sample plus pipeline stage
- parameter RAM_WRITE_LATENCY = 1
- )
- (
- input user_clk_i,
- input reset_i,
-
- input wen,
- input [12:0] waddr,
- input [71:0] wdata,
- input ren,
- input rce,
- input [12:0] raddr,
- output [71:0] rdata
- );
-
- // turn on the bram output register
- localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0;
-
- // calculate the data width of the individual brams
- localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 72 :
- (NUM_BRAMS == 2) ? 36 :
- (NUM_BRAMS == 4) ? 18 :
- (NUM_BRAMS == 8) ? 9 :
- 4
- );
-
- parameter TCQ = 1;
-
- //synthesis translate_off
- initial begin
- $display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d",
- $time, NUM_BRAMS, DOB_REG, WIDTH, RAM_WRITE_LATENCY, RAM_RADDR_LATENCY, RAM_RDATA_LATENCY);
-
- case (NUM_BRAMS)
- 1,2,4,8,18:;
- default:
- begin
- $display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS);
- $finish;
- end
- endcase // case(NUM_BRAMS)
-
- case (RAM_RADDR_LATENCY)
- 0,1:;
- default:
- begin
- $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY);
- $finish;
- end
- endcase // case (RAM_RADDR_LATENCY)
-
- case (RAM_RDATA_LATENCY)
- 1,2,3:;
- default:
- begin
- $display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY);
- $finish;
- end
- endcase // case (RAM_RDATA_LATENCY)
-
- case (RAM_WRITE_LATENCY)
- 0,1:;
- default:
- begin
- $display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY);
- $finish;
- end
- endcase // case(RAM_WRITE_LATENCY)
-
- end
- //synthesis translate_on
-
- // model the delays for ram write latency
-
- wire wen_int;
- wire [12:0] waddr_int;
- wire [71:0] wdata_int;
-
- generate if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2
- reg wen_dly;
- reg [12:0] waddr_dly;
- reg [71:0] wdata_dly;
-
- always @(posedge user_clk_i) begin
- if (reset_i) begin
- wen_dly <= #TCQ 1'b0;
- waddr_dly <= #TCQ 13'b0;
- wdata_dly <= #TCQ 72'b0;
- end else begin
- wen_dly <= #TCQ wen;
- waddr_dly <= #TCQ waddr;
- wdata_dly <= #TCQ wdata;
- end
- end
-
- assign wen_int = wen_dly;
- assign waddr_int = waddr_dly;
- assign wdata_int = wdata_dly;
- end // if (RAM_WRITE_LATENCY == 1)
-
- else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1
- assign wen_int = wen;
- assign waddr_int = waddr;
- assign wdata_int = wdata;
- end
- endgenerate
-
- // model the delays for ram read latency
-
- wire ren_int;
- wire [12:0] raddr_int;
- wire [71:0] rdata_int;
-
- generate if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2
- reg ren_dly;
- reg [12:0] raddr_dly;
-
- always @(posedge user_clk_i) begin
- if (reset_i) begin
- ren_dly <= #TCQ 1'b0;
- raddr_dly <= #TCQ 13'b0;
- end else begin
- ren_dly <= #TCQ ren;
- raddr_dly <= #TCQ raddr;
- end // else: !if(reset_i)
- end
-
- assign ren_int = ren_dly;
- assign raddr_int = raddr_dly;
- end // block: rd_lat_addr_2
-
- else begin : raddr_lat_1
- assign ren_int = ren;
- assign raddr_int = raddr;
- end
- endgenerate
-
- generate if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3
- reg [71:0] rdata_dly;
-
- always @(posedge user_clk_i) begin
- if (reset_i) begin
- rdata_dly <= #TCQ 72'b0;
- end else begin
- rdata_dly <= #TCQ rdata_int;
- end // else: !if(reset_i)
- end
-
- assign rdata = rdata_dly;
-
- end // block: rd_lat_data_3
-
- else begin : rdata_lat_1_2
- assign #TCQ rdata = rdata_int;
- end
- endgenerate
-
- // instantiate the brams
- generate
- genvar i;
- for (i = 0; i < NUM_BRAMS; i = i + 1) begin : brams
- pcie_bram_v6 #(.DOB_REG(DOB_REG), .WIDTH(WIDTH))
- ram (.user_clk_i(user_clk_i), .reset_i(reset_i),
- .wen_i(wen_int), .waddr_i(waddr_int), .wdata_i(wdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]),
- .ren_i(ren_int), .raddr_i(raddr_int), .rdata_o(rdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]), .rce_i(rce));
- end
- endgenerate
-endmodule // pcie_brams_v6
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_misc_v6.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_misc_v6.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/pcie_pipe_misc_v6.v (nonexistent)
@@ -1,194 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : pcie_pipe_misc_v6.v
-//--
-//-- Description: Misc PIPE module for Virtex6 PCIe Block
-//--
-//--
-//--
-//--------------------------------------------------------------------------------
-
-`timescale 1ns/1ns
-
-module pcie_pipe_misc_v6 #
-(
- parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
-)
-(
-
- input wire pipe_tx_rcvr_det_i ,
- input wire pipe_tx_reset_i ,
- input wire pipe_tx_rate_i ,
- input wire pipe_tx_deemph_i ,
- input wire [2:0] pipe_tx_margin_i ,
- input wire pipe_tx_swing_i ,
-
- output wire pipe_tx_rcvr_det_o ,
- output wire pipe_tx_reset_o ,
- output wire pipe_tx_rate_o ,
- output wire pipe_tx_deemph_o ,
- output wire [2:0] pipe_tx_margin_o ,
- output wire pipe_tx_swing_o ,
-
- input wire pipe_clk ,
- input wire rst_n
-);
-
-//******************************************************************//
-// Reality check. //
-//******************************************************************//
-
- parameter TCQ = 1; // clock to out delay model
-
- reg pipe_tx_rcvr_det_q ;
- reg pipe_tx_reset_q ;
- reg pipe_tx_rate_q ;
- reg pipe_tx_deemph_q ;
- reg [2:0] pipe_tx_margin_q ;
- reg pipe_tx_swing_q ;
-
- reg pipe_tx_rcvr_det_qq ;
- reg pipe_tx_reset_qq ;
- reg pipe_tx_rate_qq ;
- reg pipe_tx_deemph_qq ;
- reg [2:0] pipe_tx_margin_qq ;
- reg pipe_tx_swing_qq ;
-
- generate
-
- if (PIPE_PIPELINE_STAGES == 0) begin
-
-
- assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
- assign pipe_tx_reset_o = pipe_tx_reset_i;
- assign pipe_tx_rate_o = pipe_tx_rate_i;
- assign pipe_tx_deemph_o = pipe_tx_deemph_i;
- assign pipe_tx_margin_o = pipe_tx_margin_i;
- assign pipe_tx_swing_o = pipe_tx_swing_i;
-
- end else if (PIPE_PIPELINE_STAGES == 1) begin
-
- always @(posedge pipe_clk) begin
-
- if (rst_n) begin
-
- pipe_tx_rcvr_det_q <= #TCQ 0;
- pipe_tx_reset_q <= #TCQ 1'b1;
- pipe_tx_rate_q <= #TCQ 0;
- pipe_tx_deemph_q <= #TCQ 1'b1;
- pipe_tx_margin_q <= #TCQ 0;
- pipe_tx_swing_q <= #TCQ 0;
-
- end else begin
-
- pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
- pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
- pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
- pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
- pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
- pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
-
- end
-
- end
-
- assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
- assign pipe_tx_reset_o = pipe_tx_reset_q;
- assign pipe_tx_rate_o = pipe_tx_rate_q;
- assign pipe_tx_deemph_o = pipe_tx_deemph_q;
- assign pipe_tx_margin_o = pipe_tx_margin_q;
- assign pipe_tx_swing_o = pipe_tx_swing_q;
-
- end else if (PIPE_PIPELINE_STAGES == 2) begin
-
- always @(posedge pipe_clk) begin
-
- if (rst_n) begin
-
- pipe_tx_rcvr_det_q <= #TCQ 0;
- pipe_tx_reset_q <= #TCQ 1'b1;
- pipe_tx_rate_q <= #TCQ 0;
- pipe_tx_deemph_q <= #TCQ 1'b1;
- pipe_tx_margin_q <= #TCQ 0;
- pipe_tx_swing_q <= #TCQ 0;
-
- pipe_tx_rcvr_det_qq <= #TCQ 0;
- pipe_tx_reset_qq <= #TCQ 1'b1;
- pipe_tx_rate_qq <= #TCQ 0;
- pipe_tx_deemph_qq <= #TCQ 1'b1;
- pipe_tx_margin_qq <= #TCQ 0;
- pipe_tx_swing_qq <= #TCQ 0;
-
- end else begin
-
- pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
- pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
- pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
- pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
- pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
- pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
-
- pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
- pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
- pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
- pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
- pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
- pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
-
- end
-
- end
-
- assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
- assign pipe_tx_reset_o = pipe_tx_reset_qq;
- assign pipe_tx_rate_o = pipe_tx_rate_qq;
- assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
- assign pipe_tx_margin_o = pipe_tx_margin_qq;
- assign pipe_tx_swing_o = pipe_tx_swing_qq;
-
- end
-
- endgenerate
-
-endmodule
Index: branches/Virtex6/ML605/v6_pcie_v1_3/source/v6_pcie_v1_3.v
===================================================================
--- branches/Virtex6/ML605/v6_pcie_v1_3/source/v6_pcie_v1_3.v (revision 9)
+++ branches/Virtex6/ML605/v6_pcie_v1_3/source/v6_pcie_v1_3.v (nonexistent)
@@ -1,1191 +0,0 @@
-//-----------------------------------------------------------------------------
-//
-// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information of Xilinx, Inc.
-// and is protected under U.S. and international copyright and other
-// intellectual property laws.
-//
-// DISCLAIMER
-//
-// This disclaimer is not a license and does not grant any rights to the
-// materials distributed herewith. Except as otherwise provided in a valid
-// license issued to you by Xilinx, and to the maximum extent permitted by
-// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
-// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
-// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
-// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
-// and (2) Xilinx shall not be liable (whether in contract or tort, including
-// negligence, or under any other theory of liability) for any loss or damage
-// of any kind or nature related to, arising under or in connection with these
-// materials, including for any direct, or any indirect, special, incidental,
-// or consequential loss or damage (including loss of data, profits, goodwill,
-// or any type of loss or damage suffered as a result of any action brought by
-// a third party) even if such damage or loss was reasonably foreseeable or
-// Xilinx had been advised of the possibility of the same.
-//
-// CRITICAL APPLICATIONS
-//
-// Xilinx products are not designed or intended to be fail-safe, or for use in
-// any application requiring fail-safe performance, such as life-support or
-// safety devices or systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any other
-// applications that could lead to death, personal injury, or severe property
-// or environmental damage (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and liability of any use of
-// Xilinx products in Critical Applications, subject only to applicable laws
-// and regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
-// AT ALL TIMES.
-//
-//-----------------------------------------------------------------------------
-// Project : Virtex-6 Integrated Block for PCI Express
-// File : v6_pcie_v1_3.v
-//--
-//-- Description: Virtex6 solution wrapper : Endpoint for PCI Express
-//--
-//--
-//--
-//--------------------------------------------------------------------------------
-
-`timescale 1ns/1ns
-
-module v6_pcie_v1_3 # (
- parameter ALLOW_X8_GEN2 = "FALSE",
- parameter BAR0 = 32'hFFFF0000,
- parameter BAR1 = 32'hFFF00000,
- parameter BAR2 = 32'hFFFFF000,
- parameter BAR3 = 32'h00000000,
- parameter BAR4 = 32'h00000000,
- parameter BAR5 = 32'h00000000,
-
- parameter CARDBUS_CIS_POINTER = 32'h00000000,
- parameter CLASS_CODE = 24'h050000,
- parameter CMD_INTX_IMPLEMENTED = "TRUE",
- parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
- parameter CPL_TIMEOUT_RANGES_SUPPORTED = 4'h2,
-
- parameter DEV_CAP_ENDPOINT_L0S_LATENCY = 7,
- parameter DEV_CAP_ENDPOINT_L1_LATENCY = 7,
- parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE",
- parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
- parameter DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
- parameter DEVICE_ID = 16'h0153,
-
- parameter DISABLE_LANE_REVERSAL = "TRUE",
- parameter DISABLE_SCRAMBLING = "FALSE",
- parameter DSN_BASE_PTR = 12'h100,
- parameter DSN_CAP_NEXTPTR = 12'h000,
- parameter DSN_CAP_ON = "TRUE",
-
- parameter ENABLE_MSG_ROUTE = 11'h00000000000,
- parameter ENABLE_RX_TD_ECRC_TRIM = "TRUE",
- parameter EXPANSION_ROM = 32'h00000000,
- parameter EXT_CFG_CAP_PTR = 6'h3F,
- parameter EXT_CFG_XP_CAP_PTR = 10'h3FF,
- parameter HEADER_TYPE = 8'h00,
- parameter INTERRUPT_PIN = 8'h1,
-
- parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
- parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
- parameter LINK_CAP_MAX_LINK_SPEED = 4'h1,
- parameter LINK_CAP_MAX_LINK_WIDTH = 6'h04,
- parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
-
- parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
- parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
- parameter LINK_CTRL2_TARGET_LINK_SPEED = 4'h0,
- parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE",
-
- parameter LL_ACK_TIMEOUT = 15'h0000,
- parameter LL_ACK_TIMEOUT_EN = "FALSE",
- parameter LL_ACK_TIMEOUT_FUNC = 0,
- parameter LL_REPLAY_TIMEOUT = 15'h0000,
- parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
- parameter LL_REPLAY_TIMEOUT_FUNC = 0,
-
- parameter LTSSM_MAX_LINK_WIDTH = LINK_CAP_MAX_LINK_WIDTH,
- parameter MSI_CAP_MULTIMSGCAP = 0,
- parameter MSI_CAP_MULTIMSG_EXTENSION = 0,
- parameter MSI_CAP_ON = "TRUE",
- parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE",
- parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
-
- parameter MSIX_CAP_ON = "FALSE",
- parameter MSIX_CAP_PBA_BIR = 0,
- parameter MSIX_CAP_PBA_OFFSET = 29'h0,
- parameter MSIX_CAP_TABLE_BIR = 0,
- parameter MSIX_CAP_TABLE_OFFSET = 29'h0,
- parameter MSIX_CAP_TABLE_SIZE = 11'h000,
-
- parameter PCIE_CAP_DEVICE_PORT_TYPE = 4'b0000,
- parameter PCIE_CAP_INT_MSG_NUM = 5'h1,
- parameter PCIE_CAP_NEXTPTR = 8'h00,
- parameter PCIE_DRP_ENABLE = "FALSE",
- parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
-
- parameter PM_CAP_DSI = "FALSE",
- parameter PM_CAP_D1SUPPORT = "FALSE",
- parameter PM_CAP_D2SUPPORT = "FALSE",
- parameter PM_CAP_NEXTPTR = 8'h48,
- parameter PM_CAP_PMESUPPORT = 5'h0F,
- parameter PM_CSR_NOSOFTRST = "TRUE",
-
- parameter PM_DATA_SCALE0 = 2'h0,
- parameter PM_DATA_SCALE1 = 2'h0,
- parameter PM_DATA_SCALE2 = 2'h0,
- parameter PM_DATA_SCALE3 = 2'h0,
- parameter PM_DATA_SCALE4 = 2'h0,
- parameter PM_DATA_SCALE5 = 2'h0,
- parameter PM_DATA_SCALE6 = 2'h0,
- parameter PM_DATA_SCALE7 = 2'h0,
-
- parameter PM_DATA0 = 8'h00,
- parameter PM_DATA1 = 8'h00,
- parameter PM_DATA2 = 8'h00,
- parameter PM_DATA3 = 8'h00,
- parameter PM_DATA4 = 8'h00,
- parameter PM_DATA5 = 8'h00,
- parameter PM_DATA6 = 8'h00,
- parameter PM_DATA7 = 8'h00,
-
- parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
- parameter REVISION_ID = 8'h06,
- parameter SUBSYSTEM_ID = 16'hABB3,
- parameter SUBSYSTEM_VENDOR_ID = 16'h0084,
-
- parameter TL_RX_RAM_RADDR_LATENCY = 0,
- parameter TL_RX_RAM_RDATA_LATENCY = 2,
- parameter TL_RX_RAM_WRITE_LATENCY = 0,
- parameter TL_TX_RAM_RADDR_LATENCY = 0,
- parameter TL_TX_RAM_RDATA_LATENCY = 2,
- parameter TL_TX_RAM_WRITE_LATENCY = 0,
-
- parameter UPCONFIG_CAPABLE = "TRUE",
- parameter USER_CLK_FREQ = 2,
- parameter VC_BASE_PTR = 12'h0,
- parameter VC_CAP_NEXTPTR = 12'h000,
- parameter VC_CAP_ON = "FALSE",
- parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
-
- parameter VC0_CPL_INFINITE = "TRUE",
- parameter VC0_RX_RAM_LIMIT = 13'h7FF,
- parameter VC0_TOTAL_CREDITS_CD = 308,
- parameter VC0_TOTAL_CREDITS_CH = 36,
- parameter VC0_TOTAL_CREDITS_NPH = 12,
- parameter VC0_TOTAL_CREDITS_PD = 308,
- parameter VC0_TOTAL_CREDITS_PH = 32,
- parameter VC0_TX_LASTPACKET = 29,
-
- parameter VENDOR_ID = 16'h10DC,
- parameter VSEC_BASE_PTR = 12'h0,
- parameter VSEC_CAP_NEXTPTR = 12'h000,
- parameter VSEC_CAP_ON = "FALSE",
-
- parameter AER_BASE_PTR = 12'h128,
- parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
- parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
- parameter AER_CAP_ID = 16'h0001,
- parameter AER_CAP_INT_MSG_NUM_MSI = 5'h0a,
- parameter AER_CAP_INT_MSG_NUM_MSIX = 5'h15,
- parameter AER_CAP_NEXTPTR = 12'h160,
- parameter AER_CAP_ON = "FALSE",
- parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
- parameter AER_CAP_VERSION = 4'h1,
-
- parameter CAPABILITIES_PTR = 8'h40,
- parameter CRM_MODULE_RSTS = 7'h00,
- parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
- parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
- parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
- parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
- parameter DEV_CAP_RSVD_14_12 = 0,
- parameter DEV_CAP_RSVD_17_16 = 0,
- parameter DEV_CAP_RSVD_31_29 = 0,
- parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
-
- parameter DISABLE_ASPM_L1_TIMER = "FALSE",
- parameter DISABLE_BAR_FILTERING = "FALSE",
- parameter DISABLE_ID_CHECK = "FALSE",
- parameter DISABLE_RX_TC_FILTER = "FALSE",
- parameter DNSTREAM_LINK_NUM = 8'h00,
-
- parameter DSN_CAP_ID = 16'h0003,
- parameter DSN_CAP_VERSION = 4'h1,
- parameter ENTER_RVRY_EI_L0 = "TRUE",
- parameter INFER_EI = 5'h0c,
- parameter IS_SWITCH = "FALSE",
-
- parameter LAST_CONFIG_DWORD = 10'h3FF,
- parameter LINK_CAP_ASPM_SUPPORT = 1,
- parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
- parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
- parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
- parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
- parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
- parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
- parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
- parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
- parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
- parameter LINK_CAP_RSVD_23_22 = 0,
- parameter LINK_CONTROL_RCB = 0,
-
- parameter MSI_BASE_PTR = 8'h48,
- parameter MSI_CAP_ID = 8'h05,
- parameter MSI_CAP_NEXTPTR = 8'h60,
- parameter MSIX_BASE_PTR = 8'h9c,
- parameter MSIX_CAP_ID = 8'h11,
- parameter MSIX_CAP_NEXTPTR = 8'h00,
- parameter N_FTS_COMCLK_GEN1 = 255,
- parameter N_FTS_COMCLK_GEN2 = 254,
- parameter N_FTS_GEN1 = 255,
- parameter N_FTS_GEN2 = 255,
-
- parameter PCIE_BASE_PTR = 8'h60,
- parameter PCIE_CAP_CAPABILITY_ID = 8'h10,
- parameter PCIE_CAP_CAPABILITY_VERSION = 4'h2,
- parameter PCIE_CAP_ON = "TRUE",
- parameter PCIE_CAP_RSVD_15_14 = 0,
- parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
- parameter PCIE_REVISION = 2,
- parameter PGL0_LANE = 0,
- parameter PGL1_LANE = 1,
- parameter PGL2_LANE = 2,
- parameter PGL3_LANE = 3,
- parameter PGL4_LANE = 4,
- parameter PGL5_LANE = 5,
- parameter PGL6_LANE = 6,
- parameter PGL7_LANE = 7,
- parameter PL_AUTO_CONFIG = 0,
- parameter PL_FAST_TRAIN = "FALSE",
-
- parameter PM_BASE_PTR = 8'h40,
- parameter PM_CAP_AUXCURRENT = 0,
- parameter PM_CAP_ID = 8'h01,
- parameter PM_CAP_ON = "TRUE",
- parameter PM_CAP_PME_CLOCK = "FALSE",
- parameter PM_CAP_RSVD_04 = 0,
- parameter PM_CAP_VERSION = 3,
- parameter PM_CSR_BPCCEN = "FALSE",
- parameter PM_CSR_B2B3 = "FALSE",
-
- parameter RECRC_CHK = 0,
- parameter RECRC_CHK_TRIM = "FALSE",
- parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
- parameter SELECT_DLL_IF = "FALSE",
- parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
- parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
- parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
- parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
- parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
- parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
- parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
- parameter SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
- parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
- parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
- parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
- parameter SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
- parameter SPARE_BIT0 = 0,
- parameter SPARE_BIT1 = 0,
- parameter SPARE_BIT2 = 0,
- parameter SPARE_BIT3 = 0,
- parameter SPARE_BIT4 = 0,
- parameter SPARE_BIT5 = 0,
- parameter SPARE_BIT6 = 0,
- parameter SPARE_BIT7 = 0,
- parameter SPARE_BIT8 = 0,
- parameter SPARE_BYTE0 = 8'h00,
- parameter SPARE_BYTE1 = 8'h00,
- parameter SPARE_BYTE2 = 8'h00,
- parameter SPARE_BYTE3 = 8'h00,
- parameter SPARE_WORD0 = 32'h00000000,
- parameter SPARE_WORD1 = 32'h00000000,
- parameter SPARE_WORD2 = 32'h00000000,
- parameter SPARE_WORD3 = 32'h00000000,
-
- parameter TL_RBYPASS = "FALSE",
- parameter TL_TFC_DISABLE = "FALSE",
- parameter TL_TX_CHECKS_DISABLE = "FALSE",
- parameter EXIT_LOOPBACK_ON_EI = "TRUE",
- parameter UPSTREAM_FACING = "TRUE",
- parameter UR_INV_REQ = "TRUE",
-
- parameter VC_CAP_ID = 16'h0002,
- parameter VC_CAP_VERSION = 4'h1,
- parameter VSEC_CAP_HDR_ID = 16'h1234,
- parameter VSEC_CAP_HDR_LENGTH = 12'h018,
- parameter VSEC_CAP_HDR_REVISION = 4'h1,
- parameter VSEC_CAP_ID = 16'h000b,
- parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
- parameter VSEC_CAP_VERSION = 4'h1
-)
-(
- //-------------------------------------------------------
- // 1. PCI Express (pci_exp) Interface
- //-------------------------------------------------------
-
- // Tx
- output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txp,
- output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txn,
-
- // Rx
- input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxp,
- input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxn,
-
- //-------------------------------------------------------
- // 2. Transaction (TRN) Interface
- //-------------------------------------------------------
-
- // Common
- output trn_clk,
- output trn_reset_n,
- output trn_lnk_up_n,
-
- // Tx
- output [5:0] trn_tbuf_av,
- output trn_tcfg_req_n,
- output trn_terr_drop_n,
- output trn_tdst_rdy_n,
- input [63:0] trn_td,
- input trn_trem_n,
- input trn_tsof_n,
- input trn_teof_n,
- input trn_tsrc_rdy_n,
- input trn_tsrc_dsc_n,
- input trn_terrfwd_n,
- input trn_tcfg_gnt_n,
- input trn_tstr_n,
-
- // Rx
- output [63:0] trn_rd,
- output trn_rrem_n,
- output trn_rsof_n,
- output trn_reof_n,
- output trn_rsrc_rdy_n,
- output trn_rsrc_dsc_n,
- output trn_rerrfwd_n,
- output [6:0] trn_rbar_hit_n,
- input trn_rdst_rdy_n,
- input trn_rnp_ok_n,
-
- // Flow Control
- output [11:0] trn_fc_cpld,
- output [7:0] trn_fc_cplh,
- output [11:0] trn_fc_npd,
- output [7:0] trn_fc_nph,
- output [11:0] trn_fc_pd,
- output [7:0] trn_fc_ph,
- input [2:0] trn_fc_sel,
-
-
- //-------------------------------------------------------
- // 3. Configuration (CFG) Interface
- //-------------------------------------------------------
-
- output [31:0] cfg_do,
- output cfg_rd_wr_done_n,
- input [31:0] cfg_di,
- input [3:0] cfg_byte_en_n,
- input [9:0] cfg_dwaddr,
- input cfg_wr_en_n,
- input cfg_rd_en_n,
-
- input cfg_err_cor_n,
- input cfg_err_ur_n,
- input cfg_err_ecrc_n,
- input cfg_err_cpl_timeout_n,
- input cfg_err_cpl_abort_n,
- input cfg_err_cpl_unexpect_n,
- input cfg_err_posted_n,
- input cfg_err_locked_n,
- input [47:0] cfg_err_tlp_cpl_header,
- output cfg_err_cpl_rdy_n,
- input cfg_interrupt_n,
- output cfg_interrupt_rdy_n,
- input cfg_interrupt_assert_n,
- input [7:0] cfg_interrupt_di,
- output [7:0] cfg_interrupt_do,
- output [2:0] cfg_interrupt_mmenable,
- output cfg_interrupt_msienable,
- output cfg_interrupt_msixenable,
- output cfg_interrupt_msixfm,
- input cfg_turnoff_ok_n,
- output cfg_to_turnoff_n,
- input cfg_trn_pending_n,
- input cfg_pm_wake_n,
- output [7:0] cfg_bus_number,
- output [4:0] cfg_device_number,
- output [2:0] cfg_function_number,
- output [15:0] cfg_status,
- output [15:0] cfg_command,
- output [15:0] cfg_dstatus,
- output [15:0] cfg_dcommand,
- output [15:0] cfg_lstatus,
- output [15:0] cfg_lcommand,
- output [15:0] cfg_dcommand2,
- output [2:0] cfg_pcie_link_state_n,
- input [63:0] cfg_dsn,
- output cfg_pmcsr_pme_en,
- output cfg_pmcsr_pme_status,
- output [1:0] cfg_pmcsr_powerstate,
- output lnk_clk_en,
-
- //-------------------------------------------------------
- // 4. Physical Layer Control and Status (PL) Interface
- //-------------------------------------------------------
-
- output [2:0] pl_initial_link_width,
- output [1:0] pl_lane_reversal_mode,
- output pl_link_gen2_capable,
- output pl_link_partner_gen2_supported,
- output pl_link_upcfg_capable,
- output [5:0] pl_ltssm_state,
- output pl_received_hot_rst,
- output pl_sel_link_rate,
- output [1:0] pl_sel_link_width,
- input pl_directed_link_auton,
- input [1:0] pl_directed_link_change,
- input pl_directed_link_speed,
- input [1:0] pl_directed_link_width,
- input pl_upstream_prefer_deemph,
-
- //-------------------------------------------------------
- // 5. System (SYS) Interface
- //-------------------------------------------------------
-
- input sys_clk,
- input sys_reset_n
-
-
-);
-
-
- wire rx_func_level_reset_n;
- wire cfg_msg_received;
- wire cfg_msg_received_pme_to;
-
- wire cfg_cmd_bme;
- wire cfg_cmd_intdis;
- wire cfg_cmd_io_en;
- wire cfg_cmd_mem_en;
- wire cfg_cmd_serr_en;
- wire cfg_dev_control_aux_power_en ;
- wire cfg_dev_control_corr_err_reporting_en ;
- wire cfg_dev_control_enable_relaxed_order ;
- wire cfg_dev_control_ext_tag_en ;
- wire cfg_dev_control_fatal_err_reporting_en ;
- wire [2:0] cfg_dev_control_maxpayload ;
- wire [2:0] cfg_dev_control_max_read_req ;
- wire cfg_dev_control_non_fatal_reporting_en ;
- wire cfg_dev_control_nosnoop_en ;
- wire cfg_dev_control_phantom_en ;
- wire cfg_dev_control_ur_err_reporting_en ;
- wire cfg_dev_control2_cpltimeout_dis ;
- wire [3:0] cfg_dev_control2_cpltimeout_val ;
- wire cfg_dev_status_corr_err_detected ;
- wire cfg_dev_status_fatal_err_detected ;
- wire cfg_dev_status_nonfatal_err_detected ;
- wire cfg_dev_status_ur_detected ;
- wire cfg_link_control_auto_bandwidth_int_en ;
- wire cfg_link_control_bandwidth_int_en ;
- wire cfg_link_control_hw_auto_width_dis ;
- wire cfg_link_control_clock_pm_en ;
- wire cfg_link_control_extended_sync ;
- wire cfg_link_control_common_clock ;
- wire cfg_link_control_retrain_link ;
- wire cfg_link_control_linkdisable ;
- wire cfg_link_control_rcb ;
- wire [1:0] cfg_link_control_aspm_control ;
- wire cfg_link_status_autobandwidth_status ;
- wire cfg_link_status_bandwidth_status ;
- wire cfg_link_status_dll_active ;
- wire cfg_link_status_link_training ;
- wire [3:0] cfg_link_status_negotiated_link_width ;
- wire [1:0] cfg_link_status_current_speed ;
- wire [15:0] cfg_msg_data;
-
- wire sys_reset_n_d;
- wire phy_rdy_n;
-
- wire trn_lnk_up_n_int;
- wire trn_lnk_up_n_int1;
-
- wire trn_reset_n_int;
- wire trn_reset_n_int1;
-
- reg [7:0] cfg_bus_number_d;
- reg [4:0] cfg_device_number_d;
- reg [2:0] cfg_function_number_d;
-
- // assigns to outputs
-
- assign cfg_to_turnoff_n = ~cfg_msg_received_pme_to;
-
- assign cfg_status = {16'b0};
-
- assign cfg_command = {5'b0,
- cfg_cmd_intdis,
- 1'b0,
- cfg_cmd_serr_en,
- 5'b0,
- cfg_cmd_bme,
- cfg_cmd_mem_en,
- cfg_cmd_io_en};
-
- assign cfg_dstatus = {10'h0,
- ~cfg_trn_pending_n,
- 1'b0,
- cfg_dev_status_ur_detected,
- cfg_dev_status_fatal_err_detected,
- cfg_dev_status_nonfatal_err_detected,
- cfg_dev_status_corr_err_detected};
-
- assign cfg_dcommand = {1'b0,
- cfg_dev_control_max_read_req,
- cfg_dev_control_nosnoop_en,
- cfg_dev_control_aux_power_en,
- cfg_dev_control_phantom_en,
- cfg_dev_control_ext_tag_en,
- cfg_dev_control_maxpayload,
- cfg_dev_control_enable_relaxed_order,
- cfg_dev_control_ur_err_reporting_en,
- cfg_dev_control_fatal_err_reporting_en,
- cfg_dev_control_non_fatal_reporting_en,
- cfg_dev_control_corr_err_reporting_en };
-
- assign cfg_lstatus = {cfg_link_status_autobandwidth_status,
- cfg_link_status_bandwidth_status,
- cfg_link_status_dll_active,
- (LINK_STATUS_SLOT_CLOCK_CONFIG == "TRUE") ? 1'b1 : 1'b0,
- cfg_link_status_link_training,
- 1'b0,
- {2'b00, cfg_link_status_negotiated_link_width},
- {2'b00, cfg_link_status_current_speed} };
-
- assign cfg_lcommand = {cfg_link_control_auto_bandwidth_int_en,
- cfg_link_control_bandwidth_int_en,
- cfg_link_control_hw_auto_width_dis,
- cfg_link_control_clock_pm_en,
- cfg_link_control_extended_sync,
- cfg_link_control_common_clock,
- cfg_link_control_retrain_link,
- cfg_link_control_linkdisable,
- cfg_link_control_rcb,
- 1'b0,
- cfg_link_control_aspm_control};
-
- assign cfg_bus_number = cfg_bus_number_d;
-
- assign cfg_device_number = cfg_device_number_d;
-
- assign cfg_function_number = cfg_function_number_d;
-
- assign cfg_dcommand2 = {11'b0,
- cfg_dev_control2_cpltimeout_dis,
- cfg_dev_control2_cpltimeout_val};
-
- // Capture Bus/Device/Function number
-
- always @(posedge trn_clk) begin
- if (trn_lnk_up_n) cfg_bus_number_d <= 8'b0;
- else if (~cfg_msg_received) cfg_bus_number_d <= cfg_msg_data[15:8];
- end
-
- always @(posedge trn_clk) begin
- if (trn_lnk_up_n) cfg_device_number_d <= 5'b0;
- else if (~cfg_msg_received) cfg_device_number_d <= cfg_msg_data[7:3];
- end
-
- always @(posedge trn_clk) begin
- if (trn_lnk_up_n) cfg_function_number_d <= 3'b0;
- else if (~cfg_msg_received) cfg_function_number_d <= cfg_msg_data[2:0];
- end
-
- // Generate trn_lnk_up_n
-
-FDCP #(
-
- .INIT(1'b1)
-
-) trn_lnk_up_n_i (
-
- .Q (trn_lnk_up_n),
- .D (trn_lnk_up_n_int1),
- .C (trn_clk),
- .CLR (1'b0),
- .PRE (1'b0)
-
-);
-
-FDCP #(
-
- .INIT(1'b1)
-
-) trn_lnk_up_n_int_i (
-
- .Q (trn_lnk_up_n_int1),
- .D (trn_lnk_up_n_int),
- .C (trn_clk),
- .CLR (1'b0),
- .PRE (1'b0)
-
-);
-
- // Generate trn_reset_n
-
-FDCP #(
-
- .INIT(1'b0)
-
-) trn_reset_n_i (
-
- .Q (trn_reset_n),
- .D (trn_reset_n_int1 & ~phy_rdy_n),
- .C (trn_clk),
- .CLR (~sys_reset_n_d),
- .PRE (1'b0)
-
-);
-
-FDCP #(
-
- .INIT(1'b0)
-
-) trn_reset_n_int_i (
-
- .Q (trn_reset_n_int1 ),
- .D (trn_reset_n_int & ~phy_rdy_n),
- .C (trn_clk),
- .CLR (~sys_reset_n_d),
- .PRE (1'b0)
-
-);
-
-
-
-//-------------------------------------------------------
-// PCI Express Reset Delay Module
-//-------------------------------------------------------
-
-pcie_reset_delay_v6 #(
-
- .PL_FAST_TRAIN ( PL_FAST_TRAIN ),
- .REF_CLK_FREQ ( REF_CLK_FREQ )
-
-)
-pcie_reset_delay_i (
-
- .ref_clk ( sys_clk_bufg ),
- .sys_reset_n ( sys_reset_n ),
- .delayed_sys_reset_n ( sys_reset_n_d )
-
-);
-
-//-------------------------------------------------------
-// PCI Express Clocking Module
-//-------------------------------------------------------
-
-pcie_clocking_v6 #(
-
- .CAP_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH),
- .CAP_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
- .REF_CLK_FREQ(REF_CLK_FREQ),
- .USER_CLK_FREQ(USER_CLK_FREQ)
-
-)
-pcie_clocking_i (
-
- .sys_clk ( sys_clk ),
- .gt_pll_lock ( gt_pll_lock ),
- .sel_lnk_rate ( pl_sel_link_rate ),
- .sel_lnk_width ( pl_sel_link_width ),
-
- .sys_clk_bufg ( sys_clk_bufg ),
- .pipe_clk ( pipe_clk ),
- .user_clk ( user_clk ),
- .block_clk ( block_clk ),
- .clock_locked ( clock_locked )
-
-);
-
-//-------------------------------------------------------
-// Virtex6 PCI Express Block Module
-//-------------------------------------------------------
-
-pcie_2_0_v6 #(
-
- .REF_CLK_FREQ ( REF_CLK_FREQ ),
- .PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ),
- .AER_BASE_PTR ( AER_BASE_PTR ),
- .AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
- .AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
- .AER_CAP_ID ( AER_CAP_ID ),
- .AER_CAP_INT_MSG_NUM_MSI ( AER_CAP_INT_MSG_NUM_MSI ),
- .AER_CAP_INT_MSG_NUM_MSIX ( AER_CAP_INT_MSG_NUM_MSIX ),
- .AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
- .AER_CAP_ON ( AER_CAP_ON ),
- .AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
- .AER_CAP_VERSION ( AER_CAP_VERSION ),
- .ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
- .BAR0 ( BAR0 ),
- .BAR1 ( BAR1 ),
- .BAR2 ( BAR2 ),
- .BAR3 ( BAR3 ),
- .BAR4 ( BAR4 ),
- .BAR5 ( BAR5 ),
- .CAPABILITIES_PTR ( CAPABILITIES_PTR ),
- .CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
- .CLASS_CODE ( CLASS_CODE ),
- .CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
- .CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
- .CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
- .CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
- .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
- .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
- .DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
- .DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
- .DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
- .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
- .DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
- .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
- .DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
- .DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
- .DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
- .DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
- .DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
- .DEVICE_ID ( DEVICE_ID ),
- .DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
- .DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
- .DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
- .DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
- .DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
- .DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
- .DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
- .DSN_BASE_PTR ( DSN_BASE_PTR ),
- .DSN_CAP_ID ( DSN_CAP_ID ),
- .DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
- .DSN_CAP_ON ( DSN_CAP_ON ),
- .DSN_CAP_VERSION ( DSN_CAP_VERSION ),
- .ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
- .ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
- .ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
- .EXPANSION_ROM ( EXPANSION_ROM ),
- .EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
- .EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
- .HEADER_TYPE ( HEADER_TYPE ),
- .INFER_EI ( INFER_EI ),
- .INTERRUPT_PIN ( INTERRUPT_PIN ),
- .IS_SWITCH ( IS_SWITCH ),
- .LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
- .LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
- .LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
- .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
- .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
- .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
- .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
- .LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
- .LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
- .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
- .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
- .LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
- .LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
- .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
- .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
- .LINK_CAP_RSVD_23_22 ( LINK_CAP_RSVD_23_22 ),
- .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
- .LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
- .LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
- .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
- .LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
- .LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
- .LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
- .LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
- .LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
- .LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
- .LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
- .LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
- .LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
- .MSI_BASE_PTR ( MSI_BASE_PTR ),
- .MSI_CAP_ID ( MSI_CAP_ID ),
- .MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
- .MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
- .MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
- .MSI_CAP_ON ( MSI_CAP_ON ),
- .MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
- .MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
- .MSIX_BASE_PTR ( MSIX_BASE_PTR ),
- .MSIX_CAP_ID ( MSIX_CAP_ID ),
- .MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
- .MSIX_CAP_ON ( MSIX_CAP_ON ),
- .MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
- .MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
- .MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
- .MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
- .MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
- .N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
- .N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
- .N_FTS_GEN1 ( N_FTS_GEN1 ),
- .N_FTS_GEN2 ( N_FTS_GEN2 ),
- .PCIE_BASE_PTR ( PCIE_BASE_PTR ),
- .PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
- .PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
- .PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
- .PCIE_CAP_INT_MSG_NUM ( PCIE_CAP_INT_MSG_NUM ),
- .PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
- .PCIE_CAP_ON ( PCIE_CAP_ON ),
- .PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
- .PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
- .PCIE_REVISION ( PCIE_REVISION ),
- .PGL0_LANE ( PGL0_LANE ),
- .PGL1_LANE ( PGL1_LANE ),
- .PGL2_LANE ( PGL2_LANE ),
- .PGL3_LANE ( PGL3_LANE ),
- .PGL4_LANE ( PGL4_LANE ),
- .PGL5_LANE ( PGL5_LANE ),
- .PGL6_LANE ( PGL6_LANE ),
- .PGL7_LANE ( PGL7_LANE ),
- .PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
- .PL_FAST_TRAIN ( PL_FAST_TRAIN ),
- .PM_BASE_PTR ( PM_BASE_PTR ),
- .PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
- .PM_CAP_DSI ( PM_CAP_DSI ),
- .PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
- .PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
- .PM_CAP_ID ( PM_CAP_ID ),
- .PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
- .PM_CAP_ON ( PM_CAP_ON ),
- .PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
- .PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
- .PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
- .PM_CAP_VERSION ( PM_CAP_VERSION ),
- .PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
- .PM_CSR_B2B3 ( PM_CSR_B2B3 ),
- .PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
- .PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
- .PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
- .PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
- .PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
- .PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
- .PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
- .PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
- .PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
- .PM_DATA0 ( PM_DATA0 ),
- .PM_DATA1 ( PM_DATA1 ),
- .PM_DATA2 ( PM_DATA2 ),
- .PM_DATA3 ( PM_DATA3 ),
- .PM_DATA4 ( PM_DATA4 ),
- .PM_DATA5 ( PM_DATA5 ),
- .PM_DATA6 ( PM_DATA6 ),
- .PM_DATA7 ( PM_DATA7 ),
- .RECRC_CHK ( RECRC_CHK ),
- .RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
- .REVISION_ID ( REVISION_ID ),
- .ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
- .SELECT_DLL_IF ( SELECT_DLL_IF ),
- .SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
- .SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
- .SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
- .SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
- .SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
- .SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
- .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
- .SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
- .SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
- .SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
- .SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
- .SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
- .SPARE_BIT0 ( SPARE_BIT0 ),
- .SPARE_BIT1 ( SPARE_BIT1 ),
- .SPARE_BIT2 ( SPARE_BIT2 ),
- .SPARE_BIT3 ( SPARE_BIT3 ),
- .SPARE_BIT4 ( SPARE_BIT4 ),
- .SPARE_BIT5 ( SPARE_BIT5 ),
- .SPARE_BIT6 ( SPARE_BIT6 ),
- .SPARE_BIT7 ( SPARE_BIT7 ),
- .SPARE_BIT8 ( SPARE_BIT8 ),
- .SPARE_BYTE0 ( SPARE_BYTE0 ),
- .SPARE_BYTE1 ( SPARE_BYTE1 ),
- .SPARE_BYTE2 ( SPARE_BYTE2 ),
- .SPARE_BYTE3 ( SPARE_BYTE3 ),
- .SPARE_WORD0 ( SPARE_WORD0 ),
- .SPARE_WORD1 ( SPARE_WORD1 ),
- .SPARE_WORD2 ( SPARE_WORD2 ),
- .SPARE_WORD3 ( SPARE_WORD3 ),
- .SUBSYSTEM_ID ( SUBSYSTEM_ID ),
- .SUBSYSTEM_VENDOR_ID ( SUBSYSTEM_VENDOR_ID ),
- .TL_RBYPASS ( TL_RBYPASS ),
- .TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
- .TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
- .TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
- .TL_TFC_DISABLE ( TL_TFC_DISABLE ),
- .TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
- .TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
- .TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
- .TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
- .UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
- .UPSTREAM_FACING ( UPSTREAM_FACING ),
- .EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
- .UR_INV_REQ ( UR_INV_REQ ),
- .USER_CLK_FREQ ( USER_CLK_FREQ ),
- .VC_BASE_PTR ( VC_BASE_PTR ),
- .VC_CAP_ID ( VC_CAP_ID ),
- .VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
- .VC_CAP_ON ( VC_CAP_ON ),
- .VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
- .VC_CAP_VERSION ( VC_CAP_VERSION ),
- .VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
- .VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
- .VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
- .VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
- .VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
- .VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
- .VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
- .VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
- .VENDOR_ID ( VENDOR_ID ),
- .VSEC_BASE_PTR ( VSEC_BASE_PTR ),
- .VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
- .VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
- .VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
- .VSEC_CAP_ID ( VSEC_CAP_ID ),
- .VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
- .VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
- .VSEC_CAP_ON ( VSEC_CAP_ON ),
- .VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
-
-)
-pcie_2_0_i (
-
- .PCIEXPRXN( pci_exp_rxn ),
- .PCIEXPRXP( pci_exp_rxp ),
- .PCIEXPTXN( pci_exp_txn ),
- .PCIEXPTXP( pci_exp_txp ),
-
- .SYSCLK( sys_clk ),
- .TRNLNKUPN( trn_lnk_up_n_int ),
- .TRNCLK( trn_clk ),
-
- .FUNDRSTN (sys_reset_n_d),
- .PHYRDYN( phy_rdy_n ),
-
- .LNKCLKEN ( lnk_clk_en ),
- .USERRSTN( trn_reset_n_int ),
- .RECEIVEDFUNCLVLRSTN( rx_func_level_reset_n ),
- .SYSRSTN( ~phy_rdy_n ),
- .PLRSTN( 1'b1 ),
- .DLRSTN( 1'b1 ),
- .TLRSTN( 1'b1 ),
- .FUNCLVLRSTN( 1'b1 ),
- .CMRSTN( 1'b1 ),
- .CMSTICKYRSTN( 1'b1 ),
-
- .TRNRBARHITN( trn_rbar_hit_n ),
- .TRNRD( trn_rd ),
- .TRNRECRCERRN( ),
- .TRNREOFN( trn_reof_n ),
- .TRNRERRFWDN( trn_rerrfwd_n ),
- .TRNRREMN( trn_rrem_n ),
- .TRNRSOFN( trn_rsof_n ),
- .TRNRSRCDSCN( trn_rsrc_dsc_n ),
- .TRNRSRCRDYN( trn_rsrc_rdy_n ),
- .TRNRDSTRDYN( trn_rdst_rdy_n ),
- .TRNRNPOKN( trn_rnp_ok_n ),
-
- .TRNTBUFAV( trn_tbuf_av ),
- .TRNTCFGREQN( trn_tcfg_req_n ),
- .TRNTDLLPDSTRDYN( ),
- .TRNTDSTRDYN( trn_tdst_rdy_n ),
- .TRNTERRDROPN( trn_terr_drop_n ),
- .TRNTCFGGNTN( trn_tcfg_gnt_n ),
- .TRNTD( trn_td ),
- .TRNTDLLPDATA( 32'b0 ),
- .TRNTDLLPSRCRDYN( 1'b1 ),
- .TRNTECRCGENN( 1'b1 ),
- .TRNTEOFN( trn_teof_n ),
- .TRNTERRFWDN( trn_terrfwd_n ),
- .TRNTREMN( trn_trem_n ),
- .TRNTSOFN( trn_tsof_n ),
- .TRNTSRCDSCN( trn_tsrc_dsc_n ),
- .TRNTSRCRDYN( trn_tsrc_rdy_n ),
- .TRNTSTRN( trn_tstr_n ),
-
- .TRNFCCPLD( trn_fc_cpld ),
- .TRNFCCPLH( trn_fc_cplh ),
- .TRNFCNPD( trn_fc_npd ),
- .TRNFCNPH( trn_fc_nph ),
- .TRNFCPD( trn_fc_pd ),
- .TRNFCPH( trn_fc_ph ),
- .TRNFCSEL( trn_fc_sel ),
-
- .CFGAERECRCCHECKEN(),
- .CFGAERECRCGENEN(),
- .CFGCOMMANDBUSMASTERENABLE( cfg_cmd_bme ),
- .CFGCOMMANDINTERRUPTDISABLE( cfg_cmd_intdis ),
- .CFGCOMMANDIOENABLE( cfg_cmd_io_en ),
- .CFGCOMMANDMEMENABLE( cfg_cmd_mem_en ),
- .CFGCOMMANDSERREN( cfg_cmd_serr_en ),
- .CFGDEVCONTROLAUXPOWEREN( cfg_dev_control_aux_power_en ),
- .CFGDEVCONTROLCORRERRREPORTINGEN( cfg_dev_control_corr_err_reporting_en ),
- .CFGDEVCONTROLENABLERO( cfg_dev_control_enable_relaxed_order ),
- .CFGDEVCONTROLEXTTAGEN( cfg_dev_control_ext_tag_en ),
- .CFGDEVCONTROLFATALERRREPORTINGEN( cfg_dev_control_fatal_err_reporting_en ),
- .CFGDEVCONTROLMAXPAYLOAD( cfg_dev_control_maxpayload ),
- .CFGDEVCONTROLMAXREADREQ( cfg_dev_control_max_read_req ),
- .CFGDEVCONTROLNONFATALREPORTINGEN( cfg_dev_control_non_fatal_reporting_en ),
- .CFGDEVCONTROLNOSNOOPEN( cfg_dev_control_nosnoop_en ),
- .CFGDEVCONTROLPHANTOMEN( cfg_dev_control_phantom_en ),
- .CFGDEVCONTROLURERRREPORTINGEN( cfg_dev_control_ur_err_reporting_en ),
- .CFGDEVCONTROL2CPLTIMEOUTDIS( cfg_dev_control2_cpltimeout_dis ),
- .CFGDEVCONTROL2CPLTIMEOUTVAL( cfg_dev_control2_cpltimeout_val ),
- .CFGDEVSTATUSCORRERRDETECTED( cfg_dev_status_corr_err_detected ),
- .CFGDEVSTATUSFATALERRDETECTED( cfg_dev_status_fatal_err_detected ),
- .CFGDEVSTATUSNONFATALERRDETECTED( cfg_dev_status_nonfatal_err_detected ),
- .CFGDEVSTATUSURDETECTED( cfg_dev_status_ur_detected ),
- .CFGDO( cfg_do ),
- .CFGERRAERHEADERLOGSETN(),
- .CFGERRCPLRDYN( cfg_err_cpl_rdy_n ),
- .CFGINTERRUPTDO( cfg_interrupt_do ),
- .CFGINTERRUPTMMENABLE( cfg_interrupt_mmenable ),
- .CFGINTERRUPTMSIENABLE( cfg_interrupt_msienable ),
- .CFGINTERRUPTMSIXENABLE( cfg_interrupt_msixenable ),
- .CFGINTERRUPTMSIXFM( cfg_interrupt_msixfm ),
- .CFGINTERRUPTRDYN( cfg_interrupt_rdy_n ),
- .CFGLINKCONTROLRCB( cfg_link_control_rcb ),
- .CFGLINKCONTROLASPMCONTROL( cfg_link_control_aspm_control ),
- .CFGLINKCONTROLAUTOBANDWIDTHINTEN( cfg_link_control_auto_bandwidth_int_en ),
- .CFGLINKCONTROLBANDWIDTHINTEN( cfg_link_control_bandwidth_int_en ),
- .CFGLINKCONTROLCLOCKPMEN( cfg_link_control_clock_pm_en ),
- .CFGLINKCONTROLCOMMONCLOCK( cfg_link_control_common_clock ),
- .CFGLINKCONTROLEXTENDEDSYNC( cfg_link_control_extended_sync ),
- .CFGLINKCONTROLHWAUTOWIDTHDIS( cfg_link_control_hw_auto_width_dis ),
- .CFGLINKCONTROLLINKDISABLE( cfg_link_control_linkdisable ),
- .CFGLINKCONTROLRETRAINLINK( cfg_link_control_retrain_link ),
- .CFGLINKSTATUSAUTOBANDWIDTHSTATUS( cfg_link_status_autobandwidth_status ),
- .CFGLINKSTATUSBANDWITHSTATUS( cfg_link_status_bandwidth_status ),
- .CFGLINKSTATUSCURRENTSPEED( cfg_link_status_current_speed ),
- .CFGLINKSTATUSDLLACTIVE( cfg_link_status_dll_active ),
- .CFGLINKSTATUSLINKTRAINING( cfg_link_status_link_training ),
- .CFGLINKSTATUSNEGOTIATEDWIDTH( cfg_link_status_negotiated_link_width ),
- .CFGMSGDATA( cfg_msg_data ),
- .CFGMSGRECEIVED( cfg_msg_received ),
- .CFGMSGRECEIVEDASSERTINTA(),
- .CFGMSGRECEIVEDASSERTINTB(),
- .CFGMSGRECEIVEDASSERTINTC(),
- .CFGMSGRECEIVEDASSERTINTD(),
- .CFGMSGRECEIVEDDEASSERTINTA(),
- .CFGMSGRECEIVEDDEASSERTINTB(),
- .CFGMSGRECEIVEDDEASSERTINTC(),
- .CFGMSGRECEIVEDDEASSERTINTD(),
- .CFGMSGRECEIVEDERRCOR(),
- .CFGMSGRECEIVEDERRFATAL(),
- .CFGMSGRECEIVEDERRNONFATAL(),
- .CFGMSGRECEIVEDPMASNAK(),
- .CFGMSGRECEIVEDPMETO( cfg_msg_received_pme_to ),
- .CFGMSGRECEIVEDPMETOACK(),
- .CFGMSGRECEIVEDPMPME(),
- .CFGMSGRECEIVEDSETSLOTPOWERLIMIT(),
- .CFGMSGRECEIVEDUNLOCK(),
- .CFGPCIELINKSTATE( cfg_pcie_link_state_n ),
- .CFGPMCSRPMEEN ( cfg_pmcsr_pme_en ),
- .CFGPMCSRPMESTATUS ( cfg_pmcsr_pme_status ),
- .CFGPMCSRPOWERSTATE ( cfg_pmcsr_powerstate ),
- .CFGPMRCVASREQL1N(),
- .CFGPMRCVENTERL1N(),
- .CFGPMRCVENTERL23N(),
- .CFGPMRCVREQACKN(),
- .CFGRDWRDONEN( cfg_rd_wr_done_n ),
- .CFGSLOTCONTROLELECTROMECHILCTLPULSE(),
- .CFGTRANSACTION(),
- .CFGTRANSACTIONADDR(),
- .CFGTRANSACTIONTYPE(),
- .CFGVCTCVCMAP(),
- .CFGBYTEENN( cfg_byte_en_n ),
- .CFGDI( cfg_di ),
- .CFGDSBUSNUMBER( 8'b0 ),
- .CFGDSDEVICENUMBER( 5'b0 ),
- .CFGDSFUNCTIONNUMBER( 3'b0 ),
- .CFGDSN( cfg_dsn ),
- .CFGDWADDR( cfg_dwaddr ),
- .CFGERRACSN( 1'b1 ),
- .CFGERRAERHEADERLOG( 128'h0 ),
- .CFGERRCORN( cfg_err_cor_n ),
- .CFGERRCPLABORTN( cfg_err_cpl_abort_n ),
- .CFGERRCPLTIMEOUTN( cfg_err_cpl_timeout_n ),
- .CFGERRCPLUNEXPECTN( cfg_err_cpl_unexpect_n ),
- .CFGERRECRCN( cfg_err_ecrc_n ),
- .CFGERRLOCKEDN( cfg_err_locked_n ),
- .CFGERRPOSTEDN( cfg_err_posted_n ),
- .CFGERRTLPCPLHEADER( cfg_err_tlp_cpl_header ),
- .CFGERRURN( cfg_err_ur_n ),
- .CFGINTERRUPTASSERTN( cfg_interrupt_assert_n ),
- .CFGINTERRUPTDI( cfg_interrupt_di ),
- .CFGINTERRUPTN( cfg_interrupt_n ),
- .CFGPMDIRECTASPML1N( 1'b1 ),
- .CFGPMSENDPMACKN( 1'b1 ),
- .CFGPMSENDPMETON( 1'b1 ),
- .CFGPMSENDPMNAKN( 1'b1 ),
- .CFGPMTURNOFFOKN( cfg_turnoff_ok_n ),
- .CFGPMWAKEN( cfg_pm_wake_n ),
- .CFGPORTNUMBER( 8'h0 ),
- .CFGRDENN( cfg_rd_en_n ),
- .CFGTRNPENDINGN( cfg_trn_pending_n ),
- .CFGWRENN( cfg_wr_en_n ),
- .CFGWRREADONLYN( 1'b1 ),
- .CFGWRRW1CASRWN( 1'b1 ),
-
- .PLINITIALLINKWIDTH( pl_initial_link_width ),
- .PLLANEREVERSALMODE( pl_lane_reversal_mode ),
- .PLLINKGEN2CAP( pl_link_gen2_capable ),
- .PLLINKPARTNERGEN2SUPPORTED( pl_link_partner_gen2_supported ),
- .PLLINKUPCFGCAP( pl_link_upcfg_capable ),
- .PLLTSSMSTATE( pl_ltssm_state ),
- .PLPHYLNKUPN( ), // Debug
- .PLRECEIVEDHOTRST( pl_received_hot_rst ),
- .PLRXPMSTATE(), // Debug
- .PLSELLNKRATE( pl_sel_link_rate ),
- .PLSELLNKWIDTH( pl_sel_link_width ),
- .PLTXPMSTATE(), // Debug
- .PLDIRECTEDLINKAUTON( pl_directed_link_auton ),
- .PLDIRECTEDLINKCHANGE( pl_directed_link_change ),
- .PLDIRECTEDLINKSPEED( pl_directed_link_speed ),
- .PLDIRECTEDLINKWIDTH( pl_directed_link_width ),
- .PLDOWNSTREAMDEEMPHSOURCE( 1'b0 ),
- .PLUPSTREAMPREFERDEEMPH( pl_upstream_prefer_deemph ),
- .PLTRANSMITHOTRST( 1'b0 ),
-
- .DBGSCLRA(),
- .DBGSCLRB(),
- .DBGSCLRC(),
- .DBGSCLRD(),
- .DBGSCLRE(),
- .DBGSCLRF(),
- .DBGSCLRG(),
- .DBGSCLRH(),
- .DBGSCLRI(),
- .DBGSCLRJ(),
- .DBGSCLRK(),
- .DBGVECA(),
- .DBGVECB(),
- .DBGVECC(),
- .PLDBGVEC(),
- .DBGMODE( 2'b0 ),
- .DBGSUBMODE( 1'b0 ),
- .PLDBGMODE( 3'b0 ),
-
- .DRPDO(),
- .DRPDRDY(),
- .DRPCLK(1'b0),
- .DRPDADDR(9'b0),
- .DRPDEN(1'b0),
- .DRPDI(16'b0),
- .DRPDWE(1'b0),
-
- .GTPLLLOCK( gt_pll_lock ),
- .PIPECLK( pipe_clk ),
- .USERCLK( user_clk ),
- .CLOCKLOCKED( clock_locked )
-
-
-);
-
-endmodule
Index: branches/Virtex6/ML605/ml605_link_wrapper.v
===================================================================
--- branches/Virtex6/ML605/ml605_link_wrapper.v (revision 9)
+++ branches/Virtex6/ML605/ml605_link_wrapper.v (nonexistent)
@@ -1,181 +0,0 @@
-`include "mgt_parameters.h"
-
-module ml605_link_wrapper #
-(
- parameter SIMULATION = 0,
- parameter DATAWIDTH = 16,
- parameter WORDS = DATAWIDTH/8,
- parameter ALIGN_CHAR = `K285,
- parameter READY_CHAR0 = `K284,
- parameter READY_CHAR1 = `K287
-)
-(
- input TILE0_REFCLK_PAD_N_IN,
- input TILE0_REFCLK_PAD_P_IN,
- input RXN_IN,
- input RXP_IN,
- output wire TXN_OUT,
- output wire TXP_OUT,
- input wire SFP_LOS,
-
- output wire tx_clk,
- output wire rx_clk,
- output wire link_active,
-
- output wire ctrl2send_stop,
- input wire ctrl2send_start,
- input wire ctrl2send_end,
- input wire [15:0] ctrl2send,
-
- output wire data2send_stop,
- input wire data2send_start,
- input wire data2send_end,
- input wire [15:0] data2send,
-
- input wire dlm2send_valid,
- input wire [3:0] dlm2send,
-
- output wire [3:0] dlm_rec,
- output wire dlm_rec_valid,
-
- output wire data_rec_start,
- output wire data_rec_end,
- output wire [15:0] data_rec,
- output wire crc_error_rec,
- input wire data_rec_stop,
-
- output wire ctrl_rec_start,
- output wire ctrl_rec_end,
- output wire [15:0] ctrl_rec,
- input wire ctrl_rec_stop
-
-);
-
-`include "cbm_lp_defines.h"
-
-wire [1:0] TXN_OUT_i;
-wire [1:0] TXP_OUT_i;
-wire tx_ready0;
-wire rx_ready0;
-wire [DATAWIDTH-1:0] rx_data0;
-wire [WORDS-1:0] rx_charisk0;
-wire [DATAWIDTH-1:0] tx_data0;
-wire [WORDS-1:0] tx_charisk0;
-
-wire [(DATAWIDTH-1):0] rx_data2fifo0;
-wire [(WORDS-1):0] rx_charisk2fifo0;
-
-wire [(DATAWIDTH-1):0] rx_data2idlefilter0;
-wire [(WORDS-1):0] rx_charisk2idlefilter0;
-
-wire [(DATAWIDTH-1):0] rx_data2idlemux0;
-wire [(WORDS-1):0] rx_charisk2idlemux0;
-
-reg [(DATAWIDTH-1):0] rx_data2serdes_temp0;
-reg [(WORDS-1):0] rx_charisk2serdes_temp0;
-
-reg [(DATAWIDTH-1):0] rx_data2serdes0;
-reg [(WORDS-1):0] rx_charisk2serdes0;
-
-reg no_idle0;
-wire rxfifo_shift_out0;
-reg rxfifo_shift_out_del0;
-
-
-
- assign TXN_OUT = TXN_OUT_i[0];
- assign TXP_OUT = TXP_OUT_i[0];
-
- gtp_det_lat_wrapper_16bit #
- (
- .ALIGN_CHAR(`K285),
- .READY_CHAR0(`K284),
- .READY_CHAR1(`K287),
- .SIMULATION(SIMULATION) //some things get adjusted for simulation
- )
- gtp_wrapper_i
- (
- .TILE0_REFCLK_PAD_N_IN (TILE0_REFCLK_PAD_N_IN),
- .TILE0_REFCLK_PAD_P_IN (TILE0_REFCLK_PAD_P_IN),
- .GTPRESET_IN (1'b0),
- .TILE0_PLLLKDET_OUT ( ), //
- .RXN_IN ({1'b0, RXN_IN}),
- .RXP_IN ({1'b0, RXP_IN}),
- .TXN_OUT (TXN_OUT_i),
- .TXP_OUT (TXP_OUT_i),
- .SFP_LOS ({1'b0, SFP_LOS}),
-
- .TX_USRCLK (tx_clk),
- .RX_USRCLK0 (rx_clk),
- .RX_USRCLK1 ( ), //
- .TX_READY0 (tx_ready0),
- .TX_READY1 ( ), //
- .RX_READY0 (rx_ready0),
- .RX_READY1 ( ), //
- .RX_DATA0 (rx_data2fifo0),
- .RX_DATA1 ( ), //
- .RX_CHARISK0 (rx_charisk2fifo0),
- .RX_CHARISK1 ( ), //
- .TX_DATA0 (tx_data0),
- .TX_DATA1 ('b0),
- .TX_CHARISK0 (tx_charisk0),
- .TX_CHARISK1 ('b0)
- );
-
-
-syncfifo4cbm rx0_fifo
-(
- .res_n(rx_ready0),
- .w_clk(rx_clk),
- .r_clk(tx_clk),
- .data_in(rx_data2fifo0),
- .charisk_in(rx_charisk2fifo0),
- .data_out(rx_data0),
- .charisk_out(rx_charisk0)
-);
-
-
-lp_cbm_top lp_cbm_top_I0(
- .clk(tx_clk),
- .res_n(tx_ready0),
- .link_active(link_active),
- .link_clk(),
-
- .ctrl2send_stop(ctrl2send_stop),
- .ctrl2send_start(ctrl2send_start),
- .ctrl2send_end(ctrl2send_end),
- .ctrl2send(ctrl2send),
- .crc_error_send(1'b0),
-
- .data2send_stop(data2send_stop),
- .data2send_start(data2send_start),
- .data2send_end(data2send_end),
- .data2send(data2send),
-
- .dlm2send_va(dlm2send_valid),
- .dlm2send(dlm2send),
-
- .dlm_rec_type(dlm_rec),
- .dlm_rec_va(dlm_rec_valid),
-
- .data_rec(data_rec),
- .data_rec_start(data_rec_start),
- .data_rec_end(data_rec_end),
- .data_rec_stop(data_rec_stop),
- .crc_error_rec(crc_error_rec),
-
- .ctrl_rec(ctrl_rec),
- .ctrl_rec_start(ctrl_rec_start),
- .ctrl_rec_end(ctrl_rec_end),
- .ctrl_rec_stop(ctrl_rec_stop),
-
- .clk_link(tx_clk),
- .data_from_link({rx_charisk0, rx_data0}),
- .data2link({tx_charisk0, tx_data0}),
-
- .cable_detected(rx_ready0),
- .dll_locked(rx_ready0)
-);
-
-
-endmodule
\ No newline at end of file
Index: branches/Virtex6/ML605/tx_Mem_Reader.vhd
===================================================================
--- branches/Virtex6/ML605/tx_Mem_Reader.vhd (revision 9)
+++ branches/Virtex6/ML605/tx_Mem_Reader.vhd (nonexistent)
@@ -1,881 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Design Name:
--- Module Name: tx_Mem_Reader - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
---
--- Revision 1.00 - first release. 20.03.2008
---
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.abb64Package.all;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity tx_Mem_Reader is
- port (
-
- -- DDR Read Interface
- DDR_rdc_sof : OUT std_logic;
- DDR_rdc_eof : OUT std_logic;
- DDR_rdc_v : OUT std_logic;
- DDR_rdc_FA : OUT std_logic;
- DDR_rdc_Shift : OUT std_logic;
- DDR_rdc_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- DDR_rdc_full : IN std_logic;
-
- -- DDR payload FIFO Read Port
- DDR_FIFO_RdEn : OUT std_logic;
- DDR_FIFO_Empty : IN std_logic;
- DDR_FIFO_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
-
- -- Event Buffer read port
- eb_FIFO_re : OUT std_logic;
- eb_FIFO_empty : IN std_logic;
- eb_FIFO_qout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- Register Read interface
- Regs_RdAddr : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
- Regs_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- Read Command interface
- RdNumber : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
- RdNumber_eq_One : IN std_logic;
- RdNumber_eq_Two : IN std_logic;
- StartAddr : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- Shift_1st_QWord : IN std_logic;
- FixedAddr : IN std_logic;
- is_CplD : IN std_logic;
- BAR_value : IN std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
- RdCmd_Req : IN std_logic;
- RdCmd_Ack : OUT std_logic;
-
- -- Output port of the memory buffer
- mbuf_Din : OUT std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
- mbuf_WE : OUT std_logic;
- mbuf_Full : IN std_logic;
- mbuf_aFull : IN std_logic;
- mbuf_UserFull : IN std_logic; -- Test pin, intended for DDR flow interrupted
-
- -- Common ports
- Tx_TimeOut : OUT std_logic;
- Tx_eb_TimeOut : OUT std_logic;
- mReader_Rst_n : IN std_logic;
- trn_clk : IN std_logic
- );
-
-end tx_Mem_Reader;
-
-
-architecture Behavioral of tx_Mem_Reader is
-
-
- type mReaderStates is ( St_mR_Idle -- Memory reader Idle
-
- , St_mR_CmdLatch -- Capture the read command
- , St_mR_Transfer -- Acknowlege the command request
-
- , St_mR_DDR_A -- DDR access state A
--- , St_mR_DDR_B -- DDR access state B
- , St_mR_DDR_C -- DDR access state C
-
- , St_mR_Last -- Last word is reached
- );
-
- -- State variables
- signal TxMReader_State : mReaderStates;
-
-
- -- DDR Read Interface
- signal DDR_rdc_sof_i : std_logic;
- signal DDR_rdc_eof_i : std_logic;
- signal DDR_rdc_v_i : std_logic;
- signal DDR_rdc_Shift_i : std_logic;
- signal DDR_rdc_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal DDR_rdc_full_i : std_logic;
-
-
- -- Register read address
- signal Regs_RdAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
- signal Regs_RdEn : std_logic;
- signal Regs_Hit : std_logic;
- signal Regs_Write_mbuf_r1 : std_logic;
- signal Regs_Write_mbuf_r2 : std_logic;
- signal Regs_Write_mbuf_r3 : std_logic;
-
- -- DDR FIFO read enable
- signal DDR_FIFO_RdEn_i : std_logic;
- signal DDR_FIFO_RdEn_Mask : std_logic;
- signal DDR_FIFO_Hit : std_logic;
- signal DDR_FIFO_Write_mbuf_r1 : std_logic;
- signal DDR_FIFO_Write_mbuf_r2 : std_logic;
- signal DDR_FIFO_Write_mbuf_r3 : std_logic;
-
- -- Event Buffer
- signal eb_FIFO_Hit : std_logic;
- signal eb_FIFO_Write_mbuf : std_logic;
- signal eb_FIFO_Write_mbuf_r1 : std_logic;
- signal eb_FIFO_Write_mbuf_r2 : std_logic;
- signal eb_FIFO_re_i : std_logic;
- signal eb_FIFO_RdEn_Mask_rise : std_logic;
- signal eb_FIFO_RdEn_Mask_rise_r1 : std_logic;
- signal eb_FIFO_RdEn_Mask_rise_r2 : std_logic;
- signal eb_FIFO_RdEn_Mask_rise_r3 : std_logic;
- signal eb_FIFO_RdEn_Mask : std_logic;
- signal eb_FIFO_RdEn_Mask_r1 : std_logic;
- signal eb_FIFO_RdEn_Mask_r2 : std_logic;
- signal ebFIFO_Rd_1DW : std_logic;
- signal eb_FIFO_qout_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal eb_FIFO_qout_shift : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal eb_FIFO_qout_swapped : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- Memory data outputs
- signal eb_FIFO_Dout_wire : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal DDR_Dout_wire : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal Regs_RdQout_wire : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal mbuf_Din_wire_OR : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- Output port of the memory buffer
- signal mbuf_Din_i : std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
- signal mbuf_WE_i : std_logic;
- signal mbuf_Full_i : std_logic;
- signal mbuf_aFull_i : std_logic;
- signal mbuf_UserFull_i : std_logic;
- signal mbuf_aFull_r1 : std_logic;
-
-
- -- Read command request and acknowledge
- signal RdCmd_Req_i : std_logic;
- signal RdCmd_Ack_i : std_logic;
-
- signal Shift_1st_QWord_k : std_logic;
- signal is_CplD_k : std_logic;
- signal may_be_MWr_k : std_logic;
- signal TRem_n_last_QWord : std_logic;
-
- signal regs_Rd_Counter : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
- signal regs_Rd_Cntr_eq_One : std_logic;
- signal regs_Rd_Cntr_eq_Two : std_logic;
- signal DDR_Rd_Counter : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
- signal DDR_Rd_Cntr_eq_One : std_logic;
-
- signal ebFIFO_Rd_Counter : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
- signal ebFIFO_Rd_Cntr_eq_Two : std_logic;
-
- signal Address_var : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal Address_step : std_logic_vector(4-1 downto 0);
- signal TxTLP_eof_n : std_logic;
-
- signal TxTLP_eof_n_r1 : std_logic;
--- signal TxTLP_eof_n_r2 : std_logic;
-
- signal TimeOut_Counter : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal TO_Cnt_Rst : std_logic;
- signal Tx_TimeOut_i : std_logic;
- signal Tx_eb_TimeOut_i : std_logic;
-
-
-begin
-
- -- read command REQ + ACK
- RdCmd_Req_i <= RdCmd_Req;
- RdCmd_Ack <= RdCmd_Ack_i;
-
- -- Time out signal out
- Tx_TimeOut <= Tx_TimeOut_i;
- Tx_eb_TimeOut <= Tx_eb_TimeOut_i;
-
-------------------------------------------------------------
---- Memory read control
-------------------------------------------------------------
-
- -- Event Buffer read
- eb_FIFO_re <= eb_FIFO_re_i ;
-
- -- DDR FIFO Read
- DDR_rdc_sof <= DDR_rdc_sof_i ;
- DDR_rdc_eof <= DDR_rdc_eof_i ;
- DDR_rdc_v <= DDR_rdc_v_i ;
- DDR_rdc_FA <= '0' ; -- DDR_rdc_FA_i ;
- DDR_rdc_Shift <= DDR_rdc_Shift_i;
- DDR_rdc_din <= DDR_rdc_din_i ;
- DDR_rdc_full_i <= DDR_rdc_full ;
-
- DDR_FIFO_RdEn <= DDR_FIFO_RdEn_i;
-
-
- -- Register address for read
- Regs_RdAddr <= Regs_RdAddr_i;
-
- -- Memory buffer write port
- mbuf_Din <= mbuf_Din_i;
- mbuf_WE <= mbuf_WE_i;
- mbuf_Full_i <= mbuf_Full;
- mbuf_aFull_i <= mbuf_aFull;
- mbuf_UserFull_i <= mbuf_UserFull;
-
-
- --
- Regs_RdAddr_i <= Address_var(C_EP_AWIDTH-1 downto 0);
-
------------------------------------------------------
--- Synchronous Delay: mbuf_aFull
---
- Synchron_Delay_mbuf_aFull:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
- mbuf_aFull_r1 <= mbuf_aFull_i or mbuf_Full_i
- or mbuf_UserFull_i;
- end if;
- end process;
-
-
--- ---------------------------------------------------
--- State Machine: Tx Memory read control
---
- mR_FSM_Control:
- process ( trn_clk, mReader_Rst_n)
- begin
- if mReader_Rst_n = '0' then
- DDR_rdc_sof_i <= '0';
- DDR_rdc_eof_i <= '0';
- DDR_rdc_v_i <= '0';
- DDR_rdc_Shift_i <= '0';
- DDR_rdc_din_i <= (OTHERS=>'0');
-
- eb_FIFO_Hit <= '0';
- eb_FIFO_re_i <= '0';
- eb_FIFO_RdEn_Mask <= '0';
-
- DDR_FIFO_Hit <= '0';
- DDR_FIFO_RdEn_i <= '0';
- DDR_FIFO_RdEn_Mask <= '0';
- Regs_Hit <= '0';
- Regs_RdEn <= '0';
- regs_Rd_Counter <= (Others=>'0');
- DDR_Rd_Counter <= (Others=>'0');
- DDR_Rd_Cntr_eq_One <= '0';
-
- ebFIFO_Rd_Counter <= (Others=>'0');
- ebFIFO_Rd_Cntr_eq_Two<= '0';
-
- regs_Rd_Cntr_eq_One <= '0';
- regs_Rd_Cntr_eq_Two <= '0';
-
- Shift_1st_QWord_k <= '0';
- is_CplD_k <= '0';
- may_be_MWr_k <= '0';
- TRem_n_last_QWord <= '0';
-
- Address_var <= (Others=>'1');
- TxTLP_eof_n <= '1';
-
- TO_Cnt_Rst <= '0';
-
- RdCmd_Ack_i <= '0';
- TxMReader_State <= St_mR_Idle;
-
- elsif trn_clk'event and trn_clk = '1' then
-
- case TxMReader_State is
-
- when St_mR_Idle =>
- if RdCmd_Req_i='0' then
- TxMReader_State <= St_mR_Idle;
- eb_FIFO_Hit <= '0';
- Regs_Hit <= '0';
- Regs_RdEn <= '0';
- TxTLP_eof_n <= '1';
- Address_var <= (Others=>'1');
- RdCmd_Ack_i <= '0';
- is_CplD_k <= '0';
- may_be_MWr_k <= '0';
- else
- RdCmd_Ack_i <= '1';
- Shift_1st_QWord_k <= Shift_1st_QWord;
- TRem_n_last_QWord <= Shift_1st_QWord xor RdNumber(0);
- is_CplD_k <= is_CplD;
- may_be_MWr_k <= not is_CplD;
- TxTLP_eof_n <= '1';
- if BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
- = CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
- then
- eb_FIFO_Hit <= '0';
- DDR_FIFO_Hit <= '1';
- Regs_Hit <= '0';
- Regs_RdEn <= '0';
- Address_var <= Address_var;
- TxMReader_State <= St_mR_DDR_A;
- elsif BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
- = CONV_STD_LOGIC_VECTOR(CINT_REGS_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
- then
- eb_FIFO_Hit <= '0';
- DDR_FIFO_Hit <= '0';
- Regs_Hit <= '1';
- Regs_RdEn <= '1';
- if Shift_1st_QWord='1' then
- Address_var(C_EP_AWIDTH-1 downto 0) <= StartAddr(C_EP_AWIDTH-1 downto 0) - "100";
- else
- Address_var(C_EP_AWIDTH-1 downto 0) <= StartAddr(C_EP_AWIDTH-1 downto 0);
- end if;
- TxMReader_State <= St_mR_CmdLatch;
- elsif BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
- = CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
- then
- eb_FIFO_Hit <= '1';
- DDR_FIFO_Hit <= '0';
- Regs_Hit <= '0';
- Regs_RdEn <= '0';
- Address_var <= Address_var;
- TxMReader_State <= St_mR_DDR_C;
- else
- eb_FIFO_Hit <= '0';
- DDR_FIFO_Hit <= '0';
- Regs_Hit <= '0';
- Regs_RdEn <= '0';
- Address_var <= Address_var;
- TxMReader_State <= St_mR_CmdLatch;
- end if;
-
- end if;
-
-
- when St_mR_DDR_A =>
- DDR_rdc_sof_i <= '1';
- DDR_rdc_eof_i <= '0';
- DDR_rdc_v_i <= '1';
- DDR_rdc_Shift_i <= Shift_1st_QWord_k;
- DDR_rdc_din_i <= C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_TLP_FLD_WIDTH_OF_LENG+2+32)
- & RdNumber & "00"
- & StartAddr(C_DBUS_WIDTH-1-32 downto 0);
- Regs_RdEn <= '0';
- DDR_FIFO_RdEn_i <= '0';
- TxTLP_eof_n <= '1';
- RdCmd_Ack_i <= '1';
- TxMReader_State <= St_mR_DDR_C; -- St_mR_DDR_B;
-
-
- when St_mR_DDR_C =>
- DDR_rdc_sof_i <= '0';
- DDR_rdc_eof_i <= '0';
- DDR_rdc_v_i <= '0';
- DDR_rdc_din_i <= DDR_rdc_din_i;
- RdCmd_Ack_i <= '0';
- TxTLP_eof_n <= '1';
--- if DDR_FIFO_Hit='1' and DDR_FIFO_Empty='1' then
- if DDR_FIFO_Hit='1' and DDR_FIFO_Empty='1' and Tx_TimeOut_i='0' then
- TxMReader_State <= St_mR_DDR_C;
--- elsif eb_FIFO_Hit='1' and eb_FIFO_empty='1' then
- elsif eb_FIFO_Hit='1' and eb_FIFO_empty='1' and Tx_eb_TimeOut_i='0' then
- TxMReader_State <= St_mR_DDR_C;
- else
- TxMReader_State <= St_mR_CmdLatch;
- end if;
-
-
- when St_mR_CmdLatch =>
- RdCmd_Ack_i <= '0';
- if regs_Rd_Cntr_eq_One = '1' then
- Regs_RdEn <= '0';
- Address_var <= Address_var;
- TxTLP_eof_n <= '0';
- TxMReader_State <= St_mR_Last;
- elsif regs_Rd_Cntr_eq_Two = '1' then
- if Shift_1st_QWord_k='1' then
- TxMReader_State <= St_mR_Transfer;
- Regs_RdEn <= Regs_RdEn; -- '1';
- TxTLP_eof_n <= '1';
- Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
- else
- TxMReader_State <= St_mR_Last;
- Regs_RdEn <= '0';
- TxTLP_eof_n <= '0';
- Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
- end if;
- else
- Regs_RdEn <= Regs_RdEn;
- Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
- TxTLP_eof_n <= '1';
- TxMReader_State <= St_mR_Transfer;
- end if;
-
-
- when St_mR_Transfer =>
- RdCmd_Ack_i <= '0';
- if DDR_FIFO_Hit='1' and DDR_FIFO_RdEn_Mask='1' then
- Address_var <= Address_var;
- Regs_RdEn <= '0';
- TxTLP_eof_n <= '0';
- TxMReader_State <= St_mR_Last;
- elsif eb_FIFO_Hit='1' and eb_FIFO_RdEn_Mask='1' then
- Address_var <= Address_var;
- Regs_RdEn <= '0';
- TxTLP_eof_n <= '0';
- TxMReader_State <= St_mR_Last;
- elsif eb_FIFO_Hit='0' and regs_Rd_Cntr_eq_One = '1' then
- Address_var <= Address_var;
- Regs_RdEn <= '0';
- TxTLP_eof_n <= '0';
- TxMReader_State <= St_mR_Last;
- elsif eb_FIFO_Hit='0' and regs_Rd_Cntr_eq_Two = '1' then
- Address_var <= Address_var;
- Regs_RdEn <= '0';
- TxTLP_eof_n <= '0';
- TxMReader_State <= St_mR_Last;
- elsif mbuf_aFull_r1 = '1' then
- Address_var <= Address_var;
- Regs_RdEn <= '0';
- TxTLP_eof_n <= TxTLP_eof_n;
- TxMReader_State <= St_mR_Transfer;
- else
- Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
- Regs_RdEn <= Regs_Hit;
- TxTLP_eof_n <= TxTLP_eof_n;
- TxMReader_State <= St_mR_Transfer;
- end if;
-
-
- when St_mR_Last =>
- Regs_RdEn <= '0';
- DDR_FIFO_RdEn_i <= '0';
- TxTLP_eof_n <= (not DDR_FIFO_Hit) and (not eb_FIFO_Hit);
- RdCmd_Ack_i <= '0';
- TxMReader_State <= St_mR_Idle;
-
-
- when Others =>
- Address_var <= Address_var;
- eb_FIFO_Hit <= '0';
- Regs_RdEn <= '0';
- DDR_FIFO_RdEn_i <= '0';
- TxTLP_eof_n <= '1';
- RdCmd_Ack_i <= '0';
- TxMReader_State <= St_mR_Idle;
-
- end case;
-
-
- case TxMReader_State is
- when St_mR_Idle =>
- TO_Cnt_Rst <= '1';
-
- when Others =>
- TO_Cnt_Rst <= '0';
-
- end case;
-
-
- case TxMReader_State is
-
- when St_mR_Idle =>
- DDR_FIFO_RdEn_i <= '0';
- DDR_FIFO_RdEn_Mask <= '0';
-
- when Others =>
- if DDR_Rd_Cntr_eq_One = '1'
- and (DDR_FIFO_Empty='0' or Tx_TimeOut_i='1')
- and DDR_FIFO_RdEn_i='1'
- then
- DDR_FIFO_RdEn_Mask <= '1';
- DDR_FIFO_RdEn_i <= '0';
- else
- DDR_FIFO_RdEn_Mask <= DDR_FIFO_RdEn_Mask;
- DDR_FIFO_RdEn_i <= DDR_FIFO_Hit
- and not mbuf_aFull_r1
- and not DDR_FIFO_RdEn_Mask;
- end if;
- end case;
-
-
- case TxMReader_State is
-
- when St_mR_Idle =>
- eb_FIFO_re_i <= '0';
- eb_FIFO_RdEn_Mask <= '0';
-
- when Others =>
- if ebFIFO_Rd_Cntr_eq_Two = '1'
- and (eb_FIFO_empty='0' or Tx_eb_TimeOut_i='1')
- and eb_FIFO_re_i='1'
- then
- eb_FIFO_RdEn_Mask <= '1';
- eb_FIFO_re_i <= '0';
- else
- eb_FIFO_RdEn_Mask <= eb_FIFO_RdEn_Mask;
- eb_FIFO_re_i <= eb_FIFO_Hit
- and not mbuf_aFull_r1
- and not eb_FIFO_RdEn_Mask;
- end if;
- end case;
-
-
- case TxMReader_State is
-
- when St_mR_Idle =>
- if RdCmd_Req_i='1' and
- BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
- /= CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
- then
- regs_Rd_Counter <= RdNumber;
- regs_Rd_Cntr_eq_One <= RdNumber_eq_One;
- regs_Rd_Cntr_eq_Two <= RdNumber_eq_Two;
- else
- regs_Rd_Counter <= (Others=>'0');
- regs_Rd_Cntr_eq_One <= '0';
- regs_Rd_Cntr_eq_Two <= '0';
- end if;
-
- when St_mR_CmdLatch =>
- if DDR_FIFO_Hit='0' then
- if Shift_1st_QWord_k='1' then
- regs_Rd_Counter <= regs_Rd_Counter - '1';
- if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG) then
- regs_Rd_Cntr_eq_One <= '1';
- else
- regs_Rd_Cntr_eq_One <= '0';
- end if;
- if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(3, C_TLP_FLD_WIDTH_OF_LENG) then
- regs_Rd_Cntr_eq_Two <= '1';
- else
- regs_Rd_Cntr_eq_Two <= '0';
- end if;
- else
- regs_Rd_Counter <= regs_Rd_Counter - "10"; -- '1';
- if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(3, C_TLP_FLD_WIDTH_OF_LENG) then
- regs_Rd_Cntr_eq_One <= '1';
- else
- regs_Rd_Cntr_eq_One <= '0';
- end if;
- if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
- regs_Rd_Cntr_eq_Two <= '1';
- else
- regs_Rd_Cntr_eq_Two <= '0';
- end if;
- end if;
- else
- regs_Rd_Counter <= regs_Rd_Counter;
- regs_Rd_Cntr_eq_One <= regs_Rd_Cntr_eq_One;
- regs_Rd_Cntr_eq_Two <= regs_Rd_Cntr_eq_Two;
- end if;
-
- when St_mR_Transfer =>
- if DDR_FIFO_Hit='0'
- and mbuf_aFull_r1 = '0'
- then
- regs_Rd_Counter <= regs_Rd_Counter - "10"; -- '1';
- if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG) then
- regs_Rd_Cntr_eq_One <= '1';
- elsif regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG) then
- regs_Rd_Cntr_eq_One <= '1';
- elsif regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(3, C_TLP_FLD_WIDTH_OF_LENG) then
- regs_Rd_Cntr_eq_One <= '1';
- else
- regs_Rd_Cntr_eq_One <= '0';
- end if;
- if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
- regs_Rd_Cntr_eq_Two <= '1';
- else
- regs_Rd_Cntr_eq_Two <= '0';
- end if;
- else
- regs_Rd_Counter <= regs_Rd_Counter;
- regs_Rd_Cntr_eq_One <= regs_Rd_Cntr_eq_One;
- regs_Rd_Cntr_eq_Two <= regs_Rd_Cntr_eq_Two;
- end if;
-
- when Others =>
- regs_Rd_Counter <= regs_Rd_Counter;
- regs_Rd_Cntr_eq_One <= regs_Rd_Cntr_eq_One;
- regs_Rd_Cntr_eq_Two <= regs_Rd_Cntr_eq_Two;
-
- end case;
-
-
- case TxMReader_State is
- when St_mR_Idle =>
- if RdCmd_Req_i='1' and
- BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
- = CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
- then
- if RdNumber(0)='1' then
- DDR_Rd_Counter <= RdNumber + '1';
- DDR_Rd_Cntr_eq_One <= RdNumber_eq_One;
- elsif Shift_1st_QWord='1' then
- DDR_Rd_Counter <= RdNumber + "10";
- DDR_Rd_Cntr_eq_One <= RdNumber_eq_One;
- else
- DDR_Rd_Counter <= RdNumber;
- DDR_Rd_Cntr_eq_One <= RdNumber_eq_One or RdNumber_eq_Two;
- end if;
- else
- DDR_Rd_Counter <= (Others=>'0');
- DDR_Rd_Cntr_eq_One <= '0';
- end if;
-
- when Others =>
- if ((DDR_FIFO_Empty='0' or Tx_TimeOut_i='1') and DDR_FIFO_RdEn_i='1')
- then
- DDR_Rd_Counter <= DDR_Rd_Counter - "10"; -- '1';
- if DDR_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
- DDR_Rd_Cntr_eq_One <= '1';
- else
- DDR_Rd_Cntr_eq_One <= '0';
- end if;
- else
- DDR_Rd_Counter <= DDR_Rd_Counter;
- DDR_Rd_Cntr_eq_One <= DDR_Rd_Cntr_eq_One;
- end if;
-
- end case;
-
-
- case TxMReader_State is
- when St_mR_Idle =>
- if RdCmd_Req_i='1' and
- BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
- = CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
- then
- if RdNumber_eq_One='1' then
- ebFIFO_Rd_Counter <= RdNumber + '1';
- ebFIFO_Rd_Cntr_eq_Two <= '1';
- ebFIFO_Rd_1DW <= '1';
- else
- ebFIFO_Rd_Counter <= RdNumber;
- ebFIFO_Rd_Cntr_eq_Two <= RdNumber_eq_Two; -- or RdNumber_eq_One;
- ebFIFO_Rd_1DW <= '0';
- end if;
- else
- ebFIFO_Rd_Counter <= (Others=>'0');
- ebFIFO_Rd_Cntr_eq_Two <= '0';
- ebFIFO_Rd_1DW <= '0';
- end if;
-
- when Others =>
- ebFIFO_Rd_1DW <= ebFIFO_Rd_1DW;
- if (eb_FIFO_empty='0' or Tx_eb_TimeOut_i='1') and eb_FIFO_re_i='1'
- then
- ebFIFO_Rd_Counter <= ebFIFO_Rd_Counter - "10"; -- '1';
- if ebFIFO_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
- ebFIFO_Rd_Cntr_eq_Two <= '1';
- else
- ebFIFO_Rd_Cntr_eq_Two <= '0';
- end if;
- else
- ebFIFO_Rd_Counter <= ebFIFO_Rd_Counter;
- ebFIFO_Rd_Cntr_eq_Two <= ebFIFO_Rd_Cntr_eq_Two;
- end if;
-
- end case;
-
- end if;
- end process;
-
-
------------------------------------------------------
--- Synchronous Delay: mbuf_writes
---
- Synchron_Delay_mbuf_writes:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
- Regs_Write_mbuf_r1 <= Regs_RdEn;
- Regs_Write_mbuf_r2 <= Regs_Write_mbuf_r1;
- Regs_Write_mbuf_r3 <= Regs_Write_mbuf_r2;
-
- DDR_FIFO_Write_mbuf_r1 <= DDR_FIFO_RdEn_i and (not DDR_FIFO_Empty or Tx_TimeOut_i);
- DDR_FIFO_Write_mbuf_r2 <= DDR_FIFO_Write_mbuf_r1;
- DDR_FIFO_Write_mbuf_r3 <= DDR_FIFO_Write_mbuf_r2;
-
- eb_FIFO_Write_mbuf <= eb_FIFO_re_i and (not eb_FIFO_empty or Tx_eb_TimeOut_i);
- eb_FIFO_Write_mbuf_r1 <= eb_FIFO_Write_mbuf;
- eb_FIFO_Write_mbuf_r2 <= eb_FIFO_Write_mbuf_r1;
-
- eb_FIFO_RdEn_Mask_r1 <= eb_FIFO_RdEn_Mask;
- eb_FIFO_RdEn_Mask_r2 <= eb_FIFO_RdEn_Mask_r1;
-
- end if;
- end process;
-
-
---------------------------------------------------------------------------
--- Wires to be OR'ed to build mbuf_Din
---------------------------------------------------------------------------
-
- eb_FIFO_Dout_wire <= eb_FIFO_qout_r1 when (eb_FIFO_Hit='1' and Shift_1st_QWord_k='0')
- else eb_FIFO_qout_shift when (eb_FIFO_Hit='1' and Shift_1st_QWord_k='1')
- else (OTHERS=>'0');
- DDR_Dout_wire <= DDR_FIFO_RdQout when DDR_FIFO_Hit='1' else (OTHERS=>'0');
- Regs_RdQout_wire <= Regs_RdQout when Regs_Hit='1' else (OTHERS=>'0');
-
- mbuf_Din_wire_OR <= eb_FIFO_Dout_wire or DDR_Dout_wire or Regs_RdQout_wire;
-
------------------------------------------------------
--- Synchronous Delay: mbuf_WE
---
- Synchron_Delay_mbuf_WE:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
- mbuf_WE_i <= DDR_FIFO_Write_mbuf_r1
- or Regs_Write_mbuf_r2
- or (eb_FIFO_Write_mbuf_r1 or (Shift_1st_QWord_k and eb_FIFO_RdEn_Mask_rise_r1))
- ;
- end if;
- end process;
-
-
------------------------------------------------------
--- Synchronous Delay: TxTLP_eof_n
---
- Synchron_Delay_TxTLP_eof_n:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
- TxTLP_eof_n_r1 <= TxTLP_eof_n;
--- TxTLP_eof_n_r2 <= TxTLP_eof_n_r1;
- end if;
- end process;
-
--- eb_FIFO_qout_swapped <= eb_FIFO_qout(C_DBUS_WIDTH/2-1 downto 0) & eb_FIFO_qout(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2);
- eb_FIFO_qout_swapped <= eb_FIFO_qout(C_DBUS_WIDTH/2+7 downto C_DBUS_WIDTH/2)
- & eb_FIFO_qout(C_DBUS_WIDTH/2+15 downto C_DBUS_WIDTH/2+8)
- & eb_FIFO_qout(C_DBUS_WIDTH/2+23 downto C_DBUS_WIDTH/2+16)
- & eb_FIFO_qout(C_DBUS_WIDTH/2+31 downto C_DBUS_WIDTH/2+24)
-
- & eb_FIFO_qout(7 downto 0)
- & eb_FIFO_qout(15 downto 8)
- & eb_FIFO_qout(23 downto 16)
- & eb_FIFO_qout(31 downto 24)
- ;
-
------------------------------------------------------
--- Synchronous Delay: eb_FIFO_qout
---
- Synchron_Delay_eb_FIFO_qout:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
- eb_FIFO_RdEn_Mask_rise <= eb_FIFO_RdEn_Mask and not eb_FIFO_RdEn_Mask_r1;
- eb_FIFO_RdEn_Mask_rise_r1 <= eb_FIFO_RdEn_Mask_rise;
- eb_FIFO_RdEn_Mask_rise_r2 <= eb_FIFO_RdEn_Mask_rise_r1;
- eb_FIFO_qout_r1 <= eb_FIFO_qout_swapped;
- eb_FIFO_qout_shift <= eb_FIFO_qout_r1(C_DBUS_WIDTH/2-1 downto 0)
- & eb_FIFO_qout_swapped(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2);
- end if;
- end process;
-
------------------------------------------------------
--- Synchronous Delay: mbuf_Din
---
- Synchron_Delay_mbuf_Din:
- process ( trn_clk, mReader_Rst_n)
- begin
- if mReader_Rst_n = '0' then
- mbuf_Din_i <= (C_DBUS_WIDTH=>'1', Others=>'0');
-
- elsif trn_clk'event and trn_clk = '1' then
- if Tx_TimeOut_i='1' and DDR_FIFO_Hit='1' then
- mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= (OTHERS=>'1');
- elsif Tx_eb_TimeOut_i='1' and eb_FIFO_Hit='1' and is_CplD_k='1' then
- mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= (OTHERS=>'1');
- elsif Tx_eb_TimeOut_i='1' and eb_FIFO_Hit='1' and may_be_MWr_k='1' then
- mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= (OTHERS=>'1');
- else
- mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= Endian_Invert_64(mbuf_Din_wire_OR);
- end if;
-
- if DDR_FIFO_Hit='1' then
- mbuf_Din_i(C_DBUS_WIDTH) <= not DDR_FIFO_RdEn_Mask;
- mbuf_Din_i(70) <= TRem_n_last_QWord;
- elsif eb_FIFO_Hit='1' then
- if Shift_1st_QWord_k='1' and ebFIFO_Rd_1DW='0' then
- mbuf_Din_i(C_DBUS_WIDTH) <= not eb_FIFO_RdEn_Mask_r2;
- else
- mbuf_Din_i(C_DBUS_WIDTH) <= not eb_FIFO_RdEn_Mask_r1;
- end if;
- mbuf_Din_i(70) <= TRem_n_last_QWord;
- else
- mbuf_Din_i(C_DBUS_WIDTH) <= TxTLP_eof_n_r1;
- mbuf_Din_i(70) <= TRem_n_last_QWord;
- end if;
- end if;
- end process;
-
-
------------------------------------------------------
--- Synchronous: Time-out counter
---
- Synchron_TimeOut_Counter:
- process ( trn_clk, TO_Cnt_Rst )
- begin
- if TO_Cnt_Rst='1' then
- TimeOut_Counter <= (OTHERS=>'0');
- elsif trn_clk'event and trn_clk = '1' then
- TimeOut_Counter(21 downto 0) <= TimeOut_Counter(21 downto 0) + '1';
- end if;
- end process;
-
------------------------------------------------------
--- Synchronous: Tx_TimeOut
---
- SynchOUT_Tx_TimeOut:
- process ( trn_clk, mReader_Rst_n )
- begin
- if mReader_Rst_n='0' then
- Tx_TimeOut_i <= '0';
- elsif trn_clk'event and trn_clk = '1' then
- if TimeOut_Counter(21 downto 6)=X"FFFF" then
--- if TimeOut_Counter(4 downto 1)=X"F" then
- Tx_TimeOut_i <= '1';
- else
- Tx_TimeOut_i <= Tx_TimeOut_i;
- end if;
- end if;
- end process;
-
------------------------------------------------------
--- Synchronous: Tx_eb_TimeOut
---
- SynchOUT_Tx_eb_TimeOut:
- process ( trn_clk, mReader_Rst_n )
- begin
- if mReader_Rst_n='0' then
- Tx_eb_TimeOut_i <= '0';
- elsif trn_clk'event and trn_clk = '1' then
--- if TimeOut_Counter(3 downto 0)=X"F" then
- if TimeOut_Counter(6 downto 3)=X"F"
- and is_CplD_k='1'
- then
- Tx_eb_TimeOut_i <= '1';
- elsif TimeOut_Counter(8 downto 5)=X"F"
- and may_be_MWr_k='1'
- then
- Tx_eb_TimeOut_i <= '1';
- else
- Tx_eb_TimeOut_i <= Tx_eb_TimeOut_i;
- end if;
- end if;
- end process;
-
-end architecture Behavioral;
Index: branches/Virtex6/ML605/protocol_if.vhd
===================================================================
--- branches/Virtex6/ML605/protocol_if.vhd (revision 9)
+++ branches/Virtex6/ML605/protocol_if.vhd (nonexistent)
@@ -1,612 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: ziti
--- Engineer: wgao
---
--- Create Date: 17:01:32 19 Jun 2009
--- Design Name:
--- Module Name: protocol_IF - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.abb64Package.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity protocol_IF is
--- Generic (
--- C_PRO_DAQ_WIDTH : integer := 16 ;
--- C_PRO_DLM_WIDTH : integer := 4 ;
--- C_PRO_CTL_WIDTH : integer := 16
--- );
- Port (
-
- -- DAQ Tx
- data2send_start : OUT std_logic;
- data2send_end : OUT std_logic;
- data2send : OUT std_logic_vector(64-1 downto 0);
- crc_error_send : OUT std_logic;
- data2send_stop : IN std_logic;
-
- -- DAQ Rx
- data_rec_start : IN std_logic;
- data_rec_end : IN std_logic;
- data_rec : IN std_logic_vector(64-1 downto 0);
- crc_error_rec : IN std_logic;
- data_rec_stop : OUT std_logic;
-
--- -- [dg] DAQ Rx
--- dg_data_rec_start : IN std_logic;
--- dg_data_rec_end : IN std_logic;
--- dg_data_rec : IN std_logic_vector(16-1 downto 0);
--- dg_crc_error_rec : IN std_logic;
-
- -- CTL Tx
- ctrl2send_start : OUT std_logic;
- ctrl2send_end : OUT std_logic;
- ctrl2send : OUT std_logic_vector(16-1 downto 0);
- ctrl2send_stop : IN std_logic;
-
- -- CTL Rx
- ctrl_rec_start : IN std_logic;
- ctrl_rec_end : IN std_logic;
- ctrl_rec : IN std_logic_vector(16-1 downto 0);
- ctrl_rec_stop : OUT std_logic;
-
--- -- [dg] CTL Rx
--- dg_ctrl_rec_start : IN std_logic;
--- dg_ctrl_rec_end : IN std_logic;
--- dg_ctrl_rec : IN std_logic_vector(16-1 downto 0);
-
- -- DLM Tx
- dlm2send_va : OUT std_logic;
- dlm2send_type : OUT std_logic_vector(4-1 downto 0);
-
- -- DLM Rx
- dlm_rec_va : IN std_logic;
- dlm_rec_type : IN std_logic_vector(4-1 downto 0);
-
--- -- [dg] DLM Rx
--- dg_dlm_rec_va : IN std_logic;
--- dg_dlm_rec_type : IN std_logic_vector(4-1 downto 0);
-
- -- Common signals
- link_tx_clk : IN std_logic;
- link_rx_clk : IN std_logic;
- link_active : IN std_logic_vector(2-1 downto 0);
- protocol_clk : OUT std_logic;
- protocol_res_n : OUT std_logic;
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-
- -- Fabric side: DAQ Rx
- daq_rv : IN std_logic;
- daq_rsof : IN std_logic;
- daq_reof : IN std_logic;
- daq_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- daq_rstop : OUT std_logic;
-
- -- Fabric side: DAQ Tx
- daq_tv : OUT std_logic;
- daq_tsof : OUT std_logic;
- daq_teof : OUT std_logic;
- daq_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- daq_tstop : IN std_logic;
-
- -- Fabric side: CTL Rx
- ctl_rv : IN std_logic;
- ctl_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
- ctl_rstop : OUT std_logic;
-
- -- Fabric side: CTL Tx
- ctl_ttake : IN std_logic;
- ctl_tv : OUT std_logic;
- ctl_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
- ctl_tstop : IN std_logic;
-
- ctl_reset : IN std_logic;
- ctl_status : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Fabric side: DLM Tx
- dlm_tv : IN std_logic;
- dlm_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Fabric side: DLM Rx
- dlm_rv : OUT std_logic;
- dlm_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Interrupter triggers
- DAQ_irq : OUT std_logic;
- CTL_irq : OUT std_logic;
- DLM_irq : OUT std_logic;
-
- -- Data generator table write port
- tab_sel : IN STD_LOGIC;
- tab_we : IN STD_LOGIC_VECTOR (2-1 downto 0);
- tab_wa : IN STD_LOGIC_VECTOR (12-1 downto 0);
- tab_wd : IN STD_LOGIC_VECTOR (64-1 downto 0);
-
- -- DG control/status signal
- dg_running : OUT STD_LOGIC;
- dg_mask : IN STD_LOGIC;
- dg_rst : IN STD_LOGIC;
-
- -- DG debug signal
- daq_start_led : OUT STD_LOGIC;
-
- -- Fabric side: Common signals
- trn_clk : IN std_logic;
- protocol_link_act : OUT std_logic_vector(2-1 downto 0);
- protocol_rst : IN std_logic
-
- );
-end entity protocol_IF;
-
-
-architecture Behavioral of protocol_IF is
-
- -- Data generator
- COMPONENT abb_dgen
- PORT (
- -- Data generator table write port
- tab_sel : IN STD_LOGIC;
- tab_we : IN STD_LOGIC_VECTOR (2-1 downto 0);
- tab_wa : IN STD_LOGIC_VECTOR (12-1 downto 0);
- tab_wd : IN STD_LOGIC_VECTOR (64-1 downto 0);
-
-
- -- DAQ Rx
- data_rec_start : OUT std_logic;
- data_rec_end : OUT std_logic;
- data_rec : OUT std_logic_vector(64-1 downto 0);
- crc_error_rec : OUT std_logic;
- data_rec_stop : IN std_logic;
-
- -- CTL Rx
- ctrl_rec_start : OUT std_logic;
- ctrl_rec_end : OUT std_logic;
- ctrl_rec : OUT std_logic_vector(16-1 downto 0);
- ctrl_rec_stop : IN std_logic;
-
- -- DLM Rx
- dlm_rec_va : OUT std_logic;
- dlm_rec_type : OUT std_logic_vector(4-1 downto 0);
-
- -- status signal
- dg_running : OUT STD_LOGIC;
- daq_start_led : OUT STD_LOGIC;
-
- -- must signals
- dg_clk : IN STD_LOGIC;
- dg_mask : IN STD_LOGIC;
- dg_rst : IN STD_LOGIC
- );
- END COMPONENT;
-
-
- COMPONENT class_daq
- PORT(
- -- DAQ Tx
- data2send_start : OUT std_logic;
- data2send_end : OUT std_logic;
- data2send : OUT std_logic_vector(64-1 downto 0);
- crc_error_send : OUT std_logic;
- data2send_stop : IN std_logic;
-
- -- DAQ Rx
- data_rec_start : IN std_logic;
- data_rec_end : IN std_logic;
- data_rec : IN std_logic_vector(64-1 downto 0);
- crc_error_rec : IN std_logic;
- data_rec_stop : OUT std_logic;
-
- -- Common signals
- link_tx_clk : IN std_logic;
- link_rx_clk : IN std_logic;
-
-
- -- Fabric side: DAQ Rx
- daq_rv : IN std_logic;
- daq_rsof : IN std_logic;
- daq_reof : IN std_logic;
- daq_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- daq_rstop : OUT std_logic;
-
- -- Fabric side: DAQ Tx
- daq_tv : OUT std_logic;
- daq_tsof : OUT std_logic;
- daq_teof : OUT std_logic;
- daq_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- daq_tstop : IN std_logic;
-
- -- Interrupter trigger
- DAQ_irq : OUT std_logic;
-
- -- Fabric side: Common signals
- trn_clk : IN std_logic;
- protocol_rst : IN std_logic
- );
- END COMPONENT;
-
- COMPONENT class_ctl
- PORT(
- -- CTL Tx
- ctrl2send_start : OUT std_logic;
- ctrl2send_end : OUT std_logic;
- ctrl2send : OUT std_logic_vector(16-1 downto 0);
- ctrl2send_stop : IN std_logic;
-
- -- CTL Rx
- ctrl_rec_start : IN std_logic;
- ctrl_rec_end : IN std_logic;
- ctrl_rec : IN std_logic_vector(16-1 downto 0);
- ctrl_rec_stop : OUT std_logic;
-
- -- Common signals
- link_active : IN std_logic_vector(2-1 downto 0);
- link_tx_clk : IN std_logic;
- link_rx_clk : IN std_logic;
-
-
- -- Fabric side: CTL Rx
- ctl_rv : IN std_logic;
- ctl_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
- ctl_rstop : OUT std_logic;
-
- -- Fabric side: CTL Tx
- ctl_ttake : IN std_logic;
- ctl_tv : OUT std_logic;
- ctl_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
- ctl_tstop : IN std_logic;
-
- -- Interrupter trigger
- CTL_irq : OUT std_logic;
- ctl_status : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Fabric side: Common signals
- trn_clk : IN std_logic;
- protocol_rst : IN std_logic
- );
- END COMPONENT;
-
- COMPONENT class_dlm
- PORT(
- -- DLM Tx
- dlm2send_va : OUT std_logic;
- dlm2send_type : OUT std_logic_vector(4-1 downto 0);
-
- -- DLM Rx
- dlm_rec_va : IN std_logic;
- dlm_rec_type : IN std_logic_vector(4-1 downto 0);
-
- -- Common signals
- link_tx_clk : IN std_logic;
- link_rx_clk : IN std_logic;
-
-
- -- Fabric side: DLM Rx
- dlm_tv : IN std_logic;
- dlm_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Fabric side: DLM Tx
- dlm_rv : OUT std_logic;
- dlm_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-
- -- Interrupter trigger
- DLM_irq : OUT std_logic;
-
- -- Fabric side: Common signals
- trn_clk : IN std_logic;
- protocol_rst : IN std_logic
- );
- END COMPONENT;
-
- -- Protocol module reset
- signal protocol_link_act_i : std_logic_vector(2-1 downto 0);
-
- -- Flow control signals
- signal data_rec_stop_i : std_logic;
- signal ctrl_rec_stop_i : std_logic;
-
-
- -- DAQ Tx
- signal data2send_start_i : std_logic;
- signal data2send_end_i : std_logic;
- signal data2send_i : std_logic_vector(64-1 downto 0);
- signal crc_error_send_i : std_logic;
- signal data2send_stop_i : std_logic;
-
- -- CTL Tx
- signal ctrl2send_start_i : std_logic;
- signal ctrl2send_end_i : std_logic;
- signal ctrl2send_i : std_logic_vector(16-1 downto 0);
- signal ctrl2send_stop_i : std_logic;
-
- -- DLM Tx
- signal dlm2send_va_i : std_logic;
- signal dlm2send_type_i : std_logic_vector(4-1 downto 0);
-
- -- [dg] DAQ Rx
- signal dg_data_rec_start : std_logic;
- signal dg_data_rec_end : std_logic;
- signal dg_data_rec : std_logic_vector(64-1 downto 0);
- signal dg_crc_error_rec : std_logic;
-
- -- [dg] CTL Rx
- signal dg_ctrl_rec_start : std_logic;
- signal dg_ctrl_rec_end : std_logic;
- signal dg_ctrl_rec : std_logic_vector(16-1 downto 0);
-
- -- [dg] DLM Rx
- signal dg_dlm_rec_va : std_logic;
- signal dg_dlm_rec_type : std_logic_vector(4-1 downto 0);
-
- -- DAQ Rx wire
- signal data_rec_start_i : std_logic;
- signal data_rec_end_i : std_logic;
- signal data_rec_i : std_logic_vector(64-1 downto 0);
- signal crc_error_rec_i : std_logic;
-
- -- CTL Rx wire
- signal ctrl_rec_start_i : std_logic;
- signal ctrl_rec_end_i : std_logic;
- signal ctrl_rec_i : std_logic_vector(16-1 downto 0);
-
- -- DLM Rx wire
- signal dlm_rec_va_i : std_logic;
- signal dlm_rec_type_i : std_logic_vector(4-1 downto 0);
-
-
-begin
-
- protocol_clk <= trn_clk;
- protocol_res_n <= not protocol_rst;
- protocol_link_act <= protocol_link_act_i;
-
- data2send_start <= (data2send_start_i or dg_data_rec_start);
- data2send_end <= (data2send_end_i or dg_data_rec_end );
- data2send <= (data2send_i or dg_data_rec );
- crc_error_send <= (crc_error_send_i or dg_crc_error_rec );
- data2send_stop_i <= data2send_stop ;
-
- data_rec_start_i <= data_rec_start ;
- data_rec_end_i <= data_rec_end ;
- data_rec_i <= data_rec ;
- crc_error_rec_i <= crc_error_rec ;
- data_rec_stop <= data_rec_stop_i;
-
- ctrl2send_start <= (ctrl2send_start_i or dg_ctrl_rec_start );
- ctrl2send_end <= (ctrl2send_end_i or dg_ctrl_rec_end );
- ctrl2send <= (ctrl2send_i or dg_ctrl_rec );
- ctrl2send_stop_i <= ctrl2send_stop ;
-
- ctrl_rec_start_i <= ctrl_rec_start ;
- ctrl_rec_end_i <= ctrl_rec_end ;
- ctrl_rec_i <= ctrl_rec ;
- ctrl_rec_stop <= ctrl_rec_stop_i;
-
- dlm2send_va <= (dlm2send_va_i or dg_dlm_rec_va );
- dlm2send_type <= (dlm2send_type_i or dg_dlm_rec_type );
-
- dlm_rec_va_i <= dlm_rec_va ;
- dlm_rec_type_i <= dlm_rec_type ;
-
-
- -- Protocol link active signal register
- Synch_protocol_link_act:
- process (trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
- protocol_link_act_i <= link_active;
- end if;
- end process;
-
-
- -- Data generator implementation
- Gen_DataGen: if IMP_DATA_GENERATOR generate
-
- data_generator_0:
- abb_dgen
- port map (
- -- Data generator table write port
- tab_sel => '1' , -- IN STD_LOGIC;
- tab_we => tab_we , -- IN STD_LOGIC_VECTOR (8-1 downto 0);
- tab_wa => tab_wa , -- IN STD_LOGIC_VECTOR (12-1 downto 0);
- tab_wd => tab_wd , -- IN STD_LOGIC_VECTOR (64-1 downto 0);
-
- -- DAQ Rx
- data_rec_start => dg_data_rec_start , -- OUT std_logic;
- data_rec_end => dg_data_rec_end , -- OUT std_logic;
- data_rec => dg_data_rec , -- OUT std_logic_vector(16-1 downto 0);
- crc_error_rec => dg_crc_error_rec , -- OUT std_logic;
- data_rec_stop => data_rec_stop_i , -- IN std_logic;
-
- -- CTL Rx
- ctrl_rec_start => dg_ctrl_rec_start , -- OUT std_logic;
- ctrl_rec_end => dg_ctrl_rec_end , -- OUT std_logic;
- ctrl_rec => dg_ctrl_rec , -- OUT std_logic_vector(16-1 downto 0);
- ctrl_rec_stop => ctrl_rec_stop_i , -- IN std_logic;
-
- -- DLM Rx
- dlm_rec_va => dg_dlm_rec_va , -- OUT std_logic;
- dlm_rec_type => dg_dlm_rec_type , -- OUT std_logic_vector(4-1 downto 0);
-
- -- status signals
- dg_running => dg_running , -- OUT STD_LOGIC;
- daq_start_led => daq_start_led , -- OUT STD_LOGIC;
-
- -- common signals
- dg_clk => trn_clk , -- IN STD_LOGIC;
- dg_mask => dg_mask , -- IN STD_LOGIC;
- dg_rst => dg_rst -- IN STD_LOGIC
- );
-
- end generate;
-
-
- -- No data generator implementation
- NotGen_DataGen: if not IMP_DATA_GENERATOR generate
-
- -- debug signal
- daq_start_led <= '0';
-
- -- DAQ Rx
- dg_data_rec_start <= '0';
- dg_data_rec_end <= '0';
- dg_data_rec <= (OTHERS=>'0');
- dg_crc_error_rec <= '0';
-
- -- CTL Rx
- dg_ctrl_rec_start <= '0';
- dg_ctrl_rec_end <= '0';
- dg_ctrl_rec <= (OTHERS=>'0');
-
- -- DLM Rx
- dg_dlm_rec_va <= '0';
- dg_dlm_rec_type <= (OTHERS=>'0');
-
- end generate;
-
-
-
- module_class_daq:
- class_daq
- PORT MAP(
- -- DAQ Tx
- data2send_start => data2send_start_i , -- OUT std_logic;
- data2send_end => data2send_end_i , -- OUT std_logic;
- data2send => data2send_i , -- OUT std_logic_vector(16-1 downto 0);
- crc_error_send => crc_error_send_i , -- OUT std_logic;
- data2send_stop => data2send_stop_i , -- IN std_logic;
-
- -- DAQ Rx
- data_rec_start => data_rec_start_i , -- IN std_logic;
- data_rec_end => data_rec_end_i , -- IN std_logic;
- data_rec => data_rec_i , -- IN std_logic_vector(16-1 downto 0);
- crc_error_rec => crc_error_rec_i , -- IN std_logic;
- data_rec_stop => data_rec_stop_i , -- OUT std_logic;
-
- -- Common signals
- link_tx_clk => link_tx_clk , -- IN std_logic;
- link_rx_clk => link_tx_clk , -- IN std_logic;
-
-
- -- Fabric side - DAQ Rx
- daq_rv => daq_rv , -- IN std_logic;
- daq_rsof => daq_rsof , -- IN std_logic;
- daq_reof => daq_reof , -- IN std_logic;
- daq_rd => daq_rd , -- IN std_logic_vector(64-1 downto 0);
- daq_rstop => daq_rstop , -- OUT std_logic;
-
- -- Fabric side - DAQ Tx
- daq_tv => daq_tv , -- OUT std_logic;
- daq_tsof => daq_tsof , -- OUT std_logic;
- daq_teof => daq_teof , -- OUT std_logic;
- daq_td => daq_td , -- OUT std_logic_vector(64-1 downto 0);
- daq_tstop => daq_tstop , -- IN std_logic;
-
- -- Interrupter trigger
- DAQ_irq => DAQ_irq , -- OUT std_logic;
-
- -- Fabric side - Common signals
- trn_clk => trn_clk , -- IN std_logic;
- protocol_rst => protocol_rst -- IN std_logic
- );
-
-
-
- module_class_ctl:
- class_ctl
- PORT MAP(
- -- CTL Tx
- ctrl2send_start => ctrl2send_start_i , -- OUT std_logic;
- ctrl2send_end => ctrl2send_end_i , -- OUT std_logic;
- ctrl2send => ctrl2send_i , -- OUT std_logic_vector(32-1 downto 0);
- ctrl2send_stop => ctrl2send_stop_i , -- IN std_logic;
-
- -- CTL Rx
- ctrl_rec_start => ctrl_rec_start_i , -- IN std_logic;
- ctrl_rec_end => ctrl_rec_end_i , -- IN std_logic;
- ctrl_rec => ctrl_rec_i , -- IN std_logic_vector(32-1 downto 0);
- ctrl_rec_stop => ctrl_rec_stop_i , -- OUT std_logic;
-
- -- Common signals
- link_active => link_active , -- IN std_logic_vector(2-1 downto 0);
- link_tx_clk => link_tx_clk , -- IN std_logic;
- link_rx_clk => link_tx_clk , -- IN std_logic;
-
-
- -- Fabric side - CTL Rx
- ctl_rv => ctl_rv , -- IN std_logic;
- ctl_rd => ctl_rd , -- IN std_logic_vector(32-1 downto 0);
- ctl_rstop => ctl_rstop , -- OUT std_logic;
-
- -- Fabric side - CTL Tx
- ctl_ttake => ctl_ttake , -- IN std_logic;
- ctl_tv => ctl_tv , -- OUT std_logic;
- ctl_td => ctl_td , -- OUT std_logic_vector(32-1 downto 0);
- ctl_tstop => ctl_tstop , -- IN std_logic;
-
- -- Interrupter trigger
- CTL_irq => CTL_irq , -- OUT std_logic;
- ctl_status => ctl_status , -- OUT std_logic_vector(32-1 downto 0);
-
- -- Fabric side - Common signals
- trn_clk => trn_clk , -- IN std_logic;
- protocol_rst => ctl_reset -- IN std_logic
-
- );
-
-
- module_class_dlm:
- class_dlm
- PORT MAP(
- -- DLM Tx
- dlm2send_va => dlm2send_va_i , -- OUT std_logic;
- dlm2send_type => dlm2send_type_i , -- OUT std_logic_vector(4-1 downto 0);
-
- -- DLM Rx
- dlm_rec_va => dlm_rec_va_i , -- IN std_logic;
- dlm_rec_type => dlm_rec_type_i , -- IN std_logic_vector(4-1 downto 0);
-
- -- Common signals
- link_tx_clk => link_tx_clk , -- IN std_logic;
- link_rx_clk => link_tx_clk , -- IN std_logic;
-
-
- -- Fabric side - DLM Tx
- dlm_tv => dlm_tv , -- IN std_logic;
- dlm_td => dlm_td , -- IN std_logic_vector(4-1 downto 0);
-
- -- Fabric side - DLM Rx
- dlm_rv => dlm_rv , -- OUT std_logic;
- dlm_rd => dlm_rd , -- OUT std_logic_vector(4-1 downto 0);
-
- -- Interrupter trigger
- DLM_irq => DLM_irq , -- OUT std_logic;
-
- -- Fabric side - Common signals
- trn_clk => trn_clk , -- IN std_logic;
- protocol_rst => protocol_rst -- IN std_logic
-
- );
-
-
-end architecture Behavioral;
Index: branches/Virtex6/ML605/RxIn_Delays.vhd
===================================================================
--- branches/Virtex6/ML605/RxIn_Delays.vhd (revision 9)
+++ branches/Virtex6/ML605/RxIn_Delays.vhd (nonexistent)
@@ -1,1171 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Design Name:
--- Module Name: RxIn_Delay - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision 1.10 - MAX_SIZE_EXCEEDED recalculated for better timing. 31.03.2008
---
--- Revision 1.00 - first release. 20.02.2007
---
--- Additional Comments: Virtual channels resolution.
---
-----------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.abb64Package.all;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity RxIn_Delay is
- port (
- -- Common ports
- trn_clk : IN std_logic;
- trn_reset_n : IN std_logic;
- trn_lnk_up_n : IN std_logic;
-
- -- Transaction receive interface
- trn_rsof_n : IN std_logic;
- trn_reof_n : IN std_logic;
- trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
- trn_rerrfwd_n : IN std_logic;
- trn_rsrc_rdy_n : IN std_logic;
- trn_rsrc_dsc_n : IN std_logic;
- trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
- trn_rdst_rdy_n : OUT std_logic;
- Pool_wrBuf_full : IN std_logic;
- Link_Buf_full : IN std_logic;
-
- -- Delay for one clock
- trn_rsof_n_dly : OUT std_logic;
- trn_reof_n_dly : OUT std_logic;
- trn_rd_dly : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- trn_rrem_n_dly : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
- trn_rerrfwd_n_dly : OUT std_logic;
- trn_rsrc_rdy_n_dly : OUT std_logic;
- trn_rdst_rdy_n_dly : OUT std_logic;
- trn_rsrc_dsc_n_dly : OUT std_logic;
- trn_rbar_hit_n_dly : OUT std_logic_vector(C_BAR_NUMBER-1 downto 0);
-
-
- -- TLP resolution
- IORd_Type : OUT std_logic;
- IOWr_Type : OUT std_logic;
- MRd_Type : OUT std_logic_vector(3 downto 0);
- MWr_Type : OUT std_logic_vector(1 downto 0);
- CplD_Type : OUT std_logic_vector(3 downto 0);
-
- -- From Cpl/D channel
- usDMA_dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
- dsDMA_dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
-
- -- To Memory request process modules
- Tlp_straddles_4KB : OUT std_logic;
-
- -- To Cpl/D channel
- Tlp_has_4KB : OUT std_logic;
- Tlp_has_1DW : OUT std_logic;
- CplD_is_the_Last : OUT std_logic;
- CplD_on_Pool : OUT std_logic;
- CplD_on_EB : OUT std_logic;
- Req_ID_Match : OUT std_logic;
- usDex_Tag_Matched : OUT std_logic;
- dsDex_Tag_Matched : OUT std_logic;
- CplD_Tag : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
-
-
- -- Additional
- cfg_dcommand : IN std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
- localID : IN std_logic_vector(C_ID_WIDTH-1 downto 0)
- );
-
-end entity RxIn_Delay;
-
-
-
-architecture Behavioral of RxIn_Delay is
-
-
--- Max Length Checking
- signal Tlp_has_0_Length : std_logic;
- signal Tlp_has_1DW_Length_i : std_logic;
- signal MaxReadReqSize_Exceeded: std_logic;
- signal MaxPayloadSize_Exceeded: std_logic;
-
- signal Tlp_straddles_4KB_i : std_logic;
- signal CarryIn_ALC : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto 0);
- signal Tlp_has_4KB_i : std_logic;
- signal cfg_MRS : std_logic_vector(C_CFG_MRS_BIT_TOP-C_CFG_MRS_BIT_BOT downto 0);
- signal cfg_MPS : std_logic_vector(C_CFG_MPS_BIT_TOP-C_CFG_MPS_BIT_BOT downto 0);
-
- signal cfg_MRS_decoded : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
- signal cfg_MPS_decoded : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
-
- TYPE CfgThreshold is ARRAY (C_TLP_FLD_WIDTH_OF_LENG-CBIT_SENSE_OF_MAXSIZE downto 0)
- of std_logic_vector (C_TLP_FLD_WIDTH_OF_LENG downto 0);
-
- signal MaxSize_Thresholds : CfgThreshold;
-
--- As one clock of delay
- signal trn_rsof_n_r1 : std_logic;
- signal trn_reof_n_r1 : std_logic;
- signal trn_rrem_n_r1 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
- signal trn_rd_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal trn_rerrfwd_n_r1 : std_logic;
- signal trn_rsrc_rdy_n_r1 : std_logic;
- signal trn_rdst_rdy_n_i : std_logic;
- signal trn_rdst_rdy_n_r1 : std_logic;
- signal trn_rsrc_dsc_n_r1 : std_logic;
- signal trn_rbar_hit_n_r1 : std_logic_vector(C_BAR_NUMBER-1 downto 0);
-
--- TLP type decision
- signal TLP_is_MRd_BAR0_H3DW : std_logic;
- signal TLP_is_MRd_BAR1_H3DW : std_logic;
- signal TLP_is_MRd_BAR2_H3DW : std_logic;
- signal TLP_is_MRd_BAR3_H3DW : std_logic;
-
- signal TLP_is_MRd_BAR0_H4DW : std_logic;
- signal TLP_is_MRd_BAR1_H4DW : std_logic;
- signal TLP_is_MRd_BAR2_H4DW : std_logic;
- signal TLP_is_MRd_BAR3_H4DW : std_logic;
-
- signal TLP_is_MRdLk_BAR0_H3DW : std_logic;
- signal TLP_is_MRdLk_BAR1_H3DW : std_logic;
- signal TLP_is_MRdLk_BAR2_H3DW : std_logic;
- signal TLP_is_MRdLk_BAR3_H3DW : std_logic;
-
- signal TLP_is_MRdLk_BAR0_H4DW : std_logic;
- signal TLP_is_MRdLk_BAR1_H4DW : std_logic;
- signal TLP_is_MRdLk_BAR2_H4DW : std_logic;
- signal TLP_is_MRdLk_BAR3_H4DW : std_logic;
-
- signal TLP_is_MWr_BAR0_H3DW : std_logic;
- signal TLP_is_MWr_BAR1_H3DW : std_logic;
- signal TLP_is_MWr_BAR2_H3DW : std_logic;
- signal TLP_is_MWr_BAR3_H3DW : std_logic;
-
- signal TLP_is_MWr_BAR0_H4DW : std_logic;
- signal TLP_is_MWr_BAR1_H4DW : std_logic;
- signal TLP_is_MWr_BAR2_H4DW : std_logic;
- signal TLP_is_MWr_BAR3_H4DW : std_logic;
-
- signal TLP_is_IORd_BAR0 : std_logic;
- signal TLP_is_IORd_BAR1 : std_logic;
- signal TLP_is_IORd_BAR2 : std_logic;
- signal TLP_is_IORd_BAR3 : std_logic;
-
- signal TLP_is_IOWr_BAR0 : std_logic;
- signal TLP_is_IOWr_BAR1 : std_logic;
- signal TLP_is_IOWr_BAR2 : std_logic;
- signal TLP_is_IOWr_BAR3 : std_logic;
-
- signal TLP_is_IORd : std_logic;
- signal TLP_is_IOWr : std_logic;
-
- signal TLP_is_CplD : std_logic;
- signal TLP_is_Cpl : std_logic;
- signal TLP_is_CplDLk : std_logic;
- signal TLP_is_CplLk : std_logic;
-
-
- signal TLP_is_MRd_H3DW : std_logic;
- signal TLP_is_MRd_H4DW : std_logic;
- signal TLP_is_MRdLk_H3DW : std_logic;
- signal TLP_is_MRdLk_H4DW : std_logic;
-
- signal TLP_is_MWr_H3DW : std_logic;
- signal TLP_is_MWr_H4DW : std_logic;
-
-
- signal IORd_Type_i : std_logic;
- signal IOWr_Type_i : std_logic;
- signal MRd_Type_i : std_logic_vector(3 downto 0);
- signal MWr_Type_i : std_logic_vector(1 downto 0);
- signal CplD_Type_i : std_logic_vector(3 downto 0);
-
- signal Req_ID_Match_i : std_logic;
-
- signal usDex_Tag_Matched_i : std_logic;
- signal dsDex_Tag_Matched_i : std_logic;
-
-
- -----------------------------------------------------------------
- -- Inbound DW counter
- signal TLP_Payload_Address_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal TLP_DW_Length_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
- signal TLP_Address_sig : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto 0);
- signal MWr_on_Pool : std_logic;
- signal MWr_on_EB : std_logic;
- signal CplD_on_Pool_i : std_logic;
- signal CplD_on_EB_i : std_logic;
- signal CplD_is_the_Last_i : std_logic;
- signal CplD_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-
- -- Counter inside a TLP
- type TLPCntStates is ( TK_RST
- , TK_Idle
--- , TK_MWr_3Hdr_B
- , TK_MWr_3Hdr_C
--- , TK_MWr_4Hdr_B
- , TK_MWr_4Hdr_C
--- , TK_MWr_4Hdr_D
--- , TK_CplD_Hdr_B
- , TK_CplD_Hdr_C
- , TK_Body
- );
-
- signal FSM_TLP_Cnt : TLPCntStates;
-
- signal FSM_TLP_Cnt_r1 : TLPCntStates;
-
- -- CplD tag capture FSM (Address at tRAM)
- type AddrOnRAM_States is ( AOtSt_RST
- , AOtSt_Idle
- , AOtSt_HdrA
- , AOtSt_HdrB
- , AOtSt_Body
- );
-
- signal FSM_AOtRAM : AddrOnRAM_States;
-
-
-begin
-
- trn_rdst_rdy_n <= trn_rdst_rdy_n_i ; -- and trn_rsof_n and trn_rsof_n_r1 ;
-
- -- Delay
- trn_rsof_n_dly <= trn_rsof_n_r1 ;
- trn_reof_n_dly <= trn_reof_n_r1 ;
- trn_rrem_n_dly <= trn_rrem_n_r1 ;
- trn_rd_dly <= trn_rd_r1 ;
- trn_rerrfwd_n_dly <= trn_rerrfwd_n_r1 ;
- trn_rsrc_rdy_n_dly <= trn_rsrc_rdy_n_r1 ;
- trn_rdst_rdy_n_dly <= trn_rdst_rdy_n_r1 ; -- trn_rdst_rdy_n_r1 ;
- trn_rsrc_dsc_n_dly <= trn_rsrc_dsc_n_r1 ;
- trn_rbar_hit_n_dly <= trn_rbar_hit_n_r1 ;
-
-
- -- TLP resolution
- IORd_Type <= '0' ; -- IORd_Type_i ;
- IOWr_Type <= '0' ; -- IOWr_Type_i ;
- MRd_Type <= MRd_Type_i ;
- MWr_Type <= MWr_Type_i ;
- CplD_Type <= CplD_Type_i ;
-
- -- To Cpl/D channel
- Req_ID_Match <= Req_ID_Match_i ;
-
- usDex_Tag_Matched <= usDex_Tag_Matched_i ;
- dsDex_Tag_Matched <= dsDex_Tag_Matched_i ;
-
- CplD_Tag <= CplD_Tag_i ;
- CplD_is_the_Last <= CplD_is_the_Last_i ;
- CplD_on_Pool <= CplD_on_Pool_i ;
- CplD_on_EB <= CplD_on_EB_i ;
-
-
- Tlp_has_4KB <= Tlp_has_4KB_i ;
- Tlp_has_1DW <= Tlp_has_1DW_Length_i ;
-
- Tlp_straddles_4KB <= '0'; --Tlp_straddles_4KB_i ;
-
-
- -- !! !!
- MaxReadReqSize_Exceeded <= '0';
- MaxPayloadSize_Exceeded <= '0';
-
-
-
-----------------------------------------------
---
--- Synchronous Registered: TLP_DW_Length
--- Tlp_has_4KB
--- Tlp_has_1DW_Length
--- Tlp_has_0_Length
---
- FSM_TLP_1ST_DW_Info:
- process ( trn_clk, trn_reset_n)
- begin
- if trn_reset_n = '0' then
- TLP_DW_Length_i <= (OTHERS => '0');
- Tlp_has_4KB_i <= '0';
- Tlp_has_1DW_Length_i <= '0';
- Tlp_has_0_Length <= '0';
-
- elsif trn_clk'event and trn_clk = '1' then
- if trn_rsof_n='0' then
- TLP_DW_Length_i <= trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
- else
- TLP_DW_Length_i <= TLP_DW_Length_i;
- end if;
-
- if trn_rsof_n ='0' then
- if trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)=C_ALL_ZEROS(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) then
- Tlp_has_4KB_i <= '1' ;
- else
- Tlp_has_4KB_i <= '0' ;
- end if;
- else
- Tlp_has_4KB_i <= Tlp_has_4KB_i ;
- end if;
-
- if trn_rsof_n ='0' then
- if trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)
- = CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG) then
- Tlp_has_1DW_Length_i <= '1';
- else
- Tlp_has_1DW_Length_i <= '0';
- end if;
- else
- Tlp_has_1DW_Length_i <= Tlp_has_1DW_Length_i;
- end if;
-
- if trn_rsof_n ='0' then
- if trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)
- = CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
- and trn_rd(2)='0' then
- Tlp_has_0_Length <= '1';
- else
- Tlp_has_0_Length <= '0';
- end if;
- else
- Tlp_has_0_Length <= Tlp_has_0_Length;
- end if;
-
- end if;
- end process;
-
-
-
----- --------------------------------------------------------------------------
--- -- Max Payload Size bits
--- cfg_MPS <= cfg_dcommand(C_CFG_MPS_BIT_TOP downto C_CFG_MPS_BIT_BOT);
---
--- -- Max Read Request Size bits
--- cfg_MRS <= cfg_dcommand(C_CFG_MRS_BIT_TOP downto C_CFG_MRS_BIT_BOT);
---
---
---
--- -- --------------------------------
--- -- Decoding MPS
--- --
--- Trn_Rx_Decoding_MPS:
--- process ( trn_clk )
--- begin
--- if trn_clk'event and trn_clk = '1' then
---
--- case cfg_MPS is
--- when CONV_STD_LOGIC_VECTOR(0, 3) =>
--- cfg_MPS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
---
--- when CONV_STD_LOGIC_VECTOR(1, 3) =>
--- cfg_MPS_decoded <= MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
---
--- when CONV_STD_LOGIC_VECTOR(2, 3) =>
--- cfg_MPS_decoded <= MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
---
--- when CONV_STD_LOGIC_VECTOR(3, 3) =>
--- cfg_MPS_decoded <= MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
---
--- when CONV_STD_LOGIC_VECTOR(4, 3) =>
--- cfg_MPS_decoded <= MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
---
--- when CONV_STD_LOGIC_VECTOR(5, 3) =>
--- cfg_MPS_decoded <= MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
---
--- when Others =>
--- cfg_MPS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
---
--- end case;
---
--- end if;
--- end process;
---
---
--- -- --------------------------------
--- -- Decoding MRS
--- --
--- Trn_Rx_Decoding_MRS:
--- process ( trn_clk )
--- begin
--- if trn_clk'event and trn_clk = '1' then
---
--- case cfg_MRS is
--- when CONV_STD_LOGIC_VECTOR(0, 3) =>
--- cfg_MRS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
---
--- when CONV_STD_LOGIC_VECTOR(1, 3) =>
--- cfg_MRS_decoded <= MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
---
--- when CONV_STD_LOGIC_VECTOR(2, 3) =>
--- cfg_MRS_decoded <= MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
---
--- when CONV_STD_LOGIC_VECTOR(3, 3) =>
--- cfg_MRS_decoded <= MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
---
--- when CONV_STD_LOGIC_VECTOR(4, 3) =>
--- cfg_MRS_decoded <= MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
---
--- when CONV_STD_LOGIC_VECTOR(5, 3) =>
--- cfg_MRS_decoded <= MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
---
--- when Others =>
--- cfg_MRS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
---
--- end case;
---
--- end if;
--- end process;
---
---
--- -------------------------------------------------------------
--- MaxSize_Thresholds(0) <= (CBIT_SENSE_OF_MAXSIZE=>'1', Others=>'0');
--- Gen_MaxSizes:
--- FOR i IN 1 TO C_TLP_FLD_WIDTH_OF_LENG-CBIT_SENSE_OF_MAXSIZE GENERATE
--- MaxSize_Thresholds(i) <= MaxSize_Thresholds(i-1)(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0)&'0';
--- END GENERATE;
---
--- -- --------------------------------
--- -- Calculation of MPS exceed
--- --
--- Trn_Rx_MaxPayloadSize_Exceeded:
--- process ( trn_clk )
--- begin
--- if trn_clk'event and trn_clk = '1' then
---
--- case cfg_MPS_decoded is
---
----- when CONV_STD_LOGIC_VECTOR(1, 6) => -- MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
----- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
----- MaxPayloadSize_Exceeded <= '1';
----- else
----- MaxPayloadSize_Exceeded <= '0';
----- end if;
---
--- when CONV_STD_LOGIC_VECTOR(2, 6) => -- MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
--- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(1) then
--- MaxPayloadSize_Exceeded <= '1';
--- else
--- MaxPayloadSize_Exceeded <= '0';
--- end if;
---
--- when CONV_STD_LOGIC_VECTOR(4, 6) => -- MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
--- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(2) then
--- MaxPayloadSize_Exceeded <= '1';
--- else
--- MaxPayloadSize_Exceeded <= '0';
--- end if;
---
--- when CONV_STD_LOGIC_VECTOR(8, 6) => -- MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
--- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(3) then
--- MaxPayloadSize_Exceeded <= '1';
--- else
--- MaxPayloadSize_Exceeded <= '0';
--- end if;
---
--- when CONV_STD_LOGIC_VECTOR(16, 6) => -- MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
--- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(4) then
--- MaxPayloadSize_Exceeded <= '1';
--- else
--- MaxPayloadSize_Exceeded <= '0';
--- end if;
---
--- when CONV_STD_LOGIC_VECTOR(32, 6) => -- MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
--- MaxPayloadSize_Exceeded <= '0'; -- !!
---
--- when OTHERS =>
--- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
--- MaxPayloadSize_Exceeded <= '1';
--- else
--- MaxPayloadSize_Exceeded <= '0';
--- end if;
---
--- end case;
---
--- end if;
--- end process;
---
---
--- -- --------------------------------
--- -- Calculation of MRS exceed
--- --
--- Trn_Rx_MaxReadReqSize_Exceeded:
--- process ( trn_clk )
--- begin
--- if trn_clk'event and trn_clk = '1' then
---
--- case cfg_MRS_decoded is
---
----- when CONV_STD_LOGIC_VECTOR(1, 6) => -- MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
----- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
----- MaxReadReqSize_Exceeded <= '1';
----- else
----- MaxReadReqSize_Exceeded <= '0';
----- end if;
---
--- when CONV_STD_LOGIC_VECTOR(2, 6) => -- MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
--- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(1) then
--- MaxReadReqSize_Exceeded <= '1';
--- else
--- MaxReadReqSize_Exceeded <= '0';
--- end if;
---
--- when CONV_STD_LOGIC_VECTOR(4, 6) => -- MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
--- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(2) then
--- MaxReadReqSize_Exceeded <= '1';
--- else
--- MaxReadReqSize_Exceeded <= '0';
--- end if;
---
--- when CONV_STD_LOGIC_VECTOR(8, 6) => -- MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
--- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(3) then
--- MaxReadReqSize_Exceeded <= '1';
--- else
--- MaxReadReqSize_Exceeded <= '0';
--- end if;
---
--- when CONV_STD_LOGIC_VECTOR(16, 6) => -- MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
--- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(4) then
--- MaxReadReqSize_Exceeded <= '1';
--- else
--- MaxReadReqSize_Exceeded <= '0';
--- end if;
---
--- when CONV_STD_LOGIC_VECTOR(32, 6) => -- MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
--- MaxReadReqSize_Exceeded <= '0'; -- !!
---
--- when OTHERS =>
--- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
--- MaxReadReqSize_Exceeded <= '1';
--- else
--- MaxReadReqSize_Exceeded <= '0';
--- end if;
---
--- end case;
---
--- end if;
--- end process;
-
-
-
-
- -- ---------------------------------------------------------
- ---- Pipelining all trn_rx input signals for one clock
- ---- to get better timing
- ----
- Trn_Rx_Inputs_Delayed:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
- trn_rsof_n_r1 <= trn_rsof_n;
- trn_reof_n_r1 <= trn_reof_n;
- trn_rrem_n_r1 <= trn_rrem_n;
- trn_rd_r1 <= trn_rd;
- trn_rerrfwd_n_r1 <= trn_rerrfwd_n;
- trn_rsrc_rdy_n_r1 <= trn_rsrc_rdy_n;
- trn_rdst_rdy_n_r1 <= trn_rdst_rdy_n_i;
- trn_rsrc_dsc_n_r1 <= trn_rsrc_dsc_n;
- trn_rbar_hit_n_r1 <= trn_rbar_hit_n;
- end if;
- end process;
-
-
- -- -----------------------------------------
- -- TLP Types
- --
- TLP_Decision_Registered:
- process ( trn_clk, trn_reset_n)
- begin
- if trn_reset_n = '0' then
- TLP_is_MRd_H3DW <= '0';
-
- TLP_is_MRdLk_H3DW <= '0';
-
- TLP_is_MRd_H4DW <= '0';
-
- TLP_is_MRdLk_H4DW <= '0';
-
- TLP_is_MWr_H3DW <= '0';
-
- TLP_is_MWr_H4DW <= '0';
-
- TLP_is_IORd <= '0';
-
- TLP_is_IOWr <= '0';
-
- TLP_is_CplD <= '0';
- TLP_is_CplDLk <= '0';
- TLP_is_Cpl <= '0';
- TLP_is_CplLk <= '0';
-
- elsif trn_clk'event and trn_clk = '1' then
-
- -- IORd
- if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_IO_REQ
- and trn_rd(C_TLP_EP_BIT) ='0'
--- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
- and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
- and trn_rsrc_rdy_n ='0'
- and trn_rsof_n ='0'
- then
- TLP_is_IORd <= '1';
- else
- TLP_is_IORd <= '0';
- end if;
-
-
- -- IOWr
- if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_WITH_DATA
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_IO_REQ
- and trn_rd(C_TLP_EP_BIT) ='0'
--- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
- and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
- and trn_rsrc_rdy_n ='0'
- and trn_rsof_n ='0'
- then
- TLP_is_IOWr <= '1';
- else
- TLP_is_IOWr <= '0';
- end if;
-
-
- -- MRd
- if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
- and trn_rd(C_TLP_EP_BIT) ='0'
--- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
- and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
- and trn_rsrc_rdy_n ='0'
- and trn_rsof_n ='0'
- then
- TLP_is_MRd_H3DW <= '1';
- else
- TLP_is_MRd_H3DW <= '0';
- end if;
-
-
-
- if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT4_NO_DATA
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
- and trn_rd(C_TLP_EP_BIT) ='0'
--- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
- and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
- and trn_rsrc_rdy_n ='0'
- and trn_rsof_n ='0'
- then
- TLP_is_MRd_H4DW <= '1';
- else
- TLP_is_MRd_H4DW <= '0';
- end if;
-
-
- -- MRdLk
- if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ_LK
- and trn_rd(C_TLP_EP_BIT) ='0'
--- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
- and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
- and trn_rsrc_rdy_n ='0'
- and trn_rsof_n ='0'
- then
- TLP_is_MRdLk_H3DW <= '1';
- else
- TLP_is_MRdLk_H3DW <= '0';
- end if;
-
-
- if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT4_NO_DATA
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ_LK
- and trn_rd(C_TLP_EP_BIT) ='0'
--- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
- and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
- and trn_rsrc_rdy_n ='0'
- and trn_rsof_n ='0'
- then
- TLP_is_MRdLk_H4DW <= '1';
- else
- TLP_is_MRdLk_H4DW <= '0';
- end if;
-
-
-
- -- MWr
- if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_WITH_DATA
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
- and trn_rd(C_TLP_EP_BIT) ='0'
--- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
- and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
- and trn_rsrc_rdy_n ='0'
- and trn_rsof_n ='0'
- then
- TLP_is_MWr_H3DW <= '1';
- else
- TLP_is_MWr_H3DW <= '0';
- end if;
-
-
- if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT4_WITH_DATA
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
- and trn_rd(C_TLP_EP_BIT) ='0'
--- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
- and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
- and trn_rsrc_rdy_n ='0'
- and trn_rsof_n ='0'
- then
- TLP_is_MWr_H4DW <= '1';
- else
- TLP_is_MWr_H4DW <= '0';
- end if;
-
-
-
- -- CplD, Cpl/CplDLk, CplLk
- if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_WITH_DATA
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION
- and trn_rd(C_TLP_EP_BIT) ='0'
- and trn_rsrc_rdy_n ='0'
- and trn_rsof_n ='0'
- then
- TLP_is_CplD <= '1';
- else
- TLP_is_CplD <= '0';
- end if;
-
- if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_WITH_DATA
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION_LK
- and trn_rd(C_TLP_EP_BIT) ='0'
- and trn_rsrc_rdy_n ='0'
- and trn_rsof_n ='0'
- then
- TLP_is_CplDLk <= '1';
- else
- TLP_is_CplDLk <= '0';
- end if;
-
-
- if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION
- and trn_rd(C_TLP_EP_BIT) ='0'
- and trn_rsrc_rdy_n ='0'
- and trn_rsof_n ='0'
- then
- TLP_is_Cpl <= '1';
- else
- TLP_is_Cpl <= '0';
- end if;
-
- if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION_LK
- and trn_rd(C_TLP_EP_BIT) ='0'
- and trn_rsrc_rdy_n ='0'
- and trn_rsof_n ='0'
- then
- TLP_is_CplLk <= '1';
- else
- TLP_is_CplLk <= '0';
- end if;
-
- end if;
- end process;
-
-
--- --------------------------------------------------------------------------
--- TLP_is_IORd <= TLP_is_IORd_BAR0 or TLP_is_IORd_BAR1;
--- TLP_is_IOWr <= TLP_is_IOWr_BAR0 or TLP_is_IOWr_BAR1;
-
--- TLP_is_MRd_H3DW <= TLP_is_MRd_BAR0_H3DW or TLP_is_MRd_BAR1_H3DW;
--- TLP_is_MRdLk_H3DW <= TLP_is_MRdLk_BAR0_H3DW or TLP_is_MRdLk_BAR1_H3DW;
-
--- TLP_is_MRd_H4DW <= TLP_is_MRd_BAR0_H4DW or TLP_is_MRd_BAR1_H4DW;
--- TLP_is_MRdLk_H4DW <= TLP_is_MRdLk_BAR0_H4DW or TLP_is_MRdLk_BAR1_H4DW;
-
--- TLP_is_MWr_H3DW <= TLP_is_MWr_BAR0_H3DW or TLP_is_MWr_BAR1_H3DW;
-
--- TLP_is_MWr_H4DW <= TLP_is_MWr_BAR0_H4DW or TLP_is_MWr_BAR1_H4DW;
-
--- --------------------------------------------------------------------------
-
- IORd_Type_i <= TLP_is_IORd and Tlp_has_1DW_Length_i;
- IOWr_Type_i <= TLP_is_IOWr and Tlp_has_1DW_Length_i;
-
-
- MRd_Type_i <= (TLP_is_MRd_H3DW and not MaxReadReqSize_Exceeded)
- & (TLP_is_MRdLk_H3DW and not MaxReadReqSize_Exceeded)
- & (TLP_is_MRd_H4DW and not MaxReadReqSize_Exceeded)
- & (TLP_is_MRdLk_H4DW and not MaxReadReqSize_Exceeded)
- ;
-
- MWr_Type_i <= (TLP_is_MWr_H3DW and not MaxPayloadSize_Exceeded)
- & (TLP_is_MWr_H4DW and not MaxPayloadSize_Exceeded)
- ;
-
- CplD_Type_i <= (TLP_is_CplD and not MaxPayloadSize_Exceeded)
- & (TLP_is_Cpl and not MaxPayloadSize_Exceeded)
- & (TLP_is_CplDLk and not MaxPayloadSize_Exceeded)
- & (TLP_is_CplLk and not MaxPayloadSize_Exceeded)
- ;
-
-
- ---------------------------------------------------
- --
- -- Synchronous Registered: TLP_Header_Resolution
- --
- FSM_TLP_Header_Resolution:
- process ( trn_clk, trn_reset_n)
- begin
- if trn_reset_n = '0' then
- FSM_TLP_Cnt <= TK_RST;
- TLP_Payload_Address_i <= (OTHERS => '1');
- MWr_on_Pool <= '0';
- CplD_on_Pool_i <= '0';
- CplD_on_EB_i <= '0';
- trn_rdst_rdy_n_i <= '1';
-
- elsif trn_clk'event and trn_clk = '1' then
-
- -- States transition
- case FSM_TLP_Cnt is
-
- when TK_RST =>
- FSM_TLP_Cnt <= TK_Idle;
- trn_rdst_rdy_n_i <= '1';
-
- when TK_Idle =>
- trn_rdst_rdy_n_i <= '0';
- if trn_rsof_n='0' and trn_rsrc_rdy_n='0'
- and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="10"
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="00"
- then
- FSM_TLP_Cnt <= TK_MWr_3Hdr_C;
- elsif trn_rsof_n='0' and trn_rsrc_rdy_n='0'
- and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="11"
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="00"
- then
- FSM_TLP_Cnt <= TK_MWr_4Hdr_C;
- elsif trn_rsof_n='0' and trn_rsrc_rdy_n='0'
- and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="10"
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="01"
- then
- FSM_TLP_Cnt <= TK_CplD_Hdr_C;
- else
- FSM_TLP_Cnt <= TK_Idle;
- end if;
-
-
- when TK_MWr_3Hdr_C =>
- trn_rdst_rdy_n_i <= '0';
- if trn_reof_n='0' and trn_reof_n_r1='1' then -- falling edge
- FSM_TLP_Cnt <= TK_Idle;
- elsif trn_rsrc_rdy_n='1' then
- FSM_TLP_Cnt <= TK_MWr_3Hdr_C;
- else
- FSM_TLP_Cnt <= TK_Body;
- end if;
-
- when TK_MWr_4Hdr_C =>
- trn_rdst_rdy_n_i <= '0';
- if trn_reof_n='0' and trn_reof_n_r1='1' then -- falling edge
- FSM_TLP_Cnt <= TK_Idle;
- elsif trn_rsrc_rdy_n='1' then
- FSM_TLP_Cnt <= TK_MWr_4Hdr_C;
- else
- FSM_TLP_Cnt <= TK_Body; -- TK_MWr_4Hdr_D;
- end if;
-
-
- when TK_Cpld_Hdr_C =>
- trn_rdst_rdy_n_i <= '0';
- if trn_reof_n='0' and trn_reof_n_r1='1' then -- falling edge
- FSM_TLP_Cnt <= TK_Idle;
- elsif trn_rsrc_rdy_n='1' then
- FSM_TLP_Cnt <= TK_Cpld_Hdr_C;
- else
- FSM_TLP_Cnt <= TK_Body;
- end if;
-
-
- when TK_Body =>
- if trn_reof_n='0' and trn_reof_n_r1='1' then -- falling edge
- FSM_TLP_Cnt <= TK_Idle;
- trn_rdst_rdy_n_i <= '0';
- else
- FSM_TLP_Cnt <= TK_Body;
- trn_rdst_rdy_n_i <= ((MWr_on_Pool or CplD_on_Pool_i) and Pool_wrBuf_full)
- or ((MWr_on_EB or CplD_on_EB_i) and Link_Buf_full)
- ;
- end if;
-
-
- when OTHERS =>
- FSM_TLP_Cnt <= TK_RST;
-
- end case;
-
-
- -- MWr_on_Pool
- case FSM_TLP_Cnt is
-
- when TK_RST =>
- MWr_on_Pool <= '0';
- MWr_on_EB <= '0';
-
- when TK_Idle =>
- if trn_rsof_n='0' and trn_rsrc_rdy_n='0'
- and trn_rd(C_TLP_FMT_BIT_TOP) = '1'
- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="00"
- then
- MWr_on_Pool <= not trn_rbar_hit_n(CINT_DDR_SPACE_BAR);
- MWr_on_EB <= not trn_rbar_hit_n(CINT_FIFO_SPACE_BAR);
- else
- MWr_on_Pool <= MWr_on_Pool;
- MWr_on_EB <= MWr_on_EB;
- end if;
-
-
- when OTHERS =>
- MWr_on_Pool <= MWr_on_Pool;
- MWr_on_EB <= MWr_on_EB;
-
- end case;
-
-
- -- CplD_on_Pool
- case FSM_TLP_Cnt is
-
- when TK_RST =>
- CplD_on_Pool_i <= '0';
- CplD_on_EB_i <= '0';
-
- when TK_Idle =>
- CplD_on_Pool_i <= '0';
- CplD_on_EB_i <= '0';
-
- when TK_CplD_Hdr_C =>
--- if trn_rsof_n='0' and trn_rsrc_rdy_n='0'
--- and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="10"
--- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="01"
--- then
- CplD_on_Pool_i <= not trn_rd(C_CPLD_TAG_BIT_TOP) and not trn_rd(C_CPLD_TAG_BIT_TOP-1);
- CplD_on_EB_i <= not trn_rd(C_CPLD_TAG_BIT_TOP) and trn_rd(C_CPLD_TAG_BIT_TOP-1);
--- else
--- CplD_on_Pool_i <= CplD_on_Pool_i;
--- CplD_on_EB_i <= CplD_on_EB_i;
--- end if;
-
-
- when OTHERS =>
- CplD_on_Pool_i <= CplD_on_Pool_i;
- CplD_on_EB_i <= CplD_on_EB_i;
-
- end case;
-
-
- -- CplD_Tag
- case FSM_TLP_Cnt is
-
- when TK_RST =>
- CplD_Tag_i <= (OTHERS => '1');
-
--- when TK_Idle =>
--- CplD_Tag_i <= CplD_Tag_i;
-
- when TK_CplD_Hdr_C =>
--- if trn_reof_n='0' then
--- CplD_Tag_i <= (OTHERS => '1');
--- els
- if trn_rsrc_rdy_n='0' -- and trn_rdst_rdy_n='0'
- then
- CplD_Tag_i <= trn_rd(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT);
- else
- CplD_Tag_i <= CplD_Tag_i;
- end if;
-
- when OTHERS =>
- CplD_Tag_i <= CplD_Tag_i;
-
- end case;
-
-
- end if;
- end process;
-
-
- ---------------------------------------------------
- --
- -- Synchronous Registered: CplD_is_the_Last
- --
- Syn_Calc_CplD_is_the_Last:
- process ( trn_clk, trn_reset_n)
- begin
- if trn_reset_n = '0' then
- CplD_is_the_Last_i <= '0';
-
- elsif trn_clk'event and trn_clk = '1' then
-
- if trn_rsof_n='0' and trn_rsrc_rdy_n='0' then
- if trn_rd(C_TLP_TYPE_BIT_TOP-1)= '1'
- and (trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2)=trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)
- or trn_rd(1 downto 0)=CONV_STD_LOGIC_VECTOR(1, 2)) -- Zero-length
- then
- CplD_is_the_Last_i <= '1';
- else
- CplD_is_the_Last_i <= '0';
- end if;
- else
- CplD_is_the_Last_i <= CplD_is_the_Last_i;
- end if;
-
- end if;
- end process;
-
- ---------------------------------------------------
- --
- -- Synchronous Delay: FSM_TLP_Cnt
- --
- SynDelay_FSM_TLP_Cnt:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
- FSM_TLP_Cnt_r1 <= FSM_TLP_Cnt;
- end if;
- end process;
-
-
----- --------------------------------------------------------------------------
---
--- TLP_Address_sig <= '0' & trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
---
----------------------------------------------------------------------------------------
----- Calculates the Address-Length combination carry-in
--- TLP_Calc_CarryIn_ALC:
--- process ( trn_clk, trn_reset_n)
--- begin
--- if trn_reset_n = '0' then
--- CarryIn_ALC <= (OTHERS =>'0');
--- elsif trn_clk'event and trn_clk = '1' then
--- CarryIn_ALC <= ('0'& TLP_DW_Length_i) + TLP_Address_sig;
--- end if;
--- end process;
---
---
--- ---------------------------------------------------
--- --
--- -- Synchronous Registered: Tlp_straddles_4KB
--- --
--- FSM_Output_Tlp_straddles_4KB:
--- process ( trn_clk, trn_reset_n)
--- begin
--- if trn_reset_n = '0' then
--- Tlp_straddles_4KB_i <= '0';
---
--- elsif trn_clk'event and trn_clk = '1' then
---
--- case FSM_TLP_Cnt_r1 is
---
--- when TK_RST =>
--- Tlp_straddles_4KB_i <= '0';
---
--- when TK_MWr_3Hdr_C =>
--- if Tlp_has_4KB_i='1'
--- and trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
--- /=C_ALL_ZEROS(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
--- then
--- Tlp_straddles_4KB_i <= '1';
--- else
--- Tlp_straddles_4KB_i <= CarryIn_ALC(C_TLP_FLD_WIDTH_OF_LENG);
--- end if;
---
--- when TK_MWr_4Hdr_D =>
--- if Tlp_has_4KB_i='1'
--- and trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
--- /=C_ALL_ZEROS(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
--- then
--- Tlp_straddles_4KB_i <= '1';
--- else
--- Tlp_straddles_4KB_i <= CarryIn_ALC(C_TLP_FLD_WIDTH_OF_LENG);
--- end if;
---
---
--- when OTHERS =>
--- Tlp_straddles_4KB_i <= Tlp_straddles_4KB_i;
---
--- end case;
---
--- end if;
--- end process;
---
-
-
-
- -- ---------------------------------------------------------
- -- To Cpl/D channel as indicator when ReqID matched
- --
- TLP_ReqID_Matched:
- process ( trn_clk, trn_reset_n)
- begin
- if trn_reset_n = '0' then
- Req_ID_Match_i <= '0';
- elsif trn_clk'event and trn_clk = '1' then
- if trn_rd(C_CPLD_REQID_BIT_TOP downto C_CPLD_REQID_BIT_BOT)=localID then
- Req_ID_Match_i <= '1';
- else
- Req_ID_Match_i <= '0';
- end if;
- end if;
- end process;
-
-
- -- ------------------------------------------------------------
- -- To Cpl/D channel as indicator when us Tag_Descriptor matched
- --
- TLP_usDexTag_Matched:
- process ( trn_clk, trn_reset_n)
- begin
- if trn_reset_n = '0' then
- usDex_Tag_Matched_i <= '0';
- elsif trn_clk'event and trn_clk = '1' then
- if trn_rd(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=usDMA_dex_Tag then
- usDex_Tag_Matched_i <= '1';
- else
- usDex_Tag_Matched_i <= '0';
- end if;
- end if;
- end process;
-
-
- -- ------------------------------------------------------------
- -- To Cpl/D channel as indicator when ds Tag_Descriptor matched
- --
- TLP_dsDexTag_Matched:
- process ( trn_clk, trn_reset_n)
- begin
- if trn_reset_n = '0' then
- dsDex_Tag_Matched_i <= '0';
- elsif trn_clk'event and trn_clk = '1' then
- if trn_rd(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=dsDMA_dex_Tag then
- dsDex_Tag_Matched_i <= '1';
- else
- dsDex_Tag_Matched_i <= '0';
- end if;
- end if;
- end process;
-
-
-end architecture Behavioral;
Index: branches/Virtex6/ML605/abb_dgen.vhd
===================================================================
--- branches/Virtex6/ML605/abb_dgen.vhd (revision 9)
+++ branches/Virtex6/ML605/abb_dgen.vhd (nonexistent)
@@ -1,465 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: ziti
--- Engineer: wgao
---
--- Create Date: 18:29:15 29 Jun 2009
--- Design Name:
--- Module Name: abb_dgen - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.abb64Package.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity abb_dgen is
- port (
-
- -- Data generator table write port
- tab_sel : IN STD_LOGIC;
- tab_we : IN STD_LOGIC_VECTOR (2-1 downto 0);
- tab_wa : IN STD_LOGIC_VECTOR (12-1 downto 0);
- tab_wd : IN STD_LOGIC_VECTOR (64-1 downto 0);
-
- -- DAQ Rx
- data_rec_start : OUT std_logic;
- data_rec_end : OUT std_logic;
- data_rec : OUT std_logic_vector(64-1 downto 0);
- crc_error_rec : OUT std_logic;
- data_rec_stop : IN std_logic;
-
- -- CTL Rx
- ctrl_rec_start : OUT std_logic;
- ctrl_rec_end : OUT std_logic;
- ctrl_rec : OUT std_logic_vector(16-1 downto 0);
- ctrl_rec_stop : IN std_logic;
-
- -- DLM Rx
- dlm_rec_va : OUT std_logic;
- dlm_rec_type : OUT std_logic_vector(4-1 downto 0);
-
- -- status signals
- dg_running : OUT STD_LOGIC;
- daq_start_led : OUT STD_LOGIC;
-
- -- must signals
- dg_clk : IN STD_LOGIC;
- dg_mask : IN STD_LOGIC;
- dg_rst : IN STD_LOGIC
- );
-end abb_dgen;
-
-
-architecture Behavioral of abb_dgen is
-
- type DGHaltStates is ( dgST_RESET
- , dgST_Run
- , dgST_Halt
- );
-
- -- State variables
- signal dg_Halt_State : DGHaltStates;
-
- -- Data generator table, without output registering
- component v6_bram4096x64_fast
- port (
- clka : IN std_logic;
- addra : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
- wea : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
- dina : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- douta : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- clkb : IN std_logic;
- addrb : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
- web : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
- dinb : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- doutb : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
- );
- end component;
-
- -- DAQ Rx
- signal data_rec_start_i : std_logic;
- signal data_rec_end_i : std_logic;
- signal data_rec_i : std_logic_vector(64-1 downto 0);
- signal crc_error_rec_i : std_logic;
-
- -- CTL Rx
- signal ctrl_rec_start_i : std_logic;
- signal ctrl_rec_end_i : std_logic;
- signal ctrl_rec_i : std_logic_vector(16-1 downto 0);
-
- -- DLM Rx
- signal dlm_rec_va_i : std_logic;
- signal dlm_rec_type_i : std_logic_vector(4-1 downto 0);
-
- -- Table signals
- signal dg_running_i : std_logic;
- signal tab_travel : std_logic;
- signal tab_halt : std_logic;
- signal tab_we_padded : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
- signal tab_ra : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
- signal tab_ra_r1 : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
- signal tab_rb_dummy : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
- signal tab_rd_dummy : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal tab_rq : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- feature bits
- signal tab_class_bits : std_logic_vector(2-1 downto 0);
- signal tab_enable_bit : std_logic;
- signal tab_stop_bit : std_logic;
- signal tab_cerr_bit : std_logic;
- signal tab_sop_bit : std_logic;
- signal tab_eop_bit : std_logic;
-
- -- procedure control
- signal congest_daq : std_logic;
- signal congest_ctl : std_logic;
- signal delay_time_over : std_logic;
- signal delay_counter : std_logic_vector(16-1 downto 0);
- signal dg_mask_r1 : std_logic;
- signal dg_mask_rise : std_logic;
-
- -- debug signal
- signal daq_start_latch : std_logic;
- signal daq_start_led_i : std_logic := '0';
- signal cnt_daq_start : std_logic_vector(20-1 downto 0);
-
- -- Constants
- Constant C_CLASS_DAQ : std_logic_vector(2-1 downto 0) := "01";
- Constant C_CLASS_CTL : std_logic_vector(2-1 downto 0) := "10";
- Constant C_CLASS_DLM : std_logic_vector(2-1 downto 0) := "11";
-
-begin
-
- dg_running <= dg_running_i;
- dg_running_i <= tab_travel;
-
- dg_mask_rise <= dg_mask and not dg_mask_r1;
-
- data_rec_start <= data_rec_start_i when dg_mask_r1='0' else '0';
- data_rec_end <= (data_rec_end_i or dg_mask_rise) when dg_mask_r1='0' else '0';
- data_rec <= data_rec_i when dg_mask_r1='0' else (OTHERS=>'0');
- crc_error_rec <= crc_error_rec_i when dg_mask_r1='0' else '0';
-
- ctrl_rec_start <= ctrl_rec_start_i when dg_mask_r1='0' else '0';
- ctrl_rec_end <= (ctrl_rec_end_i or dg_mask_rise) when dg_mask_r1='0' else '0';
- ctrl_rec <= ctrl_rec_i when dg_mask_r1='0' else (OTHERS=>'0');
-
- dlm_rec_va <= dlm_rec_va_i when dg_mask_r1='0' else '0';
- dlm_rec_type <= dlm_rec_type_i when dg_mask_r1='0' else (OTHERS=>'0');
-
-
- -- Syn. delay: dg_mask
- Delay_dg_mask:
- process ( dg_clk)
- begin
- if dg_clk'event and dg_clk = '1' then
- dg_mask_r1 <= dg_mask;
- end if;
- end process;
-
-
- -- -------------------------------------------------
- -- Debug LED
- --
- daq_start_latch <= data_rec_start_i and not dg_mask;
- daq_start_led <= daq_start_led_i;
-
- SynProc_DGen_Debug_LED:
- process ( dg_clk, daq_start_latch)
- begin
- if daq_start_latch='1' then
- daq_start_led_i <= '1';
- cnt_daq_start <= (OTHERS=>'0');
- elsif dg_clk'event and dg_clk = '1' then
--- if cnt_daq_start=X"0000F" then
- if cnt_daq_start=X"F0000" then
- daq_start_led_i <= '0';
- cnt_daq_start <= cnt_daq_start;
- else
- daq_start_led_i <= daq_start_led_i;
- cnt_daq_start <= cnt_daq_start + '1';
- end if;
- end if;
- end process;
-
-
- -- -------------------------------------------------
- -- Data generator table block RAM instantiate
- --
- dgen_RAM:
- v6_bram4096x64_fast
- port map (
- clka => dg_clk ,
- addra => tab_wa ,
- wea => tab_we_padded ,
- dina => tab_wd ,
- douta => open ,
-
- clkb => dg_clk ,
- addrb => tab_ra ,
- web => tab_rb_dummy ,
- dinb => tab_rd_dummy ,
- doutb => tab_rq
- );
-
- tab_rb_dummy <= (OTHERS=>'0');
- tab_rd_dummy <= (OTHERS=>'1');
- tab_we_padded <= (tab_we(1) & tab_we(1) & tab_we(1) & tab_we(1)
- & tab_we(0) & tab_we(0) & tab_we(0) & tab_we(0)) when tab_sel='1'
- else (OTHERS=>'0');
-
- tab_ra <= tab_rq(59 downto 48) when (tab_travel='1' and delay_time_over='1' and congest_daq='0' and congest_ctl='0')
- else tab_ra_r1;
-
- tab_class_bits <= tab_rq(61 downto 60);
- tab_enable_bit <= tab_rq(63);
- tab_stop_bit <= tab_rq(62);
- tab_cerr_bit <= tab_rq(18);
- tab_sop_bit <= tab_rq(17);
- tab_eop_bit <= tab_rq(16);
-
-
- -- table control: travel
- Syn_tab_travel:
- process ( dg_clk, dg_rst)
- begin
- if dg_rst = '1' then
- tab_travel <= '0';
- elsif dg_clk'event and dg_clk = '1' then
- if tab_enable_bit='1' then
- tab_travel <= '1';
- elsif tab_halt='1' then
- tab_travel <= '0';
- else
- tab_travel <= tab_travel;
- end if;
- end if;
- end process;
-
- -- table control: halt
- Syn_tab_halt:
- process ( dg_clk, dg_rst)
- begin
- if dg_rst = '1' then
- tab_halt <= '1';
- dg_Halt_State <= dgST_RESET;
- elsif dg_clk'event and dg_clk = '1' then
-
- case dg_Halt_State is
- when dgST_RESET =>
- dg_Halt_State <= dgST_Run;
- tab_halt <= '0';
-
- when dgST_Run =>
- if tab_stop_bit='1' then
- dg_Halt_State <= dgST_Halt;
- tab_halt <= '1';
- else
- dg_Halt_State <= dgST_Run;
- tab_halt <= '0';
- end if;
-
- when OTHERS => -- dgST_Halt
- dg_Halt_State <= dgST_Halt;
- tab_halt <= '1';
-
- end case;
-
- end if;
- end process;
-
-
- -- table read address latch
- Syn_tab_rd_address:
- process ( dg_clk, dg_rst)
- begin
- if dg_rst = '1' then
- tab_ra_r1 <= (OTHERS=>'0');
- elsif dg_clk'event and dg_clk = '1' then
- if tab_travel='1'
- and delay_time_over='1'
- and
- (
- (congest_daq='0' and tab_class_bits=C_CLASS_DAQ)
- or
- (congest_ctl='0' and tab_class_bits=C_CLASS_CTL)
- ) then
- tab_ra_r1 <= tab_rq(59 downto 48);
- else
- tab_ra_r1 <= tab_ra_r1;
- end if;
- end if;
- end process;
-
-
- -- Delay time over
- Syn_delay_time_over:
- process ( dg_clk, dg_rst)
- begin
- if dg_rst = '1' then
- delay_time_over <= '0';
- delay_counter <= (OTHERS=>'0');
- elsif dg_clk'event and dg_clk = '1' then
- if delay_time_over='1' then
- if tab_rq(47 downto 32)=C_ALL_ZEROS(47 downto 32)
- or tab_stop_bit='1' then
- delay_counter <= (OTHERS=>'0');
- delay_time_over <= '1';
- else
- delay_counter <= tab_rq(47 downto 32);
- delay_time_over <= '0';
- end if;
- else
- if delay_counter=C_ALL_ZEROS(47 downto 32) then
- delay_counter <= (OTHERS=>'0');
- delay_time_over <= '1';
- else
- delay_counter <= delay_counter - '1';
- delay_time_over <= '0';
- end if;
- end if;
-
- end if;
- end process;
-
-
- -- table control: Congestion
- Syn_tab_Congest:
- process ( dg_clk, dg_rst)
- begin
- if dg_rst = '1' then
- congest_daq <= '0';
- congest_ctl <= '0';
- elsif dg_clk'event and dg_clk = '1' then
- if tab_class_bits=C_CLASS_DAQ and tab_eop_bit='1' and data_rec_stop='1' then
- congest_daq <= '1';
- elsif congest_daq='1' and (tab_class_bits/=C_CLASS_DAQ or data_rec_stop='0') then
- congest_daq <= '0';
- else
- congest_daq <= congest_daq;
- end if;
-
- if tab_class_bits=C_CLASS_CTL and tab_eop_bit='1' and ctrl_rec_stop='1' then
- congest_ctl <= '1';
- elsif congest_ctl='1' and (tab_class_bits/=C_CLASS_CTL or ctrl_rec_stop='0') then
- congest_ctl <= '0';
- else
- congest_ctl <= congest_ctl;
- end if;
- end if;
- end process;
-
-
- -- table output: daq
- Syn_tab_to_daq:
- process ( dg_clk, dg_rst)
- begin
- if dg_rst = '1' then
- data_rec_start_i <= '0';
- data_rec_end_i <= '0';
- data_rec_i <= (OTHERS=>'0');
- crc_error_rec_i <= '0';
- elsif dg_clk'event and dg_clk = '1' then
- if tab_class_bits=C_CLASS_DAQ then
- if tab_halt='1' then
- data_rec_start_i <= '0';
- data_rec_end_i <= '0';
- data_rec_i <= (OTHERS=>'0');
- crc_error_rec_i <= '0';
- elsif congest_daq='1' then
- data_rec_start_i <= data_rec_start_i;
- data_rec_end_i <= data_rec_end_i;
- data_rec_i <= data_rec_i;
- crc_error_rec_i <= crc_error_rec_i;
- else
- data_rec_start_i <= tab_sop_bit and tab_travel and delay_time_over;
- data_rec_end_i <= tab_eop_bit and tab_travel and delay_time_over;
- data_rec_i <= tab_rq(16-1 downto 0)&tab_rq(16-1 downto 0)&tab_rq(16-1 downto 0)&tab_rq(16-1 downto 0);
- crc_error_rec_i <= tab_cerr_bit and tab_travel and delay_time_over;
- end if;
- else
- data_rec_start_i <= '0';
- data_rec_end_i <= '0';
- data_rec_i <= (OTHERS=>'0');
- crc_error_rec_i <= '0';
- end if;
- end if;
- end process;
-
-
- -- table output: ctl
- Syn_tab_to_ctl:
- process ( dg_clk, dg_rst)
- begin
- if dg_rst = '1' then
- ctrl_rec_start_i <= '0';
- ctrl_rec_end_i <= '0';
- ctrl_rec_i <= (OTHERS=>'0');
- elsif dg_clk'event and dg_clk = '1' then
- if tab_class_bits=C_CLASS_CTL then
- if tab_halt='1' then
- ctrl_rec_start_i <= '0';
- ctrl_rec_end_i <= '0';
- ctrl_rec_i <= (OTHERS=>'0');
- elsif congest_ctl='1' then
- ctrl_rec_start_i <= ctrl_rec_start_i;
- ctrl_rec_end_i <= ctrl_rec_end_i;
- ctrl_rec_i <= ctrl_rec_i;
- else
- ctrl_rec_start_i <= tab_sop_bit and tab_travel and delay_time_over;
- ctrl_rec_end_i <= tab_eop_bit and tab_travel and delay_time_over;
- ctrl_rec_i <= tab_rq(16-1 downto 0);
- end if;
- else
- ctrl_rec_start_i <= '0';
- ctrl_rec_end_i <= '0';
- ctrl_rec_i <= (OTHERS=>'0');
- end if;
- end if;
- end process;
-
-
- -- table output: dlm
- Syn_tab_to_dlm:
- process ( dg_clk, dg_rst)
- begin
- if dg_rst = '1' then
- dlm_rec_va_i <= '0';
- dlm_rec_type_i <= (OTHERS=>'0');
- elsif dg_clk'event and dg_clk = '1' then
- if tab_class_bits=C_CLASS_DLM then
- if tab_halt='1' then
- dlm_rec_va_i <= '0';
- dlm_rec_type_i <= (OTHERS=>'0');
- else
- dlm_rec_va_i <= (tab_sop_bit or tab_eop_bit) and tab_travel and delay_time_over;
- dlm_rec_type_i <= tab_rq(4-1 downto 0);
- end if;
- else
- dlm_rec_va_i <= '0';
- dlm_rec_type_i <= (OTHERS=>'0');
- end if;
- end if;
- end process;
-
-
-end Behavioral;
Index: branches/Virtex6/ML605/v6pcie.xise
===================================================================
--- branches/Virtex6/ML605/v6pcie.xise (revision 9)
+++ branches/Virtex6/ML605/v6pcie.xise (nonexistent)
@@ -1,651 +0,0 @@
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Index: branches/Virtex6/ML605/FIFO_Wrapper.vhd
===================================================================
--- branches/Virtex6/ML605/FIFO_Wrapper.vhd (revision 9)
+++ branches/Virtex6/ML605/FIFO_Wrapper.vhd (nonexistent)
@@ -1,133 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: ZITI
--- Engineer: wgao
---
--- Create Date: 16:37:22 12 Feb 2009
--- Design Name:
--- Module Name: eb_wrapper - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.abb64Package.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity eb_wrapper is
- Generic (
- C_ASYNFIFO_WIDTH : integer := 72
- );
- Port (
- wr_clk : IN std_logic;
- wr_en : IN std_logic;
- din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
- pfull : OUT std_logic;
- full : OUT std_logic;
-
- rd_clk : IN std_logic;
- rd_en : IN std_logic;
- dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
- pempty : OUT std_logic;
- empty : OUT std_logic;
-
- data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
- rst : IN std_logic
- );
-end entity eb_wrapper;
-
-
-architecture Behavioral of eb_wrapper is
-
- --- 16384 x 72
- component eb_fifo
- port (
- wr_clk : IN std_logic;
- wr_en : IN std_logic;
- din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
- prog_full : OUT std_logic;
- full : OUT std_logic;
-
- rd_clk : IN std_logic;
- rd_en : IN std_logic;
- dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
- prog_empty : OUT std_logic;
- empty : OUT std_logic;
-
- rst : IN std_logic
- );
- end component;
-
- --- 16384 x 72, with data count synchronized to rd_clk
- component v6_eb_fifo_counted
- port (
- wr_clk : IN std_logic;
- wr_en : IN std_logic;
- din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
- prog_full : OUT std_logic;
- full : OUT std_logic;
-
- rd_clk : IN std_logic;
- rd_en : IN std_logic;
- dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
- prog_empty : OUT std_logic;
- empty : OUT std_logic;
- rd_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
-
- rst : IN std_logic
- );
- end component;
-
- signal data_count_wire : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
- signal data_count_i : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
-
-begin
-
- data_count <= data_count_i;
-
- -- ------------------------------------------
- Syn_EB_FIFO_data_count:
- process (rd_clk)
- begin
- if rd_clk'event and rd_clk = '1' then
- data_count_i <= data_count_wire;
- end if;
- end process;
-
- -- ------------------------------------------
- U0:
- v6_eb_fifo_counted
- port map (
- wr_clk => wr_clk ,
- wr_en => wr_en ,
- din => din ,
- prog_full => pfull ,
- full => full ,
-
- rd_clk => rd_clk ,
- rd_en => rd_en ,
- dout => dout ,
- prog_empty => pempty ,
- empty => empty ,
- rd_data_count => data_count_wire ,
-
- rst => rst
- );
-
-end architecture Behavioral;
Index: branches/Virtex6/ML605/rx_CplD_Channel.vhd
===================================================================
--- branches/Virtex6/ML605/rx_CplD_Channel.vhd (revision 9)
+++ branches/Virtex6/ML605/rx_CplD_Channel.vhd (nonexistent)
@@ -1,1770 +0,0 @@
-----------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Design Name:
--- Module Name: rx_CplD_Transact - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision 1.10 - x4 timing constraints met. 02.02.2007
---
--- Revision 1.04 - Timing improved. 17.01.2007
---
--- Revision 1.02 - FIFO added. 20.12.2006
---
--- Revision 1.00 - first release. 14.12.2006
---
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.abb64Package.all;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity rx_CplD_Transact is
- port (
- -- Transaction receive interface
- trn_rsof_n : IN std_logic;
- trn_reof_n : IN std_logic;
- trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
- trn_rerrfwd_n : IN std_logic;
- trn_rsrc_rdy_n : IN std_logic;
- trn_rdst_rdy_n : IN std_logic; -- !!
- trn_rsrc_dsc_n : IN std_logic;
- trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
--- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
--- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
--- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
--- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
--- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
--- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
-
-
- CplD_Type : IN std_logic_vector(3 downto 0);
-
- Req_ID_Match : IN std_logic;
- usDex_Tag_Matched : IN std_logic;
- dsDex_Tag_Matched : IN std_logic;
-
- Tlp_has_4KB : IN std_logic;
- Tlp_has_1DW : IN std_logic;
- CplD_on_Pool : IN std_logic;
- CplD_on_EB : IN std_logic;
- CplD_is_the_Last : IN std_logic;
- CplD_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
- FC_pop : OUT std_logic;
-
-
- -- Downstream DMA transferred bytes count up
- ds_DMA_Bytes_Add : OUT std_logic;
- ds_DMA_Bytes : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-
-
- -- Tag output to downstream DMA channel
- dsDMA_dex_Tag : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
-
- -- Downstream Handshake Signals with ds Channel for Busy/Done
- Tag_Map_Clear : OUT std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
-
-
- -- Downstream tRAM port A write request
- tRAM_weB : IN std_logic;
- tRAM_addrB : IN std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
- tRAM_dinB : IN std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-
- -- Tag output to upstream DMA channel
- usDMA_dex_Tag : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
-
- -- Event Buffer write port
- eb_FIFO_we : OUT std_logic;
- eb_FIFO_wsof : OUT std_logic;
- eb_FIFO_weof : OUT std_logic;
- eb_FIFO_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- Registers Write Port
- Regs_WrEn : OUT std_logic;
- Regs_WrMask : OUT std_logic_vector(2-1 downto 0);
- Regs_WrAddr : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
- Regs_WrDin : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- DDR write port
- DDR_wr_sof : OUT std_logic;
- DDR_wr_eof : OUT std_logic;
- DDR_wr_v : OUT std_logic;
- DDR_wr_FA : OUT std_logic;
- DDR_wr_Shift : OUT std_logic;
- DDR_wr_Mask : OUT std_logic_vector(2-1 downto 0);
- DDR_wr_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- DDR_wr_full : IN std_logic;
-
- -- Common ports
- trn_clk : IN std_logic;
- trn_reset_n : IN std_logic;
- trn_lnk_up_n : IN std_logic
-
- );
-
-end entity rx_CplD_Transact;
-
-
-
-architecture Behavioral of rx_CplD_Transact is
-
- type RxCplDEBStates is ( ST_EBWR_IDLE
- , ST_EBWR_TAG
- , ST_EBWR_DATA
- );
-
- signal EB_Write_State : RxCplDEBStates;
-
-
- type RxCplDTrnStates is ( ST_CplD_RESET
- , ST_CplD_IDLE
--- , ST_Cpl_HEAD1 -- Cpl Header #1 (not used)
--- , ST_CplD_HEAD1 -- CplD Header #1
- , ST_Cpl_HEAD2 -- Cpl Header #2 (not used)
- , ST_CplD_HEAD2 -- CplD Header #2
- , ST_CplD_AFetch_Special --
- , ST_CplD_AFetch_Special_Tail --
- , ST_CplD_AFetch -- Target address fetch from tRAM/registers
- , ST_CplD_AFetch_THROTTLE -- Target address fetch throttled
- , ST_CplD_ONLY_1DW -- Current CplD has only 1 DW
--- , ST_CplD_ONLY_1DW_THROTTLE -- Current CplD has only 1 DW, throttled
- , ST_CplD_1ST_DATA -- 1st data payload of the CplD
- , ST_CplD_1ST_DATA_THROTTLE -- 1st data payload of the CplD
- , ST_CplD_DATA -- data receiving
- , ST_CplD_DATA_THROTTLE -- data receiving throttled
- , ST_CplD_LAST_DATA -- Last data payload of the CplD
- );
-
- -- State variables
- signal RxCplDTrn_NextState : RxCplDTrnStates;
- signal RxCplDTrn_State : RxCplDTrnStates;
-
- -- State delay
- signal RxCplDTrn_State_r1 : RxCplDTrnStates;
- signal RxCplDTrn_State_r2 : RxCplDTrnStates;
-
- signal CplD_State_is_AFetch : std_logic;
- signal CplD_State_is_after_AFetch : std_logic;
- signal CplD_State_is_AFetch_r1 : std_logic;
-
-
- -- Shifted-glued payload
- signal concat_rd : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
-
- -- trn_rx stubs
- signal trn_rd_i : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
- signal trn_rd_r1 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
- signal trn_rd_r2 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
- signal trn_rd_r3 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
- signal trn_rd_r4 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
-
- -- trn_rd_* in little endian
- signal trn_rd_Little : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
- signal trn_rd_Little_r1 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
- signal trn_rd_Little_r2 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
- signal trn_rd_Little_r3 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
- signal trn_rd_Little_r4 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
-
- -- signal trn_rbar_hit_n_i : std_logic_vector(C_BAR_NUMBER-1 downto 0);
- signal trn_rerrfwd_n_i : std_logic;
- signal trn_rsrc_dsc_n_i : std_logic;
-
- signal trn_rsof_n_i : std_logic;
- signal trn_reof_n_i : std_logic;
- signal trn_reof_n_r1 : std_logic;
- signal trn_reof_n_r2 : std_logic;
- signal trn_reof_n_r3 : std_logic;
- signal trn_reof_n_r4 : std_logic;
-
--- signal Tlp_has_4KB_r1 : std_logic;
- signal trn_rrem_n_i : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
- signal trn_rrem_n_r1 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
- signal trn_rrem_n_r2 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
- signal trn_rrem_n_r3 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
- signal trn_rrem_n_r4 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
-
- -- Whether address increases
- signal Addr_Inc : std_logic;
-
- -- Spaces hit
--- signal FIFO_Space_Hit : std_logic;
- signal DDR_Space_Hit : std_logic;
-
-
- -- DDR write port
- signal DDR_wr_sof_i : std_logic;
- signal DDR_wr_eof_i : std_logic;
- signal DDR_wr_v_i : std_logic;
- signal DDR_wr_FA_i : std_logic;
- signal DDR_wr_Shift_i : std_logic;
- signal DDR_wr_Mask_i : std_logic_vector(2-1 downto 0);
- signal DDR_wr_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
- signal DDR_wr_full_i : std_logic;
-
-
- -- Event Buffer write port
- signal eb_FIFO_we_i : std_logic;
- signal eb_FIFO_wsof_i : std_logic;
- signal eb_FIFO_weof_i : std_logic;
- signal eb_FIFO_sof_marker : std_logic;
- signal eb_FIFO_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- Register write port
- signal Regs_WrEn_i : std_logic;
- signal Regs_WrMask_i : std_logic_vector(2-1 downto 0);
- signal Regs_WrAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
- signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-
- -- Calculation @ trn_rsof_n=0
- signal Dex_CplD_Illegal : std_logic;
- signal Reg_WrAddr_if_last_us: std_logic_vector(C_EP_AWIDTH-1 downto 0);
- signal Reg_WrAddr_if_last_ds: std_logic_vector(C_EP_AWIDTH-1 downto 0);
-
-
- -- Flow control signals
- signal trn_rdst_rdy_n_i : std_logic;
- signal trn_rsrc_rdy_n_i : std_logic;
- signal trn_rsrc_rdy_n_r1 : std_logic;
- signal trn_rsrc_rdy_n_r2 : std_logic;
- signal trn_rsrc_rdy_n_r3 : std_logic;
- signal trn_rsrc_rdy_n_r4 : std_logic;
-
-
- signal trn_rx_throttle : std_logic;
- signal trn_rx_throttle_r1 : std_logic;
- signal trn_rx_throttle_r2 : std_logic;
- signal trn_rx_throttle_r3 : std_logic;
- signal trn_rx_throttle_r4 : std_logic;
-
-
- -- Downstream DMA transferred bytes count up
- signal ds_DMA_Bytes_Add_i : std_logic;
- signal ds_DMA_Bytes_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
- signal CplD_is_Payloaded : std_logic;
-
- -- Alias for header resolution
- signal CplD_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto 0);
- signal CplD_Leng_in_Bytes : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
- signal CplD_Leng_in_Bytes_r1: std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
- signal CplD_is_1DW : std_logic;
- -- Small_CplD means CplD with less than 4 DW payload
- signal Small_CplD : std_logic;
- signal Small_CplD_r1 : std_logic;
-
-
- signal RegAddr_us_Dex : std_logic_vector(C_EP_AWIDTH-1 downto 0);
- signal RegAddr_ds_Dex : std_logic_vector(C_EP_AWIDTH-1 downto 0);
-
- signal CplD_Tag_on_Dex : std_logic;
-
- -- ----------------------------------------------------------------------
- signal Req_ID_Match_i : std_logic;
- signal Dex_Tag_Matched_i : std_logic;
-
- -- The top bit of the CplD_Tag is for distinguishing data CplD or descriptor CplD
- signal MSB_DSP_Tag : std_logic;
- signal MSB_DSP_Tag_r1 : std_logic;
- signal DSP_Tag_on_RAM : std_logic;
- signal DSP_Tag_on_RAM_r1 : std_logic;
- signal DSP_Tag_on_RAM_r2 : std_logic;
- signal DSP_Tag_on_RAM_r3 : std_logic;
- signal DSP_Tag_on_RAM_r4p : std_logic;
- signal DSP_Tag_on_FIFO : std_logic;
- -- ----------------------------------------------------------------------
- signal FC_pop_i : std_logic;
-
-
- signal Tag_Map_Clear_i : std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
-
- signal Local_Reset_i : std_logic;
-
-
- -- upstream Descriptors' tags
- signal usDMA_dex_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-
- -- downstream Descriptors' tags
- signal dsDMA_dex_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-
-
--- --- ------------------------------------------
--- --- Dual port Block Memory, used as tag RAM
--- component
--- v5tagram64x36
--- port (
--- clka : IN std_logic;
--- addra : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
--- wea : IN std_logic_vector(0 downto 0);
--- dina : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
--- douta : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
--- clkb : IN std_logic;
--- addrb : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
--- web : IN std_logic_vector(0 downto 0);
--- dinb : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
--- doutb : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0)
--- );
--- end component;
-
- --- ------------------------------------------
- --- Dual port Block Memory, used as tag RAM
- component
- FF_TagRam64x36
- port (
- clk : IN std_logic;
- addra : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
- wea : IN std_logic;
- dina : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
- douta : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
- addrb : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
- web : IN std_logic;
- dinb : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
- doutb : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0)
- );
- end component;
-
- signal tRAM_wea : std_logic_vector(0 downto 0);
- signal tRAM_addra : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
- signal tRAM_dina : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
- signal tRAM_doutA : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
- signal tRAM_weB_i : std_logic_vector(0 downto 0);
-
- signal tRAM_DoutA_r1 : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
- signal tRAM_DoutA_r2 : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
- signal tRAM_dina_aInc : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
- signal tRAM_DoutA_latch : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-
- -- updates the tag RAM as soon as possible
- signal CplD_is_the_Last_r1 : std_logic;
- signal Updates_tRAM : std_logic;
- signal Updates_tRAM_r1 : std_logic;
- signal Update_was_too_late : std_logic;
-
- signal hazard_update : std_logic;
- signal hazard_update_r1 : std_logic;
- signal hazard_update_r2 : std_logic;
- signal hazard_update_r3 : std_logic;
- signal hazard_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0);
- signal hazard_content : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
- signal tag_matches_hazard : std_logic;
-
- -- aka TLB unit
- signal TLB_Addr : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
- signal TLB_Content : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
- signal TLB_cnt : std_logic_vector(4-1 downto 0);
- signal TLB_Valid : std_logic;
- signal TLB_Hit : std_logic;
-
- Constant C_TLB_VALID_CNT : std_logic_vector(4-1 downto 0) := X"6";
-
-begin
-
- -- Event Buffer write
- eb_FIFO_we <= eb_FIFO_we_i ;
- eb_FIFO_wsof <= eb_FIFO_wsof_i ;
- eb_FIFO_weof <= eb_FIFO_weof_i ;
- eb_FIFO_din <= eb_FIFO_din_i ;
-
- -- DDR
- DDR_wr_sof <= DDR_wr_sof_i ;
- DDR_wr_eof <= DDR_wr_eof_i ;
- DDR_wr_v <= DDR_wr_v_i ;
- DDR_wr_FA <= DDR_wr_FA_i ;
- DDR_wr_Shift <= DDR_wr_Shift_i ;
- DDR_wr_Mask <= DDR_wr_Mask_i ;
- DDR_wr_din <= DDR_wr_din_i ;
- DDR_wr_full_i <= DDR_wr_full ;
-
- ds_DMA_Bytes_Add <= ds_DMA_Bytes_Add_i ;
- ds_DMA_Bytes <= ds_DMA_Bytes_i ;
-
- --
- Tag_Map_Clear <= Tag_Map_Clear_i;
-
- --
- FC_pop <= FC_pop_i;
- -- ----------------------------------------------
- --
- Syn_FC_pop:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- FC_pop_i <= '0';
- elsif trn_clk'event and trn_clk = '1' then
- FC_pop_i <= (CplD_on_Pool or CplD_on_EB)
- and CplD_is_the_Last
- and not MSB_DSP_Tag
- and not trn_reof_n_i
- and trn_reof_n_r1 -- Catch the falling edge of trn_reof_n
--- and not trn_rx_throttle
- ;
- end if;
-
- end process;
-
- -- ----------------------------------------------
- -- Synchronous: CplD_is_Payloaded
- --
- Syn_CplD_is_Payloaded:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- CplD_is_Payloaded <= '0';
- elsif trn_clk'event and trn_clk = '1' then
- if trn_rsof_n_i='0' and trn_rx_throttle='0' then
- CplD_is_Payloaded <= CplD_Type(3) or CplD_Type(1);
- else
- CplD_is_Payloaded <= CplD_is_Payloaded;
- end if;
- end if;
-
- end process;
-
-
- -- ----------------------------------------------
- -- Synchronous Accumulation: us_DMA_Bytes
- --
- Syn_ds_DMA_Bytes_Add:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- ds_DMA_Bytes_Add_i <= '0' ;
- ds_DMA_Bytes_i <= (OTHERS=>'0');
- elsif trn_clk'event and trn_clk = '1' then
- if trn_reof_n_i='0' and trn_rx_throttle='0'
- and CplD_is_Payloaded='1' and MSB_DSP_Tag='0'
- then
- ds_DMA_Bytes_Add_i <= '1' ;
- ds_DMA_Bytes_i <= CplD_Leng_in_Bytes(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
- else
- ds_DMA_Bytes_Add_i <= '0' ;
- ds_DMA_Bytes_i <= (OTHERS=>'0');
- end if;
- end if;
-
- end process;
-
-
- -- Registers writing
- Regs_WrEn <= Regs_WrEn_i;
- Regs_WrMask <= Regs_WrMask_i;
- Regs_WrAddr <= Regs_WrAddr_i;
- Regs_WrDin <= Regs_WrDin_i;
-
-
- --- Dex Tag output to us DMA channel
- usDMA_dex_Tag <= usDMA_dex_Tag_i;
-
- --- Dex Tag output to ds DMA channel
- dsDMA_dex_Tag <= dsDMA_dex_Tag_i;
-
-
- ---------------------------------------------------
- Req_ID_Match_i <= Req_ID_Match;
-
- Dex_Tag_Matched_i <= usDex_Tag_Matched or dsDex_Tag_Matched;
-
- -- positive reset
- Local_Reset_i <= not trn_reset_n;
-
-
- -- Frame signals
- trn_rsof_n_i <= trn_rsof_n;
- trn_reof_n_i <= trn_reof_n;
- trn_rd_i <= trn_rd;
- trn_rrem_n_i <= trn_rrem_n;
- trn_rsrc_rdy_n_i <= trn_rsrc_rdy_n;
- trn_rdst_rdy_n_i <= trn_rdst_rdy_n;
-
-
- -- BC of the current TLP payloads
- CplD_Leng_in_Bytes <= C_ALL_ZEROS(C_DBUS_WIDTH/2-1 downto C_TLP_FLD_WIDTH_OF_LENG+3)
- & CplD_Length & "00";
-
-
- -- Exception signals
- trn_rerrfwd_n_i <= trn_rerrfwd_n;
- trn_rsrc_dsc_n_i <= trn_rsrc_dsc_n;
-
-
- -- ( trn_rsrc_rdy_n seems never deasserted during packet)
- trn_rx_throttle <= trn_rsrc_rdy_n_i or trn_rdst_rdy_n_i;
-
-
-
--- ---------------------------------------------
--- Synchronous bit: CplD_State_is_AFetch
---
- RxFSM_CplD_State_is_AFetch:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
-
- CplD_State_is_AFetch_r1 <= CplD_State_is_AFetch;
-
- case RxCplDTrn_State is
- when ST_CplD_AFetch =>
- CplD_State_is_AFetch <= '1';
- when ST_CplD_AFetch_Special =>
- CplD_State_is_AFetch <= '1';
- when OTHERS =>
- CplD_State_is_AFetch <= '0';
- end case;
-
- end if;
- end process;
-
-
--- ---------------------------------------------
--- Synchronous bit: CplD_State_is_after_AFetch
---
- RxFSM_CplD_State_is_after_AFetch:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
-
- case RxCplDTrn_State is
- when ST_CplD_AFetch_Special_Tail =>
- CplD_State_is_after_AFetch <= '1';
- when ST_CplD_ONLY_1DW =>
- CplD_State_is_after_AFetch <= '1';
- when ST_CplD_1ST_DATA =>
- CplD_State_is_after_AFetch <= '1';
- when OTHERS =>
- CplD_State_is_after_AFetch <= '0';
- end case;
-
- end if;
- end process;
-
-
--- ---------------------------------------------
--- Delay Synchronous Delay: trn_r*
---
- Syn_Delay_trn_r_x:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
- trn_reof_n_r1 <= trn_reof_n_i;
- trn_reof_n_r2 <= trn_reof_n_r1;
- trn_reof_n_r3 <= trn_reof_n_r2;
- trn_reof_n_r4 <= trn_reof_n_r3;
-
- trn_rsrc_rdy_n_r1 <= trn_rx_throttle; -- trn_rsrc_rdy_n_i;
- trn_rsrc_rdy_n_r2 <= trn_rsrc_rdy_n_r1;
- trn_rsrc_rdy_n_r3 <= trn_rsrc_rdy_n_r2;
- trn_rsrc_rdy_n_r4 <= trn_rsrc_rdy_n_r3;
-
- trn_rx_throttle_r1 <= trn_rx_throttle;
- trn_rx_throttle_r2 <= trn_rx_throttle_r1;
- trn_rx_throttle_r3 <= trn_rx_throttle_r2;
- trn_rx_throttle_r4 <= trn_rx_throttle_r3;
-
--- DDR_wr_full_r1 <= DDR_wr_full_i;
--- DDR_wr_full_r2 <= DDR_wr_full_r1;
-
- trn_rd_r1 <= trn_rd_i;
- trn_rd_r2 <= trn_rd_r1;
- trn_rd_r3 <= trn_rd_r2;
- trn_rd_r4 <= trn_rd_r3;
-
- trn_rrem_n_r1 <= trn_rrem_n_i;
- trn_rrem_n_r2 <= trn_rrem_n_r1;
- trn_rrem_n_r3 <= trn_rrem_n_r2;
- trn_rrem_n_r4 <= trn_rrem_n_r3;
-
- end if;
- end process;
-
-
- -- Endian reversed
- trn_rd_Little <= Endian_Invert_64 (trn_rd_i);
- trn_rd_Little_r1 <= Endian_Invert_64 (trn_rd_r1);
- trn_rd_Little_r2 <= Endian_Invert_64 (trn_rd_r2);
- trn_rd_Little_r3 <= Endian_Invert_64 (trn_rd_r3);
- trn_rd_Little_r4 <= Endian_Invert_64 (trn_rd_r4);
-
-
--- ---------------------------------------------
- MSB_DSP_Tag <= CplD_Tag(C_TAG_WIDTH-1);
- DSP_Tag_on_RAM <= not CplD_Tag(C_TAG_WIDTH-1) and not CplD_Tag(C_TAG_WIDTH-2);
- DSP_Tag_on_FIFO <= not CplD_Tag(C_TAG_WIDTH-1) and CplD_Tag(C_TAG_WIDTH-2);
-
---
--- Delay Synchronous: MSB_DSP_Tag_r1
---
- Syn_Delay_MSB_DSP_Tag_r1:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
- MSB_DSP_Tag_r1 <= MSB_DSP_Tag;
- DSP_Tag_on_RAM_r1 <= DSP_Tag_on_RAM;
- DSP_Tag_on_RAM_r2 <= DSP_Tag_on_RAM_r1;
- DSP_Tag_on_RAM_r3 <= DSP_Tag_on_RAM_r2;
- DSP_Tag_on_RAM_r4p <= DSP_Tag_on_RAM_r2 or DSP_Tag_on_RAM_r3;
- end if;
- end process;
-
-
---
--- Delay Synchronous: CplD_Leng_in_Bytes
---
- Syn_Delay_CplD_Leng_in_Bytes:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
- CplD_Leng_in_Bytes_r1 <= CplD_Leng_in_Bytes;
- end if;
- end process;
-
-
--- ---------------------------------------------
--- Delay Synchronous Delay: RxCplDTrn_State
---
- RxFSM_Delay_RxTrn_State:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
- RxCplDTrn_State_r1 <= RxCplDTrn_State;
- RxCplDTrn_State_r2 <= RxCplDTrn_State_r1;
- end if;
- end process;
-
-
--- ----------------------------------------------
--- States synchronous
---
- Syn_RxTrn_States:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- RxCplDTrn_State <= ST_CplD_RESET;
- elsif trn_clk'event and trn_clk = '1' then
- RxCplDTrn_State <= RxCplDTrn_NextState;
- end if;
-
- end process;
-
-
--- Next States
- Comb_RxTrn_NextStates:
- process (
- RxCplDTrn_State
- , CplD_Type
- , MSB_DSP_Tag
- , trn_reof_n_i
- , trn_rx_throttle
- , Req_ID_Match_i
- , Dex_Tag_Matched_i
- )
- begin
- case RxCplDTrn_State is
-
- when ST_CplD_RESET =>
- RxCplDTrn_NextState <= ST_CplD_IDLE;
-
- when ST_CplD_IDLE =>
-
- if trn_rx_throttle='0' then
- case CplD_Type is
- when C_TLP_TYPE_IS_CPLD =>
- RxCplDTrn_NextState <= ST_CplD_HEAD2;
- when C_TLP_TYPE_IS_CPL =>
- RxCplDTrn_NextState <= ST_Cpl_HEAD2;
- when C_TLP_TYPE_IS_CPLDLK =>
- RxCplDTrn_NextState <= ST_CplD_HEAD2;
- when C_TLP_TYPE_IS_CPLLK =>
- RxCplDTrn_NextState <= ST_Cpl_HEAD2;
- when OTHERS =>
- RxCplDTrn_NextState <= ST_CplD_IDLE;
- end case; -- CplD_Type
- else
- RxCplDTrn_NextState <= ST_CplD_IDLE;
- end if;
-
-
-
- when ST_Cpl_HEAD2 => -- further processing to be done ...
- RxCplDTrn_NextState <= ST_CplD_IDLE;
-
-
- when ST_CplD_HEAD2 =>
- if trn_rx_throttle = '1' then
- RxCplDTrn_NextState <= ST_CplD_HEAD2;
- elsif Req_ID_Match_i='1' and Dex_Tag_Matched_i='1' then
- if trn_reof_n_i='0' then
- RxCplDTrn_NextState <= ST_CplD_AFetch_Special;
- else
- RxCplDTrn_NextState <= ST_CplD_AFetch;
- end if;
- elsif Req_ID_Match_i='1' and MSB_DSP_Tag='0' then
- if trn_reof_n_i='0' then
- RxCplDTrn_NextState <= ST_CplD_AFetch_Special;
- else
- RxCplDTrn_NextState <= ST_CplD_AFetch;
- end if;
- else
- RxCplDTrn_NextState <= ST_CplD_IDLE;
- end if;
-
-
- when ST_CplD_AFetch =>
- if trn_reof_n_i='0' then
- RxCplDTrn_NextState <= ST_CplD_ONLY_1DW;
- elsif trn_rx_throttle = '1' then
- RxCplDTrn_NextState <= ST_CplD_AFetch_THROTTLE;
- else
- RxCplDTrn_NextState <= ST_CplD_1ST_DATA;
- end if;
-
- when ST_CplD_AFetch_Special =>
- -- !!!!!!!!!!!!!!
- -- Suppose 1DW CplD (sof-eof TLP) is not followed back-to-back
- -- !!!!!!!!!!!!!!
- RxCplDTrn_NextState <= ST_CplD_AFetch_Special_Tail;
-
-
- when ST_CplD_AFetch_Special_Tail =>
- if trn_rx_throttle='0' then
- case CplD_Type is
- when C_TLP_TYPE_IS_CPLD =>
- RxCplDTrn_NextState <= ST_CplD_HEAD2;
- when C_TLP_TYPE_IS_CPL =>
- RxCplDTrn_NextState <= ST_Cpl_HEAD2;
- when C_TLP_TYPE_IS_CPLDLK =>
- RxCplDTrn_NextState <= ST_CplD_HEAD2;
- when C_TLP_TYPE_IS_CPLLK =>
- RxCplDTrn_NextState <= ST_Cpl_HEAD2;
- when OTHERS =>
- RxCplDTrn_NextState <= ST_CplD_IDLE;
- end case; -- CplD_Type
- else
- RxCplDTrn_NextState <= ST_CplD_IDLE;
- end if;
-
-
- when ST_CplD_AFetch_THROTTLE =>
- if trn_reof_n_i='0' then
- RxCplDTrn_NextState <= ST_CplD_ONLY_1DW;
- elsif trn_rx_throttle = '1' then
- RxCplDTrn_NextState <= ST_CplD_AFetch_THROTTLE;
- else
- RxCplDTrn_NextState <= ST_CplD_1ST_DATA;
- end if;
-
-
- when ST_CplD_ONLY_1DW =>
- if trn_rx_throttle='0' then
- case CplD_Type is
- when C_TLP_TYPE_IS_CPLD =>
- RxCplDTrn_NextState <= ST_CplD_HEAD2;
- when C_TLP_TYPE_IS_CPL =>
- RxCplDTrn_NextState <= ST_Cpl_HEAD2;
- when C_TLP_TYPE_IS_CPLDLK =>
- RxCplDTrn_NextState <= ST_CplD_HEAD2;
- when C_TLP_TYPE_IS_CPLLK =>
- RxCplDTrn_NextState <= ST_Cpl_HEAD2;
- when OTHERS =>
- RxCplDTrn_NextState <= ST_CplD_IDLE;
- end case; -- CplD_Type
- else
- RxCplDTrn_NextState <= ST_CplD_IDLE;
- end if;
-
-
- when ST_CplD_1ST_DATA =>
- if trn_reof_n_i='0' then
- RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
- elsif trn_rx_throttle = '1' then
- RxCplDTrn_NextState <= ST_CplD_1ST_DATA_THROTTLE;
- else
- RxCplDTrn_NextState <= ST_CplD_DATA;
- end if;
-
- when ST_CplD_1ST_DATA_THROTTLE =>
- if trn_reof_n_i='0' then
- RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
- elsif trn_rx_throttle = '1' then
- RxCplDTrn_NextState <= ST_CplD_1ST_DATA_THROTTLE;
- else
- RxCplDTrn_NextState <= ST_CplD_DATA;
- end if;
-
-
- when ST_CplD_DATA =>
- if trn_reof_n_i='0' then
- RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
- elsif trn_rx_throttle = '1' then
- RxCplDTrn_NextState <= ST_CplD_DATA_THROTTLE;
- else
- RxCplDTrn_NextState <= ST_CplD_DATA;
- end if;
-
-
- when ST_CplD_DATA_THROTTLE =>
- if trn_reof_n_i='0' then
- RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
- elsif trn_rx_throttle = '1' then
- RxCplDTrn_NextState <= ST_CplD_DATA_THROTTLE;
- else
- RxCplDTrn_NextState <= ST_CplD_DATA;
- end if;
-
-
- when ST_CplD_LAST_DATA => -- Same as IDLE, to support
- -- back-to-back transactions
- if trn_rx_throttle='0' then
- case CplD_Type is
- when C_TLP_TYPE_IS_CPLD =>
- RxCplDTrn_NextState <= ST_CplD_HEAD2;
- when C_TLP_TYPE_IS_CPL =>
- RxCplDTrn_NextState <= ST_Cpl_HEAD2;
- when C_TLP_TYPE_IS_CPLDLK =>
- RxCplDTrn_NextState <= ST_CplD_HEAD2;
- when C_TLP_TYPE_IS_CPLLK =>
- RxCplDTrn_NextState <= ST_Cpl_HEAD2;
- when OTHERS =>
- RxCplDTrn_NextState <= ST_CplD_IDLE;
- end case; -- CplD_Type
- else
- RxCplDTrn_NextState <= ST_CplD_IDLE;
- end if;
-
-
- when OTHERS =>
- RxCplDTrn_NextState <= ST_CplD_RESET;
-
- end case;
-
- end process;
-
-
--- -------------------------------------------------
--- Synchronous Registered: Tag_Map_Clear_i
---
- RxTrn_Tag_Map_Clear:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- Tag_Map_Clear_i <= (OTHERS=>'0');
-
- elsif trn_clk'event and trn_clk = '1' then
-
- FOR j IN 0 TO C_TAG_MAP_WIDTH-1 LOOP
-
- -- CplD_Tag(C_TAG_WIDTH-2) used as token of BAR
- if CplD_Tag(C_TAG_WIDTH-1)='0'
- and CplD_Tag(C_TAG_WIDTH-2-1 downto 0)=CONV_STD_LOGIC_VECTOR(j, C_TAG_WIDTH-2)
- and CplD_is_the_Last='1' then
- Tag_Map_Clear_i(j) <= '1';
- else
- Tag_Map_Clear_i(j) <= '0';
- end if;
-
- END LOOP;
-
- end if;
- end process;
-
-
-
--- -------------------------------------------------
--- Synchronous Registered: CplD_Length
---
- RxTrn_CplD_Length:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- CplD_Length <= (OTHERS => '0');
- CplD_is_1DW <= '0';
- Small_CplD <= '0';
- Small_CplD_r1 <= '0';
-
- elsif trn_clk'event and trn_clk = '1' then
-
- Small_CplD_r1 <= Small_CplD;
-
- if trn_rsof_n_i='0' then
- CplD_Length <= Tlp_has_4KB & trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
- CplD_is_1DW <= Tlp_has_1DW;
- if trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT+2)=C_ALL_ZEROS(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT+2)
- and trn_rd_i(C_TLP_LENG_BIT_BOT+1 downto C_TLP_LENG_BIT_BOT)/="00"
- and trn_rd_i(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1)="01" -- Cpl/D
- then
- Small_CplD <= '1';
- else
- Small_CplD <= '0';
- end if;
- else
- CplD_Length <= CplD_Length;
- CplD_is_1DW <= CplD_is_1DW;
- Small_CplD <= Small_CplD;
- end if;
-
- end if;
- end process;
-
-
-
-
--- -------------------------------------------------
--- Synchronous outputs: Addr_Inc
---
- RxFSM_Output_Addr_Inc:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- Addr_Inc <= '1';
-
- elsif trn_clk'event and trn_clk = '1' then
-
- case RxCplDTrn_State_r1 is
-
- when ST_CplD_RESET =>
- Addr_Inc <= '1';
-
- when ST_CplD_1ST_DATA =>
- Addr_Inc <= tRAM_DoutA_r1(CBIT_AINC_IN_TAGRAM);
-
- when ST_CplD_ONLY_1DW =>
- Addr_Inc <= tRAM_DoutA_r1(CBIT_AINC_IN_TAGRAM);
-
- when OTHERS =>
- Addr_Inc <= Addr_Inc;
-
- end case;
- end if;
- end process;
-
-
--------------------------------------------------
--- Calculation at trn_rsof_n
---
- Syn_Dex_wrAddress:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- Dex_CplD_Illegal <= '0';
- Reg_WrAddr_if_last_us <= (OTHERS=>'0'); -- C_REGS_BASE_ADDR;
- Reg_WrAddr_if_last_ds <= (OTHERS=>'0'); -- C_REGS_BASE_ADDR;
-
- elsif trn_clk'event and trn_clk = '1' then
-
- if trn_rsof_n_i = '0' then
- Reg_WrAddr_if_last_us(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_CTRL, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
- Reg_WrAddr_if_last_ds(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_CTRL, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
--- Reg_WrAddr_if_last_us(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_STA, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
--- Reg_WrAddr_if_last_ds(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_STA, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
- else
- Reg_WrAddr_if_last_us <= Reg_WrAddr_if_last_us;
- Reg_WrAddr_if_last_ds <= Reg_WrAddr_if_last_ds;
- end if;
-
- end if;
-
- end process;
-
-
--- ---------------------------------------------
--- Reg Synchronous: RegAddr_?s_Dex
---
- RxFSM_Reg_RegAddr_xs_Dex:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- RegAddr_us_Dex <= (Others=>'1');
- RegAddr_ds_Dex <= (Others=>'1');
-
- elsif trn_clk'event and trn_clk = '1' then
-
- if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)/=C_TAG0_DMA_USB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
- RegAddr_us_Dex <= (Others=>'1');
- elsif CplD_is_the_Last = '1' then -- us last/2nd dex
- RegAddr_us_Dex <= Reg_WrAddr_if_last_us;
- else -- us 1st/unique dex
- RegAddr_us_Dex <= -- C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) & ,(C_DECODE_BIT_BOT-2)
--- CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_PAH, C_DECODE_BIT_BOT) & "00";
- CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_PAH-1, C_DECODE_BIT_BOT) & "00";
- end if;
-
-
- if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)/=C_TAG0_DMA_DSB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
- RegAddr_ds_Dex <= (Others=>'1');
- elsif CplD_is_the_Last = '1' then -- ds last/2nd dex
- RegAddr_ds_Dex <= Reg_WrAddr_if_last_ds;
- else -- ds 1st/unique dex
- RegAddr_ds_Dex <= -- C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) & ,(C_DECODE_BIT_BOT-2)
--- CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_PAH, C_DECODE_BIT_BOT) & "00";
- CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_PAH-1, C_DECODE_BIT_BOT) & "00";
- end if;
-
-
- end if;
- end process;
-
-
-
--- ---------------------------------------------
--- Reg Synchronous Delay: CplD_Tag_on_Dex
---
- RxFSM_Delay_CplD_Tag_on_Dex:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- CplD_Tag_on_Dex <= '0';
-
- elsif trn_clk'event and trn_clk = '1' then
-
- if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)=C_TAG0_DMA_USB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
- CplD_Tag_on_Dex <= '1';
- elsif CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)=C_TAG0_DMA_DSB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
- CplD_Tag_on_Dex <= '1';
- else
- CplD_Tag_on_Dex <= '0';
- end if;
-
- end if;
- end process;
-
-
--------------------------------------------------------
--- Synchronous outputs: DMA_Registers
---
- RxFSM_Output_DMA_Registers:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- Regs_WrEn_i <= '0';
- Regs_WrMask_i <= (OTHERS=>'0');
- Regs_WrDin_i <= (OTHERS => '0');
-
- elsif trn_clk'event and trn_clk = '1' then
-
- case RxCplDTrn_State is
-
- when ST_CplD_AFetch =>
- if CplD_Tag_on_Dex='1' then
- Regs_WrEn_i <= '1';
- Regs_WrMask_i <= "10";
- Regs_WrDin_i <= trn_rd_Little_r1;
- else
- Regs_WrEn_i <= '0';
- Regs_WrMask_i <= (OTHERS=>'0');
- Regs_WrDin_i <= (Others=>'0');
- end if;
-
- when ST_CplD_AFetch_Special =>
- if CplD_Tag_on_Dex='1' then
- Regs_WrEn_i <= '1';
- Regs_WrMask_i <= "10";
- Regs_WrDin_i <= trn_rd_Little_r1;
- else
- Regs_WrEn_i <= '0';
- Regs_WrMask_i <= (OTHERS=>'0');
- Regs_WrDin_i <= (Others=>'0');
- end if;
-
- when ST_CplD_1ST_DATA =>
- if CplD_Tag_on_Dex='1' then
- Regs_WrEn_i <= '1';
- Regs_WrMask_i <= (OTHERS=>'0');
- Regs_WrDin_i <= trn_rd_Little_r1;
- else
- Regs_WrEn_i <= '0';
- Regs_WrMask_i <= (OTHERS=>'0');
- Regs_WrDin_i <= (Others=>'0');
- end if;
-
- when ST_CplD_ONLY_1DW =>
- if CplD_Tag_on_Dex='1' then
- Regs_WrEn_i <= '1';
- Regs_WrMask_i <= (OTHERS=>'0');
- Regs_WrDin_i <= trn_rd_Little_r1;
- else
- Regs_WrEn_i <= '0';
- Regs_WrMask_i <= (OTHERS=>'0');
- Regs_WrDin_i <= (Others=>'0');
- end if;
-
- when ST_CplD_DATA =>
- if CplD_Tag_on_Dex='1' then
- Regs_WrEn_i <= '1';
- Regs_WrMask_i <= '0' & (trn_rrem_n_r1(3) or trn_rrem_n_r1(0));
- Regs_WrDin_i <= trn_rd_Little_r1;
- else
- Regs_WrEn_i <= '0';
- Regs_WrMask_i <= (OTHERS=>'0');
- Regs_WrDin_i <= (Others=>'0');
- end if;
-
- when ST_CplD_LAST_DATA =>
- if CplD_Tag_on_Dex='1' then
- Regs_WrEn_i <= '1';
- Regs_WrMask_i <= '0' & (trn_rrem_n_r1(3) or trn_rrem_n_r1(0));
- Regs_WrDin_i <= trn_rd_Little_r1;
- else
- Regs_WrEn_i <= '0';
- Regs_WrMask_i <= (OTHERS=>'0');
- Regs_WrDin_i <= (Others=>'0');
- end if;
-
- when OTHERS =>
- Regs_WrEn_i <= '0';
- Regs_WrMask_i <= (OTHERS=>'0');
- Regs_WrDin_i <= (Others=>'0');
-
- end case;
-
- end if;
- end process;
-
-
--------------------------------------------------------
--- Synchronous outputs: DMA_Registers write Address
---
- RxFSM_Output_DMA_Registers_WrAddr:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- Regs_WrAddr_i <= (OTHERS => '1');
-
- elsif trn_clk'event and trn_clk = '1' then
-
- case RxCplDTrn_State is
-
- when ST_CplD_IDLE =>
- Regs_WrAddr_i <= (OTHERS => '1');
-
- when ST_CplD_AFetch =>
- Regs_WrAddr_i <= RegAddr_us_Dex and RegAddr_ds_Dex;
-
- when ST_CplD_AFetch_Special =>
- Regs_WrAddr_i <= RegAddr_us_Dex and RegAddr_ds_Dex;
-
- when ST_CplD_1ST_DATA =>
- Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
- <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
-
- when ST_CplD_ONLY_1DW =>
- Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
- <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
-
- when ST_CplD_DATA =>
- Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
- <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
-
- when ST_CplD_LAST_DATA =>
- Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
- <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
-
- when OTHERS =>
- Regs_WrAddr_i <= Regs_WrAddr_i;
-
- end case;
-
- end if;
- end process;
-
-
-
------------------------------------------------------
--- Synchronous Register:
--- dsDMA_dex_Tag_i
--- usDMA_dex_Tag_i
---
- FSM_Reg_DMA_dex_Tags:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- usDMA_dex_Tag_i <= C_TAG0_DMA_USB;
- dsDMA_dex_Tag_i <= C_TAG0_DMA_DSB;
-
- elsif trn_clk'event and trn_clk = '1' then
-
- case RxCplDTrn_State is
-
- when ST_CplD_AFetch =>
-
- if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=usDMA_dex_Tag_i and CplD_is_the_Last = '1' then
- usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
- else
- usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
- end if;
-
- if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=dsDMA_dex_Tag_i and CplD_is_the_Last = '1' then
- dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
- else
- dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
- end if;
-
- when ST_CplD_AFetch_Special =>
-
- if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=usDMA_dex_Tag_i and CplD_is_the_Last = '1' then
- usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
- else
- usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
- end if;
-
- if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=dsDMA_dex_Tag_i and CplD_is_the_Last = '1' then
- dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
- else
- dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
- end if;
-
- when Others =>
- usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
- dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
-
- end case;
-
- end if;
- end process;
-
-
--- -------------------------------------------------------------
--- RAM holding downstream Tags of packet MRd requests
--- -------------------------------------------------------------
-
- tRAM_addra <= CplD_Tag(C_TAGRAM_AWIDTH-1 downto 0);
- tRAM_weB_i(0) <= tRAM_weB;
-
- dspTag_BRAM:
- FF_TagRam64x36
- port map(
- clk => trn_clk ,
-
- wea => tRAM_wea(0) ,
- addra => tRAM_addra ,
- dina => tRAM_dina ,
- douta => tRAM_doutA ,
-
- web => tRAM_weB_i(0) ,
- addrb => tRAM_addrB ,
- dinb => tRAM_dinB ,
- doutb => open
- );
-
-
--- dspTag_BRAM:
--- v5tagram64x36
--- port map(
--- clka => trn_clk ,
--- addra => tRAM_addra ,
--- wea => tRAM_wea ,
--- dina => tRAM_dina ,
--- douta => tRAM_doutA ,
--- clkb => trn_clk ,
--- addrb => tRAM_addrB ,
--- web => tRAM_weB_i ,
--- dinb => tRAM_dinB ,
--- doutb => open
--- );
-
-
--- -----------------------------------------------------------------------------------
--- Synchronous delay: CplD_is_the_Last
---
- Syn_Delay_CplD_is_the_Last:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
- CplD_is_the_Last_r1 <= CplD_is_the_Last;
- end if;
- end process;
-
--- -----------------------------------------------------------------------------------
--- Synchronous output: Updates_tRAM
--- Update happens only at data TLP
--- The last CplD of one MRd does not trigger tRAM update,
--- to enable back-to-back transactions.
---
- RxFSM_Output_Updates_tRAM:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- Updates_tRAM <= '0';
-
- elsif trn_clk'event and trn_clk = '1' then
-
- Updates_tRAM <= CplD_State_is_AFetch
- and DSP_Tag_on_RAM_r1
--- and not trn_rx_throttle -- trn_rsrc_rdy_n_r1
- and not CplD_is_the_Last_r1
- ;
-
- end if;
- end process;
-
-
--- -----------------------------------------------------------------------------------
--- Synchronous output: Update_was_too_late
--- For 1DW CplD the update might be too late for the
--- next CplD with the same TAG
---
- RxFSM_Output_Update_was_too_late:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- Update_was_too_late <= '0';
- hazard_tag <= (OTHERS=>'1');
- tag_matches_hazard <= '0';
- hazard_update <= '0';
- hazard_update_r1 <= '0';
- hazard_update_r2 <= '0';
- hazard_update_r3 <= '0';
- elsif trn_clk'event and trn_clk = '1' then
-
- if Small_CplD_r1='1' and CplD_State_is_after_AFetch='1' then
- hazard_update <= '1';
- hazard_tag <= CplD_Tag;
- else
- hazard_update <= '0';
- hazard_tag <= hazard_tag;
- end if;
-
- if CplD_Tag=hazard_tag then
- tag_matches_hazard <= '1';
- else
- tag_matches_hazard <= '0';
- end if;
-
- hazard_update_r1 <= hazard_update;
- hazard_update_r2 <= hazard_update_r1;
- hazard_update_r3 <= hazard_update_r2;
-
--- Update_was_too_late <= hazard_update_r1 or hazard_update_r2 or hazard_update_r3;
- Update_was_too_late <= hazard_update or hazard_update_r1 or hazard_update_r2 or hazard_update_r3;
- end if;
- end process;
-
-
--- ---------------------------------------------
--- Delay Synchronous Delay: Updates_tRAM
---
- RxFSM_Delay_Updates_tRAM:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
- Updates_tRAM_r1 <= Updates_tRAM;
- end if;
- end process;
-
-
--- ---------------------------------------------
--- Synchronous Delay: tRAM_DoutA_r2
---
- Delay_tRAM_DoutA:
- process ( trn_clk )
- begin
- if trn_clk'event and trn_clk = '1' then
-
----- if CplD_State_is_AFetch='1' then -- [ avoid confilict in simulation, can be removed ]
--- if TLB_Hit='1'
--- and TLB_Valid='1' -- [ only for simulation. can be removed for imp.]
--- then
--- tRAM_DoutA_r1 <= TLB_Content;
--- else
--- tRAM_DoutA_r1 <= tRAM_doutA;
--- end if;
----- else
----- tRAM_DoutA_r1 <= tRAM_DoutA_r1;
----- end if;
-
- if Update_was_too_late='1' and tag_matches_hazard='1' then
- tRAM_DoutA_r1 <= hazard_content;
- else
- tRAM_DoutA_r1 <= tRAM_doutA;
- end if;
--- tRAM_DoutA_r1 <= tRAM_doutA;
- tRAM_DoutA_r2 <= tRAM_DoutA_r1;
-
- end if;
- end process;
-
-
--- ---------------------------------------------
--- Synchronous Output: hazard_content
---
- Syn_Reg_hazard_content:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- hazard_content <= (OTHERS =>'1');
- elsif trn_clk'event and trn_clk = '1' then
- if tRAM_wea(0)='1' then
- hazard_content <= tRAM_dina;
- else
- hazard_content <= hazard_content;
- end if;
- end if;
- end process;
-
-
--- ---------------------------------------------
--- Synchronous Calculation: tRAM_dina_aInc
---
- Syn_Calc_tRAM_dina_aInc:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- tRAM_dina_aInc <= (CBIT_AINC_IN_TAGRAM=>'1',
- OTHERS =>'0'
- );
- elsif trn_clk'event and trn_clk = '1' then
- tRAM_dina_aInc(C_TAGBAR_BIT_TOP downto C_TAGBAR_BIT_BOT)
- <= tRAM_DoutA_r1(C_TAGBAR_BIT_TOP downto C_TAGBAR_BIT_BOT);
- tRAM_dina_aInc(C_TAGBAR_BIT_BOT-1 downto 0) --C_EP_AWIDTH !!!!!
- <= tRAM_DoutA_r1(C_TAGBAR_BIT_BOT-1 downto 0) --C_EP_AWIDTH !!!!!
- + CplD_Leng_in_Bytes_r1(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0) ;
- end if;
- end process;
-
-
- tRAM_wea(0) <= Updates_tRAM_r1;
- tRAM_dina <= tRAM_dina_aInc;
--- tRAM_dina <= ('1' & tRAM_dina_aInc(C_TAGRAM_DWIDTH-1-1 downto 0))
--- when Addr_Inc='1'
--- else ('0' & tRAM_DoutA_r2(C_TAGRAM_DWIDTH-1-1 downto 0));
-
-
--- ---------------------------------------------
--- Synchronous Calculation: tRAM_DoutA_latch
---
- Syn_tRAM_DoutA_latch:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- tRAM_DoutA_latch <= (CBIT_AINC_IN_TAGRAM=>'1',OTHERS =>'0');
- elsif trn_clk'event and trn_clk = '1' then
- if CplD_State_is_AFetch_r1='0' then
- tRAM_DoutA_latch <= tRAM_DoutA_latch;
- elsif Update_was_too_late='1' then
- tRAM_DoutA_latch <= tRAM_DoutA_r1;
- else
- tRAM_DoutA_latch <= tRAM_DoutA;
- end if;
- end if;
- end process;
-
--- ---------------------------------------------
--- Synchronous Output: TLB (not used)
---
- Syn_Reg_TLB_Operation:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- TLB_Addr <= (OTHERS =>'1');
- TLB_Content <= (OTHERS =>'0');
- TLB_cnt <= (OTHERS =>'0');
- TLB_Valid <= '0';
- TLB_Hit <= '0';
- elsif trn_clk'event and trn_clk = '1' then
-
- if Updates_tRAM_r1='0' then
- TLB_Content <= TLB_Content;
- TLB_Addr <= TLB_Addr;
- if TLB_cnt=C_ALL_ZEROS(3 downto 0) then
- TLB_cnt <= TLB_cnt;
- TLB_Valid <= '0';
- else
- TLB_cnt <= TLB_cnt - '1';
- TLB_Valid <= '1';
- end if;
- else
- TLB_Addr <= tRAM_addra;
- TLB_cnt <= C_TLB_VALID_CNT;
- TLB_Valid <= '0';
- if Addr_Inc='1' then
- TLB_Content <= '1' & tRAM_dina_aInc(C_TAGRAM_DWIDTH-1-1 downto 0);
- else
- TLB_Content <= '0' & tRAM_DoutA_r2(C_TAGRAM_DWIDTH-1-1 downto 0);
- end if;
- end if;
-
- if TLB_Addr=tRAM_addra then
- TLB_Hit <= '1';
- else
- TLB_Hit <= '0';
- end if;
-
- end if;
- end process;
-
-
--- -------------------------------------------------
--- Synchronous outputs: DDR_Space_Hit
---
- RxFSM_Output_DDR_Space_Hit:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- DDR_Space_Hit <= '0';
- DDR_wr_sof_i <= '0';
- DDR_wr_eof_i <= '0';
- DDR_wr_v_i <= '0';
- DDR_wr_FA_i <= '0';
- DDR_wr_Shift_i <= '0';
- DDR_wr_Mask_i <= (OTHERS=>'0');
- DDR_wr_din_i <= (OTHERS=>'0');
-
- elsif trn_clk'event and trn_clk = '1' then
-
- case RxCplDTrn_State_r1 is
-
- when ST_CplD_RESET =>
- DDR_Space_Hit <= '0';
- DDR_wr_sof_i <= '0';
- DDR_wr_eof_i <= '0';
- DDR_wr_v_i <= '0';
- DDR_wr_FA_i <= '0';
- DDR_wr_Shift_i <= '0';
- DDR_wr_Mask_i <= (OTHERS=>'0');
- DDR_wr_din_i <= (OTHERS=>'0');
-
-
- when ST_CplD_AFetch =>
- if trn_reof_n_r4='0' then
- DDR_Space_Hit <= DSP_Tag_on_RAM_r1;
- DDR_wr_sof_i <= '0';
- DDR_wr_eof_i <= DSP_Tag_on_RAM_r4p;
- DDR_wr_v_i <= DSP_Tag_on_RAM_r4p; -- DSP_Tag_on_RAM; -- and not (trn_rx_throttle_r4 and trn_reof_n_r4);
- DDR_wr_FA_i <= '0';
- DDR_wr_Shift_i <= '0';
- DDR_wr_din_i <= trn_rd_Little_r4;
- DDR_wr_Mask_i <= '0' & (trn_rrem_n_r4(3) or trn_rrem_n_r4(0));
- elsif DSP_Tag_on_RAM_r1 ='1' then
- DDR_Space_Hit <= '1';
- DDR_wr_sof_i <= '0';
- DDR_wr_eof_i <= '0';
- DDR_wr_v_i <= '0'; -- not trn_rx_throttle_r1;
- DDR_wr_FA_i <= '0';
- DDR_wr_Shift_i <= '0';
- DDR_wr_Mask_i <= (OTHERS=>'0');
- DDR_wr_din_i <= (OTHERS=>'0');
- else
- DDR_Space_Hit <= '0';
- DDR_wr_sof_i <= '0';
- DDR_wr_eof_i <= '0';
- DDR_wr_v_i <= '0';
- DDR_wr_FA_i <= '0';
- DDR_wr_Shift_i <= '0';
- DDR_wr_Mask_i <= (OTHERS=>'0');
- DDR_wr_din_i <= (OTHERS=>'0');
- end if;
-
- when ST_CplD_AFetch_Special =>
- if DSP_Tag_on_RAM_r1 ='1' then
- DDR_Space_Hit <= '1';
--- DDR_wr_sof_i <= '0';
--- DDR_wr_eof_i <= '0';
--- DDR_wr_v_i <= '0'; -- not trn_rx_throttle_r1;
--- DDR_wr_FA_i <= '0';
--- DDR_wr_Shift_i <= '0';
--- DDR_wr_Mask_i <= (OTHERS=>'0');
--- DDR_wr_din_i <= (OTHERS=>'0');
- else
- DDR_Space_Hit <= '0';
--- DDR_wr_sof_i <= '0';
--- DDR_wr_eof_i <= '0';
--- DDR_wr_v_i <= '0';
--- DDR_wr_FA_i <= '0';
--- DDR_wr_Shift_i <= '0';
--- DDR_wr_Mask_i <= (OTHERS=>'0');
--- DDR_wr_din_i <= (OTHERS=>'0');
- end if;
- DDR_wr_sof_i <= '0';
- DDR_wr_eof_i <= not trn_reof_n_r4 and DDR_Space_Hit;
- DDR_wr_v_i <= (not (trn_rx_throttle_r4 and trn_reof_n_r4)) and DDR_Space_Hit;
- DDR_wr_FA_i <= '0';
- DDR_wr_Shift_i <= '0';
- DDR_wr_din_i <= trn_rd_Little_r4;
- DDR_wr_Mask_i <= '0' & (trn_rrem_n_r4(3) or trn_rrem_n_r4(0));
-
-
- when ST_CplD_AFetch_Special_Tail =>
- DDR_Space_Hit <= DDR_Space_Hit;
- DDR_wr_sof_i <= DDR_Space_Hit; -- '1';
- DDR_wr_eof_i <= '0';
- DDR_wr_v_i <= DDR_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
- DDR_wr_FA_i <= '0';
- DDR_wr_Mask_i <= (OTHERS=>'0');
- if Update_was_too_late='1' and tag_matches_hazard='1' then
- DDR_wr_Shift_i <= not hazard_content(2);
- DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
- else
- DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
- DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
- end if;
-
-
- when ST_CplD_AFetch_THROTTLE =>
- DDR_Space_Hit <= DDR_Space_Hit;
- DDR_wr_sof_i <= '0';
- DDR_wr_eof_i <= '0';
- DDR_wr_v_i <= '0';
- DDR_wr_FA_i <= '0';
- DDR_wr_Shift_i <= '0';
- DDR_wr_Mask_i <= (OTHERS=>'0');
- DDR_wr_din_i <= DDR_wr_din_i;
-
-
- when ST_CplD_1ST_DATA =>
- DDR_Space_Hit <= DDR_Space_Hit;
- DDR_wr_sof_i <= DDR_Space_Hit; -- '1';
- DDR_wr_eof_i <= '0';
- DDR_wr_v_i <= DDR_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
- DDR_wr_FA_i <= '0';
- DDR_wr_Mask_i <= (OTHERS=>'0');
- if Update_was_too_late='1' and tag_matches_hazard='1' then
- DDR_wr_Shift_i <= not hazard_content(2);
- DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
- elsif CplD_State_is_AFetch_r1 = '0' then
- DDR_wr_Shift_i <= not tRAM_DoutA_latch(2);
- DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
- else
- DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
- DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
- end if;
-
-
- when ST_CplD_ONLY_1DW =>
- DDR_Space_Hit <= DDR_Space_Hit;
- DDR_wr_sof_i <= DDR_Space_Hit; -- '1';
- DDR_wr_eof_i <= '0';
- DDR_wr_v_i <= DDR_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
- DDR_wr_FA_i <= '0';
- DDR_wr_Mask_i <= (OTHERS=>'0');
- if Update_was_too_late='1' and tag_matches_hazard='1' then
- DDR_wr_Shift_i <= not hazard_content(2);
- DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
- elsif CplD_State_is_AFetch_r1 = '0' then
- DDR_wr_Shift_i <= not tRAM_DoutA_latch(2);
- DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
- else
- DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
- DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
- end if;
-
-
- when OTHERS =>
- if trn_reof_n_r4='0' then
- DDR_Space_Hit <= '0';
- else
- DDR_Space_Hit <= DDR_Space_Hit;
- end if;
-
- DDR_wr_sof_i <= '0';
- DDR_wr_eof_i <= not trn_reof_n_r4 and DDR_Space_Hit;
- DDR_wr_v_i <= (DDR_wr_sof_i or not (trn_rx_throttle_r4 and trn_reof_n_r4)) and DDR_Space_Hit;
- DDR_wr_FA_i <= '0';
- DDR_wr_Shift_i <= '0';
- DDR_wr_din_i <= trn_rd_Little_r4;
- if DDR_wr_sof_i='1' then
- DDR_wr_Mask_i <= "10";
- else
- DDR_wr_Mask_i <= '0' & (trn_rrem_n_r4(3) or trn_rrem_n_r4(0));
- end if;
-
- end case;
-
- end if;
- end process;
-
-
-
- concat_rd <= trn_rd_r1(32-1 downto 0) & trn_rd_i(64-1 downto 32);
-
--- -------------------------------------------------
--- Synchronous outputs: eb_FIFO_Write
---
- RxFSM_Output_FIFO_Space_Hit:
- process ( trn_clk, Local_Reset_i)
- begin
- if Local_Reset_i = '1' then
- eb_FIFO_we_i <= '0';
- eb_FIFO_wsof_i <= '0';
- eb_FIFO_weof_i <= '0';
- eb_FIFO_sof_marker <= '0';
- eb_FIFO_din_i <= (OTHERS=>'0');
- EB_Write_State <= ST_EBWR_IDLE;
-
- elsif trn_clk'event and trn_clk = '1' then
-
- case EB_Write_State is
-
- when ST_EBWR_IDLE =>
- eb_FIFO_we_i <= '0';
- eb_FIFO_wsof_i <= '0';
- eb_FIFO_weof_i <= '0';
- eb_FIFO_sof_marker <= '0';
- eb_FIFO_din_i <= (OTHERS=>'0');
- if trn_rx_throttle='0'
- and CplD_Type=C_TLP_TYPE_IS_CPLD
- and trn_rd_i(0)='0' -- Odd-DW CplD is illegal
- then
- EB_Write_State <= ST_EBWR_TAG;
- else
- EB_Write_State <= ST_EBWR_IDLE;
- end if;
-
- when ST_EBWR_TAG =>
- eb_FIFO_we_i <= '0';
- eb_FIFO_wsof_i <= '0';
- eb_FIFO_weof_i <= '0';
- eb_FIFO_din_i <= (OTHERS=>'0');
- if trn_rsof_n_i='0' then
- eb_FIFO_sof_marker <= '0';
- EB_Write_State <= ST_EBWR_TAG;
- elsif trn_rx_throttle='0' and DSP_Tag_on_FIFO='1' then
- eb_FIFO_sof_marker <= '1';
- EB_Write_State <= ST_EBWR_DATA;
- else
- eb_FIFO_sof_marker <= '0';
- EB_Write_State <= ST_EBWR_IDLE;
- end if;
-
- when ST_EBWR_DATA =>
- eb_FIFO_we_i <= not trn_rx_throttle;
- eb_FIFO_wsof_i <= eb_FIFO_sof_marker and not trn_rx_throttle;
- eb_FIFO_sof_marker <= eb_FIFO_sof_marker and trn_rx_throttle;
- eb_FIFO_din_i <= Endian_Invert_64(concat_rd);
- if trn_rx_throttle='0' and trn_reof_n_i='0' then
- eb_FIFO_weof_i <= '1';
- EB_Write_State <= ST_EBWR_IDLE;
- else
- eb_FIFO_weof_i <= '0';
- EB_Write_State <= ST_EBWR_DATA;
- end if;
-
-
- when OTHERS =>
- eb_FIFO_we_i <= '0';
- eb_FIFO_wsof_i <= '0';
- eb_FIFO_weof_i <= '0';
- eb_FIFO_sof_marker <= '0';
- eb_FIFO_din_i <= (OTHERS=>'0');
- EB_Write_State <= ST_EBWR_IDLE;
-
- end case;
-
- end if;
- end process;
-
-
-end architecture Behavioral;