URL
https://opencores.org/ocsvn/pdp1/pdp1/trunk
Subversion Repositories pdp1
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- This comparison shows the changes necessary to convert path
/pdp1/trunk
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/rtl/vhdl/debounce.vhd
25,7 → 25,7
Port ( clk : in STD_LOGIC; |
clken : in STD_LOGIC; |
input : in STD_LOGIC; |
output : inout STD_LOGIC); |
output : out STD_LOGIC); |
end debounce; |
|
-- Concept: input values are asynchronously connected to SR latches. |
36,7 → 36,9
-- 00->no input value observed (reset), 10 or 01 -> steady value, 11->value changed |
signal inputv : std_logic_vector(0 to 1) := "00"; |
signal next_output : std_logic; |
signal current_output : std_logic; |
begin |
output <= current_output; |
-- our two asynch latches must agree for an update to occur |
-- the tricky part of the code was convincing the synthesizer we only need one LUT3 |
-- to implement this consensus function (inputv must agree to alter output). |
43,7 → 45,7
with inputv select |
next_output <= '0' when "10", |
'1' when "01", |
output when others; |
current_output when others; |
process (clk, input) |
begin |
-- input='0' for asynch set of input(0), synch reset |
60,7 → 62,7
end if; |
-- finally, on enabled clocks, update output |
if clken='1' and rising_edge(clk) then |
output <= next_output; |
current_output <= next_output; |
end if; |
end process; |
end Behavioral; |